add dummy assign (pulp-platform#157)

Bender.yml

@@ -59,6 +59,7 @@ sources:
   - src/sync.sv
   - src/sync_wedge.sv
   - src/unread.sv
+  - src/read.sv
   - src/cdc_reset_ctrlr_pkg.sv
   # Level 1
   - src/addr_decode_napot.sv

common_cells.core

@@ -46,6 +46,7 @@ filesets:
       - src/sync.sv
       - src/sync_wedge.sv
       - src/unread.sv
+      - src/read.sv
       - src/cdc_reset_ctrlr_pkg.sv
       # Level 1
       - src/cdc_2phase.sv

src/read.sv

@@ -0,0 +1,20 @@
+// Copyright 2022 EPFL
+// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+// Author: Davide Schiavone, EPFL, OpenHW Group
+// Date: 07.11.2022
+// Description: Dummy circuit to assign a signal, prevent signal being removed after non-ungroupped synthesis compilation
+
+(* no_ungroup *)
+module read #(
+    parameter int unsigned Width = 1,
+    parameter type T = logic [Width-1:0]
+) (
+    input  T d_i,
+    output T d_o
+);
+
+  assign d_o = d_i;
+
+endmodule

src_files.yml

@@ -42,6 +42,7 @@ common_cells_all:
     - src/sync.sv
     - src/sync_wedge.sv
     - src/unread.sv
+    - src/read.sv
     - src/cdc_reset_ctrlr_pkg.sv
     # Level 1
     - src/cdc_2phase.sv