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1. 4-bit_Flash_ADC 4-bit_Flash_ADC Public

   This repository presents the design of 4-bit_Flash_ADC implemented using eSim open source EDA tool.

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2. 4bit_binary_counter 4bit_binary_counter Public

   Verilog 1

3. dvsd_wt8216m dvsd_wt8216m Public

   Forked from Ikarthikmb/dvsd_wt8216m

   IP layout design of a 8-bit Wallace tree Multiplier

   Verilog

4. OpenLane OpenLane Public

   Forked from The-OpenROAD-Project/OpenLane

   OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

   Verilog

5. vsdserializer_v1 vsdserializer_v1 Public

   Forked from Devipriya1921/vsdserializer_v1

   Verilog

6. dvsd_4bit_binary_counter dvsd_4bit_binary_counter Public

   About This project produced a clean GDS - Final Layout with all details that are used to print photomasks used in the fabrication of a behavioral RTL of an 4bit Binary Counter, using SkyWater 130 n…

   Verilog