forked from grate-driver/linux
-
Notifications
You must be signed in to change notification settings - Fork 0
/
he.c
2863 lines (2293 loc) · 76 KB
/
he.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
he.c
ForeRunnerHE ATM Adapter driver for ATM on Linux
Copyright (C) 1999-2001 Naval Research Laboratory
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*
he.c
ForeRunnerHE ATM Adapter driver for ATM on Linux
Copyright (C) 1999-2001 Naval Research Laboratory
Permission to use, copy, modify and distribute this software and its
documentation is hereby granted, provided that both the copyright
notice and this permission notice appear in all copies of the software,
derivative works or modified versions, and any portions thereof, and
that both notices appear in supporting documentation.
NRL ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" CONDITION AND
DISCLAIMS ANY LIABILITY OF ANY KIND FOR ANY DAMAGES WHATSOEVER
RESULTING FROM THE USE OF THIS SOFTWARE.
This driver was written using the "Programmer's Reference Manual for
ForeRunnerHE(tm)", MANU0361-01 - Rev. A, 08/21/98.
AUTHORS:
chas williams <chas@cmf.nrl.navy.mil>
eric kinzie <ekinzie@cmf.nrl.navy.mil>
NOTES:
4096 supported 'connections'
group 0 is used for all traffic
interrupt queue 0 is used for all interrupts
aal0 support (based on work from ulrich.u.muller@nokia.com)
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/skbuff.h>
#include <linux/pci.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/bitmap.h>
#include <linux/slab.h>
#include <asm/io.h>
#include <asm/byteorder.h>
#include <linux/uaccess.h>
#include <linux/atmdev.h>
#include <linux/atm.h>
#include <linux/sonet.h>
#undef USE_SCATTERGATHER
#undef USE_CHECKSUM_HW /* still confused about this */
/* #undef HE_DEBUG */
#include "he.h"
#include "suni.h"
#include <linux/atm_he.h>
#define hprintk(fmt,args...) printk(KERN_ERR DEV_LABEL "%d: " fmt, he_dev->number , ##args)
#ifdef HE_DEBUG
#define HPRINTK(fmt,args...) printk(KERN_DEBUG DEV_LABEL "%d: " fmt, he_dev->number , ##args)
#else /* !HE_DEBUG */
#define HPRINTK(fmt,args...) do { } while (0)
#endif /* HE_DEBUG */
/* declarations */
static int he_open(struct atm_vcc *vcc);
static void he_close(struct atm_vcc *vcc);
static int he_send(struct atm_vcc *vcc, struct sk_buff *skb);
static int he_ioctl(struct atm_dev *dev, unsigned int cmd, void __user *arg);
static irqreturn_t he_irq_handler(int irq, void *dev_id);
static void he_tasklet(unsigned long data);
static int he_proc_read(struct atm_dev *dev,loff_t *pos,char *page);
static int he_start(struct atm_dev *dev);
static void he_stop(struct he_dev *dev);
static void he_phy_put(struct atm_dev *, unsigned char, unsigned long);
static unsigned char he_phy_get(struct atm_dev *, unsigned long);
static u8 read_prom_byte(struct he_dev *he_dev, int addr);
/* globals */
static struct he_dev *he_devs;
static bool disable64;
static short nvpibits = -1;
static short nvcibits = -1;
static short rx_skb_reserve = 16;
static bool irq_coalesce = true;
static bool sdh;
/* Read from EEPROM = 0000 0011b */
static unsigned int readtab[] = {
CS_HIGH | CLK_HIGH,
CS_LOW | CLK_LOW,
CLK_HIGH, /* 0 */
CLK_LOW,
CLK_HIGH, /* 0 */
CLK_LOW,
CLK_HIGH, /* 0 */
CLK_LOW,
CLK_HIGH, /* 0 */
CLK_LOW,
CLK_HIGH, /* 0 */
CLK_LOW,
CLK_HIGH, /* 0 */
CLK_LOW | SI_HIGH,
CLK_HIGH | SI_HIGH, /* 1 */
CLK_LOW | SI_HIGH,
CLK_HIGH | SI_HIGH /* 1 */
};
/* Clock to read from/write to the EEPROM */
static unsigned int clocktab[] = {
CLK_LOW,
CLK_HIGH,
CLK_LOW,
CLK_HIGH,
CLK_LOW,
CLK_HIGH,
CLK_LOW,
CLK_HIGH,
CLK_LOW,
CLK_HIGH,
CLK_LOW,
CLK_HIGH,
CLK_LOW,
CLK_HIGH,
CLK_LOW,
CLK_HIGH,
CLK_LOW
};
static const struct atmdev_ops he_ops =
{
.open = he_open,
.close = he_close,
.ioctl = he_ioctl,
.send = he_send,
.phy_put = he_phy_put,
.phy_get = he_phy_get,
.proc_read = he_proc_read,
.owner = THIS_MODULE
};
#define he_writel(dev, val, reg) do { writel(val, (dev)->membase + (reg)); wmb(); } while (0)
#define he_readl(dev, reg) readl((dev)->membase + (reg))
/* section 2.12 connection memory access */
static __inline__ void
he_writel_internal(struct he_dev *he_dev, unsigned val, unsigned addr,
unsigned flags)
{
he_writel(he_dev, val, CON_DAT);
(void) he_readl(he_dev, CON_DAT); /* flush posted writes */
he_writel(he_dev, flags | CON_CTL_WRITE | CON_CTL_ADDR(addr), CON_CTL);
while (he_readl(he_dev, CON_CTL) & CON_CTL_BUSY);
}
#define he_writel_rcm(dev, val, reg) \
he_writel_internal(dev, val, reg, CON_CTL_RCM)
#define he_writel_tcm(dev, val, reg) \
he_writel_internal(dev, val, reg, CON_CTL_TCM)
#define he_writel_mbox(dev, val, reg) \
he_writel_internal(dev, val, reg, CON_CTL_MBOX)
static unsigned
he_readl_internal(struct he_dev *he_dev, unsigned addr, unsigned flags)
{
he_writel(he_dev, flags | CON_CTL_READ | CON_CTL_ADDR(addr), CON_CTL);
while (he_readl(he_dev, CON_CTL) & CON_CTL_BUSY);
return he_readl(he_dev, CON_DAT);
}
#define he_readl_rcm(dev, reg) \
he_readl_internal(dev, reg, CON_CTL_RCM)
#define he_readl_tcm(dev, reg) \
he_readl_internal(dev, reg, CON_CTL_TCM)
#define he_readl_mbox(dev, reg) \
he_readl_internal(dev, reg, CON_CTL_MBOX)
/* figure 2.2 connection id */
#define he_mkcid(dev, vpi, vci) (((vpi << (dev)->vcibits) | vci) & 0x1fff)
/* 2.5.1 per connection transmit state registers */
#define he_writel_tsr0(dev, val, cid) \
he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 0)
#define he_readl_tsr0(dev, cid) \
he_readl_tcm(dev, CONFIG_TSRA | (cid << 3) | 0)
#define he_writel_tsr1(dev, val, cid) \
he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 1)
#define he_writel_tsr2(dev, val, cid) \
he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 2)
#define he_writel_tsr3(dev, val, cid) \
he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 3)
#define he_writel_tsr4(dev, val, cid) \
he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 4)
/* from page 2-20
*
* NOTE While the transmit connection is active, bits 23 through 0
* of this register must not be written by the host. Byte
* enables should be used during normal operation when writing
* the most significant byte.
*/
#define he_writel_tsr4_upper(dev, val, cid) \
he_writel_internal(dev, val, CONFIG_TSRA | (cid << 3) | 4, \
CON_CTL_TCM \
| CON_BYTE_DISABLE_2 \
| CON_BYTE_DISABLE_1 \
| CON_BYTE_DISABLE_0)
#define he_readl_tsr4(dev, cid) \
he_readl_tcm(dev, CONFIG_TSRA | (cid << 3) | 4)
#define he_writel_tsr5(dev, val, cid) \
he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 5)
#define he_writel_tsr6(dev, val, cid) \
he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 6)
#define he_writel_tsr7(dev, val, cid) \
he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 7)
#define he_writel_tsr8(dev, val, cid) \
he_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 0)
#define he_writel_tsr9(dev, val, cid) \
he_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 1)
#define he_writel_tsr10(dev, val, cid) \
he_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 2)
#define he_writel_tsr11(dev, val, cid) \
he_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 3)
#define he_writel_tsr12(dev, val, cid) \
he_writel_tcm(dev, val, CONFIG_TSRC | (cid << 1) | 0)
#define he_writel_tsr13(dev, val, cid) \
he_writel_tcm(dev, val, CONFIG_TSRC | (cid << 1) | 1)
#define he_writel_tsr14(dev, val, cid) \
he_writel_tcm(dev, val, CONFIG_TSRD | cid)
#define he_writel_tsr14_upper(dev, val, cid) \
he_writel_internal(dev, val, CONFIG_TSRD | cid, \
CON_CTL_TCM \
| CON_BYTE_DISABLE_2 \
| CON_BYTE_DISABLE_1 \
| CON_BYTE_DISABLE_0)
/* 2.7.1 per connection receive state registers */
#define he_writel_rsr0(dev, val, cid) \
he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 0)
#define he_readl_rsr0(dev, cid) \
he_readl_rcm(dev, 0x00000 | (cid << 3) | 0)
#define he_writel_rsr1(dev, val, cid) \
he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 1)
#define he_writel_rsr2(dev, val, cid) \
he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 2)
#define he_writel_rsr3(dev, val, cid) \
he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 3)
#define he_writel_rsr4(dev, val, cid) \
he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 4)
#define he_writel_rsr5(dev, val, cid) \
he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 5)
#define he_writel_rsr6(dev, val, cid) \
he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 6)
#define he_writel_rsr7(dev, val, cid) \
he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 7)
static __inline__ struct atm_vcc*
__find_vcc(struct he_dev *he_dev, unsigned cid)
{
struct hlist_head *head;
struct atm_vcc *vcc;
struct sock *s;
short vpi;
int vci;
vpi = cid >> he_dev->vcibits;
vci = cid & ((1 << he_dev->vcibits) - 1);
head = &vcc_hash[vci & (VCC_HTABLE_SIZE -1)];
sk_for_each(s, head) {
vcc = atm_sk(s);
if (vcc->dev == he_dev->atm_dev &&
vcc->vci == vci && vcc->vpi == vpi &&
vcc->qos.rxtp.traffic_class != ATM_NONE) {
return vcc;
}
}
return NULL;
}
static int he_init_one(struct pci_dev *pci_dev,
const struct pci_device_id *pci_ent)
{
struct atm_dev *atm_dev = NULL;
struct he_dev *he_dev = NULL;
int err = 0;
printk(KERN_INFO "ATM he driver\n");
if (pci_enable_device(pci_dev))
return -EIO;
if (dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(32)) != 0) {
printk(KERN_WARNING "he: no suitable dma available\n");
err = -EIO;
goto init_one_failure;
}
atm_dev = atm_dev_register(DEV_LABEL, &pci_dev->dev, &he_ops, -1, NULL);
if (!atm_dev) {
err = -ENODEV;
goto init_one_failure;
}
pci_set_drvdata(pci_dev, atm_dev);
he_dev = kzalloc(sizeof(struct he_dev),
GFP_KERNEL);
if (!he_dev) {
err = -ENOMEM;
goto init_one_failure;
}
he_dev->pci_dev = pci_dev;
he_dev->atm_dev = atm_dev;
he_dev->atm_dev->dev_data = he_dev;
atm_dev->dev_data = he_dev;
he_dev->number = atm_dev->number;
tasklet_init(&he_dev->tasklet, he_tasklet, (unsigned long) he_dev);
spin_lock_init(&he_dev->global_lock);
if (he_start(atm_dev)) {
he_stop(he_dev);
err = -ENODEV;
goto init_one_failure;
}
he_dev->next = NULL;
if (he_devs)
he_dev->next = he_devs;
he_devs = he_dev;
return 0;
init_one_failure:
if (atm_dev)
atm_dev_deregister(atm_dev);
kfree(he_dev);
pci_disable_device(pci_dev);
return err;
}
static void he_remove_one(struct pci_dev *pci_dev)
{
struct atm_dev *atm_dev;
struct he_dev *he_dev;
atm_dev = pci_get_drvdata(pci_dev);
he_dev = HE_DEV(atm_dev);
/* need to remove from he_devs */
he_stop(he_dev);
atm_dev_deregister(atm_dev);
kfree(he_dev);
pci_disable_device(pci_dev);
}
static unsigned
rate_to_atmf(unsigned rate) /* cps to atm forum format */
{
#define NONZERO (1 << 14)
unsigned exp = 0;
if (rate == 0)
return 0;
rate <<= 9;
while (rate > 0x3ff) {
++exp;
rate >>= 1;
}
return (NONZERO | (exp << 9) | (rate & 0x1ff));
}
static void he_init_rx_lbfp0(struct he_dev *he_dev)
{
unsigned i, lbm_offset, lbufd_index, lbuf_addr, lbuf_count;
unsigned lbufs_per_row = he_dev->cells_per_row / he_dev->cells_per_lbuf;
unsigned lbuf_bufsize = he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD;
unsigned row_offset = he_dev->r0_startrow * he_dev->bytes_per_row;
lbufd_index = 0;
lbm_offset = he_readl(he_dev, RCMLBM_BA);
he_writel(he_dev, lbufd_index, RLBF0_H);
for (i = 0, lbuf_count = 0; i < he_dev->r0_numbuffs; ++i) {
lbufd_index += 2;
lbuf_addr = (row_offset + (lbuf_count * lbuf_bufsize)) / 32;
he_writel_rcm(he_dev, lbuf_addr, lbm_offset);
he_writel_rcm(he_dev, lbufd_index, lbm_offset + 1);
if (++lbuf_count == lbufs_per_row) {
lbuf_count = 0;
row_offset += he_dev->bytes_per_row;
}
lbm_offset += 4;
}
he_writel(he_dev, lbufd_index - 2, RLBF0_T);
he_writel(he_dev, he_dev->r0_numbuffs, RLBF0_C);
}
static void he_init_rx_lbfp1(struct he_dev *he_dev)
{
unsigned i, lbm_offset, lbufd_index, lbuf_addr, lbuf_count;
unsigned lbufs_per_row = he_dev->cells_per_row / he_dev->cells_per_lbuf;
unsigned lbuf_bufsize = he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD;
unsigned row_offset = he_dev->r1_startrow * he_dev->bytes_per_row;
lbufd_index = 1;
lbm_offset = he_readl(he_dev, RCMLBM_BA) + (2 * lbufd_index);
he_writel(he_dev, lbufd_index, RLBF1_H);
for (i = 0, lbuf_count = 0; i < he_dev->r1_numbuffs; ++i) {
lbufd_index += 2;
lbuf_addr = (row_offset + (lbuf_count * lbuf_bufsize)) / 32;
he_writel_rcm(he_dev, lbuf_addr, lbm_offset);
he_writel_rcm(he_dev, lbufd_index, lbm_offset + 1);
if (++lbuf_count == lbufs_per_row) {
lbuf_count = 0;
row_offset += he_dev->bytes_per_row;
}
lbm_offset += 4;
}
he_writel(he_dev, lbufd_index - 2, RLBF1_T);
he_writel(he_dev, he_dev->r1_numbuffs, RLBF1_C);
}
static void he_init_tx_lbfp(struct he_dev *he_dev)
{
unsigned i, lbm_offset, lbufd_index, lbuf_addr, lbuf_count;
unsigned lbufs_per_row = he_dev->cells_per_row / he_dev->cells_per_lbuf;
unsigned lbuf_bufsize = he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD;
unsigned row_offset = he_dev->tx_startrow * he_dev->bytes_per_row;
lbufd_index = he_dev->r0_numbuffs + he_dev->r1_numbuffs;
lbm_offset = he_readl(he_dev, RCMLBM_BA) + (2 * lbufd_index);
he_writel(he_dev, lbufd_index, TLBF_H);
for (i = 0, lbuf_count = 0; i < he_dev->tx_numbuffs; ++i) {
lbufd_index += 1;
lbuf_addr = (row_offset + (lbuf_count * lbuf_bufsize)) / 32;
he_writel_rcm(he_dev, lbuf_addr, lbm_offset);
he_writel_rcm(he_dev, lbufd_index, lbm_offset + 1);
if (++lbuf_count == lbufs_per_row) {
lbuf_count = 0;
row_offset += he_dev->bytes_per_row;
}
lbm_offset += 2;
}
he_writel(he_dev, lbufd_index - 1, TLBF_T);
}
static int he_init_tpdrq(struct he_dev *he_dev)
{
he_dev->tpdrq_base = dma_alloc_coherent(&he_dev->pci_dev->dev,
CONFIG_TPDRQ_SIZE * sizeof(struct he_tpdrq),
&he_dev->tpdrq_phys,
GFP_KERNEL);
if (he_dev->tpdrq_base == NULL) {
hprintk("failed to alloc tpdrq\n");
return -ENOMEM;
}
he_dev->tpdrq_tail = he_dev->tpdrq_base;
he_dev->tpdrq_head = he_dev->tpdrq_base;
he_writel(he_dev, he_dev->tpdrq_phys, TPDRQ_B_H);
he_writel(he_dev, 0, TPDRQ_T);
he_writel(he_dev, CONFIG_TPDRQ_SIZE - 1, TPDRQ_S);
return 0;
}
static void he_init_cs_block(struct he_dev *he_dev)
{
unsigned clock, rate, delta;
int reg;
/* 5.1.7 cs block initialization */
for (reg = 0; reg < 0x20; ++reg)
he_writel_mbox(he_dev, 0x0, CS_STTIM0 + reg);
/* rate grid timer reload values */
clock = he_is622(he_dev) ? 66667000 : 50000000;
rate = he_dev->atm_dev->link_rate;
delta = rate / 16 / 2;
for (reg = 0; reg < 0x10; ++reg) {
/* 2.4 internal transmit function
*
* we initialize the first row in the rate grid.
* values are period (in clock cycles) of timer
*/
unsigned period = clock / rate;
he_writel_mbox(he_dev, period, CS_TGRLD0 + reg);
rate -= delta;
}
if (he_is622(he_dev)) {
/* table 5.2 (4 cells per lbuf) */
he_writel_mbox(he_dev, 0x000800fa, CS_ERTHR0);
he_writel_mbox(he_dev, 0x000c33cb, CS_ERTHR1);
he_writel_mbox(he_dev, 0x0010101b, CS_ERTHR2);
he_writel_mbox(he_dev, 0x00181dac, CS_ERTHR3);
he_writel_mbox(he_dev, 0x00280600, CS_ERTHR4);
/* table 5.3, 5.4, 5.5, 5.6, 5.7 */
he_writel_mbox(he_dev, 0x023de8b3, CS_ERCTL0);
he_writel_mbox(he_dev, 0x1801, CS_ERCTL1);
he_writel_mbox(he_dev, 0x68b3, CS_ERCTL2);
he_writel_mbox(he_dev, 0x1280, CS_ERSTAT0);
he_writel_mbox(he_dev, 0x68b3, CS_ERSTAT1);
he_writel_mbox(he_dev, 0x14585, CS_RTFWR);
he_writel_mbox(he_dev, 0x4680, CS_RTATR);
/* table 5.8 */
he_writel_mbox(he_dev, 0x00159ece, CS_TFBSET);
he_writel_mbox(he_dev, 0x68b3, CS_WCRMAX);
he_writel_mbox(he_dev, 0x5eb3, CS_WCRMIN);
he_writel_mbox(he_dev, 0xe8b3, CS_WCRINC);
he_writel_mbox(he_dev, 0xdeb3, CS_WCRDEC);
he_writel_mbox(he_dev, 0x68b3, CS_WCRCEIL);
/* table 5.9 */
he_writel_mbox(he_dev, 0x5, CS_OTPPER);
he_writel_mbox(he_dev, 0x14, CS_OTWPER);
} else {
/* table 5.1 (4 cells per lbuf) */
he_writel_mbox(he_dev, 0x000400ea, CS_ERTHR0);
he_writel_mbox(he_dev, 0x00063388, CS_ERTHR1);
he_writel_mbox(he_dev, 0x00081018, CS_ERTHR2);
he_writel_mbox(he_dev, 0x000c1dac, CS_ERTHR3);
he_writel_mbox(he_dev, 0x0014051a, CS_ERTHR4);
/* table 5.3, 5.4, 5.5, 5.6, 5.7 */
he_writel_mbox(he_dev, 0x0235e4b1, CS_ERCTL0);
he_writel_mbox(he_dev, 0x4701, CS_ERCTL1);
he_writel_mbox(he_dev, 0x64b1, CS_ERCTL2);
he_writel_mbox(he_dev, 0x1280, CS_ERSTAT0);
he_writel_mbox(he_dev, 0x64b1, CS_ERSTAT1);
he_writel_mbox(he_dev, 0xf424, CS_RTFWR);
he_writel_mbox(he_dev, 0x4680, CS_RTATR);
/* table 5.8 */
he_writel_mbox(he_dev, 0x000563b7, CS_TFBSET);
he_writel_mbox(he_dev, 0x64b1, CS_WCRMAX);
he_writel_mbox(he_dev, 0x5ab1, CS_WCRMIN);
he_writel_mbox(he_dev, 0xe4b1, CS_WCRINC);
he_writel_mbox(he_dev, 0xdab1, CS_WCRDEC);
he_writel_mbox(he_dev, 0x64b1, CS_WCRCEIL);
/* table 5.9 */
he_writel_mbox(he_dev, 0x6, CS_OTPPER);
he_writel_mbox(he_dev, 0x1e, CS_OTWPER);
}
he_writel_mbox(he_dev, 0x8, CS_OTTLIM);
for (reg = 0; reg < 0x8; ++reg)
he_writel_mbox(he_dev, 0x0, CS_HGRRT0 + reg);
}
static int he_init_cs_block_rcm(struct he_dev *he_dev)
{
unsigned (*rategrid)[16][16];
unsigned rate, delta;
int i, j, reg;
unsigned rate_atmf, exp, man;
unsigned long long rate_cps;
int mult, buf, buf_limit = 4;
rategrid = kmalloc( sizeof(unsigned) * 16 * 16, GFP_KERNEL);
if (!rategrid)
return -ENOMEM;
/* initialize rate grid group table */
for (reg = 0x0; reg < 0xff; ++reg)
he_writel_rcm(he_dev, 0x0, CONFIG_RCMABR + reg);
/* initialize rate controller groups */
for (reg = 0x100; reg < 0x1ff; ++reg)
he_writel_rcm(he_dev, 0x0, CONFIG_RCMABR + reg);
/* initialize tNrm lookup table */
/* the manual makes reference to a routine in a sample driver
for proper configuration; fortunately, we only need this
in order to support abr connection */
/* initialize rate to group table */
rate = he_dev->atm_dev->link_rate;
delta = rate / 32;
/*
* 2.4 transmit internal functions
*
* we construct a copy of the rate grid used by the scheduler
* in order to construct the rate to group table below
*/
for (j = 0; j < 16; j++) {
(*rategrid)[0][j] = rate;
rate -= delta;
}
for (i = 1; i < 16; i++)
for (j = 0; j < 16; j++)
if (i > 14)
(*rategrid)[i][j] = (*rategrid)[i - 1][j] / 4;
else
(*rategrid)[i][j] = (*rategrid)[i - 1][j] / 2;
/*
* 2.4 transmit internal function
*
* this table maps the upper 5 bits of exponent and mantissa
* of the atm forum representation of the rate into an index
* on rate grid
*/
rate_atmf = 0;
while (rate_atmf < 0x400) {
man = (rate_atmf & 0x1f) << 4;
exp = rate_atmf >> 5;
/*
instead of '/ 512', use '>> 9' to prevent a call
to divdu3 on x86 platforms
*/
rate_cps = (unsigned long long) (1UL << exp) * (man + 512) >> 9;
if (rate_cps < 10)
rate_cps = 10; /* 2.2.1 minimum payload rate is 10 cps */
for (i = 255; i > 0; i--)
if ((*rategrid)[i/16][i%16] >= rate_cps)
break; /* pick nearest rate instead? */
/*
* each table entry is 16 bits: (rate grid index (8 bits)
* and a buffer limit (8 bits)
* there are two table entries in each 32-bit register
*/
#ifdef notdef
buf = rate_cps * he_dev->tx_numbuffs /
(he_dev->atm_dev->link_rate * 2);
#else
/* this is pretty, but avoids _divdu3 and is mostly correct */
mult = he_dev->atm_dev->link_rate / ATM_OC3_PCR;
if (rate_cps > (272ULL * mult))
buf = 4;
else if (rate_cps > (204ULL * mult))
buf = 3;
else if (rate_cps > (136ULL * mult))
buf = 2;
else if (rate_cps > (68ULL * mult))
buf = 1;
else
buf = 0;
#endif
if (buf > buf_limit)
buf = buf_limit;
reg = (reg << 16) | ((i << 8) | buf);
#define RTGTBL_OFFSET 0x400
if (rate_atmf & 0x1)
he_writel_rcm(he_dev, reg,
CONFIG_RCMABR + RTGTBL_OFFSET + (rate_atmf >> 1));
++rate_atmf;
}
kfree(rategrid);
return 0;
}
static int he_init_group(struct he_dev *he_dev, int group)
{
struct he_buff *heb, *next;
dma_addr_t mapping;
int i;
he_writel(he_dev, 0x0, G0_RBPS_S + (group * 32));
he_writel(he_dev, 0x0, G0_RBPS_T + (group * 32));
he_writel(he_dev, 0x0, G0_RBPS_QI + (group * 32));
he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0),
G0_RBPS_BS + (group * 32));
/* bitmap table */
he_dev->rbpl_table = bitmap_zalloc(RBPL_TABLE_SIZE, GFP_KERNEL);
if (!he_dev->rbpl_table) {
hprintk("unable to allocate rbpl bitmap table\n");
return -ENOMEM;
}
/* rbpl_virt 64-bit pointers */
he_dev->rbpl_virt = kmalloc_array(RBPL_TABLE_SIZE,
sizeof(*he_dev->rbpl_virt),
GFP_KERNEL);
if (!he_dev->rbpl_virt) {
hprintk("unable to allocate rbpl virt table\n");
goto out_free_rbpl_table;
}
/* large buffer pool */
he_dev->rbpl_pool = dma_pool_create("rbpl", &he_dev->pci_dev->dev,
CONFIG_RBPL_BUFSIZE, 64, 0);
if (he_dev->rbpl_pool == NULL) {
hprintk("unable to create rbpl pool\n");
goto out_free_rbpl_virt;
}
he_dev->rbpl_base = dma_alloc_coherent(&he_dev->pci_dev->dev,
CONFIG_RBPL_SIZE * sizeof(struct he_rbp),
&he_dev->rbpl_phys, GFP_KERNEL);
if (he_dev->rbpl_base == NULL) {
hprintk("failed to alloc rbpl_base\n");
goto out_destroy_rbpl_pool;
}
INIT_LIST_HEAD(&he_dev->rbpl_outstanding);
for (i = 0; i < CONFIG_RBPL_SIZE; ++i) {
heb = dma_pool_alloc(he_dev->rbpl_pool, GFP_KERNEL, &mapping);
if (!heb)
goto out_free_rbpl;
heb->mapping = mapping;
list_add(&heb->entry, &he_dev->rbpl_outstanding);
set_bit(i, he_dev->rbpl_table);
he_dev->rbpl_virt[i] = heb;
he_dev->rbpl_hint = i + 1;
he_dev->rbpl_base[i].idx = i << RBP_IDX_OFFSET;
he_dev->rbpl_base[i].phys = mapping + offsetof(struct he_buff, data);
}
he_dev->rbpl_tail = &he_dev->rbpl_base[CONFIG_RBPL_SIZE - 1];
he_writel(he_dev, he_dev->rbpl_phys, G0_RBPL_S + (group * 32));
he_writel(he_dev, RBPL_MASK(he_dev->rbpl_tail),
G0_RBPL_T + (group * 32));
he_writel(he_dev, (CONFIG_RBPL_BUFSIZE - sizeof(struct he_buff))/4,
G0_RBPL_BS + (group * 32));
he_writel(he_dev,
RBP_THRESH(CONFIG_RBPL_THRESH) |
RBP_QSIZE(CONFIG_RBPL_SIZE - 1) |
RBP_INT_ENB,
G0_RBPL_QI + (group * 32));
/* rx buffer ready queue */
he_dev->rbrq_base = dma_alloc_coherent(&he_dev->pci_dev->dev,
CONFIG_RBRQ_SIZE * sizeof(struct he_rbrq),
&he_dev->rbrq_phys, GFP_KERNEL);
if (he_dev->rbrq_base == NULL) {
hprintk("failed to allocate rbrq\n");
goto out_free_rbpl;
}
he_dev->rbrq_head = he_dev->rbrq_base;
he_writel(he_dev, he_dev->rbrq_phys, G0_RBRQ_ST + (group * 16));
he_writel(he_dev, 0, G0_RBRQ_H + (group * 16));
he_writel(he_dev,
RBRQ_THRESH(CONFIG_RBRQ_THRESH) | RBRQ_SIZE(CONFIG_RBRQ_SIZE - 1),
G0_RBRQ_Q + (group * 16));
if (irq_coalesce) {
hprintk("coalescing interrupts\n");
he_writel(he_dev, RBRQ_TIME(768) | RBRQ_COUNT(7),
G0_RBRQ_I + (group * 16));
} else
he_writel(he_dev, RBRQ_TIME(0) | RBRQ_COUNT(1),
G0_RBRQ_I + (group * 16));
/* tx buffer ready queue */
he_dev->tbrq_base = dma_alloc_coherent(&he_dev->pci_dev->dev,
CONFIG_TBRQ_SIZE * sizeof(struct he_tbrq),
&he_dev->tbrq_phys, GFP_KERNEL);
if (he_dev->tbrq_base == NULL) {
hprintk("failed to allocate tbrq\n");
goto out_free_rbpq_base;
}
he_dev->tbrq_head = he_dev->tbrq_base;
he_writel(he_dev, he_dev->tbrq_phys, G0_TBRQ_B_T + (group * 16));
he_writel(he_dev, 0, G0_TBRQ_H + (group * 16));
he_writel(he_dev, CONFIG_TBRQ_SIZE - 1, G0_TBRQ_S + (group * 16));
he_writel(he_dev, CONFIG_TBRQ_THRESH, G0_TBRQ_THRESH + (group * 16));
return 0;
out_free_rbpq_base:
dma_free_coherent(&he_dev->pci_dev->dev, CONFIG_RBRQ_SIZE *
sizeof(struct he_rbrq), he_dev->rbrq_base,
he_dev->rbrq_phys);
out_free_rbpl:
list_for_each_entry_safe(heb, next, &he_dev->rbpl_outstanding, entry)
dma_pool_free(he_dev->rbpl_pool, heb, heb->mapping);
dma_free_coherent(&he_dev->pci_dev->dev, CONFIG_RBPL_SIZE *
sizeof(struct he_rbp), he_dev->rbpl_base,
he_dev->rbpl_phys);
out_destroy_rbpl_pool:
dma_pool_destroy(he_dev->rbpl_pool);
out_free_rbpl_virt:
kfree(he_dev->rbpl_virt);
out_free_rbpl_table:
bitmap_free(he_dev->rbpl_table);
return -ENOMEM;
}
static int he_init_irq(struct he_dev *he_dev)
{
int i;
/* 2.9.3.5 tail offset for each interrupt queue is located after the
end of the interrupt queue */
he_dev->irq_base = dma_alloc_coherent(&he_dev->pci_dev->dev,
(CONFIG_IRQ_SIZE + 1) * sizeof(struct he_irq),
&he_dev->irq_phys, GFP_KERNEL);
if (he_dev->irq_base == NULL) {
hprintk("failed to allocate irq\n");
return -ENOMEM;
}
he_dev->irq_tailoffset = (unsigned *)
&he_dev->irq_base[CONFIG_IRQ_SIZE];
*he_dev->irq_tailoffset = 0;
he_dev->irq_head = he_dev->irq_base;
he_dev->irq_tail = he_dev->irq_base;
for (i = 0; i < CONFIG_IRQ_SIZE; ++i)
he_dev->irq_base[i].isw = ITYPE_INVALID;
he_writel(he_dev, he_dev->irq_phys, IRQ0_BASE);
he_writel(he_dev,
IRQ_SIZE(CONFIG_IRQ_SIZE) | IRQ_THRESH(CONFIG_IRQ_THRESH),
IRQ0_HEAD);
he_writel(he_dev, IRQ_INT_A | IRQ_TYPE_LINE, IRQ0_CNTL);
he_writel(he_dev, 0x0, IRQ0_DATA);
he_writel(he_dev, 0x0, IRQ1_BASE);
he_writel(he_dev, 0x0, IRQ1_HEAD);
he_writel(he_dev, 0x0, IRQ1_CNTL);
he_writel(he_dev, 0x0, IRQ1_DATA);
he_writel(he_dev, 0x0, IRQ2_BASE);
he_writel(he_dev, 0x0, IRQ2_HEAD);
he_writel(he_dev, 0x0, IRQ2_CNTL);
he_writel(he_dev, 0x0, IRQ2_DATA);
he_writel(he_dev, 0x0, IRQ3_BASE);
he_writel(he_dev, 0x0, IRQ3_HEAD);
he_writel(he_dev, 0x0, IRQ3_CNTL);
he_writel(he_dev, 0x0, IRQ3_DATA);
/* 2.9.3.2 interrupt queue mapping registers */
he_writel(he_dev, 0x0, GRP_10_MAP);
he_writel(he_dev, 0x0, GRP_32_MAP);
he_writel(he_dev, 0x0, GRP_54_MAP);
he_writel(he_dev, 0x0, GRP_76_MAP);
if (request_irq(he_dev->pci_dev->irq,
he_irq_handler, IRQF_SHARED, DEV_LABEL, he_dev)) {
hprintk("irq %d already in use\n", he_dev->pci_dev->irq);
return -EINVAL;
}
he_dev->irq = he_dev->pci_dev->irq;
return 0;
}
static int he_start(struct atm_dev *dev)
{
struct he_dev *he_dev;
struct pci_dev *pci_dev;
unsigned long membase;
u16 command;
u32 gen_cntl_0, host_cntl, lb_swap;
u8 cache_size, timer;
unsigned err;
unsigned int status, reg;
int i, group;
he_dev = HE_DEV(dev);
pci_dev = he_dev->pci_dev;
membase = pci_resource_start(pci_dev, 0);
HPRINTK("membase = 0x%lx irq = %d.\n", membase, pci_dev->irq);
/*
* pci bus controller initialization
*/
/* 4.3 pci bus controller-specific initialization */
if (pci_read_config_dword(pci_dev, GEN_CNTL_0, &gen_cntl_0) != 0) {
hprintk("can't read GEN_CNTL_0\n");
return -EINVAL;
}
gen_cntl_0 |= (MRL_ENB | MRM_ENB | IGNORE_TIMEOUT);
if (pci_write_config_dword(pci_dev, GEN_CNTL_0, gen_cntl_0) != 0) {