forked from grate-driver/linux
-
Notifications
You must be signed in to change notification settings - Fork 0
/
diva.c
1283 lines (1158 loc) · 33.7 KB
/
diva.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/* $Id: diva.c,v 1.33.2.6 2004/02/11 13:21:33 keil Exp $
*
* low level stuff for Eicon.Diehl Diva Family ISDN cards
*
* Author Karsten Keil
* Copyright by Karsten Keil <keil@isdn4linux.de>
*
* This software may be used and distributed according to the terms
* of the GNU General Public License, incorporated herein by reference.
*
* For changes and modifications please read
* Documentation/isdn/HiSax.cert
*
* Thanks to Eicon Technology for documents and information
*
*/
#include <linux/init.h>
#include "hisax.h"
#include "isac.h"
#include "hscx.h"
#include "ipac.h"
#include "ipacx.h"
#include "isdnl1.h"
#include <linux/pci.h>
#include <linux/isapnp.h>
static const char *Diva_revision = "$Revision: 1.33.2.6 $";
#define byteout(addr,val) outb(val,addr)
#define bytein(addr) inb(addr)
#define DIVA_HSCX_DATA 0
#define DIVA_HSCX_ADR 4
#define DIVA_ISA_ISAC_DATA 2
#define DIVA_ISA_ISAC_ADR 6
#define DIVA_ISA_CTRL 7
#define DIVA_IPAC_ADR 0
#define DIVA_IPAC_DATA 1
#define DIVA_PCI_ISAC_DATA 8
#define DIVA_PCI_ISAC_ADR 0xc
#define DIVA_PCI_CTRL 0x10
/* SUB Types */
#define DIVA_ISA 1
#define DIVA_PCI 2
#define DIVA_IPAC_ISA 3
#define DIVA_IPAC_PCI 4
#define DIVA_IPACX_PCI 5
/* CTRL (Read) */
#define DIVA_IRQ_STAT 0x01
#define DIVA_EEPROM_SDA 0x02
/* CTRL (Write) */
#define DIVA_IRQ_REQ 0x01
#define DIVA_RESET 0x08
#define DIVA_EEPROM_CLK 0x40
#define DIVA_PCI_LED_A 0x10
#define DIVA_PCI_LED_B 0x20
#define DIVA_ISA_LED_A 0x20
#define DIVA_ISA_LED_B 0x40
#define DIVA_IRQ_CLR 0x80
/* Siemens PITA */
#define PITA_MISC_REG 0x1c
#ifdef __BIG_ENDIAN
#define PITA_PARA_SOFTRESET 0x00000001
#define PITA_SER_SOFTRESET 0x00000002
#define PITA_PARA_MPX_MODE 0x00000004
#define PITA_INT0_ENABLE 0x00000200
#else
#define PITA_PARA_SOFTRESET 0x01000000
#define PITA_SER_SOFTRESET 0x02000000
#define PITA_PARA_MPX_MODE 0x04000000
#define PITA_INT0_ENABLE 0x00020000
#endif
#define PITA_INT0_STATUS 0x02
static inline u_char
readreg(unsigned int ale, unsigned int adr, u_char off)
{
register u_char ret;
byteout(ale, off);
ret = bytein(adr);
return (ret);
}
static inline void
readfifo(unsigned int ale, unsigned int adr, u_char off, u_char * data, int size)
{
byteout(ale, off);
insb(adr, data, size);
}
static inline void
writereg(unsigned int ale, unsigned int adr, u_char off, u_char data)
{
byteout(ale, off);
byteout(adr, data);
}
static inline void
writefifo(unsigned int ale, unsigned int adr, u_char off, u_char *data, int size)
{
byteout(ale, off);
outsb(adr, data, size);
}
static inline u_char
memreadreg(unsigned long adr, u_char off)
{
return(*((unsigned char *)
(((unsigned int *)adr) + off)));
}
static inline void
memwritereg(unsigned long adr, u_char off, u_char data)
{
register u_char *p;
p = (unsigned char *)(((unsigned int *)adr) + off);
*p = data;
}
/* Interface functions */
static u_char
ReadISAC(struct IsdnCardState *cs, u_char offset)
{
return(readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset));
}
static void
WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value)
{
writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset, value);
}
static void
ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size)
{
readfifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0, data, size);
}
static void
WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size)
{
writefifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0, data, size);
}
static u_char
ReadISAC_IPAC(struct IsdnCardState *cs, u_char offset)
{
return (readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset+0x80));
}
static void
WriteISAC_IPAC(struct IsdnCardState *cs, u_char offset, u_char value)
{
writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset|0x80, value);
}
static void
ReadISACfifo_IPAC(struct IsdnCardState *cs, u_char * data, int size)
{
readfifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0x80, data, size);
}
static void
WriteISACfifo_IPAC(struct IsdnCardState *cs, u_char * data, int size)
{
writefifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0x80, data, size);
}
static u_char
ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset)
{
return(readreg(cs->hw.diva.hscx_adr,
cs->hw.diva.hscx, offset + (hscx ? 0x40 : 0)));
}
static void
WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value)
{
writereg(cs->hw.diva.hscx_adr,
cs->hw.diva.hscx, offset + (hscx ? 0x40 : 0), value);
}
static u_char
MemReadISAC_IPAC(struct IsdnCardState *cs, u_char offset)
{
return (memreadreg(cs->hw.diva.cfg_reg, offset+0x80));
}
static void
MemWriteISAC_IPAC(struct IsdnCardState *cs, u_char offset, u_char value)
{
memwritereg(cs->hw.diva.cfg_reg, offset|0x80, value);
}
static void
MemReadISACfifo_IPAC(struct IsdnCardState *cs, u_char * data, int size)
{
while(size--)
*data++ = memreadreg(cs->hw.diva.cfg_reg, 0x80);
}
static void
MemWriteISACfifo_IPAC(struct IsdnCardState *cs, u_char * data, int size)
{
while(size--)
memwritereg(cs->hw.diva.cfg_reg, 0x80, *data++);
}
static u_char
MemReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset)
{
return(memreadreg(cs->hw.diva.cfg_reg, offset + (hscx ? 0x40 : 0)));
}
static void
MemWriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value)
{
memwritereg(cs->hw.diva.cfg_reg, offset + (hscx ? 0x40 : 0), value);
}
/* IO-Functions for IPACX type cards */
static u_char
MemReadISAC_IPACX(struct IsdnCardState *cs, u_char offset)
{
return (memreadreg(cs->hw.diva.cfg_reg, offset));
}
static void
MemWriteISAC_IPACX(struct IsdnCardState *cs, u_char offset, u_char value)
{
memwritereg(cs->hw.diva.cfg_reg, offset, value);
}
static void
MemReadISACfifo_IPACX(struct IsdnCardState *cs, u_char * data, int size)
{
while(size--)
*data++ = memreadreg(cs->hw.diva.cfg_reg, 0);
}
static void
MemWriteISACfifo_IPACX(struct IsdnCardState *cs, u_char * data, int size)
{
while(size--)
memwritereg(cs->hw.diva.cfg_reg, 0, *data++);
}
static u_char
MemReadHSCX_IPACX(struct IsdnCardState *cs, int hscx, u_char offset)
{
return(memreadreg(cs->hw.diva.cfg_reg, offset +
(hscx ? IPACX_OFF_B2 : IPACX_OFF_B1)));
}
static void
MemWriteHSCX_IPACX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value)
{
memwritereg(cs->hw.diva.cfg_reg, offset +
(hscx ? IPACX_OFF_B2 : IPACX_OFF_B1), value);
}
/*
* fast interrupt HSCX stuff goes here
*/
#define READHSCX(cs, nr, reg) readreg(cs->hw.diva.hscx_adr, \
cs->hw.diva.hscx, reg + (nr ? 0x40 : 0))
#define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.diva.hscx_adr, \
cs->hw.diva.hscx, reg + (nr ? 0x40 : 0), data)
#define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.diva.hscx_adr, \
cs->hw.diva.hscx, (nr ? 0x40 : 0), ptr, cnt)
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.diva.hscx_adr, \
cs->hw.diva.hscx, (nr ? 0x40 : 0), ptr, cnt)
#include "hscx_irq.c"
static irqreturn_t
diva_interrupt(int intno, void *dev_id)
{
struct IsdnCardState *cs = dev_id;
u_char val, sval;
u_long flags;
int cnt=5;
spin_lock_irqsave(&cs->lock, flags);
while (((sval = bytein(cs->hw.diva.ctrl)) & DIVA_IRQ_REQ) && cnt) {
val = readreg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_ISTA + 0x40);
if (val)
hscx_int_main(cs, val);
val = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_ISTA);
if (val)
isac_interrupt(cs, val);
cnt--;
}
if (!cnt)
printk(KERN_WARNING "Diva: IRQ LOOP\n");
writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK, 0xFF);
writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK + 0x40, 0xFF);
writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_MASK, 0xFF);
writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_MASK, 0x0);
writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK, 0x0);
writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK + 0x40, 0x0);
spin_unlock_irqrestore(&cs->lock, flags);
return IRQ_HANDLED;
}
static irqreturn_t
diva_irq_ipac_isa(int intno, void *dev_id)
{
struct IsdnCardState *cs = dev_id;
u_char ista,val;
u_long flags;
int icnt=5;
spin_lock_irqsave(&cs->lock, flags);
ista = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_ISTA);
Start_IPACISA:
if (cs->debug & L1_DEB_IPAC)
debugl1(cs, "IPAC ISTA %02X", ista);
if (ista & 0x0f) {
val = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, HSCX_ISTA + 0x40);
if (ista & 0x01)
val |= 0x01;
if (ista & 0x04)
val |= 0x02;
if (ista & 0x08)
val |= 0x04;
if (val)
hscx_int_main(cs, val);
}
if (ista & 0x20) {
val = 0xfe & readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_ISTA + 0x80);
if (val) {
isac_interrupt(cs, val);
}
}
if (ista & 0x10) {
val = 0x01;
isac_interrupt(cs, val);
}
ista = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_ISTA);
if ((ista & 0x3f) && icnt) {
icnt--;
goto Start_IPACISA;
}
if (!icnt)
printk(KERN_WARNING "DIVA IPAC IRQ LOOP\n");
writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_MASK, 0xFF);
writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_MASK, 0xC0);
spin_unlock_irqrestore(&cs->lock, flags);
return IRQ_HANDLED;
}
static inline void
MemwaitforCEC(struct IsdnCardState *cs, int hscx)
{
int to = 50;
while ((MemReadHSCX(cs, hscx, HSCX_STAR) & 0x04) && to) {
udelay(1);
to--;
}
if (!to)
printk(KERN_WARNING "HiSax: waitforCEC timeout\n");
}
static inline void
MemwaitforXFW(struct IsdnCardState *cs, int hscx)
{
int to = 50;
while ((!(MemReadHSCX(cs, hscx, HSCX_STAR) & 0x44) == 0x40) && to) {
udelay(1);
to--;
}
if (!to)
printk(KERN_WARNING "HiSax: waitforXFW timeout\n");
}
static inline void
MemWriteHSCXCMDR(struct IsdnCardState *cs, int hscx, u_char data)
{
MemwaitforCEC(cs, hscx);
MemWriteHSCX(cs, hscx, HSCX_CMDR, data);
}
static void
Memhscx_empty_fifo(struct BCState *bcs, int count)
{
u_char *ptr;
struct IsdnCardState *cs = bcs->cs;
int cnt;
if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
debugl1(cs, "hscx_empty_fifo");
if (bcs->hw.hscx.rcvidx + count > HSCX_BUFMAX) {
if (cs->debug & L1_DEB_WARN)
debugl1(cs, "hscx_empty_fifo: incoming packet too large");
MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x80);
bcs->hw.hscx.rcvidx = 0;
return;
}
ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx;
cnt = count;
while (cnt--)
*ptr++ = memreadreg(cs->hw.diva.cfg_reg, bcs->hw.hscx.hscx ? 0x40 : 0);
MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x80);
ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx;
bcs->hw.hscx.rcvidx += count;
if (cs->debug & L1_DEB_HSCX_FIFO) {
char *t = bcs->blog;
t += sprintf(t, "hscx_empty_fifo %c cnt %d",
bcs->hw.hscx.hscx ? 'B' : 'A', count);
QuickHex(t, ptr, count);
debugl1(cs, bcs->blog);
}
}
static void
Memhscx_fill_fifo(struct BCState *bcs)
{
struct IsdnCardState *cs = bcs->cs;
int more, count, cnt;
int fifo_size = test_bit(HW_IPAC, &cs->HW_Flags)? 64: 32;
u_char *ptr,*p;
if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
debugl1(cs, "hscx_fill_fifo");
if (!bcs->tx_skb)
return;
if (bcs->tx_skb->len <= 0)
return;
more = (bcs->mode == L1_MODE_TRANS) ? 1 : 0;
if (bcs->tx_skb->len > fifo_size) {
more = !0;
count = fifo_size;
} else
count = bcs->tx_skb->len;
cnt = count;
MemwaitforXFW(cs, bcs->hw.hscx.hscx);
p = ptr = bcs->tx_skb->data;
skb_pull(bcs->tx_skb, count);
bcs->tx_cnt -= count;
bcs->hw.hscx.count += count;
while(cnt--)
memwritereg(cs->hw.diva.cfg_reg, bcs->hw.hscx.hscx ? 0x40 : 0,
*p++);
MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, more ? 0x8 : 0xa);
if (cs->debug & L1_DEB_HSCX_FIFO) {
char *t = bcs->blog;
t += sprintf(t, "hscx_fill_fifo %c cnt %d",
bcs->hw.hscx.hscx ? 'B' : 'A', count);
QuickHex(t, ptr, count);
debugl1(cs, bcs->blog);
}
}
static void
Memhscx_interrupt(struct IsdnCardState *cs, u_char val, u_char hscx)
{
u_char r;
struct BCState *bcs = cs->bcs + hscx;
struct sk_buff *skb;
int fifo_size = test_bit(HW_IPAC, &cs->HW_Flags)? 64: 32;
int count;
if (!test_bit(BC_FLG_INIT, &bcs->Flag))
return;
if (val & 0x80) { /* RME */
r = MemReadHSCX(cs, hscx, HSCX_RSTA);
if ((r & 0xf0) != 0xa0) {
if (!(r & 0x80))
if (cs->debug & L1_DEB_WARN)
debugl1(cs, "HSCX invalid frame");
if ((r & 0x40) && bcs->mode)
if (cs->debug & L1_DEB_WARN)
debugl1(cs, "HSCX RDO mode=%d",
bcs->mode);
if (!(r & 0x20))
if (cs->debug & L1_DEB_WARN)
debugl1(cs, "HSCX CRC error");
MemWriteHSCXCMDR(cs, hscx, 0x80);
} else {
count = MemReadHSCX(cs, hscx, HSCX_RBCL) & (
test_bit(HW_IPAC, &cs->HW_Flags)? 0x3f: 0x1f);
if (count == 0)
count = fifo_size;
Memhscx_empty_fifo(bcs, count);
if ((count = bcs->hw.hscx.rcvidx - 1) > 0) {
if (cs->debug & L1_DEB_HSCX_FIFO)
debugl1(cs, "HX Frame %d", count);
if (!(skb = dev_alloc_skb(count)))
printk(KERN_WARNING "HSCX: receive out of memory\n");
else {
memcpy(skb_put(skb, count), bcs->hw.hscx.rcvbuf, count);
skb_queue_tail(&bcs->rqueue, skb);
}
}
}
bcs->hw.hscx.rcvidx = 0;
schedule_event(bcs, B_RCVBUFREADY);
}
if (val & 0x40) { /* RPF */
Memhscx_empty_fifo(bcs, fifo_size);
if (bcs->mode == L1_MODE_TRANS) {
/* receive audio data */
if (!(skb = dev_alloc_skb(fifo_size)))
printk(KERN_WARNING "HiSax: receive out of memory\n");
else {
memcpy(skb_put(skb, fifo_size), bcs->hw.hscx.rcvbuf, fifo_size);
skb_queue_tail(&bcs->rqueue, skb);
}
bcs->hw.hscx.rcvidx = 0;
schedule_event(bcs, B_RCVBUFREADY);
}
}
if (val & 0x10) { /* XPR */
if (bcs->tx_skb) {
if (bcs->tx_skb->len) {
Memhscx_fill_fifo(bcs);
return;
} else {
if (test_bit(FLG_LLI_L1WAKEUP,&bcs->st->lli.flag) &&
(PACKET_NOACK != bcs->tx_skb->pkt_type)) {
u_long flags;
spin_lock_irqsave(&bcs->aclock, flags);
bcs->ackcnt += bcs->hw.hscx.count;
spin_unlock_irqrestore(&bcs->aclock, flags);
schedule_event(bcs, B_ACKPENDING);
}
dev_kfree_skb_irq(bcs->tx_skb);
bcs->hw.hscx.count = 0;
bcs->tx_skb = NULL;
}
}
if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
bcs->hw.hscx.count = 0;
test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
Memhscx_fill_fifo(bcs);
} else {
test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
schedule_event(bcs, B_XMTBUFREADY);
}
}
}
static inline void
Memhscx_int_main(struct IsdnCardState *cs, u_char val)
{
u_char exval;
struct BCState *bcs;
if (val & 0x01) { // EXB
bcs = cs->bcs + 1;
exval = MemReadHSCX(cs, 1, HSCX_EXIR);
if (exval & 0x40) {
if (bcs->mode == 1)
Memhscx_fill_fifo(bcs);
else {
/* Here we lost an TX interrupt, so
* restart transmitting the whole frame.
*/
if (bcs->tx_skb) {
skb_push(bcs->tx_skb, bcs->hw.hscx.count);
bcs->tx_cnt += bcs->hw.hscx.count;
bcs->hw.hscx.count = 0;
}
MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x01);
if (cs->debug & L1_DEB_WARN)
debugl1(cs, "HSCX B EXIR %x Lost TX", exval);
}
} else if (cs->debug & L1_DEB_HSCX)
debugl1(cs, "HSCX B EXIR %x", exval);
}
if (val & 0xf8) {
if (cs->debug & L1_DEB_HSCX)
debugl1(cs, "HSCX B interrupt %x", val);
Memhscx_interrupt(cs, val, 1);
}
if (val & 0x02) { // EXA
bcs = cs->bcs;
exval = MemReadHSCX(cs, 0, HSCX_EXIR);
if (exval & 0x40) {
if (bcs->mode == L1_MODE_TRANS)
Memhscx_fill_fifo(bcs);
else {
/* Here we lost an TX interrupt, so
* restart transmitting the whole frame.
*/
if (bcs->tx_skb) {
skb_push(bcs->tx_skb, bcs->hw.hscx.count);
bcs->tx_cnt += bcs->hw.hscx.count;
bcs->hw.hscx.count = 0;
}
MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x01);
if (cs->debug & L1_DEB_WARN)
debugl1(cs, "HSCX A EXIR %x Lost TX", exval);
}
} else if (cs->debug & L1_DEB_HSCX)
debugl1(cs, "HSCX A EXIR %x", exval);
}
if (val & 0x04) { // ICA
exval = MemReadHSCX(cs, 0, HSCX_ISTA);
if (cs->debug & L1_DEB_HSCX)
debugl1(cs, "HSCX A interrupt %x", exval);
Memhscx_interrupt(cs, exval, 0);
}
}
static irqreturn_t
diva_irq_ipac_pci(int intno, void *dev_id)
{
struct IsdnCardState *cs = dev_id;
u_char ista,val;
int icnt=5;
u_char *cfg;
u_long flags;
spin_lock_irqsave(&cs->lock, flags);
cfg = (u_char *) cs->hw.diva.pci_cfg;
val = *cfg;
if (!(val & PITA_INT0_STATUS)) {
spin_unlock_irqrestore(&cs->lock, flags);
return IRQ_NONE; /* other shared IRQ */
}
*cfg = PITA_INT0_STATUS; /* Reset pending INT0 */
ista = memreadreg(cs->hw.diva.cfg_reg, IPAC_ISTA);
Start_IPACPCI:
if (cs->debug & L1_DEB_IPAC)
debugl1(cs, "IPAC ISTA %02X", ista);
if (ista & 0x0f) {
val = memreadreg(cs->hw.diva.cfg_reg, HSCX_ISTA + 0x40);
if (ista & 0x01)
val |= 0x01;
if (ista & 0x04)
val |= 0x02;
if (ista & 0x08)
val |= 0x04;
if (val)
Memhscx_int_main(cs, val);
}
if (ista & 0x20) {
val = 0xfe & memreadreg(cs->hw.diva.cfg_reg, ISAC_ISTA + 0x80);
if (val) {
isac_interrupt(cs, val);
}
}
if (ista & 0x10) {
val = 0x01;
isac_interrupt(cs, val);
}
ista = memreadreg(cs->hw.diva.cfg_reg, IPAC_ISTA);
if ((ista & 0x3f) && icnt) {
icnt--;
goto Start_IPACPCI;
}
if (!icnt)
printk(KERN_WARNING "DIVA IPAC PCI IRQ LOOP\n");
memwritereg(cs->hw.diva.cfg_reg, IPAC_MASK, 0xFF);
memwritereg(cs->hw.diva.cfg_reg, IPAC_MASK, 0xC0);
spin_unlock_irqrestore(&cs->lock, flags);
return IRQ_HANDLED;
}
static irqreturn_t
diva_irq_ipacx_pci(int intno, void *dev_id)
{
struct IsdnCardState *cs = dev_id;
u_char val;
u_char *cfg;
u_long flags;
spin_lock_irqsave(&cs->lock, flags);
cfg = (u_char *) cs->hw.diva.pci_cfg;
val = *cfg;
if (!(val &PITA_INT0_STATUS)) {
spin_unlock_irqrestore(&cs->lock, flags);
return IRQ_NONE; // other shared IRQ
}
interrupt_ipacx(cs); // handler for chip
*cfg = PITA_INT0_STATUS; // Reset PLX interrupt
spin_unlock_irqrestore(&cs->lock, flags);
return IRQ_HANDLED;
}
static void
release_io_diva(struct IsdnCardState *cs)
{
int bytecnt;
if ((cs->subtyp == DIVA_IPAC_PCI) ||
(cs->subtyp == DIVA_IPACX_PCI) ) {
u_int *cfg = (unsigned int *)cs->hw.diva.pci_cfg;
*cfg = 0; /* disable INT0/1 */
*cfg = 2; /* reset pending INT0 */
if (cs->hw.diva.cfg_reg)
iounmap((void *)cs->hw.diva.cfg_reg);
if (cs->hw.diva.pci_cfg)
iounmap((void *)cs->hw.diva.pci_cfg);
return;
} else if (cs->subtyp != DIVA_IPAC_ISA) {
del_timer(&cs->hw.diva.tl);
if (cs->hw.diva.cfg_reg)
byteout(cs->hw.diva.ctrl, 0); /* LED off, Reset */
}
if ((cs->subtyp == DIVA_ISA) || (cs->subtyp == DIVA_IPAC_ISA))
bytecnt = 8;
else
bytecnt = 32;
if (cs->hw.diva.cfg_reg) {
release_region(cs->hw.diva.cfg_reg, bytecnt);
}
}
static void
iounmap_diva(struct IsdnCardState *cs)
{
if ((cs->subtyp == DIVA_IPAC_PCI) || (cs->subtyp == DIVA_IPACX_PCI)) {
if (cs->hw.diva.cfg_reg) {
iounmap((void *)cs->hw.diva.cfg_reg);
cs->hw.diva.cfg_reg = 0;
}
if (cs->hw.diva.pci_cfg) {
iounmap((void *)cs->hw.diva.pci_cfg);
cs->hw.diva.pci_cfg = 0;
}
}
return;
}
static void
reset_diva(struct IsdnCardState *cs)
{
if (cs->subtyp == DIVA_IPAC_ISA) {
writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_POTA2, 0x20);
mdelay(10);
writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_POTA2, 0x00);
mdelay(10);
writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_MASK, 0xc0);
} else if (cs->subtyp == DIVA_IPAC_PCI) {
unsigned int *ireg = (unsigned int *)(cs->hw.diva.pci_cfg +
PITA_MISC_REG);
*ireg = PITA_PARA_SOFTRESET | PITA_PARA_MPX_MODE;
mdelay(10);
*ireg = PITA_PARA_MPX_MODE;
mdelay(10);
memwritereg(cs->hw.diva.cfg_reg, IPAC_MASK, 0xc0);
} else if (cs->subtyp == DIVA_IPACX_PCI) {
unsigned int *ireg = (unsigned int *)(cs->hw.diva.pci_cfg +
PITA_MISC_REG);
*ireg = PITA_PARA_SOFTRESET | PITA_PARA_MPX_MODE;
mdelay(10);
*ireg = PITA_PARA_MPX_MODE | PITA_SER_SOFTRESET;
mdelay(10);
MemWriteISAC_IPACX(cs, IPACX_MASK, 0xff); // Interrupts off
} else { /* DIVA 2.0 */
cs->hw.diva.ctrl_reg = 0; /* Reset On */
byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg);
mdelay(10);
cs->hw.diva.ctrl_reg |= DIVA_RESET; /* Reset Off */
byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg);
mdelay(10);
if (cs->subtyp == DIVA_ISA)
cs->hw.diva.ctrl_reg |= DIVA_ISA_LED_A;
else {
/* Workaround PCI9060 */
byteout(cs->hw.diva.pci_cfg + 0x69, 9);
cs->hw.diva.ctrl_reg |= DIVA_PCI_LED_A;
}
byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg);
}
}
#define DIVA_ASSIGN 1
static void
diva_led_handler(struct IsdnCardState *cs)
{
int blink = 0;
if ((cs->subtyp == DIVA_IPAC_ISA) ||
(cs->subtyp == DIVA_IPAC_PCI) ||
(cs->subtyp == DIVA_IPACX_PCI) )
return;
del_timer(&cs->hw.diva.tl);
if (cs->hw.diva.status & DIVA_ASSIGN)
cs->hw.diva.ctrl_reg |= (DIVA_ISA == cs->subtyp) ?
DIVA_ISA_LED_A : DIVA_PCI_LED_A;
else {
cs->hw.diva.ctrl_reg ^= (DIVA_ISA == cs->subtyp) ?
DIVA_ISA_LED_A : DIVA_PCI_LED_A;
blink = 250;
}
if (cs->hw.diva.status & 0xf000)
cs->hw.diva.ctrl_reg |= (DIVA_ISA == cs->subtyp) ?
DIVA_ISA_LED_B : DIVA_PCI_LED_B;
else if (cs->hw.diva.status & 0x0f00) {
cs->hw.diva.ctrl_reg ^= (DIVA_ISA == cs->subtyp) ?
DIVA_ISA_LED_B : DIVA_PCI_LED_B;
blink = 500;
} else
cs->hw.diva.ctrl_reg &= ~((DIVA_ISA == cs->subtyp) ?
DIVA_ISA_LED_B : DIVA_PCI_LED_B);
byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg);
if (blink) {
init_timer(&cs->hw.diva.tl);
cs->hw.diva.tl.expires = jiffies + ((blink * HZ) / 1000);
add_timer(&cs->hw.diva.tl);
}
}
static int
Diva_card_msg(struct IsdnCardState *cs, int mt, void *arg)
{
u_int *ireg;
u_long flags;
switch (mt) {
case CARD_RESET:
spin_lock_irqsave(&cs->lock, flags);
reset_diva(cs);
spin_unlock_irqrestore(&cs->lock, flags);
return(0);
case CARD_RELEASE:
release_io_diva(cs);
return(0);
case CARD_INIT:
spin_lock_irqsave(&cs->lock, flags);
reset_diva(cs);
if (cs->subtyp == DIVA_IPACX_PCI) {
ireg = (unsigned int *)cs->hw.diva.pci_cfg;
*ireg = PITA_INT0_ENABLE;
init_ipacx(cs, 3); // init chip and enable interrupts
spin_unlock_irqrestore(&cs->lock, flags);
return (0);
}
if (cs->subtyp == DIVA_IPAC_PCI) {
ireg = (unsigned int *)cs->hw.diva.pci_cfg;
*ireg = PITA_INT0_ENABLE;
}
inithscxisac(cs, 3);
spin_unlock_irqrestore(&cs->lock, flags);
return(0);
case CARD_TEST:
return(0);
case (MDL_REMOVE | REQUEST):
cs->hw.diva.status = 0;
break;
case (MDL_ASSIGN | REQUEST):
cs->hw.diva.status |= DIVA_ASSIGN;
break;
case MDL_INFO_SETUP:
if ((long)arg)
cs->hw.diva.status |= 0x0200;
else
cs->hw.diva.status |= 0x0100;
break;
case MDL_INFO_CONN:
if ((long)arg)
cs->hw.diva.status |= 0x2000;
else
cs->hw.diva.status |= 0x1000;
break;
case MDL_INFO_REL:
if ((long)arg) {
cs->hw.diva.status &= ~0x2000;
cs->hw.diva.status &= ~0x0200;
} else {
cs->hw.diva.status &= ~0x1000;
cs->hw.diva.status &= ~0x0100;
}
break;
}
if ((cs->subtyp != DIVA_IPAC_ISA) &&
(cs->subtyp != DIVA_IPAC_PCI) &&
(cs->subtyp != DIVA_IPACX_PCI)) {
spin_lock_irqsave(&cs->lock, flags);
diva_led_handler(cs);
spin_unlock_irqrestore(&cs->lock, flags);
}
return(0);
}
static int __devinit setup_diva_common(struct IsdnCardState *cs)
{
int bytecnt;
u_char val;
if ((cs->subtyp == DIVA_ISA) || (cs->subtyp == DIVA_IPAC_ISA))
bytecnt = 8;
else
bytecnt = 32;
printk(KERN_INFO
"Diva: %s card configured at %#lx IRQ %d\n",
(cs->subtyp == DIVA_PCI) ? "PCI" :
(cs->subtyp == DIVA_ISA) ? "ISA" :
(cs->subtyp == DIVA_IPAC_ISA) ? "IPAC ISA" :
(cs->subtyp == DIVA_IPAC_PCI) ? "IPAC PCI" : "IPACX PCI",
cs->hw.diva.cfg_reg, cs->irq);
if ((cs->subtyp == DIVA_IPAC_PCI) ||
(cs->subtyp == DIVA_IPACX_PCI) ||
(cs->subtyp == DIVA_PCI) )
printk(KERN_INFO "Diva: %s space at %#lx\n",
(cs->subtyp == DIVA_PCI) ? "PCI" :
(cs->subtyp == DIVA_IPAC_PCI) ? "IPAC PCI" : "IPACX PCI",
cs->hw.diva.pci_cfg);
if ((cs->subtyp != DIVA_IPAC_PCI) &&
(cs->subtyp != DIVA_IPACX_PCI) ) {
if (!request_region(cs->hw.diva.cfg_reg, bytecnt, "diva isdn")) {
printk(KERN_WARNING
"HiSax: %s config port %lx-%lx already in use\n",
"diva",
cs->hw.diva.cfg_reg,
cs->hw.diva.cfg_reg + bytecnt);
iounmap_diva(cs);
return (0);
}
}
cs->BC_Read_Reg = &ReadHSCX;
cs->BC_Write_Reg = &WriteHSCX;
cs->BC_Send_Data = &hscx_fill_fifo;
cs->cardmsg = &Diva_card_msg;
setup_isac(cs);
if (cs->subtyp == DIVA_IPAC_ISA) {
cs->readisac = &ReadISAC_IPAC;
cs->writeisac = &WriteISAC_IPAC;
cs->readisacfifo = &ReadISACfifo_IPAC;
cs->writeisacfifo = &WriteISACfifo_IPAC;
cs->irq_func = &diva_irq_ipac_isa;
val = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_ID);
printk(KERN_INFO "Diva: IPAC version %x\n", val);
} else if (cs->subtyp == DIVA_IPAC_PCI) {
cs->readisac = &MemReadISAC_IPAC;
cs->writeisac = &MemWriteISAC_IPAC;
cs->readisacfifo = &MemReadISACfifo_IPAC;
cs->writeisacfifo = &MemWriteISACfifo_IPAC;
cs->BC_Read_Reg = &MemReadHSCX;
cs->BC_Write_Reg = &MemWriteHSCX;
cs->BC_Send_Data = &Memhscx_fill_fifo;
cs->irq_func = &diva_irq_ipac_pci;
val = memreadreg(cs->hw.diva.cfg_reg, IPAC_ID);
printk(KERN_INFO "Diva: IPAC version %x\n", val);
} else if (cs->subtyp == DIVA_IPACX_PCI) {
cs->readisac = &MemReadISAC_IPACX;
cs->writeisac = &MemWriteISAC_IPACX;
cs->readisacfifo = &MemReadISACfifo_IPACX;
cs->writeisacfifo = &MemWriteISACfifo_IPACX;
cs->BC_Read_Reg = &MemReadHSCX_IPACX;
cs->BC_Write_Reg = &MemWriteHSCX_IPACX;
cs->BC_Send_Data = NULL; // function located in ipacx module
cs->irq_func = &diva_irq_ipacx_pci;
printk(KERN_INFO "Diva: IPACX Design Id: %x\n",
MemReadISAC_IPACX(cs, IPACX_ID) &0x3F);
} else { /* DIVA 2.0 */
cs->hw.diva.tl.function = (void *) diva_led_handler;
cs->hw.diva.tl.data = (long) cs;
init_timer(&cs->hw.diva.tl);
cs->readisac = &ReadISAC;
cs->writeisac = &WriteISAC;
cs->readisacfifo = &ReadISACfifo;
cs->writeisacfifo = &WriteISACfifo;
cs->irq_func = &diva_interrupt;
ISACVersion(cs, "Diva:");
if (HscxVersion(cs, "Diva:")) {
printk(KERN_WARNING
"Diva: wrong HSCX versions check IO address\n");
release_io_diva(cs);
return (0);
}
}
return (1);
}
#ifdef CONFIG_ISA
static int __devinit setup_diva_isa(struct IsdnCard *card)