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Merge branch 'perf/urgent' into perf/core, to pick up fixes
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Signed-off-by: Ingo Molnar <mingo@kernel.org>
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Ingo Molnar committed Aug 10, 2017
2 parents c3a3800 + 9b231d9 commit 1ccb2f4
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Showing 720 changed files with 12,548 additions and 17,572 deletions.
8 changes: 8 additions & 0 deletions Documentation/admin-guide/pm/cpufreq.rst
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Expand Up @@ -237,6 +237,14 @@ are the following:
This attribute is not present if the scaling driver in use does not
support it.

``cpuinfo_cur_freq``
Current frequency of the CPUs belonging to this policy as obtained from
the hardware (in KHz).

This is expected to be the frequency the hardware actually runs at.
If that frequency cannot be determined, this attribute should not
be present.

``cpuinfo_max_freq``
Maximum possible operating frequency the CPUs belonging to this policy
can run at (in kHz).
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1 change: 1 addition & 0 deletions Documentation/device-mapper/dm-raid.txt
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Expand Up @@ -343,3 +343,4 @@ Version History
1.11.0 Fix table line argument order
(wrong raid10_copies/raid10_format sequence)
1.11.1 Add raid4/5/6 journal write-back support via journal_mode option
1.12.1 fix for MD deadlock between mddev_suspend() and md_write_start() available
14 changes: 11 additions & 3 deletions Documentation/devicetree/bindings/ata/sata_rcar.txt
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@@ -1,22 +1,30 @@
* Renesas R-Car SATA

Required properties:
- compatible : should contain one of the following:
- compatible : should contain one or more of the following:
- "renesas,sata-r8a7779" for R-Car H1
("renesas,rcar-sata" is deprecated)
- "renesas,sata-r8a7790-es1" for R-Car H2 ES1
- "renesas,sata-r8a7790" for R-Car H2 other than ES1
- "renesas,sata-r8a7791" for R-Car M2-W
- "renesas,sata-r8a7793" for R-Car M2-N
- "renesas,sata-r8a7795" for R-Car H3
- "renesas,rcar-gen2-sata" for a generic R-Car Gen2 compatible device
- "renesas,rcar-gen3-sata" for a generic R-Car Gen3 compatible device
- "renesas,rcar-sata" is deprecated

When compatible with the generic version nodes
must list the SoC-specific version corresponding
to the platform first followed by the generic
version.

- reg : address and length of the SATA registers;
- interrupts : must consist of one interrupt specifier.
- clocks : must contain a reference to the functional clock.

Example:

sata0: sata@ee300000 {
compatible = "renesas,sata-r8a7791";
compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata";
reg = <0 0xee300000 0 0x2000>;
interrupt-parent = <&gic>;
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
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Expand Up @@ -8,7 +8,6 @@ Required properties:

Optional properties:
- clocks: Reference to the crypto engine clock.
- dma-mask: The address mask limitation. Defaults to 64.

Example:

Expand All @@ -24,6 +23,5 @@ Example:
interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3",
"eip";
clocks = <&cpm_syscon0 1 26>;
dma-mask = <0xff 0xffffffff>;
status = "disabled";
};
5 changes: 5 additions & 0 deletions Documentation/devicetree/bindings/gpio/gpio-exar.txt
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@@ -0,0 +1,5 @@
Exportable MPIO interface of Exar UART chips

Required properties of the device:
- exar,first-pin: first exportable pins (0..15)
- ngpios: number of exportable pins (1..16)
2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
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Expand Up @@ -40,7 +40,7 @@ Optional properties:
Example for a Mali-T760:

gpu@ffa30000 {
compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard";
compatible = "rockchip,rk3288-mali", "arm,mali-t760";
reg = <0xffa30000 0x10000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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1 change: 0 additions & 1 deletion Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
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Expand Up @@ -78,7 +78,6 @@ Example:
};

dwmmc0@12200000 {
num-slots = <1>;
cap-mmc-highspeed;
cap-sd-highspeed;
broken-cd;
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1 change: 0 additions & 1 deletion Documentation/devicetree/bindings/mmc/img-dw-mshc.txt
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Expand Up @@ -24,6 +24,5 @@ Example:

fifo-depth = <0x20>;
bus-width = <4>;
num-slots = <1>;
disable-wp;
};
2 changes: 0 additions & 2 deletions Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
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Expand Up @@ -36,7 +36,6 @@ Example:

/* Board portion */
dwmmc0@fcd03000 {
num-slots = <1>;
vmmc-supply = <&ldo12>;
fifo-depth = <0x100>;
pinctrl-names = "default";
Expand All @@ -52,7 +51,6 @@ Example:

dwmmc_1: dwmmc1@f723e000 {
compatible = "hisilicon,hi6220-dw-mshc";
num-slots = <0x1>;
bus-width = <0x4>;
disable-wp;
cap-sd-highspeed;
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16 changes: 7 additions & 9 deletions Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
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Expand Up @@ -12,12 +12,12 @@ Required Properties:
* #address-cells: should be 1.
* #size-cells: should be 0.

# Slots: The slot specific information are contained within child-nodes with
each child-node representing a supported slot. There should be atleast one
child node representing a card slot. The name of the child node representing
the slot is recommended to be slot@n where n is the unique number of the slot
connected to the controller. The following are optional properties which
can be included in the slot child node.
# Slots (DEPRECATED): The slot specific information are contained within
child-nodes with each child-node representing a supported slot. There should
be atleast one child node representing a card slot. The name of the child node
representing the slot is recommended to be slot@n where n is the unique number
of the slot connected to the controller. The following are optional properties
which can be included in the slot child node.

* reg: specifies the physical slot number. The valid values of this
property is 0 to (num-slots -1), where num-slots is the value
Expand Down Expand Up @@ -63,7 +63,7 @@ Optional properties:
clock(cclk_out). If it's not specified, max is 200MHZ and min is 400KHz by default.
(Use the "max-frequency" instead of "clock-freq-min-max".)

* num-slots: specifies the number of slots supported by the controller.
* num-slots (DEPRECATED): specifies the number of slots supported by the controller.
The number of physical slots actually used could be equal or less than the
value specified by num-slots. If this property is not specified, the value
of num-slot property is assumed to be 1.
Expand Down Expand Up @@ -124,7 +124,6 @@ board specific portions as listed below.
dwmmc0@12200000 {
clock-frequency = <400000000>;
clock-freq-min-max = <400000 200000000>;
num-slots = <1>;
broken-cd;
fifo-depth = <0x80>;
card-detect-delay = <200>;
Expand All @@ -139,7 +138,6 @@ board specific portions as listed below.
dwmmc0@12200000 {
clock-frequency = <400000000>;
clock-freq-min-max = <400000 200000000>;
num-slots = <1>;
broken-cd;
fifo-depth = <0x80>;
card-detect-delay = <200>;
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1 change: 0 additions & 1 deletion Documentation/devicetree/bindings/mmc/zx-dw-mshc.txt
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Expand Up @@ -25,7 +25,6 @@ Example:
clock-frequency = <50000000>;
clocks = <&topcrm SD0_AHB>, <&topcrm SD0_WCLK>;
clock-names = "biu", "ciu";
num-slots = <1>;
max-frequency = <50000000>;
cap-sdio-irq;
cap-sd-highspeed;
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2 changes: 1 addition & 1 deletion Documentation/gpio/gpio-legacy.txt
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Expand Up @@ -459,7 +459,7 @@ pin controller?

This is done by registering "ranges" of pins, which are essentially
cross-reference tables. These are described in
Documentation/pinctrl.txt
Documentation/driver-api/pinctl.rst

While the pin allocation is totally managed by the pinctrl subsystem,
gpio (under gpiolib) is still maintained by gpio drivers. It may happen
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