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Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux
Pull DRM updates from Dave Airlie: "This is the one and only next pull for 3.8, we had a regression we found last week, so I was waiting for that to resolve itself, and I ended up with some Intel fixes on top as well. Highlights: - new driver: nvidia tegra 20/30/hdmi support - radeon: add support for previously unused DMA engines, more HDMI regs, eviction speeds ups and fixes - i915: HSW support enable, agp removal on GEN6, seqno wrapping - exynos: IPP subsystem support (image post proc), HDMI - nouveau: display class reworking, nv20->40 z compression - ttm: start of locking fixes, rcu usage for lookups, - core: documentation updates, docbook integration, monotonic clock usage, move from connector to object properties" * 'drm-next' of git://people.freedesktop.org/~airlied/linux: (590 commits) drm/exynos: add gsc ipp driver drm/exynos: add rotator ipp driver drm/exynos: add fimc ipp driver drm/exynos: add iommu support for ipp drm/exynos: add ipp subsystem drm/exynos: support device tree for fimd radeon: fix regression with eviction since evict caching changes drm/radeon: add more pedantic checks in the CP DMA checker drm/radeon: bump version for CS ioctl support for async DMA drm/radeon: enable the async DMA rings in the CS ioctl drm/radeon: add VM CS parser support for async DMA on cayman/TN/SI drm/radeon/kms: add evergreen/cayman CS parser for async DMA (v2) drm/radeon/kms: add 6xx/7xx CS parser for async DMA (v2) drm/radeon: fix htile buffer size computation for command stream checker drm/radeon: fix fence locking in the pageflip callback drm/radeon: make indirect register access concurrency-safe drm/radeon: add W|RREG32_IDX for MM_INDEX|DATA based mmio accesss drm/exynos: support extended screen coordinate of fimd drm/exynos: fix x, y coordinates for right bottom pixel drm/exynos: fix fb offset calculation for plane ...
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Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
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NVIDIA Tegra host1x | ||
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Required properties: | ||
- compatible: "nvidia,tegra<chip>-host1x" | ||
- reg: Physical base address and length of the controller's registers. | ||
- interrupts: The interrupt outputs from the controller. | ||
- #address-cells: The number of cells used to represent physical base addresses | ||
in the host1x address space. Should be 1. | ||
- #size-cells: The number of cells used to represent the size of an address | ||
range in the host1x address space. Should be 1. | ||
- ranges: The mapping of the host1x address space to the CPU address space. | ||
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The host1x top-level node defines a number of children, each representing one | ||
of the following host1x client modules: | ||
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- mpe: video encoder | ||
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Required properties: | ||
- compatible: "nvidia,tegra<chip>-mpe" | ||
- reg: Physical base address and length of the controller's registers. | ||
- interrupts: The interrupt outputs from the controller. | ||
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- vi: video input | ||
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Required properties: | ||
- compatible: "nvidia,tegra<chip>-vi" | ||
- reg: Physical base address and length of the controller's registers. | ||
- interrupts: The interrupt outputs from the controller. | ||
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- epp: encoder pre-processor | ||
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Required properties: | ||
- compatible: "nvidia,tegra<chip>-epp" | ||
- reg: Physical base address and length of the controller's registers. | ||
- interrupts: The interrupt outputs from the controller. | ||
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- isp: image signal processor | ||
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Required properties: | ||
- compatible: "nvidia,tegra<chip>-isp" | ||
- reg: Physical base address and length of the controller's registers. | ||
- interrupts: The interrupt outputs from the controller. | ||
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- gr2d: 2D graphics engine | ||
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Required properties: | ||
- compatible: "nvidia,tegra<chip>-gr2d" | ||
- reg: Physical base address and length of the controller's registers. | ||
- interrupts: The interrupt outputs from the controller. | ||
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- gr3d: 3D graphics engine | ||
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Required properties: | ||
- compatible: "nvidia,tegra<chip>-gr3d" | ||
- reg: Physical base address and length of the controller's registers. | ||
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- dc: display controller | ||
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Required properties: | ||
- compatible: "nvidia,tegra<chip>-dc" | ||
- reg: Physical base address and length of the controller's registers. | ||
- interrupts: The interrupt outputs from the controller. | ||
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Each display controller node has a child node, named "rgb", that represents | ||
the RGB output associated with the controller. It can take the following | ||
optional properties: | ||
- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing | ||
- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection | ||
- nvidia,edid: supplies a binary EDID blob | ||
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- hdmi: High Definition Multimedia Interface | ||
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Required properties: | ||
- compatible: "nvidia,tegra<chip>-hdmi" | ||
- reg: Physical base address and length of the controller's registers. | ||
- interrupts: The interrupt outputs from the controller. | ||
- vdd-supply: regulator for supply voltage | ||
- pll-supply: regulator for PLL | ||
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Optional properties: | ||
- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing | ||
- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection | ||
- nvidia,edid: supplies a binary EDID blob | ||
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- tvo: TV encoder output | ||
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Required properties: | ||
- compatible: "nvidia,tegra<chip>-tvo" | ||
- reg: Physical base address and length of the controller's registers. | ||
- interrupts: The interrupt outputs from the controller. | ||
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- dsi: display serial interface | ||
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Required properties: | ||
- compatible: "nvidia,tegra<chip>-dsi" | ||
- reg: Physical base address and length of the controller's registers. | ||
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Example: | ||
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/ { | ||
... | ||
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host1x { | ||
compatible = "nvidia,tegra20-host1x", "simple-bus"; | ||
reg = <0x50000000 0x00024000>; | ||
interrupts = <0 65 0x04 /* mpcore syncpt */ | ||
0 67 0x04>; /* mpcore general */ | ||
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#address-cells = <1>; | ||
#size-cells = <1>; | ||
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ranges = <0x54000000 0x54000000 0x04000000>; | ||
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mpe { | ||
compatible = "nvidia,tegra20-mpe"; | ||
reg = <0x54040000 0x00040000>; | ||
interrupts = <0 68 0x04>; | ||
}; | ||
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vi { | ||
compatible = "nvidia,tegra20-vi"; | ||
reg = <0x54080000 0x00040000>; | ||
interrupts = <0 69 0x04>; | ||
}; | ||
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epp { | ||
compatible = "nvidia,tegra20-epp"; | ||
reg = <0x540c0000 0x00040000>; | ||
interrupts = <0 70 0x04>; | ||
}; | ||
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isp { | ||
compatible = "nvidia,tegra20-isp"; | ||
reg = <0x54100000 0x00040000>; | ||
interrupts = <0 71 0x04>; | ||
}; | ||
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gr2d { | ||
compatible = "nvidia,tegra20-gr2d"; | ||
reg = <0x54140000 0x00040000>; | ||
interrupts = <0 72 0x04>; | ||
}; | ||
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gr3d { | ||
compatible = "nvidia,tegra20-gr3d"; | ||
reg = <0x54180000 0x00040000>; | ||
}; | ||
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dc@54200000 { | ||
compatible = "nvidia,tegra20-dc"; | ||
reg = <0x54200000 0x00040000>; | ||
interrupts = <0 73 0x04>; | ||
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rgb { | ||
status = "disabled"; | ||
}; | ||
}; | ||
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dc@54240000 { | ||
compatible = "nvidia,tegra20-dc"; | ||
reg = <0x54240000 0x00040000>; | ||
interrupts = <0 74 0x04>; | ||
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rgb { | ||
status = "disabled"; | ||
}; | ||
}; | ||
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hdmi { | ||
compatible = "nvidia,tegra20-hdmi"; | ||
reg = <0x54280000 0x00040000>; | ||
interrupts = <0 75 0x04>; | ||
status = "disabled"; | ||
}; | ||
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tvo { | ||
compatible = "nvidia,tegra20-tvo"; | ||
reg = <0x542c0000 0x00040000>; | ||
interrupts = <0 76 0x04>; | ||
status = "disabled"; | ||
}; | ||
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dsi { | ||
compatible = "nvidia,tegra20-dsi"; | ||
reg = <0x54300000 0x00040000>; | ||
status = "disabled"; | ||
}; | ||
}; | ||
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||
... | ||
}; |
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