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Merge tag 'clk-for-linus-3.11' of git://git.linaro.org/people/mturque…
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Pull clock framework updates from Mike Turquette:
 "The common clock framework changes for 3.11 include new clock drivers
  across several different platforms and architectures, fixes to
  existing drivers, a MAINTAINERS file fix and improvements to the basic
  clock types that allow them to be of use to more platforms than before.

  Only a few fixes to the core framework are included with most all of
  the changes landing in the various clock drivers themselves."

* tag 'clk-for-linus-3.11' of git://git.linaro.org/people/mturquette/linux: (55 commits)
  clk: tegra: fix ifdef for tegra_periph_reset_assert inline
  clk: tegra: provide tegra_periph_reset_assert alternative
  clk: exynos4: Fix clock aliases for cpufreq related clocks
  clk: samsung: Add MUX_FA macro to pass flag and alias
  clk: add support for Rockchip gate clocks
  clk: vexpress: Make the clock drivers directly available for arm64
  clk: vexpress: Use full node name to identify individual clocks
  clk: tegra: T114: add DFLL DVCO reset control
  clk: tegra: T114: add DFLL source clocks
  clk: tegra: T114: add FCPU clock shaper programming, needed by the DFLL
  clk: gate: add CLK_GATE_HIWORD_MASK
  clk: divider: add CLK_DIVIDER_HIWORD_MASK flag
  clk: mux: add CLK_MUX_HIWORD_MASK
  clk: Always notify whole subtree when reparenting
  MAINTAINERS: make drivers/clk entry match subdirs
  clk: honor CLK_GET_RATE_NOCACHE in clk_set_rate
  clk: use clk_get_rate() for debugfs
  clk: tegra: Use override bits when needed
  clk: tegra: override bits for Tegra30 PLLM
  clk: tegra: override bits for Tegra114 PLLM
  ...
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@torvalds
torvalds committed Jul 3, 2013
2 parents 750b2d7 + 45e3ec3 commit 92295f6
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24 changes: 24 additions & 0 deletions Documentation/devicetree/bindings/clock/nspire-clock.txt
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TI-NSPIRE Clocks

Required properties:
- compatible: Valid compatible properties include:
"lsi,nspire-cx-ahb-divider" for the AHB divider in the CX model
"lsi,nspire-classic-ahb-divider" for the AHB divider in the older model
"lsi,nspire-cx-clock" for the base clock in the CX model
"lsi,nspire-classic-clock" for the base clock in the older model

- reg: Physical base address of the controller and length of memory mapped
region.

Optional:
- clocks: For the "nspire-*-ahb-divider" compatible clocks, this is the parent
clock where it divides the rate from.

Example:

ahb_clk {
#clock-cells = <0>;
compatible = "lsi,nspire-cx-clock";
reg = <0x900B0000 0x4>;
clocks = <&base_clk>;
};
74 changes: 74 additions & 0 deletions Documentation/devicetree/bindings/clock/rockchip.txt
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Device Tree Clock bindings for arch-rockchip

This binding uses the common clock binding[1].

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

== Gate clocks ==

The gate registers form a continuos block which makes the dt node
structure a matter of taste, as either all gates can be put into
one gate clock spanning all registers or they can be divided into
the 10 individual gates containing 16 clocks each.
The code supports both approaches.

Required properties:
- compatible : "rockchip,rk2928-gate-clk"
- reg : shall be the control register address(es) for the clock.
- #clock-cells : from common clock binding; shall be set to 1
- clock-output-names : the corresponding gate names that the clock controls
- clocks : should contain the parent clock for each individual gate,
therefore the number of clocks elements should match the number of
clock-output-names

Example using multiple gate clocks:

clk_gates0: gate-clk@200000d0 {
compatible = "rockchip,rk2928-gate-clk";
reg = <0x200000d0 0x4>;
clocks = <&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;

clock-output-names =
"gate_core_periph", "gate_cpu_gpll",
"gate_ddrphy", "gate_aclk_cpu",
"gate_hclk_cpu", "gate_pclk_cpu",
"gate_atclk_cpu", "gate_i2s0",
"gate_i2s0_frac", "gate_i2s1",
"gate_i2s1_frac", "gate_i2s2",
"gate_i2s2_frac", "gate_spdif",
"gate_spdif_frac", "gate_testclk";

#clock-cells = <1>;
};

clk_gates1: gate-clk@200000d4 {
compatible = "rockchip,rk2928-gate-clk";
reg = <0x200000d4 0x4>;
clocks = <&xin24m>, <&xin24m>,
<&xin24m>, <&dummy>,
<&dummy>, <&xin24m>,
<&xin24m>, <&dummy>,
<&xin24m>, <&dummy>,
<&xin24m>, <&dummy>,
<&xin24m>, <&dummy>,
<&xin24m>, <&dummy>;

clock-output-names =
"gate_timer0", "gate_timer1",
"gate_timer2", "gate_jtag",
"gate_aclk_lcdc1_src", "gate_otgphy0",
"gate_otgphy1", "gate_ddr_gpll",
"gate_uart0", "gate_frac_uart0",
"gate_uart1", "gate_frac_uart1",
"gate_uart2", "gate_frac_uart2",
"gate_uart3", "gate_frac_uart3";

#clock-cells = <1>;
};
5 changes: 5 additions & 0 deletions Documentation/devicetree/bindings/clock/silabs,si5351.txt
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Expand Up @@ -44,6 +44,11 @@ Optional child node properties:
- silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth
divider.
- silabs,pll-master: boolean, multisynth can change pll frequency.
- silabs,disable-state : clock output disable state, shall be
0 = clock output is driven LOW when disabled
1 = clock output is driven HIGH when disabled
2 = clock output is FLOATING (HIGH-Z) when disabled
3 = clock output is NEVER disabled

==Example==

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117 changes: 13 additions & 104 deletions Documentation/devicetree/bindings/clock/sunxi.txt
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Expand Up @@ -12,22 +12,30 @@ Required properties:
"allwinner,sun4i-axi-clk" - for the AXI clock
"allwinner,sun4i-axi-gates-clk" - for the AXI gates
"allwinner,sun4i-ahb-clk" - for the AHB clock
"allwinner,sun4i-ahb-gates-clk" - for the AHB gates
"allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10
"allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
"allwinner,sun4i-apb0-clk" - for the APB0 clock
"allwinner,sun4i-apb0-gates-clk" - for the APB0 gates
"allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10
"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
"allwinner,sun4i-apb1-clk" - for the APB1 clock
"allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
"allwinner,sun4i-apb1-gates-clk" - for the APB1 gates
"allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10
"allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13

Required properties for all clocks:
- reg : shall be the control register address for the clock.
- clocks : shall be the input parent clock(s) phandle for the clock
- #clock-cells : from common clock binding; shall be set to 0 except for
"allwinner,sun4i-*-gates-clk" where it shall be set to 1
"allwinner,*-gates-clk" where it shall be set to 1

Additionally, "allwinner,sun4i-*-gates-clk" clocks require:
Additionally, "allwinner,*-gates-clk" clocks require:
- clock-output-names : the corresponding gate names that the clock controls

Clock consumers should specify the desired clocks they use with a
"clocks" phandle cell. Consumers that are using a gated clock should
provide an additional ID in their clock property. The values of this
ID are documented in sunxi/<soc>-gates.txt.

For example:

osc24M: osc24M@01c20050 {
Expand All @@ -50,102 +58,3 @@ cpu: cpu@01c20054 {
reg = <0x01c20054 0x4>;
clocks = <&osc32k>, <&osc24M>, <&pll1>;
};



Gate clock outputs

The "allwinner,sun4i-*-gates-clk" clocks provide several gatable outputs;
their corresponding offsets as present on sun4i are listed below. Note that
some of these gates are not present on sun5i.

* AXI gates ("allwinner,sun4i-axi-gates-clk")

DRAM 0

* AHB gates ("allwinner,sun4i-ahb-gates-clk")

USB0 0
EHCI0 1
OHCI0 2*
EHCI1 3
OHCI1 4*
SS 5
DMA 6
BIST 7
MMC0 8
MMC1 9
MMC2 10
MMC3 11
MS 12**
NAND 13
SDRAM 14

ACE 16
EMAC 17
TS 18

SPI0 20
SPI1 21
SPI2 22
SPI3 23
PATA 24
SATA 25**
GPS 26*

VE 32
TVD 33
TVE0 34
TVE1 35
LCD0 36
LCD1 37

CSI0 40
CSI1 41

HDMI 43
DE_BE0 44
DE_BE1 45
DE_FE0 46
DE_FE1 47

MP 50

MALI400 52

* APB0 gates ("allwinner,sun4i-apb0-gates-clk")

CODEC 0
SPDIF 1*
AC97 2
IIS 3

PIO 5
IR0 6
IR1 7

KEYPAD 10

* APB1 gates ("allwinner,sun4i-apb1-gates-clk")

I2C0 0
I2C1 1
I2C2 2

CAN 4
SCR 5
PS20 6
PS21 7

UART0 16
UART1 17
UART2 18
UART3 19
UART4 20
UART5 21
UART6 22
UART7 23

Notation:
[*]: The datasheet didn't mention these, but they are present on AW code
[**]: The datasheet had this marked as "NC" but they are used on AW code
93 changes: 93 additions & 0 deletions Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt
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Gate clock outputs
------------------

* AXI gates ("allwinner,sun4i-axi-gates-clk")

DRAM 0

* AHB gates ("allwinner,sun4i-ahb-gates-clk")

USB0 0
EHCI0 1
OHCI0 2*
EHCI1 3
OHCI1 4*
SS 5
DMA 6
BIST 7
MMC0 8
MMC1 9
MMC2 10
MMC3 11
MS 12**
NAND 13
SDRAM 14

ACE 16
EMAC 17
TS 18

SPI0 20
SPI1 21
SPI2 22
SPI3 23
PATA 24
SATA 25**
GPS 26*

VE 32
TVD 33
TVE0 34
TVE1 35
LCD0 36
LCD1 37

CSI0 40
CSI1 41

HDMI 43
DE_BE0 44
DE_BE1 45
DE_FE1 46
DE_FE1 47

MP 50

MALI400 52

* APB0 gates ("allwinner,sun4i-apb0-gates-clk")

CODEC 0
SPDIF 1*
AC97 2
IIS 3

PIO 5
IR0 6
IR1 7

KEYPAD 10

* APB1 gates ("allwinner,sun4i-apb1-gates-clk")

I2C0 0
I2C1 1
I2C2 2

CAN 4
SCR 5
PS20 6
PS21 7

UART0 16
UART1 17
UART2 18
UART3 19
UART4 20
UART5 21
UART6 22
UART7 23

Notation:
[*]: The datasheet didn't mention these, but they are present on AW code
[**]: The datasheet had this marked as "NC" but they are used on AW code
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