Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

A Verilog synthesis flow for Minecraft redstone circuits

A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.

FIFO buffer library. Written and verified in SystemVerilog. Can be synthetised in ASIC or FPGA.

UART controller that uses a master-slave architecture to enstablish a communication with the other device during the configuration process. This repository provides RTL code and testbench for the d…

This repository contains different modules which execute arithmetic operations.

General purpose FPGA based System On Chip built around a powerful RISC-V 32 bit CPU.