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4 stars written in Verilog
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The-OpenROAD-Project / OpenROAD-flow-scripts

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

Verilog 320 275 Updated Sep 28, 2024

mflowgen / freepdk-45nm

ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen

Verilog 141 34 Updated Mar 8, 2020

andres-mancera / ethernet_10ge_mac_SV_tb

SystemVerilog testbench for an Ethernet 10GE MAC core

Verilog 44 17 Updated Apr 1, 2016

chipsalliance / UHDM-integration-tests

Verilog 30 8 Updated Oct 2, 2023

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