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GabbedT
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General purpose FPGA based System On Chip built around a powerful RISC-V 32 bit CPU.
A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.
Text, diagrams, and source code for the book Computer Graphics from scratch.
Adapted code to generate multiported SRAMs in Skywater 130 PDK
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
Xark's Open Source Embedded Retro Adapter - FPGA based video for rosco_m68k and others
UART controller that uses a master-slave architecture to enstablish a communication with the other device during the configuration process. This repository provides RTL code and testbench for the d…
SystemVerilog testbench for an Ethernet 10GE MAC core
This repository contains different modules which execute arithmetic operations.
FIFO buffer library. Written and verified in SystemVerilog. Can be synthetised in ASIC or FPGA.
A Verilog synthesis flow for Minecraft redstone circuits
A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model
This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an opensource RTL2GDS flow using OpenLANE and opensource PDK prov…
Physical Design Flow from RTL to GDS using Opensource tools.
ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
mflowgen -- A Modular ASIC/FPGA Flow Generator
Qflow full end-to-end digital synthesis flow for ASIC designs
PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open processes.
Hammer: Highly Agile Masks Made Effortlessly from RTL