Variables information

This page describes configuration variables and their default values.

Required variables

Variable	Description
DESIGN_NAME	The name of the top level module of the design
VERILOG_FILES	The path of the design's verilog files
CLOCK_PERIOD	The clock period for the design in ns
CLOCK_NET	The name of the Net input to root clock buffer.
CLOCK_PORT	The name of the design's clock port

Optional variables

These variables are optional that can be specified in the design configuration file.

Synthesis

Variable	Description
LIB_SYNTH	The library used for synthesis by yosys. (Default: $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/sky130_fd_sc_hd__tt_025C_1v80.lib)
SYNTH_BIN	The yosys binary used in the flow. (Default: yosys)
SYNTH_DRIVING_CELL	The cell to drive the input ports. (Default: sky130_fd_sc_hd__inv_8)
SYNTH_DRIVING_CELL_PIN	The name of the SYNTH_DRIVING_CELL output pin. (Default: Y)
SYNTH_CAP_LOAD	The capacitive load on the output ports in femtofarads. (Default: 17.65 ff)
SYNTH_MAX_FANOUT	The max load that the output ports can drive. (Default: 5 cells)
SYNTH_MAX_TRANS	The max transition time (slew) from high to low or low to high on cell inputs in ns. Used in synthesis (Default: Calculated at runtime as 10% of the provided clock period)
SYNTH_STRATEGY	Strategies for abc logic synthesis and technology mapping Possible values are 0, 1 (delay), 2, and 3 (area) (Default: 2)
SYNTH_BUFFERING	Enables abc cell buffering Enabled = 1, Disabled = 0 (Default: 1)
SYNTH_SIZING	Enables abc cell sizing (instead of buffering) Enabled = 1, Disabled = 0 (Default: 0)
SYNTH_READ_BLACKBOX_LIB	A flag that enable reading the full(untrimmed) libretry file as a blackbox for synthesis. Please note that this is not used in technology mapping. This should only be used when trying to preserve gate instances in the rtl of the design. Enabled = 1, Disabled = 0 (Default: 0)
SYNTH_NO_FLAT	A flag that disables flattening the heirachry during synthesis, only flattening it after synthesis, mapping and optimizations. Enabled = 1, Disabled = 0 (Default: 0)
LIB_SLOWEST	Points to the lib file, corresponding to the slowest corner, for max delay calculation during STA. (Default:$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib)
LIB_FASTEST	Points to the lib file, corresponding to the fastest corner, for min delay calculation during STA. (Default:$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/sky130_fd_sc_hd__ss_100C_1v60.lib)
LIB_TYPICAL	Library used for typical delay calculation during STA. (DefaultLIB_SYNTH)
CLOCK_BUFFER_FANOUT	Fanout of clock tree buffers. (Default: 16)
ROOT_CLK_BUFFER	Root clock buffer of the clock tree. (Default: sky130_fd_sc_hd__clkbuf_16)
CLK_BUFFER	Clock buffer used for inner nodes of the clock tree. (Default: sky130_fd_sc_hd__clkbuf_4)
CLK_BUFFER_INPUT	Input pin of the clock tree buffer. (Default: A)
CLK_BUFFER_OUTPUT	Output pin of the clock tree buffer. (Default: X)
BASE_SDC_FILE	Specifies the base sdc file to source before running Static Timing Analysis. (Default: $::env(OPENLANE_ROOT)/scripts/base.sdc)
VERILOG_INCLUDE_DIRS	Specifies the verilog includes directories. Optional.
SYNTH_FLAT_TOP	Specifies whether or not the top level should be flattened during elaboration. 1 = True, 0= False Default=0.

Floorplanning

Variable	Description
FP_CORE_UTIL	The core utilization percentage. (Default: 50 percent)
FP_ASPECT_RATIO	The core's aspect ratio (height / width). (Default: 1)
FP_SIZING	Whether to use relative sizing by making use of FP_CORE_UTIL or absolute one using DIE_AREA. (Default: "relative" - accepts "absolute" as well)
DIE_AREA	Specific die area to be used in floorplanning. Specified as a 4-corner rectangle. Units in microns (Default: unset)
FP_IO_HMETAL	The metal layer on which to place the io pins horizontally (top and bottom of the die). (Default: 4)
FP_IO_VMETAL	The metal layer on which to place the io pins vertically (sides of the die) (Default: 3)
FP_WELLTAP_CELL	The name of the welltap cell during welltap insertion.
FP_ENDCAP_CELL	The name of the endcap cell during endcap insertion.
FP_PDN_VOFFSET	The offset of the vertical power stripes on the metal layer 4 in the power distribution network (Default: 16.32)
FP_PDN_VPITCH	The pitch of the vertical power stripes on the metal layer 4 in the power distribution network (Default: 153.6)
FP_PDN_HOFFSET	The offset of the horizontal power stripes on the metal layer 5 in the power distribution network (Default: 16.65)
FP_PDN_HPITCH	The pitch of the horizontal power stripes on the metal layer 5 in the power distribution network (Default: 153.18)
FP_TAPCELL_DIST	The horizontal distance between two tapcell columns (Default: 25)
FP_IO_VEXTEND	Extends the vertical io pins outside of the die by the specified units (Default: -1 Disabled)
FP_IO_HEXTEND	Extends the horizontal io pins outside of the die by the specified units (Default: -1 Disabled)
FP_IO_VTHICKNESS_MULT	A multiplier for vertical pin thickness. Base thickness is the pins layer minwidth (Default: 1)
FP_IO_HTHICKNESS_MULT	A multiplier for horizontal pin thickness. Base thickness is the pins layer minwidth (Default: 1)
BOTTOM_MARGIN_MULT	The core margin, in multiples of site heights, from the bottom boundary. (Default: 4)
TOP_MARGIN_MULT	The core margin, in multiples of site heights, from the top boundary. (Default: 4)
LEFT_MARGIN_MULT	The core margin, in multiples of site widths, from the left boundary. (Default: 12)
RIGHT_MARGIN_MULT	The core margin, in multiples of site widths, from the right boundary. (Default: 12)

Placement

Variable	Description
PL_TARGET_DENSITY	The desired placement density of cells. It reflects how spread the cells would be on the core area. 1 = closely dense. 0 = widely spread (Default: 0.4)
PL_TIME_DIRVEN	Specifies whether the placer should use time driven placement. 0 = false, 1 = true (Default: 0)
PL_LIB	Specifies the library for time driven placement (Default: LIB_TYPICAL)
PL_BASIC_PLACEMENT	Specifies whether the placer should run basic placement or not (by running initial placement, increasing the minimum overflow to 0.9, and limiting the number of iterations to 20). 0 = false, 1 = true (Default: 0)
PL_SKIP_INITIAL_PLACEMENT	Specifies whether the placer should run initial placement or not. 0 = false, 1 = true (Default: 0)
PL_ROUTABILITY_DRIVEN	Specifies whether the placer should use routability driven placement. 0 = false, 1 = true (Default: 0)
PL_OPENPHYSYN_OPTIMIZATIONS	Specifies whether OpenPhySyn should be used to perform timing optimizations or not. 0 = false, 1 = true (Default: 1)
PSN_ENABLE_RESIZING	Enables driver resizing by OpenPhySyn. 0 = Disabled, 1 = Enabled (Default: 1)
PSN_ENABLE_PIN_SWAP	Enables pin swapping for timing optimization by OpenPhySyn. 0 = Disabled, 1 = Enabled (Default: 1)
PL_RESIZER_OVERBUFFER	Enables inserting buffers to reduce the number of long wires.1 = Enabled, 0 = Disabled (Default: 0)
LIB_OPT	Points to the lib file, corresponding to the slowest corner, for max delay calculation during OpenPhySyn optimizations. This is usually a trimmed version of LIB_SLOWEST. Default: $::env(TMP_DIR)/opt.lib

CTS

Variable	Description
CTS_TARGET_SKEW	The target clock skew in picoseconds. (Default: 20 ps)
CTS_ROOT_BUFFER	The name of cell inserted at the root of the clock tree.
CLOCK_TREE_SYNTH	Enable clock tree synthesis for tirtonCTS. (Default: 1)
CTS_TOLERANCE	an integer value that represents a tradeoff of QoR and runtime. Higher values will produce smaller runtime but worse QoR (Default: 100)

Routing

Variable	Description
GLB_RT_MINLAYER	The number of lowest layer to be used in routing. (Default: 6)
GLB_RT_MAXLAYER	The number of highest layer to be used in routing. (Default: 6)
GLB_RT_ADJUSTMENT	Reduction in the routing capacity of the edges between the cells in the global routing graph. Values range from 0 to 1. 1 = most reduction, 0 = least reduction (Default: 0.15)
GLB_RT_L1_ADJUSTMENT	Reduction in the routing capacity of the edges between the cells in the global routing graph but specific to li1 layer in sky130A. Values range from 0 to 1 (Default: 0)
GLB_RT_L2_ADJUSTMENT	Reduction in the routing capacity of the edges between the cells in the global routing graph but specific to met1 in sky130A. Values range from 0 to 1 (Default: 0)
GLB_RT_UNIDIRECTIONAL	Allow unidirectional routing. 0 = false, 1 = true (Default: 1)
GLB_RT_ALLOW_CONGESTION	Allow congestion in the resultign guides. 0 = false, 1 = true (Default: 0)
GLB_RT_OVERFLOW_ITERS	The maximum number of iterations waiting for the overflow to reach the desired value. (Default: 50)
GLB_RT_TILES	The size of the GCELL used by Fastroute during global routing. (Default: 15)
ROUTING_CORES	Specifies the number of threads to be used in TritonRoute. (Default: 4)

Magic

Variable	Description
MAGIC_PAD	A flag to pad the views generated by magic (.mag, .lef, .gds) with one site. 1 = Enabled, 0 = Disabled (Default: 0 )
MAGIC_ZEROIZE_ORIGIN	A flag to move the layout such that it's origin in the lef generated by magic is 0,0. 1 = Enabled, 0 = Disabled (Default: 1 )
MAGIC_GENERATE_GDS	A flag to generate gds view via magic . 1 = Enabled, 0 = Disabled (Default: 1 )
MAGIC_GENERATE_LEF	A flag to generate lef view via magic . 1 = Enabled, 0 = Disabled (Default: 1 )

LVS

Variable	Description
LVS_INSERT_POWER_PINS	Enables power pins insertion before running lvs. 1 = Enabled, 0 = Disabled (Default: 1 )

Misc

Variable	Description
PDK	Specifies the process design kit (PDK). (Default: sky130A )
STD_CELL_LIBRARY	Specifies the standard cell library to be used under the specified PDK. (Default: sky130_fd_sc_hd )
PDK_ROOT	Specifies the folder path of the PDK. It searches for a config.tcl in $PDK_ROOT/$PDK/libs.tech/openlane/ directory and at least have one standard cell library config defined in $PDK_ROOT/$PDK/libs.tech/openlane/$STD_CELL_LIBRARY.
CELL_PAD	Cell padding; increases the width of cells. (Default: 2 microns -- 2 sites)
DIODE_PADDING	Diode cell padding; increases the width of diode cells during placement checks. (Default: 2 microns -- 2 sites)

Flow control

Variable	Description
RUN_ROUTING_DETAILED	Enables detailed routing. 1 = Enabled, 0 = Disabled (Default: 1)
RUN_MAGIC	Enables running magic and GDSII streaming.1 = Enabled, 0 = Disabled (Default: 0)
RUN_SIMPLE_CTS	Enables inserting simple clock tree after synthesis .1 = Enabled, 0 = Disabled (Default: 0)
FILL_INSERTION	Enables fill cells insertion after cts (if enabled) .1 = Enabled, 0 = Disabled (Default: 0)
DIODE_INSERTION_STRATEGY	Specifies the insertion strategy of diodes to be used in the flow. 0 = No diode insertion, 1 = Spray diodes, 2 = insert fake diodes and replace them with real diodes if needed (Default: 1)
WIDEN_SITE	Specifies the new virtual width of the site to be used in all stages up to diode insertion, then switched back to the original site width. It can be either a factor or an absolute value controlled by WIDEN_SITE_IS_FACTOR (Default: 1)
WIDEN_SITE_IS_FACTOR	Specifies whether the given WIDEN_SITE should be treated as a factor or an absolute value. 0 = absolute, 1 = factor (Default: 1)
USE_ARC_ANTENNA_CHECK	Specifies whether to use the openroad ARC antenna checker or magic antenna checker. 0=magic antenna checker, 1=ARC OR antenna checker (Default: 0)
RUN_SPEF_EXTRACTION	Specifies whether or not to run SPEF extraction on the routed DEF. 1=enabled 0=disabled Default 1
SPEF_WIRE_MODEL	Specifies the wire model used in SPEF extraction. Options are L or Pi Default L
SPEF_EDGE_CAP_FACTOR	Specifies the edge capacitance factor used in SPEF extraction. Ranges from 0 to 1 Default 1

Checkers

Variable	Description
CHECK_UNMAPPED_CELLS	Checks if there are unmapped cells after synthesis and aborts if any was found. 1 = Enabled, 0 = Disabled (Default: 0)
CHECK_ASSIGN_STATEMENTS	Checks for assign statement in the generated gate level netlist and aborts of any was found.1 = Enabled, 0 = Disabled (Default: 0)
CHECK_LATCHES_IN_DESIGN	Checks for any latches or failures in synthesis and aborts if any was found. 1 = Enabled, 0 = Disabled (Default: 1)
CHECK_DIODE_PLACEMENT	Checks if there was any failure in legalizing placement after inserting diodes and aborts if any was found.1 = Enabled, 0 = Disabled (Default: 1)