diff --git a/Makefile b/Makefile index 88128ec72a26..e0d7a52d3b09 100644 --- a/Makefile +++ b/Makefile @@ -599,6 +599,7 @@ KBUILD_CFLAGS += $(KCFLAGS) UBOOTINCLUDE := \ -Iinclude \ $(if $(KBUILD_SRC), -I$(srctree)/include) \ + -I$(srctree)/lib/libfdt \ $(if $(CONFIG_SYS_THUMB_BUILD), $(if $(CONFIG_HAS_THUMB2),, \ -I$(srctree)/arch/$(ARCH)/thumb1/include),) \ -I$(srctree)/arch/$(ARCH)/include \ @@ -637,6 +638,7 @@ libs-y += drivers/net/ libs-y += drivers/net/phy/ libs-y += drivers/pci/ libs-y += drivers/power/ \ + drivers/power/domain/ \ drivers/power/fuel_gauge/ \ drivers/power/mfd/ \ drivers/power/pmic/ \ @@ -771,6 +773,10 @@ ifneq ($(CONFIG_BUILD_TARGET),) ALL-y += $(CONFIG_BUILD_TARGET:"%"=%) endif +ifneq ($(CONFIG_SYS_INIT_SP_BSS_OFFSET),) +ALL-y += init_sp_bss_offset_check +endif + LDFLAGS_u-boot += $(LDFLAGS_FINAL) ifneq ($(CONFIG_SYS_TEXT_BASE),) LDFLAGS_u-boot += -Ttext $(CONFIG_SYS_TEXT_BASE) @@ -859,6 +865,33 @@ binary_size_check: u-boot-nodtb.bin FORCE fi \ fi +ifneq ($(CONFIG_SYS_INIT_SP_BSS_OFFSET),) +ifneq ($(CONFIG_SYS_MALLOC_F_LEN),) +subtract_sys_malloc_f_len = space=$$(($${space} - $(CONFIG_SYS_MALLOC_F_LEN))) +else +subtract_sys_malloc_f_len = true +endif +# The 1/4 margin below is somewhat arbitrary. The likely initial SP usage is +# so low that the DTB could probably use 90%+ of the available space, for +# current values of CONFIG_SYS_INIT_SP_BSS_OFFSET at least. However, let's be +# safe for now and tweak this later if space becomes tight. +# A rejected alternative would be to check that some absolute minimum stack +# space was available. However, since CONFIG_SYS_INIT_SP_BSS_OFFSET is +# deliberately build-specific, to take account of build-to-build stack usage +# differences due to different feature sets, there is no common absolute value +# to check against. +init_sp_bss_offset_check: u-boot.dtb FORCE + @dtb_size=$(shell wc -c u-boot.dtb | awk '{print $$1}') ; \ + space=$(CONFIG_SYS_INIT_SP_BSS_OFFSET) ; \ + $(subtract_sys_malloc_f_len) ; \ + quarter_space=$$(($${space} / 4)) ; \ + if [ $${dtb_size} -gt $${quarter_space} ]; then \ + echo "u-boot.dtb is larger than 1 quarter of " >&2 ; \ + echo "(CONFIG_SYS_INIT_SP_BSS_OFFSET - CONFIG_SYS_MALLOC_F_LEN)" >&2 ; \ + exit 1 ; \ + fi +endif + u-boot-nodtb.bin: u-boot FORCE $(call if_changed,objcopy) $(call DO_STATIC_RELA,$<,$@,$(CONFIG_SYS_TEXT_BASE)) diff --git a/README b/README index 26d5ad273ef2..15542b816d4b 100644 --- a/README +++ b/README @@ -5,6 +5,15 @@ # SPDX-License-Identifier: GPL-2.0+ # +TMR Instructions: +================= + +The TMR code is written in common/tmr.c and implemented in common/main.c (n main_loop()). + +Before flashing, some modifications must be made on the TX2i filesystem. Make 3 copies of the boot image (stored as /boot/Image, /boot/Image1, /boot/Image2), and store an md5 hash for each (/boot/hash, /boot/hash1, /boot/hash2). The filesize of the image is hard-coded into the TMR code (0x34048008 bytes, in hex), and this should be changed on common/tmr.c:68 if using an image of a different size. + +To flash the kernel, follow the "U-Boot Customization" instructions in the L4T docs, particularly the "Flashing U-Boot Only" section. + Summary: ======== diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3237a74f7223..f4fd90b07cd1 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -7,6 +7,52 @@ config SYS_ARCH config ARM64 bool +if ARM64 +config POSITION_INDEPENDENT + bool "Generate position-independent pre-relocation code" + help + U-Boot expects to be linked to a specific hard-coded address, and to + be loaded to and run from that address. This option lifts that + restriction, thus allowing the code to be loaded to and executed + from almost any address. This logic relies on the relocation + information that is embedded into the binary to support U-Boot + relocating itself to the top-of-RAM later during execution. + +config SYS_INIT_SP_BSS_OFFSET + int + help + U-Boot typically uses a hard-coded value for the stack pointer + before relocation. Define this option to instead calculate the + initial SP at run-time. This is useful to avoid hard-coding addresses + into U-Boot, so that can be loaded and executed at arbitrary + addresses and thus avoid using arbitrary addresses at runtime. This + option's value is the offset added to &_bss_start in order to + calculate the stack pointer. This offset should be large enough so + that the early malloc region, global data (gd), and early stack usage + do not overlap any appended DTB. + +config LINUX_KERNEL_IMAGE_HEADER + bool + help + Place a Linux kernel image header at the start of the U-Boot binary. + The format of the header is described in the Linux kernel source at + Documentation/arm64/booting.txt. This feature is useful since the + image header reports the amount of memory (BSS and similar) that + U-Boot needs to use, but which isn't part of the binary. + +if LINUX_KERNEL_IMAGE_HEADER +config LNX_KRNL_IMG_TEXT_OFFSET_BASE + hex + help + The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the + TEXT_OFFSET value written in to the Linux kernel image header. +endif +endif + +config STATIC_RELA + bool + default y if ARM64 && !POSITION_INDEPENDENT + config DMA_ADDR_T_64BIT bool default y if ARM64 diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S index 46f25e63f01d..f1deaa723024 100644 --- a/arch/arm/cpu/armv8/cache.S +++ b/arch/arm/cpu/armv8/cache.S @@ -150,11 +150,23 @@ ENTRY(__asm_invalidate_icache_all) ret ENDPROC(__asm_invalidate_icache_all) -ENTRY(__asm_flush_l3_cache) +ENTRY(__asm_invalidate_l3_dcache) mov x0, #0 /* return status as success */ ret -ENDPROC(__asm_flush_l3_cache) - .weak __asm_flush_l3_cache +ENDPROC(__asm_invalidate_l3_dcache) + .weak __asm_invalidate_l3_dcache + +ENTRY(__asm_flush_l3_dcache) + mov x0, #0 /* return status as success */ + ret +ENDPROC(__asm_flush_l3_dcache) + .weak __asm_flush_l3_dcache + +ENTRY(__asm_invalidate_l3_icache) + mov x0, #0 /* return status as success */ + ret +ENDPROC(__asm_invalidate_l3_icache) + .weak __asm_invalidate_l3_icache /* * void __asm_switch_ttbr(ulong new_ttbr) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 1615542a99f3..e3af6e9b0889 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -408,19 +408,20 @@ __weak void mmu_setup(void) void invalidate_dcache_all(void) { __asm_invalidate_dcache_all(); + __asm_invalidate_l3_dcache(); } /* * Performs a clean & invalidation of the entire data cache at all levels. * This function needs to be inline to avoid using stack. - * __asm_flush_l3_cache return status of timeout + * __asm_flush_l3_dcache return status of timeout */ inline void flush_dcache_all(void) { int ret; __asm_flush_dcache_all(); - ret = __asm_flush_l3_cache(); + ret = __asm_flush_l3_dcache(); if (ret) debug("flushing dcache returns 0x%x\n", ret); else @@ -607,7 +608,7 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, void icache_enable(void) { - __asm_invalidate_icache_all(); + invalidate_icache_all(); set_sctlr(get_sctlr() | CR_I); } @@ -624,6 +625,7 @@ int icache_status(void) void invalidate_icache_all(void) { __asm_invalidate_icache_all(); + __asm_invalidate_l3_icache(); } #else /* CONFIG_SYS_ICACHE_OFF */ diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c index e06c3cc04de4..bd76de22fb5e 100644 --- a/arch/arm/cpu/armv8/cpu.c +++ b/arch/arm/cpu/armv8/cpu.c @@ -16,6 +16,8 @@ #include #include +void __weak board_cleanup_before_linux(void){} + int cleanup_before_linux(void) { /* @@ -24,6 +26,9 @@ int cleanup_before_linux(void) * * disable interrupt and turn off caches etc ... */ + + board_cleanup_before_linux(); + disable_interrupts(); /* diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 5af6b73bc9e8..655200660970 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -230,7 +230,7 @@ hnf_set_pstate: ret -ENTRY(__asm_flush_l3_cache) +ENTRY(__asm_flush_l3_dcache) /* * Return status in x0 * success 0 @@ -260,7 +260,7 @@ ENTRY(__asm_flush_l3_cache) mov x0, x8 mov lr, x29 ret -ENDPROC(__asm_flush_l3_cache) +ENDPROC(__asm_flush_l3_dcache) #endif #ifdef CONFIG_MP diff --git a/arch/arm/cpu/armv8/linux-kernel-image-header-vars.h b/arch/arm/cpu/armv8/linux-kernel-image-header-vars.h new file mode 100644 index 000000000000..3e720937f012 --- /dev/null +++ b/arch/arm/cpu/armv8/linux-kernel-image-header-vars.h @@ -0,0 +1,86 @@ +/* + * (C) Copyright 2017 NVIDIA Corporation + * + * Derived from Linux kernel v4.14 files: + * + * arch/arm64/include/asm/assembler.h: + * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S + * Copyright (C) 1996-2000 Russell King + * Copyright (C) 2012 ARM Ltd. + * + * arch/arm64/kernel/head.S: + * Based on arch/arm/kernel/head.S + * Copyright (C) 1994-2002 Russell King + * Copyright (C) 2003-2012 ARM Ltd. + * Authors: Catalin Marinas + * Will Deacon + * + * arch/arm64/kernel/image.h: + * Copyright (C) 2014 ARM Ltd. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +/* + * There aren't any ELF relocations we can use to endian-swap values known only + * at link time (e.g. the subtraction of two symbol addresses), so we must get + * the linker to endian-swap certain values before emitting them. + * + * Note that, in order for this to work when building the ELF64 PIE executable + * (for KASLR), these values should not be referenced via R_AARCH64_ABS64 + * relocations, since these are fixed up at runtime rather than at build time + * when PIE is in effect. So we need to split them up in 32-bit high and low + * words. + */ +#ifdef CONFIG_CPU_BIG_ENDIAN +#define DATA_LE32(data) \ + ((((data) & 0x000000ff) << 24) | \ + (((data) & 0x0000ff00) << 8) | \ + (((data) & 0x00ff0000) >> 8) | \ + (((data) & 0xff000000) >> 24)) +#else +#define DATA_LE32(data) ((data) & 0xffffffff) +#endif + +#define DEFINE_IMAGE_LE64(sym, data) \ + sym##_lo32 = DATA_LE32((data) & 0xffffffff); \ + sym##_hi32 = DATA_LE32((data) >> 32) + +#define __MAX(a, b) (((a) > (b)) ? (a) : (b)) +#define __CODE_DATA_SIZE (__bss_start - _start) +#define __BSS_SIZE (__bss_end - __bss_start) +#ifdef CONFIG_SYS_INIT_SP_BSS_OFFSET +#define __MAX_EXTRA_RAM_USAGE __MAX(__BSS_SIZE, CONFIG_SYS_INIT_SP_BSS_OFFSET) +#else +#define __MAX_EXTRA_RAM_USAGE __BSS_SIZE +#endif +#define __MEM_USAGE (__CODE_DATA_SIZE + __MAX_EXTRA_RAM_USAGE) + +#ifdef CONFIG_CPU_BIG_ENDIAN +#define __HEAD_FLAG_BE 1 +#else +#define __HEAD_FLAG_BE 0 +#endif + +#define __HEAD_FLAG_PAGE_SIZE 1 /* 4K hard-coded */ + +#define __HEAD_FLAG_PHYS_BASE 1 + +#define __HEAD_FLAGS ((__HEAD_FLAG_BE << 0) | \ + (__HEAD_FLAG_PAGE_SIZE << 1) | \ + (__HEAD_FLAG_PHYS_BASE << 3)) + +#define TEXT_OFFSET (CONFIG_SYS_TEXT_BASE - \ + CONFIG_LNX_KRNL_IMG_TEXT_OFFSET_BASE) + +/* + * These will output as part of the Image header, which should be little-endian + * regardless of the endianness of the kernel. While constant values could be + * endian swapped in head.S, all are done here for consistency. + */ +#define HEAD_SYMBOLS \ + DEFINE_IMAGE_LE64(_kernel_size_le, __MEM_USAGE); \ + DEFINE_IMAGE_LE64(_kernel_offset_le, TEXT_OFFSET); \ + DEFINE_IMAGE_LE64(_kernel_flags_le, __HEAD_FLAGS); + + HEAD_SYMBOLS diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index dfce46920668..a2c436e459e3 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -19,7 +19,11 @@ .globl _start _start: +#if defined(CONFIG_LINUX_KERNEL_IMAGE_HEADER) +#include +#else b reset +#endif #ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK /* @@ -53,6 +57,37 @@ _bss_end_ofs: .quad __bss_end - _start reset: + /* Allow the board to save important registers */ + b save_boot_params +.globl save_boot_params_ret +save_boot_params_ret: + +#if CONFIG_POSITION_INDEPENDENT + /* + * Fix .rela.dyn relocations. This allows U-Boot to be loaded to and + * executed at a different address than it was linked at. + */ +pie_fixup: + adr x0, _start /* x0 <- Runtime value of _start */ + ldr x1, _TEXT_BASE /* x1 <- Linked value of _start */ + sub x9, x0, x1 /* x9 <- Run-vs-link offset */ + adr x2, __rel_dyn_start /* x2 <- Runtime &__rel_dyn_start */ + adr x3, __rel_dyn_end /* x3 <- Runtime &__rel_dyn_end */ +pie_fix_loop: + ldp x0, x1, [x2], #16 /* (x0, x1) <- (Link location, fixup) */ + ldr x4, [x2], #8 /* x4 <- addend */ + cmp w1, #1027 /* relative fixup? */ + bne pie_skip_reloc + /* relative fix: store addend plus offset at dest location */ + add x0, x0, x9 + add x4, x4, x9 + str x4, [x0] +pie_skip_reloc: + cmp x2, x3 + b.lo pie_fix_loop +pie_fixup_done: +#endif + #ifdef CONFIG_SYS_RESET_SCTRL bl reset_sctrl #endif @@ -81,14 +116,6 @@ reset: msr cpacr_el1, x0 /* Enable FP/SIMD */ 0: - /* Enalbe SMPEN bit for coherency. - * This register is not architectural but at the moment - * this bit should be set for A53/A57/A72. - */ - mrs x0, S3_1_c15_c2_1 /* cpuactlr_el1 */ - orr x0, x0, #0x40 - msr S3_1_c15_c2_1, x0 - /* Apply ARM core specific erratas */ bl apply_core_errata @@ -288,3 +315,7 @@ ENTRY(c_runtime_cpu_setup) ret ENDPROC(c_runtime_cpu_setup) + +WEAK(save_boot_params) + b save_boot_params_ret /* back to my caller */ +ENDPROC(save_boot_params) diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds index fd15ad59637d..a622ba51ee6d 100644 --- a/arch/arm/cpu/armv8/u-boot.lds +++ b/arch/arm/cpu/armv8/u-boot.lds @@ -8,6 +8,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include + OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") OUTPUT_ARCH(aarch64) ENTRY(_start) @@ -102,4 +104,8 @@ SECTIONS /DISCARD/ : { *(.plt*) } /DISCARD/ : { *(.interp*) } /DISCARD/ : { *(.gnu*) } + +#ifdef CONFIG_LINUX_KERNEL_IMAGE_HEADER +#include "linux-kernel-image-header-vars.h" +#endif } diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ef573ec68515..bbd4deb1cb00 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -53,11 +53,13 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra124-jetson-tk1.dtb \ tegra124-nyan-big.dtb \ tegra124-venice2.dtb \ - tegra186-p2771-0000.dtb \ + tegra186-p2771-0000-000.dtb \ + tegra186-p2771-0000-500.dtb \ tegra210-e2220-1170.dtb \ tegra210-p2371-0000.dtb \ tegra210-p2371-2180.dtb \ - tegra210-p2571.dtb + tegra210-p2571.dtb \ + tegra210-p3450-porg.dtb dtb-$(CONFIG_ARCH_MVEBU) += \ armada-375-db.dtb \ diff --git a/arch/arm/dts/tegra186-p2771-0000-000.dts b/arch/arm/dts/tegra186-p2771-0000-000.dts new file mode 100644 index 000000000000..d97c6fd3d09a --- /dev/null +++ b/arch/arm/dts/tegra186-p2771-0000-000.dts @@ -0,0 +1,32 @@ +/dts-v1/; + +#include "tegra186-p2771-0000.dtsi" + +/ { + model = "NVIDIA P2771-0000-000"; + compatible = "nvidia,p2771-0000-000", "nvidia,p2771-0000", "nvidia,tegra186"; + + sdhci@3400000 { + cd-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 6) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 5) GPIO_ACTIVE_HIGH>; + }; + + pcie-controller@10003000 { + status = "okay"; + + pci@1,0 { + status = "okay"; + nvidia,num-lanes = <2>; + }; + + pci@2,0 { + status = "disabled"; + nvidia,num-lanes = <1>; + }; + + pci@3,0 { + status = "okay"; + nvidia,num-lanes = <1>; + }; + }; +}; diff --git a/arch/arm/dts/tegra186-p2771-0000-500.dts b/arch/arm/dts/tegra186-p2771-0000-500.dts new file mode 100644 index 000000000000..393a8b246a0b --- /dev/null +++ b/arch/arm/dts/tegra186-p2771-0000-500.dts @@ -0,0 +1,32 @@ +/dts-v1/; + +#include "tegra186-p2771-0000.dtsi" + +/ { + model = "NVIDIA P2771-0000-500"; + compatible = "nvidia,p2771-0000-500", "nvidia,p2771-0000", "nvidia,tegra186"; + + sdhci@3400000 { + cd-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 5) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 6) GPIO_ACTIVE_HIGH>; + }; + + pcie-controller@10003000 { + status = "okay"; + + pci@1,0 { + status = "okay"; + nvidia,num-lanes = <4>; + }; + + pci@2,0 { + status = "disabled"; + nvidia,num-lanes = <0>; + }; + + pci@3,0 { + status = "disabled"; + nvidia,num-lanes = <1>; + }; + }; +}; diff --git a/arch/arm/dts/tegra186-p2771-0000.dts b/arch/arm/dts/tegra186-p2771-0000.dts deleted file mode 100644 index 5f29ee450194..000000000000 --- a/arch/arm/dts/tegra186-p2771-0000.dts +++ /dev/null @@ -1,25 +0,0 @@ -/dts-v1/; - -#include "tegra186.dtsi" - -/ { - model = "NVIDIA P2771-0000"; - compatible = "nvidia,p2771-0000", "nvidia,tegra186"; - - chosen { - stdout-path = &uarta; - }; - - aliases { - sdhci0 = "/sdhci@3460000"; - }; - - memory { - reg = <0x0 0x80000000 0x0 0x60000000>; - }; - - sdhci@3460000 { - status = "okay"; - bus-width = <8>; - }; -}; diff --git a/arch/arm/dts/tegra186-p2771-0000.dtsi b/arch/arm/dts/tegra186-p2771-0000.dtsi new file mode 100644 index 000000000000..6852ca6175fe --- /dev/null +++ b/arch/arm/dts/tegra186-p2771-0000.dtsi @@ -0,0 +1,83 @@ +#include "tegra186.dtsi" + +/ { + model = "NVIDIA P2771-0000"; + compatible = "nvidia,p2771-0000", "nvidia,tegra186"; + + chosen { + stdout-path = &uarta; + }; + + aliases { + sdhci0 = "/sdhci@3460000"; + sdhci1 = "/sdhci@3440000"; + sdhci2 = "/sdhci@3400000"; + i2c0 = "/bpmp/i2c"; + i2c1 = "/i2c@3160000"; + i2c2 = "/i2c@c240000"; + i2c3 = "/i2c@3180000"; + i2c4 = "/i2c@3190000"; + i2c5 = "/i2c@31c0000"; + i2c6 = "/i2c@c250000"; + i2c7 = "/i2c@31e0000"; + }; + + memory { + reg = <0x0 0x80000000 0x0 0x60000000>; + }; + + ethernet@2490000 { + status = "okay"; + phy-reset-gpios = <&gpio_main TEGRA_MAIN_GPIO(M, 4) GPIO_ACTIVE_LOW>; + }; + + i2c@3160000 { + status = "okay"; + }; + + i2c@3180000 { + status = "okay"; + }; + + i2c@3190000 { + status = "okay"; + }; + + i2c@31c0000 { + status = "okay"; + }; + + sdhci@3400000 { + status = "okay"; + wp-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 4) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + }; + + sdhci@3440000 { + status = "okay"; + bus-width = <4>; + }; + + sdhci@3460000 { + status = "okay"; + bus-width = <8>; + }; + + i2c@c240000 { + status = "okay"; + }; + + i2c@c250000 { + status = "okay"; + }; + + i2c@31e0000 { + status = "okay"; + }; + + bpmp { + i2c { + status = "okay"; + }; + }; +}; diff --git a/arch/arm/dts/tegra186.dtsi b/arch/arm/dts/tegra186.dtsi index fce34fa6500e..dd9e3b869de7 100644 --- a/arch/arm/dts/tegra186.dtsi +++ b/arch/arm/dts/tegra186.dtsi @@ -1,14 +1,18 @@ #include "skeleton.dtsi" -#include +#include +#include #include -#include +#include +#include +#include / { compatible = "nvidia,tegra186"; + interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; - gpio@2200000 { + gpio_main: gpio@2200000 { compatible = "nvidia,tegra186-gpio"; reg-names = "security", "gpio"; reg = @@ -27,6 +31,26 @@ #interrupt-cells = <2>; }; + ethernet@2490000 { + compatible = "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"; + reg = <0x0 0x02490000 0x0 0x10000>; + interrupts = ; + clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, + <&bpmp TEGRA186_CLK_EQOS_AXI>, + <&bpmp TEGRA186_CLK_EQOS_RX>, + <&bpmp TEGRA186_CLK_EQOS_PTP_REF>, + <&bpmp TEGRA186_CLK_EQOS_TX>; + clock-names = "slave_bus", + "master_bus", + "rx", + "ptp_ref", + "tx"; + resets = <&bpmp TEGRA186_RESET_EQOS>; + reset-names = "eqos"; + phy-mode = "rgmii"; + status = "disabled"; + }; + uarta: serial@3100000 { compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; reg = <0x0 0x03100000 0x0 0x10000>; @@ -34,26 +58,152 @@ status = "disabled"; }; + gen1_i2c: i2c@3160000 { + compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x3160000 0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA186_CLK_I2C1>; + clock-names = "div-clk"; + resets = <&bpmp TEGRA186_RESET_I2C1>; + reset-names = "i2c"; + status = "disabled"; + }; + + cam_i2c: i2c@3180000 { + compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x3180000 0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA186_CLK_I2C3>; + clock-names = "div-clk"; + resets = <&bpmp TEGRA186_RESET_I2C3>; + reset-names = "i2c"; + status = "disabled"; + }; + + dp_aux_ch1_i2c: i2c@3190000 { + compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x3190000 0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA186_CLK_I2C4>; + clock-names = "div-clk"; + resets = <&bpmp TEGRA186_RESET_I2C4>; + reset-names = "i2c"; + status = "disabled"; + }; + + dp_aux_ch0_i2c: i2c@31b0000 { + compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x31b0000 0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA186_CLK_I2C6>; + clock-names = "div-clk"; + resets = <&bpmp TEGRA186_RESET_I2C6>; + reset-names = "i2c"; + status = "disabled"; + }; + + gen7_i2c: i2c@31c0000 { + compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x31c0000 0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA186_CLK_I2C7>; + clock-names = "div-clk"; + resets = <&bpmp TEGRA186_RESET_I2C7>; + reset-names = "i2c"; + status = "disabled"; + }; + + gen9_i2c: i2c@31e0000 { + compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x31e0000 0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA186_CLK_I2C9>; + clock-names = "div-clk"; + resets = <&bpmp TEGRA186_RESET_I2C9>; + reset-names = "i2c"; + status = "disabled"; + }; + + sdhci@3400000 { + compatible = "nvidia,tegra186-sdhci"; + reg = <0x0 0x03400000 0x0 0x200>; + resets = <&bpmp TEGRA186_RESET_SDMMC1>; + reset-names = "sdhci"; + clocks = <&bpmp TEGRA186_CLK_SDMMC1>; + interrupts = ; + status = "disabled"; + }; + sdhci@3460000 { compatible = "nvidia,tegra186-sdhci"; reg = <0x0 0x03460000 0x0 0x200>; + resets = <&bpmp TEGRA186_RESET_SDMMC4>; + reset-names = "sdhci"; + clocks = <&bpmp TEGRA186_CLK_SDMMC4>; interrupts = ; status = "disabled"; }; + gic: interrupt-controller@3881000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x3881000 0x0 0x1000>, + <0x0 0x3882000 0x0 0x2000>, + <0x0 0x3884000 0x0 0x2000>, + <0x0 0x3886000 0x0 0x2000>; + interrupts = ; + interrupt-parent = <&gic>; + }; + hsp: hsp@3c00000 { compatible = "nvidia,tegra186-hsp"; reg = <0x0 0x03c00000 0x0 0xa0000>; interrupts = ; - nvidia,num-SM = <0x8>; - nvidia,num-AS = <0x2>; - nvidia,num-SS = <0x2>; - nvidia,num-DB = <0x7>; - nvidia,num-SI = <0x8>; - #mbox-cells = <1>; + interrupt-names = "doorbell"; + #mbox-cells = <2>; }; - gpio@c2f0000 { + gen2_i2c: i2c@c240000 { + compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0xc240000 0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA186_CLK_I2C2>; + clock-names = "div-clk"; + resets = <&bpmp TEGRA186_RESET_I2C2>; + reset-names = "i2c"; + status = "disabled"; + }; + + gen8_i2c: i2c@c250000 { + compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0xc250000 0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA186_CLK_I2C8>; + clock-names = "div-clk"; + resets = <&bpmp TEGRA186_RESET_I2C8>; + reset-names = "i2c"; + status = "disabled"; + }; + + gpio_aon: gpio@c2f0000 { compatible = "nvidia,tegra186-gpio-aon"; reg-names = "security", "gpio"; reg = @@ -66,4 +216,123 @@ interrupt-controller; #interrupt-cells = <2>; }; + + pcie-controller@10003000 { + compatible = "nvidia,tegra186-pcie"; + device_type = "pci"; + reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ + 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ + 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ + reg-names = "pads", "afi", "cs"; + interrupts = , /* controller interrupt */ + , /* MSI interrupt */ + ; /* Wake interrupt */ + interrupt-names = "intr", "msi", "wake"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + + bus-range = <0x00 0xff>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ + 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ + 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ + 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ + 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07f00000 /* non-prefetchable memory (127 MiB) */ + 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ + + clocks = <&bpmp TEGRA186_CLK_PCIE>, + <&bpmp TEGRA186_CLK_AFI>; + clock-names = "pex", "afi"; + resets = <&bpmp TEGRA186_RESET_PCIE>, + <&bpmp TEGRA186_RESET_AFI>, + <&bpmp TEGRA186_RESET_PCIEXCLK>; + reset-names = "pex", "afi", "pcie_x"; + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; + status = "disabled"; + + pci@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; + reg = <0x000800 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + + pci@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; + reg = <0x001000 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <1>; + }; + + pci@3,0 { + device_type = "pci"; + assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; + reg = <0x001800 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <1>; + }; + }; + + sysram@30000000 { + compatible = "nvidia,tegra186-sysram", "mmio-sram"; + reg = <0x0 0x30000000 0x0 0x50000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; + + sysram_cpu_bpmp_tx: shmem@4e000 { + compatible = "nvidia,tegra186-bpmp-shmem"; + reg = <0x0 0x4e000 0x0 0x1000>; + }; + + sysram_cpu_bpmp_rx: shmem@4f000 { + compatible = "nvidia,tegra186-bpmp-shmem"; + reg = <0x0 0x4f000 0x0 0x1000>; + }; + }; + + bpmp: bpmp { + compatible = "nvidia,tegra186-bpmp"; + mboxes = <&hsp HSP_MBOX_TYPE_DB HSP_DB_MASTER_BPMP>; + /* + * In theory, these references, and the configuration in the + * node these reference point at, are board-specific, since + * they depend on the BCT's memory carve-out setup, the + * firmware that's actually loaded onto the BPMP, etc. However, + * in practice, all boards are likely to use identical values. + */ + shmem = <&sysram_cpu_bpmp_tx &sysram_cpu_bpmp_rx>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + + bpmp_i2c: i2c { + compatible = "nvidia,tegra186-bpmp-i2c"; + nvidia,bpmp-bus-id = <5>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; }; diff --git a/arch/arm/dts/tegra210-p2371-2180.dts b/arch/arm/dts/tegra210-p2371-2180.dts index bf35497d83f7..608a42ab3d0f 100644 --- a/arch/arm/dts/tegra210-p2371-2180.dts +++ b/arch/arm/dts/tegra210-p2371-2180.dts @@ -12,8 +12,12 @@ aliases { i2c0 = "/i2c@0,7000d000"; + i2c2 = "/i2c@0,7000c400"; + i2c3 = "/i2c@0,7000c500"; + i2c5 = "/i2c@0,546c0c00"; sdhci0 = "/sdhci@0,700b0600"; - sdhci1 = "/sdhci@0,700b0000"; + sdhci1 = "/sdhci@0,700b0200"; + sdhci2 = "/sdhci@0,700b0000"; usb0 = "/usb@0,7d000000"; }; @@ -33,6 +37,11 @@ }; }; + i2c@0,546c0c00 { + status = "okay"; + clock-frequency = <400000>; + }; + padctl@0,7009f000 { pinctrl-0 = <&padctl_default>; pinctrl-names = "default"; @@ -79,11 +88,26 @@ bus-width = <4>; }; + sdhci@0,700b0200 { + status = "okay"; + bus-width = <4>; + }; + sdhci@0,700b0600 { status = "okay"; bus-width = <8>; }; + i2c@0,7000c400 { + status = "okay"; + clock-frequency = <400000>; + }; + + i2c@0,7000c500 { + status = "okay"; + clock-frequency = <400000>; + }; + i2c@0,7000d000 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm/dts/tegra210-p3450-porg.dts b/arch/arm/dts/tegra210-p3450-porg.dts new file mode 100644 index 000000000000..2b1fbad1ab40 --- /dev/null +++ b/arch/arm/dts/tegra210-p3450-porg.dts @@ -0,0 +1,132 @@ +/dts-v1/; + +#include "tegra210.dtsi" + +/ { + model = "NVIDIA P3450-Porg"; + compatible = "nvidia,p3450-porg", "nvidia,tegra210"; + + chosen { + stdout-path = &uarta; + }; + + aliases { + i2c0 = "/i2c@0,7000d000"; + i2c2 = "/i2c@0,7000c400"; + i2c3 = "/i2c@0,7000c500"; + i2c4 = "/i2c@0,7000c700"; + sdhci0 = "/sdhci@0,700b0600"; + sdhci1 = "/sdhci@0,700b0000"; + spi0 = "/spi@0,70410000"; + usb0 = "/usb@0,7d000000"; + }; + + memory { + reg = <0x0 0x80000000 0x0 0xc0000000>; + }; + + pcie-controller@0,01003000 { + status = "okay"; + + pci@1,0 { + status = "okay"; + }; + + pci@2,0 { + status = "okay"; + }; + }; + + padctl@0,7009f000 { + pinctrl-0 = <&padctl_default>; + pinctrl-names = "default"; + + padctl_default: pinmux { + xusb { + nvidia,lanes = "otg-1", "otg-2"; + nvidia,function = "xusb"; + nvidia,iddq = <0>; + }; + + usb3 { + nvidia,lanes = "pcie-5", "pcie-6"; + nvidia,function = "usb3"; + nvidia,iddq = <0>; + }; + + pcie-x1 { + nvidia,lanes = "pcie-0"; + nvidia,function = "pcie-x1"; + nvidia,iddq = <0>; + }; + + pcie-x4 { + nvidia,lanes = "pcie-1", "pcie-2", + "pcie-3", "pcie-4"; + nvidia,function = "pcie-x4"; + nvidia,iddq = <0>; + }; + + sata { + nvidia,lanes = "sata-0"; + nvidia,function = "sata"; + nvidia,iddq = <0>; + }; + }; + }; + + sdhci@0,700b0000 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + }; + + sdhci@0,700b0600 { + status = "okay"; + bus-width = <8>; + }; + + i2c@0,7000c400 { + status = "okay"; + clock-frequency = <400000>; + }; + + i2c@0,7000c500 { + status = "okay"; + clock-frequency = <400000>; + }; + + i2c@0,7000c700 { + status = "okay"; + clock-frequency = <400000>; + }; + + i2c@0,7000d000 { + status = "okay"; + clock-frequency = <400000>; + }; + + spi@0,70410000 { + status = "okay"; + spi-max-frequency = <80000000>; + }; + + usb@0,7d000000 { + status = "okay"; + dr_mode = "peripheral"; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; +}; diff --git a/arch/arm/dts/tegra210.dtsi b/arch/arm/dts/tegra210.dtsi index a8c2f1994ff7..fe019027f3ce 100644 --- a/arch/arm/dts/tegra210.dtsi +++ b/arch/arm/dts/tegra210.dtsi @@ -91,6 +91,27 @@ interrupt-parent = <&gic>; }; + i2c@0,546c0c00 { + compatible = "nvidia,tegra210-i2c-vi"; + reg = <0x0 0x546c0c00 0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA210_CLK_VI_I2C>, + <&tegra_car TEGRA210_CLK_I2CSLOW>, + <&tegra_car TEGRA210_CLK_HOST1X>; + clock-names = "div-clk", + "slow-clk", + "host1x-clk"; + resets = <&tegra_car TEGRA210_CLK_VI_I2C>, + <&tegra_car TEGRA210_CLK_I2CSLOW>, + <&tegra_car TEGRA210_CLK_HOST1X>; + reset-names = "i2c", + "i2c-slow", + "host1x"; + status = "disabled"; + }; + tegra_car: clock@0,60006000 { compatible = "nvidia,tegra210-car"; reg = <0x0 0x60006000 0x0 0x1000>; diff --git a/arch/arm/include/asm/arch-tegra/ap.h b/arch/arm/include/asm/arch-tegra/ap.h index 8c2586c6f548..1c67bd7e0506 100644 --- a/arch/arm/include/asm/arch-tegra/ap.h +++ b/arch/arm/include/asm/arch-tegra/ap.h @@ -28,6 +28,7 @@ #define NV_PA_BASE_SRAM 0x40000000 #define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100) +#define EXCEP_VECTOR_COP_RESET_VECTOR (NV_PA_EVP_BASE + 0x200) #define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0) #define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0) diff --git a/arch/arm/include/asm/arch-tegra/board.h b/arch/arm/include/asm/arch-tegra/board.h index 783bb3c0fa12..f5ffa3b7e6a2 100644 --- a/arch/arm/include/asm/arch-tegra/board.h +++ b/arch/arm/include/asm/arch-tegra/board.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010,2011 + * (C) Copyright 2010-2017 * NVIDIA Corporation * * SPDX-License-Identifier: GPL-2.0+ diff --git a/arch/arm/include/asm/arch-tegra/bpmp_abi.h b/arch/arm/include/asm/arch-tegra/bpmp_abi.h new file mode 100644 index 000000000000..7b6ad899cf6f --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/bpmp_abi.h @@ -0,0 +1,1591 @@ +/* + * Copyright (c) 2014-2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ABI_BPMP_ABI_H_ +#define _ABI_BPMP_ABI_H_ + +#ifdef LK +#include +#endif + +#ifndef __ABI_PACKED +#define __ABI_PACKED __attribute__((packed)) +#endif + +#ifdef NO_GCC_EXTENSIONS +#define EMPTY char empty; +#define EMPTY_ARRAY 1 +#else +#define EMPTY +#define EMPTY_ARRAY 0 +#endif + +#ifndef __UNION_ANON +#define __UNION_ANON +#endif +/** + * @file + */ + + +/** + * @defgroup MRQ MRQ Messages + * @brief Messages sent to/from BPMP via IPC + * @{ + * @defgroup MRQ_Format Message Format + * @defgroup MRQ_Codes Message Request (MRQ) Codes + * @defgroup MRQ_Payloads Message Payloads + * @defgroup Error_Codes Error Codes + * @} + */ + +/** + * @addtogroup MRQ_Format Message Format + * @{ + * The CPU requests the BPMP to perform a particular service by + * sending it an IVC frame containing a single MRQ message. An MRQ + * message consists of a @ref mrq_request followed by a payload whose + * format depends on mrq_request::mrq. + * + * The BPMP processes the data and replies with an IVC frame (on the + * same IVC channel) containing and MRQ response. An MRQ response + * consists of a @ref mrq_response followed by a payload whose format + * depends on the associated mrq_request::mrq. + * + * A well-defined subset of the MRQ messages that the CPU sends to the + * BPMP can lead to BPMP eventually sending an MRQ message to the + * CPU. For example, when the CPU uses an #MRQ_THERMAL message to set + * a thermal trip point, the BPMP may eventually send a single + * #MRQ_THERMAL message of its own to the CPU indicating that the trip + * point has been crossed. + * @} + */ + +/** + * @ingroup MRQ_Format + * @brief header for an MRQ message + * + * Provides the MRQ number for the MRQ message: #mrq. The remainder of + * the MRQ message is a payload (immediately following the + * mrq_request) whose format depends on mrq. + * + * @todo document the flags + */ +struct mrq_request { + /** @brief MRQ number of the request */ + uint32_t mrq; + /** @brief flags for the request */ + uint32_t flags; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Format + * @brief header for an MRQ response + * + * Provides an error code for the associated MRQ message. The + * remainder of the MRQ response is a payload (immediately following + * the mrq_response) whose format depends on the associated + * mrq_request::mrq + * + * @todo document the flags + */ +struct mrq_response { + /** @brief error code for the MRQ request itself */ + int32_t err; + /** @brief flags for the response */ + uint32_t flags; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Format + * Minimum needed size for an IPC message buffer + */ +#define MSG_MIN_SZ 128 +/** + * @ingroup MRQ_Format + * Minimum size guaranteed for data in an IPC message buffer + */ +#define MSG_DATA_MIN_SZ 120 + +/** + * @ingroup MRQ_Codes + * @name Legal MRQ codes + * These are the legal values for mrq_request::mrq + * @{ + */ + +#define MRQ_PING 0 +#define MRQ_QUERY_TAG 1 +#define MRQ_MODULE_LOAD 4 +#define MRQ_MODULE_UNLOAD 5 +#define MRQ_TRACE_MODIFY 7 +#define MRQ_WRITE_TRACE 8 +#define MRQ_THREADED_PING 9 +#define MRQ_MODULE_MAIL 11 +#define MRQ_DEBUGFS 19 +#define MRQ_RESET 20 +#define MRQ_I2C 21 +#define MRQ_CLK 22 +#define MRQ_QUERY_ABI 23 +#define MRQ_PG_READ_STATE 25 +#define MRQ_PG_UPDATE_STATE 26 +#define MRQ_THERMAL 27 +#define MRQ_CPU_VHINT 28 +#define MRQ_ABI_RATCHET 29 +#define MRQ_EMC_DVFS_LATENCY 31 +#define MRQ_TRACE_ITER 64 + +/** @} */ + +/** + * @ingroup MRQ_Codes + * @brief Maximum MRQ code to be sent by CPU software to + * BPMP. Subject to change in future + */ +#define MAX_CPU_MRQ_ID 64 + +/** + * @addtogroup MRQ_Payloads Message Payloads + * @{ + * @defgroup Ping + * @defgroup Query_Tag Query Tag + * @defgroup Module Loadable Modules + * @defgroup Trace + * @defgroup Debugfs + * @defgroup Reset + * @defgroup I2C + * @defgroup Clocks + * @defgroup ABI_info ABI Info + * @defgroup MC_Flush MC Flush + * @defgroup Powergating + * @defgroup Thermal + * @defgroup Vhint CPU Voltage hint + * @defgroup MRQ_Deprecated Deprecated MRQ messages + * @defgroup EMC + * @} + */ + + +/** + * @ingroup MRQ_Codes + * @def MRQ_PING + * @brief A simple ping + * + * * Platforms: All + * * Initiators: Any + * * Targets: Any + * * Request Payload: @ref mrq_ping_request + * * Response Payload: @ref mrq_ping_response + * + * @ingroup MRQ_Codes + * @def MRQ_THREADED_PING + * @brief A deeper ping + * + * * Platforms: All + * * Initiators: Any + * * Targets: BPMP + * * Request Payload: @ref mrq_ping_request + * * Response Payload: @ref mrq_ping_response + * + * Behavior is equivalent to a simple #MRQ_PING except that BPMP + * responds from a thread context (providing a slightly more robust + * sign of life). + * + */ + +/** + * @ingroup Ping + * @brief request with #MRQ_PING + * + * Used by the sender of an #MRQ_PING message to request a pong from + * recipient. The response from the recipient is computed based on + * #challenge. + */ +struct mrq_ping_request { +/** @brief arbitrarily chosen value */ + uint32_t challenge; +} __ABI_PACKED; + +/** + * @ingroup Ping + * @brief response to #MRQ_PING + * + * Sent in response to an #MRQ_PING message. #reply should be the + * mrq_ping_request challenge left shifted by 1 with the carry-bit + * dropped. + * + */ +struct mrq_ping_response { + /** @brief response to the MRQ_PING challege */ + uint32_t reply; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_QUERY_TAG + * @brief Query BPMP firmware's tag (i.e. version information) + * + * * Platforms: All + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_query_tag_request + * * Response Payload: N/A + * + */ + +/** + * @ingroup Query_Tag + * @brief request with #MRQ_QUERY_TAG + * + * Used by #MRQ_QUERY_TAG call to ask BPMP to fill in the memory + * pointed by #addr with BPMP firmware header. + * + * The sender is reponsible for ensuring that #addr is mapped in to + * the recipient's address map. + */ +struct mrq_query_tag_request { + /** @brief base address to store the firmware header */ + uint32_t addr; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_MODULE_LOAD + * @brief dynamically load a BPMP code module + * + * * Platforms: All + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_module_load_request + * * Response Payload: @ref mrq_module_load_response + * + * @note This MRQ is disabled on production systems + * + */ + +/** + * @ingroup Module + * @brief request with #MRQ_MODULE_LOAD + * + * Used by #MRQ_MODULE_LOAD calls to ask the recipient to dynamically + * load the code located at #phys_addr and having size #size + * bytes. #phys_addr is treated as a void pointer. + * + * The recipient copies the code from #phys_addr to locally allocated + * memory prior to responding to this message. + * + * @todo document the module header format + * + * The sender is responsible for ensuring that the code is mapped in + * the recipient's address map. + * + */ +struct mrq_module_load_request { + /** @brief base address of the code to load. Treated as (void *) */ + uint32_t phys_addr; /* (void *) */ + /** @brief size in bytes of code to load */ + uint32_t size; +} __ABI_PACKED; + +/** + * @ingroup Module + * @brief response to #MRQ_MODULE_LOAD + * + * @todo document mrq_response::err + */ +struct mrq_module_load_response { + /** @brief handle to the loaded module */ + uint32_t base; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_MODULE_UNLOAD + * @brief unload a previously loaded code module + * + * * Platforms: All + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_module_unload_request + * * Response Payload: N/A + * + * @note This MRQ is disabled on production systems + */ + +/** + * @ingroup Module + * @brief request with #MRQ_MODULE_UNLOAD + * + * Used by #MRQ_MODULE_UNLOAD calls to request that a previously loaded + * module be unloaded. + */ +struct mrq_module_unload_request { + /** @brief handle of the module to unload */ + uint32_t base; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_TRACE_MODIFY + * @brief modify the set of enabled trace events + * + * * Platforms: All + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_trace_modify_request + * * Response Payload: @ref mrq_trace_modify_response + * + * @note This MRQ is disabled on production systems + */ + +/** + * @ingroup Trace + * @brief request with #MRQ_TRACE_MODIFY + * + * Used by %MRQ_TRACE_MODIFY calls to enable or disable specify trace + * events. #set takes precedence for any bit set in both #set and + * #clr. + */ +struct mrq_trace_modify_request { + /** @brief bit mask of trace events to disable */ + uint32_t clr; + /** @brief bit mask of trace events to enable */ + uint32_t set; +} __ABI_PACKED; + +/** + * @ingroup Trace + * @brief response to #MRQ_TRACE_MODIFY + * + * Sent in repsonse to an #MRQ_TRACE_MODIFY message. #mask reflects the + * state of which events are enabled after the recipient acted on the + * message. + * + */ +struct mrq_trace_modify_response { + /** @brief bit mask of trace event enable states */ + uint32_t mask; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_WRITE_TRACE + * @brief Write trace data to a buffer + * + * * Platforms: All + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_write_trace_request + * * Response Payload: @ref mrq_write_trace_response + * + * mrq_response::err depends on the @ref mrq_write_trace_request field + * values. err is -#BPMP_EINVAL if size is zero or area is NULL or + * area is in an illegal range. A positive value for err indicates the + * number of bytes written to area. + * + * @note This MRQ is disabled on production systems + */ + +/** + * @ingroup Trace + * @brief request with #MRQ_WRITE_TRACE + * + * Used by MRQ_WRITE_TRACE calls to ask the recipient to copy trace + * data from the recipient's local buffer to the output buffer. #area + * is treated as a byte-aligned pointer in the recipient's address + * space. + * + * The sender is responsible for ensuring that the output + * buffer is mapped in the recipient's address map. The recipient is + * responsible for protecting its own code and data from accidental + * overwrites. + */ +struct mrq_write_trace_request { + /** @brief base address of output buffer */ + uint32_t area; + /** @brief size in bytes of the output buffer */ + uint32_t size; +} __ABI_PACKED; + +/** + * @ingroup Trace + * @brief response to #MRQ_WRITE_TRACE + * + * Once this response is sent, the respondent will not access the + * output buffer further. + */ +struct mrq_write_trace_response { + /** + * @brief flag whether more data remains in local buffer + * + * Value is 1 if the entire local trace buffer has been + * drained to the outputbuffer. Value is 0 otherwise. + */ + uint32_t eof; +} __ABI_PACKED; + +/** @private */ +struct mrq_threaded_ping_request { + uint32_t challenge; +} __ABI_PACKED; + +/** @private */ +struct mrq_threaded_ping_response { + uint32_t reply; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_MODULE_MAIL + * @brief send a message to a loadable module + * + * * Platforms: All + * * Initiators: Any + * * Targets: BPMP + * * Request Payload: @ref mrq_module_mail_request + * * Response Payload: @ref mrq_module_mail_response + * + * @note This MRQ is disabled on production systems + */ + +/** + * @ingroup Module + * @brief request with #MRQ_MODULE_MAIL + */ +struct mrq_module_mail_request { + /** @brief handle to the previously loaded module */ + uint32_t base; + /** @brief module-specific mail payload + * + * The length of data[ ] is unknown to the BPMP core firmware + * but it is limited to the size of an IPC message. + */ + uint8_t data[EMPTY_ARRAY]; +} __ABI_PACKED; + +/** + * @ingroup Module + * @brief response to #MRQ_MODULE_MAIL + */ +struct mrq_module_mail_response { + /** @brief module-specific mail payload + * + * The length of data[ ] is unknown to the BPMP core firmware + * but it is limited to the size of an IPC message. + */ + uint8_t data[EMPTY_ARRAY]; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_DEBUGFS + * @brief Interact with BPMP's debugfs file nodes + * + * * Platforms: T186 + * * Initiators: Any + * * Targets: BPMP + * * Request Payload: @ref mrq_debugfs_request + * * Response Payload: @ref mrq_debugfs_response + */ + +/** + * @addtogroup Debugfs + * @{ + * + * The BPMP firmware implements a pseudo-filesystem called + * debugfs. Any driver within the firmware may register with debugfs + * to expose an arbitrary set of "files" in the filesystem. When + * software on the CPU writes to a debugfs file, debugfs passes the + * written data to a callback provided by the driver. When software on + * the CPU reads a debugfs file, debugfs queries the driver for the + * data to return to the CPU. The intention of the debugfs filesystem + * is to provide information useful for debugging the system at + * runtime. + * + * @note The files exposed via debugfs are not part of the + * BPMP firmware's ABI. debugfs files may be added or removed in any + * given version of the firmware. Typically the semantics of a debugfs + * file are consistent from version to version but even that is not + * guaranteed. + * + * @} + */ +/** @ingroup Debugfs */ +enum mrq_debugfs_commands { + CMD_DEBUGFS_READ = 1, + CMD_DEBUGFS_WRITE = 2, + CMD_DEBUGFS_DUMPDIR = 3, + CMD_DEBUGFS_MAX +}; + +/** + * @ingroup Debugfs + * @brief parameters for CMD_DEBUGFS_READ/WRITE command + */ +struct cmd_debugfs_fileop_request { + /** @brief physical address pointing at filename */ + uint32_t fnameaddr; + /** @brief length in bytes of filename buffer */ + uint32_t fnamelen; + /** @brief physical address pointing to data buffer */ + uint32_t dataaddr; + /** @brief length in bytes of data buffer */ + uint32_t datalen; +} __ABI_PACKED; + +/** + * @ingroup Debugfs + * @brief parameters for CMD_DEBUGFS_READ/WRITE command + */ +struct cmd_debugfs_dumpdir_request { + /** @brief physical address pointing to data buffer */ + uint32_t dataaddr; + /** @brief length in bytes of data buffer */ + uint32_t datalen; +} __ABI_PACKED; + +/** + * @ingroup Debugfs + * @brief response data for CMD_DEBUGFS_READ/WRITE command + */ +struct cmd_debugfs_fileop_response { + /** @brief always 0 */ + uint32_t reserved; + /** @brief number of bytes read from or written to data buffer */ + uint32_t nbytes; +} __ABI_PACKED; + +/** + * @ingroup Debugfs + * @brief response data for CMD_DEBUGFS_DUMPDIR command + */ +struct cmd_debugfs_dumpdir_response { + /** @brief always 0 */ + uint32_t reserved; + /** @brief number of bytes read from or written to data buffer */ + uint32_t nbytes; +} __ABI_PACKED; + +/** + * @ingroup Debugfs + * @brief request with #MRQ_DEBUGFS. + * + * The sender of an MRQ_DEBUGFS message uses #cmd to specify a debugfs + * command to execute. Legal commands are the values of @ref + * mrq_debugfs_commands. Each command requires a specific additional + * payload of data. + * + * |command |payload| + * |-------------------|-------| + * |CMD_DEBUGFS_READ |fop | + * |CMD_DEBUGFS_WRITE |fop | + * |CMD_DEBUGFS_DUMPDIR|dumpdir| + */ +struct mrq_debugfs_request { + uint32_t cmd; + union { + struct cmd_debugfs_fileop_request fop; + struct cmd_debugfs_dumpdir_request dumpdir; + } __UNION_ANON; +} __ABI_PACKED; + +/** + * @ingroup Debugfs + */ +struct mrq_debugfs_response { + /** @brief always 0 */ + int32_t reserved; + union { + /** @brief response data for CMD_DEBUGFS_READ OR + * CMD_DEBUGFS_WRITE command + */ + struct cmd_debugfs_fileop_response fop; + /** @brief response data for CMD_DEBUGFS_DUMPDIR command */ + struct cmd_debugfs_dumpdir_response dumpdir; + } __UNION_ANON; +} __ABI_PACKED; + +/** + * @addtogroup Debugfs + * @{ + */ +#define DEBUGFS_S_ISDIR (1 << 9) +#define DEBUGFS_S_IRUSR (1 << 8) +#define DEBUGFS_S_IWUSR (1 << 7) +/** @} */ + + +/** + * @ingroup MRQ_Codes + * @def MRQ_RESET + * @brief reset an IP block + * + * * Platforms: T186 + * * Initiators: Any + * * Targets: BPMP + * * Request Payload: @ref mrq_reset_request + * * Response Payload: N/A + */ + +/** + * @ingroup Reset + */ +enum mrq_reset_commands { + CMD_RESET_ASSERT = 1, + CMD_RESET_DEASSERT = 2, + CMD_RESET_MODULE = 3, + CMD_RESET_MAX, /* not part of ABI and subject to change */ +}; + +/** + * @ingroup Reset + * @brief request with MRQ_RESET + * + * Used by the sender of an #MRQ_RESET message to request BPMP to + * assert or or deassert a given reset line. + */ +struct mrq_reset_request { + /** @brief reset action to perform (@enum mrq_reset_commands) */ + uint32_t cmd; + /** @brief id of the reset to affected */ + uint32_t reset_id; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_I2C + * @brief issue an i2c transaction + * + * * Platforms: T186 + * * Initiators: Any + * * Targets: BPMP + * * Request Payload: @ref mrq_i2c_request + * * Response Payload: @ref mrq_i2c_response + */ + +/** + * @addtogroup I2C + * @{ + */ +#define TEGRA_I2C_IPC_MAX_IN_BUF_SIZE (MSG_DATA_MIN_SZ - 12) +#define TEGRA_I2C_IPC_MAX_OUT_BUF_SIZE (MSG_DATA_MIN_SZ - 4) +/** @} */ + +/** + * @ingroup I2C + * @name Serial I2C flags + * Use these flags with serial_i2c_request::flags + * @{ + */ +#define SERIALI2C_TEN 0x0010 +#define SERIALI2C_RD 0x0001 +#define SERIALI2C_STOP 0x8000 +#define SERIALI2C_NOSTART 0x4000 +#define SERIALI2C_REV_DIR_ADDR 0x2000 +#define SERIALI2C_IGNORE_NAK 0x1000 +#define SERIALI2C_NO_RD_ACK 0x0800 +#define SERIALI2C_RECV_LEN 0x0400 +/** @} */ +/** @ingroup I2C */ +enum { + CMD_I2C_XFER = 1 +}; + +/** + * @ingroup I2C + * @brief serializable i2c request + * + * Instances of this structure are packed (little-endian) into + * cmd_i2c_xfer_request::data_buf. Each instance represents a single + * transaction (or a portion of a transaction with repeated starts) on + * an i2c bus. + * + * Because these structures are packed, some instances are likely to + * be misaligned. Additionally because #data is variable length, it is + * not possible to iterate through a serialized list of these + * structures without inspecting #len in each instance. It may be + * easier to serialize or deserialize cmd_i2c_xfer_request::data_buf + * manually rather than using this structure definition. +*/ +struct serial_i2c_request { + /** @brief I2C slave address */ + uint16_t addr; + /** @brief bitmask of SERIALI2C_ flags */ + uint16_t flags; + /** @brief length of I2C transaction in bytes */ + uint16_t len; + /** @brief for write transactions only, #len bytes of data */ + uint8_t data[]; +} __ABI_PACKED; + +/** + * @ingroup I2C + * @brief trigger one or more i2c transactions + */ +struct cmd_i2c_xfer_request { + /** @brief valid bus number from mach-t186/i2c-t186.h*/ + uint32_t bus_id; + + /** @brief count of valid bytes in #data_buf*/ + uint32_t data_size; + + /** @brief serialized packed instances of @ref serial_i2c_request*/ + uint8_t data_buf[TEGRA_I2C_IPC_MAX_IN_BUF_SIZE]; +} __ABI_PACKED; + +/** + * @ingroup I2C + * @brief container for data read from the i2c bus + * + * Processing an cmd_i2c_xfer_request::data_buf causes BPMP to execute + * zero or more I2C reads. The data read from the bus is serialized + * into #data_buf. + */ +struct cmd_i2c_xfer_response { + /** @brief count of valid bytes in #data_buf*/ + uint32_t data_size; + /** @brief i2c read data */ + uint8_t data_buf[TEGRA_I2C_IPC_MAX_OUT_BUF_SIZE]; +} __ABI_PACKED; + +/** + * @ingroup I2C + * @brief request with #MRQ_I2C + */ +struct mrq_i2c_request { + /** @brief always CMD_I2C_XFER (i.e. 1) */ + uint32_t cmd; + /** @brief parameters of the transfer request */ + struct cmd_i2c_xfer_request xfer; +} __ABI_PACKED; + +/** + * @ingroup I2C + * @brief response to #MRQ_I2C + */ +struct mrq_i2c_response { + struct cmd_i2c_xfer_response xfer; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_CLK + * + * * Platforms: T186 + * * Initiators: Any + * * Targets: BPMP + * * Request Payload: @ref mrq_clk_request + * * Response Payload: @ref mrq_clk_response + * @addtogroup Clocks + * @{ + */ + +/** + * @name MRQ_CLK sub-commands + * @{ + */ +enum { + CMD_CLK_GET_RATE = 1, + CMD_CLK_SET_RATE = 2, + CMD_CLK_ROUND_RATE = 3, + CMD_CLK_GET_PARENT = 4, + CMD_CLK_SET_PARENT = 5, + CMD_CLK_IS_ENABLED = 6, + CMD_CLK_ENABLE = 7, + CMD_CLK_DISABLE = 8, + CMD_CLK_GET_ALL_INFO = 14, + CMD_CLK_GET_MAX_CLK_ID = 15, + CMD_CLK_MAX, +}; +/** @} */ + +#define MRQ_CLK_NAME_MAXLEN 40 +#define MRQ_CLK_MAX_PARENTS 16 + +/** @private */ +struct cmd_clk_get_rate_request { + EMPTY +} __ABI_PACKED; + +struct cmd_clk_get_rate_response { + int64_t rate; +} __ABI_PACKED; + +struct cmd_clk_set_rate_request { + int32_t unused; + int64_t rate; +} __ABI_PACKED; + +struct cmd_clk_set_rate_response { + int64_t rate; +} __ABI_PACKED; + +struct cmd_clk_round_rate_request { + int32_t unused; + int64_t rate; +} __ABI_PACKED; + +struct cmd_clk_round_rate_response { + int64_t rate; +} __ABI_PACKED; + +/** @private */ +struct cmd_clk_get_parent_request { + EMPTY +} __ABI_PACKED; + +struct cmd_clk_get_parent_response { + uint32_t parent_id; +} __ABI_PACKED; + +struct cmd_clk_set_parent_request { + uint32_t parent_id; +} __ABI_PACKED; + +struct cmd_clk_set_parent_response { + uint32_t parent_id; +} __ABI_PACKED; + +/** @private */ +struct cmd_clk_is_enabled_request { + EMPTY +} __ABI_PACKED; + +struct cmd_clk_is_enabled_response { + int32_t state; +} __ABI_PACKED; + +/** @private */ +struct cmd_clk_enable_request { + EMPTY +} __ABI_PACKED; + +/** @private */ +struct cmd_clk_enable_response { + EMPTY +} __ABI_PACKED; + +/** @private */ +struct cmd_clk_disable_request { + EMPTY +} __ABI_PACKED; + +/** @private */ +struct cmd_clk_disable_response { + EMPTY +} __ABI_PACKED; + +/** @private */ +struct cmd_clk_get_all_info_request { + EMPTY +} __ABI_PACKED; + +struct cmd_clk_get_all_info_response { + uint32_t flags; + uint32_t parent; + uint32_t parents[MRQ_CLK_MAX_PARENTS]; + uint8_t num_parents; + uint8_t name[MRQ_CLK_NAME_MAXLEN]; +} __ABI_PACKED; + +/** @private */ +struct cmd_clk_get_max_clk_id_request { + EMPTY +} __ABI_PACKED; + +struct cmd_clk_get_max_clk_id_response { + uint32_t max_id; +} __ABI_PACKED; +/** @} */ + +/** + * @ingroup Clocks + * @brief request with #MRQ_CLK + * + * Used by the sender of an #MRQ_CLK message to control clocks. The + * clk_request is split into several sub-commands. Some sub-commands + * require no additional data. Others have a sub-command specific + * payload + * + * |sub-command |payload | + * |----------------------------|-----------------------| + * |CMD_CLK_GET_RATE |- | + * |CMD_CLK_SET_RATE |clk_set_rate | + * |CMD_CLK_ROUND_RATE |clk_round_rate | + * |CMD_CLK_GET_PARENT |- | + * |CMD_CLK_SET_PARENT |clk_set_parent | + * |CMD_CLK_IS_ENABLED |- | + * |CMD_CLK_ENABLE |- | + * |CMD_CLK_DISABLE |- | + * |CMD_CLK_GET_ALL_INFO |- | + * |CMD_CLK_GET_MAX_CLK_ID |- | + * + */ + +struct mrq_clk_request { + /** @brief sub-command and clock id concatenated to 32-bit word. + * - bits[31..24] is the sub-cmd. + * - bits[23..0] is the clock id + */ + uint32_t cmd_and_id; + + union { + /** @private */ + struct cmd_clk_get_rate_request clk_get_rate; + struct cmd_clk_set_rate_request clk_set_rate; + struct cmd_clk_round_rate_request clk_round_rate; + /** @private */ + struct cmd_clk_get_parent_request clk_get_parent; + struct cmd_clk_set_parent_request clk_set_parent; + /** @private */ + struct cmd_clk_enable_request clk_enable; + /** @private */ + struct cmd_clk_disable_request clk_disable; + /** @private */ + struct cmd_clk_is_enabled_request clk_is_enabled; + /** @private */ + struct cmd_clk_get_all_info_request clk_get_all_info; + /** @private */ + struct cmd_clk_get_max_clk_id_request clk_get_max_clk_id; + } __UNION_ANON; +} __ABI_PACKED; + +/** + * @ingroup Clocks + * @brief response to MRQ_CLK + * + * Each sub-command supported by @ref mrq_clk_request may return + * sub-command-specific data. Some do and some do not as indicated in + * the following table + * + * |sub-command |payload | + * |----------------------------|------------------------| + * |CMD_CLK_GET_RATE |clk_get_rate | + * |CMD_CLK_SET_RATE |clk_set_rate | + * |CMD_CLK_ROUND_RATE |clk_round_rate | + * |CMD_CLK_GET_PARENT |clk_get_parent | + * |CMD_CLK_SET_PARENT |clk_set_parent | + * |CMD_CLK_IS_ENABLED |clk_is_enabled | + * |CMD_CLK_ENABLE |- | + * |CMD_CLK_DISABLE |- | + * |CMD_CLK_GET_ALL_INFO |clk_get_all_info | + * |CMD_CLK_GET_MAX_CLK_ID |clk_get_max_id | + * + */ + +struct mrq_clk_response { + union { + struct cmd_clk_get_rate_response clk_get_rate; + struct cmd_clk_set_rate_response clk_set_rate; + struct cmd_clk_round_rate_response clk_round_rate; + struct cmd_clk_get_parent_response clk_get_parent; + struct cmd_clk_set_parent_response clk_set_parent; + /** @private */ + struct cmd_clk_enable_response clk_enable; + /** @private */ + struct cmd_clk_disable_response clk_disable; + struct cmd_clk_is_enabled_response clk_is_enabled; + struct cmd_clk_get_all_info_response clk_get_all_info; + struct cmd_clk_get_max_clk_id_response clk_get_max_clk_id; + } __UNION_ANON; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_QUERY_ABI + * @brief check if an MRQ is implemented + * + * * Platforms: All + * * Initiators: Any + * * Targets: Any + * * Request Payload: @ref mrq_query_abi_request + * * Response Payload: @ref mrq_query_abi_response + */ + +/** + * @ingroup ABI_info + * @brief request with MRQ_QUERY_ABI + * + * Used by #MRQ_QUERY_ABI call to check if MRQ code #mrq is supported + * by the recipient. + */ +struct mrq_query_abi_request { + /** @brief MRQ code to query */ + uint32_t mrq; +} __ABI_PACKED; + +/** + * @ingroup ABI_info + * @brief response to MRQ_QUERY_ABI + */ +struct mrq_query_abi_response { + /** @brief 0 if queried MRQ is supported. Else, -#BPMP_ENODEV */ + int32_t status; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_PG_READ_STATE + * @brief read the power-gating state of a partition + * + * * Platforms: T186 + * * Initiators: Any + * * Targets: BPMP + * * Request Payload: @ref mrq_pg_read_state_request + * * Response Payload: @ref mrq_pg_read_state_response + * @addtogroup Powergating + * @{ + */ + +/** + * @brief request with #MRQ_PG_READ_STATE + * + * Used by MRQ_PG_READ_STATE call to read the current state of a + * partition. + */ +struct mrq_pg_read_state_request { + /** @brief ID of partition */ + uint32_t partition_id; +} __ABI_PACKED; + +/** + * @brief response to MRQ_PG_READ_STATE + * @todo define possible errors. + */ +struct mrq_pg_read_state_response { + /** @brief read as don't care */ + uint32_t sram_state; + /** @brief state of power partition + * * 0 : off + * * 1 : on + */ + uint32_t logic_state; +} __ABI_PACKED; + +/** @} */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_PG_UPDATE_STATE + * @brief modify the power-gating state of a partition + * + * * Platforms: T186 + * * Initiators: Any + * * Targets: BPMP + * * Request Payload: @ref mrq_pg_update_state_request + * * Response Payload: N/A + * @addtogroup Powergating + * @{ + */ + +/** + * @brief request with mrq_pg_update_state_request + * + * Used by #MRQ_PG_UPDATE_STATE call to request BPMP to change the + * state of a power partition #partition_id. + */ +struct mrq_pg_update_state_request { + /** @brief ID of partition */ + uint32_t partition_id; + /** @brief secondary control of power partition + * @details Ignored by many versions of the BPMP + * firmware. For maximum compatibility, set the value + * according to @logic_state + * * 0x1: power ON partition (@ref logic_state == 0x3) + * * 0x3: power OFF partition (@ref logic_state == 0x1) + */ + uint32_t sram_state; + /** @brief controls state of power partition, legal values are + * * 0x1 : power OFF partition + * * 0x3 : power ON partition + */ + uint32_t logic_state; + /** @brief change state of clocks of the power partition, legal values + * * 0x0 : do not change clock state + * * 0x1 : disable partition clocks (only applicable when + * @ref logic_state == 0x1) + * * 0x3 : enable partition clocks (only applicable when + * @ref logic_state == 0x3) + */ + uint32_t clock_state; +} __ABI_PACKED; +/** @} */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_THERMAL + * @brief interact with BPMP thermal framework + * + * * Platforms: T186 + * * Initiators: Any + * * Targets: Any + * * Request Payload: TODO + * * Response Payload: TODO + * + * @addtogroup Thermal + * + * The BPMP firmware includes a thermal framework. Drivers within the + * bpmp firmware register with the framework to provide thermal + * zones. Each thermal zone corresponds to an entity whose temperature + * can be measured. The framework also has a notion of trip points. A + * trip point consists of a thermal zone id, a temperature, and a + * callback routine. The framework invokes the callback when the zone + * hits the indicated temperature. The BPMP firmware uses this thermal + * framework interally to implement various temperature-dependent + * functions. + * + * Software on the CPU can use #MRQ_THERMAL (with payload @ref + * mrq_thermal_host_to_bpmp_request) to interact with the BPMP thermal + * framework. The CPU must It can query the number of supported zones, + * query zone temperatures, and set trip points. + * + * When a trip point set by the CPU gets crossed, BPMP firmware issues + * an IPC to the CPU having mrq_request::mrq = #MRQ_THERMAL and a + * payload of @ref mrq_thermal_bpmp_to_host_request. + * @{ + */ +enum mrq_thermal_host_to_bpmp_cmd { + /** + * @brief Check whether the BPMP driver supports the specified + * request type. + * + * Host needs to supply request parameters. + * + * mrq_response::err is 0 if the specified request is + * supported and -#BPMP_ENODEV otherwise. + */ + CMD_THERMAL_QUERY_ABI = 0, + + /** + * @brief Get the current temperature of the specified zone. + * + * Host needs to supply request parameters. + * + * mrq_response::err is + * * 0: Temperature query succeeded. + * * -#BPMP_EINVAL: Invalid request parameters. + * * -#BPMP_ENOENT: No driver registered for thermal zone.. + * * -#BPMP_EFAULT: Problem reading temperature measurement. + */ + CMD_THERMAL_GET_TEMP = 1, + + /** + * @brief Enable or disable and set the lower and upper + * thermal limits for a thermal trip point. Each zone has + * one trip point. + * + * Host needs to supply request parameters. Once the + * temperature hits a trip point, the BPMP will send a message + * to the CPU having MRQ=MRQ_THERMAL and + * type=CMD_THERMAL_HOST_TRIP_REACHED + * + * mrq_response::err is + * * 0: Trip successfully set. + * * -#BPMP_EINVAL: Invalid request parameters. + * * -#BPMP_ENOENT: No driver registered for thermal zone. + * * -#BPMP_EFAULT: Problem setting trip point. + */ + CMD_THERMAL_SET_TRIP = 2, + + /** + * @brief Get the number of supported thermal zones. + * + * No request parameters required. + * + * mrq_response::err is always 0, indicating success. + */ + CMD_THERMAL_GET_NUM_ZONES = 3, + + /** @brief: number of supported host-to-bpmp commands. May + * increase in future + */ + CMD_THERMAL_HOST_TO_BPMP_NUM +}; + +enum mrq_thermal_bpmp_to_host_cmd { + /** + * @brief Indication that the temperature for a zone has + * exceeded the range indicated in the thermal trip point + * for the zone. + * + * BPMP needs to supply request parameters. Host only needs to + * acknowledge. + */ + CMD_THERMAL_HOST_TRIP_REACHED = 100, + + /** @brief: number of supported bpmp-to-host commands. May + * increase in future + */ + CMD_THERMAL_BPMP_TO_HOST_NUM +}; + +/* + * Host->BPMP request data for request type CMD_THERMAL_QUERY_ABI + * + * zone: Request type for which to check existence. + */ +struct cmd_thermal_query_abi_request { + uint32_t type; +} __ABI_PACKED; + +/* + * Host->BPMP request data for request type CMD_THERMAL_GET_TEMP + * + * zone: Number of thermal zone. + */ +struct cmd_thermal_get_temp_request { + uint32_t zone; +} __ABI_PACKED; + +/* + * BPMP->Host reply data for request CMD_THERMAL_GET_TEMP + * + * error: 0 if request succeeded. + * -BPMP_EINVAL if request parameters were invalid. + * -BPMP_ENOENT if no driver was registered for the specified thermal zone. + * -BPMP_EFAULT for other thermal zone driver errors. + * temp: Current temperature in millicelsius. + */ +struct cmd_thermal_get_temp_response { + int32_t temp; +} __ABI_PACKED; + +/* + * Host->BPMP request data for request type CMD_THERMAL_SET_TRIP + * + * zone: Number of thermal zone. + * low: Temperature of lower trip point in millicelsius + * high: Temperature of upper trip point in millicelsius + * enabled: 1 to enable trip point, 0 to disable trip point + */ +struct cmd_thermal_set_trip_request { + uint32_t zone; + int32_t low; + int32_t high; + uint32_t enabled; +} __ABI_PACKED; + +/* + * BPMP->Host request data for request type CMD_THERMAL_HOST_TRIP_REACHED + * + * zone: Number of thermal zone where trip point was reached. + */ +struct cmd_thermal_host_trip_reached_request { + uint32_t zone; +} __ABI_PACKED; + +/* + * BPMP->Host reply data for request type CMD_THERMAL_GET_NUM_ZONES + * + * num: Number of supported thermal zones. The thermal zones are indexed + * starting from zero. + */ +struct cmd_thermal_get_num_zones_response { + uint32_t num; +} __ABI_PACKED; + +/* + * Host->BPMP request data. + * + * Reply type is union mrq_thermal_bpmp_to_host_response. + * + * type: Type of request. Values listed in enum mrq_thermal_type. + * data: Request type specific parameters. + */ +struct mrq_thermal_host_to_bpmp_request { + uint32_t type; + union { + struct cmd_thermal_query_abi_request query_abi; + struct cmd_thermal_get_temp_request get_temp; + struct cmd_thermal_set_trip_request set_trip; + } __UNION_ANON; +} __ABI_PACKED; + +/* + * BPMP->Host request data. + * + * type: Type of request. Values listed in enum mrq_thermal_type. + * data: Request type specific parameters. + */ +struct mrq_thermal_bpmp_to_host_request { + uint32_t type; + union { + struct cmd_thermal_host_trip_reached_request host_trip_reached; + } __UNION_ANON; +} __ABI_PACKED; + +/* + * Data in reply to a Host->BPMP request. + */ +union mrq_thermal_bpmp_to_host_response { + struct cmd_thermal_get_temp_response get_temp; + struct cmd_thermal_get_num_zones_response get_num_zones; +} __ABI_PACKED; +/** @} */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_CPU_VHINT + * @brief Query CPU voltage hint data + * + * * Platforms: T186 + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_cpu_vhint_request + * * Response Payload: N/A + * + * @addtogroup Vhint CPU Voltage hint + * @{ + */ + +/** + * @brief request with #MRQ_CPU_VHINT + * + * Used by #MRQ_CPU_VHINT call by CCPLEX to retrieve voltage hint data + * from BPMP to memory space pointed by #addr. CCPLEX is responsible + * to allocate sizeof(cpu_vhint_data) sized block of memory and + * appropriately map it for BPMP before sending the request. + */ +struct mrq_cpu_vhint_request { + /** @brief IOVA address for the #cpu_vhint_data */ + uint32_t addr; /* struct cpu_vhint_data * */ + /** @brief ID of the cluster whose data is requested */ + uint32_t cluster_id; /* enum cluster_id */ +} __ABI_PACKED; + +/** + * @brief description of the CPU v/f relation + * + * Used by #MRQ_CPU_VHINT call to carry data pointed by #addr of + * struct mrq_cpu_vhint_request + */ +struct cpu_vhint_data { + uint32_t ref_clk_hz; /**< reference frequency in Hz */ + uint16_t pdiv; /**< post divider value */ + uint16_t mdiv; /**< input divider value */ + uint16_t ndiv_max; /**< fMAX expressed with max NDIV value */ + /** table of ndiv values as a function of vINDEX (voltage index) */ + uint16_t ndiv[80]; + /** minimum allowed NDIV value */ + uint16_t ndiv_min; + /** minimum allowed voltage hint value (as in vINDEX) */ + uint16_t vfloor; + /** maximum allowed voltage hint value (as in vINDEX) */ + uint16_t vceil; + /** post-multiplier for vindex value */ + uint16_t vindex_mult; + /** post-divider for vindex value */ + uint16_t vindex_div; + /** reserved for future use */ + uint16_t reserved[328]; +} __ABI_PACKED; + +/** @} */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_ABI_RATCHET + * @brief ABI ratchet value query + * + * * Platforms: T186 + * * Initiators: Any + * * Targets: BPMP + * * Request Payload: @ref mrq_abi_ratchet_request + * * Response Payload: @ref mrq_abi_ratchet_response + * @addtogroup ABI_info + * @{ + */ + +/** + * @brief an ABI compatibility mechanism + * + * BPMP_ABI_RATCHET_VALUE may increase for various reasons in a future + * revision of this header file. + * 1. That future revision deprecates some MRQ + * 2. That future revision introduces a breaking change to an existing + * MRQ or + * 3. A bug is discovered in an existing implementation of the BPMP-FW + * (or possibly one of its clients) which warrants deprecating that + * implementation. + */ +#define BPMP_ABI_RATCHET_VALUE 3 + +/** + * @brief request with #MRQ_ABI_RATCHET. + * + * #ratchet should be #BPMP_ABI_RATCHET_VALUE from the ABI header + * against which the requester was compiled. + * + * If ratchet is less than BPMP's #BPMP_ABI_RATCHET_VALUE, BPMP may + * reply with mrq_response::err = -#BPMP_ERANGE to indicate that + * BPMP-FW cannot interoperate correctly with the requester. Requester + * should cease further communication with BPMP. + * + * Otherwise, err shall be 0. + */ +struct mrq_abi_ratchet_request { + /** @brief requester's ratchet value */ + uint16_t ratchet; +}; + +/** + * @brief response to #MRQ_ABI_RATCHET + * + * #ratchet shall be #BPMP_ABI_RATCHET_VALUE from the ABI header + * against which BPMP firwmare was compiled. + * + * If #ratchet is less than the requester's #BPMP_ABI_RATCHET_VALUE, + * the requster must either interoperate with BPMP according to an ABI + * header version with BPMP_ABI_RATCHET_VALUE = ratchet or cease + * communication with BPMP. + * + * If mrq_response::err is 0 and ratchet is greater than or equal to the + * requester's BPMP_ABI_RATCHET_VALUE, the requester should continue + * normal operation. + */ +struct mrq_abi_ratchet_response { + /** @brief BPMP's ratchet value */ + uint16_t ratchet; +}; +/** @} */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_EMC_DVFS_LATENCY + * @brief query frequency dependent EMC DVFS latency + * + * * Platforms: T186 + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: N/A + * * Response Payload: @ref mrq_emc_dvfs_latency_response + * @addtogroup EMC + * @{ + */ + +/** + * @brief used by @ref mrq_emc_dvfs_latency_response + */ +struct emc_dvfs_latency { + /** @brief EMC frequency in kHz */ + uint32_t freq; + /** @brief EMC DVFS latency in nanoseconds */ + uint32_t latency; +} __ABI_PACKED; + +#define EMC_DVFS_LATENCY_MAX_SIZE 14 +/** + * @brief response to #MRQ_EMC_DVFS_LATENCY + */ +struct mrq_emc_dvfs_latency_response { + /** @brief the number valid entries in #pairs */ + uint32_t num_pairs; + /** @brief EMC information */ + struct emc_dvfs_latency pairs[EMC_DVFS_LATENCY_MAX_SIZE]; +} __ABI_PACKED; + +/** @} */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_TRACE_ITER + * @brief manage the trace iterator + * + * * Platforms: All + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: N/A + * * Response Payload: @ref mrq_trace_iter_request + * @addtogroup Trace + * @{ + */ +enum { + /** @brief (re)start the tracing now. Ignore older events */ + TRACE_ITER_INIT = 0, + /** @brief clobber all events in the trace buffer */ + TRACE_ITER_CLEAN = 1 +}; + +/** + * @brief request with #MRQ_TRACE_ITER + */ +struct mrq_trace_iter_request { + /** @brief TRACE_ITER_INIT or TRACE_ITER_CLEAN */ + uint32_t cmd; +} __ABI_PACKED; + +/** @} */ + +/* + * 4. Enumerations + */ + +/* + * 4.1 CPU enumerations + * + * See + * + * 4.2 CPU Cluster enumerations + * + * See + * + * 4.3 System low power state enumerations + * + * See + */ + +/* + * 4.4 Clock enumerations + * + * For clock enumerations, see + */ + +/* + * 4.5 Reset enumerations + * + * For reset enumerations, see + */ + +/* + * 4.6 Thermal sensor enumerations + * + * For thermal sensor enumerations, see + */ + +/** + * @defgroup Error_Codes + * Negative values for mrq_response::err generally indicate some + * error. The ABI defines the following error codes. Negating these + * defines is an exercise left to the user. + * @{ + */ +/** @brief No such file or directory */ +#define BPMP_ENOENT 2 +/** @brief No MRQ handler */ +#define BPMP_ENOHANDLER 3 +/** @brief I/O error */ +#define BPMP_EIO 5 +/** @brief Bad sub-MRQ command */ +#define BPMP_EBADCMD 6 +/** @brief Not enough memory */ +#define BPMP_ENOMEM 12 +/** @brief Permission denied */ +#define BPMP_EACCES 13 +/** @brief Bad address */ +#define BPMP_EFAULT 14 +/** @brief No such device */ +#define BPMP_ENODEV 19 +/** @brief Argument is a directory */ +#define BPMP_EISDIR 21 +/** @brief Invalid argument */ +#define BPMP_EINVAL 22 +/** @brief Timeout during operation */ +#define BPMP_ETIMEDOUT 23 +/** @brief Out of range */ +#define BPMP_ERANGE 34 +/** @} */ +/** @} */ +#endif diff --git a/arch/arm/include/asm/arch-tegra/cboot.h b/arch/arm/include/asm/arch-tegra/cboot.h new file mode 100644 index 000000000000..02ae3dff6ad7 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/cboot.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA_CBOOT_H_ +#define _TEGRA_CBOOT_H_ + +extern unsigned long cboot_boot_x0; + +int set_ethaddr_from_cboot(const void *fdt); + +#endif diff --git a/arch/arm/include/asm/arch-tegra/ivc.h b/arch/arm/include/asm/arch-tegra/ivc.h new file mode 100644 index 000000000000..7f2287ae2802 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/ivc.h @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ASM_ARCH_TEGRA_IVC_H +#define _ASM_ARCH_TEGRA_IVC_H + +#include + +/* + * Tegra IVC is a communication protocol that transfers fixed-size frames + * bi-directionally and in-order between the local CPU and some remote entity. + * Communication is via a statically sized and allocated buffer in shared + * memory and a notification mechanism. + * + * This API handles all aspects of the shared memory buffer's metadata, and + * leaves all aspects of the frame content to the calling code; frames + * typically contain some higher-level protocol. The notification mechanism is + * also handled externally to this API, since it can vary from instance to + * instance. + * + * The client model is to first find some free (for TX) or filled (for RX) + * frame, process that frame's memory buffer (fill or read it), and then + * inform the protocol that the frame has been filled/read, i.e. advance the + * write/read pointer. If the channel is full, there may be no available frames + * to fill/read. In this case, client code may either poll for an available + * frame, or wait for the remote entity to send a notification to the local + * CPU. + */ + +/** + * struct tegra_ivc - In-memory shared memory layout. + * + * This is described in detail in ivc.c. + */ +struct tegra_ivc_channel_header; + +/** + * struct tegra_ivc - Software state of an IVC channel. + * + * This state is internal to the IVC code and should not be accessed directly + * by clients. It is public solely so clients can allocate storage for the + * structure. + */ +struct tegra_ivc { + /** + * rx_channel - Pointer to the shared memory region used to receive + * messages from the remote entity. + */ + struct tegra_ivc_channel_header *rx_channel; + /** + * tx_channel - Pointer to the shared memory region used to send + * messages to the remote entity. + */ + struct tegra_ivc_channel_header *tx_channel; + /** + * r_pos - The position in list of frames in rx_channel that we are + * reading from. + */ + uint32_t r_pos; + /** + * w_pos - The position in list of frames in tx_channel that we are + * writing to. + */ + uint32_t w_pos; + /** + * nframes - The number of frames allocated (in each direction) in + * shared memory. + */ + uint32_t nframes; + /** + * frame_size - The size of each frame in shared memory. + */ + uint32_t frame_size; + /** + * notify - Function to call to notify the remote processor of a + * change in channel state. + */ + void (*notify)(struct tegra_ivc *); +}; + +/** + * tegra_ivc_read_get_next_frame - Locate the next frame to receive. + * + * Locate the next frame to be received/processed, return the address of the + * frame, and do not remove it from the queue. Repeated calls to this function + * will return the same address until tegra_ivc_read_advance() is called. + * + * @ivc The IVC channel. + * @frame Pointer to be filled with the address of the frame to receive. + * + * @return 0 if a frame is available, else a negative error code. + */ +int tegra_ivc_read_get_next_frame(struct tegra_ivc *ivc, void **frame); + +/** + * tegra_ivc_read_advance - Advance the read queue. + * + * Inform the protocol and remote entity that the frame returned by + * tegra_ivc_read_get_next_frame() has been processed. The remote end may then + * re-use it to transmit further data. Subsequent to this function returning, + * tegra_ivc_read_get_next_frame() will return a different frame. + * + * @ivc The IVC channel. + * + * @return 0 if OK, else a negative error code. + */ +int tegra_ivc_read_advance(struct tegra_ivc *ivc); + +/** + * tegra_ivc_write_get_next_frame - Locate the next frame to fill for transmit. + * + * Locate the next frame to be filled for transmit, return the address of the + * frame, and do not add it to the queue. Repeated calls to this function + * will return the same address until tegra_ivc_read_advance() is called. + * + * @ivc The IVC channel. + * @frame Pointer to be filled with the address of the frame to fill. + * + * @return 0 if a frame is available, else a negative error code. + */ +int tegra_ivc_write_get_next_frame(struct tegra_ivc *ivc, void **frame); + +/** + * tegra_ivc_write_advance - Advance the write queue. + * + * Inform the protocol and remote entity that the frame returned by + * tegra_ivc_write_get_next_frame() has been filled and should be transmitted. + * The remote end may then read data from it. Subsequent to this function + * returning, tegra_ivc_write_get_next_frame() will return a different frame. + * + * @ivc The IVC channel. + * + * @return 0 if OK, else a negative error code. + */ +int tegra_ivc_write_advance(struct tegra_ivc *ivc); + +/** + * tegra_ivc_channel_notified - handle internal messages + * + * This function must be called following every notification. + * + * @ivc The IVC channel. + * + * @return 0 if the channel is ready for communication, or -EAGAIN if a + * channel reset is in progress. + */ +int tegra_ivc_channel_notified(struct tegra_ivc *ivc); + +/** + * tegra_ivc_channel_reset - initiates a reset of the shared memory state + * + * This function must be called after a channel is initialized but before it + * is used for communication. The channel will be ready for use when a + * subsequent call to notify the remote of the channel reset indicates the + * reset operation is complete. + * + * @ivc The IVC channel. + */ +void tegra_ivc_channel_reset(struct tegra_ivc *ivc); + +/** + * tegra_ivc_init - Initialize a channel's software state. + * + * @ivc The IVC channel. + * @rx_base Address of the the RX shared memory buffer. + * @tx_base Address of the the TX shared memory buffer. + * @nframes Number of frames in each shared memory buffer. + * @frame_size Size of each frame. + * + * @return 0 if OK, else a negative error code. + */ +int tegra_ivc_init(struct tegra_ivc *ivc, ulong rx_base, ulong tx_base, + uint32_t nframes, uint32_t frame_size, + void (*notify)(struct tegra_ivc *)); + +#endif diff --git a/arch/arm/include/asm/arch-tegra/pmc.h b/arch/arm/include/asm/arch-tegra/pmc.h index 66c08797656c..2b96f68700ed 100644 --- a/arch/arm/include/asm/arch-tegra/pmc.h +++ b/arch/arm/include/asm/arch-tegra/pmc.h @@ -1,6 +1,5 @@ /* - * (C) Copyright 2010-2015 - * NVIDIA Corporation + * Copyright (c) 2010-2018, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -389,4 +388,11 @@ struct pmc_ctlr { /* APBDEV_PMC_CNTRL2_0 0x440 */ #define HOLD_CKE_LOW_EN (1 << 12) +/* PMC read/write functions */ +u32 tegra_pmc_readl(unsigned long offset); +void tegra_pmc_writel(u32 value, unsigned long offset); + +/* PMC_CNTRL_0 MAIN_RST*/ +#define MAIN_RST_BIT 4 + #endif /* PMC_H */ diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h index 3add1b3c09bb..4c00dfc1f522 100644 --- a/arch/arm/include/asm/arch-tegra/tegra.h +++ b/arch/arm/include/asm/arch-tegra/tegra.h @@ -31,7 +31,11 @@ #define NV_PA_SLINK5_BASE (NV_PA_APB_MISC_BASE + 0xDC00) #define NV_PA_SLINK6_BASE (NV_PA_APB_MISC_BASE + 0xDE00) #define TEGRA_DVC_BASE (NV_PA_APB_MISC_BASE + 0xD000) +#if defined(CONFIG_TEGRA186) +#define NV_PA_PMC_BASE 0x0C360000 +#else #define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400) +#endif #define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400) #define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800) #if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \ diff --git a/arch/arm/include/asm/arch-tegra/tegra_i2c.h b/arch/arm/include/asm/arch-tegra/tegra_i2c.h index 341df74d777d..9cd78875b383 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_i2c.h +++ b/arch/arm/include/asm/arch-tegra/tegra_i2c.h @@ -1,7 +1,7 @@ /* * NVIDIA Tegra I2C controller * - * Copyright 2010-2011 NVIDIA Corporation + * Copyright 2010-2016 NVIDIA Corporation * * SPDX-License-Identifier: GPL-2.0 */ @@ -92,6 +92,57 @@ struct i2c_ctlr { u32 clk_div; /* 6C: I2C_I2C_CLOCK_DIVISOR */ }; +/* + * Same basic reg structure as normal Tegra I2C, except based @ 0xC00, + * and each register is 16 byte-granular, i.e. CNFG is at 0xC00, but + * CMD_ADDR0 is at 0xC10 (0x04 << 2), STATUS is at 0xC70 (0x1C << 2), etc. + */ +struct i2c_vi_control { + u32 tx_fifo; /* 140 */ + u32 reserved0[3]; + u32 rx_fifo; /* 150 */ + u32 reserved1[3]; + u32 packet_status; /* 160 */ + u32 reserved2[3]; + u32 fifo_control; /* 170 */ + u32 reserved3[3]; + u32 fifo_status; /* 180 */ + u32 reserved4[3]; + u32 int_mask; /* 190 */ + u32 reserved5[3]; + u32 int_status; /* 1A0 */ +}; + +struct i2c_vi_ctlr { + u32 cnfg; /* 00: I2C_I2C_CNFG */ + u32 reserved0[3]; + u32 cmd_addr0; /* 10: I2C_I2C_CMD_ADDR0 */ + u32 reserved1[3]; + u32 cmd_addr1; /* 20: I2C_I2C_CMD_DATA1 */ + u32 reserved2[3]; + u32 cmd_data1; /* 30: I2C_I2C_CMD_DATA2 */ + u32 reserved3[3]; + u32 cmd_data2; /* 40: DVC_I2C_CMD_DATA2 */ + u32 reserved4[11]; /* 50 - 6C */ + u32 status; /* 70: I2C_I2C_STATUS */ + u32 reserved5[3]; + u32 sl_cnfg; /* 80: I2C_I2C_SL_CNFG */ + u32 reserved6[3]; + u32 sl_rcvd; /* 90: I2C_I2C_SL_RCVD */ + u32 reserved7[3]; + u32 sl_status; /* A0: I2C_I2C_SL_STATUS */ + u32 reserved8[3]; + u32 sl_addr1; /* B0: I2C_I2C_SL_ADDR1 */ + u32 reserved9[3]; + u32 sl_addr2; /* C0: I2C_I2C_SL_ADDR2 */ + u32 reserved10[11]; /* D0 - EC: */ + u32 sl_delay_count; /* F0: I2C_I2C_SL_DELAY_COUNT */ + u32 reserved11[19]; /* 100 - 11c: */ + struct i2c_vi_control control; /* 140 ~ 1A0 */ + u32 reserved12[3]; + u32 clk_div; /* 1B0: I2C_I2C_CLOCK_DIVISOR */ +}; + /* bit fields definitions for IO Packet Header 1 format */ #define PKT_HDR1_PROTOCOL_SHIFT 4 #define PKT_HDR1_PROTOCOL_MASK (0xf << PKT_HDR1_PROTOCOL_SHIFT) diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h index 75e56c4ea786..a9f762c107c0 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h +++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h @@ -1,7 +1,7 @@ /* * (C) Copyright 2009 SAMSUNG Electronics * Minkyu Kang - * Portions Copyright (C) 2011-2012 NVIDIA Corporation + * Portions Copyright (C) 2011-2012,2019 NVIDIA Corporation * * SPDX-License-Identifier: GPL-2.0+ */ @@ -9,6 +9,9 @@ #ifndef __TEGRA_MMC_H_ #define __TEGRA_MMC_H_ +#include +#include +#include #include #include @@ -50,7 +53,7 @@ struct tegra_mmc { unsigned char admaerr; /* offset 54h */ unsigned char res4[3]; /* RESERVED, offset 55h-57h */ unsigned long admaaddr; /* offset 58h-5Fh */ - unsigned char res5[0xa0]; /* RESERVED, offset 60h-FBh */ + unsigned char res5[0x9c]; /* RESERVED, offset 60h-FBh */ unsigned short slotintstatus; /* offset FCh */ unsigned short hcver; /* HOST Version */ unsigned int venclkctl; /* _VENDOR_CLOCK_CNTRL_0, 100h */ @@ -123,18 +126,33 @@ struct tegra_mmc { #define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1) -/* SDMMC1/3 settings from section 24.6 of T30 TRM */ +/* SDMMC1/3 settings from SDMMCx Initialization Sequence of TRM */ #define MEMCOMP_PADCTRL_VREF 7 -#define AUTO_CAL_ENABLED (1 << 29) +#define AUTO_CAL_ENABLE (1 << 29) +#define AUTO_CAL_ACTIVE (1 << 31) +#define AUTO_CAL_START (1 << 31) +#if defined(CONFIG_TEGRA210) +#define AUTO_CAL_PD_OFFSET (0x7D << 8) +#define AUTO_CAL_PU_OFFSET (0 << 0) +#define IO_TRIM_BYPASS_MASK (1 << 2) +#define TRIM_VAL_SHIFT 24 +#define TRIM_VAL_MASK (0x1F << TRIM_VAL_SHIFT) +#define TAP_VAL_SHIFT 16 +#define TAP_VAL_MASK (0xFF << TAP_VAL_SHIFT) +#else #define AUTO_CAL_PD_OFFSET (0x70 << 8) #define AUTO_CAL_PU_OFFSET (0x62 << 0) +#endif struct mmc_host { struct tegra_mmc *reg; int id; /* device id/number, 0-3 */ int enabled; /* 1 to enable, 0 to disable */ int width; /* Bus Width, 1, 4 or 8 */ -#ifndef CONFIG_TEGRA186 +#ifdef CONFIG_TEGRA186 + struct reset_ctl reset_ctl; + struct clk clk; +#else enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */ #endif struct gpio_desc cd_gpio; /* Change Detect GPIO */ diff --git a/arch/arm/include/asm/arch-tegra/xusb-padctl.h b/arch/arm/include/asm/arch-tegra/xusb-padctl.h index b4b4c8ba4d10..cad65054b26e 100644 --- a/arch/arm/include/asm/arch-tegra/xusb-padctl.h +++ b/arch/arm/include/asm/arch-tegra/xusb-padctl.h @@ -16,6 +16,7 @@ struct tegra_xusb_phy; struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type); void tegra_xusb_padctl_init(const void *fdt); +void tegra_xusb_padctl_exit(void); int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy); int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy); int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy); diff --git a/arch/arm/include/asm/boot0-linux-kernel-header.h b/arch/arm/include/asm/boot0-linux-kernel-header.h new file mode 100644 index 000000000000..ca28780daac5 --- /dev/null +++ b/arch/arm/include/asm/boot0-linux-kernel-header.h @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2017 NVIDIA Corporation + * + * Derived from Linux kernel v4.14 files: + * + * arch/arm64/include/asm/assembler.h: + * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S + * Copyright (C) 1996-2000 Russell King + * Copyright (C) 2012 ARM Ltd. + * + * arch/arm64/kernel/head.S: + * Based on arch/arm/kernel/head.S + * Copyright (C) 1994-2002 Russell King + * Copyright (C) 2003-2012 ARM Ltd. + * Authors: Catalin Marinas + * Will Deacon + * + * arch/arm64/kernel/image.h: + * Copyright (C) 2014 ARM Ltd. + * + * SPDX-License-Identifier: GPL-2.0 + */ + + /* + * Emit a 64-bit absolute little endian symbol reference in a way that + * ensures that it will be resolved at build time, even when building a + * PIE binary. This requires cooperation from the linker script, which + * must emit the lo32/hi32 halves individually. + */ + .macro le64sym, sym + .long \sym\()_lo32 + .long \sym\()_hi32 + .endm + +.globl _start +_start: + /* + * DO NOT MODIFY. Image header expected by Linux boot-loaders. + */ + b reset /* branch to kernel start, magic */ + .long 0 /* reserved */ + le64sym _kernel_offset_le /* Image load offset from start of RAM, little-endian */ + le64sym _kernel_size_le /* Effective size of kernel image, little-endian */ + le64sym _kernel_flags_le /* Informative flags, little-endian */ + .quad 0 /* reserved */ + .quad 0 /* reserved */ + .quad 0 /* reserved */ + .ascii "ARM\x64" /* Magic number */ + .long 0 /* reserved */ diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h index 435fc4521c2e..21ca0ce0fa5e 100644 --- a/arch/arm/include/asm/config.h +++ b/arch/arm/include/asm/config.h @@ -12,7 +12,6 @@ #ifdef CONFIG_ARM64 #define CONFIG_PHYS_64BIT -#define CONFIG_STATIC_RELA #endif #if defined(CONFIG_LS102XA) || \ diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 2bdc0bec824e..87e8bb9743f1 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -97,7 +97,9 @@ void __asm_invalidate_dcache_all(void); void __asm_flush_dcache_range(u64 start, u64 end); void __asm_invalidate_tlb_all(void); void __asm_invalidate_icache_all(void); -int __asm_flush_l3_cache(void); +int __asm_invalidate_l3_dcache(void); +int __asm_flush_l3_dcache(void); +int __asm_invalidate_l3_icache(void); void __asm_switch_ttbr(u64 new_ttbr); void armv8_switch_to_el2(void); diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 0838d89907b9..568510957ae0 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -44,7 +44,8 @@ static ulong get_sp(void) void arch_lmb_reserve(struct lmb *lmb) { - ulong sp; + ulong sp, bank_end; + int bank; /* * Booting a (Linux) kernel image @@ -60,8 +61,16 @@ void arch_lmb_reserve(struct lmb *lmb) /* adjust sp by 4K to be safe */ sp -= 4096; - lmb_reserve(lmb, sp, - gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size - sp); + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + if (sp < gd->bd->bi_dram[bank].start) + continue; + bank_end = gd->bd->bi_dram[bank].start + + gd->bd->bi_dram[bank].size; + if (sp >= bank_end) + continue; + lmb_reserve(lmb, sp, bank_end - sp); + break; + } } /** diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index cad22c7b41fe..5a3d8fdf42ba 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -71,6 +71,9 @@ ENTRY(_main) */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) ldr x0, =(CONFIG_SPL_STACK) +#elif defined(CONFIG_SYS_INIT_SP_BSS_OFFSET) + adr x0, __bss_start + add x0, x0, #CONFIG_SYS_INIT_SP_BSS_OFFSET #else ldr x0, =(CONFIG_SYS_INIT_SP_ADDR) #endif @@ -97,6 +100,14 @@ ENTRY(_main) sub x18, x18, #GD_SIZE /* new GD is below bd */ adr lr, relocation_return +#if CONFIG_POSITION_INDEPENDENT + /* Add in link-vs-runtime offset */ + adr x0, _start /* x0 <- Runtime value of _start */ + ldr x9, _TEXT_BASE /* x9 <- Linked value of _start */ + sub x9, x9, x0 /* x9 <- Run-vs-link offset */ + add lr, lr, x9 +#endif + /* Add in link-vs-relocation offset */ ldr x9, [x18, #GD_RELOC_OFF] /* x9 <- gd->reloc_off */ add lr, lr, x9 /* new return address after relocation */ ldr x0, [x18, #GD_RELOCADDR] /* x0 <- gd->relocaddr */ diff --git a/arch/arm/lib/relocate_64.S b/arch/arm/lib/relocate_64.S index 5c51cae8ab0b..1eb0909f0506 100644 --- a/arch/arm/lib/relocate_64.S +++ b/arch/arm/lib/relocate_64.S @@ -26,11 +26,24 @@ ENTRY(relocate_code) /* * Copy u-boot from flash to RAM */ - ldr x1, =__image_copy_start /* x1 <- SRC &__image_copy_start */ - subs x9, x0, x1 /* x9 <- relocation offset */ + adr x1, __image_copy_start /* x1 <- Run &__image_copy_start */ + subs x9, x0, x1 /* x8 <- Run to copy offset */ b.eq relocate_done /* skip relocation */ - ldr x2, =__image_copy_end /* x2 <- SRC &__image_copy_end */ + /* + * Don't ldr x1, __image_copy_start here, since if the code is already + * running at an address other than it was linked to, that instruction + * will load the relocated value of __image_copy_start. To + * correctly apply relocations, we need to know the linked value. + * + * Linked &__image_copy_start, which we know was at + * CONFIG_SYS_TEXT_BASE, which is stored in _TEXT_BASE, as a non- + * relocated value, since it isn't a symbol reference. + */ + ldr x1, _TEXT_BASE /* x1 <- Linked &__image_copy_start */ + subs x9, x0, x1 /* x9 <- Link to copy offset */ + adr x1, __image_copy_start /* x1 <- Run &__image_copy_start */ + adr x2, __image_copy_end /* x2 <- Run &__image_copy_end */ copy_loop: ldp x10, x11, [x1], #16 /* copy from source address [x1] */ stp x10, x11, [x0], #16 /* copy to target address [x0] */ @@ -41,8 +54,8 @@ copy_loop: /* * Fix .rela.dyn relocations */ - ldr x2, =__rel_dyn_start /* x2 <- SRC &__rel_dyn_start */ - ldr x3, =__rel_dyn_end /* x3 <- SRC &__rel_dyn_end */ + adr x2, __rel_dyn_start /* x2 <- Run &__rel_dyn_start */ + adr x3, __rel_dyn_end /* x3 <- Run &__rel_dyn_end */ fixloop: ldp x0, x1, [x2], #16 /* (x0,x1) <- (SRC location, fixup) */ ldr x4, [x2], #8 /* x4 <- addend */ diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index f4affa5512bc..8817c982a207 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -1,5 +1,13 @@ if TEGRA +config TEGRA_IVC + bool "Tegra IVC protocol" + help + IVC (Inter-VM Communication) protocol is a Tegra-specific IPC + (Inter Processor Communication) framework. Within the context of + U-Boot, it is typically used for communication between the main CPU + and various auxiliary processors. + config TEGRA_COMMON bool "Tegra common options" select DM @@ -27,8 +35,14 @@ config TEGRA_ARMV7_COMMON config TEGRA_ARMV8_COMMON bool "Tegra 64-bit common options" select ARM64 + select LINUX_KERNEL_IMAGE_HEADER select TEGRA_COMMON +if TEGRA_ARMV8_COMMON +config LNX_KRNL_IMG_TEXT_OFFSET_BASE + default 0x80000000 +endif + choice prompt "Tegra SoC select" optional @@ -56,10 +70,17 @@ config TEGRA210 config TEGRA186 bool "Tegra186 family" + select CLK select DM_MAILBOX + select DM_RESET + select MISC + select TEGRA186_BPMP + select TEGRA186_CLOCK select TEGRA186_GPIO + select TEGRA186_RESET select TEGRA_ARMV8_COMMON select TEGRA_HSP + select TEGRA_IVC endchoice diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 12ee1cd7495b..987619ebe3a3 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2010-2015 Nvidia Corporation. +# Copyright (c) 2010-2018, NVIDIA CORPORATION. All rights reserved. # # (C) Copyright 2000-2008 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -11,27 +11,29 @@ ifndef CONFIG_TEGRA186 ifdef CONFIG_SPL_BUILD obj-y += spl.o obj-y += cpu.o -else -obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o endif -obj-$(CONFIG_ARM64) += arm64-mmu.o obj-y += ap.o obj-y += board.o board2.o obj-y += cache.o obj-y += clock.o -obj-y += lowlevel_init.o obj-y += pinmux-common.o obj-y += powergate.o obj-y += xusb-padctl-dummy.o -obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o -obj-$(CONFIG_TEGRA_GPU) += gpu.o -obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o +endif +obj-$(CONFIG_ARM64) += arm64-mmu.o +obj-y += dt-edit.o +obj-y += dt-setup.o +obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o +obj-$(CONFIG_TEGRA_GPU) += gpu.o +obj-$(CONFIG_TEGRA_IVC) += ivc.o ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o obj-$(CONFIG_ARMV7_PSCI) += psci.o endif -endif +obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o +obj-y += pmc.o obj-$(CONFIG_TEGRA20) += tegra20/ obj-$(CONFIG_TEGRA30) += tegra30/ diff --git a/arch/arm/mach-tegra/arm64-mmu.c b/arch/arm/mach-tegra/arm64-mmu.c index 501c4f00c4e0..5b0bd98b4969 100644 --- a/arch/arm/mach-tegra/arm64-mmu.c +++ b/arch/arm/mach-tegra/arm64-mmu.c @@ -12,7 +12,8 @@ #include #include -static struct mm_region tegra_mem_map[] = { +/* size: IO + NR_DRAM_BANKS + terminator */ +struct mm_region tegra_mem_map[1 + CONFIG_NR_DRAM_BANKS + 1] = { { .base = 0x0UL, .size = 0x80000000UL, @@ -21,7 +22,7 @@ static struct mm_region tegra_mem_map[] = { PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { .base = 0x80000000UL, - .size = 0xff80000000UL, + .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index 3d1d26d13d13..cf108151361f 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2015 + * (C) Copyright 2010-2017 * NVIDIA Corporation * * SPDX-License-Identifier: GPL-2.0+ @@ -36,7 +36,7 @@ enum { static bool from_spl __attribute__ ((section(".data"))); -#ifndef CONFIG_SPL_BUILD +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TEGRA210) void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) { from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL; @@ -67,6 +67,7 @@ bool tegra_cpu_is_non_secure(void) } #endif +#if !defined(CONFIG_ARM64) /* Read the RAM size directly from the memory controller */ static phys_size_t query_sdram_size(void) { @@ -89,11 +90,10 @@ static phys_size_t query_sdram_size(void) if (emem_cfg >= 4096) { size_bytes = U32_MAX & ~(0x1000 - 1); } else -#endif +#endif /* !CONFIG_PHYS_64BIT */ { /* RAM size EMC is programmed to. */ size_bytes = (phys_size_t)emem_cfg * 1024 * 1024; -#ifndef CONFIG_ARM64 /* * If all RAM fits within 32-bits, it can be accessed without * LPAE, so go test the RAM size. Otherwise, we can't access @@ -104,15 +104,14 @@ static phys_size_t query_sdram_size(void) if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024)) size_bytes = get_ram_size((void *)PHYS_SDRAM_1, size_bytes); -#endif } -#endif +#endif /* !T20 */ #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) /* External memory limited to 2047 MB due to IROM/HI-VEC */ if (size_bytes == SZ_2G) size_bytes -= SZ_1M; -#endif +#endif /* T30/T114 */ return size_bytes; } @@ -123,6 +122,7 @@ int dram_init(void) gd->ram_size = query_sdram_size(); return 0; } +#endif /* CONFIG_ARM64 */ static int uart_configs[] = { #if defined(CONFIG_TEGRA20) diff --git a/arch/arm/mach-tegra/board186.c b/arch/arm/mach-tegra/board186.c index f4b6152a7937..d8c7e991f7cc 100644 --- a/arch/arm/mach-tegra/board186.c +++ b/arch/arm/mach-tegra/board186.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. + * Copyright (c) 2016-2019, NVIDIA CORPORATION. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -11,31 +11,29 @@ DECLARE_GLOBAL_DATA_PTR; -int dram_init(void) +int board_early_init_f(void) { - gd->ram_size = (1.5 * 1024 * 1024 * 1024); return 0; } -int board_early_init_f(void) +__weak int tegra_board_init(void) { return 0; } int board_init(void) { - return 0; + return tegra_board_init(); } -int board_late_init(void) +__weak int cboot_init_late(void) { return 0; } -void dram_init_banksize(void) +int board_late_init(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + return cboot_init_late(); } void pad_init_mmc(struct mmc_host *host) @@ -49,7 +47,35 @@ int board_mmc_init(bd_t *bd) return 0; } -int ft_system_setup(void *blob, bd_t *bd) +/* + * Attempt to use /chosen/nvidia,ether-mac in the cboot DTB to U-Boot's + * ethaddr environment variable if possible. + */ +int set_ethaddr_from_cboot(const void *fdt) { + int ret, node, len; + const u32 *prop; + + /* Already a valid address in the environment? If so, keep it */ + if (getenv("ethaddr")) + return 0; + + node = fdt_path_offset(fdt, "/chosen"); + if (node < 0) { + printf("Can't find /chosen node in cboot DTB\n"); + return node; + } + prop = fdt_getprop(fdt, node, "nvidia,ether-mac", &len); + if (!prop) { + printf("Can't find nvidia,ether-mac property in cboot DTB\n"); + return -ENOENT; + } + + ret = setenv("ethaddr", (void *)prop); + if (ret) { + printf("Failed to set ethaddr from cboot DTB: %d\n", ret); + return ret; + } + return 0; } diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 141d6e1cb555..0fff4539f676 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -1,10 +1,9 @@ /* - * (C) Copyright 2010,2011 + * (C) Copyright 2010,2011,2015,2017,2019 * NVIDIA Corporation * * SPDX-License-Identifier: GPL-2.0+ */ - #include #include #include @@ -41,6 +40,9 @@ #include #include #include "emc.h" +#ifdef CONFIG_TEGRA210 +#include "tegra210/cboot.h" +#endif DECLARE_GLOBAL_DATA_PTR; @@ -181,6 +183,12 @@ int board_init(void) return nvidia_board_init(); } +void board_cleanup_before_linux(void) +{ + /* power down UPHY PLL */ + tegra_xusb_padctl_exit(); +} + #ifdef CONFIG_BOARD_EARLY_INIT_F static void __gpio_early_init(void) { @@ -204,6 +212,31 @@ int board_early_init_f(void) #endif arch_timer_init(); +#if defined(CONFIG_DISABLE_SDMMC1_EARLY) + /* + * Turn off (reset/disable) SDMMC1 on Porg here, before GPIO INIT. + * We do this because earlier bootloaders have enabled power to + * SDMMC1 on Porg/Nano, and toggling power-gpio (PZ3) in + * pinmux_init() results in power being back-driven into the + * SD-card and SDMMC1 HW, which is 'bad' as per HW. + * + * From the HW team: "LDO2 from the PMIC has already been set for 3.3v in + * nvtboot/CBoot on Porg (for SD-card boot). So when U-Boot's GPIO_INIT + * table sets PZ3 to OUT0 as per the pinmux spreadsheet, it turns off + * the loadswitch. When PZ3 is 0 and not driving, essentially the SD card + * voltage turns off. Since the SDCard voltage is no longer there, the + * SDMMC CLK/DAT lines are backdriving into what essentially is a powered- + * off SDCard, that's why the voltage drops from 3.3V to 1.6V-ish" + * + * Note that this can probably be removed when we change over to storing + * all BL components on QSPI on Porg/Nano, and U-Boot then becomes the + * first one to turn on SDMMC1 power. Another fix would be to have CBoot + * disable power/gate SDMMC1 off before handing off to U-Boot/kernel. + */ + reset_set_enable(PERIPH_ID_SDMMC1, 1); + clock_set_enable(PERIPH_ID_SDMMC1, 0); +#endif /* CONFIG_DISABLE_SDMMC1_EARLY */ + pinmux_init(); board_init_uart_f(); @@ -226,6 +259,9 @@ int board_late_init(void) } #endif start_cpu_fan(); +#if defined(CONFIG_TEGRA210) + cboot_init_late(); +#endif return 0; } @@ -251,12 +287,14 @@ int board_mmc_init(bd_t *bd) void pad_init_mmc(struct mmc_host *host) { -#if defined(CONFIG_TEGRA30) +#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210) enum periph_id id = host->mmc_id; u32 val; + u16 clk_con; + int timeout; - debug("%s: sdmmc address = %08x, id = %d\n", __func__, - (unsigned int)host->reg, id); + debug("%s: sdmmc address = %p, id = %d\n", __func__, + host->reg, id); /* Set the pad drive strength for SDMMC1 or 3 only */ if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) { @@ -269,15 +307,72 @@ void pad_init_mmc(struct mmc_host *host) val &= 0xFFFFFFF0; val |= MEMCOMP_PADCTRL_VREF; writel(val, &host->reg->sdmemcmppadctl); + debug("%s: SD_MEM_COMP_PAD_CTL = 0x%08X\n", __func__, val); + + /* Disable SD Clock Enable before running auto-cal as per TRM */ + clk_con = readw(&host->reg->clkcon); + debug("%s: CLOCK_CONTROL = 0x%04X\n", __func__, clk_con); + clk_con &= ~TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE; + writew(clk_con, &host->reg->clkcon); val = readl(&host->reg->autocalcfg); val &= 0xFFFF0000; - val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED; + val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET; writel(val, &host->reg->autocalcfg); -#endif /* T30 */ + val |= AUTO_CAL_START | AUTO_CAL_ENABLE; + writel(val, &host->reg->autocalcfg); + debug("%s: AUTO_CAL_CFG = 0x%08X\n", __func__, val); + udelay(1); + + timeout = 100; /* 10 mSec max (100*100uS) */ + do { + val = readl(&host->reg->autocalsts); + udelay(100); + } while ((val & AUTO_CAL_ACTIVE) && --timeout); + val = readl(&host->reg->autocalsts); + debug("%s: Final AUTO_CAL_STATUS = 0x%08X, timeout = %d\n", + __func__, val, timeout); + + /* Re-enable SD Clock Enable when auto-cal is done */ + clk_con |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE; + writew(clk_con, &host->reg->clkcon); + clk_con = readw(&host->reg->clkcon); + debug("%s: final CLOCK_CONTROL = 0x%04X\n", __func__, clk_con); + + if (timeout == 0) { + printf("%s: Warning: Autocal timed out!\n", __func__); + /* TBD: Set CFG2TMC_SDMMC1_PAD_CAL_DRV* regs here */ + } + +#if defined(CONFIG_TEGRA210) + u32 tap_value, trim_value; + + /* Set tap/trim values for SDMMC1/3 @ <48MHz here */ + val = readl(&host->reg->venspictl); /* aka VENDOR_SYS_SW_CNTL */ + val &= IO_TRIM_BYPASS_MASK; + if (id == PERIPH_ID_SDMMC1) { + tap_value = 4; /* default */ + if (val) + tap_value = 3; + trim_value = 2; + } else { /* SDMMC3 */ + tap_value = 3; + trim_value = 3; + } + + val = readl(&host->reg->venclkctl); + val &= ~TRIM_VAL_MASK; + val |= (trim_value << TRIM_VAL_SHIFT); + val &= ~TAP_VAL_MASK; + val |= (tap_value << TAP_VAL_SHIFT); + writel(val, &host->reg->venclkctl); + debug("%s: VENDOR_CLOCK_CNTRL = 0x%08X\n", __func__, val); +#endif /* T210 */ +#endif /* T30/T210 */ } #endif /* MMC */ +#ifndef CONFIG_TEGRA210 /* * In some SW environments, a memory carve-out exists to house a secure * monitor, a trusted OS, and/or various statically allocated media buffers. @@ -397,29 +492,4 @@ ulong board_get_usable_ram_top(ulong total_size) { return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g(); } - -/* - * This function is called right before the kernel is booted. "blob" is the - * device tree that will be passed to the kernel. - */ -int ft_system_setup(void *blob, bd_t *bd) -{ - const char *gpu_compats[] = { -#if defined(CONFIG_TEGRA124) - "nvidia,gk20a", #endif -#if defined(CONFIG_TEGRA210) - "nvidia,gm20b", -#endif - }; - int i, ret; - - /* Enable GPU node if GPU setup has been performed */ - for (i = 0; i < ARRAY_SIZE(gpu_compats); i++) { - ret = tegra_gpu_enable_node(blob, gpu_compats[i]); - if (ret) - return ret; - } - - return 0; -} diff --git a/arch/arm/mach-tegra/cboot_board.c b/arch/arm/mach-tegra/cboot_board.c new file mode 100644 index 000000000000..44b71d064db4 --- /dev/null +++ b/arch/arm/mach-tegra/cboot_board.c @@ -0,0 +1,379 @@ +/* + * Copyright (c) 2016-2019, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +char *strstrip(char *s) +{ + size_t size; + char *end; + + size = strlen(s); + + if (!size) + return s; + + end = s + size - 1; + while (end >= s && isblank(*end)) + end--; + *(end + 1) = '\0'; + + while (*s && isblank(*s)) + s++; + + return s; +} + +/* + * The following few functions run late during the boot process and dynamically + * calculate the load address of various binaries. To keep track of multiple + * allocations, some writable list of RAM banks must be used. tegra_mem_map[] + * is used for this purpose to avoid making yet another copy of the list of RAM + * banks. This is safe because tegra_mem_map[] is only used once during very + * early boot to create U-Boot's page tables, long before this code runs. If + * this assumption becomes invalid later, we can just fix the code to copy the + * list of RAM banks into some private data structure before running. + */ + +extern struct mm_region tegra_mem_map[]; + +static char *gen_varname(const char *var, const char *ext) +{ + size_t len_var = strlen(var); + size_t len_ext = strlen(ext); + size_t len = len_var + len_ext + 1; + char *varext = malloc(len); + + if (!varext) + return 0; + strcpy(varext, var); + strcpy(varext + len_var, ext); + return varext; +} + +static void mark_ram_allocated(int bank, u64 allocated_start, u64 allocated_end) +{ + u64 bank_start = tegra_mem_map[bank].base; + u64 bank_size = tegra_mem_map[bank].size; + u64 bank_end = bank_start + bank_size; + bool keep_front = allocated_start != bank_start; + bool keep_tail = allocated_end != bank_end; + + if (keep_front && keep_tail) { + /* + * There are CONFIG_NR_DRAM_BANKS DRAM entries in the array, + * starting at index 1 (index 0 is MMIO). So, we are at DRAM + * entry "bank" not "bank - 1" as for a typical 0-base array. + * The number of remaining DRAM entries is therefore + * "CONFIG_NR_DRAM_BANKS - bank". We want to duplicate the + * current entry and shift up the remaining entries, dropping + * the last one. Thus, we must copy one fewer entry than the + * number remaining. + */ + memmove(&tegra_mem_map[bank + 1], &tegra_mem_map[bank], + CONFIG_NR_DRAM_BANKS - bank - 1); + tegra_mem_map[bank].size = allocated_start - bank_start; + bank++; + tegra_mem_map[bank].base = allocated_end; + tegra_mem_map[bank].size = bank_end - allocated_end; + } else if (keep_front) { + tegra_mem_map[bank].size = allocated_start - bank_start; + } else if (keep_tail) { + tegra_mem_map[bank].base = allocated_end; + tegra_mem_map[bank].size = bank_end - allocated_end; + } else { + /* + * We could move all subsequent banks down in the array but + * that's not necessary for subsequent allocations to work, so + * we skip doing so. + */ + tegra_mem_map[bank].size = 0; + } +} + +static void reserve_ram(u64 start, u64 size) +{ + int bank; + u64 end = start + size; + + for (bank = 1; bank <= CONFIG_NR_DRAM_BANKS; bank++) { + u64 bank_start = tegra_mem_map[bank].base; + u64 bank_size = tegra_mem_map[bank].size; + u64 bank_end = bank_start + bank_size; + + if (end <= bank_start || start > bank_end) + continue; + mark_ram_allocated(bank, start, end); + break; + } +} + +static u64 alloc_ram(u64 size, u64 align, u64 offset) +{ + int bank; + + for (bank = 1; bank <= CONFIG_NR_DRAM_BANKS; bank++) { + u64 bank_start = tegra_mem_map[bank].base; + u64 bank_size = tegra_mem_map[bank].size; + u64 bank_end = bank_start + bank_size; + u64 allocated = ROUND(bank_start, align) + offset; + u64 allocated_end = allocated + size; + + if (allocated_end > bank_end) + continue; + mark_ram_allocated(bank, allocated, allocated_end); + return allocated; + } + return 0; +} + +static void set_calculated_aliases(char *aliases, u64 address) +{ + char *tmp, *alias; + int err; + + aliases = strdup(aliases); + if (!aliases) { + error("strdup(aliases) failed"); + return; + } + + tmp = aliases; + while (true) { + alias = strsep(&tmp, " "); + if (!alias) + break; + debug("%s: alias: %s\n", __func__, alias); + err = setenv_hex(alias, address); + if (err) + error("Could not set %s\n", alias); + } + + free(aliases); +} + +static void set_calculated_env_var(const char *var) +{ + char *var_size; + char *var_align; + char *var_offset; + char *var_aliases; + u64 size; + u64 align; + u64 offset; + char *aliases; + u64 address; + int err; + + var_size = gen_varname(var, "_size"); + if (!var_size) + return; + var_align = gen_varname(var, "_align"); + if (!var_align) + goto out_free_var_size; + var_offset = gen_varname(var, "_offset"); + if (!var_offset) + goto out_free_var_align; + var_aliases = gen_varname(var, "_aliases"); + if (!var_aliases) + goto out_free_var_offset; + + size = getenv_hex(var_size, 0); + if (!size) { + error("%s not set or zero\n", var_size); + goto out_free_var_aliases; + } + align = getenv_hex(var_align, 1); + /* Handle extant variables, but with a value of 0 */ + if (!align) + align = 1; + offset = getenv_hex(var_offset, 0); + aliases = getenv(var_aliases); + + debug("%s: Calc var %s; size=%llx, align=%llx, offset=%llx\n", + __func__, var, size, align, offset); + if (aliases) + debug("%s: Aliases: %s\n", __func__, aliases); + + address = alloc_ram(size, align, offset); + if (!address) { + error("Could not allocate %s\n", var); + goto out_free_var_aliases; + } + debug("%s: Address %llx\n", __func__, address); + + err = setenv_hex(var, address); + if (err) + error("Could not set %s\n", var); + if (aliases) + set_calculated_aliases(aliases, address); + +out_free_var_aliases: + free(var_aliases); +out_free_var_offset: + free(var_offset); +out_free_var_align: + free(var_align); +out_free_var_size: + free(var_size); +} + +#ifdef DEBUG +static void dump_ram_banks(void) +{ + int bank; + + for (bank = 1; bank <= CONFIG_NR_DRAM_BANKS; bank++) { + u64 bank_start = tegra_mem_map[bank].base; + u64 bank_size = tegra_mem_map[bank].size; + u64 bank_end = bank_start + bank_size; + + if (!bank_size) + continue; + printf("%d: %010llx..%010llx (+%010llx)\n", bank - 1, + bank_start, bank_end, bank_size); + } +} +#endif + +static void set_calculated_env_vars(void) +{ + char *vars, *tmp, *var; + +#ifdef DEBUG + printf("RAM banks before any calculated env. var.s:\n"); + dump_ram_banks(); +#endif + + reserve_ram(cboot_boot_x0, fdt_totalsize(cboot_boot_x0)); + +#ifdef DEBUG + printf("RAM after reserving cboot DTB:\n"); + dump_ram_banks(); +#endif + + vars = getenv("calculated_vars"); + if (!vars) { + debug("%s: No env var calculated_vars\n", __func__); + return; + } + + vars = strdup(vars); + if (!vars) { + error("strdup(calculated_vars) failed"); + return; + } + + tmp = vars; + while (true) { + var = strsep(&tmp, " "); + if (!var) + break; + debug("%s: var: %s\n", __func__, var); + set_calculated_env_var(var); +#ifdef DEBUG + printf("RAM banks affter allocating %s:\n", var); + dump_ram_banks(); +#endif + } + + free(vars); +} + +static int set_fdt_addr(void) +{ + int ret; + + ret = setenv_hex("fdt_addr", cboot_boot_x0); + if (ret) { + printf("Failed to set fdt_addr to point at DTB: %d\n", ret); + goto fail; + } + + ret = setenv_hex("fdt_copy_src_addr", cboot_boot_x0); + if (ret) { + printf("Failed to set fdt_copy_src_addr to point at DTB: %d\n", + ret); + goto fail; + } + ret = 0; +fail: + return ret; +} + +__weak int set_ethaddr_from_cboot(const void *fdt) +{ + return 0; +} + +static int set_cbootargs(void) +{ + const void *cboot_blob = (void *)cboot_boot_x0; + const void *prop; + char *bargs, *s; + int node, len, ret = 0; + + /* + * Save the bootargs passed in the DTB by the previous bootloader + * (CBoot) to the env. (pointer in reg x0) + */ + + debug("%s: cboot_blob = %p\n", __func__, cboot_blob); + + node = fdt_path_offset(cboot_blob, "/chosen"); + if (node < 0) { + error("Can't find /chosen node in cboot DTB"); + return node; + } + debug("%s: found 'chosen' node: %d\n", __func__, node); + + prop = fdt_getprop(cboot_blob, node, "bootargs", &len); + if (!prop) { + error("Can't find /chosen/bootargs property in cboot DTB"); + return -ENOENT; + } + debug("%s: found 'bootargs' property, len =%d\n", __func__, len); + + /* CBoot seems to add trailing whitespace - strip it here */ + s = strdup((char *)prop); + bargs = strstrip(s); + debug("%s: bootargs = %s!\n", __func__, bargs); + + /* Set cbootargs to env for later use by extlinux files */ + ret = setenv("cbootargs", bargs); + if (ret) + printf("Failed to set cbootargs from cboot DTB: %d\n", ret); + + free(s); + return ret; +} + +int cboot_init_late(void) +{ + const void *fdt = (void *)cboot_boot_x0; + + set_calculated_env_vars(); + /* + * Ignore errors here; the value may not be used depending on + * extlinux.conf or boot script content. + */ + set_fdt_addr(); + /* Ignore errors here; not all cases care about Ethernet addresses */ + set_ethaddr_from_cboot(fdt); + /* Save CBoot bootargs to env */ + set_cbootargs(); + + return 0; +} diff --git a/arch/arm/mach-tegra/cboot_ll.S b/arch/arm/mach-tegra/cboot_ll.S new file mode 100644 index 000000000000..a3956b85f64b --- /dev/null +++ b/arch/arm/mach-tegra/cboot_ll.S @@ -0,0 +1,21 @@ +/* + * Save cboot-related boot-time CPU state + * + * (C) Copyright 2015-2017 NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +.align 8 +.globl cboot_boot_x0 +cboot_boot_x0: + .dword 0 + +ENTRY(save_boot_params) + adr x8, cboot_boot_x0 + str x0, [x8] + b save_boot_params_ret +ENDPROC(save_boot_params) diff --git a/arch/arm/mach-tegra/cboot_mem.c b/arch/arm/mach-tegra/cboot_mem.c new file mode 100644 index 000000000000..132afbe65e7a --- /dev/null +++ b/arch/arm/mach-tegra/cboot_mem.c @@ -0,0 +1,175 @@ +/* + * Copyright (c) 2016-2019, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#define SZ_4G 0x100000000ULL + +/* + * Size of a region that's large enough to hold the relocated U-Boot and all + * other allocations made around it (stack, heap, page tables, etc.) + * In practice, running "bdinfo" at the shell prompt, the stack reaches about + * 5MB from the address selected for ram_top as of the time of writing, + * so a 16MB region should be plenty. + */ +#define MIN_USABLE_RAM_SIZE SZ_16M +/* + * The amount of space we expect to require for stack usage. Used to validate + * that all reservations fit into the region selected for the relocation target + */ +#define MIN_USABLE_STACK_SIZE SZ_1M + +DECLARE_GLOBAL_DATA_PTR; + +extern struct mm_region tegra_mem_map[]; + +/* + * These variables are written to before relocation, and hence cannot be + * in.bss, since .bss overlaps the DTB that's appended to the U-Boot binary. + * The section attribute forces this into .data and avoids this issue. This + * also has the nice side-effect of the content being valid after relocation. + */ + +/* The number of valid entries in ram_banks[] */ +static int ram_bank_count __attribute__((section(".data"))); + +/* + * The usable top-of-RAM for U-Boot. This is both: + * a) Below 4GB to avoid issues with peripherals that use 32-bit addressing. + * b) At the end of a region that has enough space to hold the relocated U-Boot + * and all other allocations made around it (stack, heap, page tables, etc.) + */ +static u64 ram_top __attribute__((section(".data"))); +/* The base address of the region of RAM that ends at ram_top */ +static u64 region_base __attribute__((section(".data"))); + +int dram_init(void) +{ + unsigned int na, ns; + const void *cboot_blob = (void *)cboot_boot_x0; + int node, len, i; + const u32 *prop; + + na = fdtdec_get_uint(cboot_blob, 0, "#address-cells", 2); + ns = fdtdec_get_uint(cboot_blob, 0, "#size-cells", 2); + + node = fdt_path_offset(cboot_blob, "/memory"); + if (node < 0) { + error("Can't find /memory node in cboot DTB"); + hang(); + } + prop = fdt_getprop(cboot_blob, node, "reg", &len); + if (!prop) { + error("Can't find /memory/reg property in cboot DTB"); + hang(); + } + + /* Calculate the true # of base/size pairs to read */ + len /= 4; /* Convert bytes to number of cells */ + len /= (na + ns); /* Convert cells to number of banks */ + if (len > CONFIG_NR_DRAM_BANKS) + len = CONFIG_NR_DRAM_BANKS; + + /* Parse the /memory node, and save useful entries */ + gd->ram_size = 0; + ram_bank_count = 0; + for (i = 0; i < len; i++) { + u64 bank_start, bank_end, bank_size, usable_bank_size; + + /* Extract raw memory region data from DTB */ + bank_start = of_read_number(prop, na); + prop += na; + bank_size = of_read_number(prop, ns); + prop += ns; + gd->ram_size += bank_size; + bank_end = bank_start + bank_size; + debug("Bank %d: %llx..%llx (+%llx)\n", i, + bank_start, bank_end, bank_size); + + /* + * Align the bank to MMU section size. This is not strictly + * necessary, since the translation table construction code + * handles page granularity without issue. However, aligning + * the MMU entries reduces the size and number of levels in the + * page table, so is worth it. + */ + bank_start = ROUND(bank_start, SZ_2M); + bank_end = bank_end & ~(SZ_2M - 1); + bank_size = bank_end - bank_start; + debug(" aligned: %llx..%llx (+%llx)\n", + bank_start, bank_end, bank_size); + if (bank_end <= bank_start) + continue; + + /* Record data used to create MMU translation tables */ + ram_bank_count++; + /* Index below is deliberately 1-based to skip MMIO entry */ + tegra_mem_map[ram_bank_count].base = bank_start; + tegra_mem_map[ram_bank_count].size = bank_size; + tegra_mem_map[ram_bank_count].attrs = + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; + + /* Determine best bank to relocate U-Boot into */ + if (bank_end > SZ_4G) + bank_end = SZ_4G; + debug(" end %llx (usable)\n", bank_end); + usable_bank_size = bank_end - bank_start; + debug(" size %llx (usable)\n", usable_bank_size); + if ((usable_bank_size >= MIN_USABLE_RAM_SIZE) && + (bank_end > ram_top)) { + ram_top = bank_end; + region_base = bank_start; + debug("ram top now %llx\n", ram_top); + } + } + + /* Ensure memory map contains the desired sentinel entry */ + tegra_mem_map[ram_bank_count + 1].base = 0; + tegra_mem_map[ram_bank_count + 1].size = 0; + tegra_mem_map[ram_bank_count + 1].attrs = 0; + + /* Error out if a relocation target couldn't be found */ + if (!ram_top) { + error("Can't find a usable RAM top"); + hang(); + } + + return 0; +} + +void dram_init_banksize(void) +{ + int i; + + if ((gd->start_addr_sp - region_base) < MIN_USABLE_STACK_SIZE) { + error("Reservations exceed chosen region size"); + hang(); + } + + for (i = 0; i < ram_bank_count; i++) { + gd->bd->bi_dram[i].start = tegra_mem_map[1 + i].base; + gd->bd->bi_dram[i].size = tegra_mem_map[1 + i].size; + } + +#ifdef CONFIG_PCI + gd->pci_ram_top = ram_top; +#endif +} + +ulong board_get_usable_ram_top(ulong total_size) +{ + return ram_top; +} + +void *fdt_copy_get_blob_src_default(void) +{ + return (void *)cboot_boot_x0; +} diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index c50d56dc888b..1d023f07c757 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2018, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */ @@ -727,11 +727,16 @@ void tegra30_set_up_pllp(void) int clock_external_output(int clk_id) { - struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + u32 val; if (clk_id >= 1 && clk_id <= 3) { - setbits_le32(&pmc->pmc_clk_out_cntrl, - 1 << (2 + (clk_id - 1) * 8)); + val = tegra_pmc_readl(offsetof(struct pmc_ctlr, + pmc_clk_out_cntrl)); + val |= 1 << (2 + (clk_id - 1) * 8); + tegra_pmc_writel(val, + offsetof(struct pmc_ctlr, + pmc_clk_out_cntrl)); + } else { printf("%s: Unknown output clock id %d\n", __func__, clk_id); return -EINVAL; diff --git a/arch/arm/mach-tegra/cmd_enterrcm.c b/arch/arm/mach-tegra/cmd_enterrcm.c index a94ec93e7be1..4652d0b70dd2 100644 --- a/arch/arm/mach-tegra/cmd_enterrcm.c +++ b/arch/arm/mach-tegra/cmd_enterrcm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2012-2018, NVIDIA CORPORATION. All rights reserved. * * Derived from code (arch/arm/lib/reset.c) that is: * @@ -26,19 +26,33 @@ */ #include +#include #include #include static int do_enterrcm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + u32 pmc_scratch0_offset; puts("Entering RCM...\n"); udelay(50000); - pmc->pmc_scratch0 = 2; +#if defined(CONFIG_TEGRA186) + /* + * T186 has moved the scratch regs. Address the reg directly here + * rather than creating a new pmc reg struct for just one register. + */ + pmc_scratch0_offset = 0x32000; +#else + pmc_scratch0_offset = offsetof(struct pmc_ctlr, pmc_scratch0); +#endif + + tegra_pmc_writel(2, pmc_scratch0_offset); + disable_interrupts(); + + /* reset_cpu */ reset_cpu(0); return 0; diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c index a3ebb57f20b2..c72c46a55ffe 100644 --- a/arch/arm/mach-tegra/cpu.c +++ b/arch/arm/mach-tegra/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2018, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */ @@ -300,21 +300,19 @@ void enable_cpu_clock(int enable) static int is_cpu_powered(void) { - struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; - - return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0; + return (tegra_pmc_readl(offsetof(struct pmc_ctlr, + pmc_pwrgate_status)) & CPU_PWRED) ? 1 : 0; } static void remove_cpu_io_clamps(void) { - struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; u32 reg; debug("%s entry\n", __func__); /* Remove the clamps on the CPU I/O signals */ - reg = readl(&pmc->pmc_remove_clamping); + reg = tegra_pmc_readl(offsetof(struct pmc_ctlr, pmc_remove_clamping)); reg |= CPU_CLMP; - writel(reg, &pmc->pmc_remove_clamping); + tegra_pmc_writel(reg, offsetof(struct pmc_ctlr, pmc_remove_clamping)); /* Give I/O signals time to stabilize */ udelay(IO_STABILIZATION_DELAY); @@ -322,17 +320,19 @@ static void remove_cpu_io_clamps(void) void powerup_cpu(void) { - struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; u32 reg; int timeout = IO_STABILIZATION_DELAY; debug("%s entry\n", __func__); if (!is_cpu_powered()) { /* Toggle the CPU power state (OFF -> ON) */ - reg = readl(&pmc->pmc_pwrgate_toggle); + reg = tegra_pmc_readl(offsetof(struct pmc_ctlr, + pmc_pwrgate_toggle)); reg &= PARTID_CP; reg |= START_CP; - writel(reg, &pmc->pmc_pwrgate_toggle); + tegra_pmc_writel(reg, + offsetof(struct pmc_ctlr, + pmc_pwrgate_toggle)); /* Wait for the power to come up */ while (!is_cpu_powered()) { diff --git a/arch/arm/mach-tegra/cpu.h b/arch/arm/mach-tegra/cpu.h index 3f38969a44f1..1154f8b37ef8 100644 --- a/arch/arm/mach-tegra/cpu.h +++ b/arch/arm/mach-tegra/cpu.h @@ -16,7 +16,7 @@ #elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) || \ defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210) #define NVBL_PLLP_KHZ 408000 -#define CSITE_KHZ 204000 +#define CSITE_KHZ 136000 #else #error "Unknown Tegra chip!" #endif diff --git a/arch/arm/mach-tegra/dt-edit.c b/arch/arm/mach-tegra/dt-edit.c new file mode 100644 index 000000000000..f231966c3cde --- /dev/null +++ b/arch/arm/mach-tegra/dt-edit.c @@ -0,0 +1,423 @@ +/* + * Copyright (C) 2010-2019 NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include "dt-edit.h" + +#define fdt_for_each_property(fdt, prop, parent) \ + for (prop = fdt_first_property_offset(fdt, parent); \ + prop >= 0; \ + prop = fdt_next_property_offset(fdt, prop)) +typedef int iter_envitem(void *blob_dst, char *item, void *param); +static int fdt_copy_node_content(void *blob_src, int ofs_src, void *blob_dst, + int ofs_dst, int indent) +{ + int ofs_src_child, ofs_dst_child; + int ret; + + /* + * FIXME: This doesn't remove properties or nodes in the destination + * that are not present in the source. For the nodes we care about + * right now, this is not an issue. + */ + + fdt_for_each_property(blob_src, ofs_src_child, ofs_src) { + const void *prop; + const char *name; + int len; + + prop = fdt_getprop_by_offset(blob_src, ofs_src_child, &name, + &len); + debug("%s: %*scopy prop: %s\n", __func__, indent, "", name); +add_prop: + ret = fdt_setprop(blob_dst, ofs_dst, name, prop, len); + if (ret == -FDT_ERR_NOSPACE) { + ret = fdt_increase_size(blob_dst, 512); + debug("Increased FDT blob size by 512 bytes\n"); + if (!ret) + goto add_prop; /* retry setprop */ + else + goto err_ret; /* error out */ + } else if (ret < 0) { + error("Can't copy DT prop %s: %s\n", + name, fdt_strerror(ret)); + return ret; + } + } + + fdt_for_each_subnode(blob_src, ofs_src_child, ofs_src) { + const char *name; + + name = fdt_get_name(blob_src, ofs_src_child, NULL); + debug("%s: %*scopy node: %s\n", __func__, indent, "", name); + + ofs_dst_child = fdt_subnode_offset(blob_dst, ofs_dst, name); + if (ofs_dst_child < 0) { + debug("%s: %*s(creating it in dst)\n", __func__, + indent, ""); +add_node: + ofs_dst_child = fdt_add_subnode(blob_dst, ofs_dst, + name); + if (ofs_dst_child == -FDT_ERR_NOSPACE) { + ret = fdt_increase_size(blob_dst, 512); + debug("Increased FDT blob size by 512 bytes\n"); + if (!ret) + goto add_node; /* retry add_subnode */ + else + goto err_ret; /* error out */ + } else if (ofs_dst_child < 0) { + error("Can't copy DT node %s: %s\n", + name, fdt_strerror(ofs_dst_child)); + return ofs_dst_child; + } + } + + fdt_copy_node_content(blob_src, ofs_src_child, blob_dst, + ofs_dst_child, indent + 2); + } + + return 0; + +err_ret: + printf("Can't increase blob size: %s\n", fdt_strerror(ret)); + return ret; +} + +static int fdt_add_path(void *blob, const char *path) +{ + char *pcopy, *tmp, *node; + int ofs_parent, ofs_child, ret; + + if (path[0] != '/') { + error("Can't add path %s; missing leading /", path); + return -1; + } + path++; + if (!*path) { + debug("%s: path points at DT root!", __func__); + return 0; + } + + pcopy = strdup(path); + if (!pcopy) { + error("strdup() failed"); + return -1; + } + + tmp = pcopy; + ofs_parent = 0; + while (true) { + node = strsep(&tmp, "/"); + if (!node) + break; + debug("%s: node=%s\n", __func__, node); + ofs_child = fdt_subnode_offset(blob, ofs_parent, node); + if (ofs_child < 0) + ofs_child = fdt_add_subnode(blob, ofs_parent, node); + if (ofs_child < 0) { + error("Can't create DT node %s\n", node); + ret = ofs_child; + goto out; + } + ofs_parent = ofs_child; + } + ret = ofs_parent; + +out: + free(pcopy); + + return ret; +} + +static iter_envitem fdt_iter_copy_prop; +static int fdt_iter_copy_prop(void *blob_dst, char *prop_path, void *blob_src) +{ + char *prop_name, *node_path; + const void *prop; + int ofs_src, ofs_dst, len, ret; + + prop_name = strrchr(prop_path, '/'); + if (!prop_name) { + error("Can't copy prop %s; missing /", prop_path); + return -1; + } + *prop_name = 0; + prop_name++; + node_path = prop_path; + + if (*node_path) { + ofs_src = fdt_path_offset(blob_src, node_path); + if (ofs_src < 0) { + error("DT node %s missing in source; can't copy %s\n", + node_path, prop_name); + return -1; + } + + ofs_dst = fdt_path_offset(blob_dst, node_path); + if (ofs_src < 0) { + error("DT node %s missing in dest; can't copy prop %s\n", + node_path, prop_name); + return -1; + } + } else { + ofs_src = 0; + ofs_dst = 0; + } + + prop = fdt_getprop(blob_src, ofs_src, prop_name, &len); + if (!prop) { + error("DT property %s/%s missing in source; can't copy\n", + node_path, prop_name); + return -1; + } +add_prop: + ret = fdt_setprop(blob_dst, ofs_dst, prop_name, prop, len); + if (ret == -FDT_ERR_NOSPACE) { + ret = fdt_increase_size(blob_dst, 512); + debug("Increased FDT blob size by 512 bytes\n"); + if (!ret) + goto add_prop; /* retry setprop */ + else + goto err_ret; /* error out */ + } else if (ret < 0) { + error("Can't set DT prop %s/%s: %s\n", + node_path, prop_name, fdt_strerror(ret)); + return ret; + } + + return 0; +err_ret: + printf("Can't increase blob size: %s\n", fdt_strerror(ret)); + return ret; +} + +static iter_envitem fdt_iter_copy_node; +static int fdt_iter_copy_node(void *blob_dst, char *path, void *blob_src) +{ + int ofs_dst, ofs_src; + int ret; + + ofs_dst = fdt_add_path(blob_dst, path); + if (ofs_dst < 0) { + error("Can't find/create dest DT node %s to copy\n", path); + return ofs_dst; + } + + if (!fdtdec_get_is_enabled(blob_dst, ofs_dst)) { + debug("%s: DT node %s disabled in dest; skipping copy\n", + __func__, path); + return 0; + } + + ofs_src = fdt_path_offset(blob_src, path); + if (ofs_src < 0) { + error("DT node %s missing in source; can't copy\n", path); + return 0; + } + + ret = fdt_copy_node_content(blob_src, ofs_src, blob_dst, + ofs_dst, 2); + if (ret < 0) + return ret; + + return 0; +} + +static iter_envitem fdt_iter_del_node; +static int fdt_iter_del_node(void *blob_dst, char *node_path, void *unused_param) +{ + int ofs; + + ofs = fdt_path_offset(blob_dst, node_path); + /* Node doesn't exist -> property can't exist -> it's removed! */ + if (ofs == -FDT_ERR_NOTFOUND) + return 0; + if (ofs < 0) { + error("DT node %s lookup failure; can't del node\n", node_path); + return ofs; + } + + return fdt_del_node(blob_dst, ofs); +} + +static iter_envitem fdt_iter_del_prop; +static int fdt_iter_del_prop(void *blob_dst, char *prop_path, void *unused_param) +{ + char *prop_name, *node_path; + int ofs, ret; + + prop_name = strrchr(prop_path, '/'); + if (!prop_name) { + error("Can't del prop %s; missing /", prop_path); + return -1; + } + *prop_name = 0; + prop_name++; + node_path = prop_path; + + if (*node_path) { + ofs = fdt_path_offset(blob_dst, node_path); + /* Node doesn't exist -> property can't exist -> it's removed! */ + if (ofs == -FDT_ERR_NOTFOUND) + return 0; + if (ofs < 0) { + error("DT node %s lookup failure; can't del prop %s\n", + node_path, prop_name); + return ofs; + } + } else { + ofs = 0; + } + + ret = fdt_delprop(blob_dst, ofs, prop_name); + /* Property doesn't exist -> it's already removed! */ + if (ret == -FDT_ERR_NOTFOUND) + return 0; + return ret; +} + +static int fdt_iter_envlist(iter_envitem *func, void *blob_dst, const char *env_varname, void *param) +{ + char *items, *tmp, *item; + int ret; + + items = getenv(env_varname); + if (!items) { + debug("%s: No env var %s\n", __func__, env_varname); + return 0; + } + + items = strdup(items); + if (!items) { + error("strdup(%s) failed", env_varname); + return -1; + } + + tmp = items; + while (true) { + item = strsep(&tmp, ":"); + if (!item) + break; + debug("%s: item: %s\n", __func__, item); + ret = func(blob_dst, item, param); + if (ret < 0) { + ret = -1; + goto out; + } + } + + ret = 0; + +out: + free(items); + + return ret; +} + +__weak void *fdt_copy_get_blob_src_default(void) +{ + return NULL; +} + +static void *fdt_get_blob_src(void) +{ + char *src_addr_s; + + src_addr_s = getenv("fdt_copy_src_addr"); + if (!src_addr_s) + return fdt_copy_get_blob_src_default(); + return (void *)simple_strtoul(src_addr_s, NULL, 16); +} + +static void *fdt_get_copy_blob_src(void *blob_dst) +{ + void *blob_src = fdt_get_blob_src(); + + if (blob_src == blob_dst) + return NULL; + return blob_src; +} + +int fdt_copy_env_nodelist(void *blob_dst) +{ + void *blob_src; + + debug("%s:\n", __func__); + + blob_src = fdt_get_copy_blob_src(blob_dst); + if (!blob_src) { + debug("%s: No source DT\n", __func__); + return 0; + } + + return fdt_iter_envlist(fdt_iter_copy_node, blob_dst, "fdt_copy_node_paths", blob_src); +} + +/* Deletes node list from dst blob, then copies same node list from src->dst */ +int fdt_del_then_copy_env_nodelist(void *blob_dst) +{ + void *blob_src; + + debug("%s:\n", __func__); + + blob_src = fdt_get_copy_blob_src(blob_dst); + if (!blob_src) { + debug("%s: No source DT\n", __func__); + return 0; + } + + fdt_iter_envlist(fdt_iter_del_node, blob_dst, "fdt_del_copy_node_paths", NULL); + + return fdt_iter_envlist(fdt_iter_copy_node, blob_dst, "fdt_del_copy_node_paths", blob_src); +} + +int fdt_copy_env_proplist(void *blob_dst) +{ + void *blob_src; + + debug("%s:\n", __func__); + + blob_src = fdt_get_copy_blob_src(blob_dst); + if (!blob_src) { + debug("%s: No source DT\n", __func__); + return 0; + } + + return fdt_iter_envlist(fdt_iter_copy_prop, blob_dst, "fdt_copy_prop_paths", blob_src); +} + +int fdt_del_env_nodelist(void) +{ + void *blob_src; + + debug("%s:\n", __func__); + + blob_src = fdt_get_blob_src(); + if (!blob_src) { + error("%s: No source DT\n", __func__); + return -ENXIO; + } + + return fdt_iter_envlist(fdt_iter_del_node, blob_src, "fdt_del_node_paths", NULL); +} + +int fdt_del_env_proplist(void) +{ + void *blob_src; + + debug("%s:\n", __func__); + + blob_src = fdt_get_blob_src(); + if (!blob_src) { + error("%s: No source DT\n", __func__); + return -ENXIO; + } + + return fdt_iter_envlist(fdt_iter_del_prop, blob_src, "fdt_del_prop_paths", NULL); +} diff --git a/arch/arm/mach-tegra/dt-edit.h b/arch/arm/mach-tegra/dt-edit.h new file mode 100644 index 000000000000..77bce8459bc3 --- /dev/null +++ b/arch/arm/mach-tegra/dt-edit.h @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2010-2019 NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +void *fdt_copy_get_blob_src_default(void); + +int fdt_copy_env_proplist(void *blob_dst); +int fdt_copy_env_nodelist(void *blob_dst); +int fdt_del_env_nodelist(void); +int fdt_del_env_proplist(void); +int fdt_del_then_copy_env_nodelist(void *blob_dst); diff --git a/arch/arm/mach-tegra/dt-setup.c b/arch/arm/mach-tegra/dt-setup.c new file mode 100644 index 000000000000..5d890a3e380e --- /dev/null +++ b/arch/arm/mach-tegra/dt-setup.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2010-2019, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include "dt-edit.h" + +/* + * This function is called right before the kernel is booted. "blob" is the + * device tree that will be passed to the kernel. + */ +int ft_system_setup(void *blob, bd_t *bd) +{ + const char *gpu_compats[] = { +#if defined(CONFIG_TEGRA124) + "nvidia,gk20a", +#endif + }; + int i, ret; + + /* Enable GPU node if GPU setup has been performed */ + for (i = 0; i < ARRAY_SIZE(gpu_compats); i++) { + ret = tegra_gpu_enable_node(blob, gpu_compats[i]); + if (ret) + return ret; + } + + fdt_del_env_nodelist(); + fdt_del_env_proplist(); + fdt_copy_env_nodelist(blob); + fdt_copy_env_proplist(blob); + fdt_del_then_copy_env_nodelist(blob); + + return 0; +} diff --git a/arch/arm/mach-tegra/ft_board_info.c b/arch/arm/mach-tegra/ft_board_info.c new file mode 100644 index 000000000000..7dd3a405b19c --- /dev/null +++ b/arch/arm/mach-tegra/ft_board_info.c @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2010-2016 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include "ft_board_info.h" + +int ft_board_info_set(void *blob, const struct ft_board_info *bi, + const char *chosen_subnode_name) +{ + int chosen, offset, ret; + u32 val; + + chosen = fdt_path_offset(blob, "/chosen"); + if (!chosen) { + chosen = fdt_add_subnode(blob, 0, "chosen"); + if (chosen < 0) { + error("fdt_add_subnode(/, chosen) failed: %s.\n", + fdt_strerror(chosen)); + return chosen; + } + } + + offset = fdt_add_subnode(blob, chosen, chosen_subnode_name); + if (offset < 0) { + error("fdt_add_subnode(/chosen, %s): %s.\n", + chosen_subnode_name, fdt_strerror(offset)); + return offset; + } + + val = cpu_to_fdt32(bi->id); + ret = fdt_setprop(blob, offset, "id", &val, sizeof(val)); + if (ret < 0) { + error("could not update id property %s.\n", + fdt_strerror(ret)); + return ret; + } + + val = cpu_to_fdt32(bi->sku); + ret = fdt_setprop(blob, offset, "sku", &val, sizeof(val)); + if (ret < 0) { + error("could not update sku property %s.\n", + fdt_strerror(ret)); + return ret; + } + + val = cpu_to_fdt32(bi->fab); + ret = fdt_setprop(blob, offset, "fab", &val, sizeof(val)); + if (ret < 0) { + error("could not update fab property %s.\n", + fdt_strerror(ret)); + return ret; + } + + val = cpu_to_fdt32(bi->major); + ret = fdt_setprop(blob, offset, "major_revision", &val, sizeof(val)); + if (ret < 0) { + error("could not update major_revision property %s.\n", + fdt_strerror(ret)); + return ret; + } + + val = cpu_to_fdt32(bi->minor); + ret = fdt_setprop(blob, offset, "minor_revision", &val, sizeof(val)); + if (ret < 0) { + error("could not update minor_revision property %s.\n", + fdt_strerror(ret)); + return ret; + } + + return 0; +} diff --git a/arch/arm/mach-tegra/ft_board_info.h b/arch/arm/mach-tegra/ft_board_info.h new file mode 100644 index 000000000000..c320aee044b4 --- /dev/null +++ b/arch/arm/mach-tegra/ft_board_info.h @@ -0,0 +1,23 @@ +/* + * Board info related definitions + * + * (C) Copyright 2015 NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_INFO_H_ +#define _BOARD_INFO_H_ + +struct ft_board_info { + u32 id; + u32 sku; + u32 fab; + u32 major; + u32 minor; +}; + +int ft_board_info_set(void *blob, const struct ft_board_info *bi, + const char *chosen_subnode_name); + +#endif diff --git a/arch/arm/mach-tegra/gpu.c b/arch/arm/mach-tegra/gpu.c index 74b64a620c5f..8c41365e5732 100644 --- a/arch/arm/mach-tegra/gpu.c +++ b/arch/arm/mach-tegra/gpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */ @@ -17,6 +17,7 @@ static bool _configured; void tegra_gpu_config(void) { +#if !defined(CONFIG_ARM64) struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE; /* Turn VPR off */ @@ -27,8 +28,8 @@ void tegra_gpu_config(void) readl(&mc->mc_video_protect_reg_ctrl); debug("configured VPR\n"); - _configured = true; +#endif /* !ARM64 */ } #if defined(CONFIG_OF_LIBFDT) diff --git a/arch/arm/mach-tegra/ivc.c b/arch/arm/mach-tegra/ivc.c new file mode 100644 index 000000000000..cf6626fb12c7 --- /dev/null +++ b/arch/arm/mach-tegra/ivc.c @@ -0,0 +1,553 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include + +#define TEGRA_IVC_ALIGN 64 + +/* + * IVC channel reset protocol. + * + * Each end uses its tx_channel.state to indicate its synchronization state. + */ +enum ivc_state { + /* + * This value is zero for backwards compatibility with services that + * assume channels to be initially zeroed. Such channels are in an + * initially valid state, but cannot be asynchronously reset, and must + * maintain a valid state at all times. + * + * The transmitting end can enter the established state from the sync or + * ack state when it observes the receiving endpoint in the ack or + * established state, indicating that has cleared the counters in our + * rx_channel. + */ + ivc_state_established = 0, + + /* + * If an endpoint is observed in the sync state, the remote endpoint is + * allowed to clear the counters it owns asynchronously with respect to + * the current endpoint. Therefore, the current endpoint is no longer + * allowed to communicate. + */ + ivc_state_sync, + + /* + * When the transmitting end observes the receiving end in the sync + * state, it can clear the w_count and r_count and transition to the ack + * state. If the remote endpoint observes us in the ack state, it can + * return to the established state once it has cleared its counters. + */ + ivc_state_ack +}; + +/* + * This structure is divided into two-cache aligned parts, the first is only + * written through the tx_channel pointer, while the second is only written + * through the rx_channel pointer. This delineates ownership of the cache lines, + * which is critical to performance and necessary in non-cache coherent + * implementations. + */ +struct tegra_ivc_channel_header { + union { + /* fields owned by the transmitting end */ + struct { + uint32_t w_count; + uint32_t state; + }; + uint8_t w_align[TEGRA_IVC_ALIGN]; + }; + union { + /* fields owned by the receiving end */ + uint32_t r_count; + uint8_t r_align[TEGRA_IVC_ALIGN]; + }; +}; + +static inline void tegra_ivc_invalidate_counter(struct tegra_ivc *ivc, + struct tegra_ivc_channel_header *h, + ulong offset) +{ + ulong base = ((ulong)h) + offset; + invalidate_dcache_range(base, base + TEGRA_IVC_ALIGN); +} + +static inline void tegra_ivc_flush_counter(struct tegra_ivc *ivc, + struct tegra_ivc_channel_header *h, + ulong offset) +{ + ulong base = ((ulong)h) + offset; + flush_dcache_range(base, base + TEGRA_IVC_ALIGN); +} + +static inline ulong tegra_ivc_frame_addr(struct tegra_ivc *ivc, + struct tegra_ivc_channel_header *h, + uint32_t frame) +{ + BUG_ON(frame >= ivc->nframes); + + return ((ulong)h) + sizeof(struct tegra_ivc_channel_header) + + (ivc->frame_size * frame); +} + +static inline void *tegra_ivc_frame_pointer(struct tegra_ivc *ivc, + struct tegra_ivc_channel_header *ch, + uint32_t frame) +{ + return (void *)tegra_ivc_frame_addr(ivc, ch, frame); +} + +static inline void tegra_ivc_invalidate_frame(struct tegra_ivc *ivc, + struct tegra_ivc_channel_header *h, + unsigned frame) +{ + ulong base = tegra_ivc_frame_addr(ivc, h, frame); + invalidate_dcache_range(base, base + ivc->frame_size); +} + +static inline void tegra_ivc_flush_frame(struct tegra_ivc *ivc, + struct tegra_ivc_channel_header *h, + unsigned frame) +{ + ulong base = tegra_ivc_frame_addr(ivc, h, frame); + flush_dcache_range(base, base + ivc->frame_size); +} + +static inline int tegra_ivc_channel_empty(struct tegra_ivc *ivc, + struct tegra_ivc_channel_header *ch) +{ + /* + * This function performs multiple checks on the same values with + * security implications, so create snapshots with ACCESS_ONCE() to + * ensure that these checks use the same values. + */ + uint32_t w_count = ACCESS_ONCE(ch->w_count); + uint32_t r_count = ACCESS_ONCE(ch->r_count); + + /* + * Perform an over-full check to prevent denial of service attacks where + * a server could be easily fooled into believing that there's an + * extremely large number of frames ready, since receivers are not + * expected to check for full or over-full conditions. + * + * Although the channel isn't empty, this is an invalid case caused by + * a potentially malicious peer, so returning empty is safer, because it + * gives the impression that the channel has gone silent. + */ + if (w_count - r_count > ivc->nframes) + return 1; + + return w_count == r_count; +} + +static inline int tegra_ivc_channel_full(struct tegra_ivc *ivc, + struct tegra_ivc_channel_header *ch) +{ + /* + * Invalid cases where the counters indicate that the queue is over + * capacity also appear full. + */ + return (ACCESS_ONCE(ch->w_count) - ACCESS_ONCE(ch->r_count)) >= + ivc->nframes; +} + +static inline void tegra_ivc_advance_rx(struct tegra_ivc *ivc) +{ + ACCESS_ONCE(ivc->rx_channel->r_count) = + ACCESS_ONCE(ivc->rx_channel->r_count) + 1; + + if (ivc->r_pos == ivc->nframes - 1) + ivc->r_pos = 0; + else + ivc->r_pos++; +} + +static inline void tegra_ivc_advance_tx(struct tegra_ivc *ivc) +{ + ACCESS_ONCE(ivc->tx_channel->w_count) = + ACCESS_ONCE(ivc->tx_channel->w_count) + 1; + + if (ivc->w_pos == ivc->nframes - 1) + ivc->w_pos = 0; + else + ivc->w_pos++; +} + +static inline int tegra_ivc_check_read(struct tegra_ivc *ivc) +{ + ulong offset; + + /* + * tx_channel->state is set locally, so it is not synchronized with + * state from the remote peer. The remote peer cannot reset its + * transmit counters until we've acknowledged its synchronization + * request, so no additional synchronization is required because an + * asynchronous transition of rx_channel->state to ivc_state_ack is not + * allowed. + */ + if (ivc->tx_channel->state != ivc_state_established) + return -ECONNRESET; + + /* + * Avoid unnecessary invalidations when performing repeated accesses to + * an IVC channel by checking the old queue pointers first. + * Synchronization is only necessary when these pointers indicate empty + * or full. + */ + if (!tegra_ivc_channel_empty(ivc, ivc->rx_channel)) + return 0; + + offset = offsetof(struct tegra_ivc_channel_header, w_count); + tegra_ivc_invalidate_counter(ivc, ivc->rx_channel, offset); + return tegra_ivc_channel_empty(ivc, ivc->rx_channel) ? -ENOMEM : 0; +} + +static inline int tegra_ivc_check_write(struct tegra_ivc *ivc) +{ + ulong offset; + + if (ivc->tx_channel->state != ivc_state_established) + return -ECONNRESET; + + if (!tegra_ivc_channel_full(ivc, ivc->tx_channel)) + return 0; + + offset = offsetof(struct tegra_ivc_channel_header, r_count); + tegra_ivc_invalidate_counter(ivc, ivc->tx_channel, offset); + return tegra_ivc_channel_full(ivc, ivc->tx_channel) ? -ENOMEM : 0; +} + +static inline uint32_t tegra_ivc_channel_avail_count(struct tegra_ivc *ivc, + struct tegra_ivc_channel_header *ch) +{ + /* + * This function isn't expected to be used in scenarios where an + * over-full situation can lead to denial of service attacks. See the + * comment in tegra_ivc_channel_empty() for an explanation about + * special over-full considerations. + */ + return ACCESS_ONCE(ch->w_count) - ACCESS_ONCE(ch->r_count); +} + +int tegra_ivc_read_get_next_frame(struct tegra_ivc *ivc, void **frame) +{ + int result = tegra_ivc_check_read(ivc); + if (result < 0) + return result; + + /* + * Order observation of w_pos potentially indicating new data before + * data read. + */ + mb(); + + tegra_ivc_invalidate_frame(ivc, ivc->rx_channel, ivc->r_pos); + *frame = tegra_ivc_frame_pointer(ivc, ivc->rx_channel, ivc->r_pos); + + return 0; +} + +int tegra_ivc_read_advance(struct tegra_ivc *ivc) +{ + ulong offset; + int result; + + /* + * No read barriers or synchronization here: the caller is expected to + * have already observed the channel non-empty. This check is just to + * catch programming errors. + */ + result = tegra_ivc_check_read(ivc); + if (result) + return result; + + tegra_ivc_advance_rx(ivc); + offset = offsetof(struct tegra_ivc_channel_header, r_count); + tegra_ivc_flush_counter(ivc, ivc->rx_channel, offset); + + /* + * Ensure our write to r_pos occurs before our read from w_pos. + */ + mb(); + + offset = offsetof(struct tegra_ivc_channel_header, w_count); + tegra_ivc_invalidate_counter(ivc, ivc->rx_channel, offset); + + if (tegra_ivc_channel_avail_count(ivc, ivc->rx_channel) == + ivc->nframes - 1) + ivc->notify(ivc); + + return 0; +} + +int tegra_ivc_write_get_next_frame(struct tegra_ivc *ivc, void **frame) +{ + int result = tegra_ivc_check_write(ivc); + if (result) + return result; + + *frame = tegra_ivc_frame_pointer(ivc, ivc->tx_channel, ivc->w_pos); + + return 0; +} + +int tegra_ivc_write_advance(struct tegra_ivc *ivc) +{ + ulong offset; + int result; + + result = tegra_ivc_check_write(ivc); + if (result) + return result; + + tegra_ivc_flush_frame(ivc, ivc->tx_channel, ivc->w_pos); + + /* + * Order any possible stores to the frame before update of w_pos. + */ + mb(); + + tegra_ivc_advance_tx(ivc); + offset = offsetof(struct tegra_ivc_channel_header, w_count); + tegra_ivc_flush_counter(ivc, ivc->tx_channel, offset); + + /* + * Ensure our write to w_pos occurs before our read from r_pos. + */ + mb(); + + offset = offsetof(struct tegra_ivc_channel_header, r_count); + tegra_ivc_invalidate_counter(ivc, ivc->tx_channel, offset); + + if (tegra_ivc_channel_avail_count(ivc, ivc->tx_channel) == 1) + ivc->notify(ivc); + + return 0; +} + +/* + * =============================================================== + * IVC State Transition Table - see tegra_ivc_channel_notified() + * =============================================================== + * + * local remote action + * ----- ------ ----------------------------------- + * SYNC EST + * SYNC ACK reset counters; move to EST; notify + * SYNC SYNC reset counters; move to ACK; notify + * ACK EST move to EST; notify + * ACK ACK move to EST; notify + * ACK SYNC reset counters; move to ACK; notify + * EST EST + * EST ACK + * EST SYNC reset counters; move to ACK; notify + * + * =============================================================== + */ +int tegra_ivc_channel_notified(struct tegra_ivc *ivc) +{ + ulong offset; + enum ivc_state peer_state; + + /* Copy the receiver's state out of shared memory. */ + offset = offsetof(struct tegra_ivc_channel_header, w_count); + tegra_ivc_invalidate_counter(ivc, ivc->rx_channel, offset); + peer_state = ACCESS_ONCE(ivc->rx_channel->state); + + if (peer_state == ivc_state_sync) { + /* + * Order observation of ivc_state_sync before stores clearing + * tx_channel. + */ + mb(); + + /* + * Reset tx_channel counters. The remote end is in the SYNC + * state and won't make progress until we change our state, + * so the counters are not in use at this time. + */ + ivc->tx_channel->w_count = 0; + ivc->rx_channel->r_count = 0; + + ivc->w_pos = 0; + ivc->r_pos = 0; + + /* + * Ensure that counters appear cleared before new state can be + * observed. + */ + mb(); + + /* + * Move to ACK state. We have just cleared our counters, so it + * is now safe for the remote end to start using these values. + */ + ivc->tx_channel->state = ivc_state_ack; + offset = offsetof(struct tegra_ivc_channel_header, w_count); + tegra_ivc_flush_counter(ivc, ivc->tx_channel, offset); + + /* + * Notify remote end to observe state transition. + */ + ivc->notify(ivc); + } else if (ivc->tx_channel->state == ivc_state_sync && + peer_state == ivc_state_ack) { + /* + * Order observation of ivc_state_sync before stores clearing + * tx_channel. + */ + mb(); + + /* + * Reset tx_channel counters. The remote end is in the ACK + * state and won't make progress until we change our state, + * so the counters are not in use at this time. + */ + ivc->tx_channel->w_count = 0; + ivc->rx_channel->r_count = 0; + + ivc->w_pos = 0; + ivc->r_pos = 0; + + /* + * Ensure that counters appear cleared before new state can be + * observed. + */ + mb(); + + /* + * Move to ESTABLISHED state. We know that the remote end has + * already cleared its counters, so it is safe to start + * writing/reading on this channel. + */ + ivc->tx_channel->state = ivc_state_established; + offset = offsetof(struct tegra_ivc_channel_header, w_count); + tegra_ivc_flush_counter(ivc, ivc->tx_channel, offset); + + /* + * Notify remote end to observe state transition. + */ + ivc->notify(ivc); + } else if (ivc->tx_channel->state == ivc_state_ack) { + /* + * At this point, we have observed the peer to be in either + * the ACK or ESTABLISHED state. Next, order observation of + * peer state before storing to tx_channel. + */ + mb(); + + /* + * Move to ESTABLISHED state. We know that we have previously + * cleared our counters, and we know that the remote end has + * cleared its counters, so it is safe to start writing/reading + * on this channel. + */ + ivc->tx_channel->state = ivc_state_established; + offset = offsetof(struct tegra_ivc_channel_header, w_count); + tegra_ivc_flush_counter(ivc, ivc->tx_channel, offset); + + /* + * Notify remote end to observe state transition. + */ + ivc->notify(ivc); + } else { + /* + * There is no need to handle any further action. Either the + * channel is already fully established, or we are waiting for + * the remote end to catch up with our current state. Refer + * to the diagram in "IVC State Transition Table" above. + */ + } + + if (ivc->tx_channel->state != ivc_state_established) + return -EAGAIN; + + return 0; +} + +void tegra_ivc_channel_reset(struct tegra_ivc *ivc) +{ + ulong offset; + + ivc->tx_channel->state = ivc_state_sync; + offset = offsetof(struct tegra_ivc_channel_header, w_count); + tegra_ivc_flush_counter(ivc, ivc->tx_channel, offset); + ivc->notify(ivc); +} + +static int check_ivc_params(ulong qbase1, ulong qbase2, uint32_t nframes, + uint32_t frame_size) +{ + int ret = 0; + + BUG_ON(offsetof(struct tegra_ivc_channel_header, w_count) & + (TEGRA_IVC_ALIGN - 1)); + BUG_ON(offsetof(struct tegra_ivc_channel_header, r_count) & + (TEGRA_IVC_ALIGN - 1)); + BUG_ON(sizeof(struct tegra_ivc_channel_header) & + (TEGRA_IVC_ALIGN - 1)); + + if ((uint64_t)nframes * (uint64_t)frame_size >= 0x100000000) { + error("tegra_ivc: nframes * frame_size overflows\n"); + return -EINVAL; + } + + /* + * The headers must at least be aligned enough for counters + * to be accessed atomically. + */ + if ((qbase1 & (TEGRA_IVC_ALIGN - 1)) || + (qbase2 & (TEGRA_IVC_ALIGN - 1))) { + error("tegra_ivc: channel start not aligned\n"); + return -EINVAL; + } + + if (frame_size & (TEGRA_IVC_ALIGN - 1)) { + error("tegra_ivc: frame size not adequately aligned\n"); + return -EINVAL; + } + + if (qbase1 < qbase2) { + if (qbase1 + frame_size * nframes > qbase2) + ret = -EINVAL; + } else { + if (qbase2 + frame_size * nframes > qbase1) + ret = -EINVAL; + } + + if (ret) { + error("tegra_ivc: queue regions overlap\n"); + return ret; + } + + return 0; +} + +int tegra_ivc_init(struct tegra_ivc *ivc, ulong rx_base, ulong tx_base, + uint32_t nframes, uint32_t frame_size, + void (*notify)(struct tegra_ivc *)) +{ + int ret; + + if (!ivc) + return -EINVAL; + + ret = check_ivc_params(rx_base, tx_base, nframes, frame_size); + if (ret) + return ret; + + ivc->rx_channel = (struct tegra_ivc_channel_header *)rx_base; + ivc->tx_channel = (struct tegra_ivc_channel_header *)tx_base; + ivc->w_pos = 0; + ivc->r_pos = 0; + ivc->nframes = nframes; + ivc->frame_size = frame_size; + ivc->notify = notify; + + return 0; +} diff --git a/arch/arm/mach-tegra/lowlevel_init.S b/arch/arm/mach-tegra/lowlevel_init.S deleted file mode 100644 index 1273f94aa38e..000000000000 --- a/arch/arm/mach-tegra/lowlevel_init.S +++ /dev/null @@ -1,40 +0,0 @@ -/* - * SoC-specific setup info - * - * (C) Copyright 2010,2011 - * NVIDIA Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#ifdef CONFIG_ARM64 - .align 5 -ENTRY(reset_cpu) - /* get address for global reset register */ - ldr x1, =PRM_RSTCTRL - ldr w3, [x1] - /* force reset */ - orr w3, w3, #0x10 - str w3, [x1] - mov w0, w0 -1: - b 1b -ENDPROC(reset_cpu) -#else - .align 5 -ENTRY(reset_cpu) - ldr r1, rstctl @ get addr for global reset - @ reg - ldr r3, [r1] - orr r3, r3, #0x10 - str r3, [r1] @ force reset - mov r0, r0 -_loop_forever: - b _loop_forever -rstctl: - .word PRM_RSTCTRL -ENDPROC(reset_cpu) -#endif diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c new file mode 100644 index 000000000000..f36971f7af48 --- /dev/null +++ b/arch/arm/mach-tegra/pmc.c @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_ACCESS_PMC_VIA_SMC +#ifndef CONFIG_ARM64 +#error CONFIG_ACCESS_PMC_VIA_SMC only supported with CONFIG_ARM64 +#endif +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#define NR_SMC_REGS 6 + +#define PMC_READ 0xaa +#define PMC_WRITE 0xbb +#define TEGRA_SIP_PMC_COMMAND_FID 0xC2FFFE00 + +struct pmc_smc_regs { + u64 args[NR_SMC_REGS]; +}; + +#if defined(CONFIG_ACCESS_PMC_VIA_SMC) +static void send_smc(u32 func, struct pmc_smc_regs *regs) +{ + u32 ret = func; + asm volatile( + "mov x0, %0\n" + "ldp x1, x2, [%1, #16 * 0]\n" + "ldp x3, x4, [%1, #16 * 1]\n" + "ldp x5, x6, [%1, #16 * 2]\n" + "smc #0\n" + "mov %0, x0\n" + "stp x1, x2, [%1, #16 * 0]\n" + : "+r" (ret) + : "r" (regs) + : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", + "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17"); + if (ret) + printf("%s: failed (ret=%d)\n", __func__, ret); +} +#endif + +#ifdef CONFIG_ACCESS_PMC_VIA_SMC +static bool get_secure_pmc_setting(void) +{ + int node_offset; + const void *fdt; + static bool secure_pmc; + static bool initialized; + + if (!initialized) { + initialized = true; + fdt = (void *)cboot_boot_x0; + node_offset = fdt_node_offset_by_compatible(fdt, + -1, "nvidia,tegra210-pmc"); + if (node_offset < 0) { + printf("%s: compatible node not found\n", __func__); + secure_pmc = false; + return secure_pmc; + } + if (!fdt_getprop(fdt, node_offset, "nvidia,secure-pmc", NULL)) + secure_pmc = false; + else + secure_pmc = true; + } + return secure_pmc; +} +#endif + +uint32_t tegra_pmc_readl(unsigned long offset) +{ +#ifdef CONFIG_ACCESS_PMC_VIA_SMC + struct pmc_smc_regs regs; + + if (get_secure_pmc_setting()) { + regs.args[0] = PMC_READ; + regs.args[1] = offset; + regs.args[2] = 0; + regs.args[3] = 0; + regs.args[4] = 0; + regs.args[5] = 0; + send_smc(TEGRA_SIP_PMC_COMMAND_FID, ®s); + return (u32)regs.args[0]; + } +#endif + return readl(NV_PA_PMC_BASE + offset); +} + +void tegra_pmc_writel(u32 value, unsigned long offset) +{ +#ifdef CONFIG_ACCESS_PMC_VIA_SMC + struct pmc_smc_regs regs; + + if (get_secure_pmc_setting()) { + regs.args[0] = PMC_WRITE; + regs.args[1] = offset; + regs.args[2] = value; + regs.args[3] = 0; + regs.args[4] = 0; + regs.args[5] = 0; + send_smc(TEGRA_SIP_PMC_COMMAND_FID, ®s); + } +#endif + writel(value, NV_PA_PMC_BASE + offset); +} + +void reset_cpu(ulong addr) +{ + u32 val; + + val = tegra_pmc_readl(offsetof(struct pmc_ctlr, pmc_cntrl)); + val |= (1 << MAIN_RST_BIT); + tegra_pmc_writel(val, offsetof(struct pmc_ctlr, pmc_cntrl)); +} diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index 30ae036bff05..c6a130021293 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */ @@ -12,6 +12,7 @@ #include #include #include +#include #define PWRGATE_TOGGLE 0x30 #define PWRGATE_TOGGLE_START (1 << 8) @@ -25,18 +26,18 @@ static int tegra_powergate_set(enum tegra_powergate id, bool state) u32 value, mask = state ? (1 << id) : 0, old_mask; unsigned long start, timeout = 25; - value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS); + value = tegra_pmc_readl(PWRGATE_STATUS); old_mask = value & (1 << id); if (mask == old_mask) return 0; - writel(PWRGATE_TOGGLE_START | id, NV_PA_PMC_BASE + PWRGATE_TOGGLE); + tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); start = get_timer(0); while (get_timer(start) < timeout) { - value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS); + value = tegra_pmc_readl(PWRGATE_STATUS); if ((value & (1 << id)) == mask) return 0; } @@ -70,7 +71,7 @@ static int tegra_powergate_remove_clamping(enum tegra_powergate id) else value = 1 << id; - writel(value, NV_PA_PMC_BASE + REMOVE_CLAMPING); + tegra_pmc_writel(value, REMOVE_CLAMPING); return 0; } diff --git a/arch/arm/mach-tegra/tegra186/Kconfig b/arch/arm/mach-tegra/tegra186/Kconfig index 97cf23f31f80..1d4e96c15001 100644 --- a/arch/arm/mach-tegra/tegra186/Kconfig +++ b/arch/arm/mach-tegra/tegra186/Kconfig @@ -20,6 +20,9 @@ endchoice config SYS_SOC default "tegra186" +config SYS_INIT_SP_BSS_OFFSET + default 524288 + source "board/nvidia/p2771-0000/Kconfig" endif diff --git a/arch/arm/mach-tegra/tegra186/Makefile b/arch/arm/mach-tegra/tegra186/Makefile index ce4610d8f809..38528f4d8d00 100644 --- a/arch/arm/mach-tegra/tegra186/Makefile +++ b/arch/arm/mach-tegra/tegra186/Makefile @@ -1,8 +1,9 @@ -# Copyright (c) 2016, NVIDIA CORPORATION. +# Copyright (c) 2016-2017, NVIDIA CORPORATION. # # SPDX-License-Identifier: GPL-2.0 -obj-y += ../arm64-mmu.o obj-y += ../board186.o -obj-y += ../lowlevel_init.o -obj-$(CONFIG_DISPLAY_CPUINFO) += ../sys_info.o +obj-y += cache.o +obj-y += ../cboot_board.o +obj-y += ../cboot_ll.o +obj-y += ../cboot_mem.o diff --git a/arch/arm/mach-tegra/tegra186/cache.S b/arch/arm/mach-tegra/tegra186/cache.S new file mode 100644 index 000000000000..3061dc2ecff2 --- /dev/null +++ b/arch/arm/mach-tegra/tegra186/cache.S @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include + +#define SMC_SIP_INVOKE_MCE 0x82FFFF00 +#define MCE_SMC_ROC_FLUSH_CACHE (SMC_SIP_INVOKE_MCE | 11) +#define MCE_SMC_ROC_FLUSH_CACHE_ONLY (SMC_SIP_INVOKE_MCE | 14) +#define MCE_SMC_ROC_CLEAN_CACHE_ONLY (SMC_SIP_INVOKE_MCE | 15) + +ENTRY(__asm_tegra_cache_smc) + mov x1, #0 + mov x2, #0 + mov x3, #0 + mov x4, #0 + mov x5, #0 + mov x6, #0 + smc #0 + mov x0, #0 + ret +ENDPROC(__asm_invalidate_l3_dcache) + +ENTRY(__asm_invalidate_l3_dcache) + mov x0, #(MCE_SMC_ROC_FLUSH_CACHE_ONLY & 0xffff) + movk x0, #(MCE_SMC_ROC_FLUSH_CACHE_ONLY >> 16), lsl #16 + b __asm_tegra_cache_smc +ENDPROC(__asm_invalidate_l3_dcache) + +ENTRY(__asm_flush_l3_dcache) + mov x0, #(MCE_SMC_ROC_CLEAN_CACHE_ONLY & 0xffff) + movk x0, #(MCE_SMC_ROC_CLEAN_CACHE_ONLY >> 16), lsl #16 + b __asm_tegra_cache_smc +ENDPROC(__asm_flush_l3_dcache) + +ENTRY(__asm_invalidate_l3_icache) + mov x0, #(MCE_SMC_ROC_FLUSH_CACHE & 0xffff) + movk x0, #(MCE_SMC_ROC_FLUSH_CACHE >> 16), lsl #16 + b __asm_tegra_cache_smc +ENDPROC(__asm_invalidate_l3_icache) diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach-tegra/tegra210/Kconfig index 055fb124d8b7..99fa9cc54000 100644 --- a/arch/arm/mach-tegra/tegra210/Kconfig +++ b/arch/arm/mach-tegra/tegra210/Kconfig @@ -31,14 +31,26 @@ config TARGET_P2571 help P2571 is a P2530 married to a P1963 I/O board +config TARGET_P3450_PORG + bool "NVIDIA Tegra210 P3450-Porg (Jetson Nano) board" + help + P3450-Porg (Jetson Nano developer kit) is a P3448 CPU board married + to a P3449 I/O board. The combination contains SoC, DRAM, SPI, SD + card slot, HDMI, USB micro-B port, USB3.1 hub/host ports, PCIe/NVMe, + and two GPIO expansion headers. + endchoice config SYS_SOC default "tegra210" +config SYS_INIT_SP_BSS_OFFSET + default 524288 + source "board/nvidia/e2220-1170/Kconfig" source "board/nvidia/p2371-0000/Kconfig" source "board/nvidia/p2371-2180/Kconfig" source "board/nvidia/p2571/Kconfig" +source "board/nvidia/p3450-porg/Kconfig" endif diff --git a/arch/arm/mach-tegra/tegra210/Makefile b/arch/arm/mach-tegra/tegra210/Makefile index b6012fc7baac..fdad46a34765 100644 --- a/arch/arm/mach-tegra/tegra210/Makefile +++ b/arch/arm/mach-tegra/tegra210/Makefile @@ -1,12 +1,14 @@ +# Copyright (c) 2013-2017, NVIDIA CORPORATION. # -# (C) Copyright 2013-2015 -# NVIDIA Corporation -# -# SPDX-License-Identifier: GPL-2.0+ +# SPDX-License-Identifier: GPL-2.0 # obj-y += clock.o obj-y += funcmux.o +obj-y += ../cboot_ll.o +obj-y += ../cboot_mem.o +obj-y += ../cboot_board.o obj-y += pinmux.o obj-y += xusb-padctl.o +obj-y += ../ft_board_info.o obj-y += ../xusb-padctl-common.o diff --git a/arch/arm/mach-tegra/tegra210/cboot.h b/arch/arm/mach-tegra/tegra210/cboot.h new file mode 100644 index 000000000000..58f9218da7cb --- /dev/null +++ b/arch/arm/mach-tegra/tegra210/cboot.h @@ -0,0 +1,17 @@ +/* + * cboot-related code + * + * (C) Copyright 2015-2017 NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CBOOT_H_ +#define _CBOOT_H_ + +#include + +void cboot_init(void); +void cboot_init_late(void); + +#endif diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c index f0052e7934a1..a1edddddc730 100644 --- a/arch/arm/mach-tegra/tegra210/clock.c +++ b/arch/arm/mach-tegra/tegra210/clock.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013-2015 + * (C) Copyright 2013-2016 * NVIDIA Corporation * * SPDX-License-Identifier: GPL-2.0+ @@ -334,7 +334,7 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = { TYPE(PERIPHC_DMIC3, CLOCK_TYPE_NONE), TYPE(PERIPHC_APE, CLOCK_TYPE_NONE), TYPE(PERIPHC_QSPI, CLOCK_TYPE_PC01C00_C42C41TC40), - TYPE(PERIPHC_VI_I2C, CLOCK_TYPE_NONE), + TYPE(PERIPHC_VI_I2C, CLOCK_TYPE_PC2CC3M_T16), TYPE(PERIPHC_USB2_HSIC_TRK, CLOCK_TYPE_NONE), TYPE(PERIPHC_PEX_SATA_USB_RX_BYP, CLOCK_TYPE_NONE), @@ -1204,24 +1204,5 @@ int tegra_plle_enable(void) value &= ~PLLE_SS_CNTL_INTERP_RESET; writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); - /* 7. Enable HW power sequencer for PLLE */ - - value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); - value &= ~PLLE_MISC_IDDQ_SWCTL; - writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); - - value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX); - value &= ~PLLE_AUX_SS_SWCTL; - value &= ~PLLE_AUX_ENABLE_SWCTL; - value |= PLLE_AUX_SS_SEQ_INCLUDE; - value |= PLLE_AUX_USE_LOCKDET; - writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX); - - /* 8. Wait 1 us */ - - udelay(1); - value |= PLLE_AUX_SEQ_ENABLE; - writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX); - return 0; } diff --git a/arch/arm/mach-tegra/tegra210/xusb-padctl.c b/arch/arm/mach-tegra/tegra210/xusb-padctl.c index 9ec93e7c4c4c..d6f53fce19d2 100644 --- a/arch/arm/mach-tegra/tegra210/xusb-padctl.c +++ b/arch/arm/mach-tegra/tegra210/xusb-padctl.c @@ -167,6 +167,17 @@ static int phy_unprepare(struct tegra_xusb_phy *phy) return tegra_xusb_padctl_disable(phy->padctl); } +#define XUSB_PADCTL_USB3_PAD_MUX 0x28 +#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE (1 << 0) +#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0 (1 << 1) +#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1 (1 << 2) +#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2 (1 << 3) +#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3 (1 << 4) +#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4 (1 << 5) +#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK5 (1 << 6) +#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK6 (1 << 7) +#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0 (1 << 8) + #define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK (0xff << 20) #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(x) (((x) & 0xff) << 20) @@ -363,31 +374,6 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy) value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN; padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); - value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); - value &= ~CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL; - value &= ~CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL; - value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET; - value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ; - writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); - - value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); - value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD; - padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); - - value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); - value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD; - padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); - - value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); - value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD; - padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); - - udelay(1); - - value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); - value |= CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE; - writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); - debug("< %s()\n", __func__); return 0; } @@ -435,3 +421,35 @@ void tegra_xusb_padctl_init(const void *fdt) debug("< %s()\n", __func__); } + +void tegra_xusb_padctl_exit(void) +{ + u32 value; + + debug("> %s\n", __func__); + + value = padctl_readl(&padctl, XUSB_PADCTL_USB3_PAD_MUX); + value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE; + value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0; + value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1; + value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2; + value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3; + value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4; + value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK5; + value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK6; + value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0; + padctl_writel(&padctl, value, XUSB_PADCTL_USB3_PAD_MUX); + + value = padctl_readl(&padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); + value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ; + value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK; + value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP(3); + value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE; + padctl_writel(&padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); + + reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 1); + while (padctl.enable) + tegra_xusb_padctl_disable(&padctl); + + debug("< %s()\n", __func__); +} diff --git a/arch/arm/mach-tegra/xusb-padctl-dummy.c b/arch/arm/mach-tegra/xusb-padctl-dummy.c index 65f8d2ea967a..5102d5aef45e 100644 --- a/arch/arm/mach-tegra/xusb-padctl-dummy.c +++ b/arch/arm/mach-tegra/xusb-padctl-dummy.c @@ -37,3 +37,7 @@ int __weak tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy) void __weak tegra_xusb_padctl_init(const void *fdt) { } + +void __weak tegra_xusb_padctl_exit(void) +{ +} diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 9e46f9e815a6..fff175d1b7a2 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -262,6 +262,16 @@ }; }; + pwrdom: power-domain { + compatible = "sandbox,power-domain"; + #power-domain-cells = <1>; + }; + + power-domain-test { + compatible = "sandbox,power-domain-test"; + power-domains = <&pwrdom 2>; + }; + ram { compatible = "sandbox,ram"; }; diff --git a/arch/sandbox/include/asm/power-domain.h b/arch/sandbox/include/asm/power-domain.h new file mode 100644 index 000000000000..cad388549eef --- /dev/null +++ b/arch/sandbox/include/asm/power-domain.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __SANDBOX_POWER_DOMAIN_H +#define __SANDBOX_POWER_DOMAIN_H + +#include + +struct udevice; + +int sandbox_power_domain_query(struct udevice *dev, unsigned long id); + +int sandbox_power_domain_test_get(struct udevice *dev); +int sandbox_power_domain_test_on(struct udevice *dev); +int sandbox_power_domain_test_off(struct udevice *dev); +int sandbox_power_domain_test_free(struct udevice *dev); + +#endif diff --git a/board/nvidia/e2220-1170/e2220-1170.c b/board/nvidia/e2220-1170/e2220-1170.c index d66a72e5204c..4689eb45a925 100644 --- a/board/nvidia/e2220-1170/e2220-1170.c +++ b/board/nvidia/e2220-1170/e2220-1170.c @@ -10,7 +10,6 @@ #include #include #include "../p2571/max77620_init.h" -#include "pinmux-config-e2220-1170.h" void pin_mux_mmc(void) { @@ -31,21 +30,3 @@ void pin_mux_mmc(void) if (ret) printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); } - -/* - * Routine: pinmux_init - * Description: Do individual peripheral pinmux configs - */ -void pinmux_init(void) -{ - pinmux_clear_tristate_input_clamping(); - - gpio_config_table(e2220_1170_gpio_inits, - ARRAY_SIZE(e2220_1170_gpio_inits)); - - pinmux_config_pingrp_table(e2220_1170_pingrps, - ARRAY_SIZE(e2220_1170_pingrps)); - - pinmux_config_drvgrp_table(e2220_1170_drvgrps, - ARRAY_SIZE(e2220_1170_drvgrps)); -} diff --git a/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h b/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h deleted file mode 100644 index 7955ca5cdf83..000000000000 --- a/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h +++ /dev/null @@ -1,277 +0,0 @@ -/* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * THIS FILE IS AUTO-GENERATED - DO NOT EDIT! - * - * To generate this file, use the tegra-pinmux-scripts tool available from - * https://github.com/NVIDIA/tegra-pinmux-scripts - * Run "board-to-uboot.py e2220-1170". - */ - -#ifndef _PINMUX_CONFIG_E2220_1170_H_ -#define _PINMUX_CONFIG_E2220_1170_H_ - -#define GPIO_INIT(_port, _gpio, _init) \ - { \ - .gpio = TEGRA_GPIO(_port, _gpio), \ - .init = TEGRA_GPIO_INIT_##_init, \ - } - -static const struct tegra_gpio_config e2220_1170_gpio_inits[] = { - /* port, pin, init_val */ - GPIO_INIT(A, 5, IN), - GPIO_INIT(A, 6, IN), - GPIO_INIT(B, 4, IN), - GPIO_INIT(E, 6, IN), - GPIO_INIT(G, 2, OUT0), - GPIO_INIT(G, 3, OUT0), - GPIO_INIT(H, 0, OUT0), - GPIO_INIT(H, 1, OUT0), - GPIO_INIT(H, 2, IN), - GPIO_INIT(H, 3, OUT0), - GPIO_INIT(H, 4, OUT0), - GPIO_INIT(H, 5, IN), - GPIO_INIT(H, 6, OUT0), - GPIO_INIT(H, 7, OUT0), - GPIO_INIT(I, 0, OUT0), - GPIO_INIT(I, 1, IN), - GPIO_INIT(I, 2, OUT0), - GPIO_INIT(I, 3, OUT0), - GPIO_INIT(K, 0, IN), - GPIO_INIT(K, 1, OUT0), - GPIO_INIT(K, 2, OUT0), - GPIO_INIT(K, 3, OUT0), - GPIO_INIT(K, 4, IN), - GPIO_INIT(K, 5, OUT0), - GPIO_INIT(K, 6, IN), - GPIO_INIT(K, 7, OUT0), - GPIO_INIT(L, 0, OUT0), - GPIO_INIT(S, 4, OUT0), - GPIO_INIT(S, 5, OUT0), - GPIO_INIT(S, 6, OUT0), - GPIO_INIT(S, 7, OUT0), - GPIO_INIT(T, 0, OUT0), - GPIO_INIT(T, 1, OUT0), - GPIO_INIT(V, 1, OUT0), - GPIO_INIT(V, 2, OUT0), - GPIO_INIT(V, 3, IN), - GPIO_INIT(V, 5, OUT0), - GPIO_INIT(V, 6, OUT0), - GPIO_INIT(X, 0, IN), - GPIO_INIT(X, 1, IN), - GPIO_INIT(X, 2, IN), - GPIO_INIT(X, 3, IN), - GPIO_INIT(X, 4, IN), - GPIO_INIT(X, 5, IN), - GPIO_INIT(X, 6, IN), - GPIO_INIT(X, 7, IN), - GPIO_INIT(Y, 0, IN), - GPIO_INIT(Y, 1, IN), - GPIO_INIT(Z, 0, IN), - GPIO_INIT(Z, 4, OUT0), - GPIO_INIT(BB, 2, OUT0), - GPIO_INIT(BB, 3, OUT0), - GPIO_INIT(BB, 4, IN), - GPIO_INIT(CC, 1, IN), - GPIO_INIT(CC, 5, OUT0), - GPIO_INIT(CC, 6, IN), - GPIO_INIT(CC, 7, OUT0), -}; - -#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ - { \ - .pingrp = PMUX_PINGRP_##_pingrp, \ - .func = PMUX_FUNC_##_mux, \ - .pull = PMUX_PULL_##_pull, \ - .tristate = PMUX_TRI_##_tri, \ - .io = PMUX_PIN_##_io, \ - .od = PMUX_PIN_OD_##_od, \ - .e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \ - .lock = PMUX_PIN_LOCK_DEFAULT, \ - } - -static const struct pmux_pingrp_config e2220_1170_pingrps[] = { - /* pingrp, mux, pull, tri, e_input, od, e_io_hv */ - PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), - PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, UP, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(PEX_WAKE_N_PA2, PE, UP, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), - PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, UP, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PA6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP1_FS_PB0, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP1_DIN_PB1, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP1_DOUT_PB2, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP1_SCLK_PB3, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI2_MOSI_PB4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI2_MISO_PB5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI2_SCK_PB6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI2_CS0_PB7, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI1_MOSI_PC0, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI1_MISO_PC1, SPI1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI1_SCK_PC2, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI1_CS0_PC3, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI1_CS1_PC4, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI4_SCK_PC5, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI4_CS0_PC6, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI4_MOSI_PC7, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI4_MISO_PD0, SPI4, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART3_RX_PD2, UARTC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART3_RTS_PD3, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART3_CTS_PD4, UARTC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DMIC1_CLK_PE0, DMIC1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(DMIC1_DAT_PE1, DMIC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DMIC2_CLK_PE2, DMIC2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(DMIC2_DAT_PE3, DMIC2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DMIC3_CLK_PE4, DMIC3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(DMIC3_DAT_PE5, DMIC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PE6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(UART2_TX_PG0, UART, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART2_RX_PG1, UART, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART2_RTS_PG2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART2_CTS_PG3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(WIFI_RST_PH1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PH6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(AP_WAKE_NFC_PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(NFC_INT_PI1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(GPS_RST_PI3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(DAP4_FS_PJ4, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP4_DIN_PJ5, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP4_DOUT_PJ6, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP4_SCLK_PJ7, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK0, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PK2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PK3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PK4, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PK6, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PL0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PL1, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(CAM_RST_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM_AF_EN_PS5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM_FLASH_EN_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM1_STROBE_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART1_RTS_PU2, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART1_CTS_PU3, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(LCD_RST_PV2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(LCD_GPIO1_PV3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(AP_READY_PV5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(TOUCH_CLK_PV7, TOUCH, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(MODEM_WAKE_AP_PX0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(TOUCH_INT_PX1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(MOTION_INT_PX2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(ALS_PROX_INT_PX3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_SLIDE_SW_PY0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(LCD_TE_PY2, DISPLAYA, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PZ2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PZ3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PZ4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(AUD_MCLK_PBB0, AUD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(GPIO_X1_AUD_PBB3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(GPIO_X3_AUD_PBB4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(SPDIF_OUT_PCC2, SPDIF, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPDIF_IN_PCC3, SPDIF, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(USB_VBUS_EN1_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), - PINCFG(DP_HPD0_PCC6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PCC7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), - PINCFG(SPI2_CS1_PDD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_SCK_PEE0, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(QSPI_CS_N_PEE1, QSPI, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO0_PEE2, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO1_PEE3, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO2_PEE4, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO3_PEE5, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CLK_REQ, SYS, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -}; - -#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ - { \ - .drvgrp = PMUX_DRVGRP_##_drvgrp, \ - .slwf = _slwf, \ - .slwr = _slwr, \ - .drvup = _drvup, \ - .drvdn = _drvdn, \ - .lpmd = PMUX_LPMD_##_lpmd, \ - .schmt = PMUX_SCHMT_##_schmt, \ - .hsm = PMUX_HSM_##_hsm, \ - } - -static const struct pmux_drvgrp_config e2220_1170_drvgrps[] = { -}; - -#endif /* PINMUX_CONFIG_E2220_1170_H */ diff --git a/board/nvidia/p2371-0000/p2371-0000.c b/board/nvidia/p2371-0000/p2371-0000.c index 9df543a4c9e8..4689eb45a925 100644 --- a/board/nvidia/p2371-0000/p2371-0000.c +++ b/board/nvidia/p2371-0000/p2371-0000.c @@ -10,7 +10,6 @@ #include #include #include "../p2571/max77620_init.h" -#include "pinmux-config-p2371-0000.h" void pin_mux_mmc(void) { @@ -31,21 +30,3 @@ void pin_mux_mmc(void) if (ret) printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); } - -/* - * Routine: pinmux_init - * Description: Do individual peripheral pinmux configs - */ -void pinmux_init(void) -{ - pinmux_clear_tristate_input_clamping(); - - gpio_config_table(p2371_0000_gpio_inits, - ARRAY_SIZE(p2371_0000_gpio_inits)); - - pinmux_config_pingrp_table(p2371_0000_pingrps, - ARRAY_SIZE(p2371_0000_pingrps)); - - pinmux_config_drvgrp_table(p2371_0000_drvgrps, - ARRAY_SIZE(p2371_0000_drvgrps)); -} diff --git a/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h b/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h deleted file mode 100644 index 24acbccd97b2..000000000000 --- a/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h +++ /dev/null @@ -1,268 +0,0 @@ -/* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * THIS FILE IS AUTO-GENERATED - DO NOT EDIT! - * - * To generate this file, use the tegra-pinmux-scripts tool available from - * https://github.com/NVIDIA/tegra-pinmux-scripts - * Run "board-to-uboot.py p2371-0000". - */ - -#ifndef _PINMUX_CONFIG_P2371_0000_H_ -#define _PINMUX_CONFIG_P2371_0000_H_ - -#define GPIO_INIT(_port, _gpio, _init) \ - { \ - .gpio = TEGRA_GPIO(_port, _gpio), \ - .init = TEGRA_GPIO_INIT_##_init, \ - } - -static const struct tegra_gpio_config p2371_0000_gpio_inits[] = { - /* port, pin, init_val */ - GPIO_INIT(A, 5, IN), - GPIO_INIT(E, 4, OUT0), - GPIO_INIT(E, 6, IN), - GPIO_INIT(G, 0, IN), - GPIO_INIT(G, 3, OUT0), - GPIO_INIT(H, 0, OUT0), - GPIO_INIT(H, 2, IN), - GPIO_INIT(H, 3, OUT0), - GPIO_INIT(H, 4, OUT0), - GPIO_INIT(H, 5, IN), - GPIO_INIT(H, 6, OUT0), - GPIO_INIT(H, 7, OUT0), - GPIO_INIT(I, 0, OUT0), - GPIO_INIT(I, 1, IN), - GPIO_INIT(I, 2, OUT0), - GPIO_INIT(I, 3, OUT0), - GPIO_INIT(K, 4, IN), - GPIO_INIT(K, 5, OUT0), - GPIO_INIT(K, 6, IN), - GPIO_INIT(K, 7, OUT0), - GPIO_INIT(L, 0, OUT0), - GPIO_INIT(S, 4, OUT0), - GPIO_INIT(S, 5, OUT0), - GPIO_INIT(S, 6, OUT0), - GPIO_INIT(S, 7, OUT0), - GPIO_INIT(T, 0, OUT0), - GPIO_INIT(T, 1, OUT0), - GPIO_INIT(V, 1, OUT0), - GPIO_INIT(V, 2, OUT0), - GPIO_INIT(V, 5, OUT0), - GPIO_INIT(V, 6, OUT0), - GPIO_INIT(V, 7, OUT1), - GPIO_INIT(X, 0, IN), - GPIO_INIT(X, 1, IN), - GPIO_INIT(X, 2, IN), - GPIO_INIT(X, 3, IN), - GPIO_INIT(X, 4, IN), - GPIO_INIT(X, 5, IN), - GPIO_INIT(X, 6, IN), - GPIO_INIT(X, 7, IN), - GPIO_INIT(Y, 1, IN), - GPIO_INIT(Z, 0, IN), - GPIO_INIT(Z, 4, OUT0), - GPIO_INIT(BB, 2, OUT0), - GPIO_INIT(BB, 3, OUT0), - GPIO_INIT(CC, 1, IN), - GPIO_INIT(CC, 6, IN), - GPIO_INIT(CC, 7, OUT0), -}; - -#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ - { \ - .pingrp = PMUX_PINGRP_##_pingrp, \ - .func = PMUX_FUNC_##_mux, \ - .pull = PMUX_PULL_##_pull, \ - .tristate = PMUX_TRI_##_tri, \ - .io = PMUX_PIN_##_io, \ - .od = PMUX_PIN_OD_##_od, \ - .e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \ - .lock = PMUX_PIN_LOCK_DEFAULT, \ - } - -static const struct pmux_pingrp_config p2371_0000_pingrps[] = { - /* pingrp, mux, pull, tri, e_input, od, e_io_hv */ - PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH), - PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(PEX_WAKE_N_PA2, PE, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH), - PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PA6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(DAP1_FS_PB0, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP1_DIN_PB1, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP1_DOUT_PB2, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP1_SCLK_PB3, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI2_MOSI_PB4, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI2_MISO_PB5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI2_SCK_PB6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI2_CS0_PB7, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI1_MOSI_PC0, SPI1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI1_MISO_PC1, SPI1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI1_SCK_PC2, SPI1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI1_CS0_PC3, SPI1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI1_CS1_PC4, SPI1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI4_SCK_PC5, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI4_CS0_PC6, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI4_MOSI_PC7, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPI4_MISO_PD0, SPI4, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART3_RX_PD2, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART3_RTS_PD3, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART3_CTS_PD4, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DMIC1_CLK_PE0, DMIC1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(DMIC1_DAT_PE1, DMIC1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DMIC2_CLK_PE2, DMIC2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(DMIC2_DAT_PE3, DMIC2, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DMIC3_CLK_PE4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(DMIC3_DAT_PE5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(PE6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(UART2_TX_PG0, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART2_RX_PG1, UARTB, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART2_RTS_PG2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART2_CTS_PG3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(WIFI_RST_PH1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PH6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(AP_WAKE_NFC_PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(NFC_INT_PI1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(GPS_RST_PI3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(DAP4_FS_PJ4, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP4_DIN_PJ5, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP4_DOUT_PJ6, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP4_SCLK_PJ7, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK0, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK1, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK2, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK3, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK4, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PK6, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PL0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PL1, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(CAM_RST_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM_AF_EN_PS5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM_FLASH_EN_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM1_STROBE_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART1_RTS_PU2, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART1_CTS_PU3, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(LCD_RST_PV2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(LCD_GPIO1_PV3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(AP_READY_PV5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(TOUCH_CLK_PV7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(MODEM_WAKE_AP_PX0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(TOUCH_INT_PX1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(MOTION_INT_PX2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(ALS_PROX_INT_PX3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_SLIDE_SW_PY0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(LCD_TE_PY2, DISPLAYA, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PZ2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(PZ3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(PZ4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(AUD_MCLK_PBB0, AUD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(GPIO_X1_AUD_PBB3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(GPIO_X3_AUD_PBB4, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(SPDIF_OUT_PCC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPDIF_IN_PCC3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(USB_VBUS_EN1_PCC5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), - PINCFG(DP_HPD0_PCC6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PCC7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), - PINCFG(SPI2_CS1_PDD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_SCK_PEE0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_CS_N_PEE1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO0_PEE2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO1_PEE3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO2_PEE4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO3_PEE5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CLK_REQ, SYS, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -}; - -#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ - { \ - .drvgrp = PMUX_DRVGRP_##_drvgrp, \ - .slwf = _slwf, \ - .slwr = _slwr, \ - .drvup = _drvup, \ - .drvdn = _drvdn, \ - .lpmd = PMUX_LPMD_##_lpmd, \ - .schmt = PMUX_SCHMT_##_schmt, \ - .hsm = PMUX_HSM_##_hsm, \ - } - -static const struct pmux_drvgrp_config p2371_0000_drvgrps[] = { -}; - -#endif /* PINMUX_CONFIG_P2371_0000_H */ diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c index 0f587eaaa796..99593b93fbbe 100644 --- a/board/nvidia/p2371-2180/p2371-2180.c +++ b/board/nvidia/p2371-2180/p2371-2180.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013-2015 + * (C) Copyright 2013-2019 * NVIDIA Corporation * * SPDX-License-Identifier: GPL-2.0+ @@ -7,10 +7,10 @@ #include #include +#include #include #include #include "../p2571/max77620_init.h" -#include "pinmux-config-p2371-2180.h" void pin_mux_mmc(void) { @@ -30,24 +30,28 @@ void pin_mux_mmc(void) ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1); if (ret) printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); -} - -/* - * Routine: pinmux_init - * Description: Do individual peripheral pinmux configs - */ -void pinmux_init(void) -{ - pinmux_clear_tristate_input_clamping(); - - gpio_config_table(p2371_2180_gpio_inits, - ARRAY_SIZE(p2371_2180_gpio_inits)); - pinmux_config_pingrp_table(p2371_2180_pingrps, - ARRAY_SIZE(p2371_2180_pingrps)); + /* Disable LDO4 discharge */ + ret = dm_i2c_read(dev, MAX77620_CNFG2_L4_REG, &val, 1); + if (ret) { + printf("i2c_read 0 0x3c 0x2c failed: %d\n", ret); + } else { + val &= ~BIT(1); /* ADE */ + ret = dm_i2c_write(dev, MAX77620_CNFG2_L4_REG, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x2c failed: %d\n", ret); + } - pinmux_config_drvgrp_table(p2371_2180_drvgrps, - ARRAY_SIZE(p2371_2180_drvgrps)); + /* Set MBLPD */ + ret = dm_i2c_read(dev, MAX77620_CNFGGLBL1_REG, &val, 1); + if (ret) { + printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret); + } else { + val |= BIT(6); /* MBLPD */ + ret = dm_i2c_write(dev, MAX77620_CNFGGLBL1_REG, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret); + } } #ifdef CONFIG_PCI_TEGRA @@ -73,3 +77,4 @@ int tegra_pcie_board_init(void) return 0; } #endif /* PCI */ + diff --git a/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h b/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h deleted file mode 100644 index 601728e4693a..000000000000 --- a/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h +++ /dev/null @@ -1,279 +0,0 @@ -/* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * THIS FILE IS AUTO-GENERATED - DO NOT EDIT! - * - * To generate this file, use the tegra-pinmux-scripts tool available from - * https://github.com/NVIDIA/tegra-pinmux-scripts - * Run "board-to-uboot.py p2371-2180". - */ - -#ifndef _PINMUX_CONFIG_P2371_2180_H_ -#define _PINMUX_CONFIG_P2371_2180_H_ - -#define GPIO_INIT(_port, _gpio, _init) \ - { \ - .gpio = TEGRA_GPIO(_port, _gpio), \ - .init = TEGRA_GPIO_INIT_##_init, \ - } - -static const struct tegra_gpio_config p2371_2180_gpio_inits[] = { - /* port, pin, init_val */ - GPIO_INIT(A, 5, IN), - GPIO_INIT(B, 0, IN), - GPIO_INIT(B, 1, IN), - GPIO_INIT(B, 2, IN), - GPIO_INIT(B, 3, IN), - GPIO_INIT(C, 0, IN), - GPIO_INIT(C, 1, IN), - GPIO_INIT(C, 2, IN), - GPIO_INIT(C, 3, IN), - GPIO_INIT(C, 4, IN), - GPIO_INIT(E, 4, IN), - GPIO_INIT(E, 5, IN), - GPIO_INIT(E, 6, IN), - GPIO_INIT(H, 0, OUT0), - GPIO_INIT(H, 1, OUT0), - GPIO_INIT(H, 2, IN), - GPIO_INIT(H, 3, OUT0), - GPIO_INIT(H, 4, OUT0), - GPIO_INIT(H, 5, IN), - GPIO_INIT(H, 6, IN), - GPIO_INIT(H, 7, IN), - GPIO_INIT(I, 0, OUT0), - GPIO_INIT(I, 1, IN), - GPIO_INIT(I, 2, OUT0), - GPIO_INIT(K, 4, IN), - GPIO_INIT(K, 5, OUT0), - GPIO_INIT(K, 6, IN), - GPIO_INIT(K, 7, IN), - GPIO_INIT(L, 1, IN), - GPIO_INIT(S, 4, OUT0), - GPIO_INIT(S, 5, OUT0), - GPIO_INIT(S, 6, OUT0), - GPIO_INIT(S, 7, OUT0), - GPIO_INIT(T, 0, OUT0), - GPIO_INIT(T, 1, OUT0), - GPIO_INIT(U, 2, IN), - GPIO_INIT(U, 3, IN), - GPIO_INIT(V, 1, OUT0), - GPIO_INIT(V, 2, OUT0), - GPIO_INIT(V, 3, IN), - GPIO_INIT(V, 5, OUT0), - GPIO_INIT(V, 6, OUT0), - GPIO_INIT(X, 0, IN), - GPIO_INIT(X, 1, IN), - GPIO_INIT(X, 2, IN), - GPIO_INIT(X, 3, IN), - GPIO_INIT(X, 4, IN), - GPIO_INIT(X, 5, IN), - GPIO_INIT(X, 6, IN), - GPIO_INIT(X, 7, IN), - GPIO_INIT(Y, 0, IN), - GPIO_INIT(Y, 1, IN), - GPIO_INIT(Z, 0, IN), - GPIO_INIT(Z, 2, IN), - GPIO_INIT(Z, 3, OUT0), - GPIO_INIT(BB, 0, IN), - GPIO_INIT(BB, 2, OUT0), - GPIO_INIT(BB, 3, IN), - GPIO_INIT(CC, 1, IN), -}; - -#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ - { \ - .pingrp = PMUX_PINGRP_##_pingrp, \ - .func = PMUX_FUNC_##_mux, \ - .pull = PMUX_PULL_##_pull, \ - .tristate = PMUX_TRI_##_tri, \ - .io = PMUX_PIN_##_io, \ - .od = PMUX_PIN_OD_##_od, \ - .e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \ - .lock = PMUX_PIN_LOCK_DEFAULT, \ - } - -static const struct pmux_pingrp_config p2371_2180_pingrps[] = { - /* pingrp, mux, pull, tri, e_input, od, e_io_hv */ - PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH), - PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(PEX_WAKE_N_PA2, PE, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH), - PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PA6, SATA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(DAP1_FS_PB0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP1_DIN_PB1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP1_DOUT_PB2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP1_SCLK_PB3, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI2_MOSI_PB4, SPI2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI2_MISO_PB5, SPI2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI2_SCK_PB6, SPI2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI2_CS0_PB7, SPI2, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI1_MOSI_PC0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI1_MISO_PC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI1_SCK_PC2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI1_CS0_PC3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI1_CS1_PC4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI4_SCK_PC5, SPI4, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI4_CS0_PC6, SPI4, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI4_MOSI_PC7, SPI4, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SPI4_MISO_PD0, SPI4, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART3_RX_PD2, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART3_RTS_PD3, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART3_CTS_PD4, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DMIC1_CLK_PE0, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DMIC1_DAT_PE1, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DMIC2_CLK_PE2, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DMIC2_DAT_PE3, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DMIC3_CLK_PE4, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DMIC3_DAT_PE5, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PE6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(UART2_TX_PG0, UARTB, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART2_RX_PG1, UARTB, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART2_RTS_PG2, UARTB, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART2_CTS_PG3, UARTB, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(WIFI_RST_PH1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PH6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(AP_WAKE_NFC_PH7, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(NFC_INT_PI1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(GPS_RST_PI3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(DAP4_FS_PJ4, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP4_DIN_PJ5, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP4_DOUT_PJ6, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP4_SCLK_PJ7, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK0, I2S5B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK1, I2S5B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK2, I2S5B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK3, I2S5B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PK6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PK7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PL0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(PL1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(CAM_RST_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM_AF_EN_PS5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM_FLASH_EN_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM1_STROBE_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART1_RTS_PU2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(UART1_CTS_PU3, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(LCD_RST_PV2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(LCD_GPIO1_PV3, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(AP_READY_PV5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(TOUCH_CLK_PV7, TOUCH, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(MODEM_WAKE_AP_PX0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(TOUCH_INT_PX1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(MOTION_INT_PX2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(ALS_PROX_INT_PX3, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_SLIDE_SW_PY0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(LCD_TE_PY2, DISPLAYA, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PZ2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PZ3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PZ4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(AUD_MCLK_PBB0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(GPIO_X1_AUD_PBB3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(GPIO_X3_AUD_PBB4, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL), - PINCFG(SPDIF_OUT_PCC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SPDIF_IN_PCC3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(USB_VBUS_EN1_PCC5, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - PINCFG(DP_HPD0_PCC6, DP, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(PCC7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), - PINCFG(SPI2_CS1_PDD0, SPI2, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(QSPI_SCK_PEE0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_CS_N_PEE1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO0_PEE2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO1_PEE3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO2_PEE4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO3_PEE5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), - PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(CLK_REQ, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -}; - -#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ - { \ - .drvgrp = PMUX_DRVGRP_##_drvgrp, \ - .slwf = _slwf, \ - .slwr = _slwr, \ - .drvup = _drvup, \ - .drvdn = _drvdn, \ - .lpmd = PMUX_LPMD_##_lpmd, \ - .schmt = PMUX_SCHMT_##_schmt, \ - .hsm = PMUX_HSM_##_hsm, \ - } - -static const struct pmux_drvgrp_config p2371_2180_drvgrps[] = { -}; - -#endif /* PINMUX_CONFIG_P2371_2180_H */ diff --git a/board/nvidia/p2571/max77620_init.h b/board/nvidia/p2571/max77620_init.h index 92c3719112a4..39e550149aae 100644 --- a/board/nvidia/p2571/max77620_init.h +++ b/board/nvidia/p2571/max77620_init.h @@ -13,6 +13,8 @@ #define MAX77620_I2C_ADDR 0x78 #define MAX77620_I2C_ADDR_7BIT 0x3C +#define MAX77620_CNFGGLBL1_REG 0x00 + #define MAX77620_SD0_REG 0x16 #define MAX77620_SD1_REG 0x17 #define MAX77620_SD2_REG 0x18 diff --git a/board/nvidia/p2771-0000/p2771-0000.c b/board/nvidia/p2771-0000/p2771-0000.c index 4ba8ebc0dce8..529ed9d4547a 100644 --- a/board/nvidia/p2771-0000/p2771-0000.c +++ b/board/nvidia/p2771-0000/p2771-0000.c @@ -5,3 +5,51 @@ */ #include +#include +#include "../p2571/max77620_init.h" + +int tegra_board_init(void) +{ + struct udevice *dev; + uchar val; + int ret; + + /* Turn on MAX77620 LDO3 to 3.3V for SD card power */ + debug("%s: Set LDO3 for VDDIO_SDMMC_AP power to 3.3V\n", __func__); + ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev); + if (ret) { + printf("%s: Cannot find MAX77620 I2C chip\n", __func__); + return ret; + } + /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ + val = 0xF2; + ret = dm_i2c_write(dev, MAX77620_CNFG1_L3_REG, &val, 1); + if (ret) { + printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); + return ret; + } + + return 0; +} + +int tegra_pcie_board_init(void) +{ + struct udevice *dev; + uchar val; + int ret; + + /* Turn on MAX77620 LDO7 to 1.05V for PEX power */ + debug("%s: Set LDO7 for PEX power to 1.05V\n", __func__); + ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev); + if (ret) { + printf("%s: Cannot find MAX77620 I2C chip\n", __func__); + return -1; + } + /* 0xC5 for 1.05v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ + val = 0xC5; + ret = dm_i2c_write(dev, MAX77620_CNFG1_L7_REG, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x31 failed: %d\n", ret); + + return 0; +} diff --git a/board/nvidia/p3450-porg/Kconfig b/board/nvidia/p3450-porg/Kconfig new file mode 100644 index 000000000000..34d2def933b2 --- /dev/null +++ b/board/nvidia/p3450-porg/Kconfig @@ -0,0 +1,15 @@ +if TARGET_P3450_PORG + +config SYS_BOARD + default "p3450-porg" + +config SYS_VENDOR + default "nvidia" + +config SYS_CONFIG_NAME + default "p3450-porg" + +config NANO_EMMC + bool "Module has eMMC" + +endif diff --git a/board/nvidia/p3450-porg/MAINTAINERS b/board/nvidia/p3450-porg/MAINTAINERS new file mode 100644 index 000000000000..d3fa05f15b69 --- /dev/null +++ b/board/nvidia/p3450-porg/MAINTAINERS @@ -0,0 +1,6 @@ +P3450-porg BOARD +M: Tom Warren +S: Maintained +F: board/nvidia/p3450-porg/ +F: include/configs/p3450-porg.h +F: configs/p3450-porg_defconfig diff --git a/board/nvidia/p3450-porg/Makefile b/board/nvidia/p3450-porg/Makefile new file mode 100644 index 000000000000..1fe9ff4586a1 --- /dev/null +++ b/board/nvidia/p3450-porg/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2018 +# NVIDIA Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += p3450-porg.o diff --git a/board/nvidia/p3450-porg/p3450-porg.c b/board/nvidia/p3450-porg/p3450-porg.c new file mode 100644 index 000000000000..ca8f5d8b9abb --- /dev/null +++ b/board/nvidia/p3450-porg/p3450-porg.c @@ -0,0 +1,141 @@ +/* + * (C) Copyright 2018-2019 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include "../p2571/max77620_init.h" + +#define ETH_ALEN 6 + +void pin_mux_mmc(void) +{ + struct udevice *dev; + uchar val; + int ret; + + /* Turn on MAX77620 LDO2 to 3.3V for SD card power */ + debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__); + ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev); + if (ret) { + printf("%s: Cannot find MAX77620 I2C chip\n", __func__); + return; + } + /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ + val = 0xF2; + ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); + + /* Disable LDO4 discharge */ + ret = dm_i2c_read(dev, MAX77620_CNFG2_L4_REG, &val, 1); + if (ret) { + printf("i2c_read 0 0x3c 0x2c failed: %d\n", ret); + } else { + val &= ~BIT(1); /* ADE */ + ret = dm_i2c_write(dev, MAX77620_CNFG2_L4_REG, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x2c failed: %d\n", ret); + } + + /* Set MBLPD */ + ret = dm_i2c_read(dev, MAX77620_CNFGGLBL1_REG, &val, 1); + if (ret) { + printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret); + } else { + val |= BIT(6); /* MBLPD */ + ret = dm_i2c_write(dev, MAX77620_CNFGGLBL1_REG, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret); + } +} + +#ifdef CONFIG_PCI_TEGRA +int tegra_pcie_board_init(void) +{ + struct udevice *dev; + uchar val; + int ret; + + /* Turn on MAX77620 LDO1 to 1.05V for PEX power */ + debug("%s: Set LDO1 for PEX power to 1.05V\n", __func__); + ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev); + if (ret) { + printf("%s: Cannot find MAX77620 I2C chip\n", __func__); + return -1; + } + /* 0xCA for 1.05v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ + val = 0xCA; + ret = dm_i2c_write(dev, MAX77620_CNFG1_L1_REG, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x25 failed: %d\n", ret); + + return 0; +} +#endif /* PCI */ + +/* + * Attempt to use /chosen/nvidia,ethernet-mac in the cboot DTB as U-Boot's + * ethaddr environment variable if possible. + */ +int set_ethaddr_from_cboot(const void *fdt) +{ + int node, len, err; + const uchar *mac; + + /* Already a valid address in the environment? If so, keep it */ + if (getenv("ethaddr")) + return 0; + + node = fdt_path_offset(fdt, "/chosen"); + if (node < 0) { + printf("Can't find /chosen node in CBoot DTB\n"); + return node; + } + mac = fdt_getprop(fdt, node, "nvidia,ethernet-mac", &len); + if (!mac) { + printf("Can't find nvidia,ethernet-mac property in CBoot DTB\n"); + return -ENOENT; + } + + debug("%s: MAC address: %s\n", __func__, mac); + + /* Set MAC address */ + err = setenv("ethaddr", (void *)mac); + if (err) { + printf("Failed to set ethaddr from CBoot DTB: %d\n", err); + return err; + } + + return 0; +} + +int ft_board_setup(void *fdt, bd_t *bd) +{ + uchar mac[ETH_ALEN]; + int node, err; + + node = fdt_path_offset(fdt, "/pcie@1003000/pci@2,0/ethernet@0,0"); + if (node < 0) + return 0; + + debug("PCI ethernet device tree node found\n"); + + if (eth_getenv_enetaddr("ethaddr", mac)) { + err = fdt_setprop(fdt, node, "mac-address", mac, ETH_ALEN); + if (err < 0) + return 0; + + debug("MAC address set: %02x:%02x:%02x:%02x:%02x:%02x\n", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + } + + return 0; +} diff --git a/board/nvidia/venice2/as3722_init.c b/board/nvidia/venice2/as3722_init.c index 960fea7ee7e3..1770ec2468de 100644 --- a/board/nvidia/venice2/as3722_init.c +++ b/board/nvidia/venice2/as3722_init.c @@ -32,7 +32,18 @@ void pmic_enable_cpu_vdd(void) { debug("%s entry\n", __func__); - /* Don't need to set up VDD_CORE - already done - by OTP */ +#ifdef AS3722_SD1VOLTAGE_DATA + /* Set up VDD_CORE, for boards where OTP is incorrect*/ + debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__); + /* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */ + tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); + tegra_i2c_ll_write_data(AS3722_SD1VOLTAGE_DATA, I2C_SEND_2_BYTES); + /* + * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. + * tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES); + */ + udelay(10 * 1000); +#endif debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__); /* diff --git a/board/nvidia/venice2/as3722_init.h b/board/nvidia/venice2/as3722_init.h index 992b11f64351..c6b1247149e4 100644 --- a/board/nvidia/venice2/as3722_init.h +++ b/board/nvidia/venice2/as3722_init.h @@ -25,8 +25,10 @@ #endif #define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG) -#define AS3722_SD1VOLTAGE_DATA (0x3200 | AS3722_SD1VOLTAGE_REG) +#ifdef CONFIG_TARGET_JETSON_TK1 +#define AS3722_SD1VOLTAGE_DATA (0x2800 | AS3722_SD1VOLTAGE_REG) #define AS3722_SD1CONTROL_DATA (0x0200 | AS3722_SDCONTROL_REG) +#endif #define AS3722_SD6CONTROL_DATA (0x4000 | AS3722_SDCONTROL_REG) #define AS3722_SD6VOLTAGE_DATA (0x2800 | AS3722_SD6VOLTAGE_REG) diff --git a/cmd/Kconfig b/cmd/Kconfig index d69b817c827b..ddd829901798 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -522,6 +522,16 @@ config CMD_LINK_LOCAL help Acquire a network IP address using the link-local protocol +config BOOTP_PREFER_SERVERIP + bool "serverip variable takes precedent over DHCP server IP." + depends on CMD_NET + help + By default a BOOTP/DHCP reply will overwrite the 'serverip' variable. + + With this option enabled, the 'serverip' variable in the environment + takes precedence over DHCP server IP and will only be set by the DHCP + server if not already set in the environment. + endmenu menu "Misc commands" diff --git a/cmd/bootm.c b/cmd/bootm.c index 16fdea5507be..1c83e9701fbc 100644 --- a/cmd/bootm.c +++ b/cmd/bootm.c @@ -22,6 +22,8 @@ #include #include #include +#include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -645,7 +647,7 @@ struct Image_header { uint32_t code1; /* Executable code */ uint64_t text_offset; /* Image load offset, LE */ uint64_t image_size; /* Effective Image size, LE */ - uint64_t res1; /* reserved */ + uint64_t flags; /* Kernel flags, LE */ uint64_t res2; /* reserved */ uint64_t res3; /* reserved */ uint64_t res4; /* reserved */ @@ -659,7 +661,7 @@ static int booti_setup(bootm_headers_t *images) { struct Image_header *ih; uint64_t dst; - uint64_t image_size; + uint64_t image_size, text_offset; ih = (struct Image_header *)map_sysmem(images->ep, 0); @@ -667,19 +669,33 @@ static int booti_setup(bootm_headers_t *images) puts("Bad Linux ARM64 Image magic!\n"); return 1; } - + + /* + * Prior to Linux commit a2c1d73b94ed, the text_offset field + * is of unknown endianness. In these cases, the image_size + * field is zero, and we can assume a fixed value of 0x80000. + */ if (ih->image_size == 0) { puts("Image lacks image_size field, assuming 16MiB\n"); image_size = 16 << 20; + text_offset = 0x80000; } else { image_size = le64_to_cpu(ih->image_size); + text_offset = le64_to_cpu(ih->text_offset); } /* - * If we are not at the correct run-time location, set the new - * correct location and then move the image there. + * If bit 3 of the flags field is set, the 2MB aligned base of the + * kernel image can be anywhere in physical memory, so respect + * images->ep. Otherwise, relocate the image to the base of RAM + * since memory below it is not accessible via the linear mapping. */ - dst = gd->bd->bi_dram[0].start + le64_to_cpu(ih->text_offset); + if (le64_to_cpu(ih->flags) & BIT(3)) + dst = images->ep - text_offset; + else + dst = gd->bd->bi_dram[0].start; + + dst = ALIGN(dst, SZ_2M) + text_offset; unmap_sysmem(ih); diff --git a/cmd/fdt.c b/cmd/fdt.c index 898217ffe5f8..16c7c580df9d 100644 --- a/cmd/fdt.c +++ b/cmd/fdt.c @@ -244,7 +244,7 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* * Set the value of a property in the working_fdt. */ - } else if (argv[1][0] == 's') { + } else if (strncmp(argv[1], "se", 2) == 0) { char *pathp; /* path */ char *prop; /* property */ int nodeoffset; /* node offset from libfdt */ diff --git a/cmd/md5sum.c b/cmd/md5sum.c index 23bb81e88cbf..e653b80deb85 100644 --- a/cmd/md5sum.c +++ b/cmd/md5sum.c @@ -13,6 +13,7 @@ #include #include #include +#include "../lib/md5.c" /* * Store the resulting sum to an address or variable diff --git a/cmd/pxe.c b/cmd/pxe.c index 9434a18177a7..7de0559e4209 100644 --- a/cmd/pxe.c +++ b/cmd/pxe.c @@ -18,6 +18,9 @@ #include "menu.h" #include "cli.h" +#ifdef CONFIG_HUSH_PARSER +#include "cli_hush.h" +#endif #define MAX_TFTP_PATH_LEN 127 @@ -681,7 +684,9 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label *label) if ((label->ipappend & 0x3) || label->append) { char bootargs[CONFIG_SYS_CBSIZE] = ""; char finalbootargs[CONFIG_SYS_CBSIZE]; - +#ifdef CONFIG_HUSH_PARSER + char *distro_bootpart, *hush_bootpart; +#endif if (strlen(label->append ?: "") + strlen(ip_str) + strlen(mac_str) + 1 > sizeof(bootargs)) { printf("bootarg overflow %zd+%zd+%zd+1 > %zd\n", @@ -696,9 +701,23 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label *label) strcat(bootargs, ip_str); strcat(bootargs, mac_str); +#ifdef CONFIG_HUSH_PARSER + distro_bootpart = getenv("distro_bootpart"); + hush_bootpart = get_local_var("distro_bootpart"); + if (hush_bootpart && !distro_bootpart) { + char partnumstr[32]; + unsigned long partnum = simple_strtoul(hush_bootpart, NULL, 16); + snprintf(partnumstr, sizeof(partnumstr), "%lu", partnum); + setenv("distro_bootpart", partnumstr); + } +#endif cli_simple_process_macros(bootargs, finalbootargs); setenv("bootargs", finalbootargs); printf("append: %s\n", finalbootargs); +#ifdef CONFIG_HUSH_PARSER + if (hush_bootpart && !distro_bootpart) + setenv("distro_bootpart", NULL); +#endif } bootm_argv[1] = getenv("kernel_addr_r"); diff --git a/common/autoboot.c b/common/autoboot.c index c52bad84a4d0..1c618669358e 100644 --- a/common/autoboot.c +++ b/common/autoboot.c @@ -255,7 +255,7 @@ static int __abortboot(int bootdelay) } # endif /* CONFIG_AUTOBOOT_KEYED */ -static int abortboot(int bootdelay) +int abortboot(int bootdelay) { int abort = 0; diff --git a/common/fdt_support.c b/common/fdt_support.c index 5d8eb12f1073..9ca151d8f873 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -450,11 +450,20 @@ int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks) return 0; len = fdt_pack_reg(blob, tmp, start, size, banks); - +add_reg: err = fdt_setprop(blob, nodeoffset, "reg", tmp, len); - if (err < 0) { - printf("WARNING: could not set %s %s.\n", - "reg", fdt_strerror(err)); + if (err == -FDT_ERR_NOSPACE) { + err = fdt_increase_size(blob, 512); + debug("Increased FDT blob size by 512 bytes\n"); + if (!err) + goto add_reg; /* retry setprop */ + else { + printf("Can't increase blob size: %s\n", + fdt_strerror(err)); + return err; + } + } else if (err < 0) { + printf("Can't add memory node: %s\n", fdt_strerror(err)); return err; } return 0; @@ -997,8 +1006,8 @@ static void of_dump_addr(const char *s, const fdt32_t *addr, int na) { } struct of_bus { const char *name; const char *addresses; - int (*match)(void *blob, int parentoffset); - void (*count_cells)(void *blob, int parentoffset, + int (*match)(const void *blob, int parentoffset); + void (*count_cells)(const void *blob, int parentoffset, int *addrc, int *sizec); u64 (*map)(fdt32_t *addr, const fdt32_t *range, int na, int ns, int pna); @@ -1006,7 +1015,7 @@ struct of_bus { }; /* Default translator (generic bus) */ -void of_bus_default_count_cells(void *blob, int parentoffset, +void of_bus_default_count_cells(const void *blob, int parentoffset, int *addrc, int *sizec) { const fdt32_t *prop; @@ -1055,7 +1064,7 @@ static int of_bus_default_translate(fdt32_t *addr, u64 offset, int na) #ifdef CONFIG_OF_ISA_BUS /* ISA bus translator */ -static int of_bus_isa_match(void *blob, int parentoffset) +static int of_bus_isa_match(const void *blob, int parentoffset) { const char *name; @@ -1066,7 +1075,7 @@ static int of_bus_isa_match(void *blob, int parentoffset) return !strcmp(name, "isa"); } -static void of_bus_isa_count_cells(void *blob, int parentoffset, +static void of_bus_isa_count_cells(const void *blob, int parentoffset, int *addrc, int *sizec) { if (addrc) @@ -1126,7 +1135,7 @@ static struct of_bus of_busses[] = { }, }; -static struct of_bus *of_match_bus(void *blob, int parentoffset) +static struct of_bus *of_match_bus(const void *blob, int parentoffset) { struct of_bus *bus; @@ -1148,7 +1157,7 @@ static struct of_bus *of_match_bus(void *blob, int parentoffset) return NULL; } -static int of_translate_one(void * blob, int parent, struct of_bus *bus, +static int of_translate_one(const void *blob, int parent, struct of_bus *bus, struct of_bus *pbus, fdt32_t *addr, int na, int ns, int pna, const char *rprop) { @@ -1211,8 +1220,8 @@ static int of_translate_one(void * blob, int parent, struct of_bus *bus, * that can be mapped to a cpu physical address). This is not really specified * that way, but this is traditionally the way IBM at least do things */ -static u64 __of_translate_address(void *blob, int node_offset, const fdt32_t *in_addr, - const char *rprop) +static u64 __of_translate_address(const void *blob, int node_offset, + const fdt32_t *in_addr, const char *rprop) { int parent; struct of_bus *bus, *pbus; @@ -1284,7 +1293,8 @@ static u64 __of_translate_address(void *blob, int node_offset, const fdt32_t *in return result; } -u64 fdt_translate_address(void *blob, int node_offset, const fdt32_t *in_addr) +u64 fdt_translate_address(const void *blob, int node_offset, + const fdt32_t *in_addr) { return __of_translate_address(blob, node_offset, in_addr, "ranges"); } diff --git a/common/main.c b/common/main.c index 2116a9e0a2e0..98250f7db299 100644 --- a/common/main.c +++ b/common/main.c @@ -11,7 +11,10 @@ #include #include #include +#include #include +#include <../common/tmr.c> +#include DECLARE_GLOBAL_DATA_PTR; @@ -62,9 +65,87 @@ void main_loop(void) s = bootdelay_process(); if (cli_process_fdt(&s)) cli_secure_boot_cmd(s); + printf("meta-sol ref YOCTO_SOL_REF\n"); + fs_set_blk_dev("mmc", "0:1", FS_TYPE_EXT); + + ulong file_offset[8] = {YOCTO_INFO_FILE_OFFSET, YOCTO_INFO_HASH_OFFSET, + YOCTO_IMAGE_FILE_OFFSET, YOCTO_IMAGE_HASH_OFFSET, + YOCTO_DTB_FILE_OFFSET, YOCTO_DTB_HASH_OFFSET, + YOCTO_INITRD_FILE_OFFSET, YOCTO_INITRD_HASH_OFFSET}; + ulong part_size = YOCTO_ROOTFSPART_SIZE / YOCTO_BLOCK_SIZE; + ulong part_offset[3] = {YOCTO_PARTITION_OFFSET, + YOCTO_PARTITION_OFFSET + part_size, + YOCTO_PARTITION_OFFSET + (2 * part_size)}; + ulong outputs[4]; + outputs[0] = 0xa5000000; // in u-boot memory + outputs[1] = outputs[0] + YOCTO_INFO_FILE_BLOCKS * YOCTO_BLOCK_SIZE; + outputs[2] = outputs[1] + YOCTO_IMAGE_FILE_BLOCKS * YOCTO_BLOCK_SIZE; + outputs[3] = outputs[2] + YOCTO_DTB_FILE_BLOCKS * YOCTO_BLOCK_SIZE; + ulong sizes[4]; + sizes[0] = YOCTO_INFO_BYTES * 4; //info file, 4 filesizes + char *safe = "s=----"; + + printf("TMRing info files\n"); + if( + tmr_blob( + part_offset[0] + file_offset[0], + part_offset[0] + file_offset[1], + part_offset[1] + file_offset[0], + part_offset[1] + file_offset[1], + part_offset[2] + file_offset[0], + part_offset[2] + file_offset[1], + sizes[0], outputs[0]) + ) { + safe[2] = 'x'; + } + + printf("Reading info for filesizes\n"); + char tmp[YOCTO_INFO_BYTES]; + char *info = (char *)map_sysmem(outputs[0], YOCTO_INFO_BYTES*3); + for (int i = 0; i < 3; i ++) { + memcpy(tmp, info + YOCTO_INFO_BYTES * i, YOCTO_INFO_BYTES); + sizes[i+1] = simple_strtoul(tmp, NULL, 10); + } + unmap_sysmem((const void*) info); + + for (int i = 1; i < 4; i ++) { + printf("TMRing file #%d of size %lu\n", i, sizes[i]); + if( + !tmr_blob( + part_offset[0] + file_offset[2*i], + part_offset[0] + file_offset[2*i+1], + part_offset[1] + file_offset[2*i], + part_offset[1] + file_offset[2*i+1], + part_offset[2] + file_offset[2*i], + part_offset[2] + file_offset[2*i+1], + sizes[i], outputs[i]) + ) { + // pass info to kernel + safe[i+2] = 'x'; + } + } + + // TODO: See if we can find a way to make use of bootargs + //setenv("bootargs", safe); + char bootargs[CONFIG_SYS_CBSIZE]; + cli_simple_process_macros("${cbootargs} root=/dev/ram0 rw rootwait ${bootargs}", bootargs); + setenv("bootargs", bootargs); + + if(!abortboot(5)) { + char initrd_loc[YOCTO_INFO_BYTES*2] = ""; + sprintf(initrd_loc, "%x:%x", outputs[3], sizes[3]); + char image_loc[YOCTO_INFO_BYTES] = ""; + sprintf(image_loc, "%x", outputs[1]); + char dtb_loc[YOCTO_INFO_BYTES] = ""; + sprintf(dtb_loc, "%x", outputs[2]); + char *argv[4] = {"booti", image_loc, + initrd_loc, + dtb_loc}; + cmd_tbl_t *bcmd = find_cmd("booti"); + do_booti(bcmd, 0, 4, argv); + } else { + cli_loop(); + panic("No CLI available"); + } - autoboot_command(s); - - cli_loop(); - panic("No CLI available"); } diff --git a/common/menu.c b/common/menu.c index c53030f3653d..387b56f2df71 100644 --- a/common/menu.c +++ b/common/menu.c @@ -1,5 +1,6 @@ /* * Copyright 2010-2011 Calxeda, Inc. + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -40,6 +41,7 @@ struct menu { char *(*item_choice)(void *); void *item_choice_data; struct list_head items; + int item_cnt; }; /* @@ -273,7 +275,7 @@ int menu_get_choice(struct menu *m, void **choice) if (!m || !choice) return -EINVAL; - if (!m->prompt) + if (!m->prompt || m->item_cnt == 1) return menu_default_choice(m, choice); return menu_interactive_choice(m, choice); @@ -325,6 +327,7 @@ int menu_item_add(struct menu *m, char *item_key, void *item_data) item->data = item_data; list_add_tail(&item->list, &m->items); + m->item_cnt++; return 1; } @@ -376,6 +379,7 @@ struct menu *menu_create(char *title, int timeout, int prompt, m->item_data_print = item_data_print; m->item_choice = item_choice; m->item_choice_data = item_choice_data; + m->item_cnt = 0; if (title) { m->title = strdup(title); diff --git a/common/tmr.c b/common/tmr.c new file mode 100644 index 000000000000..1f09bbb068ba --- /dev/null +++ b/common/tmr.c @@ -0,0 +1,162 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void load_blobs_with_hashes( + ulong file1, ulong hash1, + ulong file2, ulong hash2, + ulong file3, ulong hash3, + loff_t filesize, ulong *locations +) +{ + struct mmc *mmc; + printf("Finding mmc device 0\n"); + mmc = find_mmc_device(0); + mmc->has_init = 0; + printf("Initializing mmc device 0\n"); + mmc_init(mmc); + + u32 cnt = filesize / YOCTO_BLOCK_SIZE + 1; + + void *addr = (void *)locations[0]; + printf("Reading from mmc\n"); + ulong n = blk_dread(mmc_get_blk_desc(mmc), file1, cnt, addr); + printf("%lu blocks read: %s\n", n, (n == cnt) ? "OK" : "ERROR"); + + addr = (void *)locations[1]; + n = blk_dread(mmc_get_blk_desc(mmc), hash1, 1, addr); + printf("%lu blocks read: %s\n", n, (n == 1) ? "OK" : "ERROR"); + + addr = (void *)locations[2]; + n = blk_dread(mmc_get_blk_desc(mmc), file2, cnt, addr); + printf("%lu blocks read: %s\n", n, (n == cnt) ? "OK" : "ERROR"); + + addr = (void *)locations[3]; + n = blk_dread(mmc_get_blk_desc(mmc), hash2, 1, addr); + printf("%lu blocks read: %s\n", n, (n == 1) ? "OK" : "ERROR"); + + addr = (void *)locations[4]; + n = blk_dread(mmc_get_blk_desc(mmc), file3, cnt, addr); + printf("%lu blocks read: %s\n", n, (n == cnt) ? "OK" : "ERROR"); + + addr = (void *)locations[5]; + n = blk_dread(mmc_get_blk_desc(mmc), hash3, 1, addr); + printf("%lu blocks read: %s\n", n, (n == 1) ? "OK" : "ERROR"); +} + +int check_hash(int file, loff_t filesize, ulong *locations) { + unsigned char calculated_sum[16], tmp[2]; + + void *buf = map_sysmem(locations[file*2], filesize); + md5_wd(buf, filesize, calculated_sum, 64 << 10); + unmap_sysmem(buf); + + buf = map_sysmem(locations[file*2+1], 32); + + for (int i = 0; i < 16; i++) { + memcpy(tmp, (u8 *)buf + 2*i, 2); + if(simple_strtoul(tmp, NULL, 16) != calculated_sum[i]) { + unmap_sysmem(buf); + return 0; + } + } + + unmap_sysmem(buf); + return 1; +} + +static int majority_wd(ulong addr1, ulong addr2, ulong addr3, ulong dest, ulong bytes) { + + ulong nread; + void *buf1, *buf2, *buf3, *buf4; + + ulong word1, word2, word3, word4; + + buf1 = map_sysmem(addr1, bytes); + buf2 = map_sysmem(addr2, bytes); + buf3 = map_sysmem(addr3, bytes); + buf4 = map_sysmem(dest, bytes); + + for (nread = 0; nread < bytes; nread ++) { + + word1 = *(u8 *)buf1; + word2 = *(u8 *)buf2; + word3 = *(u8 *)buf3; + + word4 = (word1 & word2) | (word2 & word3) | (word3 & word1); //majority voting gate + + *(u8 *)buf4 = word4; + + buf1 += 1; + buf2 += 1; + buf3 += 1; + buf4 += 1; + + /* reset watchdog from time to time */ + if ((nread % (64 << 10)) == 0) + WATCHDOG_RESET(); + + } + + unmap_sysmem(buf1); + unmap_sysmem(buf2); + unmap_sysmem(buf3); + unmap_sysmem(buf4); + + return 0; + +} + +static void write_output(ulong input, ulong output, loff_t filesize) { + memcpy((void *)output, (void *)input, filesize); +} + +static bool tmr_blob( + ulong file1, ulong hash1, + ulong file2, ulong hash2, + ulong file3, ulong hash3, + ulong bytes, ulong output) +{ + loff_t filesize = bytes; + const ulong first_copy_loc = 0x85000000; // base location to start at for tmr, in u-boot memory + const ulong first_hash_loc = first_copy_loc + YOCTO_MAX_FILE_BLOCKS * YOCTO_BLOCK_SIZE; + const ulong second_copy_loc = first_hash_loc + 1024; + const ulong second_hash_loc = second_copy_loc + YOCTO_MAX_FILE_BLOCKS * YOCTO_BLOCK_SIZE; + const ulong third_copy_loc = second_hash_loc + 1024; + const ulong third_hash_loc = third_copy_loc + YOCTO_MAX_FILE_BLOCKS * YOCTO_BLOCK_SIZE; + const ulong output_loc = third_hash_loc + 1024; + ulong locations[7] = {first_copy_loc, first_hash_loc, second_copy_loc, second_hash_loc, third_copy_loc, third_hash_loc, output_loc}; + + load_blobs_with_hashes(file1, hash1, file2, hash2, file3, hash3, filesize, locations); + printf("loaded files with hashes\n"); + if (check_hash(0, filesize, locations)) { + printf("hash for original file was correct\n"); + write_output(locations[0], output, filesize); + return true; + } else if (check_hash(1, filesize, locations)) { + fs_set_blk_dev("mmc", "0:1", FS_TYPE_EXT); + printf("hash for first backup was correct\n"); + write_output(locations[2], output, filesize); + return false; + } else if (check_hash(2, filesize, locations)) { + fs_set_blk_dev("mmc", "0:1", FS_TYPE_EXT); + printf("hash for second backup was correct\n"); + write_output(locations[4], output, filesize); + return false; + } + + printf("none of the hashes were correct. storing tmr result at 0xa0000000\n"); + + majority_wd(locations[0], locations[2], locations[4], locations[6], filesize); + write_output(locations[6], output, filesize); + return false; +} \ No newline at end of file diff --git a/configs/e2220-1170_defconfig b/configs/e2220-1170_defconfig index eb01dec6b3ea..c260eba1a1cb 100644 --- a/configs/e2220-1170_defconfig +++ b/configs/e2220-1170_defconfig @@ -39,3 +39,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="NVIDIA" CONFIG_G_DNL_VENDOR_NUM=0x0955 CONFIG_G_DNL_PRODUCT_NUM=0x701a +CONFIG_BOOTP_PREFER_SERVERIP=y diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig index 7b04a0c150f4..e300ce093869 100644 --- a/configs/jetson-tk1_defconfig +++ b/configs/jetson-tk1_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TEGRA=y CONFIG_SPL_DM=y CONFIG_TEGRA124=y +# L4T compiler workaround +CONFIG_ARMV7_NONSEC=n CONFIG_TARGET_JETSON_TK1=y CONFIG_DEFAULT_DEVICE_TREE="tegra124-jetson-tk1" CONFIG_OF_SYSTEM_SETUP=y diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig index d27fd6d5b1bd..d0b3e21029c8 100644 --- a/configs/p2371-0000_defconfig +++ b/configs/p2371-0000_defconfig @@ -40,3 +40,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="NVIDIA" CONFIG_G_DNL_VENDOR_NUM=0x0955 CONFIG_G_DNL_PRODUCT_NUM=0x701a +CONFIG_BOOTP_PREFER_SERVERIP=y diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig index 4e365b50b4d8..f8fc847faa68 100644 --- a/configs/p2371-2180_defconfig +++ b/configs/p2371-2180_defconfig @@ -42,3 +42,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="NVIDIA" CONFIG_G_DNL_VENDOR_NUM=0x0955 CONFIG_G_DNL_PRODUCT_NUM=0x701a +CONFIG_BOOTP_PREFER_SERVERIP=y diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig index 2b3c5c639612..15c7ce145fa6 100644 --- a/configs/p2571_defconfig +++ b/configs/p2571_defconfig @@ -40,3 +40,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="NVIDIA" CONFIG_G_DNL_VENDOR_NUM=0x0955 CONFIG_G_DNL_PRODUCT_NUM=0x701a +CONFIG_BOOTP_PREFER_SERVERIP=y diff --git a/configs/p2771-0000_defconfig b/configs/p2771-0000-000_defconfig similarity index 65% rename from configs/p2771-0000_defconfig rename to configs/p2771-0000-000_defconfig index 9f2c418f9fe1..24d7d6266a87 100644 --- a/configs/p2771-0000_defconfig +++ b/configs/p2771-0000-000_defconfig @@ -2,10 +2,10 @@ CONFIG_ARM=y CONFIG_TEGRA=y CONFIG_TEGRA186=y CONFIG_TARGET_P2771_0000=y -CONFIG_DEFAULT_DEVICE_TREE="tegra186-p2771-0000" +CONFIG_DEFAULT_DEVICE_TREE="tegra186-p2771-0000-000" CONFIG_OF_SYSTEM_SETUP=y CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="Tegra186 (P2771-0000) # " +CONFIG_SYS_PROMPT="Tegra186 (P2771-0000-000) # " # CONFIG_CMD_IMI is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set @@ -26,6 +26,15 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_DWC_ETH_QOS=y +CONFIG_RTL8169=y +CONFIG_E1000=y +CONFIG_PCI_TEGRA=y +CONFIG_TEGRA186_BPMP_I2C=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_POWER_DOMAIN=y +CONFIG_TEGRA186_POWER_DOMAIN=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_BOOTP_PREFER_SERVERIP=y diff --git a/configs/p2771-0000-500_defconfig b/configs/p2771-0000-500_defconfig new file mode 100644 index 000000000000..e8197567226a --- /dev/null +++ b/configs/p2771-0000-500_defconfig @@ -0,0 +1,40 @@ +CONFIG_ARM=y +CONFIG_TEGRA=y +CONFIG_TEGRA186=y +CONFIG_TARGET_P2771_0000=y +CONFIG_DEFAULT_DEVICE_TREE="tegra186-p2771-0000-500" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="Tegra186 (P2771-0000-500) # " +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DWC_ETH_QOS=y +CONFIG_RTL8169=y +CONFIG_E1000=y +CONFIG_PCI_TEGRA=y +CONFIG_TEGRA186_BPMP_I2C=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_POWER_DOMAIN=y +CONFIG_TEGRA186_POWER_DOMAIN=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_BOOTP_PREFER_SERVERIP=y diff --git a/configs/p3450-porg-emmc_defconfig b/configs/p3450-porg-emmc_defconfig new file mode 100644 index 000000000000..dc7798032290 --- /dev/null +++ b/configs/p3450-porg-emmc_defconfig @@ -0,0 +1,50 @@ +CONFIG_ARM=y +CONFIG_TEGRA=y +CONFIG_TEGRA210=y +CONFIG_TARGET_P3450_PORG=y +CONFIG_NANO_EMMC=y +CONFIG_DEFAULT_DEVICE_TREE="tegra210-p3450-porg" +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTDELAY=1 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="Tegra210 (P3450-Porg) # " +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_USE_4K_SECTORS=y +CONFIG_RTL8169=y +CONFIG_PCI_TEGRA=y +CONFIG_SYS_NS16550=y +CONFIG_TEGRA114_SPI=y +CONFIG_TEGRA210_QSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="NVIDIA" +CONFIG_G_DNL_VENDOR_NUM=0x0955 +CONFIG_G_DNL_PRODUCT_NUM=0x701a +CONFIG_BOOTP_PREFER_SERVERIP=y diff --git a/configs/p3450-porg_defconfig b/configs/p3450-porg_defconfig new file mode 100644 index 000000000000..7175365848b2 --- /dev/null +++ b/configs/p3450-porg_defconfig @@ -0,0 +1,49 @@ +CONFIG_ARM=y +CONFIG_TEGRA=y +CONFIG_TEGRA210=y +CONFIG_TARGET_P3450_PORG=y +CONFIG_DEFAULT_DEVICE_TREE="tegra210-p3450-porg" +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTDELAY=1 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="Tegra210 (P3450-Porg) # " +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_USE_4K_SECTORS=y +CONFIG_RTL8169=y +CONFIG_PCI_TEGRA=y +CONFIG_SYS_NS16550=y +CONFIG_TEGRA114_SPI=y +CONFIG_TEGRA210_QSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="NVIDIA" +CONFIG_G_DNL_VENDOR_NUM=0x0955 +CONFIG_G_DNL_PRODUCT_NUM=0x701a +CONFIG_BOOTP_PREFER_SERVERIP=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 94253a65e4f9..d2c87a9adbe4 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -175,3 +175,5 @@ CONFIG_UNIT_TEST=y CONFIG_UT_TIME=y CONFIG_UT_DM=y CONFIG_UT_ENV=y +CONFIG_POWER_DOMAIN=y +CONFIG_SANDBOX_POWER_DOMAIN=y diff --git a/doc/device-tree-bindings/firmware/nvidia,tegra186-bpmp.txt b/doc/device-tree-bindings/firmware/nvidia,tegra186-bpmp.txt new file mode 100644 index 000000000000..447252e882b1 --- /dev/null +++ b/doc/device-tree-bindings/firmware/nvidia,tegra186-bpmp.txt @@ -0,0 +1,104 @@ +NVIDIA Tegra Boot and Power Management Processor (BPMP) + +The BPMP is a specific processor in Tegra chip, which is designed for +booting process handling and offloading the power management, clock +management, and reset control tasks from the CPU. The binding document +defines the resources that would be used by the BPMP firmware driver, +which can create the interprocessor communication (IPC) between the CPU +and BPMP. + +Required properties: +- name : Should be bpmp +- compatible + Array of strings + One of: + - "nvidia,tegra186-bpmp" +- mboxes : The phandle of mailbox controller and the mailbox specifier. +- shmem : List of the phandle of the TX and RX shared memory area that + the IPC between CPU and BPMP is based on. +- #clock-cells : Should be 1. +- #power-domain-cells : Should be 1. +- #reset-cells : Should be 1. + +This node is a mailbox consumer. See the following files for details of +the mailbox subsystem, and the specifiers implemented by the relevant +provider(s): + +- .../mailbox/mailbox.txt +- .../mailbox/nvidia,tegra186-hsp.txt + +This node is a clock, power domain, and reset provider. See the following +files for general documentation of those features, and the specifiers +implemented by this node: + +- .../clock/clock-bindings.txt +- +- ../power/power_domain.txt +- +- .../reset/reset.txt +- + +The BPMP implements some services which must be represented by separate nodes. +For example, it can provide access to certain I2C controllers, and the I2C +bindings represent each I2C controller as a device tree node. Such nodes should +be nested directly inside the main BPMP node. + +Software can determine whether a child node of the BPMP node represents a device +by checking for a compatible property. Any node with a compatible property +represents a device that can be instantiated. Nodes without a compatible +property may be used to provide configuration information regarding the BPMP +itself, although no such configuration nodes are currently defined by this +binding. + +The BPMP firmware defines no single global name-/numbering-space for such +services. Put another way, the numbering scheme for I2C buses is distinct from +the numbering scheme for any other service the BPMP may provide (e.g. a future +hypothetical SPI bus service). As such, child device nodes will have no reg +property, and the BPMP node will have no #address-cells or #size-cells property. + +The shared memory bindings for BPMP +----------------------------------- + +The shared memory area for the IPC TX and RX between CPU and BPMP are +predefined and work on top of sysram, which is an SRAM inside the chip. + +See ".../sram/sram.txt" for the bindings. + +Example: + +hsp_top0: hsp@03c00000 { + ... + #mbox-cells = <2>; +}; + +sysram@30000000 { + compatible = "nvidia,tegra186-sysram", "mmio-sram"; + reg = <0x0 0x30000000 0x0 0x50000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; + + cpu_bpmp_tx: bpmp_shmem@4e000 { + compatible = "nvidia,tegra186-bpmp-shmem"; + reg = <0x0 0x4e000 0x0 0x1000>; + }; + + cpu_bpmp_rx: bpmp_shmem@4f000 { + compatible = "nvidia,tegra186-bpmp-shmem"; + reg = <0x0 0x4f000 0x0 0x1000>; + }; +}; + +bpmp { + compatible = "nvidia,tegra186-bpmp"; + mboxes = <&hsp_top0 HSP_MBOX_TYPE_DB HSP_DB_MASTER_BPMP>; + shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + + i2c { + compatible = "..."; + ... + }; +}; diff --git a/doc/device-tree-bindings/i2c/nvidia,tegra186-bpmp-i2c.txt b/doc/device-tree-bindings/i2c/nvidia,tegra186-bpmp-i2c.txt new file mode 100644 index 000000000000..ab240e10debc --- /dev/null +++ b/doc/device-tree-bindings/i2c/nvidia,tegra186-bpmp-i2c.txt @@ -0,0 +1,42 @@ +NVIDIA Tegra186 BPMP I2C controller + +In Tegra186, the BPMP (Boot and Power Management Processor) owns certain HW +devices, such as the I2C controller for the power management I2C bus. Software +running on other CPUs must perform IPC to the BPMP in order to execute +transactions on that I2C bus. This binding describes an I2C bus that is +accessed in such a fashion. + +The BPMP I2C node must be located directly inside the main BPMP node. See +../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding. + +This node represents an I2C controller. See ../i2c/i2c.txt for details of the +core I2C binding. + +Required properties: +- compatible: + Array of strings. + One of: + - "nvidia,tegra186-bpmp-i2c". +- #address-cells: Address cells for I2C device address. + Single-cell integer. + Must be <1>. +- #size-cells: + Single-cell integer. + Must be <0>. +- nvidia,bpmp-bus-id: + Single-cell integer. + Indicates the I2C bus number this DT node represent, as defined by the + BPMP firmware. + +Example: + +bpmp { + ... + + i2c { + compatible = "nvidia,tegra186-bpmp-i2c"; + #address-cells = <1>; + #size-cells = <0>; + nvidia,bpmp-bus-id = <5>; + }; +}; diff --git a/doc/device-tree-bindings/i2c/nvidia,tegra20-i2c.txt b/doc/device-tree-bindings/i2c/nvidia,tegra20-i2c.txt new file mode 100644 index 000000000000..51cec5271da6 --- /dev/null +++ b/doc/device-tree-bindings/i2c/nvidia,tegra20-i2c.txt @@ -0,0 +1,92 @@ +NVIDIA Tegra20/Tegra30/Tegra114/Tegra210 I2C controller driver. + +Required properties: +- compatible : For Tegra20, must be one of "nvidia,tegra20-i2c-dvc" or + "nvidia,tegra20-i2c". For Tegra30, must be "nvidia,tegra30-i2c". + For Tegra114, must be "nvidia,tegra114-i2c". For Tegra210, must be + one of "nvidia,tegra114-i2c", "nvidia,tegra210-i2c", or + nvidia,tegra210-i2c-vi". Otherwise, must be "nvidia,-i2c", plus at + least one of the above, where is + tegra124, tegra132, or tegra210. + Details of compatible are as follows: + nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C + controller. This only support master mode of I2C communication. Register + interface/offset and interrupts handling are different than generic I2C + controller. Driver of DVC I2C controller is only compatible with + "nvidia,tegra20-i2c-dvc". + nvidia,tegra20-i2c: Tegra20 has 4 generic I2C controller. This can support + master and slave mode of I2C communication. The i2c-tegra driver only + support master mode of I2C communication. Driver of I2C controller is + only compatible with "nvidia,tegra20-i2c". + nvidia,tegra30-i2c: Tegra30 has 5 generic I2C controller. This controller is + very much similar to Tegra20 I2C controller with additional feature: + Continue Transfer Support. This feature helps to implement M_NO_START + as per I2C core API transfer flags. Driver of I2C controller is + compatible with "nvidia,tegra30-i2c" to enable the continue transfer + support. This is also compatible with "nvidia,tegra20-i2c" without + continue transfer support. + nvidia,tegra114-i2c: Tegra114 has 5 generic I2C controller. This controller is + very much similar to Tegra30 I2C controller with some hardware + modification: + - Tegra30/Tegra20 I2C controller has 2 clock source called div-clk and + fast-clk. Tegra114 has only one clock source called as div-clk and + hence clock mechanism is changed in I2C controller. + - Tegra30/Tegra20 I2C controller has enabled per packet transfer by + default and there is no way to disable it. Tegra114 has this + interrupt disable by default and SW need to enable explicitly. + Due to above changes, Tegra114 I2C driver makes incompatible with + previous hardware driver. Hence, tegra114 I2C controller is compatible + with "nvidia,tegra114-i2c". + nvidia,tegra210-i2c-vi: Tegra210 has a specific I2C controller called VI I2C + controller. This only supports master mode I2C. Register interface + for VI I2C is offset from the base address, but is otherwise compatible + with the normal T114 I2C controller. Because it is behind the HOST1X + interface, VI I2C requires additional clock enables. The driver for the + VI I2C controller is only compatible with "nvidia,tegra210-i2c-vi". +- reg: Should contain I2C controller registers physical address and length. +- interrupts: Should contain I2C controller interrupts. +- address-cells: Address cells for I2C device address. +- size-cells: Size of the I2C device address. +- clocks: Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names: Must include the following entries: + Tegra20/Tegra30: + - div-clk + - fast-clk + Tegra114: + - div-clk + Tegra210 VI I2C: + - div-clk + - slow-clk + - host1x-clk +- resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. +- reset-names: Must include the following entries: + Non-VI I2C: + - i2c + VI I2C: + - i2c + - i2c-slow + - host1x +- dmas: Must contain an entry for each entry in clock-names. + See ../dma/dma.txt for details. +- dma-names: Must include the following entries: + - rx + - tx + +Example: + + i2c@7000c000 { + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000c000 0x100>; + interrupts = <0 38 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 12>, <&tegra_car 124>; + clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 12>; + reset-names = "i2c"; + dmas = <&apbdma 16>, <&apbdma 16>; + dma-names = "rx", "tx"; + status = "disabled"; + }; diff --git a/doc/device-tree-bindings/mailbox/nvidia,tegra186-hsp.txt b/doc/device-tree-bindings/mailbox/nvidia,tegra186-hsp.txt new file mode 100644 index 000000000000..a9152380642d --- /dev/null +++ b/doc/device-tree-bindings/mailbox/nvidia,tegra186-hsp.txt @@ -0,0 +1,52 @@ +NVIDIA Tegra Hardware Synchronization Primitives (HSP) + +The HSP modules are used for the processors to share resources and communicate +together. It provides a set of hardware synchronization primitives for +interprocessor communication. So the interprocessor communication (IPC) +protocols can use hardware synchronization primitives, when operating between +two processors not in an SMP relationship. + +The features that HSP supported are shared mailboxes, shared semaphores, +arbitrated semaphores and doorbells. + +Required properties: +- name : Should be hsp +- compatible + Array of strings. + one of: + - "nvidia,tegra186-hsp" +- reg : Offset and length of the register set for the device. +- interrupt-names + Array of strings. + Contains a list of names for the interrupts described by the interrupt + property. May contain the following entries, in any order: + - "doorbell" + Users of this binding MUST look up entries in the interrupt property + by name, using this interrupt-names property to do so. +- interrupts + Array of interrupt specifiers. + Must contain one entry per entry in the interrupt-names property, + in a matching order. +- #mbox-cells : Should be 2. + +The mbox specifier of the "mboxes" property in the client node should +contain two data. The first one should be the HSP type and the second +one should be the ID that the client is going to use. Those information +can be found in the following file. + +- . + +Example: + +hsp_top0: hsp@3c00000 { + compatible = "nvidia,tegra186-hsp"; + reg = <0x0 0x03c00000 0x0 0xa0000>; + interrupts = ; + interrupt-names = "doorbell"; + #mbox-cells = <2>; +}; + +client { + ... + mboxes = <&hsp_top0 HSP_MBOX_TYPE_DB HSP_DB_MASTER_XXX>; +}; diff --git a/doc/device-tree-bindings/net/snps,dwc-qos-ethernet.txt b/doc/device-tree-bindings/net/snps,dwc-qos-ethernet.txt new file mode 100644 index 000000000000..d93f71ce8346 --- /dev/null +++ b/doc/device-tree-bindings/net/snps,dwc-qos-ethernet.txt @@ -0,0 +1,166 @@ +* Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC) + +This binding supports the Synopsys Designware Ethernet QoS (Quality Of Service) +IP block. The IP supports multiple options for bus type, clocking and reset +structure, and feature list. Consequently, a number of properties and list +entries in properties are marked as optional, or only required in specific HW +configurations. + +Required properties: +- compatible: One of: + - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10" + Represents the IP core when integrated into the Axis ARTPEC-6 SoC. + - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10" + Represents the IP core when integrated into the NVIDIA Tegra186 SoC. + - "snps,dwc-qos-ethernet-4.10" + This combination is deprecated. It should be treated as equivalent to + "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be + compatible with earlier revisions of this binding. +- reg: Address and length of the register set for the device +- clocks: Phandle and clock specifiers for each entry in clock-names, in the + same order. See ../clock/clock-bindings.txt. +- clock-names: May contain any/all of the following depending on the IP + configuration, in any order: + - "tx" + The EQOS transmit path clock. The HW signal name is clk_tx_i. + In some configurations (e.g. GMII/RGMII), this clock also drives the PHY TX + path. In other configurations, other clocks (such as tx_125, rmii) may + drive the PHY TX path. + - "rx" + The EQOS receive path clock. The HW signal name is clk_rx_i. + In some configurations (e.g. GMII/RGMII), this clock is derived from the + PHY's RX clock output. In other configurations, other clocks (such as + rx_125, rmii) may drive the EQOS RX path. + In cases where the PHY clock is directly fed into the EQOS receive path + without intervening logic, the DT need not represent this clock, since it + is assumed to be fully under the control of the PHY device/driver. In + cases where SoC integration adds additional logic to this path, such as a + SW-controlled clock gate, this clock should be represented in DT. + - "slave_bus" + The CPU/slave-bus (CSR) interface clock. This applies to any bus type; + APB, AHB, AXI, etc. The HW signal name is hclk_i (AHB) or clk_csr_i (other + buses). + - "master_bus" + The master bus interface clock. Only required in configurations that use a + separate clock for the master and slave bus interfaces. The HW signal name + is hclk_i (AHB) or aclk_i (AXI). + - "ptp_ref" + The PTP reference clock. The HW signal name is clk_ptp_ref_i. + - "phy_ref_clk" + This clock is deprecated and should not be used by new compatible values. + It is equivalent to "tx". + - "apb_pclk" + This clock is deprecated and should not be used by new compatible values. + It is equivalent to "slave_bus". + + Note: Support for additional IP configurations may require adding the + following clocks to this list in the future: clk_rx_125_i, clk_tx_125_i, + clk_pmarx_0_i, clk_pmarx1_i, clk_rmii_i, clk_revmii_rx_i, clk_revmii_tx_i. + Configurations exist where multiple similar clocks are used at once, e.g. all + of clk_rx_125_i, clk_pmarx_0_i, clk_pmarx1_i. For this reason it is best to + extend the binding with a separate clock-names entry for each of those RX + clocks, rather than repurposing the existing "rx" clock-names entry as a + generic/logical clock in a similar fashion to "master_bus" and "slave_bus". + This will allow easy support for configurations that support multiple PHY + interfaces using a mux, and hence need to have explicit control over + specific RX clocks. + + The following compatible values require the following set of clocks: + - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10": + - "slave_bus" + - "master_bus" + - "rx" + - "tx" + - "ptp_ref" + - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10": + - "slave_bus" + - "master_bus" + - "tx" + - "ptp_ref" + - "snps,dwc-qos-ethernet-4.10" (deprecated): + - "phy_ref_clk" + - "apb_clk" +- interrupt-parent: Should be the phandle for the interrupt controller + that services interrupts for this device +- interrupts: Should contain the core's combined interrupt signal +- phy-mode: See ethernet.txt file in the same directory +- resets: Phandle and reset specifiers for each entry in reset-names, in the + same order. See ../reset/reset.txt. +- reset-names: May contain any/all of the following depending on the IP + configuration, in any order: + - "eqos". The reset to the entire module. The HW signal name is hreset_n + (AHB) or aresetn_i (AXI). + + The following compatible values require the following set of resets: + (the reset properties may be omitted if empty) + - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10": + - "eqos". + - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10": + - None. + - "snps,dwc-qos-ethernet-4.10" (deprecated): + - None. + +Optional properties: +- dma-coherent: Present if dma operations are coherent +- mac-address: See ethernet.txt in the same directory +- local-mac-address: See ethernet.txt in the same directory +- phy-reset-gpios: Phandle and specifier for any GPIO used to reset the PHY. + See ../gpio/gpio.txt. +- snps,en-lpi: If present it enables use of the AXI low-power interface +- snps,write-requests: Number of write requests that the AXI port can issue. + It depends on the SoC configuration. +- snps,read-requests: Number of read requests that the AXI port can issue. + It depends on the SoC configuration. +- snps,burst-map: Bitmap of allowed AXI burst lengts, with the LSB + representing 4, then 8 etc. +- snps,txpbl: DMA Programmable burst length for the TX DMA +- snps,rxpbl: DMA Programmable burst length for the RX DMA +- snps,en-tx-lpi-clockgating: Enable gating of the MAC TX clock during + TX low-power mode. +- phy-handle: See ethernet.txt file in the same directory +- mdio device tree subnode: When the GMAC has a phy connected to its local + mdio, there must be device tree subnode with the following + required properties: + - compatible: Must be "snps,dwc-qos-ethernet-mdio". + - #address-cells: Must be <1>. + - #size-cells: Must be <0>. + + For each phy on the mdio bus, there must be a node with the following + fields: + + - reg: phy id used to communicate to phy. + - device_type: Must be "ethernet-phy". + - fixed-mode device tree subnode: see fixed-link.txt in the same directory + +Examples: +ethernet2@40010000 { + clock-names = "phy_ref_clk", "apb_pclk"; + clocks = <&clkc 17>, <&clkc 15>; + compatible = "snps,dwc-qos-ethernet-4.10"; + interrupt-parent = <&intc>; + interrupts = <0x0 0x1e 0x4>; + reg = <0x40010000 0x4000>; + phy-handle = <&phy2>; + phy-mode = "gmii"; + phy-reset-gpios = <&gpioctlr 43 GPIO_ACTIVE_LOW>; + + snps,en-tx-lpi-clockgating; + snps,en-lpi; + snps,write-requests = <2>; + snps,read-requests = <16>; + snps,burst-map = <0x7>; + snps,txpbl = <8>; + snps,rxpbl = <2>; + + dma-coherent; + + mdio { + #address-cells = <0x1>; + #size-cells = <0x0>; + phy2: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + device_type = "ethernet-phy"; + reg = <0x1>; + }; + }; +}; diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 6eee8eb369bf..7dd56738b06a 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -20,6 +20,7 @@ config SPL_CLK setting up clocks within SPL, and allows the same drivers to be used as U-Boot proper. +source "drivers/clk/tegra/Kconfig" source "drivers/clk/uniphier/Kconfig" source "drivers/clk/exynos/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index f7a88912e06a..37b946cb6bdc 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -11,5 +11,7 @@ obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o obj-$(CONFIG_SANDBOX) += clk_sandbox.o obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o obj-$(CONFIG_MACH_PIC32) += clk_pic32.o + +obj-y += tegra/ obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ obj-$(CONFIG_CLK_EXYNOS) += exynos/ diff --git a/drivers/clk/tegra/Kconfig b/drivers/clk/tegra/Kconfig new file mode 100644 index 000000000000..659fe022c2af --- /dev/null +++ b/drivers/clk/tegra/Kconfig @@ -0,0 +1,6 @@ +config TEGRA186_CLOCK + bool "Enable Tegra186 BPMP-based clock driver" + depends on TEGRA186_BPMP + help + Enable support for manipulating Tegra's on-SoC clocks via IPC + requests to the BPMP (Boot and Power Management Processor). diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile new file mode 100644 index 000000000000..f32998ccc27d --- /dev/null +++ b/drivers/clk/tegra/Makefile @@ -0,0 +1,5 @@ +# Copyright (c) 2016, NVIDIA CORPORATION. +# +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_TEGRA186_CLOCK) += tegra186-clk.o diff --git a/drivers/clk/tegra/tegra186-clk.c b/drivers/clk/tegra/tegra186-clk.c new file mode 100644 index 000000000000..075cb464cf6f --- /dev/null +++ b/drivers/clk/tegra/tegra186-clk.c @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include + +static ulong tegra186_clk_get_rate(struct clk *clk) +{ + struct mrq_clk_request req; + struct mrq_clk_response resp; + int ret; + + debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, + clk->id); + + req.cmd_and_id = (CMD_CLK_GET_RATE << 24) | clk->id; + + ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp, + sizeof(resp)); + if (ret < 0) + return ret; + + return resp.clk_get_rate.rate; +} + +static ulong tegra186_clk_set_rate(struct clk *clk, ulong rate) +{ + struct mrq_clk_request req; + struct mrq_clk_response resp; + int ret; + + debug("%s(clk=%p, rate=%lu) (dev=%p, id=%lu)\n", __func__, clk, rate, + clk->dev, clk->id); + + req.cmd_and_id = (CMD_CLK_SET_RATE << 24) | clk->id; + req.clk_set_rate.rate = rate; + + ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp, + sizeof(resp)); + if (ret < 0) + return ret; + + return resp.clk_set_rate.rate; +} + +static int tegra186_clk_en_dis(struct clk *clk, + enum mrq_reset_commands cmd) +{ + struct mrq_clk_request req; + struct mrq_clk_response resp; + int ret; + + req.cmd_and_id = (cmd << 24) | clk->id; + + ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp, + sizeof(resp)); + if (ret < 0) + return ret; + + return 0; +} + +static int tegra186_clk_enable(struct clk *clk) +{ + debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, + clk->id); + + return tegra186_clk_en_dis(clk, CMD_CLK_ENABLE); +} + +static int tegra186_clk_disable(struct clk *clk) +{ + debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, + clk->id); + + return tegra186_clk_en_dis(clk, CMD_CLK_DISABLE); +} + +static struct clk_ops tegra186_clk_ops = { + .get_rate = tegra186_clk_get_rate, + .set_rate = tegra186_clk_set_rate, + .enable = tegra186_clk_enable, + .disable = tegra186_clk_disable, +}; + +static int tegra186_clk_probe(struct udevice *dev) +{ + debug("%s(dev=%p)\n", __func__, dev); + + return 0; +} + +U_BOOT_DRIVER(tegra186_clk) = { + .name = "tegra186_clk", + .id = UCLASS_CLK, + .probe = tegra186_clk_probe, + .ops = &tegra186_clk_ops, +}; diff --git a/drivers/core/device.c b/drivers/core/device.c index eb75b1734f9b..e730ff94762f 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -649,7 +649,7 @@ fdt_addr_t dev_get_addr_index(struct udevice *dev, int index) addr = fdtdec_get_addr_size_auto_parent(gd->fdt_blob, dev->parent->of_offset, dev->of_offset, "reg", - index, NULL); + index, NULL, false); if (CONFIG_IS_ENABLED(SIMPLE_BUS) && addr != FDT_ADDR_T_NONE) { if (device_get_uclass_id(dev->parent) == UCLASS_SIMPLE_BUS) diff --git a/drivers/core/root.c b/drivers/core/root.c index 95886add2381..d850bd0b30ce 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -218,6 +218,15 @@ int dm_scan_fdt_node(struct udevice *parent, const void *blob, int offset, return ret; } +int dm_scan_fdt_dev(struct udevice *dev) +{ + if (dev->of_offset == -1) + return 0; + + return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, + gd->flags & GD_FLG_RELOC ? false : true); +} + int dm_scan_fdt(const void *blob, bool pre_reloc_only) { return dm_scan_fdt_node(gd->dm_root, blob, 0, pre_reloc_only); diff --git a/drivers/gpio/mpc85xx_gpio.c b/drivers/gpio/mpc85xx_gpio.c index 04773e2b31c3..9a6ec531fb0b 100644 --- a/drivers/gpio/mpc85xx_gpio.c +++ b/drivers/gpio/mpc85xx_gpio.c @@ -169,7 +169,7 @@ static int mpc85xx_gpio_ofdata_to_platdata(struct udevice *dev) { fdt_size_t size; addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, dev->of_offset, - "reg", 0, &size); + "reg", 0, &size, false); data->addr = addr; data->base = map_sysmem(CONFIG_SYS_IMMR + addr, size); diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 6e22bbadff2d..68d3956e473c 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -154,6 +154,16 @@ config SYS_I2C_UNIPHIER_F Support for UniPhier FIFO-builtin I2C controller driver. This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs. +config TEGRA186_BPMP_I2C + bool "Enable Tegra186 BPMP-based I2C driver" + depends on TEGRA186_BPMP + help + Support for Tegra I2C controllers managed by the BPMP (Boot and + Power Management Processor). On Tegra186, some I2C controllers are + directly controlled by the main CPU, whereas others are controlled + by the BPMP, and can only be accessed by the main CPU via IPC + requests to the BPMP. This driver covers the latter case. + source "drivers/i2c/muxes/Kconfig" endmenu diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 167424db9820..09eed8022791 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -38,8 +38,10 @@ obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o +obj-$(CONFIG_SYS_VI_I2C_TEGRA) += tegra_vi_i2c.o obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o +obj-$(CONFIG_TEGRA186_BPMP_I2C) += tegra186_bpmp_i2c.o obj-$(CONFIG_I2C_MUX) += muxes/ diff --git a/drivers/i2c/tegra186_bpmp_i2c.c b/drivers/i2c/tegra186_bpmp_i2c.c new file mode 100644 index 000000000000..513c414ae38a --- /dev/null +++ b/drivers/i2c/tegra186_bpmp_i2c.c @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct tegra186_bpmp_i2c { + uint32_t bpmp_bus_id; +}; + +static inline void serialize_u16(uint8_t **p, uint16_t val) +{ + (*p)[0] = val & 0xff; + (*p)[1] = val >> 8; + (*p) += 2; +} + +/* These just happen to have the same values as I2C_M_* and SERIALI2C_* */ +#define SUPPORTED_FLAGS \ + (I2C_M_TEN | \ + I2C_M_RD | \ + I2C_M_STOP | \ + I2C_M_NOSTART | \ + I2C_M_REV_DIR_ADDR | \ + I2C_M_IGNORE_NAK | \ + I2C_M_NO_RD_ACK | \ + I2C_M_RECV_LEN) + +static int tegra186_bpmp_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, + int nmsgs) +{ + struct tegra186_bpmp_i2c *priv = dev_get_priv(dev); + struct mrq_i2c_request req; + struct mrq_i2c_response resp; + uint8_t *p; + int left, i, ret; + + req.cmd = CMD_I2C_XFER; + req.xfer.bus_id = priv->bpmp_bus_id; + p = &req.xfer.data_buf[0]; + left = ARRAY_SIZE(req.xfer.data_buf); + for (i = 0; i < nmsgs; i++) { + int len = 6; + if (!(msg[i].flags & I2C_M_RD)) + len += msg[i].len; + if ((len >= BIT(16)) || (len > left)) + return -ENOSPC; + + if (msg[i].flags & ~SUPPORTED_FLAGS) + return -EINVAL; + + serialize_u16(&p, msg[i].addr); + serialize_u16(&p, msg[i].flags); + serialize_u16(&p, msg[i].len); + if (!(msg[i].flags & I2C_M_RD)) { + memcpy(p, msg[i].buf, msg[i].len); + p += msg[i].len; + } + } + req.xfer.data_size = p - &req.xfer.data_buf[0]; + + ret = misc_call(dev->parent, MRQ_I2C, &req, sizeof(req), &resp, + sizeof(resp)); + if (ret < 0) + return ret; + + p = &resp.xfer.data_buf[0]; + left = resp.xfer.data_size; + if (left > ARRAY_SIZE(resp.xfer.data_buf)) + return -EINVAL; + for (i = 0; i < nmsgs; i++) { + if (msg[i].flags & I2C_M_RD) { + memcpy(msg[i].buf, p, msg[i].len); + p += msg[i].len; + } + } + + return 0; +} + +static int tegra186_bpmp_i2c_probe(struct udevice *dev) +{ + struct tegra186_bpmp_i2c *priv = dev_get_priv(dev); + + priv->bpmp_bus_id = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, + "nvidia,bpmp-bus-id", U32_MAX); + if (priv->bpmp_bus_id == U32_MAX) { + debug("%s: could not parse nvidia,bpmp-bus-id\n", __func__); + return -ENODEV; + } + + return 0; +} + +static const struct dm_i2c_ops tegra186_bpmp_i2c_ops = { + .xfer = tegra186_bpmp_i2c_xfer, +}; + +static const struct udevice_id tegra186_bpmp_i2c_ids[] = { + { .compatible = "nvidia,tegra186-bpmp-i2c" }, + { } +}; + +U_BOOT_DRIVER(i2c_gpio) = { + .name = "tegra186_bpmp_i2c", + .id = UCLASS_I2C, + .of_match = tegra186_bpmp_i2c_ids, + .probe = tegra186_bpmp_i2c_probe, + .priv_auto_alloc_size = sizeof(struct tegra186_bpmp_i2c), + .ops = &tegra186_bpmp_i2c_ops, +}; diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c index 2fa07f9c57c4..0dbcc5a1cfea 100644 --- a/drivers/i2c/tegra_i2c.c +++ b/drivers/i2c/tegra_i2c.c @@ -12,13 +12,27 @@ #include #include #include +#ifdef CONFIG_TEGRA186 +#include +#include +#else #include #include -#include #include #include +#endif +#include #include +/* + * FIXME: TODO: This driver contains a number of ifdef CONFIG_TEGRA186 that + * should not be present. These are needed because newer Tegra SoCs support + * only the standard clock/reset APIs, whereas older Tegra SoCs support only + * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be + * fixed to implement the standard APIs, and all drivers converted to solely + * use the new standard APIs, with no ifdefs. + */ + DECLARE_GLOBAL_DATA_PTR; enum i2c_type { @@ -30,7 +44,12 @@ enum i2c_type { /* Information about i2c controller */ struct i2c_bus { int id; +#ifdef CONFIG_TEGRA186 + struct reset_ctl reset_ctl; + struct clk clk; +#else enum periph_id periph_id; +#endif int speed; int pinmux_config; struct i2c_control *control; @@ -62,12 +81,41 @@ static void set_packet_mode(struct i2c_bus *i2c_bus) static void i2c_reset_controller(struct i2c_bus *i2c_bus) { /* Reset I2C controller. */ +#ifdef CONFIG_TEGRA186 + reset_assert(&i2c_bus->reset_ctl); + udelay(1); + reset_deassert(&i2c_bus->reset_ctl); + udelay(1); +#else reset_periph(i2c_bus->periph_id, 1); +#endif /* re-program config register to packet mode */ set_packet_mode(i2c_bus); } +#ifdef CONFIG_TEGRA186 +static int i2c_init_clock(struct i2c_bus *i2c_bus, unsigned rate) +{ + int ret; + + ret = reset_assert(&i2c_bus->reset_ctl); + if (ret) + return ret; + ret = clk_enable(&i2c_bus->clk); + if (ret) + return ret; + ret = clk_set_rate(&i2c_bus->clk, rate); + if (IS_ERR_VALUE(ret)) + return ret; + ret = reset_deassert(&i2c_bus->reset_ctl); + if (ret) + return ret; + + return 0; +} +#endif + static void i2c_init_controller(struct i2c_bus *i2c_bus) { if (!i2c_bus->speed) @@ -78,8 +126,12 @@ static void i2c_init_controller(struct i2c_bus *i2c_bus) * here, in section 23.3.1, but in fact we seem to need a factor of * 16 to get the right frequency. */ +#ifdef CONFIG_TEGRA186 + i2c_init_clock(i2c_bus, i2c_bus->speed * 2 * 8); +#else clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH, i2c_bus->speed * 2 * 8); +#endif if (i2c_bus->type == TYPE_114) { /* @@ -94,12 +146,17 @@ static void i2c_init_controller(struct i2c_bus *i2c_bus) * is running, we hang, and we need it for the new calc. */ int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16; + unsigned rate = CLK_MULT_STD_FAST_MODE * + (clk_div_stdfst_mode + 1) * i2c_bus->speed * 2; debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__, clk_div_stdfst_mode); +#ifdef CONFIG_TEGRA186 + i2c_init_clock(i2c_bus, rate); +#else clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH, - CLK_MULT_STD_FAST_MODE * (clk_div_stdfst_mode + 1) * - i2c_bus->speed * 2); + rate); +#endif } /* Reset I2C controller. */ @@ -112,7 +169,9 @@ static void i2c_init_controller(struct i2c_bus *i2c_bus) setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK); } +#ifndef CONFIG_TEGRA186 funcmux_select(i2c_bus->periph_id, i2c_bus->pinmux_config); +#endif } static void send_packet_headers( @@ -333,8 +392,12 @@ static int tegra_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) static int tegra_i2c_probe(struct udevice *dev) { struct i2c_bus *i2c_bus = dev_get_priv(dev); +#ifdef CONFIG_TEGRA186 + int ret; +#else const void *blob = gd->fdt_blob; int node = dev->of_offset; +#endif bool is_dvc; i2c_bus->id = dev->seq; @@ -345,6 +408,18 @@ static int tegra_i2c_probe(struct udevice *dev) * We don't have a binding for pinmux yet. Leave it out for now. So * far no one needs anything other than the default. */ +#ifdef CONFIG_TEGRA186 + ret = reset_get_by_name(dev, "i2c", &i2c_bus->reset_ctl); + if (ret) { + error("reset_get_by_name() failed: %d\n", ret); + return ret; + } + ret = clk_get_by_name(dev, "div-clk", &i2c_bus->clk); + if (ret) { + error("clk_get_by_name() failed: %d\n", ret); + return ret; + } +#else i2c_bus->pinmux_config = FUNCMUX_DEFAULT; i2c_bus->periph_id = clock_decode_periph_id(blob, node); @@ -359,6 +434,7 @@ static int tegra_i2c_probe(struct udevice *dev) */ if (i2c_bus->periph_id == -1) return -EINVAL; +#endif is_dvc = dev_get_driver_data(dev) == TYPE_DVC; if (is_dvc) { @@ -370,7 +446,12 @@ static int tegra_i2c_probe(struct udevice *dev) i2c_init_controller(i2c_bus); debug("%s: controller bus %d at %p, periph_id %d, speed %d: ", is_dvc ? "dvc" : "i2c", dev->seq, i2c_bus->regs, - i2c_bus->periph_id, i2c_bus->speed); +#ifndef CONFIG_TEGRA186 + i2c_bus->periph_id, +#else + -1, +#endif + i2c_bus->speed); return 0; } diff --git a/drivers/i2c/tegra_vi_i2c.c b/drivers/i2c/tegra_vi_i2c.c new file mode 100644 index 000000000000..589b4b3c0834 --- /dev/null +++ b/drivers/i2c/tegra_vi_i2c.c @@ -0,0 +1,453 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. All rights reserved. + * Copyright (c) 2010-2016, NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* Information about i2c controller */ +struct i2c_bus { + int id; + enum periph_id periph_id; + int speed; + int pinmux_config; + struct i2c_vi_control *control; + struct i2c_vi_ctlr *regs; +}; + +static void set_packet_mode(struct i2c_bus *i2c_bus) +{ + u32 config; + + config = I2C_CNFG_NEW_MASTER_FSM_MASK | I2C_CNFG_PACKET_MODE_MASK; + + writel(config, &i2c_bus->regs->cnfg); + /* + * program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe + * issues, i.e., some slaves may be wrongly detected. + */ + setbits_le32(&i2c_bus->regs->sl_cnfg, I2C_SL_CNFG_NEWSL_MASK); +} + +static void i2c_reset_controller(struct i2c_bus *i2c_bus) +{ + /* Reset I2C controller. */ + reset_periph(i2c_bus->periph_id, 1); + + /* re-program config register to packet mode */ + set_packet_mode(i2c_bus); +} + +static void i2c_init_controller(struct i2c_bus *i2c_bus) +{ + if (!i2c_bus->speed) + return; + debug("%s: speed=%d\n", __func__, i2c_bus->speed); + /* + * Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8 + * here, in section 23.3.1, but in fact we seem to need a factor of + * 16 to get the right frequency. + */ + clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH, + i2c_bus->speed * 2 * 8); + + /* + * T210 I2C uses a single clock source for standard/fast and + * HS clock speeds. The new clock rate setting calculation is: + * SCL = CLK_SOURCE.I2C / + * (CLK_MULT_STD_FAST_MODE * (I2C_CLK_DIV_STD_FAST_MODE+1) * + * I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1). + * + * NOTE: We do this here, after the initial clock/pll start, + * because if we read the clk_div reg before the controller + * is running, we hang, and we need it for the new calc. + */ + int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16; + debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__, + clk_div_stdfst_mode); + + clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH, + CLK_MULT_STD_FAST_MODE * (clk_div_stdfst_mode + 1) * + i2c_bus->speed * 2); + + /* Reset I2C controller. */ + i2c_reset_controller(i2c_bus); +} + +static void send_packet_headers( + struct i2c_bus *i2c_bus, + struct i2c_trans_info *trans, + u32 packet_id, + bool end_with_repeated_start) +{ + u32 data; + + /* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */ + data = PROTOCOL_TYPE_I2C << PKT_HDR1_PROTOCOL_SHIFT; + data |= packet_id << PKT_HDR1_PKT_ID_SHIFT; + data |= i2c_bus->id << PKT_HDR1_CTLR_ID_SHIFT; + writel(data, &i2c_bus->control->tx_fifo); + debug("pkt header 1 sent (0x%x)\n", data); + + /* prepare header2 */ + data = (trans->num_bytes - 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT; + writel(data, &i2c_bus->control->tx_fifo); + debug("pkt header 2 sent (0x%x)\n", data); + + /* prepare IO specific header: configure the slave address */ + data = trans->address << PKT_HDR3_SLAVE_ADDR_SHIFT; + + /* Enable Read if it is not a write transaction */ + if (!(trans->flags & I2C_IS_WRITE)) + data |= PKT_HDR3_READ_MODE_MASK; + if (end_with_repeated_start) + data |= PKT_HDR3_REPEAT_START_MASK; + + /* Write I2C specific header */ + writel(data, &i2c_bus->control->tx_fifo); + debug("pkt header 3 sent (0x%x)\n", data); +} + +static int wait_for_tx_fifo_empty(struct i2c_vi_control *control) +{ + u32 count; + int timeout_us = I2C_TIMEOUT_USEC; + + while (timeout_us >= 0) { + count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK) + >> TX_FIFO_EMPTY_CNT_SHIFT; + if (count == I2C_FIFO_DEPTH) + return 1; + udelay(10); + timeout_us -= 10; + } + + return 0; +} + +static int wait_for_rx_fifo_notempty(struct i2c_vi_control *control) +{ + u32 count; + int timeout_us = I2C_TIMEOUT_USEC; + + while (timeout_us >= 0) { + count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK) + >> TX_FIFO_FULL_CNT_SHIFT; + if (count) + return 1; + udelay(10); + timeout_us -= 10; + } + + return 0; +} + +static int wait_for_transfer_complete(struct i2c_vi_control *control) +{ + int int_status; + int timeout_us = I2C_TIMEOUT_USEC; + + while (timeout_us >= 0) { + int_status = readl(&control->int_status); + if (int_status & I2C_INT_NO_ACK_MASK) + return -int_status; + if (int_status & I2C_INT_ARBITRATION_LOST_MASK) + return -int_status; + if (int_status & I2C_INT_XFER_COMPLETE_MASK) + return 0; + + udelay(10); + timeout_us -= 10; + } + + return -1; +} + +static int send_recv_packets(struct i2c_bus *i2c_bus, + struct i2c_trans_info *trans) +{ + struct i2c_vi_control *control = i2c_bus->control; + u32 int_status; + u32 words; + u8 *dptr; + u32 local; + uchar last_bytes; + int error = 0; + int is_write = trans->flags & I2C_IS_WRITE; + + /* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */ + int_status = readl(&control->int_status); + writel(int_status, &control->int_status); + + send_packet_headers(i2c_bus, trans, 1, + trans->flags & I2C_USE_REPEATED_START); + + words = DIV_ROUND_UP(trans->num_bytes, 4); + last_bytes = trans->num_bytes & 3; + dptr = trans->buf; + + while (words) { + u32 *wptr = (u32 *)dptr; + + if (is_write) { + /* deal with word alignment */ + if ((words == 1) && last_bytes) { + local = 0; + memcpy(&local, dptr, last_bytes); + } else if ((unsigned long)dptr & 3) { + memcpy(&local, dptr, sizeof(u32)); + } else { + local = *wptr; + } + writel(local, &control->tx_fifo); + debug("pkt data sent (0x%x)\n", local); + if (!wait_for_tx_fifo_empty(control)) { + error = -1; + goto exit; + } + } else { + if (!wait_for_rx_fifo_notempty(control)) { + error = -1; + goto exit; + } + /* + * for the last word, we read into our local buffer, + * in case that caller did not provide enough buffer. + */ + local = readl(&control->rx_fifo); + if ((words == 1) && last_bytes) + memcpy(dptr, (char *)&local, last_bytes); + else if ((unsigned long)dptr & 3) + memcpy(dptr, &local, sizeof(u32)); + else + *wptr = local; + debug("pkt data received (0x%x)\n", local); + } + words--; + dptr += sizeof(u32); + } + + if (wait_for_transfer_complete(control)) { + error = -1; + goto exit; + } + return 0; +exit: + /* error, reset the controller. */ + i2c_reset_controller(i2c_bus); + + return error; +} + +static int tegra_i2c_write_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data, + u32 len, bool end_with_repeated_start) +{ + int error; + struct i2c_trans_info trans_info; + + trans_info.address = addr; + trans_info.buf = data; + trans_info.flags = I2C_IS_WRITE; + if (end_with_repeated_start) + trans_info.flags |= I2C_USE_REPEATED_START; + trans_info.num_bytes = len; + trans_info.is_10bit_address = 0; + + error = send_recv_packets(i2c_bus, &trans_info); + if (error) + debug("tegra_i2c_write_data: Error (%d) !!!\n", error); + + return error; +} + +static int tegra_i2c_read_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data, + u32 len) +{ + int error; + struct i2c_trans_info trans_info; + + trans_info.address = addr | 1; + trans_info.buf = data; + trans_info.flags = 0; + trans_info.num_bytes = len; + trans_info.is_10bit_address = 0; + + error = send_recv_packets(i2c_bus, &trans_info); + if (error) + debug("tegra_i2c_read_data: Error (%d) !!!\n", error); + + return error; +} + +static int tegra_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) +{ + struct i2c_bus *i2c_bus = dev_get_priv(dev); + + i2c_bus->speed = speed; + i2c_init_controller(i2c_bus); + + return 0; +} + +static int tegra_i2c_probe(struct udevice *dev) +{ + struct i2c_bus *i2c_bus = dev_get_priv(dev); + const void *blob = gd->fdt_blob; + int node = dev->of_offset; + + i2c_bus->id = dev->seq; + i2c_bus->regs = + (struct i2c_vi_ctlr *)fdtdec_get_addr(blob, node, "reg"); + + i2c_bus->periph_id = clock_decode_periph_id(blob, node); + + /* + * Unfortunately, U-Boot doesn't yet support multiple 'clocks' + * entries in the DT. We need to have the I2CSLOW and HOST1X + * periphs unreset/clocked so we can access the VI_I2C register + * space. Do that here. + */ + + clock_set_enable(PERIPH_ID_I2CSLOW, 1); + clock_set_enable(PERIPH_ID_HOST1X, 1); + + /* Give clocks time to stabilize */ + udelay(IO_STABILIZATION_DELAY); + + reset_set_enable(PERIPH_ID_I2CSLOW, 0); + reset_set_enable(PERIPH_ID_HOST1X, 0); + + if (i2c_bus->periph_id == -1) + return -EINVAL; + + i2c_bus->control = &i2c_bus->regs->control; + + i2c_init_controller(i2c_bus); + debug("%s: %s controller bus %d at %p, periph_id %d, speed %d\n", + __func__, "VI", dev->seq, i2c_bus->regs, + i2c_bus->periph_id, i2c_bus->speed); + + return 0; +} + +/* i2c write version without the register address */ +static int i2c_write_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer, + int len, bool end_with_repeated_start) +{ + int rc; + + debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len); + debug("write_data: "); + /* use rc for counter */ + for (rc = 0; rc < len; ++rc) + debug(" 0x%02x", buffer[rc]); + debug("\n"); + + /* Shift 7-bit address over for lower-level i2c functions */ + rc = tegra_i2c_write_data(i2c_bus, chip << 1, buffer, len, + end_with_repeated_start); + if (rc) + debug("i2c_write_data(): rc=%d\n", rc); + + return rc; +} + +/* i2c read version without the register address */ +static int i2c_read_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer, + int len) +{ + int rc; + + debug("inside i2c_read_data():\n"); + /* Shift 7-bit address over for lower-level i2c functions */ + rc = tegra_i2c_read_data(i2c_bus, chip << 1, buffer, len); + if (rc) { + debug("i2c_read_data(): rc=%d\n", rc); + return rc; + } + + debug("i2c_read_data: "); + /* reuse rc for counter*/ + for (rc = 0; rc < len; ++rc) + debug(" 0x%02x", buffer[rc]); + debug("\n"); + + return 0; +} + +/* Probe to see if a chip is present. */ +static int tegra_i2c_probe_chip(struct udevice *bus, uint chip_addr, + uint chip_flags) +{ + struct i2c_bus *i2c_bus = dev_get_priv(bus); + int rc; + u8 reg; + + /* Shift 7-bit address over for lower-level i2c functions */ + rc = tegra_i2c_write_data(i2c_bus, chip_addr << 1, ®, sizeof(reg), + false); + + return rc; +} + +static int tegra_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, + int nmsgs) +{ + struct i2c_bus *i2c_bus = dev_get_priv(bus); + int ret; + + debug("i2c_xfer: %d messages\n", nmsgs); + for (; nmsgs > 0; nmsgs--, msg++) { + bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD); + + debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); + if (msg->flags & I2C_M_RD) { + ret = i2c_read_data(i2c_bus, msg->addr, msg->buf, + msg->len); + } else { + ret = i2c_write_data(i2c_bus, msg->addr, msg->buf, + msg->len, next_is_read); + } + if (ret) { + debug("i2c_write: error sending\n"); + return -EREMOTEIO; + } + } + + return 0; +} + +static const struct dm_i2c_ops tegra_i2c_ops = { + .xfer = tegra_i2c_xfer, + .probe_chip = tegra_i2c_probe_chip, + .set_bus_speed = tegra_i2c_set_bus_speed, +}; + +static const struct udevice_id tegra_i2c_ids[] = { + { .compatible = "nvidia,tegra210-i2c-vi" }, + { } +}; + +U_BOOT_DRIVER(i2c_vi_tegra) = { + .name = "i2c_vi_tegra", + .id = UCLASS_I2C, + .of_match = tegra_i2c_ids, + .probe = tegra_i2c_probe, + .priv_auto_alloc_size = sizeof(struct i2c_bus), + .ops = &tegra_i2c_ops, +}; diff --git a/drivers/mailbox/tegra-hsp.c b/drivers/mailbox/tegra-hsp.c index 5c781a50b6ac..3d0362d58740 100644 --- a/drivers/mailbox/tegra-hsp.c +++ b/drivers/mailbox/tegra-hsp.c @@ -8,7 +8,19 @@ #include #include #include -#include +#include + +#define TEGRA_HSP_INT_DIMENSIONING 0x380 +#define TEGRA_HSP_INT_DIMENSIONING_NSI_SHIFT 16 +#define TEGRA_HSP_INT_DIMENSIONING_NSI_MASK 0xf +#define TEGRA_HSP_INT_DIMENSIONING_NDB_SHIFT 12 +#define TEGRA_HSP_INT_DIMENSIONING_NDB_MASK 0xf +#define TEGRA_HSP_INT_DIMENSIONING_NAS_SHIFT 8 +#define TEGRA_HSP_INT_DIMENSIONING_NAS_MASK 0xf +#define TEGRA_HSP_INT_DIMENSIONING_NSS_SHIFT 4 +#define TEGRA_HSP_INT_DIMENSIONING_NSS_MASK 0xf +#define TEGRA_HSP_INT_DIMENSIONING_NSM_SHIFT 0 +#define TEGRA_HSP_INT_DIMENSIONING_NSM_MASK 0xf #define TEGRA_HSP_DB_REG_TRIGGER 0x0 #define TEGRA_HSP_DB_REG_ENABLE 0x4 @@ -51,7 +63,7 @@ static void tegra_hsp_writel(struct tegra_hsp *thsp, uint32_t val, static int tegra_hsp_db_id(ulong chan_id) { switch (chan_id) { - case TEGRA_HSP_MASTER_BPMP: + case (HSP_MBOX_TYPE_DB << 16) | HSP_DB_MASTER_BPMP: return TEGRA_HSP_DB_ID_BPMP; default: debug("Invalid channel ID\n"); @@ -59,6 +71,21 @@ static int tegra_hsp_db_id(ulong chan_id) } } +static int tegra_hsp_of_xlate(struct mbox_chan *chan, + struct fdtdec_phandle_args *args) +{ + debug("%s(chan=%p)\n", __func__, chan); + + if (args->args_count != 2) { + debug("Invaild args_count: %d\n", args->args_count); + return -EINVAL; + } + + chan->id = (args->args[0] << 16) | args->args[1]; + + return 0; +} + static int tegra_hsp_request(struct mbox_chan *chan) { int db_id; @@ -121,6 +148,7 @@ static int tegra_hsp_bind(struct udevice *dev) static int tegra_hsp_probe(struct udevice *dev) { struct tegra_hsp *thsp = dev_get_priv(dev); + u32 val; int nr_sm, nr_ss, nr_as; debug("%s(dev=%p)\n", __func__, dev); @@ -129,12 +157,14 @@ static int tegra_hsp_probe(struct udevice *dev) if (thsp->regs == FDT_ADDR_T_NONE) return -ENODEV; - nr_sm = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "nvidia,num-SM", - 0); - nr_ss = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "nvidia,num-SS", - 0); - nr_as = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "nvidia,num-AS", - 0); + val = readl(thsp->regs + TEGRA_HSP_INT_DIMENSIONING); + nr_sm = (val >> TEGRA_HSP_INT_DIMENSIONING_NSM_SHIFT) & + TEGRA_HSP_INT_DIMENSIONING_NSM_MASK; + nr_ss = (val >> TEGRA_HSP_INT_DIMENSIONING_NSS_SHIFT) & + TEGRA_HSP_INT_DIMENSIONING_NSS_MASK; + nr_as = (val >> TEGRA_HSP_INT_DIMENSIONING_NAS_SHIFT) & + TEGRA_HSP_INT_DIMENSIONING_NAS_MASK; + thsp->db_base = (1 + (nr_sm >> 1) + nr_ss + nr_as) << 16; return 0; @@ -146,6 +176,7 @@ static const struct udevice_id tegra_hsp_ids[] = { }; struct mbox_ops tegra_hsp_mbox_ops = { + .of_xlate = tegra_hsp_of_xlate, .request = tegra_hsp_request, .free = tegra_hsp_free, .send = tegra_hsp_send, diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 2373037685c2..55c6845c0cb2 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -130,6 +130,18 @@ config SYSRESET to effect a reset. The uclass will try all available drivers when reset_walk() is called. +config TEGRA186_BPMP + bool "Enable support for the Tegra186 BPMP driver" + depends on TEGRA186 + help + The Tegra BPMP (Boot and Power Management Processor) is a separate + auxiliary CPU embedded into Tegra to perform power management work, + and controls related features such as clocks, resets, power domains, + PMIC I2C bus, etc. This driver provides the core low-level + communication path by which feature-specific drivers (such as clock) + can make requests to the BPMP. This driver is similar to an MFD + driver in the Linux kernel. + config WINBOND_W83627 bool "Enable Winbond Super I/O driver" help diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 066639ba1f10..679a24d36d87 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o obj-$(CONFIG_STATUS_LED) += status_led.o obj-$(CONFIG_SANDBOX) += swap_case.o obj-$(CONFIG_SANDBOX) += syscon_sandbox.o +obj-$(CONFIG_TEGRA186_BPMP) += tegra186_bpmp.o obj-$(CONFIG_TWL4030_LED) += twl4030_led.o obj-$(CONFIG_FSL_IFC) += fsl_ifc.o obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o diff --git a/drivers/misc/misc-uclass.c b/drivers/misc/misc-uclass.c index 13a6ea508b14..d9eea3dac5c0 100644 --- a/drivers/misc/misc-uclass.c +++ b/drivers/misc/misc-uclass.c @@ -45,6 +45,17 @@ int misc_ioctl(struct udevice *dev, unsigned long request, void *buf) return ops->ioctl(dev, request, buf); } +int misc_call(struct udevice *dev, int msgid, void *tx_msg, int tx_size, + void *rx_msg, int rx_size) +{ + const struct misc_ops *ops = device_get_ops(dev); + + if (!ops->call) + return -ENOSYS; + + return ops->call(dev, msgid, tx_msg, tx_size, rx_msg, rx_size); +} + UCLASS_DRIVER(misc) = { .id = UCLASS_MISC, .name = "misc", diff --git a/drivers/misc/tegra186_bpmp.c b/drivers/misc/tegra186_bpmp.c new file mode 100644 index 000000000000..f4ddbea3760e --- /dev/null +++ b/drivers/misc/tegra186_bpmp.c @@ -0,0 +1,257 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define BPMP_IVC_FRAME_COUNT 1 +#define BPMP_IVC_FRAME_SIZE 128 + +#define BPMP_FLAG_DO_ACK BIT(0) +#define BPMP_FLAG_RING_DOORBELL BIT(1) + +DECLARE_GLOBAL_DATA_PTR; + +struct tegra186_bpmp { + struct mbox_chan mbox; + struct tegra_ivc ivc; +}; + +static int tegra186_bpmp_call(struct udevice *dev, int mrq, void *tx_msg, + int tx_size, void *rx_msg, int rx_size) +{ + struct tegra186_bpmp *priv = dev_get_priv(dev); + int ret, err; + void *ivc_frame; + struct mrq_request *req; + struct mrq_response *resp; + ulong start_time; + + debug("%s(dev=%p, mrq=%u, tx_msg=%p, tx_size=%d, rx_msg=%p, rx_size=%d) (priv=%p)\n", + __func__, dev, mrq, tx_msg, tx_size, rx_msg, rx_size, priv); + + if ((tx_size > BPMP_IVC_FRAME_SIZE) || (rx_size > BPMP_IVC_FRAME_SIZE)) + return -EINVAL; + + ret = tegra_ivc_write_get_next_frame(&priv->ivc, &ivc_frame); + if (ret) { + error("tegra_ivc_write_get_next_frame() failed: %d\n", ret); + return ret; + } + + req = ivc_frame; + req->mrq = mrq; + req->flags = BPMP_FLAG_DO_ACK | BPMP_FLAG_RING_DOORBELL; + memcpy(req + 1, tx_msg, tx_size); + + ret = tegra_ivc_write_advance(&priv->ivc); + if (ret) { + error("tegra_ivc_write_advance() failed: %d\n", ret); + return ret; + } + + start_time = timer_get_us(); + for (;;) { + ret = tegra_ivc_channel_notified(&priv->ivc); + if (ret) { + error("tegra_ivc_channel_notified() failed: %d\n", ret); + return ret; + } + + ret = tegra_ivc_read_get_next_frame(&priv->ivc, &ivc_frame); + if (!ret) + break; + + /* Timeout 20ms; roughly 10x current max observed duration */ + if ((timer_get_us() - start_time) > 20 * 1000) { + error("tegra_ivc_read_get_next_frame() timed out (%d)\n", + ret); + return -ETIMEDOUT; + } + } + + resp = ivc_frame; + err = resp->err; + if (!err && rx_msg && rx_size) + memcpy(rx_msg, resp + 1, rx_size); + + ret = tegra_ivc_read_advance(&priv->ivc); + if (ret) { + error("tegra_ivc_write_advance() failed: %d\n", ret); + return ret; + } + + if (err) { + error("BPMP responded with error %d\n", err); + /* err isn't a U-Boot error code, so don't that */ + return -EIO; + } + + return rx_size; +} + +/** + * The BPMP exposes multiple different services. We create a sub-device for + * each separate type of service, since each device must be of the appropriate + * UCLASS. + */ +static int tegra186_bpmp_bind(struct udevice *dev) +{ + int ret; + struct udevice *child; + + debug("%s(dev=%p)\n", __func__, dev); + + ret = device_bind_driver_to_node(dev, "tegra186_clk", "tegra186_clk", + dev->of_offset, &child); + if (ret) + return ret; + + ret = device_bind_driver_to_node(dev, "tegra186_reset", + "tegra186_reset", dev->of_offset, + &child); + if (ret) + return ret; + + ret = device_bind_driver_to_node(dev, "tegra186_power_domain", + "tegra186_power_domain", + dev->of_offset, &child); + if (ret) + return ret; + + ret = dm_scan_fdt_dev(dev); + if (ret) + return ret; + + return 0; +} + +static ulong tegra186_bpmp_get_shmem(struct udevice *dev, int index) +{ + int ret; + struct fdtdec_phandle_args args; + fdt_addr_t reg; + + ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset, + "shmem", NULL, 0, index, &args); + if (ret < 0) { + error("fdtdec_parse_phandle_with_args() failed: %d\n", ret); + return ret; + } + + reg = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, args.node, + "reg", 0, NULL, true); + if (reg == FDT_ADDR_T_NONE) { + error("fdtdec_get_addr_size_auto_noparent() failed\n"); + return -ENODEV; + } + + return reg; +} + +static void tegra186_bpmp_ivc_notify(struct tegra_ivc *ivc) +{ + struct tegra186_bpmp *priv = + container_of(ivc, struct tegra186_bpmp, ivc); + int ret; + + ret = mbox_send(&priv->mbox, NULL); + if (ret) + error("mbox_send() failed: %d\n", ret); +} + +static int tegra186_bpmp_probe(struct udevice *dev) +{ + struct tegra186_bpmp *priv = dev_get_priv(dev); + int ret; + ulong tx_base, rx_base, start_time; + + debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv); + + ret = mbox_get_by_index(dev, 0, &priv->mbox); + if (ret) { + error("mbox_get_by_index() failed: %d\n", ret); + return ret; + } + + tx_base = tegra186_bpmp_get_shmem(dev, 0); + if (IS_ERR_VALUE(tx_base)) { + error("tegra186_bpmp_get_shmem failed for tx_base\n"); + return tx_base; + } + rx_base = tegra186_bpmp_get_shmem(dev, 1); + if (IS_ERR_VALUE(rx_base)) { + error("tegra186_bpmp_get_shmem failed for rx_base\n"); + return rx_base; + } + debug("shmem: rx=%lx, tx=%lx\n", rx_base, tx_base); + + ret = tegra_ivc_init(&priv->ivc, rx_base, tx_base, BPMP_IVC_FRAME_COUNT, + BPMP_IVC_FRAME_SIZE, tegra186_bpmp_ivc_notify); + if (ret) { + error("tegra_ivc_init() failed: %d\n", ret); + return ret; + } + + tegra_ivc_channel_reset(&priv->ivc); + start_time = timer_get_us(); + for (;;) { + ret = tegra_ivc_channel_notified(&priv->ivc); + if (!ret) + break; + + /* Timeout 100ms */ + if ((timer_get_us() - start_time) > 100 * 1000) { + error("Initial IVC reset timed out (%d)\n", ret); + ret = -ETIMEDOUT; + goto err_free_mbox; + } + } + + return 0; + +err_free_mbox: + mbox_free(&priv->mbox); + + return ret; +} + +static int tegra186_bpmp_remove(struct udevice *dev) +{ + struct tegra186_bpmp *priv = dev_get_priv(dev); + + debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv); + + mbox_free(&priv->mbox); + + return 0; +} + +static struct misc_ops tegra186_bpmp_ops = { + .call = tegra186_bpmp_call, +}; + +static const struct udevice_id tegra186_bpmp_ids[] = { + { .compatible = "nvidia,tegra186-bpmp" }, + { } +}; + +U_BOOT_DRIVER(tegra186_bpmp) = { + .name = "tegra186_bpmp", + .id = UCLASS_MISC, + .of_match = tegra186_bpmp_ids, + .bind = tegra186_bpmp_bind, + .probe = tegra186_bpmp_probe, + .remove = tegra186_bpmp_remove, + .ops = &tegra186_bpmp_ops, + .priv_auto_alloc_size = sizeof(struct tegra186_bpmp), +}; diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c index 96dcdbec5196..f78b20e6fd2e 100644 --- a/drivers/mmc/msm_sdhci.c +++ b/drivers/mmc/msm_sdhci.c @@ -168,7 +168,8 @@ static int msm_ofdata_to_platdata(struct udevice *dev) priv->base = (void *)fdtdec_get_addr_size_auto_parent(gd->fdt_blob, parent->of_offset, dev->of_offset, - "reg", 1, NULL); + "reg", 1, NULL, + false); if (priv->base == (void *)FDT_ADDR_T_NONE || host->ioaddr == (void *)FDT_ADDR_T_NONE) return -EINVAL; diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c index c9d9432e5e87..5901ebaecbea 100644 --- a/drivers/mmc/tegra_mmc.c +++ b/drivers/mmc/tegra_mmc.c @@ -9,6 +9,7 @@ #include #include +#include #include #include #ifndef CONFIG_TEGRA186 @@ -19,6 +20,15 @@ #include #include +/* + * FIXME: TODO: This driver contains a number of ifdef CONFIG_TEGRA186 that + * should not be present. These are needed because newer Tegra SoCs support + * only the standard clock/reset APIs, whereas older Tegra SoCs support only + * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be + * fixed to implement the standard APIs, and all drivers converted to solely + * use the new standard APIs, with no ifdefs. + */ + DECLARE_GLOBAL_DATA_PTR; struct mmc_host mmc_host[CONFIG_SYS_MMC_MAX_DEVICE]; @@ -359,11 +369,29 @@ static void mmc_change_clock(struct mmc_host *host, uint clock) */ if (clock == 0) goto out; -#ifndef CONFIG_TEGRA186 - clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock, - &div); +#ifdef CONFIG_TEGRA186 + { + ulong rate = clk_set_rate(&host->clk, clock); + div = (rate + clock - 1) / clock; + } #else - div = (20000000 + clock - 1) / clock; +#if defined(CONFIG_TEGRA210) + if (host->mmc_id == PERIPH_ID_SDMMC1 && clock <= 400000) { + /* clock_adjust_periph_pll_div() chooses a 'bad' clock + * on SDMMC1 T210, so skip it here and force a clock + * that's been spec'd in the table in the TRM for + * card-detect (400KHz). + */ + uint effective_rate = clock_adjust_periph_pll_div(host->mmc_id, + CLOCK_ID_PERIPH, 24727273, NULL); + div = 62; + + debug("%s: WAR: Using SDMMC1 clock of %u, div %d to achieve %dHz card clock ...\n", + __func__, effective_rate, div, clock); + } else +#endif + clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock, + &div); #endif debug("div = %d\n", div); @@ -538,6 +566,9 @@ static int do_mmc_init(int dev_index, bool removable) { struct mmc_host *host; struct mmc *mmc; +#ifdef CONFIG_TEGRA186 + int ret; +#endif /* DT should have been read & host config filled in */ host = &mmc_host[dev_index]; @@ -549,7 +580,21 @@ static int do_mmc_init(int dev_index, bool removable) gpio_get_number(&host->cd_gpio)); host->clock = 0; -#ifndef CONFIG_TEGRA186 + +#ifdef CONFIG_TEGRA186 + ret = reset_assert(&host->reset_ctl); + if (ret) + return ret; + ret = clk_enable(&host->clk); + if (ret) + return ret; + ret = clk_set_rate(&host->clk, 20000000); + if (IS_ERR_VALUE(ret)) + return ret; + ret = reset_deassert(&host->reset_ctl); + if (ret) + return ret; +#else clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000); #endif @@ -576,18 +621,15 @@ static int do_mmc_init(int dev_index, bool removable) * (actually 52MHz) */ host->cfg.f_min = 375000; -#ifndef CONFIG_TEGRA186 host->cfg.f_max = 48000000; -#else - host->cfg.f_max = 375000; -#endif host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; mmc = mmc_create(&host->cfg, host); - mmc->block_dev.removable = removable; if (mmc == NULL) return -1; + mmc->block_dev.removable = removable; + mmc->block_dev.devnum = dev_index; return 0; } @@ -612,7 +654,27 @@ static int mmc_get_config(const void *blob, int node, struct mmc_host *host, return -FDT_ERR_NOTFOUND; } -#ifndef CONFIG_TEGRA186 +#ifdef CONFIG_TEGRA186 + { + /* + * FIXME: This variable should go away when the MMC device + * actually is a udevice. + */ + struct udevice dev; + int ret; + dev.of_offset = node; + ret = reset_get_by_name(&dev, "sdhci", &host->reset_ctl); + if (ret) { + debug("reset_get_by_name() failed: %d\n", ret); + return ret; + } + ret = clk_get_by_index(&dev, 0, &host->clk); + if (ret) { + debug("clk_get_by_index() failed: %d\n", ret); + return ret; + } + } +#else host->mmc_id = clock_decode_periph_id(blob, node); if (host->mmc_id == PERIPH_ID_NONE) { debug("%s: could not decode periph id\n", __func__); diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c index c577d9ed6c91..924a81e6c27e 100644 --- a/drivers/mtd/spi/sf_params.c +++ b/drivers/mtd/spi/sf_params.c @@ -51,6 +51,7 @@ const struct spi_flash_params spi_flash_params_table[] = { {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP}, {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP}, {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, + {"MX25U3235F", 0xc22536, 0x0, 4 * 1024, 1024, RD_NORM, SECT_4K}, #endif #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, RD_NORM, 0}, diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index c1cb689ccf33..ba29eb02a758 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -64,6 +64,17 @@ config ALTERA_TSE Please find details on the "Triple-Speed Ethernet MegaCore Function Resource Center" of Altera. +config DWC_ETH_QOS + bool "Synopsys DWC Ethernet QOS device support" + depends on DM_ETH + select PHYLIB + help + This driver supports the Synopsys Designware Ethernet QOS (Quality + Of Service) IP block. The IP supports many options for bus type, + clocking/reset structure, and feature list. This driver currently + supports the specific configuration used in NVIDIA's Tegra186 chip, + but should be extensible to other combinations quite easily. + config E1000 bool "Intel PRO/1000 Gigabit Ethernet support" help diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 570259216980..94b2bb022122 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -75,3 +75,4 @@ obj-$(CONFIG_FSL_MC_ENET) += ldpaa_eth/ obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o obj-$(CONFIG_VSC9953) += vsc9953.o obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o +obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index 2ce4ec69f1df..2a458955ed05 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -1145,7 +1145,8 @@ static const struct eth_ops cpsw_eth_ops = { static inline fdt_addr_t cpsw_get_addr_by_node(const void *fdt, int node) { - return fdtdec_get_addr_size_auto_noparent(fdt, node, "reg", 0, NULL); + return fdtdec_get_addr_size_auto_noparent(fdt, node, "reg", 0, NULL, + false); } static int cpsw_eth_ofdata_to_platdata(struct udevice *dev) diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c new file mode 100644 index 000000000000..81eeba2e051a --- /dev/null +++ b/drivers/net/dwc_eth_qos.c @@ -0,0 +1,1552 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + * + * Portions based on U-Boot's rtl8169.c. + */ + +/* + * This driver supports the Synopsys Designware Ethernet QOS (Quality Of + * Service) IP block. The IP supports multiple options for bus type, clocking/ + * reset structure, and feature list. + * + * The driver is written such that generic core logic is kept separate from + * configuration-specific logic. Code that interacts with configuration- + * specific resources is split out into separate functions to avoid polluting + * common code. If/when this driver is enhanced to support multiple + * configurations, the core code should be adapted to call all configuration- + * specific functions through function pointers, with the definition of those + * function pointers being supplied by struct udevice_id eqos_ids[]'s .data + * field. + * + * The following configurations are currently supported: + * tegra186: + * NVIDIA's Tegra186 chip. This configuration uses an AXI master/DMA bus, an + * AHB slave/register bus, contains the DMA, MTL, and MAC sub-blocks, and + * supports a single RGMII PHY. This configuration also has SW control over + * all clock and reset signals to the HW block. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Core registers */ + +#define EQOS_MAC_REGS_BASE 0x000 +struct eqos_mac_regs { + uint32_t configuration; /* 0x000 */ + uint32_t unused_004[(0x070 - 0x004) / 4]; /* 0x004 */ + uint32_t q0_tx_flow_ctrl; /* 0x070 */ + uint32_t unused_070[(0x090 - 0x074) / 4]; /* 0x074 */ + uint32_t rx_flow_ctrl; /* 0x090 */ + uint32_t unused_094; /* 0x094 */ + uint32_t txq_prty_map0; /* 0x098 */ + uint32_t unused_09c; /* 0x09c */ + uint32_t rxq_ctrl0; /* 0x0a0 */ + uint32_t unused_0a4; /* 0x0a4 */ + uint32_t rxq_ctrl2; /* 0x0a8 */ + uint32_t unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */ + uint32_t us_tic_counter; /* 0x0dc */ + uint32_t unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */ + uint32_t hw_feature0; /* 0x11c */ + uint32_t hw_feature1; /* 0x120 */ + uint32_t hw_feature2; /* 0x124 */ + uint32_t unused_128[(0x200 - 0x128) / 4]; /* 0x128 */ + uint32_t mdio_address; /* 0x200 */ + uint32_t mdio_data; /* 0x204 */ + uint32_t unused_208[(0x300 - 0x208) / 4]; /* 0x208 */ + uint32_t address0_high; /* 0x300 */ + uint32_t address0_low; /* 0x304 */ +}; + +#define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23) +#define EQOS_MAC_CONFIGURATION_CST BIT(21) +#define EQOS_MAC_CONFIGURATION_ACS BIT(20) +#define EQOS_MAC_CONFIGURATION_WD BIT(19) +#define EQOS_MAC_CONFIGURATION_JD BIT(17) +#define EQOS_MAC_CONFIGURATION_JE BIT(16) +#define EQOS_MAC_CONFIGURATION_PS BIT(15) +#define EQOS_MAC_CONFIGURATION_FES BIT(14) +#define EQOS_MAC_CONFIGURATION_DM BIT(13) +#define EQOS_MAC_CONFIGURATION_TE BIT(1) +#define EQOS_MAC_CONFIGURATION_RE BIT(0) + +#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16 +#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_MASK 0xffff +#define EQOS_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1) + +#define EQOS_MAC_RX_FLOW_CTRL_RFE BIT(0) + +#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT 0 +#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK 0xff + +#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0 +#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3 +#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0 +#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2 + +#define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0 +#define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff + +#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6 +#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f +#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0 +#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f + +#define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21 +#define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16 +#define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8 +#define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2 +#define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4) +#define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT 2 +#define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3 +#define EQOS_MAC_MDIO_ADDRESS_GOC_WRITE 1 +#define EQOS_MAC_MDIO_ADDRESS_C45E BIT(1) +#define EQOS_MAC_MDIO_ADDRESS_GB BIT(0) + +#define EQOS_MAC_MDIO_DATA_GD_MASK 0xffff + +#define EQOS_MTL_REGS_BASE 0xd00 +struct eqos_mtl_regs { + uint32_t txq0_operation_mode; /* 0xd00 */ + uint32_t unused_d04; /* 0xd04 */ + uint32_t txq0_debug; /* 0xd08 */ + uint32_t unused_d0c[(0xd18 - 0xd0c) / 4]; /* 0xd0c */ + uint32_t txq0_quantum_weight; /* 0xd18 */ + uint32_t unused_d1c[(0xd30 - 0xd1c) / 4]; /* 0xd1c */ + uint32_t rxq0_operation_mode; /* 0xd30 */ + uint32_t unused_d34; /* 0xd34 */ + uint32_t rxq0_debug; /* 0xd38 */ +}; + +#define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16 +#define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK 0x1ff +#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2 +#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK 3 +#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2 +#define EQOS_MTL_TXQ0_OPERATION_MODE_TSF BIT(1) +#define EQOS_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0) + +#define EQOS_MTL_TXQ0_DEBUG_TXQSTS BIT(4) +#define EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT 1 +#define EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK 3 + +#define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 20 +#define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK 0x3ff +#define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT 14 +#define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK 0x3f +#define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT 8 +#define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3f +#define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7) +#define EQOS_MTL_RXQ0_OPERATION_MODE_RSF BIT(5) + +#define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16 +#define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK 0x7fff +#define EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4 +#define EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK 3 + +#define EQOS_DMA_REGS_BASE 0x1000 +struct eqos_dma_regs { + uint32_t mode; /* 0x1000 */ + uint32_t sysbus_mode; /* 0x1004 */ + uint32_t unused_1008[(0x1100 - 0x1008) / 4]; /* 0x1008 */ + uint32_t ch0_control; /* 0x1100 */ + uint32_t ch0_tx_control; /* 0x1104 */ + uint32_t ch0_rx_control; /* 0x1108 */ + uint32_t unused_110c; /* 0x110c */ + uint32_t ch0_txdesc_list_haddress; /* 0x1110 */ + uint32_t ch0_txdesc_list_address; /* 0x1114 */ + uint32_t ch0_rxdesc_list_haddress; /* 0x1118 */ + uint32_t ch0_rxdesc_list_address; /* 0x111c */ + uint32_t ch0_txdesc_tail_pointer; /* 0x1120 */ + uint32_t unused_1124; /* 0x1124 */ + uint32_t ch0_rxdesc_tail_pointer; /* 0x1128 */ + uint32_t ch0_txdesc_ring_length; /* 0x112c */ + uint32_t ch0_rxdesc_ring_length; /* 0x1130 */ +}; + +#define EQOS_DMA_MODE_SWR BIT(0) + +#define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16 +#define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK 0xf +#define EQOS_DMA_SYSBUS_MODE_EAME BIT(11) +#define EQOS_DMA_SYSBUS_MODE_BLEN16 BIT(3) +#define EQOS_DMA_SYSBUS_MODE_BLEN8 BIT(2) +#define EQOS_DMA_SYSBUS_MODE_BLEN4 BIT(1) + +#define EQOS_DMA_CH0_CONTROL_PBLX8 BIT(16) + +#define EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16 +#define EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK 0x3f +#define EQOS_DMA_CH0_TX_CONTROL_OSP BIT(4) +#define EQOS_DMA_CH0_TX_CONTROL_ST BIT(0) + +#define EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16 +#define EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK 0x3f +#define EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 1 +#define EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK 0x3fff +#define EQOS_DMA_CH0_RX_CONTROL_SR BIT(0) + +/* These registers are Tegra186-specific */ +#define EQOS_TEGRA186_REGS_BASE 0x8800 +struct eqos_tegra186_regs { + uint32_t sdmemcomppadctrl; /* 0x8800 */ + uint32_t auto_cal_config; /* 0x8804 */ + uint32_t unused_8808; /* 0x8808 */ + uint32_t auto_cal_status; /* 0x880c */ +}; + +#define EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD BIT(31) + +#define EQOS_AUTO_CAL_CONFIG_START BIT(31) +#define EQOS_AUTO_CAL_CONFIG_ENABLE BIT(29) + +#define EQOS_AUTO_CAL_STATUS_ACTIVE BIT(31) + +/* Descriptors */ + +#define EQOS_DESCRIPTOR_WORDS 4 +#define EQOS_DESCRIPTOR_SIZE (EQOS_DESCRIPTOR_WORDS * 4) +/* We assume ARCH_DMA_MINALIGN >= 16; 16 is the EQOS HW minimum */ +#define EQOS_DESCRIPTOR_ALIGN ARCH_DMA_MINALIGN +#define EQOS_DESCRIPTORS_TX 4 +#define EQOS_DESCRIPTORS_RX 4 +#define EQOS_DESCRIPTORS_NUM (EQOS_DESCRIPTORS_TX + EQOS_DESCRIPTORS_RX) +#define EQOS_DESCRIPTORS_SIZE ALIGN(EQOS_DESCRIPTORS_NUM * \ + EQOS_DESCRIPTOR_SIZE, ARCH_DMA_MINALIGN) +#define EQOS_BUFFER_ALIGN ARCH_DMA_MINALIGN +#define EQOS_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN) +#define EQOS_RX_BUFFER_SIZE (EQOS_DESCRIPTORS_RX * EQOS_MAX_PACKET_SIZE) + +/* + * Warn if the cache-line size is larger than the descriptor size. In such + * cases the driver will likely fail because the CPU needs to flush the cache + * when requeuing RX buffers, therefore descriptors written by the hardware + * may be discarded. Architectures with full IO coherence, such as x86, do not + * experience this issue, and hence are excluded from this condition. + * + * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause + * the driver to allocate descriptors from a pool of non-cached memory. + */ +#if EQOS_DESCRIPTOR_SIZE < ARCH_DMA_MINALIGN +#if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \ + !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86) +#warning Cache line size is larger than descriptor size +#endif +#endif + +struct eqos_desc { + u32 des0; + u32 des1; + u32 des2; + u32 des3; +}; + +#define EQOS_DESC3_OWN BIT(31) +#define EQOS_DESC3_FD BIT(29) +#define EQOS_DESC3_LD BIT(28) +#define EQOS_DESC3_BUF1V BIT(24) + +struct eqos_config { + bool reg_access_always_ok; +}; + +struct eqos_priv { + struct udevice *dev; + const struct eqos_config *config; + fdt_addr_t regs; + struct eqos_mac_regs *mac_regs; + struct eqos_mtl_regs *mtl_regs; + struct eqos_dma_regs *dma_regs; + struct eqos_tegra186_regs *tegra186_regs; + struct reset_ctl reset_ctl; + struct gpio_desc phy_reset_gpio; + struct clk clk_master_bus; + struct clk clk_rx; + struct clk clk_ptp_ref; + struct clk clk_tx; + struct clk clk_slave_bus; + struct mii_dev *mii; + struct phy_device *phy; + void *descs; + struct eqos_desc *tx_descs; + struct eqos_desc *rx_descs; + int tx_desc_idx, rx_desc_idx; + void *tx_dma_buf; + void *rx_dma_buf; + void *rx_pkt; + bool started; + bool reg_access_ok; +}; + +/* + * TX and RX descriptors are 16 bytes. This causes problems with the cache + * maintenance on CPUs where the cache-line size exceeds the size of these + * descriptors. What will happen is that when the driver receives a packet + * it will be immediately requeued for the hardware to reuse. The CPU will + * therefore need to flush the cache-line containing the descriptor, which + * will cause all other descriptors in the same cache-line to be flushed + * along with it. If one of those descriptors had been written to by the + * device those changes (and the associated packet) will be lost. + * + * To work around this, we make use of non-cached memory if available. If + * descriptors are mapped uncached there's no need to manually flush them + * or invalidate them. + * + * Note that this only applies to descriptors. The packet data buffers do + * not have the same constraints since they are 1536 bytes large, so they + * are unlikely to share cache-lines. + */ +static void *eqos_alloc_descs(unsigned int num) +{ +#ifdef CONFIG_SYS_NONCACHED_MEMORY + return (void *)noncached_alloc(EQOS_DESCRIPTORS_SIZE, + EQOS_DESCRIPTOR_ALIGN); +#else + return memalign(EQOS_DESCRIPTOR_ALIGN, EQOS_DESCRIPTORS_SIZE); +#endif +} + +static void eqos_free_descs(void *descs) +{ +#ifdef CONFIG_SYS_NONCACHED_MEMORY + /* FIXME: noncached_alloc() has no opposite */ +#else + free(descs); +#endif +} + +static void eqos_inval_desc(void *desc) +{ +#ifndef CONFIG_SYS_NONCACHED_MEMORY + unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); + unsigned long end = ALIGN(start + EQOS_DESCRIPTOR_SIZE, + ARCH_DMA_MINALIGN); + + invalidate_dcache_range(start, end); +#endif +} + +static void eqos_flush_desc(void *desc) +{ +#ifndef CONFIG_SYS_NONCACHED_MEMORY + flush_cache((unsigned long)desc, EQOS_DESCRIPTOR_SIZE); +#endif +} + +static void eqos_inval_buffer(void *buf, size_t size) +{ + unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1); + unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN); + + invalidate_dcache_range(start, end); +} + +static void eqos_flush_buffer(void *buf, size_t size) +{ + flush_cache((unsigned long)buf, size); +} + +static int eqos_mdio_wait_idle(struct eqos_priv *eqos) +{ + return wait_for_bit(__func__, &eqos->mac_regs->mdio_address, + EQOS_MAC_MDIO_ADDRESS_GB, false, 1000000, true); +} + +static int eqos_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad, + int mdio_reg) +{ + struct eqos_priv *eqos = bus->priv; + u32 val; + int ret; + + debug("%s(dev=%p, addr=%x, reg=%d):\n", __func__, eqos->dev, mdio_addr, + mdio_reg); + + ret = eqos_mdio_wait_idle(eqos); + if (ret) { + error("MDIO not idle at entry"); + return ret; + } + + val = readl(&eqos->mac_regs->mdio_address); + val &= EQOS_MAC_MDIO_ADDRESS_SKAP | + EQOS_MAC_MDIO_ADDRESS_C45E; + val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) | + (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) | + (EQOS_MAC_MDIO_ADDRESS_CR_20_35 << + EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) | + (EQOS_MAC_MDIO_ADDRESS_GOC_READ << + EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) | + EQOS_MAC_MDIO_ADDRESS_GB; + writel(val, &eqos->mac_regs->mdio_address); + + udelay(10); + + ret = eqos_mdio_wait_idle(eqos); + if (ret) { + error("MDIO read didn't complete"); + return ret; + } + + val = readl(&eqos->mac_regs->mdio_data); + val &= EQOS_MAC_MDIO_DATA_GD_MASK; + + debug("%s: val=%x\n", __func__, val); + + return val; +} + +static int eqos_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad, + int mdio_reg, u16 mdio_val) +{ + struct eqos_priv *eqos = bus->priv; + u32 val; + int ret; + + debug("%s(dev=%p, addr=%x, reg=%d, val=%x):\n", __func__, eqos->dev, + mdio_addr, mdio_reg, mdio_val); + + ret = eqos_mdio_wait_idle(eqos); + if (ret) { + error("MDIO not idle at entry"); + return ret; + } + + writel(mdio_val, &eqos->mac_regs->mdio_data); + + val = readl(&eqos->mac_regs->mdio_address); + val &= EQOS_MAC_MDIO_ADDRESS_SKAP | + EQOS_MAC_MDIO_ADDRESS_C45E; + val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) | + (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) | + (EQOS_MAC_MDIO_ADDRESS_CR_20_35 << + EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) | + (EQOS_MAC_MDIO_ADDRESS_GOC_WRITE << + EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) | + EQOS_MAC_MDIO_ADDRESS_GB; + writel(val, &eqos->mac_regs->mdio_address); + + udelay(10); + + ret = eqos_mdio_wait_idle(eqos); + if (ret) { + error("MDIO read didn't complete"); + return ret; + } + + return 0; +} + +static int eqos_start_clks_tegra186(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + int ret; + + debug("%s(dev=%p):\n", __func__, dev); + + ret = clk_enable(&eqos->clk_slave_bus); + if (ret < 0) { + error("clk_enable(clk_slave_bus) failed: %d", ret); + goto err; + } + + ret = clk_enable(&eqos->clk_master_bus); + if (ret < 0) { + error("clk_enable(clk_master_bus) failed: %d", ret); + goto err_disable_clk_slave_bus; + } + + ret = clk_enable(&eqos->clk_rx); + if (ret < 0) { + error("clk_enable(clk_rx) failed: %d", ret); + goto err_disable_clk_master_bus; + } + + ret = clk_enable(&eqos->clk_ptp_ref); + if (ret < 0) { + error("clk_enable(clk_ptp_ref) failed: %d", ret); + goto err_disable_clk_rx; + } + + ret = clk_set_rate(&eqos->clk_ptp_ref, 125 * 1000 * 1000); + if (ret < 0) { + error("clk_set_rate(clk_ptp_ref) failed: %d", ret); + goto err_disable_clk_ptp_ref; + } + + ret = clk_enable(&eqos->clk_tx); + if (ret < 0) { + error("clk_enable(clk_tx) failed: %d", ret); + goto err_disable_clk_ptp_ref; + } + + debug("%s: OK\n", __func__); + return 0; + +err_disable_clk_ptp_ref: + clk_disable(&eqos->clk_ptp_ref); +err_disable_clk_rx: + clk_disable(&eqos->clk_rx); +err_disable_clk_master_bus: + clk_disable(&eqos->clk_master_bus); +err_disable_clk_slave_bus: + clk_disable(&eqos->clk_slave_bus); +err: + debug("%s: FAILED: %d\n", __func__, ret); + return ret; +} + +void eqos_stop_clks_tegra186(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + + debug("%s(dev=%p):\n", __func__, dev); + + clk_disable(&eqos->clk_tx); + clk_disable(&eqos->clk_ptp_ref); + clk_disable(&eqos->clk_rx); + clk_disable(&eqos->clk_master_bus); + clk_disable(&eqos->clk_slave_bus); + + debug("%s: OK\n", __func__); +} + +static int eqos_start_resets_tegra186(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + int ret; + + debug("%s(dev=%p):\n", __func__, dev); + + ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1); + if (ret < 0) { + error("dm_gpio_set_value(phy_reset, assert) failed: %d", ret); + return ret; + } + + udelay(2); + + ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0); + if (ret < 0) { + error("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret); + return ret; + } + + ret = reset_assert(&eqos->reset_ctl); + if (ret < 0) { + error("reset_assert() failed: %d", ret); + return ret; + } + + udelay(2); + + ret = reset_deassert(&eqos->reset_ctl); + if (ret < 0) { + error("reset_deassert() failed: %d", ret); + return ret; + } + + debug("%s: OK\n", __func__); + return 0; +} + +static int eqos_stop_resets_tegra186(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + + reset_assert(&eqos->reset_ctl); + dm_gpio_set_value(&eqos->phy_reset_gpio, 1); + + return 0; +} + +static int eqos_calibrate_pads_tegra186(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + int ret; + + debug("%s(dev=%p):\n", __func__, dev); + + setbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl, + EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD); + + udelay(1); + + setbits_le32(&eqos->tegra186_regs->auto_cal_config, + EQOS_AUTO_CAL_CONFIG_START | EQOS_AUTO_CAL_CONFIG_ENABLE); + + ret = wait_for_bit(__func__, &eqos->tegra186_regs->auto_cal_status, + EQOS_AUTO_CAL_STATUS_ACTIVE, true, 10, false); + if (ret) { + error("calibrate didn't start"); + goto failed; + } + + ret = wait_for_bit(__func__, &eqos->tegra186_regs->auto_cal_status, + EQOS_AUTO_CAL_STATUS_ACTIVE, false, 10, false); + if (ret) { + error("calibrate didn't finish"); + goto failed; + } + + ret = 0; + +failed: + clrbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl, + EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD); + + debug("%s: returns %d\n", __func__, ret); + + return ret; +} + +static int eqos_disable_calibration_tegra186(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + + debug("%s(dev=%p):\n", __func__, dev); + + clrbits_le32(&eqos->tegra186_regs->auto_cal_config, + EQOS_AUTO_CAL_CONFIG_ENABLE); + + return 0; +} + +static ulong eqos_get_tick_clk_rate_tegra186(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + + return clk_get_rate(&eqos->clk_slave_bus); +} + +static int eqos_set_full_duplex(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + + debug("%s(dev=%p):\n", __func__, dev); + + setbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM); + + return 0; +} + +static int eqos_set_half_duplex(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + + debug("%s(dev=%p):\n", __func__, dev); + + clrbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM); + + /* WAR: Flush TX queue when switching to half-duplex */ + setbits_le32(&eqos->mtl_regs->txq0_operation_mode, + EQOS_MTL_TXQ0_OPERATION_MODE_FTQ); + + return 0; +} + +static int eqos_set_gmii_speed(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + + debug("%s(dev=%p):\n", __func__, dev); + + clrbits_le32(&eqos->mac_regs->configuration, + EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES); + + return 0; +} + +static int eqos_set_mii_speed_100(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + + debug("%s(dev=%p):\n", __func__, dev); + + setbits_le32(&eqos->mac_regs->configuration, + EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES); + + return 0; +} + +static int eqos_set_mii_speed_10(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + + debug("%s(dev=%p):\n", __func__, dev); + + clrsetbits_le32(&eqos->mac_regs->configuration, + EQOS_MAC_CONFIGURATION_FES, EQOS_MAC_CONFIGURATION_PS); + + return 0; +} + +static int eqos_set_tx_clk_speed_tegra186(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + ulong rate; + int ret; + + debug("%s(dev=%p):\n", __func__, dev); + + switch (eqos->phy->speed) { + case SPEED_1000: + rate = 125 * 1000 * 1000; + break; + case SPEED_100: + rate = 25 * 1000 * 1000; + break; + case SPEED_10: + rate = 2.5 * 1000 * 1000; + break; + default: + error("invalid speed %d", eqos->phy->speed); + return -EINVAL; + } + + ret = clk_set_rate(&eqos->clk_tx, rate); + if (ret < 0) { + error("clk_set_rate(tx_clk, %lu) failed: %d", rate, ret); + return ret; + } + + return 0; +} + +static int eqos_adjust_link(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + int ret; + bool en_calibration; + + debug("%s(dev=%p):\n", __func__, dev); + + if (eqos->phy->duplex) + ret = eqos_set_full_duplex(dev); + else + ret = eqos_set_half_duplex(dev); + if (ret < 0) { + error("eqos_set_*_duplex() failed: %d", ret); + return ret; + } + + switch (eqos->phy->speed) { + case SPEED_1000: + en_calibration = true; + ret = eqos_set_gmii_speed(dev); + break; + case SPEED_100: + en_calibration = true; + ret = eqos_set_mii_speed_100(dev); + break; + case SPEED_10: + en_calibration = false; + ret = eqos_set_mii_speed_10(dev); + break; + default: + error("invalid speed %d", eqos->phy->speed); + return -EINVAL; + } + if (ret < 0) { + error("eqos_set_*mii_speed*() failed: %d", ret); + return ret; + } + + if (en_calibration) { + ret = eqos_calibrate_pads_tegra186(dev); + if (ret < 0) { + error("eqos_calibrate_pads_tegra186() failed: %d", ret); + return ret; + } + } else { + ret = eqos_disable_calibration_tegra186(dev); + if (ret < 0) { + error("eqos_disable_calibration_tegra186() failed: %d", + ret); + return ret; + } + } + + ret = eqos_set_tx_clk_speed_tegra186(dev); + if (ret < 0) { + error("eqos_set_tx_clk_speed_tegra186() failed: %d", ret); + return ret; + } + + return 0; +} + +static int eqos_write_hwaddr(struct udevice *dev) +{ + struct eth_pdata *plat = dev_get_platdata(dev); + struct eqos_priv *eqos = dev_get_priv(dev); + uint32_t val; + + /* + * This function may be called before start() or after stop(). At that + * time, on at least some configurations of the EQoS HW, all clocks to + * the EQoS HW block will be stopped, and a reset signal applied. If + * any register access is attempted in this state, bus timeouts or CPU + * hangs may occur. This check prevents that. + * + * A simple solution to this problem would be to not implement + * write_hwaddr(), since start() always writes the MAC address into HW + * anyway. However, it is desirable to implement write_hwaddr() to + * support the case of SW that runs subsequent to U-Boot which expects + * the MAC address to already be programmed into the EQoS registers, + * which must happen irrespective of whether the U-Boot user (or + * scripts) actually made use of the EQoS device, and hence + * irrespective of whether start() was ever called. + * + * Note that this requirement by subsequent SW is not valid for + * Tegra186, and is likely not valid for any non-PCI instantiation of + * the EQoS HW block. This function is implemented solely as + * future-proofing with the expectation the driver will eventually be + * ported to some system where the expectation above is true. + */ + if (!eqos->config->reg_access_always_ok && !eqos->reg_access_ok) + return 0; + + /* Update the MAC address */ + val = (plat->enetaddr[5] << 8) | + (plat->enetaddr[4]); + writel(val, &eqos->mac_regs->address0_high); + val = (plat->enetaddr[3] << 24) | + (plat->enetaddr[2] << 16) | + (plat->enetaddr[1] << 8) | + (plat->enetaddr[0]); + writel(val, &eqos->mac_regs->address0_low); + + return 0; +} + +static int eqos_start(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + int ret, i; + ulong rate; + u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl; + ulong last_rx_desc; + + debug("%s(dev=%p):\n", __func__, dev); + + eqos->tx_desc_idx = 0; + eqos->rx_desc_idx = 0; + + ret = eqos_start_clks_tegra186(dev); + if (ret < 0) { + error("eqos_start_clks_tegra186() failed: %d", ret); + goto err; + } + + ret = eqos_start_resets_tegra186(dev); + if (ret < 0) { + error("eqos_start_resets_tegra186() failed: %d", ret); + goto err_stop_clks; + } + + udelay(10); + + eqos->reg_access_ok = true; + + ret = wait_for_bit(__func__, &eqos->dma_regs->mode, + EQOS_DMA_MODE_SWR, false, 10, false); + if (ret) { + error("EQOS_DMA_MODE_SWR stuck"); + goto err_stop_resets; + } + + ret = eqos_calibrate_pads_tegra186(dev); + if (ret < 0) { + error("eqos_calibrate_pads_tegra186() failed: %d", ret); + goto err_stop_resets; + } + + rate = eqos_get_tick_clk_rate_tegra186(dev); + val = (rate / 1000000) - 1; + writel(val, &eqos->mac_regs->us_tic_counter); + + eqos->phy = phy_connect(eqos->mii, 0, dev, 0); + if (!eqos->phy) { + error("phy_connect() failed"); + goto err_stop_resets; + } + ret = phy_config(eqos->phy); + if (ret < 0) { + error("phy_config() failed: %d", ret); + goto err_shutdown_phy; + } + ret = phy_startup(eqos->phy); + if (ret < 0) { + error("phy_startup() failed: %d", ret); + goto err_shutdown_phy; + } + + if (!eqos->phy->link) { + error("No link"); + goto err_shutdown_phy; + } + + ret = eqos_adjust_link(dev); + if (ret < 0) { + error("eqos_adjust_link() failed: %d", ret); + goto err_shutdown_phy; + } + + /* Configure MTL */ + + /* Enable Store and Forward mode for TX */ + /* Program Tx operating mode */ + setbits_le32(&eqos->mtl_regs->txq0_operation_mode, + EQOS_MTL_TXQ0_OPERATION_MODE_TSF | + (EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED << + EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT)); + + /* Transmit Queue weight */ + writel(0x10, &eqos->mtl_regs->txq0_quantum_weight); + + /* Enable Store and Forward mode for RX, since no jumbo frame */ + setbits_le32(&eqos->mtl_regs->rxq0_operation_mode, + EQOS_MTL_RXQ0_OPERATION_MODE_RSF); + + /* Transmit/Receive queue fifo size; use all RAM for 1 queue */ + val = readl(&eqos->mac_regs->hw_feature1); + tx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) & + EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK; + rx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) & + EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK; + + /* + * r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting. + * r/tqs is encoded as (n / 256) - 1. + */ + tqs = (128 << tx_fifo_sz) / 256 - 1; + rqs = (128 << rx_fifo_sz) / 256 - 1; + + clrsetbits_le32(&eqos->mtl_regs->txq0_operation_mode, + EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK << + EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT, + tqs << EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT); + clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode, + EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK << + EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT, + rqs << EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT); + + /* Flow control used only if each channel gets 4KB or more FIFO */ + if (rqs >= ((4096 / 256) - 1)) { + u32 rfd, rfa; + + setbits_le32(&eqos->mtl_regs->rxq0_operation_mode, + EQOS_MTL_RXQ0_OPERATION_MODE_EHFC); + + /* + * Set Threshold for Activating Flow Contol space for min 2 + * frames ie, (1500 * 1) = 1500 bytes. + * + * Set Threshold for Deactivating Flow Contol for space of + * min 1 frame (frame size 1500bytes) in receive fifo + */ + if (rqs == ((4096 / 256) - 1)) { + /* + * This violates the above formula because of FIFO size + * limit therefore overflow may occur inspite of this. + */ + rfd = 0x3; /* Full-3K */ + rfa = 0x1; /* Full-1.5K */ + } else if (rqs == ((8192 / 256) - 1)) { + rfd = 0x6; /* Full-4K */ + rfa = 0xa; /* Full-6K */ + } else if (rqs == ((16384 / 256) - 1)) { + rfd = 0x6; /* Full-4K */ + rfa = 0x12; /* Full-10K */ + } else { + rfd = 0x6; /* Full-4K */ + rfa = 0x1E; /* Full-16K */ + } + + clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode, + (EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK << + EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) | + (EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK << + EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT), + (rfd << + EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) | + (rfa << + EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT)); + } + + /* Configure MAC */ + + clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0, + EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK << + EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT, + EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB << + EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT); + + /* Set TX flow control parameters */ + /* Set Pause Time */ + setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl, + 0xffff << EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT); + /* Assign priority for TX flow control */ + clrbits_le32(&eqos->mac_regs->txq_prty_map0, + EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK << + EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT); + /* Assign priority for RX flow control */ + clrbits_le32(&eqos->mac_regs->rxq_ctrl2, + EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK << + EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT); + /* Enable flow control */ + setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl, + EQOS_MAC_Q0_TX_FLOW_CTRL_TFE); + setbits_le32(&eqos->mac_regs->rx_flow_ctrl, + EQOS_MAC_RX_FLOW_CTRL_RFE); + + clrsetbits_le32(&eqos->mac_regs->configuration, + EQOS_MAC_CONFIGURATION_GPSLCE | + EQOS_MAC_CONFIGURATION_WD | + EQOS_MAC_CONFIGURATION_JD | + EQOS_MAC_CONFIGURATION_JE, + EQOS_MAC_CONFIGURATION_CST | + EQOS_MAC_CONFIGURATION_ACS); + + eqos_write_hwaddr(dev); + + /* Configure DMA */ + + /* Enable OSP mode */ + setbits_le32(&eqos->dma_regs->ch0_tx_control, + EQOS_DMA_CH0_TX_CONTROL_OSP); + + /* RX buffer size. Must be a multiple of bus width */ + clrsetbits_le32(&eqos->dma_regs->ch0_rx_control, + EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK << + EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT, + EQOS_MAX_PACKET_SIZE << + EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT); + + setbits_le32(&eqos->dma_regs->ch0_control, + EQOS_DMA_CH0_CONTROL_PBLX8); + + /* + * Burst length must be < 1/2 FIFO size. + * FIFO size in tqs is encoded as (n / 256) - 1. + * Each burst is n * 8 (PBLX8) * 16 (AXI width) == 128 bytes. + * Half of n * 256 is n * 128, so pbl == tqs, modulo the -1. + */ + pbl = tqs + 1; + if (pbl > 32) + pbl = 32; + clrsetbits_le32(&eqos->dma_regs->ch0_tx_control, + EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK << + EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT, + pbl << EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT); + + clrsetbits_le32(&eqos->dma_regs->ch0_rx_control, + EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK << + EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT, + 8 << EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT); + + /* DMA performance configuration */ + val = (2 << EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) | + EQOS_DMA_SYSBUS_MODE_EAME | EQOS_DMA_SYSBUS_MODE_BLEN16 | + EQOS_DMA_SYSBUS_MODE_BLEN8 | EQOS_DMA_SYSBUS_MODE_BLEN4; + writel(val, &eqos->dma_regs->sysbus_mode); + + /* Set up descriptors */ + + memset(eqos->descs, 0, EQOS_DESCRIPTORS_SIZE); + for (i = 0; i < EQOS_DESCRIPTORS_RX; i++) { + struct eqos_desc *rx_desc = &(eqos->rx_descs[i]); + rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf + + (i * EQOS_MAX_PACKET_SIZE)); + rx_desc->des3 |= EQOS_DESC3_OWN | EQOS_DESC3_BUF1V; + } + flush_cache((unsigned long)eqos->descs, EQOS_DESCRIPTORS_SIZE); + + writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress); + writel((ulong)eqos->tx_descs, &eqos->dma_regs->ch0_txdesc_list_address); + writel(EQOS_DESCRIPTORS_TX - 1, + &eqos->dma_regs->ch0_txdesc_ring_length); + + writel(0, &eqos->dma_regs->ch0_rxdesc_list_haddress); + writel((ulong)eqos->rx_descs, &eqos->dma_regs->ch0_rxdesc_list_address); + writel(EQOS_DESCRIPTORS_RX - 1, + &eqos->dma_regs->ch0_rxdesc_ring_length); + + /* Enable everything */ + + setbits_le32(&eqos->mac_regs->configuration, + EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE); + + setbits_le32(&eqos->dma_regs->ch0_tx_control, + EQOS_DMA_CH0_TX_CONTROL_ST); + setbits_le32(&eqos->dma_regs->ch0_rx_control, + EQOS_DMA_CH0_RX_CONTROL_SR); + + /* TX tail pointer not written until we need to TX a packet */ + /* + * Point RX tail pointer at last descriptor. Ideally, we'd point at the + * first descriptor, implying all descriptors were available. However, + * that's not distinguishable from none of the descriptors being + * available. + */ + last_rx_desc = (ulong)&(eqos->rx_descs[(EQOS_DESCRIPTORS_RX - 1)]); + writel(last_rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer); + + eqos->started = true; + + debug("%s: OK\n", __func__); + return 0; + +err_shutdown_phy: + phy_shutdown(eqos->phy); + eqos->phy = NULL; +err_stop_resets: + eqos_stop_resets_tegra186(dev); +err_stop_clks: + eqos_stop_clks_tegra186(dev); +err: + error("FAILED: %d", ret); + return ret; +} + +void eqos_stop(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + int i; + + debug("%s(dev=%p):\n", __func__, dev); + + if (!eqos->started) + return; + eqos->started = false; + eqos->reg_access_ok = false; + + /* Disable TX DMA */ + clrbits_le32(&eqos->dma_regs->ch0_tx_control, + EQOS_DMA_CH0_TX_CONTROL_ST); + + /* Wait for TX all packets to drain out of MTL */ + for (i = 0; i < 1000000; i++) { + u32 val = readl(&eqos->mtl_regs->txq0_debug); + u32 trcsts = (val >> EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT) & + EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK; + u32 txqsts = val & EQOS_MTL_TXQ0_DEBUG_TXQSTS; + if ((trcsts != 1) && (!txqsts)) + break; + } + + /* Turn off MAC TX and RX */ + clrbits_le32(&eqos->mac_regs->configuration, + EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE); + + /* Wait for all RX packets to drain out of MTL */ + for (i = 0; i < 1000000; i++) { + u32 val = readl(&eqos->mtl_regs->rxq0_debug); + u32 prxq = (val >> EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT) & + EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK; + u32 rxqsts = (val >> EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) & + EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK; + if ((!prxq) && (!rxqsts)) + break; + } + + /* Turn off RX DMA */ + clrbits_le32(&eqos->dma_regs->ch0_rx_control, + EQOS_DMA_CH0_RX_CONTROL_SR); + + if (eqos->phy) { + phy_shutdown(eqos->phy); + eqos->phy = NULL; + } + eqos_stop_resets_tegra186(dev); + eqos_stop_clks_tegra186(dev); + + debug("%s: OK\n", __func__); +} + +int eqos_send(struct udevice *dev, void *packet, int length) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + struct eqos_desc *tx_desc; + int i; + + debug("%s(dev=%p, packet=%p, length=%d):\n", __func__, dev, packet, + length); + + memcpy(eqos->tx_dma_buf, packet, length); + eqos_flush_buffer(eqos->tx_dma_buf, length); + + tx_desc = &(eqos->tx_descs[eqos->tx_desc_idx]); + eqos->tx_desc_idx++; + eqos->tx_desc_idx %= EQOS_DESCRIPTORS_TX; + + tx_desc->des0 = (ulong)eqos->tx_dma_buf; + tx_desc->des1 = 0; + tx_desc->des2 = length; + /* + * Make sure that if HW sees the _OWN write below, it will see all the + * writes to the rest of the descriptor too. + */ + mb(); + tx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_FD | EQOS_DESC3_LD | length; + eqos_flush_desc(tx_desc); + + writel((ulong)(tx_desc + 1), &eqos->dma_regs->ch0_txdesc_tail_pointer); + + for (i = 0; i < 1000000; i++) { + eqos_inval_desc(tx_desc); + if (!(readl(&tx_desc->des3) & EQOS_DESC3_OWN)) + return 0; + udelay(1); + } + + debug("%s: TX timeout\n", __func__); + + return -ETIMEDOUT; +} + +int eqos_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + struct eqos_desc *rx_desc; + int length; + + debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags); + + rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]); + if (rx_desc->des3 & EQOS_DESC3_OWN) { + debug("%s: RX packet not available\n", __func__); + return -EAGAIN; + } + + *packetp = eqos->rx_dma_buf + + (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE); + length = rx_desc->des3 & 0x7fff; + debug("%s: *packetp=%p, length=%d\n", __func__, *packetp, length); + + eqos_inval_buffer(*packetp, length); + + return length; +} + +int eqos_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + uchar *packet_expected; + struct eqos_desc *rx_desc; + + debug("%s(packet=%p, length=%d)\n", __func__, packet, length); + + packet_expected = eqos->rx_dma_buf + + (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE); + if (packet != packet_expected) { + debug("%s: Unexpected packet (expected %p)\n", __func__, + packet_expected); + return -EINVAL; + } + + rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]); + rx_desc->des0 = (u32)(ulong)packet; + rx_desc->des1 = 0; + rx_desc->des2 = 0; + /* + * Make sure that if HW sees the _OWN write below, it will see all the + * writes to the rest of the descriptor too. + */ + mb(); + rx_desc->des3 |= EQOS_DESC3_OWN | EQOS_DESC3_BUF1V; + eqos_flush_desc(rx_desc); + + writel((ulong)rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer); + + eqos->rx_desc_idx++; + eqos->rx_desc_idx %= EQOS_DESCRIPTORS_RX; + + return 0; +} + +static int eqos_probe_resources_core(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + int ret; + + debug("%s(dev=%p):\n", __func__, dev); + + eqos->descs = eqos_alloc_descs(EQOS_DESCRIPTORS_TX + + EQOS_DESCRIPTORS_RX); + if (!eqos->descs) { + debug("%s: eqos_alloc_descs() failed\n", __func__); + ret = -ENOMEM; + goto err; + } + eqos->tx_descs = (struct eqos_desc *)eqos->descs; + eqos->rx_descs = (eqos->tx_descs + EQOS_DESCRIPTORS_TX); + debug("%s: tx_descs=%p, rx_descs=%p\n", __func__, eqos->tx_descs, + eqos->rx_descs); + + eqos->tx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_MAX_PACKET_SIZE); + if (!eqos->tx_dma_buf) { + debug("%s: memalign(tx_dma_buf) failed\n", __func__); + ret = -ENOMEM; + goto err_free_descs; + } + debug("%s: rx_dma_buf=%p\n", __func__, eqos->rx_dma_buf); + + eqos->rx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_RX_BUFFER_SIZE); + if (!eqos->rx_dma_buf) { + debug("%s: memalign(rx_dma_buf) failed\n", __func__); + ret = -ENOMEM; + goto err_free_tx_dma_buf; + } + debug("%s: tx_dma_buf=%p\n", __func__, eqos->tx_dma_buf); + + eqos->rx_pkt = malloc(EQOS_MAX_PACKET_SIZE); + if (!eqos->rx_pkt) { + debug("%s: malloc(rx_pkt) failed\n", __func__); + ret = -ENOMEM; + goto err_free_rx_dma_buf; + } + debug("%s: rx_pkt=%p\n", __func__, eqos->rx_pkt); + + debug("%s: OK\n", __func__); + return 0; + +err_free_rx_dma_buf: + free(eqos->rx_dma_buf); +err_free_tx_dma_buf: + free(eqos->tx_dma_buf); +err_free_descs: + eqos_free_descs(eqos->descs); +err: + + debug("%s: returns %d\n", __func__, ret); + return ret; +} + +static int eqos_remove_resources_core(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + + debug("%s(dev=%p):\n", __func__, dev); + + free(eqos->rx_pkt); + free(eqos->rx_dma_buf); + free(eqos->tx_dma_buf); + eqos_free_descs(eqos->descs); + + debug("%s: OK\n", __func__); + return 0; +} + +static int eqos_probe_resources_tegra186(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + int ret; + + debug("%s(dev=%p):\n", __func__, dev); + + ret = reset_get_by_name(dev, "eqos", &eqos->reset_ctl); + if (ret) { + error("reset_get_by_name(rst) failed: %d", ret); + return ret; + } + + ret = gpio_request_by_name(dev, "phy-reset-gpios", 0, + &eqos->phy_reset_gpio, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + if (ret) { + error("gpio_request_by_name(phy reset) failed: %d", ret); + goto err_free_reset_eqos; + } + + ret = clk_get_by_name(dev, "slave_bus", &eqos->clk_slave_bus); + if (ret) { + error("clk_get_by_name(slave_bus) failed: %d", ret); + goto err_free_gpio_phy_reset; + } + + ret = clk_get_by_name(dev, "master_bus", &eqos->clk_master_bus); + if (ret) { + error("clk_get_by_name(master_bus) failed: %d", ret); + goto err_free_clk_slave_bus; + } + + ret = clk_get_by_name(dev, "rx", &eqos->clk_rx); + if (ret) { + error("clk_get_by_name(rx) failed: %d", ret); + goto err_free_clk_master_bus; + } + + ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref); + if (ret) { + error("clk_get_by_name(ptp_ref) failed: %d", ret); + goto err_free_clk_rx; + return ret; + } + + ret = clk_get_by_name(dev, "tx", &eqos->clk_tx); + if (ret) { + error("clk_get_by_name(tx) failed: %d", ret); + goto err_free_clk_ptp_ref; + } + + debug("%s: OK\n", __func__); + return 0; + +err_free_clk_ptp_ref: + clk_free(&eqos->clk_ptp_ref); +err_free_clk_rx: + clk_free(&eqos->clk_rx); +err_free_clk_master_bus: + clk_free(&eqos->clk_master_bus); +err_free_clk_slave_bus: + clk_free(&eqos->clk_slave_bus); +err_free_gpio_phy_reset: + dm_gpio_free(dev, &eqos->phy_reset_gpio); +err_free_reset_eqos: + reset_free(&eqos->reset_ctl); + + debug("%s: returns %d\n", __func__, ret); + return ret; +} + +static int eqos_remove_resources_tegra186(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + + debug("%s(dev=%p):\n", __func__, dev); + + clk_free(&eqos->clk_tx); + clk_free(&eqos->clk_ptp_ref); + clk_free(&eqos->clk_rx); + clk_free(&eqos->clk_slave_bus); + clk_free(&eqos->clk_master_bus); + dm_gpio_free(dev, &eqos->phy_reset_gpio); + reset_free(&eqos->reset_ctl); + + debug("%s: OK\n", __func__); + return 0; +} + +static int eqos_probe(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + int ret; + + debug("%s(dev=%p):\n", __func__, dev); + + eqos->dev = dev; + eqos->config = (void *)dev_get_driver_data(dev); + + eqos->regs = dev_get_addr(dev); + if (eqos->regs == FDT_ADDR_T_NONE) { + error("dev_get_addr() failed"); + return -ENODEV; + } + eqos->mac_regs = (void *)(eqos->regs + EQOS_MAC_REGS_BASE); + eqos->mtl_regs = (void *)(eqos->regs + EQOS_MTL_REGS_BASE); + eqos->dma_regs = (void *)(eqos->regs + EQOS_DMA_REGS_BASE); + eqos->tegra186_regs = (void *)(eqos->regs + EQOS_TEGRA186_REGS_BASE); + + ret = eqos_probe_resources_core(dev); + if (ret < 0) { + error("eqos_probe_resources_core() failed: %d", ret); + return ret; + } + + ret = eqos_probe_resources_tegra186(dev); + if (ret < 0) { + error("eqos_probe_resources_tegra186() failed: %d", ret); + goto err_remove_resources_core; + } + + eqos->mii = mdio_alloc(); + if (!eqos->mii) { + error("mdio_alloc() failed"); + goto err_remove_resources_tegra; + } + eqos->mii->read = eqos_mdio_read; + eqos->mii->write = eqos_mdio_write; + eqos->mii->priv = eqos; + strcpy(eqos->mii->name, dev->name); + + ret = mdio_register(eqos->mii); + if (ret < 0) { + error("mdio_register() failed: %d", ret); + goto err_free_mdio; + } + + debug("%s: OK\n", __func__); + return 0; + +err_free_mdio: + mdio_free(eqos->mii); +err_remove_resources_tegra: + eqos_remove_resources_tegra186(dev); +err_remove_resources_core: + eqos_remove_resources_core(dev); + + debug("%s: returns %d\n", __func__, ret); + return ret; +} + +static int eqos_remove(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + + debug("%s(dev=%p):\n", __func__, dev); + + mdio_unregister(eqos->mii); + mdio_free(eqos->mii); + eqos_remove_resources_tegra186(dev); + eqos_probe_resources_core(dev); + + debug("%s: OK\n", __func__); + return 0; +} + +static const struct eth_ops eqos_ops = { + .start = eqos_start, + .stop = eqos_stop, + .send = eqos_send, + .recv = eqos_recv, + .free_pkt = eqos_free_pkt, + .write_hwaddr = eqos_write_hwaddr, +}; + +static const struct eqos_config eqos_tegra186_config = { + .reg_access_always_ok = false, +}; + +static const struct udevice_id eqos_ids[] = { + { + .compatible = "nvidia,tegra186-eqos", + .data = (ulong)&eqos_tegra186_config + }, + { } +}; + +U_BOOT_DRIVER(eth_eqos) = { + .name = "eth_eqos", + .id = UCLASS_ETH, + .of_match = eqos_ids, + .probe = eqos_probe, + .remove = eqos_remove, + .ops = &eqos_ops, + .priv_auto_alloc_size = sizeof(struct eqos_priv), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 196989b3864f..02e6d18bdd23 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -1522,11 +1522,10 @@ e1000_initialize_hardware_bits(struct e1000_hw *hw) reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); - /* IGB is cool */ - if (hw->mac_type == e1000_igb) - return; switch (hw->mac_type) { + case e1000_igb: /* IGB is cool */ + return; case e1000_82571: case e1000_82572: /* Clear PHY TX compatible mode bits */ diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index 1cc0b40935c5..5e933581b8d2 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -241,6 +241,9 @@ enum RTL8169_register_content { /*_TBICSRBit*/ TBILinkOK = 0x02000000, + + /* FuncEvent/Misc */ + RxDv_Gated_En = 0x80000, }; static struct { @@ -262,6 +265,7 @@ static struct { {"RTL-8168/8111g", 0x4c, 0xff7e1880,}, {"RTL-8101e", 0x34, 0xff7e1880,}, {"RTL-8100e", 0x32, 0xff7e1880,}, + {"RTL-8168h/8111h", 0x54, 0xff7e1880,}, }; enum _DescStatusBit { @@ -339,9 +343,6 @@ struct rtl8169_private { static struct rtl8169_private *tpc; -static const u16 rtl8169_intr_mask = - SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr | - TxOK | RxErr | RxOK; static const unsigned int rtl8169_rx_config = (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); @@ -948,6 +949,23 @@ static void rtl_halt(struct eth_device *dev) } #endif +#ifdef CONFIG_DM_ETH +static int rtl8169_write_hwaddr(struct udevice *dev) +{ + struct eth_pdata *plat = dev_get_platdata(dev); + unsigned int i; + + RTL_W8(Cfg9346, Cfg9346_Unlock); + + for (i = 0; i < MAC_ADDR_LEN; i++) + RTL_W8(MAC0 + i, plat->enetaddr[i]); + + RTL_W8(Cfg9346, Cfg9346_Lock); + + return 0; +} +#endif + /************************************************************************** INIT - Look for an adapter, this routine's visible to the outside ***************************************************************************/ @@ -1194,6 +1212,19 @@ static int rtl8169_eth_probe(struct udevice *dev) return ret; } + /* + * WAR for DHCP failure after rebooting from kernel. + * Clear RxDv_Gated_En bit which was set by kernel driver. + * Without this, U-Boot can't get an IP via DHCP. + * Register (FuncEvent, aka MISC) and RXDV_GATED_EN bit are from + * the r8169.c kernel driver. + */ + + u32 val = RTL_R32(FuncEvent); + debug("%s: FuncEvent/Misc (0xF0) = 0x%08X\n", __func__, val); + val &= ~RxDv_Gated_En; + RTL_W32(FuncEvent, val); + return 0; } @@ -1202,6 +1233,7 @@ static const struct eth_ops rtl8169_eth_ops = { .send = rtl8169_eth_send, .recv = rtl8169_eth_recv, .stop = rtl8169_eth_stop, + .write_hwaddr = rtl8169_write_hwaddr, }; static const struct udevice_id rtl8169_eth_ids[] = { diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 26aa2b0930a0..669e37bb5dc5 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -31,6 +31,7 @@ config PCI_SANDBOX config PCI_TEGRA bool "Tegra PCI support" depends on TEGRA + depends on (TEGRA186 && POWER_DOMAIN) || (!TEGRA186) help Enable support for the PCIe controller found on some generations of Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c index 352cdef56ab4..ea8adb98db33 100644 --- a/drivers/pci/pci_tegra.c +++ b/drivers/pci/pci_tegra.c @@ -13,22 +13,35 @@ #define pr_fmt(fmt) "tegra-pcie: " fmt #include +#include #include #include #include #include #include +#include +#include #include #include +#include + +#ifndef CONFIG_TEGRA186 #include #include #include - -#include - #include +#endif + +/* + * FIXME: TODO: This driver contains a number of ifdef CONFIG_TEGRA186 that + * should not be present. These are needed because newer Tegra SoCs support + * only the standard clock/reset APIs, whereas older Tegra SoCs support only + * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be + * fixed to implement the standard APIs, and all drivers converted to solely + * use the new standard APIs, with no ifdefs. + */ DECLARE_GLOBAL_DATA_PTR; @@ -103,6 +116,9 @@ DECLARE_GLOBAL_DATA_PTR; #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20) #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20) #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20) +#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_401 (0x0 << 20) +#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_211 (0x1 << 20) +#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_111 (0x2 << 20) #define AFI_FUSE 0x104 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) @@ -110,6 +126,7 @@ DECLARE_GLOBAL_DATA_PTR; #define AFI_PEX0_CTRL 0x110 #define AFI_PEX1_CTRL 0x118 #define AFI_PEX2_CTRL 0x128 +#define AFI_PEX2_CTRL_T186 0x19c #define AFI_PEX_CTRL_RST (1 << 0) #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) #define AFI_PEX_CTRL_REFCLK_EN (1 << 3) @@ -173,6 +190,7 @@ enum tegra_pci_id { TEGRA30_PCIE, TEGRA124_PCIE, TEGRA210_PCIE, + TEGRA186_PCIE, }; struct tegra_pcie_port { @@ -189,6 +207,7 @@ struct tegra_pcie_soc { unsigned int num_ports; unsigned long pads_pll_ctl; unsigned long tx_ref_sel; + unsigned long afi_pex2_ctrl; u32 pads_refclk_cfg0; u32 pads_refclk_cfg1; bool has_pex_clkreq_en; @@ -209,7 +228,17 @@ struct tegra_pcie { unsigned long xbar; const struct tegra_pcie_soc *soc; + +#ifdef CONFIG_TEGRA186 + struct clk clk_afi; + struct clk clk_pex; + struct reset_ctl reset_afi; + struct reset_ctl reset_pex; + struct reset_ctl reset_pcie_x; + struct power_domain pwrdom; +#else struct tegra_xusb_phy *phy; +#endif }; static void afi_writel(struct tegra_pcie *pcie, unsigned long value, @@ -229,10 +258,12 @@ static void pads_writel(struct tegra_pcie *pcie, unsigned long value, writel(value, pcie->pads.start + offset); } +#ifndef CONFIG_TEGRA186 static unsigned long pads_readl(struct tegra_pcie *pcie, unsigned long offset) { return readl(pcie->pads.start + offset); } +#endif static unsigned long rp_readl(struct tegra_pcie_port *port, unsigned long offset) @@ -400,6 +431,24 @@ static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes, return 0; } break; + case TEGRA186_PCIE: + switch (lanes) { + case 0x0010004: + debug("x4 x1 configuration\n"); + *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_401; + return 0; + + case 0x0010102: + debug("x2 x1 x1 configuration\n"); + *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_211; + return 0; + + case 0x0010101: + debug("x1 x1 x1 configuration\n"); + *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_111; + return 0; + } + break; default: break; } @@ -471,6 +520,7 @@ static int tegra_pcie_parse_dt(const void *fdt, int node, enum tegra_pci_id id, return err; } +#ifndef CONFIG_TEGRA186 pcie->phy = tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE); if (pcie->phy) { err = tegra_xusb_phy_prepare(pcie->phy); @@ -479,6 +529,7 @@ static int tegra_pcie_parse_dt(const void *fdt, int node, enum tegra_pci_id id, return err; } } +#endif fdt_for_each_subnode(fdt, subnode, node) { unsigned int index = 0, num_lanes = 0; @@ -523,6 +574,44 @@ static int tegra_pcie_parse_dt(const void *fdt, int node, enum tegra_pci_id id, return 0; } +#ifdef CONFIG_TEGRA186 +static int tegra_pcie_power_on(struct tegra_pcie *pcie) +{ + int ret; + + ret = power_domain_on(&pcie->pwrdom); + if (ret) { + error("power_domain_on() failed: %d\n", ret); + return ret; + } + + ret = clk_enable(&pcie->clk_afi); + if (ret) { + error("clk_enable(afi) failed: %d\n", ret); + return ret; + } + + ret = clk_enable(&pcie->clk_pex); + if (ret) { + error("clk_enable(pex) failed: %d\n", ret); + return ret; + } + + ret = reset_deassert(&pcie->reset_afi); + if (ret) { + error("reset_deassert(afi) failed: %d\n", ret); + return ret; + } + + ret = reset_deassert(&pcie->reset_pex); + if (ret) { + error("reset_deassert(pex) failed: %d\n", ret); + return ret; + } + + return 0; +} +#else static int tegra_pcie_power_on(struct tegra_pcie *pcie) { const struct tegra_pcie_soc *soc = pcie->soc; @@ -639,6 +728,7 @@ static int tegra_pcie_phy_enable(struct tegra_pcie *pcie) return 0; } +#endif static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) { @@ -647,7 +737,11 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) u32 value; int err; +#ifdef CONFIG_TEGRA186 + { +#else if (pcie->phy) { +#endif value = afi_readl(pcie, AFI_PLLE_CONTROL); value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; @@ -675,6 +769,7 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) afi_writel(pcie, value, AFI_FUSE); +#ifndef CONFIG_TEGRA186 if (pcie->phy) err = tegra_xusb_phy_enable(pcie->phy); else @@ -684,9 +779,18 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) error("failed to power on PHY: %d\n", err); return err; } +#endif /* take the PCIEXCLK logic out of reset */ +#ifdef CONFIG_TEGRA186 + err = reset_deassert(&pcie->reset_pcie_x); + if (err) { + error("reset_deassert(pcie_x) failed: %d\n", err); + return err; + } +#else reset_set_enable(PERIPH_ID_PCIEXCLK, 0); +#endif /* finally enable PCIe */ value = afi_readl(pcie, AFI_CONFIGURATION); @@ -787,7 +891,7 @@ static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port) break; case 2: - ret = AFI_PEX2_CTRL; + ret = port->pcie->soc->afi_pex2_ctrl; break; } @@ -945,6 +1049,7 @@ static const struct tegra_pcie_soc pci_tegra_soc[] = { .num_ports = 3, .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, + .afi_pex2_ctrl = AFI_PEX2_CTRL, .pads_refclk_cfg0 = 0xfa5cfa5c, .pads_refclk_cfg1 = 0xfa5cfa5c, .has_pex_clkreq_en = true, @@ -972,7 +1077,16 @@ static const struct tegra_pcie_soc pci_tegra_soc[] = { .has_cml_clk = true, .has_gen2 = true, .force_pca_enable = true, - } + }, + [TEGRA186_PCIE] = { + .num_ports = 3, + .afi_pex2_ctrl = AFI_PEX2_CTRL_T186, + .pads_refclk_cfg0 = 0x80b880b8, + .pads_refclk_cfg1 = 0x000480b8, + .has_pex_clkreq_en = true, + .has_pex_bias_ctrl = true, + .has_gen2 = true, + }, }; static int pci_tegra_ofdata_to_platdata(struct udevice *dev) @@ -996,6 +1110,44 @@ static int pci_tegra_probe(struct udevice *dev) struct tegra_pcie *pcie = dev_get_priv(dev); int err; +#ifdef CONFIG_TEGRA186 + err = clk_get_by_name(dev, "afi", &pcie->clk_afi); + if (err) { + debug("clk_get_by_name(afi) failed: %d\n", err); + return err; + } + + err = clk_get_by_name(dev, "pex", &pcie->clk_pex); + if (err) { + debug("clk_get_by_name(pex) failed: %d\n", err); + return err; + } + + err = reset_get_by_name(dev, "afi", &pcie->reset_afi); + if (err) { + debug("reset_get_by_name(afi) failed: %d\n", err); + return err; + } + + err = reset_get_by_name(dev, "pex", &pcie->reset_pex); + if (err) { + debug("reset_get_by_name(pex) failed: %d\n", err); + return err; + } + + err = reset_get_by_name(dev, "pcie_x", &pcie->reset_pcie_x); + if (err) { + debug("reset_get_by_name(pcie_x) failed: %d\n", err); + return err; + } + + err = power_domain_get(dev, &pcie->pwrdom); + if (err) { + debug("power_domain_get() failed: %d\n", err); + return err; + } +#endif + err = tegra_pcie_power_on(pcie); if (err < 0) { error("failed to power on"); @@ -1033,6 +1185,7 @@ static const struct udevice_id pci_tegra_ids[] = { { .compatible = "nvidia,tegra30-pcie", .data = TEGRA30_PCIE }, { .compatible = "nvidia,tegra124-pcie", .data = TEGRA124_PCIE }, { .compatible = "nvidia,tegra210-pcie", .data = TEGRA210_PCIE }, + { .compatible = "nvidia,tegra186-pcie", .data = TEGRA186_PCIE }, { } }; diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index 3c4416780591..b42270312650 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -1,5 +1,7 @@ menu "Power" +source "drivers/power/domain/Kconfig" + source "drivers/power/pmic/Kconfig" source "drivers/power/regulator/Kconfig" diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig new file mode 100644 index 000000000000..132e33250e8c --- /dev/null +++ b/drivers/power/domain/Kconfig @@ -0,0 +1,27 @@ +menu "Power Domain Support" + +config POWER_DOMAIN + bool "Enable power domain support using Driver Model" + depends on DM && OF_CONTROL + help + Enable support for the power domain driver class. Many SoCs allow + power to be applied to or removed from portions of the SoC (power + domains). This may be used to save power. This API provides the + means to control such power management hardware. + +config SANDBOX_POWER_DOMAIN + bool "Enable the sandbox power domain test driver" + depends on POWER_DOMAIN && SANDBOX + help + Enable support for a test power domain driver implementation, which + simply accepts requests to power on/off various HW modules without + actually doing anything beyond a little error checking. + +config TEGRA186_POWER_DOMAIN + bool "Enable Tegra186 BPMP-based power domain driver" + depends on TEGRA186_BPMP + help + Enable support for manipulating Tegra's on-SoC power domains via IPC + requests to the BPMP (Boot and Power Management Processor). + +endmenu diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile new file mode 100644 index 000000000000..2c3d92638fbe --- /dev/null +++ b/drivers/power/domain/Makefile @@ -0,0 +1,8 @@ +# Copyright (c) 2016, NVIDIA CORPORATION. +# +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_POWER_DOMAIN) += power-domain-uclass.o +obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o +obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o +obj-$(CONFIG_TEGRA186_POWER_DOMAIN) += tegra186-power-domain.o diff --git a/drivers/power/domain/power-domain-uclass.c b/drivers/power/domain/power-domain-uclass.c new file mode 100644 index 000000000000..1bb6262fa1b9 --- /dev/null +++ b/drivers/power/domain/power-domain-uclass.c @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static inline struct power_domain_ops *power_domain_dev_ops(struct udevice *dev) +{ + return (struct power_domain_ops *)dev->driver->ops; +} + +static int power_domain_of_xlate_default(struct power_domain *power_domain, + struct fdtdec_phandle_args *args) +{ + debug("%s(power_domain=%p)\n", __func__, power_domain); + + if (args->args_count != 1) { + debug("Invalid args_count: %d\n", args->args_count); + return -EINVAL; + } + + power_domain->id = args->args[0]; + + return 0; +} + +int power_domain_get(struct udevice *dev, struct power_domain *power_domain) +{ + struct fdtdec_phandle_args args; + int ret; + struct udevice *dev_power_domain; + struct power_domain_ops *ops; + + debug("%s(dev=%p, power_domain=%p)\n", __func__, dev, power_domain); + + ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset, + "power-domains", + "#power-domain-cells", 0, 0, + &args); + if (ret) { + debug("%s: fdtdec_parse_phandle_with_args failed: %d\n", + __func__, ret); + return ret; + } + + ret = uclass_get_device_by_of_offset(UCLASS_POWER_DOMAIN, args.node, + &dev_power_domain); + if (ret) { + debug("%s: uclass_get_device_by_of_offset failed: %d\n", + __func__, ret); + return ret; + } + ops = power_domain_dev_ops(dev_power_domain); + + power_domain->dev = dev_power_domain; + if (ops->of_xlate) + ret = ops->of_xlate(power_domain, &args); + else + ret = power_domain_of_xlate_default(power_domain, &args); + if (ret) { + debug("of_xlate() failed: %d\n", ret); + return ret; + } + + ret = ops->request(power_domain); + if (ret) { + debug("ops->request() failed: %d\n", ret); + return ret; + } + + return 0; +} + +int power_domain_free(struct power_domain *power_domain) +{ + struct power_domain_ops *ops = power_domain_dev_ops(power_domain->dev); + + debug("%s(power_domain=%p)\n", __func__, power_domain); + + return ops->free(power_domain); +} + +int power_domain_on(struct power_domain *power_domain) +{ + struct power_domain_ops *ops = power_domain_dev_ops(power_domain->dev); + + debug("%s(power_domain=%p)\n", __func__, power_domain); + + return ops->on(power_domain); +} + +int power_domain_off(struct power_domain *power_domain) +{ + struct power_domain_ops *ops = power_domain_dev_ops(power_domain->dev); + + debug("%s(power_domain=%p)\n", __func__, power_domain); + + return ops->off(power_domain); +} + +UCLASS_DRIVER(power_domain) = { + .id = UCLASS_POWER_DOMAIN, + .name = "power_domain", +}; diff --git a/drivers/power/domain/sandbox-power-domain-test.c b/drivers/power/domain/sandbox-power-domain-test.c new file mode 100644 index 000000000000..92a3a2a5273b --- /dev/null +++ b/drivers/power/domain/sandbox-power-domain-test.c @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include + +struct sandbox_power_domain_test { + struct power_domain pd; +}; + +int sandbox_power_domain_test_get(struct udevice *dev) +{ + struct sandbox_power_domain_test *sbrt = dev_get_priv(dev); + + return power_domain_get(dev, &sbrt->pd); +} + +int sandbox_power_domain_test_on(struct udevice *dev) +{ + struct sandbox_power_domain_test *sbrt = dev_get_priv(dev); + + return power_domain_on(&sbrt->pd); +} + +int sandbox_power_domain_test_off(struct udevice *dev) +{ + struct sandbox_power_domain_test *sbrt = dev_get_priv(dev); + + return power_domain_off(&sbrt->pd); +} + +int sandbox_power_domain_test_free(struct udevice *dev) +{ + struct sandbox_power_domain_test *sbrt = dev_get_priv(dev); + + return power_domain_free(&sbrt->pd); +} + +static const struct udevice_id sandbox_power_domain_test_ids[] = { + { .compatible = "sandbox,power-domain-test" }, + { } +}; + +U_BOOT_DRIVER(sandbox_power_domain_test) = { + .name = "sandbox_power_domain_test", + .id = UCLASS_MISC, + .of_match = sandbox_power_domain_test_ids, + .priv_auto_alloc_size = sizeof(struct sandbox_power_domain_test), +}; diff --git a/drivers/power/domain/sandbox-power-domain.c b/drivers/power/domain/sandbox-power-domain.c new file mode 100644 index 000000000000..9071346f9844 --- /dev/null +++ b/drivers/power/domain/sandbox-power-domain.c @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include + +#define SANDBOX_POWER_DOMAINS 3 + +struct sandbox_power_domain { + bool on[SANDBOX_POWER_DOMAINS]; +}; + +static int sandbox_power_domain_request(struct power_domain *power_domain) +{ + debug("%s(power_domain=%p)\n", __func__, power_domain); + + if (power_domain->id >= SANDBOX_POWER_DOMAINS) + return -EINVAL; + + return 0; +} + +static int sandbox_power_domain_free(struct power_domain *power_domain) +{ + debug("%s(power_domain=%p)\n", __func__, power_domain); + + return 0; +} + +static int sandbox_power_domain_on(struct power_domain *power_domain) +{ + struct sandbox_power_domain *sbr = dev_get_priv(power_domain->dev); + + debug("%s(power_domain=%p)\n", __func__, power_domain); + + sbr->on[power_domain->id] = true; + + return 0; +} + +static int sandbox_power_domain_off(struct power_domain *power_domain) +{ + struct sandbox_power_domain *sbr = dev_get_priv(power_domain->dev); + + debug("%s(power_domain=%p)\n", __func__, power_domain); + + sbr->on[power_domain->id] = false; + + return 0; +} + +static int sandbox_power_domain_bind(struct udevice *dev) +{ + debug("%s(dev=%p)\n", __func__, dev); + + return 0; +} + +static int sandbox_power_domain_probe(struct udevice *dev) +{ + debug("%s(dev=%p)\n", __func__, dev); + + return 0; +} + +static const struct udevice_id sandbox_power_domain_ids[] = { + { .compatible = "sandbox,power-domain" }, + { } +}; + +struct power_domain_ops sandbox_power_domain_ops = { + .request = sandbox_power_domain_request, + .free = sandbox_power_domain_free, + .on = sandbox_power_domain_on, + .off = sandbox_power_domain_off, +}; + +U_BOOT_DRIVER(sandbox_power_domain) = { + .name = "sandbox_power_domain", + .id = UCLASS_POWER_DOMAIN, + .of_match = sandbox_power_domain_ids, + .bind = sandbox_power_domain_bind, + .probe = sandbox_power_domain_probe, + .priv_auto_alloc_size = sizeof(struct sandbox_power_domain), + .ops = &sandbox_power_domain_ops, +}; + +int sandbox_power_domain_query(struct udevice *dev, unsigned long id) +{ + struct sandbox_power_domain *sbr = dev_get_priv(dev); + + debug("%s(dev=%p, id=%ld)\n", __func__, dev, id); + + if (id >= SANDBOX_POWER_DOMAINS) + return -EINVAL; + + return sbr->on[id]; +} diff --git a/drivers/power/domain/tegra186-power-domain.c b/drivers/power/domain/tegra186-power-domain.c new file mode 100644 index 000000000000..41d84de83e1a --- /dev/null +++ b/drivers/power/domain/tegra186-power-domain.c @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include + +#define UPDATE BIT(0) +#define ON BIT(1) + +static int tegra186_power_domain_request(struct power_domain *power_domain) +{ + debug("%s(power_domain=%p) (dev=%p, id=%lu)\n", __func__, + power_domain, power_domain->dev, power_domain->id); + + return 0; +} + +static int tegra186_power_domain_free(struct power_domain *power_domain) +{ + debug("%s(power_domain=%p) (dev=%p, id=%lu)\n", __func__, + power_domain, power_domain->dev, power_domain->id); + + return 0; +} + +static int tegra186_power_domain_common(struct power_domain *power_domain, + bool on) +{ + struct mrq_pg_update_state_request req; + int on_state = on ? ON : 0; + int ret; + + req.partition_id = power_domain->id; + req.logic_state = UPDATE | on_state; + req.sram_state = UPDATE | on_state; + /* + * Drivers manage their own clocks so they don't get out of sync, and + * since some power domains have many clocks, only a subset of which + * are actually needed depending on use-case. + */ + req.clock_state = UPDATE; + + ret = misc_call(power_domain->dev->parent, MRQ_PG_UPDATE_STATE, &req, + sizeof(req), NULL, 0); + if (ret < 0) + return ret; + + return 0; +} + +static int tegra186_power_domain_on(struct power_domain *power_domain) +{ + debug("%s(power_domain=%p) (dev=%p, id=%lu)\n", __func__, + power_domain, power_domain->dev, power_domain->id); + + return tegra186_power_domain_common(power_domain, true); +} + +static int tegra186_power_domain_off(struct power_domain *power_domain) +{ + debug("%s(power_domain=%p) (dev=%p, id=%lu)\n", __func__, + power_domain, power_domain->dev, power_domain->id); + + return tegra186_power_domain_common(power_domain, false); +} + +struct power_domain_ops tegra186_power_domain_ops = { + .request = tegra186_power_domain_request, + .free = tegra186_power_domain_free, + .on = tegra186_power_domain_on, + .off = tegra186_power_domain_off, +}; + +static int tegra186_power_domain_probe(struct udevice *dev) +{ + debug("%s(dev=%p)\n", __func__, dev); + + return 0; +} + +U_BOOT_DRIVER(tegra186_power_domain) = { + .name = "tegra186_power_domain", + .id = UCLASS_POWER_DOMAIN, + .probe = tegra186_power_domain_probe, + .ops = &tegra186_power_domain_ops, +}; diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 0fe8cc3827f1..5b84f2178b71 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -20,4 +20,11 @@ config SANDBOX_RESET simply accepts requests to reset various HW modules without actually doing anything beyond a little error checking. +config TEGRA186_RESET + bool "Enable Tegra186 BPMP-based reset driver" + depends on TEGRA186_BPMP + help + Enable support for manipulating Tegra's on-SoC reset signals via IPC + requests to the BPMP (Boot and Power Management Processor). + endmenu diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 71f3b219613e..ff0e0907758b 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_DM_RESET) += reset-uclass.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o +obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o diff --git a/drivers/reset/tegra186-reset.c b/drivers/reset/tegra186-reset.c new file mode 100644 index 000000000000..228adda0aa8b --- /dev/null +++ b/drivers/reset/tegra186-reset.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include + +static int tegra186_reset_request(struct reset_ctl *reset_ctl) +{ + debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl, + reset_ctl->dev, reset_ctl->id); + + return 0; +} + +static int tegra186_reset_free(struct reset_ctl *reset_ctl) +{ + debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl, + reset_ctl->dev, reset_ctl->id); + + return 0; +} + +static int tegra186_reset_common(struct reset_ctl *reset_ctl, + enum mrq_reset_commands cmd) +{ + struct mrq_reset_request req; + int ret; + + req.cmd = cmd; + req.reset_id = reset_ctl->id; + + ret = misc_call(reset_ctl->dev->parent, MRQ_RESET, &req, sizeof(req), + NULL, 0); + if (ret < 0) + return ret; + + return 0; +} + +static int tegra186_reset_assert(struct reset_ctl *reset_ctl) +{ + debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl, + reset_ctl->dev, reset_ctl->id); + + return tegra186_reset_common(reset_ctl, CMD_RESET_ASSERT); +} + +static int tegra186_reset_deassert(struct reset_ctl *reset_ctl) +{ + debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl, + reset_ctl->dev, reset_ctl->id); + + return tegra186_reset_common(reset_ctl, CMD_RESET_DEASSERT); +} + +struct reset_ops tegra186_reset_ops = { + .request = tegra186_reset_request, + .free = tegra186_reset_free, + .rst_assert = tegra186_reset_assert, + .rst_deassert = tegra186_reset_deassert, +}; + +static int tegra186_reset_probe(struct udevice *dev) +{ + debug("%s(dev=%p)\n", __func__, dev); + + return 0; +} + +U_BOOT_DRIVER(tegra186_reset) = { + .name = "tegra186_reset", + .id = UCLASS_RESET, + .probe = tegra186_reset_probe, + .ops = &tegra186_reset_ops, +}; diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c index 6bbbe9383954..0c96c8dc83e2 100644 --- a/drivers/spi/tegra210_qspi.c +++ b/drivers/spi/tegra210_qspi.c @@ -1,7 +1,7 @@ /* * NVIDIA Tegra210 QSPI controller driver * - * (C) Copyright 2015 NVIDIA Corporation + * (C) Copyright 2015-2019 NVIDIA Corporation * * SPDX-License-Identifier: GPL-2.0+ */ @@ -41,10 +41,10 @@ DECLARE_GLOBAL_DATA_PTR; #define QSPI_CMD1_BITLEN_SHIFT 0 /* COMMAND2 */ -#define QSPI_CMD2_TX_CLK_TAP_DELAY BIT(6) -#define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(11,6) -#define QSPI_CMD2_RX_CLK_TAP_DELAY BIT(0) -#define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(5,0) +#define QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT 10 +#define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(14,10) +#define QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT 0 +#define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(7,0) /* TRANSFER STATUS */ #define QSPI_XFER_STS_RDY BIT(30) @@ -126,22 +126,31 @@ static int tegra210_qspi_probe(struct udevice *bus) struct tegra210_qspi_priv *priv = dev_get_priv(bus); priv->regs = (struct qspi_regs *)plat->base; + struct qspi_regs *regs = priv->regs; priv->last_transaction_us = timer_get_us(); priv->freq = plat->frequency; priv->periph_id = plat->periph_id; + debug("%s: Freq = %u, id = %d\n", __func__, priv->freq, priv->periph_id); + /* Change SPI clock to correct frequency, PLLP_OUT0 source */ + clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq); + + /* Set tap delays here, clock change above resets QSPI controller */ + u32 reg = (0x09 << QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT) | + (0x0C << QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT); + writel(reg, ®s->command2); + debug("%s: COMMAND2 = %08x\n", __func__, readl(®s->command2)); + return 0; } -static int tegra210_qspi_claim_bus(struct udevice *bus) +static int tegra210_qspi_claim_bus(struct udevice *dev) { + struct udevice *bus = dev->parent; struct tegra210_qspi_priv *priv = dev_get_priv(bus); struct qspi_regs *regs = priv->regs; - /* Change SPI clock to correct frequency, PLLP_OUT0 source */ - clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq); - debug("%s: FIFO STATUS = %08x\n", __func__, readl(®s->fifo_status)); /* Set master mode and sw controlled CS */ @@ -302,12 +311,21 @@ static int tegra210_qspi_xfer(struct udevice *dev, unsigned int bitlen, * Wait for SPI transmit FIFO to empty, or to time out. * The RX FIFO status will be read and cleared last */ - for (tm = 0; tm < QSPI_TIMEOUT; ++tm) { + for (tm = 0; tm <= QSPI_TIMEOUT; ++tm) { u32 fifo_status, xfer_status; xfer_status = readl(®s->xfer_status); - if (!(xfer_status & QSPI_XFER_STS_RDY)) - continue; + if (!(xfer_status & QSPI_XFER_STS_RDY)) { + debug("%s: xfer_status = 0x%08X, tm = %d\n", __func__, xfer_status, tm); + if (tm >= QSPI_TIMEOUT) { + debug("%s: TIMED OUT WAITING ON RDY!\n", __func__); + ret = tm; + goto done; + } else { + debug("%s: tm = %d, continuing for loop ...\n", __func__, tm); + continue; + } + } fifo_status = readl(®s->fifo_status); if (fifo_status & QSPI_FIFO_STS_ERR) { @@ -349,7 +367,7 @@ static int tegra210_qspi_xfer(struct udevice *dev, unsigned int bitlen, /* clear ACK RDY, etc. bits */ writel(readl(®s->fifo_status), ®s->fifo_status); } - +done: if (flags & SPI_XFER_END) spi_cs_deactivate(dev); @@ -357,7 +375,7 @@ static int tegra210_qspi_xfer(struct udevice *dev, unsigned int bitlen, __func__, tmpdin, readl(®s->fifo_status)); if (ret) { - printf("%s: timeout during SPI transfer, tm %d\n", + debug("%s: timeout during SPI transfer, tm %d\n", __func__, ret); return -1; } diff --git a/drivers/spmi/spmi-msm.c b/drivers/spmi/spmi-msm.c index 0cef505e37d0..48bc15759645 100644 --- a/drivers/spmi/spmi-msm.c +++ b/drivers/spmi/spmi-msm.c @@ -153,11 +153,12 @@ static int msm_spmi_probe(struct udevice *dev) priv->spmi_core = fdtdec_get_addr_size_auto_parent(gd->fdt_blob, parent->of_offset, dev->of_offset, - "reg", 1, NULL); + "reg", 1, NULL, + false); priv->spmi_obs = fdtdec_get_addr_size_auto_parent(gd->fdt_blob, parent->of_offset, dev->of_offset, "reg", - 2, NULL); + 2, NULL, false); if (priv->arb_chnl == FDT_ADDR_T_NONE || priv->spmi_core == FDT_ADDR_T_NONE || priv->spmi_obs == FDT_ADDR_T_NONE) diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c index 40b798a43fa6..1b4edd604a1a 100644 --- a/fs/ext4/ext4_common.c +++ b/fs/ext4/ext4_common.c @@ -33,19 +33,155 @@ struct ext2_data *ext4fs_root; struct ext2fs_node *ext4fs_file; -uint32_t *ext4fs_indir1_block; +__le32 *ext4fs_indir1_block; int ext4fs_indir1_size; int ext4fs_indir1_blkno = -1; -uint32_t *ext4fs_indir2_block; +__le32 *ext4fs_indir2_block; int ext4fs_indir2_size; int ext4fs_indir2_blkno = -1; -uint32_t *ext4fs_indir3_block; +__le32 *ext4fs_indir3_block; int ext4fs_indir3_size; int ext4fs_indir3_blkno = -1; struct ext2_inode *g_parent_inode; static int symlinknest; +#if defined(CONFIG_EXT4_WRITE) +struct ext2_block_group *ext4fs_get_group_descriptor + (const struct ext_filesystem *fs, uint32_t bg_idx) +{ + return (struct ext2_block_group *)(fs->gdtable + (bg_idx * fs->gdsize)); +} + +static inline void ext4fs_sb_free_inodes_dec(struct ext2_sblock *sb) +{ + sb->free_inodes = cpu_to_le32(le32_to_cpu(sb->free_inodes) - 1); +} + +static inline void ext4fs_sb_free_blocks_dec(struct ext2_sblock *sb) +{ + uint64_t free_blocks = le32_to_cpu(sb->free_blocks); + free_blocks += (uint64_t)le32_to_cpu(sb->free_blocks_high) << 32; + free_blocks--; + + sb->free_blocks = cpu_to_le32(free_blocks & 0xffffffff); + sb->free_blocks_high = cpu_to_le16(free_blocks >> 32); +} + +static inline void ext4fs_bg_free_inodes_dec + (struct ext2_block_group *bg, const struct ext_filesystem *fs) +{ + uint32_t free_inodes = le16_to_cpu(bg->free_inodes); + if (fs->gdsize == 64) + free_inodes += le16_to_cpu(bg->free_inodes_high) << 16; + free_inodes--; + + bg->free_inodes = cpu_to_le16(free_inodes & 0xffff); + if (fs->gdsize == 64) + bg->free_inodes_high = cpu_to_le16(free_inodes >> 16); +} + +static inline void ext4fs_bg_free_blocks_dec + (struct ext2_block_group *bg, const struct ext_filesystem *fs) +{ + uint32_t free_blocks = le16_to_cpu(bg->free_blocks); + if (fs->gdsize == 64) + free_blocks += le16_to_cpu(bg->free_blocks_high) << 16; + free_blocks--; + + bg->free_blocks = cpu_to_le16(free_blocks & 0xffff); + if (fs->gdsize == 64) + bg->free_blocks_high = cpu_to_le16(free_blocks >> 16); +} + +static inline void ext4fs_bg_itable_unused_dec + (struct ext2_block_group *bg, const struct ext_filesystem *fs) +{ + uint32_t free_inodes = le16_to_cpu(bg->bg_itable_unused); + if (fs->gdsize == 64) + free_inodes += le16_to_cpu(bg->bg_itable_unused_high) << 16; + free_inodes--; + + bg->bg_itable_unused = cpu_to_le16(free_inodes & 0xffff); + if (fs->gdsize == 64) + bg->bg_itable_unused_high = cpu_to_le16(free_inodes >> 16); +} + +uint64_t ext4fs_sb_get_free_blocks(const struct ext2_sblock *sb) +{ + uint64_t free_blocks = le32_to_cpu(sb->free_blocks); + free_blocks += (uint64_t)le32_to_cpu(sb->free_blocks_high) << 32; + return free_blocks; +} + +void ext4fs_sb_set_free_blocks(struct ext2_sblock *sb, uint64_t free_blocks) +{ + sb->free_blocks = cpu_to_le32(free_blocks & 0xffffffff); + sb->free_blocks_high = cpu_to_le16(free_blocks >> 32); +} + +uint32_t ext4fs_bg_get_free_blocks(const struct ext2_block_group *bg, + const struct ext_filesystem *fs) +{ + uint32_t free_blocks = le16_to_cpu(bg->free_blocks); + if (fs->gdsize == 64) + free_blocks += le16_to_cpu(bg->free_blocks_high) << 16; + return free_blocks; +} + +static inline +uint32_t ext4fs_bg_get_free_inodes(const struct ext2_block_group *bg, + const struct ext_filesystem *fs) +{ + uint32_t free_inodes = le16_to_cpu(bg->free_inodes); + if (fs->gdsize == 64) + free_inodes += le16_to_cpu(bg->free_inodes_high) << 16; + return free_inodes; +} + +static inline uint16_t ext4fs_bg_get_flags(const struct ext2_block_group *bg) +{ + return le16_to_cpu(bg->bg_flags); +} + +static inline void ext4fs_bg_set_flags(struct ext2_block_group *bg, + uint16_t flags) +{ + bg->bg_flags = cpu_to_le16(flags); +} + +/* Block number of the block bitmap */ +uint64_t ext4fs_bg_get_block_id(const struct ext2_block_group *bg, + const struct ext_filesystem *fs) +{ + uint64_t block_nr = le32_to_cpu(bg->block_id); + if (fs->gdsize == 64) + block_nr += (uint64_t)le32_to_cpu(bg->block_id_high) << 32; + return block_nr; +} + +/* Block number of the inode bitmap */ +uint64_t ext4fs_bg_get_inode_id(const struct ext2_block_group *bg, + const struct ext_filesystem *fs) +{ + uint64_t block_nr = le32_to_cpu(bg->inode_id); + if (fs->gdsize == 64) + block_nr += (uint64_t)le32_to_cpu(bg->inode_id_high) << 32; + return block_nr; +} +#endif + +/* Block number of the inode table */ +uint64_t ext4fs_bg_get_inode_table_id(const struct ext2_block_group *bg, + const struct ext_filesystem *fs) +{ + uint64_t block_nr = le32_to_cpu(bg->inode_table_id); + if (fs->gdsize == 64) + block_nr += + (uint64_t)le32_to_cpu(bg->inode_table_id_high) << 32; + return block_nr; +} + #if defined(CONFIG_EXT4_WRITE) uint32_t ext4fs_div_roundup(uint32_t size, uint32_t n) { @@ -112,7 +248,7 @@ static int _get_new_inode_no(unsigned char *buffer) while (*ptr == 255) { ptr++; count += 8; - if (count > ext4fs_root->sblock.inodes_per_group) + if (count > le32_to_cpu(ext4fs_root->sblock.inodes_per_group)) return -1; } @@ -138,18 +274,12 @@ static int _get_new_inode_no(unsigned char *buffer) static int _get_new_blk_no(unsigned char *buffer) { - unsigned char input; - int operand, status; + int operand; int count = 0; - int j = 0; + int i; unsigned char *ptr = buffer; struct ext_filesystem *fs = get_fs(); - if (fs->blksz != 1024) - count = 0; - else - count = 1; - while (*ptr == 255) { ptr++; count += 8; @@ -157,21 +287,17 @@ static int _get_new_blk_no(unsigned char *buffer) return -1; } - for (j = 0; j < fs->blksz; j++) { - input = *ptr; - int i = 0; - while (i <= 7) { - operand = 1 << i; - status = input & operand; - if (status) { - i++; - count++; - } else { - *ptr |= operand; - return count; - } + if (fs->blksz == 1024) + count += 1; + + for (i = 0; i <= 7; i++) { + operand = 1 << i; + if (*ptr & operand) { + count++; + } else { + *ptr |= operand; + return count; } - ptr = ptr + 1; } return -1; @@ -249,7 +375,7 @@ int ext4fs_set_inode_bmap(int inode_no, unsigned char *buffer, int index) unsigned char *ptr = buffer; unsigned char operand; - inode_no -= (index * ext4fs_root->sblock.inodes_per_group); + inode_no -= (index * le32_to_cpu(ext4fs_root->sblock.inodes_per_group)); i = inode_no / 8; remainder = inode_no % 8; if (remainder == 0) { @@ -274,7 +400,7 @@ void ext4fs_reset_inode_bmap(int inode_no, unsigned char *buffer, int index) unsigned char *ptr = buffer; unsigned char operand; - inode_no -= (index * ext4fs_root->sblock.inodes_per_group); + inode_no -= (index * le32_to_cpu(ext4fs_root->sblock.inodes_per_group)); i = inode_no / 8; remainder = inode_no % 8; if (remainder == 0) { @@ -289,19 +415,20 @@ void ext4fs_reset_inode_bmap(int inode_no, unsigned char *buffer, int index) *ptr = *ptr & ~(operand); } -int ext4fs_checksum_update(unsigned int i) +uint16_t ext4fs_checksum_update(uint32_t i) { struct ext2_block_group *desc; struct ext_filesystem *fs = get_fs(); - __u16 crc = 0; + uint16_t crc = 0; + __le32 le32_i = cpu_to_le32(i); - desc = (struct ext2_block_group *)&fs->bgd[i]; - if (fs->sb->feature_ro_compat & EXT4_FEATURE_RO_COMPAT_GDT_CSUM) { + desc = ext4fs_get_group_descriptor(fs, i); + if (le32_to_cpu(fs->sb->feature_ro_compat) & EXT4_FEATURE_RO_COMPAT_GDT_CSUM) { int offset = offsetof(struct ext2_block_group, bg_checksum); crc = ext2fs_crc16(~0, fs->sb->unique_id, sizeof(fs->sb->unique_id)); - crc = ext2fs_crc16(crc, &i, sizeof(i)); + crc = ext2fs_crc16(crc, &le32_i, sizeof(le32_i)); crc = ext2fs_crc16(crc, desc, offset); offset += sizeof(desc->bg_checksum); /* skip checksum */ assert(offset == sizeof(*desc)); @@ -322,7 +449,7 @@ static int check_void_in_dentry(struct ext2_dirent *dir, char *filename) dentry_length = sizeof(struct ext2_dirent) + dir->namelen + padding_factor; - sizeof_void_space = dir->direntlen - dentry_length; + sizeof_void_space = le16_to_cpu(dir->direntlen) - dentry_length; if (sizeof_void_space == 0) return 0; @@ -333,58 +460,57 @@ static int check_void_in_dentry(struct ext2_dirent *dir, char *filename) new_entry_byte_reqd = strlen(filename) + sizeof(struct ext2_dirent) + padding_factor; if (sizeof_void_space >= new_entry_byte_reqd) { - dir->direntlen = dentry_length; + dir->direntlen = cpu_to_le16(dentry_length); return sizeof_void_space; } return 0; } -void ext4fs_update_parent_dentry(char *filename, int *p_ino, int file_type) +int ext4fs_update_parent_dentry(char *filename, int file_type) { unsigned int *zero_buffer = NULL; char *root_first_block_buffer = NULL; - int direct_blk_idx; - long int root_blknr; + int blk_idx; long int first_block_no_of_root = 0; - long int previous_blknr = -1; int totalbytes = 0; - short int padding_factor = 0; unsigned int new_entry_byte_reqd; - unsigned int last_entry_dirlen; int sizeof_void_space = 0; int templength = 0; - int inodeno; + int inodeno = -1; int status; struct ext_filesystem *fs = get_fs(); /* directory entry */ struct ext2_dirent *dir; char *temp_dir = NULL; + uint32_t new_blk_no; + uint32_t new_size; + uint32_t new_blockcnt; + uint32_t directory_blocks; zero_buffer = zalloc(fs->blksz); if (!zero_buffer) { printf("No Memory\n"); - return; + return -1; } root_first_block_buffer = zalloc(fs->blksz); if (!root_first_block_buffer) { free(zero_buffer); printf("No Memory\n"); - return; + return -1; } + new_entry_byte_reqd = ROUND(strlen(filename) + + sizeof(struct ext2_dirent), 4); restart: + directory_blocks = le32_to_cpu(g_parent_inode->size) >> + LOG2_BLOCK_SIZE(ext4fs_root); + blk_idx = directory_blocks - 1; +restart_read: /* read the block no allocated to a file */ - for (direct_blk_idx = 0; direct_blk_idx < INDIRECT_BLOCKS; - direct_blk_idx++) { - root_blknr = read_allocated_block(g_parent_inode, - direct_blk_idx); - if (root_blknr == 0) { - first_block_no_of_root = previous_blknr; - break; - } - previous_blknr = root_blknr; - } + first_block_no_of_root = read_allocated_block(g_parent_inode, blk_idx, NULL); + if (first_block_no_of_root <= 0) + goto fail; status = ext4fs_devread((lbaint_t)first_block_no_of_root * fs->sect_perblk, @@ -396,66 +522,63 @@ void ext4fs_update_parent_dentry(char *filename, int *p_ino, int file_type) goto fail; dir = (struct ext2_dirent *)root_first_block_buffer; totalbytes = 0; - while (dir->direntlen > 0) { - /* - * blocksize-totalbytes because last directory length - * i.e. dir->direntlen is free availble space in the - * block that means it is a last entry of directory - * entry - */ - /* traversing the each directory entry */ - if (fs->blksz - totalbytes == dir->direntlen) { - if (strlen(filename) % 4 != 0) - padding_factor = 4 - (strlen(filename) % 4); - - new_entry_byte_reqd = strlen(filename) + - sizeof(struct ext2_dirent) + padding_factor; - padding_factor = 0; - /* - * update last directory entry length to its - * length because we are creating new directory - * entry - */ - if (dir->namelen % 4 != 0) - padding_factor = 4 - (dir->namelen % 4); - - last_entry_dirlen = dir->namelen + - sizeof(struct ext2_dirent) + padding_factor; - if ((fs->blksz - totalbytes - last_entry_dirlen) < - new_entry_byte_reqd) { - printf("1st Block Full:Allocate new block\n"); - - if (direct_blk_idx == INDIRECT_BLOCKS - 1) { + while (le16_to_cpu(dir->direntlen) > 0) { + unsigned short used_len = ROUND(dir->namelen + + sizeof(struct ext2_dirent), 4); + + /* last entry of block */ + if (fs->blksz - totalbytes == le16_to_cpu(dir->direntlen)) { + + /* check if new entry fits */ + if ((used_len + new_entry_byte_reqd) <= + le16_to_cpu(dir->direntlen)) { + dir->direntlen = cpu_to_le16(used_len); + break; + } else { + if (blk_idx > 0) { + printf("Block full, trying previous\n"); + blk_idx--; + goto restart_read; + } + printf("All blocks full: Allocate new\n"); + + if (le32_to_cpu(g_parent_inode->flags) & + EXT4_EXTENTS_FL) { + printf("Directory uses extents\n"); + goto fail; + } + if (directory_blocks >= INDIRECT_BLOCKS) { printf("Directory exceeds limit\n"); goto fail; } - g_parent_inode->b.blocks.dir_blocks - [direct_blk_idx] = ext4fs_get_new_blk_no(); - if (g_parent_inode->b.blocks.dir_blocks - [direct_blk_idx] == -1) { + new_blk_no = ext4fs_get_new_blk_no(); + if (new_blk_no == -1) { printf("no block left to assign\n"); goto fail; } - put_ext4(((uint64_t) - ((uint64_t)g_parent_inode->b. - blocks.dir_blocks[direct_blk_idx] * - (uint64_t)fs->blksz)), zero_buffer, fs->blksz); - g_parent_inode->size = - g_parent_inode->size + fs->blksz; - g_parent_inode->blockcnt = - g_parent_inode->blockcnt + fs->sect_perblk; + put_ext4((uint64_t)new_blk_no * fs->blksz, zero_buffer, fs->blksz); + g_parent_inode->b.blocks. + dir_blocks[directory_blocks] = + cpu_to_le32(new_blk_no); + + new_size = le32_to_cpu(g_parent_inode->size); + new_size += fs->blksz; + g_parent_inode->size = cpu_to_le32(new_size); + + new_blockcnt = le32_to_cpu(g_parent_inode->blockcnt); + new_blockcnt += fs->sect_perblk; + g_parent_inode->blockcnt = cpu_to_le32(new_blockcnt); + if (ext4fs_put_metadata (root_first_block_buffer, first_block_no_of_root)) goto fail; goto restart; } - dir->direntlen = last_entry_dirlen; - break; } - templength = dir->direntlen; + templength = le16_to_cpu(dir->direntlen); totalbytes = totalbytes + templength; sizeof_void_space = check_void_in_dentry(dir, filename); if (sizeof_void_space) @@ -465,7 +588,7 @@ void ext4fs_update_parent_dentry(char *filename, int *p_ino, int file_type) } /* make a pointer ready for creating next directory entry */ - templength = dir->direntlen; + templength = le16_to_cpu(dir->direntlen); totalbytes = totalbytes + templength; dir = (struct ext2_dirent *)((char *)dir + templength); @@ -475,11 +598,11 @@ void ext4fs_update_parent_dentry(char *filename, int *p_ino, int file_type) printf("no inode left to assign\n"); goto fail; } - dir->inode = inodeno; + dir->inode = cpu_to_le32(inodeno); if (sizeof_void_space) - dir->direntlen = sizeof_void_space; + dir->direntlen = cpu_to_le16(sizeof_void_space); else - dir->direntlen = fs->blksz - totalbytes; + dir->direntlen = cpu_to_le16(fs->blksz - totalbytes); dir->namelen = strlen(filename); dir->filetype = FILETYPE_REG; /* regular file */ @@ -487,8 +610,6 @@ void ext4fs_update_parent_dentry(char *filename, int *p_ino, int file_type) temp_dir = temp_dir + sizeof(struct ext2_dirent); memcpy(temp_dir, filename, strlen(filename)); - *p_ino = inodeno; - /* update or write the 1st block of root inode */ if (ext4fs_put_metadata(root_first_block_buffer, first_block_no_of_root)) @@ -497,82 +618,65 @@ void ext4fs_update_parent_dentry(char *filename, int *p_ino, int file_type) fail: free(zero_buffer); free(root_first_block_buffer); + + return inodeno; } static int search_dir(struct ext2_inode *parent_inode, char *dirname) { int status; - int inodeno; - int totalbytes; - int templength; - int direct_blk_idx; + int inodeno = 0; + int offset; + int blk_idx; long int blknr; - int found = 0; - char *ptr = NULL; - unsigned char *block_buffer = NULL; + char *block_buffer = NULL; struct ext2_dirent *dir = NULL; - struct ext2_dirent *previous_dir = NULL; struct ext_filesystem *fs = get_fs(); + uint32_t directory_blocks; + char *direntname; - /* read the block no allocated to a file */ - for (direct_blk_idx = 0; direct_blk_idx < INDIRECT_BLOCKS; - direct_blk_idx++) { - blknr = read_allocated_block(parent_inode, direct_blk_idx); - if (blknr == 0) - goto fail; + directory_blocks = le32_to_cpu(parent_inode->size) >> + LOG2_BLOCK_SIZE(ext4fs_root); - /* read the blocks of parenet inode */ - block_buffer = zalloc(fs->blksz); - if (!block_buffer) + block_buffer = zalloc(fs->blksz); + if (!block_buffer) + goto fail; + + /* get the block no allocated to a file */ + for (blk_idx = 0; blk_idx < directory_blocks; blk_idx++) { + blknr = read_allocated_block(parent_inode, blk_idx, NULL); + if (blknr <= 0) goto fail; + /* read the directory block */ status = ext4fs_devread((lbaint_t)blknr * fs->sect_perblk, 0, fs->blksz, (char *)block_buffer); if (status == 0) goto fail; - dir = (struct ext2_dirent *)block_buffer; - ptr = (char *)dir; - totalbytes = 0; - while (dir->direntlen >= 0) { - /* - * blocksize-totalbytes because last directory - * length i.e.,*dir->direntlen is free availble - * space in the block that means - * it is a last entry of directory entry - */ - if (strlen(dirname) == dir->namelen) { - if (strncmp(dirname, ptr + - sizeof(struct ext2_dirent), - dir->namelen) == 0) { - previous_dir->direntlen += - dir->direntlen; - inodeno = dir->inode; - dir->inode = 0; - found = 1; - break; - } - } + offset = 0; + do { + dir = (struct ext2_dirent *)(block_buffer + offset); + direntname = (char*)(dir) + sizeof(struct ext2_dirent); - if (fs->blksz - totalbytes == dir->direntlen) + int direntlen = le16_to_cpu(dir->direntlen); + if (direntlen < sizeof(struct ext2_dirent)) break; - /* traversing the each directory entry */ - templength = dir->direntlen; - totalbytes = totalbytes + templength; - previous_dir = dir; - dir = (struct ext2_dirent *)((char *)dir + templength); - ptr = (char *)dir; - } + if (dir->inode && (strlen(dirname) == dir->namelen) && + (strncmp(dirname, direntname, dir->namelen) == 0)) { + inodeno = le32_to_cpu(dir->inode); + break; + } + + offset += direntlen; - if (found == 1) { + } while (offset < fs->blksz); + + if (inodeno > 0) { free(block_buffer); - block_buffer = NULL; return inodeno; } - - free(block_buffer); - block_buffer = NULL; } fail: @@ -720,7 +824,7 @@ int ext4fs_get_parent_inode_num(const char *dirname, char *dname, int flags) if (matched_inode_no != -1) { ext4fs_iget(matched_inode_no, &temp_inode); - if (temp_inode.mode & S_IFDIR) { + if (le16_to_cpu(temp_inode.mode) & S_IFDIR) { printf("It is a Directory\n"); result_inode_no = -1; goto fail; @@ -748,15 +852,13 @@ int ext4fs_get_parent_inode_num(const char *dirname, char *dname, int flags) return result_inode_no; } -static int check_filename(char *filename, unsigned int blknr) +static int unlink_filename(char *filename, unsigned int blknr) { - unsigned int first_block_no_of_root; int totalbytes = 0; int templength = 0; int status, inodeno; int found = 0; char *root_first_block_buffer = NULL; - char *root_first_block_addr = NULL; struct ext2_dirent *dir = NULL; struct ext2_dirent *previous_dir = NULL; char *ptr = NULL; @@ -764,46 +866,48 @@ static int check_filename(char *filename, unsigned int blknr) int ret = -1; /* get the first block of root */ - first_block_no_of_root = blknr; root_first_block_buffer = zalloc(fs->blksz); if (!root_first_block_buffer) return -ENOMEM; - root_first_block_addr = root_first_block_buffer; - status = ext4fs_devread((lbaint_t)first_block_no_of_root * - fs->sect_perblk, 0, + status = ext4fs_devread((lbaint_t)blknr * fs->sect_perblk, 0, fs->blksz, root_first_block_buffer); if (status == 0) goto fail; - if (ext4fs_log_journal(root_first_block_buffer, first_block_no_of_root)) + if (ext4fs_log_journal(root_first_block_buffer, blknr)) goto fail; dir = (struct ext2_dirent *)root_first_block_buffer; ptr = (char *)dir; totalbytes = 0; - while (dir->direntlen >= 0) { + while (le16_to_cpu(dir->direntlen) >= 0) { /* * blocksize-totalbytes because last * directory length i.e., *dir->direntlen * is free availble space in the block that * means it is a last entry of directory entry */ - if (strlen(filename) == dir->namelen) { - if (strncmp(filename, ptr + sizeof(struct ext2_dirent), - dir->namelen) == 0) { - printf("file found deleting\n"); - previous_dir->direntlen += dir->direntlen; - inodeno = dir->inode; + if (dir->inode && (strlen(filename) == dir->namelen) && + (strncmp(ptr + sizeof(struct ext2_dirent), + filename, dir->namelen) == 0)) { + printf("file found, deleting\n"); + inodeno = le32_to_cpu(dir->inode); + if (previous_dir) { + uint16_t new_len; + new_len = le16_to_cpu(previous_dir->direntlen); + new_len += le16_to_cpu(dir->direntlen); + previous_dir->direntlen = cpu_to_le16(new_len); + } else { dir->inode = 0; - found = 1; - break; } + found = 1; + break; } - if (fs->blksz - totalbytes == dir->direntlen) + if (fs->blksz - totalbytes == le16_to_cpu(dir->direntlen)) break; /* traversing the each directory entry */ - templength = dir->direntlen; + templength = le16_to_cpu(dir->direntlen); totalbytes = totalbytes + templength; previous_dir = dir; dir = (struct ext2_dirent *)((char *)dir + templength); @@ -812,8 +916,7 @@ static int check_filename(char *filename, unsigned int blknr) if (found == 1) { - if (ext4fs_put_metadata(root_first_block_addr, - first_block_no_of_root)) + if (ext4fs_put_metadata(root_first_block_buffer, blknr)) goto fail; ret = inodeno; } @@ -823,19 +926,22 @@ static int check_filename(char *filename, unsigned int blknr) return ret; } -int ext4fs_filename_check(char *filename) +int ext4fs_filename_unlink(char *filename) { - short direct_blk_idx = 0; + int blk_idx; long int blknr = -1; int inodeno = -1; + uint32_t directory_blocks; + + directory_blocks = le32_to_cpu(g_parent_inode->size) >> + LOG2_BLOCK_SIZE(ext4fs_root); /* read the block no allocated to a file */ - for (direct_blk_idx = 0; direct_blk_idx < INDIRECT_BLOCKS; - direct_blk_idx++) { - blknr = read_allocated_block(g_parent_inode, direct_blk_idx); - if (blknr == 0) + for (blk_idx = 0; blk_idx < directory_blocks; blk_idx++) { + blknr = read_allocated_block(g_parent_inode, blk_idx, NULL); + if (blknr <= 0) break; - inodeno = check_filename(filename, blknr); + inodeno = unlink_filename(filename, blknr); if (inodeno != -1) return inodeno; } @@ -843,53 +949,54 @@ int ext4fs_filename_check(char *filename) return -1; } -long int ext4fs_get_new_blk_no(void) +uint32_t ext4fs_get_new_blk_no(void) { short i; short status; int remainder; unsigned int bg_idx; static int prev_bg_bitmap_index = -1; - unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group; + unsigned int blk_per_grp = le32_to_cpu(ext4fs_root->sblock.blocks_per_group); struct ext_filesystem *fs = get_fs(); char *journal_buffer = zalloc(fs->blksz); char *zero_buffer = zalloc(fs->blksz); if (!journal_buffer || !zero_buffer) goto fail; - struct ext2_block_group *bgd = (struct ext2_block_group *)fs->gdtable; if (fs->first_pass_bbmap == 0) { for (i = 0; i < fs->no_blkgrp; i++) { - if (bgd[i].free_blocks) { - if (bgd[i].bg_flags & EXT4_BG_BLOCK_UNINIT) { - put_ext4(((uint64_t) ((uint64_t)bgd[i].block_id * - (uint64_t)fs->blksz)), - zero_buffer, fs->blksz); - bgd[i].bg_flags = - bgd[i]. - bg_flags & ~EXT4_BG_BLOCK_UNINIT; + struct ext2_block_group *bgd = NULL; + bgd = ext4fs_get_group_descriptor(fs, i); + if (ext4fs_bg_get_free_blocks(bgd, fs)) { + uint16_t bg_flags = ext4fs_bg_get_flags(bgd); + uint64_t b_bitmap_blk = + ext4fs_bg_get_block_id(bgd, fs); + if (bg_flags & EXT4_BG_BLOCK_UNINIT) { memcpy(fs->blk_bmaps[i], zero_buffer, fs->blksz); + put_ext4(b_bitmap_blk * fs->blksz, + fs->blk_bmaps[i], fs->blksz); + bg_flags &= ~EXT4_BG_BLOCK_UNINIT; + ext4fs_bg_set_flags(bgd, bg_flags); } fs->curr_blkno = _get_new_blk_no(fs->blk_bmaps[i]); if (fs->curr_blkno == -1) - /* if block bitmap is completely fill */ + /* block bitmap is completely filled */ continue; fs->curr_blkno = fs->curr_blkno + (i * fs->blksz * 8); fs->first_pass_bbmap++; - bgd[i].free_blocks--; - fs->sb->free_blocks--; - status = ext4fs_devread((lbaint_t) - bgd[i].block_id * - fs->sect_perblk, 0, - fs->blksz, + ext4fs_bg_free_blocks_dec(bgd, fs); + ext4fs_sb_free_blocks_dec(fs->sb); + status = ext4fs_devread(b_bitmap_blk * + fs->sect_perblk, + 0, fs->blksz, journal_buffer); if (status == 0) goto fail; if (ext4fs_log_journal(journal_buffer, - bgd[i].block_id)) + b_bitmap_blk)) goto fail; goto success; } else { @@ -899,8 +1006,8 @@ long int ext4fs_get_new_blk_no(void) goto fail; } else { -restart: fs->curr_blkno++; +restart: /* get the blockbitmap index respective to blockno */ bg_idx = fs->curr_blkno / blk_per_grp; if (fs->blksz == 1024) { @@ -916,45 +1023,47 @@ long int ext4fs_get_new_blk_no(void) if (bg_idx >= fs->no_blkgrp) goto fail; - if (bgd[bg_idx].free_blocks == 0) { + struct ext2_block_group *bgd = NULL; + bgd = ext4fs_get_group_descriptor(fs, bg_idx); + if (ext4fs_bg_get_free_blocks(bgd, fs) == 0) { debug("block group %u is full. Skipping\n", bg_idx); - fs->curr_blkno = fs->curr_blkno + blk_per_grp; - fs->curr_blkno--; + fs->curr_blkno = (bg_idx + 1) * blk_per_grp; + if (fs->blksz == 1024) + fs->curr_blkno += 1; goto restart; } - if (bgd[bg_idx].bg_flags & EXT4_BG_BLOCK_UNINIT) { - memset(zero_buffer, '\0', fs->blksz); - put_ext4(((uint64_t) ((uint64_t)bgd[bg_idx].block_id * - (uint64_t)fs->blksz)), zero_buffer, fs->blksz); + uint16_t bg_flags = ext4fs_bg_get_flags(bgd); + uint64_t b_bitmap_blk = ext4fs_bg_get_block_id(bgd, fs); + if (bg_flags & EXT4_BG_BLOCK_UNINIT) { memcpy(fs->blk_bmaps[bg_idx], zero_buffer, fs->blksz); - bgd[bg_idx].bg_flags = bgd[bg_idx].bg_flags & - ~EXT4_BG_BLOCK_UNINIT; + put_ext4(b_bitmap_blk * fs->blksz, + zero_buffer, fs->blksz); + bg_flags &= ~EXT4_BG_BLOCK_UNINIT; + ext4fs_bg_set_flags(bgd, bg_flags); } if (ext4fs_set_block_bmap(fs->curr_blkno, fs->blk_bmaps[bg_idx], bg_idx) != 0) { debug("going for restart for the block no %ld %u\n", fs->curr_blkno, bg_idx); + fs->curr_blkno++; goto restart; } /* journal backup */ if (prev_bg_bitmap_index != bg_idx) { - memset(journal_buffer, '\0', fs->blksz); - status = ext4fs_devread((lbaint_t)bgd[bg_idx].block_id - * fs->sect_perblk, + status = ext4fs_devread(b_bitmap_blk * fs->sect_perblk, 0, fs->blksz, journal_buffer); if (status == 0) goto fail; - if (ext4fs_log_journal(journal_buffer, - bgd[bg_idx].block_id)) + if (ext4fs_log_journal(journal_buffer, b_bitmap_blk)) goto fail; prev_bg_bitmap_index = bg_idx; } - bgd[bg_idx].free_blocks--; - fs->sb->free_blocks--; + ext4fs_bg_free_blocks_dec(bgd, fs); + ext4fs_sb_free_blocks_dec(fs->sb); goto success; } success: @@ -975,51 +1084,55 @@ int ext4fs_get_new_inode_no(void) short status; unsigned int ibmap_idx; static int prev_inode_bitmap_index = -1; - unsigned int inodes_per_grp = ext4fs_root->sblock.inodes_per_group; + unsigned int inodes_per_grp = le32_to_cpu(ext4fs_root->sblock.inodes_per_group); struct ext_filesystem *fs = get_fs(); char *journal_buffer = zalloc(fs->blksz); char *zero_buffer = zalloc(fs->blksz); if (!journal_buffer || !zero_buffer) goto fail; - struct ext2_block_group *bgd = (struct ext2_block_group *)fs->gdtable; + int has_gdt_chksum = le32_to_cpu(fs->sb->feature_ro_compat) & + EXT4_FEATURE_RO_COMPAT_GDT_CSUM ? 1 : 0; if (fs->first_pass_ibmap == 0) { for (i = 0; i < fs->no_blkgrp; i++) { - if (bgd[i].free_inodes) { - if (bgd[i].bg_itable_unused != - bgd[i].free_inodes) - bgd[i].bg_itable_unused = - bgd[i].free_inodes; - if (bgd[i].bg_flags & EXT4_BG_INODE_UNINIT) { - put_ext4(((uint64_t) - ((uint64_t)bgd[i].inode_id * - (uint64_t)fs->blksz)), + uint32_t free_inodes; + struct ext2_block_group *bgd = NULL; + bgd = ext4fs_get_group_descriptor(fs, i); + free_inodes = ext4fs_bg_get_free_inodes(bgd, fs); + if (free_inodes) { + uint16_t bg_flags = ext4fs_bg_get_flags(bgd); + uint64_t i_bitmap_blk = + ext4fs_bg_get_inode_id(bgd, fs); + if (has_gdt_chksum) + bgd->bg_itable_unused = free_inodes; + if (bg_flags & EXT4_BG_INODE_UNINIT) { + put_ext4(i_bitmap_blk * fs->blksz, zero_buffer, fs->blksz); - bgd[i].bg_flags = bgd[i].bg_flags & - ~EXT4_BG_INODE_UNINIT; + bg_flags &= ~EXT4_BG_INODE_UNINIT; + ext4fs_bg_set_flags(bgd, bg_flags); memcpy(fs->inode_bmaps[i], zero_buffer, fs->blksz); } fs->curr_inode_no = _get_new_inode_no(fs->inode_bmaps[i]); if (fs->curr_inode_no == -1) - /* if block bitmap is completely fill */ + /* inode bitmap is completely filled */ continue; fs->curr_inode_no = fs->curr_inode_no + (i * inodes_per_grp); fs->first_pass_ibmap++; - bgd[i].free_inodes--; - bgd[i].bg_itable_unused--; - fs->sb->free_inodes--; - status = ext4fs_devread((lbaint_t) - bgd[i].inode_id * - fs->sect_perblk, 0, - fs->blksz, + ext4fs_bg_free_inodes_dec(bgd, fs); + if (has_gdt_chksum) + ext4fs_bg_itable_unused_dec(bgd, fs); + ext4fs_sb_free_inodes_dec(fs->sb); + status = ext4fs_devread(i_bitmap_blk * + fs->sect_perblk, + 0, fs->blksz, journal_buffer); if (status == 0) goto fail; if (ext4fs_log_journal(journal_buffer, - bgd[i].inode_id)) + i_bitmap_blk)) goto fail; goto success; } else @@ -1031,13 +1144,16 @@ int ext4fs_get_new_inode_no(void) fs->curr_inode_no++; /* get the blockbitmap index respective to blockno */ ibmap_idx = fs->curr_inode_no / inodes_per_grp; - if (bgd[ibmap_idx].bg_flags & EXT4_BG_INODE_UNINIT) { - memset(zero_buffer, '\0', fs->blksz); - put_ext4(((uint64_t) ((uint64_t)bgd[ibmap_idx].inode_id * - (uint64_t)fs->blksz)), zero_buffer, - fs->blksz); - bgd[ibmap_idx].bg_flags = - bgd[ibmap_idx].bg_flags & ~EXT4_BG_INODE_UNINIT; + struct ext2_block_group *bgd = + ext4fs_get_group_descriptor(fs, ibmap_idx); + uint16_t bg_flags = ext4fs_bg_get_flags(bgd); + uint64_t i_bitmap_blk = ext4fs_bg_get_inode_id(bgd, fs); + + if (bg_flags & EXT4_BG_INODE_UNINIT) { + put_ext4(i_bitmap_blk * fs->blksz, + zero_buffer, fs->blksz); + bg_flags &= ~EXT4_BG_INODE_UNINIT; + ext4fs_bg_set_flags(bgd, bg_flags); memcpy(fs->inode_bmaps[ibmap_idx], zero_buffer, fs->blksz); } @@ -1052,25 +1168,19 @@ int ext4fs_get_new_inode_no(void) /* journal backup */ if (prev_inode_bitmap_index != ibmap_idx) { - memset(journal_buffer, '\0', fs->blksz); - status = ext4fs_devread((lbaint_t) - bgd[ibmap_idx].inode_id - * fs->sect_perblk, + status = ext4fs_devread(i_bitmap_blk * fs->sect_perblk, 0, fs->blksz, journal_buffer); if (status == 0) goto fail; if (ext4fs_log_journal(journal_buffer, - bgd[ibmap_idx].inode_id)) + le32_to_cpu(bgd->inode_id))) goto fail; prev_inode_bitmap_index = ibmap_idx; } - if (bgd[ibmap_idx].bg_itable_unused != - bgd[ibmap_idx].free_inodes) - bgd[ibmap_idx].bg_itable_unused = - bgd[ibmap_idx].free_inodes; - bgd[ibmap_idx].free_inodes--; - bgd[ibmap_idx].bg_itable_unused--; - fs->sb->free_inodes--; + ext4fs_bg_free_inodes_dec(bgd, fs); + if (has_gdt_chksum) + bgd->bg_itable_unused = bgd->free_inodes; + ext4fs_sb_free_inodes_dec(fs->sb); goto success; } @@ -1097,8 +1207,8 @@ static void alloc_single_indirect_block(struct ext2_inode *file_inode, long int actual_block_no; long int si_blockno; /* si :single indirect */ - unsigned int *si_buffer = NULL; - unsigned int *si_start_addr = NULL; + __le32 *si_buffer = NULL; + __le32 *si_start_addr = NULL; struct ext_filesystem *fs = get_fs(); if (*total_remaining_blocks != 0) { @@ -1128,7 +1238,7 @@ static void alloc_single_indirect_block(struct ext2_inode *file_inode, printf("no block left to assign\n"); goto fail; } - *si_buffer = actual_block_no; + *si_buffer = cpu_to_le32(actual_block_no); debug("SIAB %u: %u\n", *si_buffer, *total_remaining_blocks); @@ -1141,7 +1251,7 @@ static void alloc_single_indirect_block(struct ext2_inode *file_inode, /* write the block to disk */ put_ext4(((uint64_t) ((uint64_t)si_blockno * (uint64_t)fs->blksz)), si_start_addr, fs->blksz); - file_inode->b.blocks.indir_block = si_blockno; + file_inode->b.blocks.indir_block = cpu_to_le32(si_blockno); } fail: free(si_start_addr); @@ -1158,10 +1268,10 @@ static void alloc_double_indirect_block(struct ext2_inode *file_inode, /* di:double indirect */ long int di_blockno_parent; long int di_blockno_child; - unsigned int *di_parent_buffer = NULL; - unsigned int *di_child_buff = NULL; - unsigned int *di_block_start_addr = NULL; - unsigned int *di_child_buff_start = NULL; + __le32 *di_parent_buffer = NULL; + __le32 *di_child_buff = NULL; + __le32 *di_block_start_addr = NULL; + __le32 *di_child_buff_start = NULL; struct ext_filesystem *fs = get_fs(); if (*total_remaining_blocks != 0) { @@ -1205,7 +1315,7 @@ static void alloc_double_indirect_block(struct ext2_inode *file_inode, goto fail; di_child_buff_start = di_child_buff; - *di_parent_buffer = di_blockno_child; + *di_parent_buffer = cpu_to_le32(di_blockno_child); di_parent_buffer++; (*no_blks_reqd)++; debug("DICB %ld: %u\n", di_blockno_child, @@ -1228,7 +1338,7 @@ static void alloc_double_indirect_block(struct ext2_inode *file_inode, printf("no block left to assign\n"); goto fail; } - *di_child_buff = actual_block_no; + *di_child_buff = cpu_to_le32(actual_block_no); debug("DIAB %ld: %u\n", actual_block_no, *total_remaining_blocks); @@ -1248,7 +1358,7 @@ static void alloc_double_indirect_block(struct ext2_inode *file_inode, } put_ext4(((uint64_t) ((uint64_t)di_blockno_parent * (uint64_t)fs->blksz)), di_block_start_addr, fs->blksz); - file_inode->b.blocks.double_indir_block = di_blockno_parent; + file_inode->b.blocks.double_indir_block = cpu_to_le32(di_blockno_parent); } fail: free(di_block_start_addr); @@ -1266,12 +1376,12 @@ static void alloc_triple_indirect_block(struct ext2_inode *file_inode, long int ti_gp_blockno; long int ti_parent_blockno; long int ti_child_blockno; - unsigned int *ti_gp_buff = NULL; - unsigned int *ti_parent_buff = NULL; - unsigned int *ti_child_buff = NULL; - unsigned int *ti_gp_buff_start_addr = NULL; - unsigned int *ti_pbuff_start_addr = NULL; - unsigned int *ti_cbuff_start_addr = NULL; + __le32 *ti_gp_buff = NULL; + __le32 *ti_parent_buff = NULL; + __le32 *ti_child_buff = NULL; + __le32 *ti_gp_buff_start_addr = NULL; + __le32 *ti_pbuff_start_addr = NULL; + __le32 *ti_cbuff_start_addr = NULL; struct ext_filesystem *fs = get_fs(); if (*total_remaining_blocks != 0) { /* triple indirect grand parent block connecting to inode */ @@ -1301,7 +1411,7 @@ static void alloc_triple_indirect_block(struct ext2_inode *file_inode, goto fail; ti_pbuff_start_addr = ti_parent_buff; - *ti_gp_buff = ti_parent_blockno; + *ti_gp_buff = cpu_to_le32(ti_parent_blockno); ti_gp_buff++; (*no_blks_reqd)++; debug("TIPB %ld: %u\n", ti_parent_blockno, @@ -1319,7 +1429,7 @@ static void alloc_triple_indirect_block(struct ext2_inode *file_inode, goto fail1; ti_cbuff_start_addr = ti_child_buff; - *ti_parent_buff = ti_child_blockno; + *ti_parent_buff = cpu_to_le32(ti_child_blockno); ti_parent_buff++; (*no_blks_reqd)++; debug("TICB %ld: %u\n", ti_parent_blockno, @@ -1335,7 +1445,7 @@ static void alloc_triple_indirect_block(struct ext2_inode *file_inode, free(ti_cbuff_start_addr); goto fail1; } - *ti_child_buff = actual_block_no; + *ti_child_buff = cpu_to_le32(actual_block_no); debug("TIAB %ld: %u\n", actual_block_no, *total_remaining_blocks); @@ -1364,7 +1474,7 @@ static void alloc_triple_indirect_block(struct ext2_inode *file_inode, /* write the grand parent block */ put_ext4(((uint64_t) ((uint64_t)ti_gp_blockno * (uint64_t)fs->blksz)), ti_gp_buff_start_addr, fs->blksz); - file_inode->b.blocks.triple_indir_block = ti_gp_blockno; + file_inode->b.blocks.triple_indir_block = cpu_to_le32(ti_gp_blockno); free(ti_gp_buff_start_addr); return; } @@ -1389,7 +1499,7 @@ void ext4fs_allocate_blocks(struct ext2_inode *file_inode, printf("no block left to assign\n"); return; } - file_inode->b.blocks.dir_blocks[i] = direct_blockno; + file_inode->b.blocks.dir_blocks[i] = cpu_to_le32(direct_blockno); debug("DB %ld: %u\n", direct_blockno, total_remaining_blocks); total_remaining_blocks--; @@ -1407,12 +1517,12 @@ void ext4fs_allocate_blocks(struct ext2_inode *file_inode, #endif static struct ext4_extent_header *ext4fs_get_extent_block - (struct ext2_data *data, char *buf, + (struct ext2_data *data, struct ext_block_cache *cache, struct ext4_extent_header *ext_block, uint32_t fileblock, int log2_blksz) { struct ext4_extent_idx *index; - unsigned long long block; + lbaint_t block; int blksz = EXT2_BLOCK_SIZE(data); int i; @@ -1420,7 +1530,7 @@ static struct ext4_extent_header *ext4fs_get_extent_block index = (struct ext4_extent_idx *)(ext_block + 1); if (le16_to_cpu(ext_block->eh_magic) != EXT4_EXT_MAGIC) - return 0; + return NULL; if (ext_block->eh_depth == 0) return ext_block; @@ -1432,16 +1542,14 @@ static struct ext4_extent_header *ext4fs_get_extent_block } while (fileblock >= le32_to_cpu(index[i].ei_block)); if (--i < 0) - return 0; + return NULL; block = le16_to_cpu(index[i].ei_leaf_hi); block = (block << 32) + le32_to_cpu(index[i].ei_leaf_lo); - - if (ext4fs_devread((lbaint_t)block << log2_blksz, 0, blksz, - buf)) - ext_block = (struct ext4_extent_header *)buf; - else - return 0; + block <<= log2_blksz; + if (!ext_cache_read(cache, block, blksz)) + return NULL; + ext_block = (struct ext4_extent_header *)cache->buf; } } @@ -1451,20 +1559,20 @@ static int ext4fs_blockgroup long int blkno; unsigned int blkoff, desc_per_blk; int log2blksz = get_fs()->dev_desc->log2blksz; + int desc_size = get_fs()->gdsize; - desc_per_blk = EXT2_BLOCK_SIZE(data) / sizeof(struct ext2_block_group); + desc_per_blk = EXT2_BLOCK_SIZE(data) / desc_size; - blkno = __le32_to_cpu(data->sblock.first_data_block) + 1 + + blkno = le32_to_cpu(data->sblock.first_data_block) + 1 + group / desc_per_blk; - blkoff = (group % desc_per_blk) * sizeof(struct ext2_block_group); + blkoff = (group % desc_per_blk) * desc_size; debug("ext4fs read %d group descriptor (blkno %ld blkoff %u)\n", group, blkno, blkoff); return ext4fs_devread((lbaint_t)blkno << (LOG2_BLOCK_SIZE(data) - log2blksz), - blkoff, sizeof(struct ext2_block_group), - (char *)blkgrp); + blkoff, desc_size, (char *)blkgrp); } int ext4fs_read_inode(struct ext2_data *data, int ino, struct ext2_inode *inode) @@ -1479,14 +1587,14 @@ int ext4fs_read_inode(struct ext2_data *data, int ino, struct ext2_inode *inode) /* It is easier to calculate if the first inode is 0. */ ino--; - status = ext4fs_blockgroup(data, ino / __le32_to_cpu + status = ext4fs_blockgroup(data, ino / le32_to_cpu (sblock->inodes_per_group), &blkgrp); if (status == 0) return 0; inodes_per_block = EXT2_BLOCK_SIZE(data) / fs->inodesz; - blkno = __le32_to_cpu(blkgrp.inode_table_id) + - (ino % __le32_to_cpu(sblock->inodes_per_group)) / inodes_per_block; + blkno = ext4fs_bg_get_inode_table_id(&blkgrp, fs) + + (ino % le32_to_cpu(sblock->inodes_per_group)) / inodes_per_block; blkoff = (ino % inodes_per_block) * fs->inodesz; /* Read the inode. */ status = ext4fs_devread((lbaint_t)blkno << (LOG2_BLOCK_SIZE(data) - @@ -1498,7 +1606,8 @@ int ext4fs_read_inode(struct ext2_data *data, int ino, struct ext2_inode *inode) return 1; } -long int read_allocated_block(struct ext2_inode *inode, int fileblock) +long int read_allocated_block(struct ext2_inode *inode, int fileblock, + struct ext_block_cache *cache) { long int blknr; int blksz; @@ -1514,20 +1623,25 @@ long int read_allocated_block(struct ext2_inode *inode, int fileblock) - get_fs()->dev_desc->log2blksz; if (le32_to_cpu(inode->flags) & EXT4_EXTENTS_FL) { - char *buf = zalloc(blksz); - if (!buf) - return -ENOMEM; + struct ext_block_cache *c, cd; + if (cache) { + c = cache; + } else { + c = &cd; + ext_cache_init(c); + } struct ext4_extent_header *ext_block; struct ext4_extent *extent; int i = -1; ext_block = - ext4fs_get_extent_block(ext4fs_root, buf, + ext4fs_get_extent_block(ext4fs_root, c, (struct ext4_extent_header *) inode->b.blocks.dir_blocks, fileblock, log2_blksz); if (!ext_block) { printf("invalid extent block\n"); - free(buf); + if (!cache) + ext_cache_fini(c); return -EINVAL; } @@ -1541,25 +1655,28 @@ long int read_allocated_block(struct ext2_inode *inode, int fileblock) if (--i >= 0) { fileblock -= le32_to_cpu(extent[i].ee_block); if (fileblock >= le16_to_cpu(extent[i].ee_len)) { - free(buf); + if (!cache) + ext_cache_fini(c); return 0; } start = le16_to_cpu(extent[i].ee_start_hi); start = (start << 32) + le32_to_cpu(extent[i].ee_start_lo); - free(buf); + if (!cache) + ext_cache_fini(c); return fileblock + start; } printf("Extent Error\n"); - free(buf); + if (!cache) + ext_cache_fini(c); return -1; } /* Direct blocks. */ if (fileblock < INDIRECT_BLOCKS) - blknr = __le32_to_cpu(inode->b.blocks.dir_blocks[fileblock]); + blknr = le32_to_cpu(inode->b.blocks.dir_blocks[fileblock]); /* Indirect. */ else if (fileblock < (INDIRECT_BLOCKS + (blksz / 4))) { @@ -1586,23 +1703,23 @@ long int read_allocated_block(struct ext2_inode *inode, int fileblock) } ext4fs_indir1_size = blksz; } - if ((__le32_to_cpu(inode->b.blocks.indir_block) << + if ((le32_to_cpu(inode->b.blocks.indir_block) << log2_blksz) != ext4fs_indir1_blkno) { status = - ext4fs_devread((lbaint_t)__le32_to_cpu + ext4fs_devread((lbaint_t)le32_to_cpu (inode->b.blocks. indir_block) << log2_blksz, 0, blksz, (char *)ext4fs_indir1_block); if (status == 0) { printf("** SI ext2fs read block (indir 1)" "failed. **\n"); - return 0; + return -1; } ext4fs_indir1_blkno = - __le32_to_cpu(inode->b.blocks. + le32_to_cpu(inode->b.blocks. indir_block) << log2_blksz; } - blknr = __le32_to_cpu(ext4fs_indir1_block + blknr = le32_to_cpu(ext4fs_indir1_block [fileblock - INDIRECT_BLOCKS]); } /* Double indirect. */ @@ -1635,10 +1752,10 @@ long int read_allocated_block(struct ext2_inode *inode, int fileblock) } ext4fs_indir1_size = blksz; } - if ((__le32_to_cpu(inode->b.blocks.double_indir_block) << + if ((le32_to_cpu(inode->b.blocks.double_indir_block) << log2_blksz) != ext4fs_indir1_blkno) { status = - ext4fs_devread((lbaint_t)__le32_to_cpu + ext4fs_devread((lbaint_t)le32_to_cpu (inode->b.blocks. double_indir_block) << log2_blksz, 0, blksz, @@ -1649,7 +1766,7 @@ long int read_allocated_block(struct ext2_inode *inode, int fileblock) return -1; } ext4fs_indir1_blkno = - __le32_to_cpu(inode->b.blocks.double_indir_block) << + le32_to_cpu(inode->b.blocks.double_indir_block) << log2_blksz; } @@ -1676,9 +1793,9 @@ long int read_allocated_block(struct ext2_inode *inode, int fileblock) } ext4fs_indir2_size = blksz; } - if ((__le32_to_cpu(ext4fs_indir1_block[rblock / perblock]) << + if ((le32_to_cpu(ext4fs_indir1_block[rblock / perblock]) << log2_blksz) != ext4fs_indir2_blkno) { - status = ext4fs_devread((lbaint_t)__le32_to_cpu + status = ext4fs_devread((lbaint_t)le32_to_cpu (ext4fs_indir1_block [rblock / perblock]) << log2_blksz, 0, @@ -1690,12 +1807,12 @@ long int read_allocated_block(struct ext2_inode *inode, int fileblock) return -1; } ext4fs_indir2_blkno = - __le32_to_cpu(ext4fs_indir1_block[rblock + le32_to_cpu(ext4fs_indir1_block[rblock / perblock]) << log2_blksz; } - blknr = __le32_to_cpu(ext4fs_indir2_block[rblock % perblock]); + blknr = le32_to_cpu(ext4fs_indir2_block[rblock % perblock]); } /* Tripple indirect. */ else { @@ -1727,11 +1844,11 @@ long int read_allocated_block(struct ext2_inode *inode, int fileblock) } ext4fs_indir1_size = blksz; } - if ((__le32_to_cpu(inode->b.blocks.triple_indir_block) << + if ((le32_to_cpu(inode->b.blocks.triple_indir_block) << log2_blksz) != ext4fs_indir1_blkno) { status = ext4fs_devread ((lbaint_t) - __le32_to_cpu(inode->b.blocks.triple_indir_block) + le32_to_cpu(inode->b.blocks.triple_indir_block) << log2_blksz, 0, blksz, (char *)ext4fs_indir1_block); if (status == 0) { @@ -1740,7 +1857,7 @@ long int read_allocated_block(struct ext2_inode *inode, int fileblock) return -1; } ext4fs_indir1_blkno = - __le32_to_cpu(inode->b.blocks.triple_indir_block) << + le32_to_cpu(inode->b.blocks.triple_indir_block) << log2_blksz; } @@ -1767,11 +1884,11 @@ long int read_allocated_block(struct ext2_inode *inode, int fileblock) } ext4fs_indir2_size = blksz; } - if ((__le32_to_cpu(ext4fs_indir1_block[rblock / + if ((le32_to_cpu(ext4fs_indir1_block[rblock / perblock_parent]) << log2_blksz) != ext4fs_indir2_blkno) { - status = ext4fs_devread((lbaint_t)__le32_to_cpu + status = ext4fs_devread((lbaint_t)le32_to_cpu (ext4fs_indir1_block [rblock / perblock_parent]) << @@ -1783,7 +1900,7 @@ long int read_allocated_block(struct ext2_inode *inode, int fileblock) return -1; } ext4fs_indir2_blkno = - __le32_to_cpu(ext4fs_indir1_block[rblock / + le32_to_cpu(ext4fs_indir1_block[rblock / perblock_parent]) << log2_blksz; } @@ -1811,12 +1928,12 @@ long int read_allocated_block(struct ext2_inode *inode, int fileblock) } ext4fs_indir3_size = blksz; } - if ((__le32_to_cpu(ext4fs_indir2_block[rblock + if ((le32_to_cpu(ext4fs_indir2_block[rblock / perblock_child]) << log2_blksz) != ext4fs_indir3_blkno) { status = - ext4fs_devread((lbaint_t)__le32_to_cpu + ext4fs_devread((lbaint_t)le32_to_cpu (ext4fs_indir2_block [(rblock / perblock_child) % (blksz / 4)]) << log2_blksz, 0, @@ -1827,14 +1944,14 @@ long int read_allocated_block(struct ext2_inode *inode, int fileblock) return -1; } ext4fs_indir3_blkno = - __le32_to_cpu(ext4fs_indir2_block[(rblock / + le32_to_cpu(ext4fs_indir2_block[(rblock / perblock_child) % (blksz / 4)]) << log2_blksz; } - blknr = __le32_to_cpu(ext4fs_indir3_block + blknr = le32_to_cpu(ext4fs_indir3_block [rblock % perblock_child]); } debug("read_allocated_block %ld\n", blknr); @@ -1907,7 +2024,7 @@ int ext4fs_iterate_dir(struct ext2fs_node *dir, char *name, return 0; } /* Search the file. */ - while (fpos < __le32_to_cpu(diro->inode.size)) { + while (fpos < le32_to_cpu(diro->inode.size)) { struct ext2_dirent dirent; status = ext4fs_read_file(diro, fpos, @@ -1939,7 +2056,7 @@ int ext4fs_iterate_dir(struct ext2fs_node *dir, char *name, return 0; fdiro->data = diro->data; - fdiro->ino = __le32_to_cpu(dirent.inode); + fdiro->ino = le32_to_cpu(dirent.inode); filename[dirent.namelen] = '\0'; @@ -1954,7 +2071,7 @@ int ext4fs_iterate_dir(struct ext2fs_node *dir, char *name, type = FILETYPE_REG; } else { status = ext4fs_read_inode(diro->data, - __le32_to_cpu + le32_to_cpu (dirent.inode), &fdiro->inode); if (status == 0) { @@ -1963,15 +2080,15 @@ int ext4fs_iterate_dir(struct ext2fs_node *dir, char *name, } fdiro->inode_read = 1; - if ((__le16_to_cpu(fdiro->inode.mode) & + if ((le16_to_cpu(fdiro->inode.mode) & FILETYPE_INO_MASK) == FILETYPE_INO_DIRECTORY) { type = FILETYPE_DIRECTORY; - } else if ((__le16_to_cpu(fdiro->inode.mode) + } else if ((le16_to_cpu(fdiro->inode.mode) & FILETYPE_INO_MASK) == FILETYPE_INO_SYMLINK) { type = FILETYPE_SYMLINK; - } else if ((__le16_to_cpu(fdiro->inode.mode) + } else if ((le16_to_cpu(fdiro->inode.mode) & FILETYPE_INO_MASK) == FILETYPE_INO_REG) { type = FILETYPE_REG; @@ -1990,7 +2107,7 @@ int ext4fs_iterate_dir(struct ext2fs_node *dir, char *name, } else { if (fdiro->inode_read == 0) { status = ext4fs_read_inode(diro->data, - __le32_to_cpu( + le32_to_cpu( dirent.inode), &fdiro->inode); if (status == 0) { @@ -2014,12 +2131,12 @@ int ext4fs_iterate_dir(struct ext2fs_node *dir, char *name, break; } printf("%10u %s\n", - __le32_to_cpu(fdiro->inode.size), + le32_to_cpu(fdiro->inode.size), filename); } free(fdiro); } - fpos += __le16_to_cpu(dirent.direntlen); + fpos += le16_to_cpu(dirent.direntlen); } return 0; } @@ -2034,25 +2151,25 @@ static char *ext4fs_read_symlink(struct ext2fs_node *node) if (!diro->inode_read) { status = ext4fs_read_inode(diro->data, diro->ino, &diro->inode); if (status == 0) - return 0; + return NULL; } - symlink = zalloc(__le32_to_cpu(diro->inode.size) + 1); + symlink = zalloc(le32_to_cpu(diro->inode.size) + 1); if (!symlink) - return 0; + return NULL; - if (__le32_to_cpu(diro->inode.size) < sizeof(diro->inode.b.symlink)) { + if (le32_to_cpu(diro->inode.size) < sizeof(diro->inode.b.symlink)) { strncpy(symlink, diro->inode.b.symlink, - __le32_to_cpu(diro->inode.size)); + le32_to_cpu(diro->inode.size)); } else { status = ext4fs_read_file(diro, 0, - __le32_to_cpu(diro->inode.size), + le32_to_cpu(diro->inode.size), symlink, &actread); if ((status < 0) || (actread == 0)) { free(symlink); - return 0; + return NULL; } } - symlink[__le32_to_cpu(diro->inode.size)] = '\0'; + symlink[le32_to_cpu(diro->inode.size)] = '\0'; return symlink; } @@ -2200,7 +2317,7 @@ int ext4fs_open(const char *filename, loff_t *len) if (status == 0) goto fail; } - *len = __le32_to_cpu(fdiro->inode.size); + *len = le32_to_cpu(fdiro->inode.size); ext4fs_file = fdiro; return 0; @@ -2226,16 +2343,27 @@ int ext4fs_mount(unsigned part_length) goto fail; /* Make sure this is an ext2 filesystem. */ - if (__le16_to_cpu(data->sblock.magic) != EXT2_MAGIC) + if (le16_to_cpu(data->sblock.magic) != EXT2_MAGIC) goto fail; - if (__le32_to_cpu(data->sblock.revision_level == 0)) + + if (le32_to_cpu(data->sblock.revision_level) == 0) { fs->inodesz = 128; - else - fs->inodesz = __le16_to_cpu(data->sblock.inode_size); + } else { + debug("EXT4 features COMPAT: %08x INCOMPAT: %08x RO_COMPAT: %08x\n", + __le32_to_cpu(data->sblock.feature_compatibility), + __le32_to_cpu(data->sblock.feature_incompat), + __le32_to_cpu(data->sblock.feature_ro_compat)); + + fs->inodesz = le16_to_cpu(data->sblock.inode_size); + fs->gdsize = le32_to_cpu(data->sblock.feature_incompat) & + EXT4_FEATURE_INCOMPAT_64BIT ? + le16_to_cpu(data->sblock.descriptor_size) : 32; + } - debug("EXT2 rev %d, inode_size %d\n", - __le32_to_cpu(data->sblock.revision_level), fs->inodesz); + debug("EXT2 rev %d, inode_size %d, descriptor size %d\n", + le32_to_cpu(data->sblock.revision_level), + fs->inodesz, fs->gdsize); data->diropen.data = data; data->diropen.ino = 2; diff --git a/fs/ext4/ext4_common.h b/fs/ext4/ext4_common.h index 48fd2ac51dbb..99d49e6e5583 100644 --- a/fs/ext4/ext4_common.h +++ b/fs/ext4/ext4_common.h @@ -59,10 +59,10 @@ int ext4fs_iterate_dir(struct ext2fs_node *dir, char *name, #if defined(CONFIG_EXT4_WRITE) uint32_t ext4fs_div_roundup(uint32_t size, uint32_t n); -int ext4fs_checksum_update(unsigned int i); +uint16_t ext4fs_checksum_update(unsigned int i); int ext4fs_get_parent_inode_num(const char *dirname, char *dname, int flags); -void ext4fs_update_parent_dentry(char *filename, int *p_ino, int file_type); -long int ext4fs_get_new_blk_no(void); +int ext4fs_update_parent_dentry(char *filename, int file_type); +uint32_t ext4fs_get_new_blk_no(void); int ext4fs_get_new_inode_no(void); void ext4fs_reset_block_bmap(long int blockno, unsigned char *buffer, int index); @@ -74,5 +74,17 @@ void ext4fs_allocate_blocks(struct ext2_inode *file_inode, unsigned int total_remaining_blocks, unsigned int *total_no_of_block); void put_ext4(uint64_t off, void *buf, uint32_t size); +struct ext2_block_group *ext4fs_get_group_descriptor + (const struct ext_filesystem *fs, uint32_t bg_idx); +uint64_t ext4fs_bg_get_block_id(const struct ext2_block_group *bg, + const struct ext_filesystem *fs); +uint64_t ext4fs_bg_get_inode_id(const struct ext2_block_group *bg, + const struct ext_filesystem *fs); +uint64_t ext4fs_bg_get_inode_table_id(const struct ext2_block_group *bg, + const struct ext_filesystem *fs); +uint64_t ext4fs_sb_get_free_blocks(const struct ext2_sblock *sb); +void ext4fs_sb_set_free_blocks(struct ext2_sblock *sb, uint64_t free_blocks); +uint32_t ext4fs_bg_get_free_blocks(const struct ext2_block_group *bg, + const struct ext_filesystem *fs); #endif #endif diff --git a/fs/ext4/ext4_journal.c b/fs/ext4/ext4_journal.c index 3f613351a432..b40916b42121 100644 --- a/fs/ext4/ext4_journal.c +++ b/fs/ext4/ext4_journal.c @@ -151,7 +151,7 @@ int ext4fs_log_gdt(char *gd_table) * journal_buffer -- Buffer containing meta data * blknr -- Block number on disk of the meta data buffer */ -int ext4fs_log_journal(char *journal_buffer, long int blknr) +int ext4fs_log_journal(char *journal_buffer, uint32_t blknr) { struct ext_filesystem *fs = get_fs(); short i; @@ -183,14 +183,18 @@ int ext4fs_log_journal(char *journal_buffer, long int blknr) * metadata_buffer -- Buffer containing meta data * blknr -- Block number on disk of the meta data buffer */ -int ext4fs_put_metadata(char *metadata_buffer, long int blknr) +int ext4fs_put_metadata(char *metadata_buffer, uint32_t blknr) { struct ext_filesystem *fs = get_fs(); if (!metadata_buffer) { printf("Invalid input arguments %s\n", __func__); return -EINVAL; } - dirty_block_ptr[gd_index]->buf = zalloc(fs->blksz); + if (dirty_block_ptr[gd_index]->buf) + assert(dirty_block_ptr[gd_index]->blknr == blknr); + else + dirty_block_ptr[gd_index]->buf = zalloc(fs->blksz); + if (!dirty_block_ptr[gd_index]->buf) return -ENOMEM; memcpy(dirty_block_ptr[gd_index]->buf, metadata_buffer, fs->blksz); @@ -215,7 +219,7 @@ void print_revoke_blks(char *revk_blk) printf("total bytes %d\n", max); while (offset < max) { - blocknr = be32_to_cpu(*((long int *)(revk_blk + offset))); + blocknr = be32_to_cpu(*((__be32 *)(revk_blk + offset))); printf("revoke blknr is %ld\n", blocknr); offset += 4; } @@ -302,7 +306,7 @@ int check_blknr_for_revoke(long int blknr, int sequence_no) max = be32_to_cpu(header->r_count); while (offset < max) { - blocknr = be32_to_cpu(*((long int *) + blocknr = be32_to_cpu(*((__be32 *) (revk_blk + offset))); if (blocknr == blknr) goto found; @@ -343,7 +347,7 @@ void recover_transaction(int prev_desc_logical_no) ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO, (struct ext2_inode *)&inode_journal); blknr = read_allocated_block((struct ext2_inode *) - &inode_journal, i); + &inode_journal, i, NULL); ext4fs_devread((lbaint_t)blknr * fs->sect_perblk, 0, fs->blksz, temp_buff); p_jdb = (char *)temp_buff; @@ -368,7 +372,7 @@ void recover_transaction(int prev_desc_logical_no) be32_to_cpu(jdb->h_sequence)) == 0) continue; } - blknr = read_allocated_block(&inode_journal, i); + blknr = read_allocated_block(&inode_journal, i, NULL); ext4fs_devread((lbaint_t)blknr * fs->sect_perblk, 0, fs->blksz, metadata_buff); put_ext4((uint64_t)((uint64_t)be32_to_cpu(tag->block) * (uint64_t)fs->blksz), @@ -415,12 +419,12 @@ int ext4fs_check_journal_state(int recovery_flag) } ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO, &inode_journal); - blknr = read_allocated_block(&inode_journal, EXT2_JOURNAL_SUPERBLOCK); + blknr = read_allocated_block(&inode_journal, EXT2_JOURNAL_SUPERBLOCK, NULL); ext4fs_devread((lbaint_t)blknr * fs->sect_perblk, 0, fs->blksz, temp_buff); jsb = (struct journal_superblock_t *) temp_buff; - if (fs->sb->feature_incompat & EXT3_FEATURE_INCOMPAT_RECOVER) { + if (le32_to_cpu(fs->sb->feature_incompat) & EXT3_FEATURE_INCOMPAT_RECOVER) { if (recovery_flag == RECOVER) printf("Recovery required\n"); } else { @@ -439,7 +443,7 @@ int ext4fs_check_journal_state(int recovery_flag) i = be32_to_cpu(jsb->s_first); while (1) { - blknr = read_allocated_block(&inode_journal, i); + blknr = read_allocated_block(&inode_journal, i, NULL); memset(temp_buff1, '\0', fs->blksz); ext4fs_devread((lbaint_t)blknr * fs->sect_perblk, 0, fs->blksz, temp_buff1); @@ -517,11 +521,14 @@ int ext4fs_check_journal_state(int recovery_flag) end: if (recovery_flag == RECOVER) { + uint32_t new_feature_incompat; jsb->s_start = cpu_to_be32(1); jsb->s_sequence = cpu_to_be32(be32_to_cpu(jsb->s_sequence) + 1); /* get the superblock */ ext4_read_superblock((char *)fs->sb); - fs->sb->feature_incompat |= EXT3_FEATURE_INCOMPAT_RECOVER; + new_feature_incompat = le32_to_cpu(fs->sb->feature_incompat); + new_feature_incompat |= EXT3_FEATURE_INCOMPAT_RECOVER; + fs->sb->feature_incompat = cpu_to_le32(new_feature_incompat); /* Update the super block */ put_ext4((uint64_t) (SUPERBLOCK_SIZE), @@ -530,7 +537,7 @@ int ext4fs_check_journal_state(int recovery_flag) ext4_read_superblock((char *)fs->sb); blknr = read_allocated_block(&inode_journal, - EXT2_JOURNAL_SUPERBLOCK); + EXT2_JOURNAL_SUPERBLOCK, NULL); put_ext4((uint64_t) ((uint64_t)blknr * (uint64_t)fs->blksz), (struct journal_superblock_t *)temp_buff, (uint32_t) fs->blksz); @@ -559,7 +566,7 @@ static void update_descriptor_block(long int blknr) ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO, &inode_journal); jsb_blknr = read_allocated_block(&inode_journal, - EXT2_JOURNAL_SUPERBLOCK); + EXT2_JOURNAL_SUPERBLOCK, NULL); ext4fs_devread((lbaint_t)jsb_blknr * fs->sect_perblk, 0, fs->blksz, temp_buff); jsb = (struct journal_superblock_t *) temp_buff; @@ -611,7 +618,7 @@ static void update_commit_block(long int blknr) ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO, &inode_journal); jsb_blknr = read_allocated_block(&inode_journal, - EXT2_JOURNAL_SUPERBLOCK); + EXT2_JOURNAL_SUPERBLOCK, NULL); ext4fs_devread((lbaint_t)jsb_blknr * fs->sect_perblk, 0, fs->blksz, temp_buff); jsb = (struct journal_superblock_t *) temp_buff; @@ -638,16 +645,16 @@ void ext4fs_update_journal(void) long int blknr; int i; ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO, &inode_journal); - blknr = read_allocated_block(&inode_journal, jrnl_blk_idx++); + blknr = read_allocated_block(&inode_journal, jrnl_blk_idx++, NULL); update_descriptor_block(blknr); for (i = 0; i < MAX_JOURNAL_ENTRIES; i++) { if (journal_ptr[i]->blknr == -1) break; - blknr = read_allocated_block(&inode_journal, jrnl_blk_idx++); + blknr = read_allocated_block(&inode_journal, jrnl_blk_idx++, NULL); put_ext4((uint64_t) ((uint64_t)blknr * (uint64_t)fs->blksz), journal_ptr[i]->buf, fs->blksz); } - blknr = read_allocated_block(&inode_journal, jrnl_blk_idx++); + blknr = read_allocated_block(&inode_journal, jrnl_blk_idx++, NULL); update_commit_block(blknr); printf("update journal finished\n"); } diff --git a/fs/ext4/ext4_journal.h b/fs/ext4/ext4_journal.h index d926094becdf..3d05ad531546 100644 --- a/fs/ext4/ext4_journal.h +++ b/fs/ext4/ext4_journal.h @@ -49,9 +49,9 @@ struct dirty_blocks { /* Standard header for all descriptor blocks: */ struct journal_header_t { - __u32 h_magic; - __u32 h_blocktype; - __u32 h_sequence; + __be32 h_magic; + __be32 h_blocktype; + __be32 h_sequence; }; /* The journal superblock. All fields are in big-endian byte order. */ @@ -60,35 +60,35 @@ struct journal_superblock_t { struct journal_header_t s_header; /* Static information describing the journal */ - __u32 s_blocksize; /* journal device blocksize */ - __u32 s_maxlen; /* total blocks in journal file */ - __u32 s_first; /* first block of log information */ + __be32 s_blocksize; /* journal device blocksize */ + __be32 s_maxlen; /* total blocks in journal file */ + __be32 s_first; /* first block of log information */ /* Dynamic information describing the current state of the log */ - __u32 s_sequence; /* first commit ID expected in log */ - __u32 s_start; /* blocknr of start of log */ + __be32 s_sequence; /* first commit ID expected in log */ + __be32 s_start; /* blocknr of start of log */ /* Error value, as set by journal_abort(). */ - __s32 s_errno; + __be32 s_errno; /* Remaining fields are only valid in a version-2 superblock */ - __u32 s_feature_compat; /* compatible feature set */ - __u32 s_feature_incompat; /* incompatible feature set */ - __u32 s_feature_ro_compat; /* readonly-compatible feature set */ + __be32 s_feature_compat; /* compatible feature set */ + __be32 s_feature_incompat; /* incompatible feature set */ + __be32 s_feature_ro_compat; /* readonly-compatible feature set */ /* 0x0030 */ __u8 s_uuid[16]; /* 128-bit uuid for journal */ /* 0x0040 */ - __u32 s_nr_users; /* Nr of filesystems sharing log */ + __be32 s_nr_users; /* Nr of filesystems sharing log */ - __u32 s_dynsuper; /* Blocknr of dynamic superblock copy */ + __be32 s_dynsuper; /* Blocknr of dynamic superblock copy */ /* 0x0048 */ - __u32 s_max_transaction; /* Limit of journal blocks per trans. */ - __u32 s_max_trans_data; /* Limit of data blocks per trans. */ + __be32 s_max_transaction; /* Limit of journal blocks per trans. */ + __be32 s_max_trans_data; /* Limit of data blocks per trans. */ /* 0x0050 */ - __u32 s_padding[44]; + __be32 s_padding[44]; /* 0x0100 */ __u8 s_users[16 * 48]; /* ids of all fs'es sharing the log */ @@ -96,13 +96,13 @@ struct journal_superblock_t { } ; struct ext3_journal_block_tag { - uint32_t block; - uint32_t flags; + __be32 block; + __be32 flags; }; struct journal_revoke_header_t { struct journal_header_t r_header; - int r_count; /* Count of bytes used in the block */ + __be32 r_count; /* Count of bytes used in the block */ }; struct revoke_blk_list { @@ -115,8 +115,8 @@ extern struct ext2_data *ext4fs_root; int ext4fs_init_journal(void); int ext4fs_log_gdt(char *gd_table); int ext4fs_check_journal_state(int recovery_flag); -int ext4fs_log_journal(char *journal_buffer, long int blknr); -int ext4fs_put_metadata(char *metadata_buffer, long int blknr); +int ext4fs_log_journal(char *journal_buffer, uint32_t blknr); +int ext4fs_put_metadata(char *metadata_buffer, uint32_t blknr); void ext4fs_update_journal(void); void ext4fs_dump_metadata(void); void ext4fs_push_revoke_blk(char *buffer); diff --git a/fs/ext4/ext4_write.c b/fs/ext4/ext4_write.c index e027916763f9..d7a25db6195c 100644 --- a/fs/ext4/ext4_write.c +++ b/fs/ext4/ext4_write.c @@ -28,26 +28,67 @@ #include #include "ext4_common.h" +static inline void ext4fs_sb_free_inodes_inc(struct ext2_sblock *sb) +{ + sb->free_inodes = cpu_to_le32(le32_to_cpu(sb->free_inodes) + 1); +} + +static inline void ext4fs_sb_free_blocks_inc(struct ext2_sblock *sb) +{ + sb->free_blocks = cpu_to_le32(le32_to_cpu(sb->free_blocks) + 1); +} + +static inline void ext4fs_bg_free_inodes_inc + (struct ext2_block_group *bg, const struct ext_filesystem *fs) +{ + uint32_t free_inodes = le16_to_cpu(bg->free_inodes); + if (fs->gdsize == 64) + free_inodes += le16_to_cpu(bg->free_inodes_high) << 16; + free_inodes++; + + bg->free_inodes = cpu_to_le16(free_inodes & 0xffff); + if (fs->gdsize == 64) + bg->free_inodes_high = cpu_to_le16(free_inodes >> 16); +} + +static inline void ext4fs_bg_free_blocks_inc + (struct ext2_block_group *bg, const struct ext_filesystem *fs) +{ + uint32_t free_blocks = le16_to_cpu(bg->free_blocks); + if (fs->gdsize == 64) + free_blocks += le16_to_cpu(bg->free_blocks_high) << 16; + free_blocks++; + + bg->free_blocks = cpu_to_le16(free_blocks & 0xffff); + if (fs->gdsize == 64) + bg->free_blocks_high = cpu_to_le16(free_blocks >> 16); +} + static void ext4fs_update(void) { short i; ext4fs_update_journal(); struct ext_filesystem *fs = get_fs(); + struct ext2_block_group *bgd = NULL; /* update super block */ put_ext4((uint64_t)(SUPERBLOCK_SIZE), (struct ext2_sblock *)fs->sb, (uint32_t)SUPERBLOCK_SIZE); - /* update block groups */ + /* update block bitmaps */ for (i = 0; i < fs->no_blkgrp; i++) { - fs->bgd[i].bg_checksum = ext4fs_checksum_update(i); - put_ext4((uint64_t)((uint64_t)fs->bgd[i].block_id * (uint64_t)fs->blksz), + bgd = ext4fs_get_group_descriptor(fs, i); + bgd->bg_checksum = cpu_to_le16(ext4fs_checksum_update(i)); + uint64_t b_bitmap_blk = ext4fs_bg_get_block_id(bgd, fs); + put_ext4(b_bitmap_blk * fs->blksz, fs->blk_bmaps[i], fs->blksz); } - /* update inode table groups */ + /* update inode bitmaps */ for (i = 0; i < fs->no_blkgrp; i++) { - put_ext4((uint64_t) ((uint64_t)fs->bgd[i].inode_id * (uint64_t)fs->blksz), + bgd = ext4fs_get_group_descriptor(fs, i); + uint64_t i_bitmap_blk = ext4fs_bg_get_inode_id(bgd, fs); + put_ext4(i_bitmap_blk * fs->blksz, fs->inode_bmaps[i], fs->blksz); } @@ -65,15 +106,12 @@ static void ext4fs_update(void) int ext4fs_get_bgdtable(void) { int status; - int grp_desc_size; struct ext_filesystem *fs = get_fs(); - grp_desc_size = sizeof(struct ext2_block_group); - fs->no_blk_pergdt = (fs->no_blkgrp * grp_desc_size) / fs->blksz; - if ((fs->no_blkgrp * grp_desc_size) % fs->blksz) - fs->no_blk_pergdt++; + int gdsize_total = ROUND(fs->no_blkgrp * fs->gdsize, fs->blksz); + fs->no_blk_pergdt = gdsize_total / fs->blksz; /* allocate memory for gdtable */ - fs->gdtable = zalloc(fs->blksz * fs->no_blk_pergdt); + fs->gdtable = zalloc(gdsize_total); if (!fs->gdtable) return -ENOMEM; /* read the group descriptor table */ @@ -99,24 +137,22 @@ static void delete_single_indirect_block(struct ext2_inode *inode) { struct ext2_block_group *bgd = NULL; static int prev_bg_bmap_idx = -1; - long int blknr; + uint32_t blknr; int remainder; int bg_idx; int status; - unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group; + uint32_t blk_per_grp = le32_to_cpu(ext4fs_root->sblock.blocks_per_group); struct ext_filesystem *fs = get_fs(); char *journal_buffer = zalloc(fs->blksz); if (!journal_buffer) { printf("No memory\n"); return; } - /* get block group descriptor table */ - bgd = (struct ext2_block_group *)fs->gdtable; /* deleting the single indirect block associated with inode */ if (inode->b.blocks.indir_block != 0) { - debug("SIPB releasing %u\n", inode->b.blocks.indir_block); - blknr = inode->b.blocks.indir_block; + blknr = le32_to_cpu(inode->b.blocks.indir_block); + debug("SIPB releasing %u\n", blknr); bg_idx = blknr / blk_per_grp; if (fs->blksz == 1024) { remainder = blknr % blk_per_grp; @@ -124,18 +160,19 @@ static void delete_single_indirect_block(struct ext2_inode *inode) bg_idx--; } ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], bg_idx); - bgd[bg_idx].free_blocks++; - fs->sb->free_blocks++; + /* get block group descriptor table */ + bgd = ext4fs_get_group_descriptor(fs, bg_idx); + ext4fs_bg_free_blocks_inc(bgd, fs); + ext4fs_sb_free_blocks_inc(fs->sb); /* journal backup */ if (prev_bg_bmap_idx != bg_idx) { - status = - ext4fs_devread((lbaint_t)bgd[bg_idx].block_id * - fs->sect_perblk, 0, fs->blksz, - journal_buffer); + uint64_t b_bitmap_blk = ext4fs_bg_get_block_id(bgd, fs); + status = ext4fs_devread( + b_bitmap_blk * fs->sect_perblk, + 0, fs->blksz, journal_buffer); if (status == 0) goto fail; - if (ext4fs_log_journal - (journal_buffer, bgd[bg_idx].block_id)) + if (ext4fs_log_journal(journal_buffer, b_bitmap_blk)) goto fail; prev_bg_bmap_idx = bg_idx; } @@ -149,12 +186,12 @@ static void delete_double_indirect_block(struct ext2_inode *inode) int i; short status; static int prev_bg_bmap_idx = -1; - long int blknr; + uint32_t blknr; int remainder; int bg_idx; - unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group; - unsigned int *di_buffer = NULL; - unsigned int *DIB_start_addr = NULL; + uint32_t blk_per_grp = le32_to_cpu(ext4fs_root->sblock.blocks_per_group); + __le32 *di_buffer = NULL; + void *dib_start_addr = NULL; struct ext2_block_group *bgd = NULL; struct ext_filesystem *fs = get_fs(); char *journal_buffer = zalloc(fs->blksz); @@ -162,8 +199,6 @@ static void delete_double_indirect_block(struct ext2_inode *inode) printf("No memory\n"); return; } - /* get the block group descriptor table */ - bgd = (struct ext2_block_group *)fs->gdtable; if (inode->b.blocks.double_indir_block != 0) { di_buffer = zalloc(fs->blksz); @@ -171,8 +206,8 @@ static void delete_double_indirect_block(struct ext2_inode *inode) printf("No memory\n"); return; } - DIB_start_addr = (unsigned int *)di_buffer; - blknr = inode->b.blocks.double_indir_block; + dib_start_addr = di_buffer; + blknr = le32_to_cpu(inode->b.blocks.double_indir_block); status = ext4fs_devread((lbaint_t)blknr * fs->sect_perblk, 0, fs->blksz, (char *)di_buffer); for (i = 0; i < fs->blksz / sizeof(int); i++) { @@ -180,21 +215,24 @@ static void delete_double_indirect_block(struct ext2_inode *inode) break; debug("DICB releasing %u\n", *di_buffer); - bg_idx = *di_buffer / blk_per_grp; + bg_idx = le32_to_cpu(*di_buffer) / blk_per_grp; if (fs->blksz == 1024) { - remainder = *di_buffer % blk_per_grp; + remainder = le32_to_cpu(*di_buffer) % blk_per_grp; if (!remainder) bg_idx--; } - ext4fs_reset_block_bmap(*di_buffer, + /* get block group descriptor table */ + bgd = ext4fs_get_group_descriptor(fs, bg_idx); + ext4fs_reset_block_bmap(le32_to_cpu(*di_buffer), fs->blk_bmaps[bg_idx], bg_idx); di_buffer++; - bgd[bg_idx].free_blocks++; - fs->sb->free_blocks++; + ext4fs_bg_free_blocks_inc(bgd, fs); + ext4fs_sb_free_blocks_inc(fs->sb); /* journal backup */ if (prev_bg_bmap_idx != bg_idx) { - status = ext4fs_devread((lbaint_t) - bgd[bg_idx].block_id + uint64_t b_bitmap_blk = + ext4fs_bg_get_block_id(bgd, fs); + status = ext4fs_devread(b_bitmap_blk * fs->sect_perblk, 0, fs->blksz, journal_buffer); @@ -202,41 +240,41 @@ static void delete_double_indirect_block(struct ext2_inode *inode) goto fail; if (ext4fs_log_journal(journal_buffer, - bgd[bg_idx].block_id)) + b_bitmap_blk)) goto fail; prev_bg_bmap_idx = bg_idx; } } /* removing the parent double indirect block */ - blknr = inode->b.blocks.double_indir_block; + blknr = le32_to_cpu(inode->b.blocks.double_indir_block); bg_idx = blknr / blk_per_grp; if (fs->blksz == 1024) { remainder = blknr % blk_per_grp; if (!remainder) bg_idx--; } + /* get block group descriptor table */ + bgd = ext4fs_get_group_descriptor(fs, bg_idx); ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], bg_idx); - bgd[bg_idx].free_blocks++; - fs->sb->free_blocks++; + ext4fs_bg_free_blocks_inc(bgd, fs); + ext4fs_sb_free_blocks_inc(fs->sb); /* journal backup */ if (prev_bg_bmap_idx != bg_idx) { - memset(journal_buffer, '\0', fs->blksz); - status = ext4fs_devread((lbaint_t)bgd[bg_idx].block_id * - fs->sect_perblk, 0, fs->blksz, - journal_buffer); + uint64_t b_bitmap_blk = ext4fs_bg_get_block_id(bgd, fs); + status = ext4fs_devread(b_bitmap_blk * fs->sect_perblk, + 0, fs->blksz, journal_buffer); if (status == 0) goto fail; - if (ext4fs_log_journal(journal_buffer, - bgd[bg_idx].block_id)) + if (ext4fs_log_journal(journal_buffer, b_bitmap_blk)) goto fail; prev_bg_bmap_idx = bg_idx; } - debug("DIPB releasing %ld\n", blknr); + debug("DIPB releasing %d\n", blknr); } fail: - free(DIB_start_addr); + free(dib_start_addr); free(journal_buffer); } @@ -245,14 +283,14 @@ static void delete_triple_indirect_block(struct ext2_inode *inode) int i, j; short status; static int prev_bg_bmap_idx = -1; - long int blknr; + uint32_t blknr; int remainder; int bg_idx; - unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group; - unsigned int *tigp_buffer = NULL; - unsigned int *tib_start_addr = NULL; - unsigned int *tip_buffer = NULL; - unsigned int *tipb_start_addr = NULL; + uint32_t blk_per_grp = le32_to_cpu(ext4fs_root->sblock.blocks_per_group); + __le32 *tigp_buffer = NULL; + void *tib_start_addr = NULL; + __le32 *tip_buffer = NULL; + void *tipb_start_addr = NULL; struct ext2_block_group *bgd = NULL; struct ext_filesystem *fs = get_fs(); char *journal_buffer = zalloc(fs->blksz); @@ -260,8 +298,6 @@ static void delete_triple_indirect_block(struct ext2_inode *inode) printf("No memory\n"); return; } - /* get block group descriptor table */ - bgd = (struct ext2_block_group *)fs->gdtable; if (inode->b.blocks.triple_indir_block != 0) { tigp_buffer = zalloc(fs->blksz); @@ -269,8 +305,8 @@ static void delete_triple_indirect_block(struct ext2_inode *inode) printf("No memory\n"); return; } - tib_start_addr = (unsigned int *)tigp_buffer; - blknr = inode->b.blocks.triple_indir_block; + tib_start_addr = tigp_buffer; + blknr = le32_to_cpu(inode->b.blocks.triple_indir_block); status = ext4fs_devread((lbaint_t)blknr * fs->sect_perblk, 0, fs->blksz, (char *)tigp_buffer); for (i = 0; i < fs->blksz / sizeof(int); i++) { @@ -281,33 +317,36 @@ static void delete_triple_indirect_block(struct ext2_inode *inode) tip_buffer = zalloc(fs->blksz); if (!tip_buffer) goto fail; - tipb_start_addr = (unsigned int *)tip_buffer; - status = ext4fs_devread((lbaint_t)(*tigp_buffer) * + tipb_start_addr = tip_buffer; + status = ext4fs_devread((lbaint_t)le32_to_cpu(*tigp_buffer) * fs->sect_perblk, 0, fs->blksz, (char *)tip_buffer); for (j = 0; j < fs->blksz / sizeof(int); j++) { - if (*tip_buffer == 0) + if (le32_to_cpu(*tip_buffer) == 0) break; - bg_idx = *tip_buffer / blk_per_grp; + bg_idx = le32_to_cpu(*tip_buffer) / blk_per_grp; if (fs->blksz == 1024) { - remainder = *tip_buffer % blk_per_grp; + remainder = le32_to_cpu(*tip_buffer) % blk_per_grp; if (!remainder) bg_idx--; } - ext4fs_reset_block_bmap(*tip_buffer, + ext4fs_reset_block_bmap(le32_to_cpu(*tip_buffer), fs->blk_bmaps[bg_idx], bg_idx); tip_buffer++; - bgd[bg_idx].free_blocks++; - fs->sb->free_blocks++; + /* get block group descriptor table */ + bgd = ext4fs_get_group_descriptor(fs, bg_idx); + ext4fs_bg_free_blocks_inc(bgd, fs); + ext4fs_sb_free_blocks_inc(fs->sb); /* journal backup */ if (prev_bg_bmap_idx != bg_idx) { + uint64_t b_bitmap_blk = + ext4fs_bg_get_block_id(bgd, fs); status = ext4fs_devread( - (lbaint_t) - bgd[bg_idx].block_id * + b_bitmap_blk * fs->sect_perblk, 0, fs->blksz, journal_buffer); @@ -315,8 +354,7 @@ static void delete_triple_indirect_block(struct ext2_inode *inode) goto fail; if (ext4fs_log_journal(journal_buffer, - bgd[bg_idx]. - block_id)) + b_bitmap_blk)) goto fail; prev_bg_bmap_idx = bg_idx; } @@ -328,38 +366,41 @@ static void delete_triple_indirect_block(struct ext2_inode *inode) * removing the grand parent blocks * which is connected to inode */ - bg_idx = *tigp_buffer / blk_per_grp; + bg_idx = le32_to_cpu(*tigp_buffer) / blk_per_grp; if (fs->blksz == 1024) { - remainder = *tigp_buffer % blk_per_grp; + remainder = le32_to_cpu(*tigp_buffer) % blk_per_grp; if (!remainder) bg_idx--; } - ext4fs_reset_block_bmap(*tigp_buffer, + ext4fs_reset_block_bmap(le32_to_cpu(*tigp_buffer), fs->blk_bmaps[bg_idx], bg_idx); tigp_buffer++; - bgd[bg_idx].free_blocks++; - fs->sb->free_blocks++; + /* get block group descriptor table */ + bgd = ext4fs_get_group_descriptor(fs, bg_idx); + ext4fs_bg_free_blocks_inc(bgd, fs); + ext4fs_sb_free_blocks_inc(fs->sb); /* journal backup */ if (prev_bg_bmap_idx != bg_idx) { + uint64_t b_bitmap_blk = + ext4fs_bg_get_block_id(bgd, fs); memset(journal_buffer, '\0', fs->blksz); - status = - ext4fs_devread((lbaint_t) - bgd[bg_idx].block_id * - fs->sect_perblk, 0, - fs->blksz, journal_buffer); + status = ext4fs_devread(b_bitmap_blk * + fs->sect_perblk, 0, + fs->blksz, + journal_buffer); if (status == 0) goto fail; if (ext4fs_log_journal(journal_buffer, - bgd[bg_idx].block_id)) + b_bitmap_blk)) goto fail; prev_bg_bmap_idx = bg_idx; } } /* removing the grand parent triple indirect block */ - blknr = inode->b.blocks.triple_indir_block; + blknr = le32_to_cpu(inode->b.blocks.triple_indir_block); bg_idx = blknr / blk_per_grp; if (fs->blksz == 1024) { remainder = blknr % blk_per_grp; @@ -367,23 +408,23 @@ static void delete_triple_indirect_block(struct ext2_inode *inode) bg_idx--; } ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], bg_idx); - bgd[bg_idx].free_blocks++; - fs->sb->free_blocks++; + /* get block group descriptor table */ + bgd = ext4fs_get_group_descriptor(fs, bg_idx); + ext4fs_bg_free_blocks_inc(bgd, fs); + ext4fs_sb_free_blocks_inc(fs->sb); /* journal backup */ if (prev_bg_bmap_idx != bg_idx) { - memset(journal_buffer, '\0', fs->blksz); - status = ext4fs_devread((lbaint_t)bgd[bg_idx].block_id * - fs->sect_perblk, 0, fs->blksz, - journal_buffer); + uint64_t b_bitmap_blk = ext4fs_bg_get_block_id(bgd, fs); + status = ext4fs_devread(b_bitmap_blk * fs->sect_perblk, + 0, fs->blksz, journal_buffer); if (status == 0) goto fail; - if (ext4fs_log_journal(journal_buffer, - bgd[bg_idx].block_id)) + if (ext4fs_log_journal(journal_buffer, b_bitmap_blk)) goto fail; prev_bg_bmap_idx = bg_idx; } - debug("tigp buffer itself releasing %ld\n", blknr); + debug("tigp buffer itself releasing %d\n", blknr); } fail: free(tib_start_addr); @@ -402,126 +443,87 @@ static int ext4fs_delete_file(int inodeno) int ibmap_idx; char *read_buffer = NULL; char *start_block_address = NULL; - unsigned int no_blocks; + uint32_t no_blocks; static int prev_bg_bmap_idx = -1; unsigned int inodes_per_block; - long int blkno; + uint32_t blkno; unsigned int blkoff; - unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group; - unsigned int inode_per_grp = ext4fs_root->sblock.inodes_per_group; + uint32_t blk_per_grp = le32_to_cpu(ext4fs_root->sblock.blocks_per_group); + uint32_t inode_per_grp = le32_to_cpu(ext4fs_root->sblock.inodes_per_group); struct ext2_inode *inode_buffer = NULL; struct ext2_block_group *bgd = NULL; struct ext_filesystem *fs = get_fs(); char *journal_buffer = zalloc(fs->blksz); if (!journal_buffer) return -ENOMEM; - /* get the block group descriptor table */ - bgd = (struct ext2_block_group *)fs->gdtable; status = ext4fs_read_inode(ext4fs_root, inodeno, &inode); if (status == 0) goto fail; /* read the block no allocated to a file */ - no_blocks = inode.size / fs->blksz; - if (inode.size % fs->blksz) + no_blocks = le32_to_cpu(inode.size) / fs->blksz; + if (le32_to_cpu(inode.size) % fs->blksz) no_blocks++; if (le32_to_cpu(inode.flags) & EXT4_EXTENTS_FL) { - struct ext2fs_node *node_inode = - zalloc(sizeof(struct ext2fs_node)); - if (!node_inode) - goto fail; - node_inode->data = ext4fs_root; - node_inode->ino = inodeno; - node_inode->inode_read = 0; - memcpy(&(node_inode->inode), &inode, sizeof(struct ext2_inode)); - - for (i = 0; i < no_blocks; i++) { - blknr = read_allocated_block(&(node_inode->inode), i); - bg_idx = blknr / blk_per_grp; - if (fs->blksz == 1024) { - remainder = blknr % blk_per_grp; - if (!remainder) - bg_idx--; - } - ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], - bg_idx); - debug("EXT4_EXTENTS Block releasing %ld: %d\n", - blknr, bg_idx); - - bgd[bg_idx].free_blocks++; - fs->sb->free_blocks++; - - /* journal backup */ - if (prev_bg_bmap_idx != bg_idx) { - status = - ext4fs_devread((lbaint_t) - bgd[bg_idx].block_id * - fs->sect_perblk, 0, - fs->blksz, journal_buffer); - if (status == 0) - goto fail; - if (ext4fs_log_journal(journal_buffer, - bgd[bg_idx].block_id)) - goto fail; - prev_bg_bmap_idx = bg_idx; - } - } - if (node_inode) { - free(node_inode); - node_inode = NULL; - } + /* FIXME delete extent index blocks, i.e. eh_depth >= 1 */ + struct ext4_extent_header *eh = + (struct ext4_extent_header *) + inode.b.blocks.dir_blocks; + debug("del: dep=%d entries=%d\n", eh->eh_depth, eh->eh_entries); } else { - delete_single_indirect_block(&inode); delete_double_indirect_block(&inode); delete_triple_indirect_block(&inode); + } - /* read the block no allocated to a file */ - no_blocks = inode.size / fs->blksz; - if (inode.size % fs->blksz) - no_blocks++; - for (i = 0; i < no_blocks; i++) { - blknr = read_allocated_block(&inode, i); - bg_idx = blknr / blk_per_grp; - if (fs->blksz == 1024) { - remainder = blknr % blk_per_grp; - if (!remainder) - bg_idx--; - } - ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], - bg_idx); - debug("ActualB releasing %ld: %d\n", blknr, bg_idx); - - bgd[bg_idx].free_blocks++; - fs->sb->free_blocks++; - /* journal backup */ - if (prev_bg_bmap_idx != bg_idx) { - memset(journal_buffer, '\0', fs->blksz); - status = ext4fs_devread((lbaint_t) - bgd[bg_idx].block_id - * fs->sect_perblk, - 0, fs->blksz, - journal_buffer); - if (status == 0) - goto fail; - if (ext4fs_log_journal(journal_buffer, - bgd[bg_idx].block_id)) - goto fail; - prev_bg_bmap_idx = bg_idx; - } + /* release data blocks */ + for (i = 0; i < no_blocks; i++) { + blknr = read_allocated_block(&inode, i, NULL); + if (blknr == 0) + continue; + if (blknr < 0) + goto fail; + bg_idx = blknr / blk_per_grp; + if (fs->blksz == 1024) { + remainder = blknr % blk_per_grp; + if (!remainder) + bg_idx--; + } + ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], + bg_idx); + debug("EXT4 Block releasing %ld: %d\n", blknr, bg_idx); + + /* get block group descriptor table */ + bgd = ext4fs_get_group_descriptor(fs, bg_idx); + ext4fs_bg_free_blocks_inc(bgd, fs); + ext4fs_sb_free_blocks_inc(fs->sb); + /* journal backup */ + if (prev_bg_bmap_idx != bg_idx) { + uint64_t b_bitmap_blk = ext4fs_bg_get_block_id(bgd, fs); + status = ext4fs_devread(b_bitmap_blk * fs->sect_perblk, + 0, fs->blksz, + journal_buffer); + if (status == 0) + goto fail; + if (ext4fs_log_journal(journal_buffer, b_bitmap_blk)) + goto fail; + prev_bg_bmap_idx = bg_idx; } } + /* release inode */ /* from the inode no to blockno */ inodes_per_block = fs->blksz / fs->inodesz; ibmap_idx = inodeno / inode_per_grp; /* get the block no */ inodeno--; - blkno = __le32_to_cpu(bgd[ibmap_idx].inode_table_id) + - (inodeno % __le32_to_cpu(inode_per_grp)) / inodes_per_block; + /* get block group descriptor table */ + bgd = ext4fs_get_group_descriptor(fs, ibmap_idx); + blkno = ext4fs_bg_get_inode_table_id(bgd, fs) + + (inodeno % inode_per_grp) / inodes_per_block; /* get the offset of the inode */ blkoff = ((inodeno) % inodes_per_block) * fs->inodesz; @@ -541,7 +543,7 @@ static int ext4fs_delete_file(int inodeno) read_buffer = read_buffer + blkoff; inode_buffer = (struct ext2_inode *)read_buffer; - memset(inode_buffer, '\0', sizeof(struct ext2_inode)); + memset(inode_buffer, '\0', fs->inodesz); /* write the inode to original position in inode table */ if (ext4fs_put_metadata(start_block_address, blkno)) @@ -550,15 +552,15 @@ static int ext4fs_delete_file(int inodeno) /* update the respective inode bitmaps */ inodeno++; ext4fs_reset_inode_bmap(inodeno, fs->inode_bmaps[ibmap_idx], ibmap_idx); - bgd[ibmap_idx].free_inodes++; - fs->sb->free_inodes++; + ext4fs_bg_free_inodes_inc(bgd, fs); + ext4fs_sb_free_inodes_inc(fs->sb); /* journal backup */ memset(journal_buffer, '\0', fs->blksz); - status = ext4fs_devread((lbaint_t)bgd[ibmap_idx].inode_id * + status = ext4fs_devread(ext4fs_bg_get_inode_id(bgd, fs) * fs->sect_perblk, 0, fs->blksz, journal_buffer); if (status == 0) goto fail; - if (ext4fs_log_journal(journal_buffer, bgd[ibmap_idx].inode_id)) + if (ext4fs_log_journal(journal_buffer, ext4fs_bg_get_inode_id(bgd, fs))) goto fail; ext4fs_update(); @@ -585,12 +587,11 @@ int ext4fs_init(void) { short status; int i; - unsigned int real_free_blocks = 0; + uint32_t real_free_blocks = 0; struct ext_filesystem *fs = get_fs(); /* populate fs */ fs->blksz = EXT2_BLOCK_SIZE(ext4fs_root); - fs->inodesz = INODE_SIZE_FILESYSTEM(ext4fs_root); fs->sect_perblk = fs->blksz >> fs->dev_desc->log2blksz; /* get the superblock */ @@ -606,9 +607,9 @@ int ext4fs_init(void) /* get total no of blockgroups */ fs->no_blkgrp = (uint32_t)ext4fs_div_roundup( - (ext4fs_root->sblock.total_blocks - - ext4fs_root->sblock.first_data_block), - ext4fs_root->sblock.blocks_per_group); + le32_to_cpu(ext4fs_root->sblock.total_blocks) + - le32_to_cpu(ext4fs_root->sblock.first_data_block), + le32_to_cpu(ext4fs_root->sblock.blocks_per_group)); /* get the block group descriptor table */ fs->gdtable_blkno = ((EXT2_MIN_BLOCK_SIZE == fs->blksz) + 1); @@ -616,7 +617,6 @@ int ext4fs_init(void) printf("Error in getting the block group descriptor table\n"); goto fail; } - fs->bgd = (struct ext2_block_group *)fs->gdtable; /* load all the available bitmap block of the partition */ fs->blk_bmaps = zalloc(fs->no_blkgrp * sizeof(char *)); @@ -629,8 +629,9 @@ int ext4fs_init(void) } for (i = 0; i < fs->no_blkgrp; i++) { - status = - ext4fs_devread((lbaint_t)fs->bgd[i].block_id * + struct ext2_block_group *bgd = + ext4fs_get_group_descriptor(fs, i); + status = ext4fs_devread(ext4fs_bg_get_block_id(bgd, fs) * fs->sect_perblk, 0, fs->blksz, (char *)fs->blk_bmaps[i]); if (status == 0) @@ -648,7 +649,9 @@ int ext4fs_init(void) } for (i = 0; i < fs->no_blkgrp; i++) { - status = ext4fs_devread((lbaint_t)fs->bgd[i].inode_id * + struct ext2_block_group *bgd = + ext4fs_get_group_descriptor(fs, i); + status = ext4fs_devread(ext4fs_bg_get_inode_id(bgd, fs) * fs->sect_perblk, 0, fs->blksz, (char *)fs->inode_bmaps[i]); @@ -662,10 +665,14 @@ int ext4fs_init(void) * with the blockgroups freeblocks when improper * reboot of a linux kernel */ - for (i = 0; i < fs->no_blkgrp; i++) - real_free_blocks = real_free_blocks + fs->bgd[i].free_blocks; - if (real_free_blocks != fs->sb->free_blocks) - fs->sb->free_blocks = real_free_blocks; + for (i = 0; i < fs->no_blkgrp; i++) { + struct ext2_block_group *bgd = + ext4fs_get_group_descriptor(fs, i); + real_free_blocks = real_free_blocks + + ext4fs_bg_get_free_blocks(bgd, fs); + } + if (real_free_blocks != ext4fs_sb_get_free_blocks(fs->sb)) + ext4fs_sb_set_free_blocks(fs->sb, real_free_blocks); return 0; fail: @@ -679,8 +686,9 @@ void ext4fs_deinit(void) int i; struct ext2_inode inode_journal; struct journal_superblock_t *jsb; - long int blknr; + uint32_t blknr; struct ext_filesystem *fs = get_fs(); + uint32_t new_feature_incompat; /* free journal */ char *temp_buff = zalloc(fs->blksz); @@ -688,11 +696,11 @@ void ext4fs_deinit(void) ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO, &inode_journal); blknr = read_allocated_block(&inode_journal, - EXT2_JOURNAL_SUPERBLOCK); + EXT2_JOURNAL_SUPERBLOCK, NULL); ext4fs_devread((lbaint_t)blknr * fs->sect_perblk, 0, fs->blksz, temp_buff); jsb = (struct journal_superblock_t *)temp_buff; - jsb->s_start = cpu_to_be32(0); + jsb->s_start = 0; put_ext4((uint64_t) ((uint64_t)blknr * (uint64_t)fs->blksz), (struct journal_superblock_t *)temp_buff, fs->blksz); free(temp_buff); @@ -701,7 +709,9 @@ void ext4fs_deinit(void) /* get the superblock */ ext4_read_superblock((char *)fs->sb); - fs->sb->feature_incompat &= ~EXT3_FEATURE_INCOMPAT_RECOVER; + new_feature_incompat = le32_to_cpu(fs->sb->feature_incompat); + new_feature_incompat &= ~EXT3_FEATURE_INCOMPAT_RECOVER; + fs->sb->feature_incompat = cpu_to_le32(new_feature_incompat); put_ext4((uint64_t)(SUPERBLOCK_SIZE), (struct ext2_sblock *)fs->sb, (uint32_t)SUPERBLOCK_SIZE); free(fs->sb); @@ -728,7 +738,6 @@ void ext4fs_deinit(void) free(fs->gdtable); fs->gdtable = NULL; - fs->bgd = NULL; /* * reinitiliazed the global inode and * block bitmap first execution check variables @@ -739,12 +748,16 @@ void ext4fs_deinit(void) fs->curr_blkno = 0; } +/* + * Write data to filesystem blocks. Uses same optimization for + * contigous sectors as ext4fs_read_file + */ static int ext4fs_write_file(struct ext2_inode *file_inode, int pos, unsigned int len, char *buf) { int i; int blockcnt; - unsigned int filesize = __le32_to_cpu(file_inode->size); + uint32_t filesize = le32_to_cpu(file_inode->size); struct ext_filesystem *fs = get_fs(); int log2blksz = fs->dev_desc->log2blksz; int log2_fs_blocksize = LOG2_BLOCK_SIZE(ext4fs_root) - log2blksz; @@ -764,8 +777,8 @@ static int ext4fs_write_file(struct ext2_inode *file_inode, long int blknr; int blockend = fs->blksz; int skipfirst = 0; - blknr = read_allocated_block(file_inode, i); - if (blknr < 0) + blknr = read_allocated_block(file_inode, i, NULL); + if (blknr <= 0) return -1; blknr = blknr << log2_fs_blocksize; @@ -839,11 +852,12 @@ int ext4fs_write(const char *fname, unsigned char *buffer, struct ext2_sblock *sblock = &(ext4fs_root->sblock); unsigned int inodes_per_block; unsigned int ibmap_idx; + struct ext2_block_group *bgd = NULL; struct ext_filesystem *fs = get_fs(); ALLOC_CACHE_ALIGN_BUFFER(char, filename, 256); memset(filename, 0x00, 256); - g_parent_inode = zalloc(sizeof(struct ext2_inode)); + g_parent_inode = zalloc(fs->inodesz); if (!g_parent_inode) goto fail; @@ -857,8 +871,13 @@ int ext4fs_write(const char *fname, unsigned char *buffer, goto fail; if (ext4fs_iget(parent_inodeno, g_parent_inode)) goto fail; + /* do not mess up a directory using hash trees */ + if (le32_to_cpu(g_parent_inode->flags) & EXT4_INDEX_FL) { + printf("hash tree directory\n"); + goto fail; + } /* check if the filename is already present in root */ - existing_file_inodeno = ext4fs_filename_check(filename); + existing_file_inodeno = ext4fs_filename_unlink(filename); if (existing_file_inodeno != -1) { ret = ext4fs_delete_file(existing_file_inodeno); fs->first_pass_bbmap = 0; @@ -878,39 +897,42 @@ int ext4fs_write(const char *fname, unsigned char *buffer, } blocks_remaining = blks_reqd_for_file; /* test for available space in partition */ - if (fs->sb->free_blocks < blks_reqd_for_file) { + if (le32_to_cpu(fs->sb->free_blocks) < blks_reqd_for_file) { printf("Not enough space on partition !!!\n"); goto fail; } - ext4fs_update_parent_dentry(filename, &inodeno, FILETYPE_REG); + inodeno = ext4fs_update_parent_dentry(filename, FILETYPE_REG); + if (inodeno == -1) + goto fail; /* prepare file inode */ inode_buffer = zalloc(fs->inodesz); if (!inode_buffer) goto fail; file_inode = (struct ext2_inode *)inode_buffer; - file_inode->mode = S_IFREG | S_IRWXU | - S_IRGRP | S_IROTH | S_IXGRP | S_IXOTH; + file_inode->mode = cpu_to_le16(S_IFREG | S_IRWXU | + S_IRGRP | S_IROTH | S_IXGRP | S_IXOTH); /* ToDo: Update correct time */ - file_inode->mtime = timestamp; - file_inode->atime = timestamp; - file_inode->ctime = timestamp; - file_inode->nlinks = 1; - file_inode->size = sizebytes; + file_inode->mtime = cpu_to_le32(timestamp); + file_inode->atime = cpu_to_le32(timestamp); + file_inode->ctime = cpu_to_le32(timestamp); + file_inode->nlinks = cpu_to_le16(1); + file_inode->size = cpu_to_le32(sizebytes); /* Allocate data blocks */ ext4fs_allocate_blocks(file_inode, blocks_remaining, &blks_reqd_for_file); - file_inode->blockcnt = (blks_reqd_for_file * fs->blksz) >> - fs->dev_desc->log2blksz; + file_inode->blockcnt = cpu_to_le32((blks_reqd_for_file * fs->blksz) >> + fs->dev_desc->log2blksz); temp_ptr = zalloc(fs->blksz); if (!temp_ptr) goto fail; - ibmap_idx = inodeno / ext4fs_root->sblock.inodes_per_group; + ibmap_idx = inodeno / le32_to_cpu(ext4fs_root->sblock.inodes_per_group); inodeno--; - itable_blkno = __le32_to_cpu(fs->bgd[ibmap_idx].inode_table_id) + - (inodeno % __le32_to_cpu(sblock->inodes_per_group)) / + bgd = ext4fs_get_group_descriptor(fs, ibmap_idx); + itable_blkno = ext4fs_bg_get_inode_table_id(bgd, fs) + + (inodeno % le32_to_cpu(sblock->inodes_per_group)) / inodes_per_block; blkoff = (inodeno % inodes_per_block) * fs->inodesz; ext4fs_devread((lbaint_t)itable_blkno * fs->sect_perblk, 0, fs->blksz, @@ -924,13 +946,15 @@ int ext4fs_write(const char *fname, unsigned char *buffer, /* copy the file content into data blocks */ if (ext4fs_write_file(file_inode, 0, sizebytes, (char *)buffer) == -1) { printf("Error in copying content\n"); + /* FIXME: Deallocate data blocks */ goto fail; } - ibmap_idx = parent_inodeno / ext4fs_root->sblock.inodes_per_group; + ibmap_idx = parent_inodeno / le32_to_cpu(ext4fs_root->sblock.inodes_per_group); parent_inodeno--; - parent_itable_blkno = __le32_to_cpu(fs->bgd[ibmap_idx].inode_table_id) + + bgd = ext4fs_get_group_descriptor(fs, ibmap_idx); + parent_itable_blkno = ext4fs_bg_get_inode_table_id(bgd, fs) + (parent_inodeno % - __le32_to_cpu(sblock->inodes_per_group)) / inodes_per_block; + le32_to_cpu(sblock->inodes_per_group)) / inodes_per_block; blkoff = (parent_inodeno % inodes_per_block) * fs->inodesz; if (parent_itable_blkno != itable_blkno) { memset(temp_ptr, '\0', fs->blksz); @@ -939,22 +963,18 @@ int ext4fs_write(const char *fname, unsigned char *buffer, if (ext4fs_log_journal(temp_ptr, parent_itable_blkno)) goto fail; - memcpy(temp_ptr + blkoff, g_parent_inode, - sizeof(struct ext2_inode)); + memcpy(temp_ptr + blkoff, g_parent_inode, fs->inodesz); if (ext4fs_put_metadata(temp_ptr, parent_itable_blkno)) goto fail; - free(temp_ptr); } else { /* * If parent and child fall in same inode table block * both should be kept in 1 buffer */ - memcpy(temp_ptr + blkoff, g_parent_inode, - sizeof(struct ext2_inode)); + memcpy(temp_ptr + blkoff, g_parent_inode, fs->inodesz); gd_index--; if (ext4fs_put_metadata(temp_ptr, itable_blkno)) goto fail; - free(temp_ptr); } ext4fs_update(); ext4fs_deinit(); @@ -965,6 +985,7 @@ int ext4fs_write(const char *fname, unsigned char *buffer, fs->curr_inode_no = 0; free(inode_buffer); free(g_parent_inode); + free(temp_ptr); g_parent_inode = NULL; return 0; @@ -972,6 +993,7 @@ int ext4fs_write(const char *fname, unsigned char *buffer, ext4fs_deinit(); free(inode_buffer); free(g_parent_inode); + free(temp_ptr); g_parent_inode = NULL; return -1; diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c index 43c8897793f2..8db75543ffa0 100644 --- a/fs/ext4/ext4fs.c +++ b/fs/ext4/ext4fs.c @@ -55,7 +55,7 @@ int ext4fs_read_file(struct ext2fs_node *node, loff_t pos, int log2blksz = fs->dev_desc->log2blksz; int log2_fs_blocksize = LOG2_BLOCK_SIZE(node->data) - log2blksz; int blocksize = (1 << (log2_fs_blocksize + log2blksz)); - unsigned int filesize = __le32_to_cpu(node->inode.size); + unsigned int filesize = le32_to_cpu(node->inode.size); lbaint_t previous_block_number = -1; lbaint_t delayed_start = 0; lbaint_t delayed_extent = 0; @@ -63,6 +63,9 @@ int ext4fs_read_file(struct ext2fs_node *node, loff_t pos, lbaint_t delayed_next = 0; char *delayed_buf = NULL; short status; + struct ext_block_cache cache; + + ext_cache_init(&cache); /* Adjust len so it we can't read past the end of the file. */ if (len > filesize) @@ -75,9 +78,11 @@ int ext4fs_read_file(struct ext2fs_node *node, loff_t pos, int blockoff = pos - (blocksize * i); int blockend = blocksize; int skipfirst = 0; - blknr = read_allocated_block(&(node->inode), i); - if (blknr < 0) + blknr = read_allocated_block(&(node->inode), i, &cache); + if (blknr < 0) { + ext_cache_fini(&cache); return -1; + } blknr = blknr << log2_fs_blocksize; @@ -107,8 +112,10 @@ int ext4fs_read_file(struct ext2fs_node *node, loff_t pos, delayed_skipfirst, delayed_extent, delayed_buf); - if (status == 0) + if (status == 0) { + ext_cache_fini(&cache); return -1; + } previous_block_number = blknr; delayed_start = blknr; delayed_extent = blockend; @@ -133,8 +140,10 @@ int ext4fs_read_file(struct ext2fs_node *node, loff_t pos, delayed_skipfirst, delayed_extent, delayed_buf); - if (status == 0) + if (status == 0) { + ext_cache_fini(&cache); return -1; + } previous_block_number = -1; } memset(buf, 0, blocksize - skipfirst); @@ -146,12 +155,15 @@ int ext4fs_read_file(struct ext2fs_node *node, loff_t pos, status = ext4fs_devread(delayed_start, delayed_skipfirst, delayed_extent, delayed_buf); - if (status == 0) + if (status == 0) { + ext_cache_fini(&cache); return -1; + } previous_block_number = -1; } *actread = len; + ext_cache_fini(&cache); return 0; } @@ -248,3 +260,32 @@ int ext4fs_uuid(char *uuid_str) return -ENOSYS; #endif } + +void ext_cache_init(struct ext_block_cache *cache) +{ + memset(cache, 0, sizeof(*cache)); +} + +void ext_cache_fini(struct ext_block_cache *cache) +{ + free(cache->buf); + ext_cache_init(cache); +} + +int ext_cache_read(struct ext_block_cache *cache, lbaint_t block, int size) +{ + /* This could be more lenient, but this is simple and enough for now */ + if (cache->buf && cache->block == block && cache->size == size) + return 1; + ext_cache_fini(cache); + cache->buf = malloc(size); + if (!cache->buf) + return 0; + if (!ext4fs_devread(block, 0, size, cache->buf)) { + free(cache->buf); + return 0; + } + cache->block = block; + cache->size = size; + return 1; +} diff --git a/include/autoboot.h b/include/autoboot.h index c175f91c5a53..2fb8d08c81d3 100644 --- a/include/autoboot.h +++ b/include/autoboot.h @@ -24,6 +24,8 @@ */ const char *bootdelay_process(void); +int abortboot(int bootdelay); + /** * autoboot_command() - run the autoboot command * @@ -39,6 +41,11 @@ static inline const char *bootdelay_process(void) return NULL; } +static inline int abortboot(int bootdelay) +{ + return 0; +} + static inline void autoboot_command(const char *s) { } diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index 9ecaf38a3300..d7182244cb1a 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -314,6 +314,12 @@ #define BOOTENV_BOOT_TARGETS \ "boot_targets=" BOOT_TARGET_DEVICES(BOOTENV_DEV_NAME) "\0" +#ifndef BOOT_TARGET_DEFAULTDEVPLIST +#define BOOT_TARGET_DEFAULTDEVPLIST "1" +#endif +#define BOOTENV_SET_DEFAULTDEVPLIST \ + "defaultdevplist=" BOOT_TARGET_DEFAULTDEVPLIST "\0" + #define BOOTENV_DEV(devtypeu, devtypel, instance) \ BOOTENV_DEV_##devtypeu(devtypeu, devtypel, instance) #define BOOTENV \ @@ -326,6 +332,7 @@ BOOTENV_SHARED_IDE \ BOOTENV_SHARED_UBIFS \ BOOTENV_SHARED_EFI \ + BOOTENV_SET_DEFAULTDEVPLIST \ "boot_prefixes=/ /boot/\0" \ "boot_scripts=boot.scr.uimg boot.scr\0" \ "boot_script_dhcp=boot.scr.uimg\0" \ @@ -373,7 +380,7 @@ \ "scan_dev_for_boot_part=" \ "part list ${devtype} ${devnum} -bootable devplist; " \ - "env exists devplist || setenv devplist 1; " \ + "env exists devplist || setenv devplist $defaultdevplist; " \ "for distro_bootpart in ${devplist}; do " \ "if fstype ${devtype} " \ "${devnum}:${distro_bootpart} " \ diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h index 953c0880501d..9bb58df017b7 100644 --- a/include/configs/jetson-tk1.h +++ b/include/configs/jetson-tk1.h @@ -60,9 +60,11 @@ #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" +#if 0 /* L4T compiler workaround */ #define CONFIG_ARMV7_PSCI 1 /* Reserve top 1M for secure RAM */ #define CONFIG_ARMV7_SECURE_BASE 0xfff00000 #define CONFIG_ARMV7_SECURE_RESERVE_SIZE 0x00100000 +#endif #endif /* __CONFIG_H */ diff --git a/include/configs/p2371-2180.h b/include/configs/p2371-2180.h index 6133d3f1e71c..982914c57f02 100644 --- a/include/configs/p2371-2180.h +++ b/include/configs/p2371-2180.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013-2015 + * (C) Copyright 2013-2017 * NVIDIA Corporation * * SPDX-License-Identifier: GPL-2.0+ @@ -20,6 +20,7 @@ /* I2C */ #define CONFIG_SYS_I2C_TEGRA +#define CONFIG_SYS_VI_I2C_TEGRA /* SD/MMC */ #define CONFIG_MMC @@ -54,6 +55,16 @@ /* General networking support */ #include "tegra-common-usb-gadget.h" + +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 2) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) +#endif /* !CONFIG_SPL_BUILD */ + #include "tegra-common-post.h" /* Crystal is 38.4MHz. clk_m runs at half that rate */ diff --git a/include/configs/p2771-0000.h b/include/configs/p2771-0000.h index 257283f3b937..ab335def605b 100644 --- a/include/configs/p2771-0000.h +++ b/include/configs/p2771-0000.h @@ -14,6 +14,9 @@ /* High-level configuration options */ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2771-0000" +/* I2C */ +#define CONFIG_SYS_I2C_TEGRA + /* SD/MMC */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC @@ -25,9 +28,50 @@ #define CONFIG_SYS_MMC_ENV_PART 2 #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) +/* PCI host support */ +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_CMD_PCI + +/* Custom Commands */ +#define CONFIG_CMD_TMR +#define CONFIG_CMD_MD5SUM + +#define BOARD_EXTRA_ENV_SETTINGS \ + "calculated_vars=kernel_addr_r fdt_addr_r scriptaddr pxefile_addr_r " \ + "ramdisk_addr_r\0" \ + "kernel_addr_r_align=00200000\0" \ + "kernel_addr_r_offset=00080000\0" \ + "kernel_addr_r_size=02000000\0" \ + "kernel_addr_r_aliases=loadaddr\0" \ + "fdt_addr_r_align=00200000\0" \ + "fdt_addr_r_offset=00000000\0" \ + "fdt_addr_r_size=00200000\0" \ + "scriptaddr_align=00200000\0" \ + "scriptaddr_offset=00000000\0" \ + "scriptaddr_size=00200000\0" \ + "pxefile_addr_r_align=00200000\0" \ + "pxefile_addr_r_offset=00000000\0" \ + "pxefile_addr_r_size=00200000\0" \ + "ramdisk_addr_r_align=00200000\0" \ + "ramdisk_addr_r_offset=00000000\0" \ + "ramdisk_addr_r_size=02000000\0" + +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 2) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) +#endif + #include "tegra-common-post.h" /* Crystal is 38.4MHz. clk_m runs at half that rate */ #define COUNTER_FREQUENCY 19200000 +#undef CONFIG_NR_DRAM_BANKS +#define CONFIG_NR_DRAM_BANKS (1024 + 2) + #endif diff --git a/include/configs/p3450-porg.h b/include/configs/p3450-porg.h new file mode 100644 index 000000000000..8e177161df53 --- /dev/null +++ b/include/configs/p3450-porg.h @@ -0,0 +1,93 @@ +/* + * (C) Copyright 2018-2019 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _P3450_PORG_H +#define _P3450_PORG_H + +#include + +#include "tegra210-common.h" + +/* High-level configuration options */ +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P3450-PORG" + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTA + +/* I2C */ +#define CONFIG_SYS_I2C_TEGRA +#define CONFIG_SYS_VI_I2C_TEGRA + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC + +#ifdef CONFIG_NANO_EMMC +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) + +#define DEFAULT_MMC_DEV "0" +#else +/* Only MMC1/PXE/DHCP for now, add USB back in later when supported */ +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +/* Environment at end of QSPI, in the VER partition */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_MAX_HZ 48000000 +#define CONFIG_ENV_SPI_MODE SPI_MODE_0 +#define CONFIG_ENV_SECT_SIZE SZ_4K +/* 4MB flash, environment located as high as possible */ +#define CONFIG_ENV_OFFSET (SZ_4M - CONFIG_ENV_SIZE) + +/* SPI */ +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 24000000 +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +#define DEFAULT_MMC_DEV "1" +#endif /* CONFIG_NANO_EMMC */ + +/* USB2.0 Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA + +/* PCI host support */ +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_CMD_PCI + +#define CONFIG_PREBOOT + +#define BOARD_EXTRA_ENV_SETTINGS \ + "preboot=if test -e mmc " DEFAULT_MMC_DEV ":1 /u-boot-preboot.scr; then " \ + "load mmc " DEFAULT_MMC_DEV ":1 ${scriptaddr} /u-boot-preboot.scr; " \ + "source ${scriptaddr}; " \ + "fi\0" + +/* General networking support */ + +#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h" + +/* Crystal is 38.4MHz. clk_m runs at half that rate */ +#define COUNTER_FREQUENCY 19200000 + +/* Turn SDMMC1 off in early init on Porg/Nano */ +#define CONFIG_DISABLE_SDMMC1_EARLY + +#endif /* _P3450_PORG_H */ diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index b206ce4bf93c..07bac7ede259 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2012 + * (C) Copyright 2010-2019 * NVIDIA Corporation * * SPDX-License-Identifier: GPL-2.0+ @@ -22,16 +22,18 @@ #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ #ifndef CONFIG_SPL_BUILD +#ifndef BOOT_TARGET_DEVICES #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) +#endif /* !BOOT_TARGET_DEVICES */ #include #else #define BOOTENV -#endif +#endif /* CONFIG_SPL_BUILD */ #ifdef CONFIG_TEGRA_KEYBOARD #define STDIN_KBD_KBC ",tegra-kbc" diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 7b0940a7f20c..4c4a1ea1c647 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -76,11 +76,11 @@ * Increasing the size of the IO buffer as default nfsargs size is more * than 256 and so it is not possible to edit it */ -#define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE (1024 * 2) /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ +#define CONFIG_SYS_MAXARGS 64 /* max number of command args */ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) @@ -96,7 +96,7 @@ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 2 +#define CONFIG_NR_DRAM_BANKS 3 #define PHYS_SDRAM_1 NV_PA_SDRC_CS0 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ @@ -105,14 +105,17 @@ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ +#ifndef CONFIG_ARM64 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) +#endif #define CONFIG_CMD_ENTERRCM +#ifndef CONFIG_ARM64 /* Defines for SPL */ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_RAM_DEVICE @@ -126,6 +129,7 @@ #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_GPIO_SUPPORT +#endif #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_LATE_INIT diff --git a/include/configs/tegra186-common.h b/include/configs/tegra186-common.h index aa7b9d038a7e..7d4f02ed3c38 100644 --- a/include/configs/tegra186-common.h +++ b/include/configs/tegra186-common.h @@ -1,5 +1,5 @@ /* - * Copyright 2013-2016, NVIDIA CORPORATION. + * Copyright 2013-2019, NVIDIA CORPORATION. * * SPDX-License-Identifier: GPL-2.0 */ @@ -17,11 +17,6 @@ */ #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ -/* - * Miscellaneous configurable options - */ -#define CONFIG_STACKBASE 0x82800000 /* 40MB */ - /*----------------------------------------------------------------------- * Physical Memory Map */ @@ -61,11 +56,24 @@ "pxefile_addr_r=0x90100000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ "fdt_addr_r=0x82000000\0" \ - "ramdisk_addr_r=0x82100000\0" - -/* Defines for SPL */ -#define CONFIG_SPL_TEXT_BASE 0x80108000 -#define CONFIG_SYS_SPL_MALLOC_START 0x80090000 -#define CONFIG_SPL_STACK 0x800ffffc + "ramdisk_addr_r=0x82100000\0" \ + "fdt_copy_node_paths=" \ + "/chosen/plugin-manager:" \ + "/chosen/reset:" \ + "/memory@80000000\0" \ + "fdt_copy_prop_paths=" \ + "/bpmp/carveout-start:" \ + "/bpmp/carveout-size:" \ + "/chosen/nvidia,bluetooth-mac:" \ + "/chosen/nvidia,ether-mac:" \ + "/chosen/nvidia,wifi-mac:" \ + "/chosen/ecid:" \ + "/chosen/linux,initrd-start:" \ + "/chosen/linux,initrd-end:" \ + "/serial-number:" \ + "/trusty/status\0" \ + "fdt_del_copy_node_paths=" \ + "/reserved-memory/ramoops_carveout:" \ + "/reserved-memory/vpr-carveout\0" #endif diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h index 8f35a7bf3dc6..81a3a2a447ef 100644 --- a/include/configs/tegra210-common.h +++ b/include/configs/tegra210-common.h @@ -1,6 +1,5 @@ /* - * (C) Copyright 2013-2015 - * NVIDIA Corporation + * Copyright (c) 2013-2019, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -18,15 +17,10 @@ */ #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ -/* - * Miscellaneous configurable options - */ -#define CONFIG_STACKBASE 0x82800000 /* 40MB */ - /*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_SYS_TEXT_BASE 0x80110000 +#define CONFIG_SYS_TEXT_BASE 0x80080000 /* chainloaded as faux kernel */ /* Generic Interrupt Controller */ #define CONFIG_GICV2 @@ -46,13 +40,13 @@ * should not overlap that area, or the kernel will have to copy itself * somewhere else before decompression. Similarly, the address of any other * data passed to the kernel shouldn't overlap the start of RAM. Pushing - * this up to 16M allows for a sizable kernel to be decompressed below the + * this up to 512K allows for a sizable kernel to be decompressed below the * compressed load address. * - * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for + * fdt_addr_r simply shouldn't overlap anything else. Choosing 40M allows for * the compressed kernel to be up to 16M too. * - * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 50M allows * for the FDT/DTB to be up to 1M, which is hopefully plenty. */ #define CONFIG_LOADADDR 0x80080000 @@ -60,13 +54,26 @@ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "fdt_addr_r=0x82000000\0" \ - "ramdisk_addr_r=0x82100000\0" - -/* Defines for SPL */ -#define CONFIG_SPL_TEXT_BASE 0x80108000 -#define CONFIG_SYS_SPL_MALLOC_START 0x80090000 -#define CONFIG_SPL_STACK 0x800ffffc + "fdt_addr_r=0x83000000\0" \ + "ramdisk_addr_r=0x83200000\0" \ + "fdt_del_prop_paths=/pinmux@700008d4/pinctrl-names\0" \ + "fdt_copy_node_paths=" \ + "/chosen/plugin-manager:" \ + "/chosen/reset:" \ + "/chosen/display-board:" \ + "/chosen/proc-board:" \ + "/chosen/pmu-board:" \ + "/external-memory-controller@7001b000:" \ + "/memory@80000000\0" \ + "fdt_copy_prop_paths=" \ + "/bpmp/carveout-start:" \ + "/bpmp/carveout-size:" \ + "/chosen/nvidia,ethernet-mac:" \ + "/chosen/uuid:" \ + "/chosen/linux,initrd-start:" \ + "/chosen/linux,initrd-end:" \ + "/psci/nvidia,system-lp0-disable:" \ + "/serial-number\0" /* For USB EHCI controller */ #define CONFIG_EHCI_IS_TDI @@ -76,4 +83,7 @@ /* GPU needs setup */ #define CONFIG_TEGRA_GPU +/* PMC secure access */ +#define CONFIG_ACCESS_PMC_VIA_SMC + #endif /* _TEGRA210_COMMON_H_ */ diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index b761640b8fb8..9d49f6380352 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -37,7 +37,8 @@ #define CONFIG_ENV_SPI_MAX_HZ 48000000 #define CONFIG_ENV_SPI_MODE SPI_MODE_0 #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -#define CONFIG_ENV_OFFSET (512 * 1024) +/* 1MiB flash, environment located as high as possible */ +#define CONFIG_ENV_OFFSET (SZ_1M - CONFIG_ENV_SIZE) /* USB Host support */ #define CONFIG_USB_EHCI diff --git a/include/dm/device.h b/include/dm/device.h index f03bcd3b49ee..15c0564071b3 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -593,6 +593,22 @@ static inline bool device_is_on_pci_bus(struct udevice *dev) #define device_foreach_child_safe(pos, next, parent) \ list_for_each_entry_safe(pos, next, &parent->child_head, sibling_node) +/** + * dm_scan_fdt_dev() - Bind child device in a the device tree + * + * This handles device which have sub-nodes in the device tree. It scans all + * sub-nodes and binds drivers for each node where a driver can be found. + * + * If this is called prior to relocation, only pre-relocation devices will be + * bound (those marked with u-boot,dm-pre-reloc in the device tree, or where + * the driver has the DM_FLAG_PRE_RELOC flag set). Otherwise, all devices will + * be bound. + * + * @dev: Device to scan + * @return 0 if OK, -ve on error + */ +int dm_scan_fdt_dev(struct udevice *dev); + /* device resource management */ typedef void (*dr_release_t)(struct udevice *dev, void *res); typedef int (*dr_match_t)(struct udevice *dev, void *res, void *match_data); diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index b768660e8567..e695c4e6dce9 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -60,6 +60,7 @@ enum uclass_id { UCLASS_PINCONFIG, /* Pin configuration node device */ UCLASS_PMIC, /* PMIC I/O device */ UCLASS_PWM, /* Pulse-width modulator */ + UCLASS_POWER_DOMAIN, /* (SoC) Power domains */ UCLASS_PWRSEQ, /* Power sequence device */ UCLASS_REGULATOR, /* Regulator device */ UCLASS_REMOTEPROC, /* Remote Processor device */ diff --git a/include/dt-bindings/clock/tegra186-clock.h b/include/dt-bindings/clock/tegra186-clock.h new file mode 100644 index 000000000000..f73d32098f99 --- /dev/null +++ b/include/dt-bindings/clock/tegra186-clock.h @@ -0,0 +1,940 @@ +/** @file */ + +#ifndef _MACH_T186_CLK_T186_H +#define _MACH_T186_CLK_T186_H + +/** + * @defgroup clock_ids Clock Identifiers + * @{ + * @defgroup extern_input external input clocks + * @{ + * @def TEGRA186_CLK_OSC + * @def TEGRA186_CLK_CLK_32K + * @def TEGRA186_CLK_DTV_INPUT + * @def TEGRA186_CLK_SOR0_PAD_CLKOUT + * @def TEGRA186_CLK_SOR1_PAD_CLKOUT + * @def TEGRA186_CLK_I2S1_SYNC_INPUT + * @def TEGRA186_CLK_I2S2_SYNC_INPUT + * @def TEGRA186_CLK_I2S3_SYNC_INPUT + * @def TEGRA186_CLK_I2S4_SYNC_INPUT + * @def TEGRA186_CLK_I2S5_SYNC_INPUT + * @def TEGRA186_CLK_I2S6_SYNC_INPUT + * @def TEGRA186_CLK_SPDIFIN_SYNC_INPUT + * @} + * + * @defgroup extern_output external output clocks + * @{ + * @def TEGRA186_CLK_EXTPERIPH1 + * @def TEGRA186_CLK_EXTPERIPH2 + * @def TEGRA186_CLK_EXTPERIPH3 + * @def TEGRA186_CLK_EXTPERIPH4 + * @} + * + * @defgroup display_clks display related clocks + * @{ + * @def TEGRA186_CLK_CEC + * @def TEGRA186_CLK_DSIC + * @def TEGRA186_CLK_DSIC_LP + * @def TEGRA186_CLK_DSID + * @def TEGRA186_CLK_DSID_LP + * @def TEGRA186_CLK_DPAUX1 + * @def TEGRA186_CLK_DPAUX + * @def TEGRA186_CLK_HDA2HDMICODEC + * @def TEGRA186_CLK_NVDISPLAY_DISP + * @def TEGRA186_CLK_NVDISPLAY_DSC + * @def TEGRA186_CLK_NVDISPLAY_P0 + * @def TEGRA186_CLK_NVDISPLAY_P1 + * @def TEGRA186_CLK_NVDISPLAY_P2 + * @def TEGRA186_CLK_NVDISPLAYHUB + * @def TEGRA186_CLK_SOR_SAFE + * @def TEGRA186_CLK_SOR0 + * @def TEGRA186_CLK_SOR0_OUT + * @def TEGRA186_CLK_SOR1 + * @def TEGRA186_CLK_SOR1_OUT + * @def TEGRA186_CLK_DSI + * @def TEGRA186_CLK_MIPI_CAL + * @def TEGRA186_CLK_DSIA_LP + * @def TEGRA186_CLK_DSIB + * @def TEGRA186_CLK_DSIB_LP + * @} + * + * @defgroup camera_clks camera related clocks + * @{ + * @def TEGRA186_CLK_NVCSI + * @def TEGRA186_CLK_NVCSILP + * @def TEGRA186_CLK_VI + * @} + * + * @defgroup audio_clks audio related clocks + * @{ + * @def TEGRA186_CLK_ACLK + * @def TEGRA186_CLK_ADSP + * @def TEGRA186_CLK_ADSPNEON + * @def TEGRA186_CLK_AHUB + * @def TEGRA186_CLK_APE + * @def TEGRA186_CLK_APB2APE + * @def TEGRA186_CLK_AUD_MCLK + * @def TEGRA186_CLK_DMIC1 + * @def TEGRA186_CLK_DMIC2 + * @def TEGRA186_CLK_DMIC3 + * @def TEGRA186_CLK_DMIC4 + * @def TEGRA186_CLK_DSPK1 + * @def TEGRA186_CLK_DSPK2 + * @def TEGRA186_CLK_HDA + * @def TEGRA186_CLK_HDA2CODEC_2X + * @def TEGRA186_CLK_I2S1 + * @def TEGRA186_CLK_I2S2 + * @def TEGRA186_CLK_I2S3 + * @def TEGRA186_CLK_I2S4 + * @def TEGRA186_CLK_I2S5 + * @def TEGRA186_CLK_I2S6 + * @def TEGRA186_CLK_MAUD + * @def TEGRA186_CLK_PLL_A_OUT0 + * @def TEGRA186_CLK_SPDIF_DOUBLER + * @def TEGRA186_CLK_SPDIF_IN + * @def TEGRA186_CLK_SPDIF_OUT + * @def TEGRA186_CLK_SYNC_DMIC1 + * @def TEGRA186_CLK_SYNC_DMIC2 + * @def TEGRA186_CLK_SYNC_DMIC3 + * @def TEGRA186_CLK_SYNC_DMIC4 + * @def TEGRA186_CLK_SYNC_DMIC5 + * @def TEGRA186_CLK_SYNC_DSPK1 + * @def TEGRA186_CLK_SYNC_DSPK2 + * @def TEGRA186_CLK_SYNC_I2S1 + * @def TEGRA186_CLK_SYNC_I2S2 + * @def TEGRA186_CLK_SYNC_I2S3 + * @def TEGRA186_CLK_SYNC_I2S4 + * @def TEGRA186_CLK_SYNC_I2S5 + * @def TEGRA186_CLK_SYNC_I2S6 + * @def TEGRA186_CLK_SYNC_SPDIF + * @} + * + * @defgroup uart_clks UART clocks + * @{ + * @def TEGRA186_CLK_AON_UART_FST_MIPI_CAL + * @def TEGRA186_CLK_UARTA + * @def TEGRA186_CLK_UARTB + * @def TEGRA186_CLK_UARTC + * @def TEGRA186_CLK_UARTD + * @def TEGRA186_CLK_UARTE + * @def TEGRA186_CLK_UARTF + * @def TEGRA186_CLK_UARTG + * @def TEGRA186_CLK_UART_FST_MIPI_CAL + * @} + * + * @defgroup i2c_clks I2C clocks + * @{ + * @def TEGRA186_CLK_AON_I2C_SLOW + * @def TEGRA186_CLK_I2C1 + * @def TEGRA186_CLK_I2C2 + * @def TEGRA186_CLK_I2C3 + * @def TEGRA186_CLK_I2C4 + * @def TEGRA186_CLK_I2C5 + * @def TEGRA186_CLK_I2C6 + * @def TEGRA186_CLK_I2C8 + * @def TEGRA186_CLK_I2C9 + * @def TEGRA186_CLK_I2C1 + * @def TEGRA186_CLK_I2C12 + * @def TEGRA186_CLK_I2C13 + * @def TEGRA186_CLK_I2C14 + * @def TEGRA186_CLK_I2C_SLOW + * @def TEGRA186_CLK_VI_I2C + * @} + * + * @defgroup spi_clks SPI clocks + * @{ + * @def TEGRA186_CLK_SPI1 + * @def TEGRA186_CLK_SPI2 + * @def TEGRA186_CLK_SPI3 + * @def TEGRA186_CLK_SPI4 + * @} + * + * @defgroup storage storage related clocks + * @{ + * @def TEGRA186_CLK_SATA + * @def TEGRA186_CLK_SATA_OOB + * @def TEGRA186_CLK_SATA_IOBIST + * @def TEGRA186_CLK_SDMMC_LEGACY_TM + * @def TEGRA186_CLK_SDMMC1 + * @def TEGRA186_CLK_SDMMC2 + * @def TEGRA186_CLK_SDMMC3 + * @def TEGRA186_CLK_SDMMC4 + * @def TEGRA186_CLK_QSPI + * @def TEGRA186_CLK_QSPI_OUT + * @def TEGRA186_CLK_UFSDEV_REF + * @def TEGRA186_CLK_UFSHC + * @} + * + * @defgroup pwm_clks PWM clocks + * @{ + * @def TEGRA186_CLK_PWM1 + * @def TEGRA186_CLK_PWM2 + * @def TEGRA186_CLK_PWM3 + * @def TEGRA186_CLK_PWM4 + * @def TEGRA186_CLK_PWM5 + * @def TEGRA186_CLK_PWM6 + * @def TEGRA186_CLK_PWM7 + * @def TEGRA186_CLK_PWM8 + * @} + * + * @defgroup plls PLLs and related clocks + * @{ + * @def TEGRA186_CLK_PLLREFE_OUT_GATED + * @def TEGRA186_CLK_PLLREFE_OUT1 + * @def TEGRA186_CLK_PLLD_OUT1 + * @def TEGRA186_CLK_PLLP_OUT0 + * @def TEGRA186_CLK_PLLP_OUT5 + * @def TEGRA186_CLK_PLLA + * @def TEGRA186_CLK_PLLE_PWRSEQ + * @def TEGRA186_CLK_PLLA_OUT1 + * @def TEGRA186_CLK_PLLREFE_REF + * @def TEGRA186_CLK_UPHY_PLL0_PWRSEQ + * @def TEGRA186_CLK_UPHY_PLL1_PWRSEQ + * @def TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH + * @def TEGRA186_CLK_PLLREFE_PEX + * @def TEGRA186_CLK_PLLREFE_IDDQ + * @def TEGRA186_CLK_PLLC_OUT_AON + * @def TEGRA186_CLK_PLLC_OUT_ISP + * @def TEGRA186_CLK_PLLC_OUT_VE + * @def TEGRA186_CLK_PLLC4_OUT + * @def TEGRA186_CLK_PLLREFE_OUT + * @def TEGRA186_CLK_PLLREFE_PLL_REF + * @def TEGRA186_CLK_PLLE + * @def TEGRA186_CLK_PLLC + * @def TEGRA186_CLK_PLLP + * @def TEGRA186_CLK_PLLD + * @def TEGRA186_CLK_PLLD2 + * @def TEGRA186_CLK_PLLREFE_VCO + * @def TEGRA186_CLK_PLLC2 + * @def TEGRA186_CLK_PLLC3 + * @def TEGRA186_CLK_PLLDP + * @def TEGRA186_CLK_PLLC4_VCO + * @def TEGRA186_CLK_PLLA1 + * @def TEGRA186_CLK_PLLNVCSI + * @def TEGRA186_CLK_PLLDISPHUB + * @def TEGRA186_CLK_PLLD3 + * @def TEGRA186_CLK_PLLBPMPCAM + * @def TEGRA186_CLK_PLLAON + * @def TEGRA186_CLK_PLLU + * @def TEGRA186_CLK_PLLC4_VCO_DIV2 + * @def TEGRA186_CLK_PLL_REF + * @def TEGRA186_CLK_PLLREFE_OUT1_DIV5 + * @def TEGRA186_CLK_UTMIP_PLL_PWRSEQ + * @def TEGRA186_CLK_PLL_U_48M + * @def TEGRA186_CLK_PLL_U_480M + * @def TEGRA186_CLK_PLLC4_OUT0 + * @def TEGRA186_CLK_PLLC4_OUT1 + * @def TEGRA186_CLK_PLLC4_OUT2 + * @def TEGRA186_CLK_PLLC4_OUT_MUX + * @def TEGRA186_CLK_DFLLDISP_DIV + * @def TEGRA186_CLK_PLLDISPHUB_DIV + * @def TEGRA186_CLK_PLLP_DIV8 + * @} + * + * @defgroup nafll_clks NAFLL clock sources + * @{ + * @def TEGRA186_CLK_NAFLL_AXI_CBB + * @def TEGRA186_CLK_NAFLL_BCPU + * @def TEGRA186_CLK_NAFLL_BPMP + * @def TEGRA186_CLK_NAFLL_DISP + * @def TEGRA186_CLK_NAFLL_GPU + * @def TEGRA186_CLK_NAFLL_ISP + * @def TEGRA186_CLK_NAFLL_MCPU + * @def TEGRA186_CLK_NAFLL_NVDEC + * @def TEGRA186_CLK_NAFLL_NVENC + * @def TEGRA186_CLK_NAFLL_NVJPG + * @def TEGRA186_CLK_NAFLL_SCE + * @def TEGRA186_CLK_NAFLL_SE + * @def TEGRA186_CLK_NAFLL_TSEC + * @def TEGRA186_CLK_NAFLL_TSECB + * @def TEGRA186_CLK_NAFLL_VI + * @def TEGRA186_CLK_NAFLL_VIC + * @} + * + * @defgroup mphy MPHY related clocks + * @{ + * @def TEGRA186_CLK_MPHY_L0_RX_SYMB + * @def TEGRA186_CLK_MPHY_L0_RX_LS_BIT + * @def TEGRA186_CLK_MPHY_L0_TX_SYMB + * @def TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT + * @def TEGRA186_CLK_MPHY_L0_RX_ANA + * @def TEGRA186_CLK_MPHY_L1_RX_ANA + * @def TEGRA186_CLK_MPHY_IOBIST + * @def TEGRA186_CLK_MPHY_TX_1MHZ_REF + * @def TEGRA186_CLK_MPHY_CORE_PLL_FIXED + * @} + * + * @defgroup eavb EAVB related clocks + * @{ + * @def TEGRA186_CLK_EQOS_AXI + * @def TEGRA186_CLK_EQOS_PTP_REF + * @def TEGRA186_CLK_EQOS_RX + * @def TEGRA186_CLK_EQOS_RX_INPUT + * @def TEGRA186_CLK_EQOS_TX + * @} + * + * @defgroup usb USB related clocks + * @{ + * @def TEGRA186_CLK_PEX_USB_PAD0_MGMT + * @def TEGRA186_CLK_PEX_USB_PAD1_MGMT + * @def TEGRA186_CLK_HSIC_TRK + * @def TEGRA186_CLK_USB2_TRK + * @def TEGRA186_CLK_USB2_HSIC_TRK + * @def TEGRA186_CLK_XUSB_CORE_SS + * @def TEGRA186_CLK_XUSB_CORE_DEV + * @def TEGRA186_CLK_XUSB_FALCON + * @def TEGRA186_CLK_XUSB_FS + * @def TEGRA186_CLK_XUSB + * @def TEGRA186_CLK_XUSB_DEV + * @def TEGRA186_CLK_XUSB_HOST + * @def TEGRA186_CLK_XUSB_SS + * @} + * + * @defgroup bigblock compute block related clocks + * @{ + * @def TEGRA186_CLK_GPCCLK + * @def TEGRA186_CLK_GPC2CLK + * @def TEGRA186_CLK_GPU + * @def TEGRA186_CLK_HOST1X + * @def TEGRA186_CLK_ISP + * @def TEGRA186_CLK_NVDEC + * @def TEGRA186_CLK_NVENC + * @def TEGRA186_CLK_NVJPG + * @def TEGRA186_CLK_SE + * @def TEGRA186_CLK_TSEC + * @def TEGRA186_CLK_TSECB + * @def TEGRA186_CLK_VIC + * @} + * + * @defgroup can CAN bus related clocks + * @{ + * @def TEGRA186_CLK_CAN1 + * @def TEGRA186_CLK_CAN1_HOST + * @def TEGRA186_CLK_CAN2 + * @def TEGRA186_CLK_CAN2_HOST + * @} + * + * @defgroup system basic system clocks + * @{ + * @def TEGRA186_CLK_ACTMON + * @def TEGRA186_CLK_AON_APB + * @def TEGRA186_CLK_AON_CPU_NIC + * @def TEGRA186_CLK_AON_NIC + * @def TEGRA186_CLK_AXI_CBB + * @def TEGRA186_CLK_BPMP_APB + * @def TEGRA186_CLK_BPMP_CPU_NIC + * @def TEGRA186_CLK_BPMP_NIC_RATE + * @def TEGRA186_CLK_CLK_M + * @def TEGRA186_CLK_EMC + * @def TEGRA186_CLK_MSS_ENCRYPT + * @def TEGRA186_CLK_SCE_APB + * @def TEGRA186_CLK_SCE_CPU_NIC + * @def TEGRA186_CLK_SCE_NIC + * @def TEGRA186_CLK_TSC + * @} + * + * @defgroup pcie_clks PCIe related clocks + * @{ + * @def TEGRA186_CLK_AFI + * @def TEGRA186_CLK_PCIE + * @def TEGRA186_CLK_PCIE2_IOBIST + * @def TEGRA186_CLK_PCIERX0 + * @def TEGRA186_CLK_PCIERX1 + * @def TEGRA186_CLK_PCIERX2 + * @def TEGRA186_CLK_PCIERX3 + * @def TEGRA186_CLK_PCIERX4 + * @} + */ + +/** @brief output of gate CLK_ENB_FUSE */ +#define TEGRA186_CLK_FUSE 0 +/** + * @brief It's not what you think + * @details output of gate CLK_ENB_GPU. This output connects to the GPU + * pwrclk. @warning: This is almost certainly not the clock you think + * it is. If you're looking for the clock of the graphics engine, see + * TEGRA186_GPCCLK + */ +#define TEGRA186_CLK_GPU 1 +/** @brief output of gate CLK_ENB_PCIE */ +#define TEGRA186_CLK_PCIE 3 +/** @brief output of the divider IPFS_CLK_DIVISOR */ +#define TEGRA186_CLK_AFI 4 +/** @brief output of gate CLK_ENB_PCIE2_IOBIST */ +#define TEGRA186_CLK_PCIE2_IOBIST 5 +/** @brief output of gate CLK_ENB_PCIERX0*/ +#define TEGRA186_CLK_PCIERX0 6 +/** @brief output of gate CLK_ENB_PCIERX1*/ +#define TEGRA186_CLK_PCIERX1 7 +/** @brief output of gate CLK_ENB_PCIERX2*/ +#define TEGRA186_CLK_PCIERX2 8 +/** @brief output of gate CLK_ENB_PCIERX3*/ +#define TEGRA186_CLK_PCIERX3 9 +/** @brief output of gate CLK_ENB_PCIERX4*/ +#define TEGRA186_CLK_PCIERX4 10 +/** @brief output branch of PLL_C for ISP, controlled by gate CLK_ENB_PLLC_OUT_ISP */ +#define TEGRA186_CLK_PLLC_OUT_ISP 11 +/** @brief output branch of PLL_C for VI, controlled by gate CLK_ENB_PLLC_OUT_VE */ +#define TEGRA186_CLK_PLLC_OUT_VE 12 +/** @brief output branch of PLL_C for AON domain, controlled by gate CLK_ENB_PLLC_OUT_AON */ +#define TEGRA186_CLK_PLLC_OUT_AON 13 +/** @brief output of gate CLK_ENB_SOR_SAFE */ +#define TEGRA186_CLK_SOR_SAFE 39 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */ +#define TEGRA186_CLK_I2S2 42 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */ +#define TEGRA186_CLK_I2S3 43 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDF_IN */ +#define TEGRA186_CLK_SPDIF_IN 44 +/** @brief output of gate CLK_ENB_SPDIF_DOUBLER */ +#define TEGRA186_CLK_SPDIF_DOUBLER 45 +/** @clkdesc{spi_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_SPI3} */ +#define TEGRA186_CLK_SPI3 46 +/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1} */ +#define TEGRA186_CLK_I2C1 47 +/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5} */ +#define TEGRA186_CLK_I2C5 48 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */ +#define TEGRA186_CLK_SPI1 49 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */ +#define TEGRA186_CLK_ISP 50 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */ +#define TEGRA186_CLK_VI 51 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */ +#define TEGRA186_CLK_SDMMC1 52 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 */ +#define TEGRA186_CLK_SDMMC2 53 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ +#define TEGRA186_CLK_SDMMC4 54 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ +#define TEGRA186_CLK_UARTA 55 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */ +#define TEGRA186_CLK_UARTB 56 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */ +#define TEGRA186_CLK_HOST1X 57 +/** + * @brief controls the EMC clock frequency. + * @details Doing a clk_set_rate on this clock will select the + * appropriate clock source, program the source rate and execute a + * specific sequence to switch to the new clock source for both memory + * controllers. This can be used to control the balance between memory + * throughput and memory controller power. + */ +#define TEGRA186_CLK_EMC 58 +/* @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */ +#define TEGRA186_CLK_EXTPERIPH4 73 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */ +#define TEGRA186_CLK_SPI4 74 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */ +#define TEGRA186_CLK_I2C3 75 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 */ +#define TEGRA186_CLK_SDMMC3 76 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */ +#define TEGRA186_CLK_UARTD 77 +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */ +#define TEGRA186_CLK_I2S1 79 +/** output of gate CLK_ENB_DTV */ +#define TEGRA186_CLK_DTV 80 +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */ +#define TEGRA186_CLK_TSEC 81 +/** @brief output of gate CLK_ENB_DP2 */ +#define TEGRA186_CLK_DP2 82 +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */ +#define TEGRA186_CLK_I2S4 84 +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */ +#define TEGRA186_CLK_I2S5 85 +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */ +#define TEGRA186_CLK_I2C4 86 +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */ +#define TEGRA186_CLK_AHUB 87 +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */ +#define TEGRA186_CLK_HDA2CODEC_2X 88 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */ +#define TEGRA186_CLK_EXTPERIPH1 89 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */ +#define TEGRA186_CLK_EXTPERIPH2 90 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */ +#define TEGRA186_CLK_EXTPERIPH3 91 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */ +#define TEGRA186_CLK_I2C_SLOW 92 +/** @brief output of the SOR1_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */ +#define TEGRA186_CLK_SOR1 93 +/** @brief output of gate CLK_ENB_CEC */ +#define TEGRA186_CLK_CEC 94 +/** @brief output of gate CLK_ENB_DPAUX1 */ +#define TEGRA186_CLK_DPAUX1 95 +/** @brief output of gate CLK_ENB_DPAUX */ +#define TEGRA186_CLK_DPAUX 96 +/** @brief output of the SOR0_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */ +#define TEGRA186_CLK_SOR0 97 +/** @brief output of gate CLK_ENB_HDA2HDMICODEC */ +#define TEGRA186_CLK_HDA2HDMICODEC 98 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SATA */ +#define TEGRA186_CLK_SATA 99 +/** @brief output of gate CLK_ENB_SATA_OOB */ +#define TEGRA186_CLK_SATA_OOB 100 +/** @brief output of gate CLK_ENB_SATA_IOBIST */ +#define TEGRA186_CLK_SATA_IOBIST 101 +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA */ +#define TEGRA186_CLK_HDA 102 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SE */ +#define TEGRA186_CLK_SE 103 +/** @brief output of gate CLK_ENB_APB2APE */ +#define TEGRA186_CLK_APB2APE 104 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */ +#define TEGRA186_CLK_APE 105 +/** @brief output of gate CLK_ENB_IQC1 */ +#define TEGRA186_CLK_IQC1 106 +/** @brief output of gate CLK_ENB_IQC2 */ +#define TEGRA186_CLK_IQC2 107 +/** divide by 2 version of TEGRA186_CLK_PLLREFE_VCO */ +#define TEGRA186_CLK_PLLREFE_OUT 108 +/** @brief output of gate CLK_ENB_PLLREFE_PLL_REF */ +#define TEGRA186_CLK_PLLREFE_PLL_REF 109 +/** @brief output of gate CLK_ENB_PLLC4_OUT */ +#define TEGRA186_CLK_PLLC4_OUT 110 +/** @brief output of mux xusb_core_clk_switch on page 67 of T186_Clocks_IAS.doc */ +#define TEGRA186_CLK_XUSB 111 +/** controls xusb_dev_ce signal on page 66 and 67 of T186_Clocks_IAS.doc */ +#define TEGRA186_CLK_XUSB_DEV 112 +/** controls xusb_host_ce signal on page 67 of T186_Clocks_IAS.doc */ +#define TEGRA186_CLK_XUSB_HOST 113 +/** controls xusb_ss_ce signal on page 67 of T186_Clocks_IAS.doc */ +#define TEGRA186_CLK_XUSB_SS 114 +/** @brief output of gate CLK_ENB_DSI */ +#define TEGRA186_CLK_DSI 115 +/** @brief output of gate CLK_ENB_MIPI_CAL */ +#define TEGRA186_CLK_MIPI_CAL 116 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP */ +#define TEGRA186_CLK_DSIA_LP 117 +/** @brief output of gate CLK_ENB_DSIB */ +#define TEGRA186_CLK_DSIB 118 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP */ +#define TEGRA186_CLK_DSIB_LP 119 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */ +#define TEGRA186_CLK_DMIC1 122 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */ +#define TEGRA186_CLK_DMIC2 123 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */ +#define TEGRA186_CLK_AUD_MCLK 124 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ +#define TEGRA186_CLK_I2C6 125 +/**output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */ +#define TEGRA186_CLK_UART_FST_MIPI_CAL 126 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */ +#define TEGRA186_CLK_VIC 127 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM */ +#define TEGRA186_CLK_SDMMC_LEGACY_TM 128 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */ +#define TEGRA186_CLK_NVDEC 129 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */ +#define TEGRA186_CLK_NVJPG 130 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */ +#define TEGRA186_CLK_NVENC 131 +/** @brief output of the QSPI_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */ +#define TEGRA186_CLK_QSPI 132 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C */ +#define TEGRA186_CLK_VI_I2C 133 +/** @brief output of gate CLK_ENB_HSIC_TRK */ +#define TEGRA186_CLK_HSIC_TRK 134 +/** @brief output of gate CLK_ENB_USB2_TRK */ +#define TEGRA186_CLK_USB2_TRK 135 +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MAUD */ +#define TEGRA186_CLK_MAUD 136 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSECB */ +#define TEGRA186_CLK_TSECB 137 +/** @brief output of gate CLK_ENB_ADSP */ +#define TEGRA186_CLK_ADSP 138 +/** @brief output of gate CLK_ENB_ADSPNEON */ +#define TEGRA186_CLK_ADSPNEON 139 +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */ +#define TEGRA186_CLK_MPHY_L0_RX_SYMB 140 +/** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */ +#define TEGRA186_CLK_MPHY_L0_RX_LS_BIT 141 +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */ +#define TEGRA186_CLK_MPHY_L0_TX_SYMB 142 +/** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */ +#define TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT 143 +/** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */ +#define TEGRA186_CLK_MPHY_L0_RX_ANA 144 +/** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */ +#define TEGRA186_CLK_MPHY_L1_RX_ANA 145 +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST */ +#define TEGRA186_CLK_MPHY_IOBIST 146 +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */ +#define TEGRA186_CLK_MPHY_TX_1MHZ_REF 147 +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */ +#define TEGRA186_CLK_MPHY_CORE_PLL_FIXED 148 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */ +#define TEGRA186_CLK_AXI_CBB 149 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */ +#define TEGRA186_CLK_DMIC3 150 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */ +#define TEGRA186_CLK_DMIC4 151 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */ +#define TEGRA186_CLK_DSPK1 152 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */ +#define TEGRA186_CLK_DSPK2 153 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ +#define TEGRA186_CLK_I2S6 154 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0 */ +#define TEGRA186_CLK_NVDISPLAY_P0 155 +/** @brief output of the NVDISPLAY_DISP_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP */ +#define TEGRA186_CLK_NVDISPLAY_DISP 156 +/** @brief output of gate CLK_ENB_NVDISPLAY_DSC */ +#define TEGRA186_CLK_NVDISPLAY_DSC 157 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB */ +#define TEGRA186_CLK_NVDISPLAYHUB 158 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1 */ +#define TEGRA186_CLK_NVDISPLAY_P1 159 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2 */ +#define TEGRA186_CLK_NVDISPLAY_P2 160 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH */ +#define TEGRA186_CLK_TACH 166 +/** @brief output of gate CLK_ENB_EQOS */ +#define TEGRA186_CLK_EQOS_AXI 167 +/** @brief output of gate CLK_ENB_EQOS_RX */ +#define TEGRA186_CLK_EQOS_RX 168 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */ +#define TEGRA186_CLK_UFSHC 178 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */ +#define TEGRA186_CLK_UFSDEV_REF 179 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */ +#define TEGRA186_CLK_NVCSI 180 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */ +#define TEGRA186_CLK_NVCSILP 181 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */ +#define TEGRA186_CLK_I2C7 182 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */ +#define TEGRA186_CLK_I2C9 183 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C12 */ +#define TEGRA186_CLK_I2C12 184 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C13 */ +#define TEGRA186_CLK_I2C13 185 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C14 */ +#define TEGRA186_CLK_I2C14 186 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */ +#define TEGRA186_CLK_PWM1 187 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */ +#define TEGRA186_CLK_PWM2 188 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */ +#define TEGRA186_CLK_PWM3 189 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */ +#define TEGRA186_CLK_PWM5 190 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */ +#define TEGRA186_CLK_PWM6 191 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */ +#define TEGRA186_CLK_PWM7 192 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */ +#define TEGRA186_CLK_PWM8 193 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */ +#define TEGRA186_CLK_UARTE 194 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */ +#define TEGRA186_CLK_UARTF 195 +/** @deprecated */ +#define TEGRA186_CLK_DBGAPB 196 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC */ +#define TEGRA186_CLK_BPMP_CPU_NIC 197 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB */ +#define TEGRA186_CLK_BPMP_APB 199 +/** @brief output of mux controlled by TEGRA186_CLK_SOC_ACTMON */ +#define TEGRA186_CLK_ACTMON 201 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC */ +#define TEGRA186_CLK_AON_CPU_NIC 208 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */ +#define TEGRA186_CLK_CAN1 210 +/** @brief output of gate CLK_ENB_CAN1_HOST */ +#define TEGRA186_CLK_CAN1_HOST 211 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */ +#define TEGRA186_CLK_CAN2 212 +/** @brief output of gate CLK_ENB_CAN2_HOST */ +#define TEGRA186_CLK_CAN2_HOST 213 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB */ +#define TEGRA186_CLK_AON_APB 214 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */ +#define TEGRA186_CLK_UARTC 215 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTG */ +#define TEGRA186_CLK_UARTG 216 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */ +#define TEGRA186_CLK_AON_UART_FST_MIPI_CAL 217 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */ +#define TEGRA186_CLK_I2C2 218 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */ +#define TEGRA186_CLK_I2C8 219 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C10 */ +#define TEGRA186_CLK_I2C10 220 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW */ +#define TEGRA186_CLK_AON_I2C_SLOW 221 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */ +#define TEGRA186_CLK_SPI2 222 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */ +#define TEGRA186_CLK_DMIC5 223 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH */ +#define TEGRA186_CLK_AON_TOUCH 224 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */ +#define TEGRA186_CLK_PWM4 225 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSC. This clock object is read only and is used for all timers in the system. */ +#define TEGRA186_CLK_TSC 226 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT */ +#define TEGRA186_CLK_MSS_ENCRYPT 227 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */ +#define TEGRA186_CLK_SCE_CPU_NIC 228 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB */ +#define TEGRA186_CLK_SCE_APB 230 +/** @brief output of gate CLK_ENB_DSIC */ +#define TEGRA186_CLK_DSIC 231 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP */ +#define TEGRA186_CLK_DSIC_LP 232 +/** @brief output of gate CLK_ENB_DSID */ +#define TEGRA186_CLK_DSID 233 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP */ +#define TEGRA186_CLK_DSID_LP 234 +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP */ +#define TEGRA186_CLK_PEX_SATA_USB_RX_BYP 236 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT */ +#define TEGRA186_CLK_SPDIF_OUT 238 +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 */ +#define TEGRA186_CLK_EQOS_PTP_REF 239 +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK */ +#define TEGRA186_CLK_EQOS_TX 240 +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK */ +#define TEGRA186_CLK_USB2_HSIC_TRK 241 +/** @brief output of mux xusb_ss_clk_switch on page 66 of T186_Clocks_IAS.doc */ +#define TEGRA186_CLK_XUSB_CORE_SS 242 +/** @brief output of mux xusb_core_dev_clk_switch on page 67 of T186_Clocks_IAS.doc */ +#define TEGRA186_CLK_XUSB_CORE_DEV 243 +/** @brief output of mux xusb_core_falcon_clk_switch on page 67 of T186_Clocks_IAS.doc */ +#define TEGRA186_CLK_XUSB_FALCON 244 +/** @brief output of mux xusb_fs_clk_switch on page 66 of T186_Clocks_IAS.doc */ +#define TEGRA186_CLK_XUSB_FS 245 +/** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */ +#define TEGRA186_CLK_PLL_A_OUT0 246 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */ +#define TEGRA186_CLK_SYNC_I2S1 247 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */ +#define TEGRA186_CLK_SYNC_I2S2 248 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */ +#define TEGRA186_CLK_SYNC_I2S3 249 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */ +#define TEGRA186_CLK_SYNC_I2S4 250 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */ +#define TEGRA186_CLK_SYNC_I2S5 251 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */ +#define TEGRA186_CLK_SYNC_I2S6 252 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */ +#define TEGRA186_CLK_SYNC_DSPK1 253 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */ +#define TEGRA186_CLK_SYNC_DSPK2 254 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */ +#define TEGRA186_CLK_SYNC_DMIC1 255 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */ +#define TEGRA186_CLK_SYNC_DMIC2 256 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */ +#define TEGRA186_CLK_SYNC_DMIC3 257 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */ +#define TEGRA186_CLK_SYNC_DMIC4 259 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF */ +#define TEGRA186_CLK_SYNC_SPDIF 260 +/** @brief output of gate CLK_ENB_PLLREFE_OUT */ +#define TEGRA186_CLK_PLLREFE_OUT_GATED 261 +/** @brief output of the divider PLLREFE_DIVP in CLK_RST_CONTROLLER_PLLREFE_BASE. PLLREFE has 2 outputs: + * * VCO/pdiv defined by this clock object + * * VCO/2 defined by TEGRA186_CLK_PLLREFE_OUT + */ +#define TEGRA186_CLK_PLLREFE_OUT1 262 +#define TEGRA186_CLK_PLLD_OUT1 267 +/** @brief output of the divider PLLP_DIVP in CLK_RST_CONTROLLER_PLLP_BASE */ +#define TEGRA186_CLK_PLLP_OUT0 269 +/** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTC */ +#define TEGRA186_CLK_PLLP_OUT5 270 +/** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */ +#define TEGRA186_CLK_PLLA 271 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY divided by the divider controlled by ACLK_CLK_DIVISOR in CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER */ +#define TEGRA186_CLK_ACLK 273 +/** fixed 48MHz clock divided down from TEGRA186_CLK_PLL_U */ +#define TEGRA186_CLK_PLL_U_48M 274 +/** fixed 480MHz clock divided down from TEGRA186_CLK_PLL_U */ +#define TEGRA186_CLK_PLL_U_480M 275 +/** @brief output of the divider PLLC4_DIVP in CLK_RST_CONTROLLER_PLLC4_BASE. Output frequency is TEGRA186_CLK_PLLC4_VCO/PLLC4_DIVP */ +#define TEGRA186_CLK_PLLC4_OUT0 276 +/** fixed /3 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/3 */ +#define TEGRA186_CLK_PLLC4_OUT1 277 +/** fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/5 */ +#define TEGRA186_CLK_PLLC4_OUT2 278 +/** @brief output of mux controlled by PLLC4_CLK_SEL in CLK_RST_CONTROLLER_PLLC4_MISC1 */ +#define TEGRA186_CLK_PLLC4_OUT_MUX 279 +/** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when DFLLDISP_DIV is selected in NVDISPLAY_DISP_CLK_SRC */ +#define TEGRA186_CLK_DFLLDISP_DIV 284 +/** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when PLLDISPHUB_DIV is selected in NVDISPLAY_DISP_CLK_SRC */ +#define TEGRA186_CLK_PLLDISPHUB_DIV 285 +/** fixed /8 divider which is used as the input for TEGRA186_CLK_SOR_SAFE */ +#define TEGRA186_CLK_PLLP_DIV8 286 +/** @brief output of divider CLK_RST_CONTROLLER_BPMP_NIC_RATE */ +#define TEGRA186_CLK_BPMP_NIC 287 +/** @brief output of the divider CLK_RST_CONTROLLER_PLLA1_OUT1 */ +#define TEGRA186_CLK_PLL_A_OUT1 288 +/** @deprecated */ +#define TEGRA186_CLK_GPC2CLK 289 +/** A fake clock which must be enabled during KFUSE read operations to ensure adequate VDD_CORE voltage. */ +#define TEGRA186_CLK_KFUSE 293 +/** + * @brief controls the PLLE hardware sequencer. + * @details This clock only has enable and disable methods. When the + * PLLE hw sequencer is enabled, PLLE, will be enabled or disabled by + * hw based on the control signals from the PCIe, SATA and XUSB + * clocks. When the PLLE hw sequencer is disabled, the state of PLLE + * is controlled by sw using clk_enable/clk_disable on + * TEGRA186_CLK_PLLE. + */ +#define TEGRA186_CLK_PLLE_PWRSEQ 294 +/** fixed 60MHz clock divided down from, TEGRA186_CLK_PLL_U */ +#define TEGRA186_CLK_PLLREFE_REF 295 +/** @brief output of mux controlled by SOR0_CLK_SEL0 and SOR0_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */ +#define TEGRA186_CLK_SOR0_OUT 296 +/** @brief output of mux controlled by SOR1_CLK_SEL0 and SOR1_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */ +#define TEGRA186_CLK_SOR1_OUT 297 +/** @brief fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */ +#define TEGRA186_CLK_PLLREFE_OUT1_DIV5 298 +/** @brief controls the UTMIP_PLL (aka PLLU) hardware sqeuencer */ +#define TEGRA186_CLK_UTMIP_PLL_PWRSEQ 301 +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT */ +#define TEGRA186_CLK_PEX_USB_PAD0_MGMT 302 +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT */ +#define TEGRA186_CLK_PEX_USB_PAD1_MGMT 303 +/** @brief controls the UPHY_PLL0 hardware sqeuencer */ +#define TEGRA186_CLK_UPHY_PLL0_PWRSEQ 304 +/** @brief controls the UPHY_PLL1 hardware sqeuencer */ +#define TEGRA186_CLK_UPHY_PLL1_PWRSEQ 305 +/** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC so the bypass output even be used when the PLL is disabled */ +#define TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH 306 +/** @brief output of the mux controlled by PLLREFE_SEL_CLKIN_PEX in CLK_RST_CONTROLLER_PLLREFE_MISC */ +#define TEGRA186_CLK_PLLREFE_PEX 307 +/** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC to turn on the PLL when enabled */ +#define TEGRA186_CLK_PLLREFE_IDDQ 308 +/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */ +#define TEGRA186_CLK_QSPI_OUT 309 +/** + * @brief GPC2CLK-div-2 + * @details fixed /2 divider. Output frequency is + * TEGRA186_CLK_GPC2CLK/2. The frequency of this clock is the + * frequency at which the GPU graphics engine runs. */ +#define TEGRA186_CLK_GPCCLK 310 +/** @brief output of divider CLK_RST_CONTROLLER_AON_NIC_RATE */ +#define TEGRA186_CLK_AON_NIC 450 +/** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */ +#define TEGRA186_CLK_SCE_NIC 451 +/** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */ +#define TEGRA186_CLK_PLLE 512 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */ +#define TEGRA186_CLK_PLLC 513 +/** Fixed 408MHz PLL for use by peripheral clocks */ +#define TEGRA186_CLK_PLLP 516 +/** @deprecated */ +#define TEGRA186_CLK_PLL_P TEGRA186_CLK_PLLP +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD_BASE for use by DSI */ +#define TEGRA186_CLK_PLLD 518 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD2_BASE for use by HDMI or DP */ +#define TEGRA186_CLK_PLLD2 519 +/** + * @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE. + * @details Note that this clock only controls the VCO output, before + * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more + * information. + */ +#define TEGRA186_CLK_PLLREFE_VCO 520 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */ +#define TEGRA186_CLK_PLLC2 521 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC3_BASE */ +#define TEGRA186_CLK_PLLC3 522 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDP_BASE for use as the DP link clock */ +#define TEGRA186_CLK_PLLDP 523 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ +#define TEGRA186_CLK_PLLC4_VCO 524 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */ +#define TEGRA186_CLK_PLLA1 525 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE */ +#define TEGRA186_CLK_PLLNVCSI 526 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDISPHUB_BASE */ +#define TEGRA186_CLK_PLLDISPHUB 527 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD3_BASE for use by HDMI or DP */ +#define TEGRA186_CLK_PLLD3 528 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLBPMPCAM_BASE */ +#define TEGRA186_CLK_PLLBPMPCAM 531 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain */ +#define TEGRA186_CLK_PLLAON 532 +/** Fixed frequency 960MHz PLL for USB and EAVB */ +#define TEGRA186_CLK_PLLU 533 +/** fixed /2 divider. Output frequency is TEGRA186_CLK_PLLC4_VCO/2 */ +#define TEGRA186_CLK_PLLC4_VCO_DIV2 535 +/** @brief NAFLL clock source for AXI_CBB */ +#define TEGRA186_CLK_NAFLL_AXI_CBB 564 +/** @brief NAFLL clock source for BPMP */ +#define TEGRA186_CLK_NAFLL_BPMP 565 +/** @brief NAFLL clock source for ISP */ +#define TEGRA186_CLK_NAFLL_ISP 566 +/** @brief NAFLL clock source for NVDEC */ +#define TEGRA186_CLK_NAFLL_NVDEC 567 +/** @brief NAFLL clock source for NVENC */ +#define TEGRA186_CLK_NAFLL_NVENC 568 +/** @brief NAFLL clock source for NVJPG */ +#define TEGRA186_CLK_NAFLL_NVJPG 569 +/** @brief NAFLL clock source for SCE */ +#define TEGRA186_CLK_NAFLL_SCE 570 +/** @brief NAFLL clock source for SE */ +#define TEGRA186_CLK_NAFLL_SE 571 +/** @brief NAFLL clock source for TSEC */ +#define TEGRA186_CLK_NAFLL_TSEC 572 +/** @brief NAFLL clock source for TSECB */ +#define TEGRA186_CLK_NAFLL_TSECB 573 +/** @brief NAFLL clock source for VI */ +#define TEGRA186_CLK_NAFLL_VI 574 +/** @brief NAFLL clock source for VIC */ +#define TEGRA186_CLK_NAFLL_VIC 575 +/** @brief NAFLL clock source for DISP */ +#define TEGRA186_CLK_NAFLL_DISP 576 +/** @brief NAFLL clock source for GPU */ +#define TEGRA186_CLK_NAFLL_GPU 577 +/** @brief NAFLL clock source for M-CPU cluster */ +#define TEGRA186_CLK_NAFLL_MCPU 578 +/** @brief NAFLL clock source for B-CPU cluster */ +#define TEGRA186_CLK_NAFLL_BCPU 579 +/** @brief input from Tegra's CLK_32K_IN pad */ +#define TEGRA186_CLK_CLK_32K 608 +/** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */ +#define TEGRA186_CLK_CLK_M 609 +/** @brief output of divider PLL_REF_DIV in CLK_RST_CONTROLLER_OSC_CTRL */ +#define TEGRA186_CLK_PLL_REF 610 +/** @brief input from Tegra's XTAL_IN */ +#define TEGRA186_CLK_OSC 612 +/** @brief clock recovered from EAVB input */ +#define TEGRA186_CLK_EQOS_RX_INPUT 613 +/** @brief clock recovered from DTV input */ +#define TEGRA186_CLK_DTV_INPUT 614 +/** @brief SOR0 brick output which feeds into SOR0_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0*/ +#define TEGRA186_CLK_SOR0_PAD_CLKOUT 615 +/** @brief SOR1 brick output which feeds into SOR1_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1*/ +#define TEGRA186_CLK_SOR1_PAD_CLKOUT 616 +/** @brief clock recovered from I2S1 input */ +#define TEGRA186_CLK_I2S1_SYNC_INPUT 617 +/** @brief clock recovered from I2S2 input */ +#define TEGRA186_CLK_I2S2_SYNC_INPUT 618 +/** @brief clock recovered from I2S3 input */ +#define TEGRA186_CLK_I2S3_SYNC_INPUT 619 +/** @brief clock recovered from I2S4 input */ +#define TEGRA186_CLK_I2S4_SYNC_INPUT 620 +/** @brief clock recovered from I2S5 input */ +#define TEGRA186_CLK_I2S5_SYNC_INPUT 621 +/** @brief clock recovered from I2S6 input */ +#define TEGRA186_CLK_I2S6_SYNC_INPUT 622 +/** @brief clock recovered from SPDIFIN input */ +#define TEGRA186_CLK_SPDIFIN_SYNC_INPUT 623 + +/** + * @brief subject to change + * @details maximum clock identifier value plus one. + */ +#define TEGRA186_CLK_CLK_MAX 624 + +/** @} */ + +#endif diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h index d134741eb513..0a05b0d36ae7 100644 --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h @@ -1,6 +1,16 @@ /* - * This header provides Tegra210-specific constants for binding - * nvidia,tegra210-car. + * This header provides constants for binding nvidia,tegra210-car. + * + * The first 224 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB + * registers. These IDs often match those in the CAR's RST_DEVICES registers, + * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In + * this case, those clocks are assigned IDs above 224 in order to highlight + * this issue. Implementations that interpret these clock IDs as bit values + * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to + * explicitly handle these special cases. + * + * The balance of the clocks controlled by the CAR are assigned IDs of 224 and + * above. */ #ifndef _DT_BINDINGS_CLOCK_TEGRA210_CAR_H @@ -14,7 +24,7 @@ #define TEGRA210_CLK_TIMER 5 #define TEGRA210_CLK_UARTA 6 /* 7 (register bit affects uartb and vfir) */ -/* 8 */ +#define TEGRA210_CLK_GPIO 8 #define TEGRA210_CLK_SDMMC2 9 /* 10 (register bit affects spdif_in and spdif_out) */ #define TEGRA210_CLK_I2S1 11 @@ -25,30 +35,31 @@ /* 16 */ #define TEGRA210_CLK_PWM 17 #define TEGRA210_CLK_I2S2 18 +/* 19 */ /* 20 (register bit affects vi and vi_sensor) */ /* 21 */ #define TEGRA210_CLK_USBD 22 #define TEGRA210_CLK_ISP 23 -/* 26 */ +/* 24 */ /* 25 */ #define TEGRA210_CLK_DISP2 26 #define TEGRA210_CLK_DISP1 27 #define TEGRA210_CLK_HOST1X 28 -#define TEGRA210_CLK_VCP 29 +/* 29 */ #define TEGRA210_CLK_I2S0 30 /* 31 */ #define TEGRA210_CLK_MC 32 -/* 33 */ +#define TEGRA210_CLK_AHBDMA 33 #define TEGRA210_CLK_APBDMA 34 /* 35 */ -#define TEGRA210_CLK_KBC 36 +/* 36 */ /* 37 */ -/* 38 */ +#define TEGRA210_CLK_PMC 38 /* 39 (register bit affects fuse and fuse_burn) */ #define TEGRA210_CLK_KFUSE 40 #define TEGRA210_CLK_SBC1 41 -#define TEGRA210_CLK_NOR 42 +/* 42 */ /* 43 */ #define TEGRA210_CLK_SBC2 44 /* 45 */ @@ -56,8 +67,8 @@ #define TEGRA210_CLK_I2C5 47 #define TEGRA210_CLK_DSIA 48 /* 49 */ -#define TEGRA210_CLK_MIPI 50 -#define TEGRA210_CLK_HDMI 51 +/* 50 */ +/* 51 */ #define TEGRA210_CLK_CSI 52 /* 53 */ #define TEGRA210_CLK_I2C2 54 @@ -65,10 +76,10 @@ #define TEGRA210_CLK_MIPI_CAL 56 #define TEGRA210_CLK_EMC 57 #define TEGRA210_CLK_USB2 58 -#define TEGRA210_CLK_USB3 59 +/* 59 */ /* 60 */ -#define TEGRA210_CLK_VDE 61 -#define TEGRA210_CLK_BSEA 62 +/* 61 */ +/* 62 */ #define TEGRA210_CLK_BSEV 63 /* 64 */ @@ -83,8 +94,8 @@ #define TEGRA210_CLK_CSITE 73 /* 74 */ /* 75 */ -#define TEGRA210_CLK_LA 76 -#define TEGRA210_CLK_TRACE 77 +/* 76 */ +/* 77 */ #define TEGRA210_CLK_SOC_THERM 78 #define TEGRA210_CLK_DTV 79 /* 80 */ @@ -98,7 +109,7 @@ /* 88 */ #define TEGRA210_CLK_XUSB_HOST 89 /* 90 */ -#define TEGRA210_CLK_MSENC 91 +/* 91 */ #define TEGRA210_CLK_CSUS 92 /* 93 */ /* 94 */ @@ -112,20 +123,20 @@ #define TEGRA210_CLK_I2S3 101 #define TEGRA210_CLK_I2S4 102 #define TEGRA210_CLK_I2C4 103 -#define TEGRA210_CLK_SBC5 104 -#define TEGRA210_CLK_SBC6 105 +/* 104 */ +/* 105 */ #define TEGRA210_CLK_D_AUDIO 106 -#define TEGRA210_CLK_APBIF 107 -#define TEGRA210_CLK_DAM0 108 -#define TEGRA210_CLK_DAM1 109 -#define TEGRA210_CLK_DAM2 110 +#define TEGRA210_CLK_APB2APE 107 +/* 108 */ +/* 109 */ +/* 110 */ #define TEGRA210_CLK_HDA2CODEC_2X 111 /* 112 */ -#define TEGRA210_CLK_AUDIO0_2X 113 -#define TEGRA210_CLK_AUDIO1_2X 114 -#define TEGRA210_CLK_AUDIO2_2X 115 -#define TEGRA210_CLK_AUDIO3_2X 116 -#define TEGRA210_CLK_AUDIO4_2X 117 +/* 113 */ +/* 114 */ +/* 115 */ +/* 116 */ +/* 117 */ #define TEGRA210_CLK_SPDIF_2X 118 #define TEGRA210_CLK_ACTMON 119 #define TEGRA210_CLK_EXTERN1 120 @@ -135,10 +146,10 @@ #define TEGRA210_CLK_SATA 124 #define TEGRA210_CLK_HDA 125 /* 126 */ -#define TEGRA210_CLK_SE 127 +/* 127 */ #define TEGRA210_CLK_HDA2HDMI 128 -#define TEGRA210_CLK_SATA_COLD 129 +/* 129 */ /* 130 */ /* 131 */ /* 132 */ @@ -152,19 +163,19 @@ /* 140 */ /* 141 */ /* 142 */ -/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */ -/* xusb_host_src and xusb_ss_src) */ +/* (bit affects xusb_falcon_src, xusb_fs_src, xusb_host_src and xusb_ss_src) */ +#define TEGRA210_CLK_XUSB_GATE 143 #define TEGRA210_CLK_CILAB 144 #define TEGRA210_CLK_CILCD 145 #define TEGRA210_CLK_CILE 146 #define TEGRA210_CLK_DSIALP 147 #define TEGRA210_CLK_DSIBLP 148 #define TEGRA210_CLK_ENTROPY 149 -#define TEGRA210_CLK_DDS 150 +/* 150 */ /* 151 */ -#define TEGRA210_CLK_DP2 152 -#define TEGRA210_CLK_AMX 153 -#define TEGRA210_CLK_ADX 154 +/* 152 */ +/* 153 */ +/* 154 */ /* 155 (bit affects dfll_ref and dfll_soc) */ #define TEGRA210_CLK_XUSB_SS 156 /* 157 */ @@ -172,8 +183,8 @@ /* 159 */ /* 160 */ -/* 161 */ -/* 162 */ +#define TEGRA210_CLK_DMIC1 161 +#define TEGRA210_CLK_DMIC2 162 /* 163 */ /* 164 */ /* 165 */ @@ -184,159 +195,207 @@ /* 170 */ #define TEGRA210_CLK_VIM2_CLK 171 /* 172 */ -/* 173 */ +#define TEGRA210_CLK_MIPIBIF 173 /* 174 */ /* 175 */ -#define TEGRA210_CLK_HDMI_AUDIO 176 +/* 176 */ #define TEGRA210_CLK_CLK72MHZ 177 #define TEGRA210_CLK_VIC03 178 /* 179 */ -#define TEGRA210_CLK_ADX1 180 +/* 180 */ #define TEGRA210_CLK_DPAUX 181 #define TEGRA210_CLK_SOR0 182 -/* 183 */ +#define TEGRA210_CLK_SOR1 183 #define TEGRA210_CLK_GPU 184 -#define TEGRA210_CLK_AMX1 185 +#define TEGRA210_CLK_DBGAPB 185 /* 186 */ -/* 187 */ +#define TEGRA210_CLK_PLL_P_OUT_ADSP 187 /* 188 */ -/* 189 */ +#define TEGRA210_CLK_PLL_G_REF 189 /* 190 */ /* 191 */ -#define TEGRA210_CLK_UARTB 192 -#define TEGRA210_CLK_VFIR 193 -#define TEGRA210_CLK_SPDIF_IN 194 -#define TEGRA210_CLK_SPDIF_OUT 195 -#define TEGRA210_CLK_VI 196 -#define TEGRA210_CLK_VI_SENSOR 197 -#define TEGRA210_CLK_FUSE 198 -#define TEGRA210_CLK_FUSE_BURN 199 -#define TEGRA210_CLK_CLK_32K 200 -#define TEGRA210_CLK_CLK_M 201 -#define TEGRA210_CLK_CLK_M_DIV2 202 -#define TEGRA210_CLK_CLK_M_DIV4 203 -#define TEGRA210_CLK_PLL_REF 204 -#define TEGRA210_CLK_PLL_C 205 -#define TEGRA210_CLK_PLL_C_OUT1 206 -#define TEGRA210_CLK_PLL_C2 207 -#define TEGRA210_CLK_PLL_C3 208 -#define TEGRA210_CLK_PLL_M 209 -#define TEGRA210_CLK_PLL_M_OUT1 210 -#define TEGRA210_CLK_PLL_P 211 -#define TEGRA210_CLK_PLL_P_OUT1 212 -#define TEGRA210_CLK_PLL_P_OUT2 213 -#define TEGRA210_CLK_PLL_P_OUT3 214 -#define TEGRA210_CLK_PLL_P_OUT4 215 -#define TEGRA210_CLK_PLL_A 216 -#define TEGRA210_CLK_PLL_A_OUT0 217 -#define TEGRA210_CLK_PLL_D 218 -#define TEGRA210_CLK_PLL_D_OUT0 219 -#define TEGRA210_CLK_PLL_D2 220 -#define TEGRA210_CLK_PLL_D2_OUT0 221 -#define TEGRA210_CLK_PLL_U 222 -#define TEGRA210_CLK_PLL_U_480M 223 -#define TEGRA210_CLK_PLL_U_60M 224 -#define TEGRA210_CLK_PLL_U_48M 225 -#define TEGRA210_CLK_PLL_U_12M 226 -/* 227 */ -/* 228 */ -#define TEGRA210_CLK_PLL_RE_VCO 229 -#define TEGRA210_CLK_PLL_RE_OUT 230 -#define TEGRA210_CLK_PLL_E 231 -#define TEGRA210_CLK_SPDIF_IN_SYNC 232 -#define TEGRA210_CLK_I2S0_SYNC 233 -#define TEGRA210_CLK_I2S1_SYNC 234 -#define TEGRA210_CLK_I2S2_SYNC 235 -#define TEGRA210_CLK_I2S3_SYNC 236 -#define TEGRA210_CLK_I2S4_SYNC 237 -#define TEGRA210_CLK_VIMCLK_SYNC 238 -#define TEGRA210_CLK_AUDIO0 239 -#define TEGRA210_CLK_AUDIO1 240 -#define TEGRA210_CLK_AUDIO2 241 -#define TEGRA210_CLK_AUDIO3 242 -#define TEGRA210_CLK_AUDIO4 243 -#define TEGRA210_CLK_SPDIF 244 -#define TEGRA210_CLK_CLK_OUT_1 245 -#define TEGRA210_CLK_CLK_OUT_2 246 -#define TEGRA210_CLK_CLK_OUT_3 247 -#define TEGRA210_CLK_BLINK 248 -/* 249 */ -/* 250 */ -/* 251 */ -#define TEGRA210_CLK_XUSB_HOST_SRC 252 -#define TEGRA210_CLK_XUSB_FALCON_SRC 253 -#define TEGRA210_CLK_XUSB_FS_SRC 254 -#define TEGRA210_CLK_XUSB_SS_SRC 255 +/* 192 */ +#define TEGRA210_CLK_SDMMC_LEGACY 193 +#define TEGRA210_CLK_NVDEC 194 +#define TEGRA210_CLK_NVJPG 195 +/* 196 */ +#define TEGRA210_CLK_DMIC3 197 +#define TEGRA210_CLK_APE 198 +/* 199 */ +/* 200 */ +/* 201 */ +#define TEGRA210_CLK_MAUD 202 +/* 203 */ +/* 204 */ +/* 205 */ +#define TEGRA210_CLK_TSECB 206 +#define TEGRA210_CLK_DPAUX1 207 +#define TEGRA210_CLK_VI_I2C 208 +#define TEGRA210_CLK_HSIC_TRK 209 +#define TEGRA210_CLK_USB2_TRK 210 +#define TEGRA210_CLK_QSPI 211 +#define TEGRA210_CLK_UARTAPE 212 +/* 213 */ +/* 214 */ +/* 215 */ +/* 216 */ +/* 217 */ +/* 218 */ +#define TEGRA210_CLK_NVENC 219 +/* 220 */ +/* 221 */ +#define TEGRA210_CLK_SOR_SAFE 222 +#define TEGRA210_CLK_PLL_P_OUT_CPU 223 -#define TEGRA210_CLK_XUSB_DEV_SRC 256 -#define TEGRA210_CLK_XUSB_DEV 257 -#define TEGRA210_CLK_XUSB_HS_SRC 258 -#define TEGRA210_CLK_SCLK 259 -#define TEGRA210_CLK_HCLK 260 -#define TEGRA210_CLK_PCLK 261 -/* 262 */ -/* 263 */ -#define TEGRA210_CLK_DFLL_REF 264 -#define TEGRA210_CLK_DFLL_SOC 265 -#define TEGRA210_CLK_VI_SENSOR2 266 -#define TEGRA210_CLK_PLL_P_OUT5 267 -#define TEGRA210_CLK_CML0 268 -#define TEGRA210_CLK_CML1 269 -#define TEGRA210_CLK_PLL_C4 270 -#define TEGRA210_CLK_PLL_DP 271 -#define TEGRA210_CLK_PLL_E_MUX 272 -#define TEGRA210_CLK_PLLD_DSI 273 -/* 274 */ -/* 275 */ -/* 276 */ -/* 277 */ -/* 278 */ -/* 279 */ -/* 280 */ + +#define TEGRA210_CLK_UARTB 224 +#define TEGRA210_CLK_VFIR 225 +#define TEGRA210_CLK_SPDIF_IN 226 +#define TEGRA210_CLK_SPDIF_OUT 227 +#define TEGRA210_CLK_VI 228 +#define TEGRA210_CLK_VI_SENSOR 229 +#define TEGRA210_CLK_FUSE 230 +#define TEGRA210_CLK_FUSE_BURN 231 +#define TEGRA210_CLK_CLK_32K 232 +#define TEGRA210_CLK_CLK_M 233 +#define TEGRA210_CLK_CLK_M_DIV2 234 +#define TEGRA210_CLK_CLK_M_DIV4 235 +#define TEGRA210_CLK_PLL_REF 236 +#define TEGRA210_CLK_PLL_C 237 +#define TEGRA210_CLK_PLL_C_OUT1 238 +#define TEGRA210_CLK_PLL_C2 239 +#define TEGRA210_CLK_PLL_C3 240 +#define TEGRA210_CLK_PLL_M 241 +#define TEGRA210_CLK_PLL_M_OUT1 242 +#define TEGRA210_CLK_PLL_P 243 +#define TEGRA210_CLK_PLL_P_OUT1 244 +#define TEGRA210_CLK_PLL_P_OUT2 245 +#define TEGRA210_CLK_PLL_P_OUT3 246 +#define TEGRA210_CLK_PLL_P_OUT4 247 +#define TEGRA210_CLK_PLL_A 248 +#define TEGRA210_CLK_PLL_A_OUT0 249 +#define TEGRA210_CLK_PLL_D 250 +#define TEGRA210_CLK_PLL_D_OUT0 251 +#define TEGRA210_CLK_PLL_D2 252 +#define TEGRA210_CLK_PLL_D2_OUT0 253 +#define TEGRA210_CLK_PLL_U 254 +#define TEGRA210_CLK_PLL_U_480M 255 + +#define TEGRA210_CLK_PLL_U_60M 256 +#define TEGRA210_CLK_PLL_U_48M 257 +/* 258 */ +#define TEGRA210_CLK_PLL_X 259 +#define TEGRA210_CLK_PLL_X_OUT0 260 +#define TEGRA210_CLK_PLL_RE_VCO 261 +#define TEGRA210_CLK_PLL_RE_OUT 262 +#define TEGRA210_CLK_PLL_E 263 +#define TEGRA210_CLK_SPDIF_IN_SYNC 264 +#define TEGRA210_CLK_I2S0_SYNC 265 +#define TEGRA210_CLK_I2S1_SYNC 266 +#define TEGRA210_CLK_I2S2_SYNC 267 +#define TEGRA210_CLK_I2S3_SYNC 268 +#define TEGRA210_CLK_I2S4_SYNC 269 +#define TEGRA210_CLK_VIMCLK_SYNC 270 +#define TEGRA210_CLK_AUDIO0 271 +#define TEGRA210_CLK_AUDIO1 272 +#define TEGRA210_CLK_AUDIO2 273 +#define TEGRA210_CLK_AUDIO3 274 +#define TEGRA210_CLK_AUDIO4 275 +#define TEGRA210_CLK_SPDIF 276 +#define TEGRA210_CLK_CLK_OUT_1 277 +#define TEGRA210_CLK_CLK_OUT_2 278 +#define TEGRA210_CLK_CLK_OUT_3 279 +#define TEGRA210_CLK_BLINK 280 /* 281 */ /* 282 */ /* 283 */ -/* 284 */ -/* 285 */ -/* 286 */ -/* 287 */ - -/* 288 */ -/* 289 */ -/* 290 */ -/* 291 */ -/* 292 */ -/* 293 */ -/* 294 */ -/* 295 */ -/* 296 */ -/* 297 */ -/* 298 */ -/* 299 */ -#define TEGRA210_CLK_AUDIO0_MUX 300 -#define TEGRA210_CLK_AUDIO1_MUX 301 -#define TEGRA210_CLK_AUDIO2_MUX 302 -#define TEGRA210_CLK_AUDIO3_MUX 303 -#define TEGRA210_CLK_AUDIO4_MUX 304 -#define TEGRA210_CLK_SPDIF_MUX 305 -#define TEGRA210_CLK_CLK_OUT_1_MUX 306 -#define TEGRA210_CLK_CLK_OUT_2_MUX 307 -#define TEGRA210_CLK_CLK_OUT_3_MUX 308 -/* 309 */ -/* 310 */ -#define TEGRA210_CLK_SOR0_LVDS 311 -#define TEGRA210_CLK_XUSB_SS_DIV2 312 +#define TEGRA210_CLK_XUSB_HOST_SRC 284 +#define TEGRA210_CLK_XUSB_FALCON_SRC 285 +#define TEGRA210_CLK_XUSB_FS_SRC 286 +#define TEGRA210_CLK_XUSB_SS_SRC 287 -#define TEGRA210_CLK_PLL_M_UD 313 -#define TEGRA210_CLK_PLL_C_UD 314 +#define TEGRA210_CLK_XUSB_DEV_SRC 288 +#define TEGRA210_CLK_XUSB_DEV 289 +#define TEGRA210_CLK_XUSB_HS_SRC 290 +#define TEGRA210_CLK_SCLK 291 +#define TEGRA210_CLK_HCLK 292 +#define TEGRA210_CLK_PCLK 293 +#define TEGRA210_CLK_CCLK_G 294 +#define TEGRA210_CLK_CCLK_LP 295 +#define TEGRA210_CLK_DFLL_REF 296 +#define TEGRA210_CLK_DFLL_SOC 297 +#define TEGRA210_CLK_VI_SENSOR2 298 +#define TEGRA210_CLK_PLL_P_OUT5 299 +#define TEGRA210_CLK_CML0 300 +#define TEGRA210_CLK_CML1 301 +#define TEGRA210_CLK_PLL_C4 302 +#define TEGRA210_CLK_PLL_DP 303 +#define TEGRA210_CLK_PLL_E_MUX 304 +#define TEGRA210_CLK_PLL_MB 305 +#define TEGRA210_CLK_PLL_A1 306 +#define TEGRA210_CLK_PLL_D_DSI_OUT 307 +#define TEGRA210_CLK_PLL_C4_OUT0 308 +#define TEGRA210_CLK_PLL_C4_OUT1 309 +#define TEGRA210_CLK_PLL_C4_OUT2 310 +#define TEGRA210_CLK_PLL_C4_OUT3 311 +#define TEGRA210_CLK_PLL_U_OUT 312 +#define TEGRA210_CLK_PLL_U_OUT1 313 +#define TEGRA210_CLK_PLL_U_OUT2 314 +#define TEGRA210_CLK_USB2_HSIC_TRK 315 +#define TEGRA210_CLK_PLL_P_OUT_HSIO 316 +#define TEGRA210_CLK_PLL_P_OUT_XUSB 317 +#define TEGRA210_CLK_XUSB_SSP_SRC 318 +/* 319 */ +/* 320 */ +/* 321 */ +/* 322 */ +/* 323 */ +/* 324 */ +/* 325 */ +/* 326 */ +/* 327 */ +/* 328 */ +/* 329 */ +/* 330 */ +/* 331 */ +/* 332 */ +/* 333 */ +/* 334 */ +/* 335 */ +/* 336 */ +/* 337 */ +/* 338 */ +/* 339 */ +/* 340 */ +/* 341 */ +/* 342 */ +/* 343 */ +/* 344 */ +/* 345 */ +/* 346 */ +/* 347 */ +/* 348 */ +/* 349 */ -#define TEGRA210_CLK_PLL_X 227 -#define TEGRA210_CLK_PLL_X_OUT0 228 +#define TEGRA210_CLK_AUDIO0_MUX 350 +#define TEGRA210_CLK_AUDIO1_MUX 351 +#define TEGRA210_CLK_AUDIO2_MUX 352 +#define TEGRA210_CLK_AUDIO3_MUX 353 +#define TEGRA210_CLK_AUDIO4_MUX 354 +#define TEGRA210_CLK_SPDIF_MUX 355 +#define TEGRA210_CLK_CLK_OUT_1_MUX 356 +#define TEGRA210_CLK_CLK_OUT_2_MUX 357 +#define TEGRA210_CLK_CLK_OUT_3_MUX 358 +#define TEGRA210_CLK_DSIA_MUX 359 +#define TEGRA210_CLK_DSIB_MUX 360 +#define TEGRA210_CLK_SOR0_LVDS 361 +#define TEGRA210_CLK_XUSB_SS_DIV2 362 -#define TEGRA210_CLK_CCLK_G 262 -#define TEGRA210_CLK_CCLK_LP 263 +#define TEGRA210_CLK_PLL_M_UD 363 +#define TEGRA210_CLK_PLL_C_UD 364 +#define TEGRA210_CLK_SCLK_MUX 365 -#define TEGRA210_CLK_CLK_MAX 315 +#define TEGRA210_CLK_CLK_MAX 366 -#endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */ +#endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */ diff --git a/include/dt-bindings/mailbox/tegra-hsp.h b/include/dt-bindings/mailbox/tegra-hsp.h deleted file mode 100644 index e8c23fa91d23..000000000000 --- a/include/dt-bindings/mailbox/tegra-hsp.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * This header provides constants for binding nvidia,tegra186-hsp. - * - * The number with TEGRA_HSP_MASTER prefix indicates the bit that is - * associated with a master ID in the doorbell registers. - */ - -#ifndef _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H -#define _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H - -#define TEGRA_HSP_MASTER_CCPLEX 17 -#define TEGRA_HSP_MASTER_BPMP 19 - -#endif diff --git a/include/dt-bindings/mailbox/tegra186-hsp.h b/include/dt-bindings/mailbox/tegra186-hsp.h new file mode 100644 index 000000000000..b4864325d74b --- /dev/null +++ b/include/dt-bindings/mailbox/tegra186-hsp.h @@ -0,0 +1,19 @@ +/* + * This header provides constants for binding nvidia,tegra186-hsp. + * + * The number with HSP_DB_MASTER prefix indicates the bit that is + * associated with a master ID in the doorbell registers. + */ + +#ifndef _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H +#define _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H + +#define HSP_MBOX_TYPE_DB 0x0 +#define HSP_MBOX_TYPE_SM 0x1 +#define HSP_MBOX_TYPE_SS 0x2 +#define HSP_MBOX_TYPE_AS 0x3 + +#define HSP_DB_MASTER_CCPLEX 17 +#define HSP_DB_MASTER_BPMP 19 + +#endif diff --git a/include/dt-bindings/power/tegra186-powergate.h b/include/dt-bindings/power/tegra186-powergate.h new file mode 100644 index 000000000000..70630c6ea768 --- /dev/null +++ b/include/dt-bindings/power/tegra186-powergate.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2015-2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H +#define _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H + +#define TEGRA186_POWER_DOMAIN_AUD 0 +#define TEGRA186_POWER_DOMAIN_DFD 1 +#define TEGRA186_POWER_DOMAIN_DISP 2 +#define TEGRA186_POWER_DOMAIN_DISPB 3 +#define TEGRA186_POWER_DOMAIN_DISPC 4 +#define TEGRA186_POWER_DOMAIN_ISPA 5 +#define TEGRA186_POWER_DOMAIN_NVDEC 6 +#define TEGRA186_POWER_DOMAIN_NVJPG 7 +#define TEGRA186_POWER_DOMAIN_MPE 8 +#define TEGRA186_POWER_DOMAIN_PCX 9 +#define TEGRA186_POWER_DOMAIN_SAX 10 +#define TEGRA186_POWER_DOMAIN_VE 11 +#define TEGRA186_POWER_DOMAIN_VIC 12 +#define TEGRA186_POWER_DOMAIN_XUSBA 13 +#define TEGRA186_POWER_DOMAIN_XUSBB 14 +#define TEGRA186_POWER_DOMAIN_XUSBC 15 +#define TEGRA186_POWER_DOMAIN_GPU 43 +#define TEGRA186_POWER_DOMAIN_MAX 44 + +#endif diff --git a/include/dt-bindings/reset/tegra186-reset.h b/include/dt-bindings/reset/tegra186-reset.h new file mode 100644 index 000000000000..26b4ba9b0a57 --- /dev/null +++ b/include/dt-bindings/reset/tegra186-reset.h @@ -0,0 +1,206 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ABI_MACH_T186_RESET_T186_H_ +#define _ABI_MACH_T186_RESET_T186_H_ + +#define TEGRA186_RESET_ACTMON 0 +#define TEGRA186_RESET_AFI 1 +#define TEGRA186_RESET_CEC 2 +#define TEGRA186_RESET_CSITE 3 +#define TEGRA186_RESET_DP2 4 +#define TEGRA186_RESET_DPAUX 5 +#define TEGRA186_RESET_DSI 6 +#define TEGRA186_RESET_DSIB 7 +#define TEGRA186_RESET_DTV 8 +#define TEGRA186_RESET_DVFS 9 +#define TEGRA186_RESET_ENTROPY 10 +#define TEGRA186_RESET_EXTPERIPH1 11 +#define TEGRA186_RESET_EXTPERIPH2 12 +#define TEGRA186_RESET_EXTPERIPH3 13 +#define TEGRA186_RESET_GPU 14 +#define TEGRA186_RESET_HDA 15 +#define TEGRA186_RESET_HDA2CODEC_2X 16 +#define TEGRA186_RESET_HDA2HDMICODEC 17 +#define TEGRA186_RESET_HOST1X 18 +#define TEGRA186_RESET_I2C1 19 +#define TEGRA186_RESET_I2C2 20 +#define TEGRA186_RESET_I2C3 21 +#define TEGRA186_RESET_I2C4 22 +#define TEGRA186_RESET_I2C5 23 +#define TEGRA186_RESET_I2C6 24 +#define TEGRA186_RESET_ISP 25 +#define TEGRA186_RESET_KFUSE 26 +#define TEGRA186_RESET_LA 27 +#define TEGRA186_RESET_MIPI_CAL 28 +#define TEGRA186_RESET_PCIE 29 +#define TEGRA186_RESET_PCIEXCLK 30 +#define TEGRA186_RESET_SATA 31 +#define TEGRA186_RESET_SATACOLD 32 +#define TEGRA186_RESET_SDMMC1 33 +#define TEGRA186_RESET_SDMMC2 34 +#define TEGRA186_RESET_SDMMC3 35 +#define TEGRA186_RESET_SDMMC4 36 +#define TEGRA186_RESET_SE 37 +#define TEGRA186_RESET_SOC_THERM 38 +#define TEGRA186_RESET_SOR0 39 +#define TEGRA186_RESET_SPI1 40 +#define TEGRA186_RESET_SPI2 41 +#define TEGRA186_RESET_SPI3 42 +#define TEGRA186_RESET_SPI4 43 +#define TEGRA186_RESET_TMR 44 +#define TEGRA186_RESET_TRIG_SYS 45 +#define TEGRA186_RESET_TSEC 46 +#define TEGRA186_RESET_UARTA 47 +#define TEGRA186_RESET_UARTB 48 +#define TEGRA186_RESET_UARTC 49 +#define TEGRA186_RESET_UARTD 50 +#define TEGRA186_RESET_VI 51 +#define TEGRA186_RESET_VIC 52 +#define TEGRA186_RESET_XUSB_DEV 53 +#define TEGRA186_RESET_XUSB_HOST 54 +#define TEGRA186_RESET_XUSB_PADCTL 55 +#define TEGRA186_RESET_XUSB_SS 56 +#define TEGRA186_RESET_AON_APB 57 +#define TEGRA186_RESET_AXI_CBB 58 +#define TEGRA186_RESET_BPMP_APB 59 +#define TEGRA186_RESET_CAN1 60 +#define TEGRA186_RESET_CAN2 61 +#define TEGRA186_RESET_DMIC5 62 +#define TEGRA186_RESET_DSIC 63 +#define TEGRA186_RESET_DSID 64 +#define TEGRA186_RESET_EMC_EMC 65 +#define TEGRA186_RESET_EMC_MEM 66 +#define TEGRA186_RESET_EMCSB_EMC 67 +#define TEGRA186_RESET_EMCSB_MEM 68 +#define TEGRA186_RESET_EQOS 69 +#define TEGRA186_RESET_GPCDMA 70 +#define TEGRA186_RESET_GPIO_CTL0 71 +#define TEGRA186_RESET_GPIO_CTL1 72 +#define TEGRA186_RESET_GPIO_CTL2 73 +#define TEGRA186_RESET_GPIO_CTL3 74 +#define TEGRA186_RESET_GPIO_CTL4 75 +#define TEGRA186_RESET_GPIO_CTL5 76 +#define TEGRA186_RESET_I2C10 77 +#define TEGRA186_RESET_I2C12 78 +#define TEGRA186_RESET_I2C13 79 +#define TEGRA186_RESET_I2C14 80 +#define TEGRA186_RESET_I2C7 81 +#define TEGRA186_RESET_I2C8 82 +#define TEGRA186_RESET_I2C9 83 +#define TEGRA186_RESET_JTAG2AXI 84 +#define TEGRA186_RESET_MPHY_IOBIST 85 +#define TEGRA186_RESET_MPHY_L0_RX 86 +#define TEGRA186_RESET_MPHY_L0_TX 87 +#define TEGRA186_RESET_NVCSI 88 +#define TEGRA186_RESET_NVDISPLAY0_HEAD0 89 +#define TEGRA186_RESET_NVDISPLAY0_HEAD1 90 +#define TEGRA186_RESET_NVDISPLAY0_HEAD2 91 +#define TEGRA186_RESET_NVDISPLAY0_MISC 92 +#define TEGRA186_RESET_NVDISPLAY0_WGRP0 93 +#define TEGRA186_RESET_NVDISPLAY0_WGRP1 94 +#define TEGRA186_RESET_NVDISPLAY0_WGRP2 95 +#define TEGRA186_RESET_NVDISPLAY0_WGRP3 96 +#define TEGRA186_RESET_NVDISPLAY0_WGRP4 97 +#define TEGRA186_RESET_NVDISPLAY0_WGRP5 98 +#define TEGRA186_RESET_PWM1 99 +#define TEGRA186_RESET_PWM2 100 +#define TEGRA186_RESET_PWM3 101 +#define TEGRA186_RESET_PWM4 102 +#define TEGRA186_RESET_PWM5 103 +#define TEGRA186_RESET_PWM6 104 +#define TEGRA186_RESET_PWM7 105 +#define TEGRA186_RESET_PWM8 106 +#define TEGRA186_RESET_SCE_APB 107 +#define TEGRA186_RESET_SOR1 108 +#define TEGRA186_RESET_TACH 109 +#define TEGRA186_RESET_TSC 110 +#define TEGRA186_RESET_UARTF 111 +#define TEGRA186_RESET_UARTG 112 +#define TEGRA186_RESET_UFSHC 113 +#define TEGRA186_RESET_UFSHC_AXI_M 114 +#define TEGRA186_RESET_UPHY 115 +#define TEGRA186_RESET_ADSP 116 +#define TEGRA186_RESET_ADSPDBG 117 +#define TEGRA186_RESET_ADSPINTF 118 +#define TEGRA186_RESET_ADSPNEON 119 +#define TEGRA186_RESET_ADSPPERIPH 120 +#define TEGRA186_RESET_ADSPSCU 121 +#define TEGRA186_RESET_ADSPWDT 122 +#define TEGRA186_RESET_APE 123 +#define TEGRA186_RESET_DPAUX1 124 +#define TEGRA186_RESET_NVDEC 125 +#define TEGRA186_RESET_NVENC 126 +#define TEGRA186_RESET_NVJPG 127 +#define TEGRA186_RESET_PEX_USB_UPHY 128 +#define TEGRA186_RESET_QSPI 129 +#define TEGRA186_RESET_TSECB 130 +#define TEGRA186_RESET_VI_I2C 131 +#define TEGRA186_RESET_UARTE 132 +#define TEGRA186_RESET_TOP_GTE 133 +#define TEGRA186_RESET_SHSP 134 +#define TEGRA186_RESET_PEX_USB_UPHY_L5 135 +#define TEGRA186_RESET_PEX_USB_UPHY_L4 136 +#define TEGRA186_RESET_PEX_USB_UPHY_L3 137 +#define TEGRA186_RESET_PEX_USB_UPHY_L2 138 +#define TEGRA186_RESET_PEX_USB_UPHY_L1 139 +#define TEGRA186_RESET_PEX_USB_UPHY_L0 140 +#define TEGRA186_RESET_PEX_USB_UPHY_PLL1 141 +#define TEGRA186_RESET_PEX_USB_UPHY_PLL0 142 +#define TEGRA186_RESET_TSCTNVI 143 +#define TEGRA186_RESET_EXTPERIPH4 144 +#define TEGRA186_RESET_DSIPADCTL 145 +#define TEGRA186_RESET_AUD_MCLK 146 +#define TEGRA186_RESET_MPHY_CLK_CTL 147 +#define TEGRA186_RESET_MPHY_L1_RX 148 +#define TEGRA186_RESET_MPHY_L1_TX 149 +#define TEGRA186_RESET_UFSHC_LP 150 +#define TEGRA186_RESET_BPMP_NIC 151 +#define TEGRA186_RESET_BPMP_NSYSPORESET 152 +#define TEGRA186_RESET_BPMP_NRESET 153 +#define TEGRA186_RESET_BPMP_DBGRESETN 154 +#define TEGRA186_RESET_BPMP_PRESETDBGN 155 +#define TEGRA186_RESET_BPMP_PM 156 +#define TEGRA186_RESET_BPMP_CVC 157 +#define TEGRA186_RESET_BPMP_DMA 158 +#define TEGRA186_RESET_BPMP_HSP 159 +#define TEGRA186_RESET_TSCTNBPMP 160 +#define TEGRA186_RESET_BPMP_TKE 161 +#define TEGRA186_RESET_BPMP_GTE 162 +#define TEGRA186_RESET_BPMP_PM_ACTMON 163 +#define TEGRA186_RESET_AON_NIC 164 +#define TEGRA186_RESET_AON_NSYSPORESET 165 +#define TEGRA186_RESET_AON_NRESET 166 +#define TEGRA186_RESET_AON_DBGRESETN 167 +#define TEGRA186_RESET_AON_PRESETDBGN 168 +#define TEGRA186_RESET_AON_ACTMON 169 +#define TEGRA186_RESET_AOPM 170 +#define TEGRA186_RESET_AOVC 171 +#define TEGRA186_RESET_AON_DMA 172 +#define TEGRA186_RESET_AON_GPIO 173 +#define TEGRA186_RESET_AON_HSP 174 +#define TEGRA186_RESET_TSCTNAON 175 +#define TEGRA186_RESET_AON_TKE 176 +#define TEGRA186_RESET_AON_GTE 177 +#define TEGRA186_RESET_SCE_NIC 178 +#define TEGRA186_RESET_SCE_NSYSPORESET 179 +#define TEGRA186_RESET_SCE_NRESET 180 +#define TEGRA186_RESET_SCE_DBGRESETN 181 +#define TEGRA186_RESET_SCE_PRESETDBGN 182 +#define TEGRA186_RESET_SCE_ACTMON 183 +#define TEGRA186_RESET_SCE_PM 184 +#define TEGRA186_RESET_SCE_DMA 185 +#define TEGRA186_RESET_SCE_HSP 186 +#define TEGRA186_RESET_TSCTNSCE 187 +#define TEGRA186_RESET_SCE_TKE 188 +#define TEGRA186_RESET_SCE_GTE 189 +#define TEGRA186_RESET_SCE_CFG 190 +#define TEGRA186_RESET_ADSP_ALL 191 +/** @brief controls the power up/down sequence of UFSHC PSW partition. Controls LP_PWR_READY, LP_ISOL_EN, and LP_RESET_N signals */ +#define TEGRA186_RESET_UFSHC_LP_SEQ 192 +#define TEGRA186_RESET_SIZE 193 + +#endif diff --git a/include/ext4fs.h b/include/ext4fs.h index cc765ae468af..884f00d95537 100644 --- a/include/ext4fs.h +++ b/include/ext4fs.h @@ -28,10 +28,12 @@ #define __EXT4__ #include +#define EXT4_INDEX_FL 0x00001000 /* Inode uses hash tree index */ #define EXT4_EXTENTS_FL 0x00080000 /* Inode uses extents */ #define EXT4_EXT_MAGIC 0xf30a #define EXT4_FEATURE_RO_COMPAT_GDT_CSUM 0x0010 #define EXT4_FEATURE_INCOMPAT_EXTENTS 0x0040 +#define EXT4_FEATURE_INCOMPAT_64BIT 0x0080 #define EXT4_INDIRECT_BLOCKS 12 #define EXT4_BG_INODE_UNINIT 0x0001 @@ -85,6 +87,8 @@ struct ext_filesystem { uint32_t inodesz; /* Sectors per Block */ uint32_t sect_perblk; + /* Group Descriptor size */ + uint16_t gdsize; /* Group Descriptor Block Number */ uint32_t gdtable_blkno; /* Total block groups of partition */ @@ -94,7 +98,6 @@ struct ext_filesystem { /* Superblock */ struct ext2_sblock *sb; /* Block group descritpor table */ - struct ext2_block_group *bgd; char *gdtable; /* Block Bitmap Related */ @@ -113,6 +116,12 @@ struct ext_filesystem { struct blk_desc *dev_desc; }; +struct ext_block_cache { + char *buf; + lbaint_t block; + int size; +}; + extern struct ext2_data *ext4fs_root; extern struct ext2fs_node *ext4fs_file; @@ -123,7 +132,7 @@ extern int gindex; int ext4fs_init(void); void ext4fs_deinit(void); -int ext4fs_filename_check(char *filename); +int ext4fs_filename_unlink(char *filename); int ext4fs_write(const char *fname, unsigned char *buffer, unsigned long sizebytes); int ext4_write_file(const char *filename, void *buf, loff_t offset, loff_t len, @@ -142,11 +151,15 @@ int ext4fs_size(const char *filename, loff_t *size); void ext4fs_free_node(struct ext2fs_node *node, struct ext2fs_node *currroot); int ext4fs_devread(lbaint_t sector, int byte_offset, int byte_len, char *buf); void ext4fs_set_blk_dev(struct blk_desc *rbdd, disk_partition_t *info); -long int read_allocated_block(struct ext2_inode *inode, int fileblock); +long int read_allocated_block(struct ext2_inode *inode, int fileblock, + struct ext_block_cache *cache); int ext4fs_probe(struct blk_desc *fs_dev_desc, disk_partition_t *fs_partition); int ext4_read_file(const char *filename, void *buf, loff_t offset, loff_t len, loff_t *actread); int ext4_read_superblock(char *buffer); int ext4fs_uuid(char *uuid_str); +void ext_cache_init(struct ext_block_cache *cache); +void ext_cache_fini(struct ext_block_cache *cache); +int ext_cache_read(struct ext_block_cache *cache, lbaint_t block, int size); #endif diff --git a/include/ext_common.h b/include/ext_common.h index 6cddf166d947..07b61fa56bdd 100644 --- a/include/ext_common.h +++ b/include/ext_common.h @@ -49,11 +49,9 @@ #define EXT2_BLOCK_SIZE(data) (1 << LOG2_BLOCK_SIZE(data)) /* Log2 size of ext2 block in bytes. */ -#define LOG2_BLOCK_SIZE(data) (__le32_to_cpu \ +#define LOG2_BLOCK_SIZE(data) (le32_to_cpu \ (data->sblock.log2_block_size) \ + EXT2_MIN_BLOCK_LOG_SIZE) -#define INODE_SIZE_FILESYSTEM(data) (__le32_to_cpu \ - (data->sblock.inode_size)) #define EXT2_FT_DIR 2 #define SUCCESS 1 @@ -66,92 +64,134 @@ /* The ext2 superblock. */ struct ext2_sblock { - uint32_t total_inodes; - uint32_t total_blocks; - uint32_t reserved_blocks; - uint32_t free_blocks; - uint32_t free_inodes; - uint32_t first_data_block; - uint32_t log2_block_size; - uint32_t log2_fragment_size; - uint32_t blocks_per_group; - uint32_t fragments_per_group; - uint32_t inodes_per_group; - uint32_t mtime; - uint32_t utime; - uint16_t mnt_count; - uint16_t max_mnt_count; - uint16_t magic; - uint16_t fs_state; - uint16_t error_handling; - uint16_t minor_revision_level; - uint32_t lastcheck; - uint32_t checkinterval; - uint32_t creator_os; - uint32_t revision_level; - uint16_t uid_reserved; - uint16_t gid_reserved; - uint32_t first_inode; - uint16_t inode_size; - uint16_t block_group_number; - uint32_t feature_compatibility; - uint32_t feature_incompat; - uint32_t feature_ro_compat; - uint32_t unique_id[4]; + __le32 total_inodes; + __le32 total_blocks; + __le32 reserved_blocks; + __le32 free_blocks; + __le32 free_inodes; + __le32 first_data_block; + __le32 log2_block_size; + __le32 log2_fragment_size; + __le32 blocks_per_group; + __le32 fragments_per_group; + __le32 inodes_per_group; + __le32 mtime; + __le32 utime; + __le16 mnt_count; + __le16 max_mnt_count; + __le16 magic; + __le16 fs_state; + __le16 error_handling; + __le16 minor_revision_level; + __le32 lastcheck; + __le32 checkinterval; + __le32 creator_os; + __le32 revision_level; + __le16 uid_reserved; + __le16 gid_reserved; + __le32 first_inode; + __le16 inode_size; + __le16 block_group_number; + __le32 feature_compatibility; + __le32 feature_incompat; + __le32 feature_ro_compat; + __le32 unique_id[4]; char volume_name[16]; char last_mounted_on[64]; - uint32_t compression_info; + __le32 compression_info; + uint8_t prealloc_blocks; + uint8_t prealloc_dir_blocks; + __le16 reserved_gdt_blocks; + uint8_t journal_uuid[16]; + __le32 journal_inode; + __le32 journal_dev; + __le32 last_orphan; + __le32 hash_seed[4]; + uint8_t default_hash_version; + uint8_t journal_backup_type; + __le16 descriptor_size; + __le32 default_mount_options; + __le32 first_meta_block_group; + __le32 mkfs_time; + __le32 journal_blocks[17]; + __le32 total_blocks_high; + __le32 reserved_blocks_high; + __le32 free_blocks_high; + __le16 min_extra_inode_size; + __le16 want_extra_inode_size; + __le32 flags; + __le16 raid_stride; + __le16 mmp_interval; + __le64 mmp_block; + __le32 raid_stripe_width; + uint8_t log2_groups_per_flex; + uint8_t checksum_type; }; struct ext2_block_group { - __u32 block_id; /* Blocks bitmap block */ - __u32 inode_id; /* Inodes bitmap block */ - __u32 inode_table_id; /* Inodes table block */ - __u16 free_blocks; /* Free blocks count */ - __u16 free_inodes; /* Free inodes count */ - __u16 used_dir_cnt; /* Directories count */ - __u16 bg_flags; - __u32 bg_reserved[2]; - __u16 bg_itable_unused; /* Unused inodes count */ - __u16 bg_checksum; /* crc16(s_uuid+grouo_num+group_desc)*/ + __le32 block_id; /* Blocks bitmap block */ + __le32 inode_id; /* Inodes bitmap block */ + __le32 inode_table_id; /* Inodes table block */ + __le16 free_blocks; /* Free blocks count */ + __le16 free_inodes; /* Free inodes count */ + __le16 used_dir_cnt; /* Directories count */ + __le16 bg_flags; + __le32 bg_exclude_bitmap; + __le16 bg_block_id_csum; + __le16 bg_inode_id_csum; + __le16 bg_itable_unused; /* Unused inodes count */ + __le16 bg_checksum; /* crc16(s_uuid+group_num+group_desc)*/ + /* following fields only exist if descriptor size is 64 */ + __le32 block_id_high; + __le32 inode_id_high; + __le32 inode_table_id_high; + __le16 free_blocks_high; + __le16 free_inodes_high; + __le16 used_dir_cnt_high; + __le16 bg_itable_unused_high; + __le32 bg_exclude_bitmap_high; + __le16 bg_block_id_csum_high; + __le16 bg_inode_id_csum_high; + __le32 bg_reserved; }; /* The ext2 inode. */ struct ext2_inode { - uint16_t mode; - uint16_t uid; - uint32_t size; - uint32_t atime; - uint32_t ctime; - uint32_t mtime; - uint32_t dtime; - uint16_t gid; - uint16_t nlinks; - uint32_t blockcnt; /* Blocks of 512 bytes!! */ - uint32_t flags; - uint32_t osd1; + __le16 mode; + __le16 uid; + __le32 size; + __le32 atime; + __le32 ctime; + __le32 mtime; + __le32 dtime; + __le16 gid; + __le16 nlinks; + __le32 blockcnt; /* Blocks of either 512 or block_size bytes */ + __le32 flags; + __le32 osd1; union { struct datablocks { - uint32_t dir_blocks[INDIRECT_BLOCKS]; - uint32_t indir_block; - uint32_t double_indir_block; - uint32_t triple_indir_block; + __le32 dir_blocks[INDIRECT_BLOCKS]; + __le32 indir_block; + __le32 double_indir_block; + __le32 triple_indir_block; } blocks; char symlink[60]; + char inline_data[60]; } b; - uint32_t version; - uint32_t acl; - uint32_t dir_acl; - uint32_t fragment_addr; - uint32_t osd2[3]; + __le32 version; + __le32 acl; + __le32 size_high; /* previously dir_acl, but never used */ + __le32 fragment_addr; + __le32 osd2[3]; }; /* The header of an ext2 directory entry. */ struct ext2_dirent { - uint32_t inode; - uint16_t direntlen; - uint8_t namelen; - uint8_t filetype; + __le32 inode; + __le16 direntlen; + __u8 namelen; + __u8 filetype; }; struct ext2fs_node { diff --git a/include/image.h b/include/image.h index d788c260e30a..a07e1b6539ca 100644 --- a/include/image.h +++ b/include/image.h @@ -50,8 +50,8 @@ struct lmb; #if IMAGE_ENABLE_FIT #include -#include -#include +#include "../lib/libfdt/libfdt.h" +#include "../lib/libfdt/fdt_support.h" # ifdef CONFIG_SPL_BUILD # ifdef CONFIG_SPL_CRC32_SUPPORT # define IMAGE_ENABLE_CRC32 1 diff --git a/include/misc.h b/include/misc.h index 2b788143b54c..03ef55cdc887 100644 --- a/include/misc.h +++ b/include/misc.h @@ -37,6 +37,27 @@ int misc_write(struct udevice *dev, int offset, void *buf, int size); */ int misc_ioctl(struct udevice *dev, unsigned long request, void *buf); +/* + * Send a message to the device and wait for a response. + * + * The caller provides the message type/ID and payload to be sent. + * The callee constructs any message header required, transmits it to the + * target, waits for a response, checks any error code in the response, + * strips any message header from the response, and returns the error code + * (or a parsed version of it) and the response message payload. + * + * @dev: the device. + * @msgid: the message ID/number to send. + * tx_msg: the request/transmit message payload. + * tx_size: the size of the buffer pointed at by tx_msg. + * rx_msg: the buffer to receive the response message payload. May be NULL if + * the caller only cares about the error code. + * rx_size: the size of the buffer pointed at by rx_msg. + * @return the response message size if OK, -ve on error + */ +int misc_call(struct udevice *dev, int msgid, void *tx_msg, int tx_size, + void *rx_msg, int rx_size); + /* * struct misc_ops - Driver model Misc operations * @@ -74,6 +95,20 @@ struct misc_ops { * @return: 0 if OK, -ve on error */ int (*ioctl)(struct udevice *dev, unsigned long request, void *buf); + /* + * Send a message to the device and wait for a response. + * + * @dev: the device + * @msgid: the message ID/number to send + * tx_msg: the request/transmit message payload + * tx_size: the size of the buffer pointed at by tx_msg + * rx_msg: the buffer to receive the response message payload. May be + * NULL if the caller only cares about the error code. + * rx_size: the size of the buffer pointed at by rx_msg + * @return the response message size if OK, -ve on error + */ + int (*call)(struct udevice *dev, int msgid, void *tx_msg, int tx_size, + void *rx_msg, int rx_size); }; #endif /* _MISC_H_ */ diff --git a/include/power-domain-uclass.h b/include/power-domain-uclass.h new file mode 100644 index 000000000000..5878021e32c2 --- /dev/null +++ b/include/power-domain-uclass.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _POWER_DOMAIN_UCLASS_H +#define _POWER_DOMAIN_UCLASS_H + +/* See power-domain.h for background documentation. */ + +#include + +struct udevice; + +/** + * struct power_domain_ops - The functions that a power domain controller driver + * must implement. + */ +struct power_domain_ops { + /** + * of_xlate - Translate a client's device-tree (OF) power domain + * specifier. + * + * The power domain core calls this function as the first step in + * implementing a client's power_domain_get() call. + * + * If this function pointer is set to NULL, the power domain core will + * use a default implementation, which assumes #power-domain-cells = + * <1>, and that the DT cell contains a simple integer power domain ID. + * + * At present, the power domain API solely supports device-tree. If + * this changes, other xxx_xlate() functions may be added to support + * those other mechanisms. + * + * @power_domain: The power domain struct to hold the + * translation result. + * @args: The power domain specifier values from device + * tree. + * @return 0 if OK, or a negative error code. + */ + int (*of_xlate)(struct power_domain *power_domain, + struct fdtdec_phandle_args *args); + /** + * request - Request a translated power domain. + * + * The power domain core calls this function as the second step in + * implementing a client's power_domain_get() call, following a + * successful xxx_xlate() call. + * + * @power_domain: The power domain to request; this has been + * filled in by a previous xxx_xlate() function + * call. + * @return 0 if OK, or a negative error code. + */ + int (*request)(struct power_domain *power_domain); + /** + * free - Free a previously requested power domain. + * + * This is the implementation of the client power_domain_free() API. + * + * @power_domain: The power domain to free. + * @return 0 if OK, or a negative error code. + */ + int (*free)(struct power_domain *power_domain); + /** + * on - Power on a power domain. + * + * @power_domain: The power domain to turn on. + * @return 0 if OK, or a negative error code. + */ + int (*on)(struct power_domain *power_domain); + /** + * off - Power off a power domain. + * + * @power_domain: The power domain to turn off. + * @return 0 if OK, or a negative error code. + */ + int (*off)(struct power_domain *power_domain); +}; + +#endif diff --git a/include/power-domain.h b/include/power-domain.h new file mode 100644 index 000000000000..10999790b568 --- /dev/null +++ b/include/power-domain.h @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _POWER_DOMAIN_H +#define _POWER_DOMAIN_H + +/** + * A power domain is a portion of an SoC or chip that is powered by a + * switchable source of power. In many cases, software has control over the + * power domain, and can turn the power source on or off. This is typically + * done to save power by powering off unused devices, or to enable software + * sequencing of initial powerup at boot. This API provides a means for + * drivers to turn power domains on and off. + * + * A driver that implements UCLASS_POWER_DOMAIN is a power domain controller or + * provider. A controller will often implement multiple separate power domains, + * since the hardware it manages often has this capability. + * power-domain-uclass.h describes the interface which power domain controllers + * must implement. + * + * Depending on the power domain controller hardware, changing the state of a + * power domain may require performing related operations on other resources. + * For example, some power domains may require certain clocks to be enabled + * whenever the power domain is powered on, or during the time when the power + * domain is transitioning state. These details are implementation-specific + * and should ideally be encapsulated entirely within the provider driver, or + * configured through mechanisms (e.g. device tree) that do not require client + * drivers to provide extra configuration information. + * + * Power domain consumers/clients are the drivers for HW modules within the + * power domain. This header file describes the API used by those drivers. + * + * In many cases, a single complex IO controller (e.g. a PCIe controller) will + * be the sole logic contained within a power domain. In such cases, it is + * logical for the relevant device driver to directly control that power + * domain. In other cases, multiple controllers, each with their own driver, + * may be contained in a single power domain. Any logic require to co-ordinate + * between drivers for these multiple controllers is beyond the scope of this + * API at present. Equally, this API does not define or implement any policy + * by which power domains are managed. + */ + +struct udevice; + +/** + * struct power_domain - A handle to (allowing control of) a single power domain. + * + * Clients provide storage for power domain handles. The content of the + * structure is managed solely by the power domain API and power domain + * drivers. A power domain struct is initialized by "get"ing the power domain + * struct. The power domain struct is passed to all other power domain APIs to + * identify which power domain to operate upon. + * + * @dev: The device which implements the power domain. + * @id: The power domain ID within the provider. + * + * Currently, the power domain API assumes that a single integer ID is enough + * to identify and configure any power domain for any power domain provider. If + * this assumption becomes invalid in the future, the struct could be expanded + * to either (a) add more fields to allow power domain providers to store + * additional information, or (b) replace the id field with an opaque pointer, + * which the provider would dynamically allocate during its .of_xlate op, and + * process during is .request op. This may require the addition of an extra op + * to clean up the allocation. + */ +struct power_domain { + struct udevice *dev; + /* + * Written by of_xlate. We assume a single id is enough for now. In the + * future, we might add more fields here. + */ + unsigned long id; +}; + +/** + * power_domain_get - Get/request the power domain for a device. + * + * This looks up and requests a power domain. Each device is assumed to have + * a single (or, at least one) power domain associated with it somehow, and + * that domain, or the first/default domain. The mapping of client device to + * provider power domain may be via device-tree properties, board-provided + * mapping tables, or some other mechanism. + * + * @dev: The client device. + * @power_domain A pointer to a power domain struct to initialize. + * @return 0 if OK, or a negative error code. + */ +int power_domain_get(struct udevice *dev, struct power_domain *power_domain); + +/** + * power_domain_free - Free a previously requested power domain. + * + * @power_domain: A power domain struct that was previously successfully + * requested by power_domain_get(). + * @return 0 if OK, or a negative error code. + */ +int power_domain_free(struct power_domain *power_domain); + +/** + * power_domain_on - Enable power to a power domain. + * + * @power_domain: A power domain struct that was previously successfully + * requested by power_domain_get(). + * @return 0 if OK, or a negative error code. + */ +int power_domain_on(struct power_domain *power_domain); + +/** + * power_domain_off - Disable power ot a power domain. + * + * @power_domain: A power domain struct that was previously successfully + * requested by power_domain_get(). + * @return 0 if OK, or a negative error code. + */ +int power_domain_off(struct power_domain *power_domain); + +#endif diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 0534c0b767d8..06e620a3320c 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -8,8 +8,9 @@ #include #include #include -#include -#include +#include "libfdt/libfdt.h" +#include "libfdt/fdt_support.h" +#include "libfdt/fdtdec.h" #include #include @@ -79,7 +80,7 @@ const char *fdtdec_get_compatible(enum fdt_compat_id id) fdt_addr_t fdtdec_get_addr_size_fixed(const void *blob, int node, const char *prop_name, int index, int na, int ns, - fdt_size_t *sizep) + fdt_size_t *sizep, bool translate) { const fdt32_t *prop, *prop_end; const fdt32_t *prop_addr, *prop_size, *prop_after_size; @@ -114,7 +115,12 @@ fdt_addr_t fdtdec_get_addr_size_fixed(const void *blob, int node, return FDT_ADDR_T_NONE; } - addr = fdtdec_get_number(prop_addr, na); +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_OF_LIBFDT) + if (translate) + addr = fdt_translate_address(blob, node, prop_addr); + else +#endif + addr = fdtdec_get_number(prop_addr, na); if (sizep) { *sizep = fdtdec_get_number(prop_size, ns); @@ -128,7 +134,8 @@ fdt_addr_t fdtdec_get_addr_size_fixed(const void *blob, int node, } fdt_addr_t fdtdec_get_addr_size_auto_parent(const void *blob, int parent, - int node, const char *prop_name, int index, fdt_size_t *sizep) + int node, const char *prop_name, int index, fdt_size_t *sizep, + bool translate) { int na, ns; @@ -149,11 +156,12 @@ fdt_addr_t fdtdec_get_addr_size_auto_parent(const void *blob, int parent, debug("na=%d, ns=%d, ", na, ns); return fdtdec_get_addr_size_fixed(blob, node, prop_name, index, na, - ns, sizep); + ns, sizep, translate); } fdt_addr_t fdtdec_get_addr_size_auto_noparent(const void *blob, int node, - const char *prop_name, int index, fdt_size_t *sizep) + const char *prop_name, int index, fdt_size_t *sizep, + bool translate) { int parent; @@ -166,7 +174,7 @@ fdt_addr_t fdtdec_get_addr_size_auto_noparent(const void *blob, int node, } return fdtdec_get_addr_size_auto_parent(blob, parent, node, prop_name, - index, sizep); + index, sizep, translate); } fdt_addr_t fdtdec_get_addr_size(const void *blob, int node, @@ -176,7 +184,7 @@ fdt_addr_t fdtdec_get_addr_size(const void *blob, int node, return fdtdec_get_addr_size_fixed(blob, node, prop_name, 0, sizeof(fdt_addr_t) / sizeof(fdt32_t), - ns, sizep); + ns, sizep, false); } fdt_addr_t fdtdec_get_addr(const void *blob, int node, diff --git a/lib/fdtdec_common.c b/lib/fdtdec_common.c index 63b704a3d719..f99f25ef70fe 100644 --- a/lib/fdtdec_common.c +++ b/lib/fdtdec_common.c @@ -10,11 +10,11 @@ #ifndef USE_HOSTCC #include -#include -#include +#include "libfdt/libfdt.h" +#include "libfdt/fdtdec.h" #else -#include "libfdt.h" -#include "fdt_support.h" +#include "libfdt/libfdt.h" +#include "libfdt/fdt_support.h" #define debug(...) #endif diff --git a/lib/libfdt/fdt.c b/lib/libfdt/fdt.c index 96017a15a27a..7bedd10d25bc 100644 --- a/lib/libfdt/fdt.c +++ b/lib/libfdt/fdt.c @@ -3,11 +3,11 @@ * Copyright (C) 2006 David Gibson, IBM Corporation. * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause */ -#include +#include "libfdt_env.h" #ifndef USE_HOSTCC -#include -#include +#include "fdt.h" +#include "libfdt.h" #else #include "fdt_host.h" #endif diff --git a/include/fdt.h b/lib/libfdt/fdt.h similarity index 100% rename from include/fdt.h rename to lib/libfdt/fdt.h diff --git a/lib/libfdt/fdt_addresses.c b/lib/libfdt/fdt_addresses.c index b6bc66ea3237..17f80cbefd25 100644 --- a/lib/libfdt/fdt_addresses.c +++ b/lib/libfdt/fdt_addresses.c @@ -3,11 +3,11 @@ * Copyright (C) 2014 David Gibson * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause */ -#include +#include "libfdt_env.h" #ifndef USE_HOSTCC -#include -#include +#include "fdt.h" +#include "libfdt.h" #else #include "fdt_host.h" #endif diff --git a/lib/libfdt/fdt_empty_tree.c b/lib/libfdt/fdt_empty_tree.c index 6fde1eb9eda0..442db2c88103 100644 --- a/lib/libfdt/fdt_empty_tree.c +++ b/lib/libfdt/fdt_empty_tree.c @@ -3,9 +3,9 @@ * Copyright (C) 2012 David Gibson, IBM Corporation. * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause */ -#include -#include -#include +#include "libfdt_env.h" +#include "fdt.h" +#include "libfdt.h" #include "libfdt_internal.h" diff --git a/lib/libfdt/fdt_region.c b/lib/libfdt/fdt_region.c index d2ce4c1c537b..cf8ef36ac789 100644 --- a/lib/libfdt/fdt_region.c +++ b/lib/libfdt/fdt_region.c @@ -5,11 +5,11 @@ * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause */ -#include +#include "libfdt_env.h" #ifndef USE_HOSTCC -#include -#include +#include "fdt.h" +#include "libfdt.h" #else #include "fdt_host.h" #endif diff --git a/lib/libfdt/fdt_ro.c b/lib/libfdt/fdt_ro.c index 12214c2dc2b5..a33f61db95f5 100644 --- a/lib/libfdt/fdt_ro.c +++ b/lib/libfdt/fdt_ro.c @@ -3,11 +3,11 @@ * Copyright (C) 2006 David Gibson, IBM Corporation. * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause */ -#include +#include "libfdt_env.h" #ifndef USE_HOSTCC -#include -#include +#include "fdt.h" +#include "libfdt.h" #else #include "fdt_host.h" #endif diff --git a/lib/libfdt/fdt_rw.c b/lib/libfdt/fdt_rw.c index e7321ccae478..5f9d0ab2cf9d 100644 --- a/lib/libfdt/fdt_rw.c +++ b/lib/libfdt/fdt_rw.c @@ -3,11 +3,11 @@ * Copyright (C) 2006 David Gibson, IBM Corporation. * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause */ -#include +#include "libfdt_env.h" #ifndef USE_HOSTCC -#include -#include +#include "fdt.h" +#include "libfdt.h" #else #include "fdt_host.h" #endif diff --git a/include/fdt_simplefb.h b/lib/libfdt/fdt_simplefb.h similarity index 100% rename from include/fdt_simplefb.h rename to lib/libfdt/fdt_simplefb.h diff --git a/lib/libfdt/fdt_strerror.c b/lib/libfdt/fdt_strerror.c index 3b7e1683d0d0..df9b082de569 100644 --- a/lib/libfdt/fdt_strerror.c +++ b/lib/libfdt/fdt_strerror.c @@ -3,11 +3,11 @@ * Copyright (C) 2006 David Gibson, IBM Corporation. * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause */ -#include +#include "libfdt_env.h" #ifndef USE_HOSTCC -#include -#include +#include "fdt.h" +#include "libfdt.h" #else #include "fdt_host.h" #endif diff --git a/include/fdt_support.h b/lib/libfdt/fdt_support.h similarity index 97% rename from include/fdt_support.h rename to lib/libfdt/fdt_support.h index d34e959ca788..4cd50970c674 100644 --- a/include/fdt_support.h +++ b/lib/libfdt/fdt_support.h @@ -10,7 +10,7 @@ #ifdef CONFIG_OF_LIBFDT -#include +#include "libfdt.h" u32 fdt_getprop_u32_default_node(const void *fdt, int off, int cell, const char *prop, const u32 dflt); @@ -174,7 +174,8 @@ int fdt_fixup_nor_flash_size(void *blob); void fdt_fixup_mtdparts(void *fdt, void *node_info, int node_info_size); void fdt_del_node_and_alias(void *blob, const char *alias); -u64 fdt_translate_address(void *blob, int node_offset, const __be32 *in_addr); +u64 fdt_translate_address(const void *blob, int node_offset, + const __be32 *in_addr); int fdt_node_offset_by_compat_reg(void *blob, const char *compat, phys_addr_t compat_off); int fdt_alloc_phandle(void *blob); @@ -233,7 +234,7 @@ static inline u64 of_read_number(const fdt32_t *cell, int size) return r; } -void of_bus_default_count_cells(void *blob, int parentoffset, +void of_bus_default_count_cells(const void *blob, int parentoffset, int *addrc, int *sizec); int ft_verify_fdt(void *fdt); int arch_fixup_memory_node(void *blob); diff --git a/lib/libfdt/fdt_sw.c b/lib/libfdt/fdt_sw.c index 70fd02655073..e5a5d6c87fe9 100644 --- a/lib/libfdt/fdt_sw.c +++ b/lib/libfdt/fdt_sw.c @@ -3,9 +3,9 @@ * Copyright (C) 2006 David Gibson, IBM Corporation. * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause */ -#include -#include -#include +#include "libfdt_env.h" +#include "fdt.h" +#include "libfdt.h" #include "libfdt_internal.h" diff --git a/lib/libfdt/fdt_wip.c b/lib/libfdt/fdt_wip.c index 9fe988655fe3..58d4043266e1 100644 --- a/lib/libfdt/fdt_wip.c +++ b/lib/libfdt/fdt_wip.c @@ -3,11 +3,11 @@ * Copyright (C) 2006 David Gibson, IBM Corporation. * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause */ -#include +#include "libfdt_env.h" #ifndef USE_HOSTCC -#include -#include +#include "fdt.h" +#include "libfdt.h" #else #include "fdt_host.h" #endif diff --git a/include/fdtdec.h b/lib/libfdt/fdtdec.h similarity index 98% rename from include/fdtdec.h rename to lib/libfdt/fdtdec.h index 05d70c4b9b3e..1ddc012f6cc1 100644 --- a/include/fdtdec.h +++ b/lib/libfdt/fdtdec.h @@ -14,7 +14,7 @@ * changes to support FDT are minimized. */ -#include +#include "libfdt.h" #include /* @@ -304,11 +304,13 @@ int fdtdec_next_compatible_subnode(const void *blob, int node, * @param na the number of cells used to represent an address * @param ns the number of cells used to represent a size * @param sizep a pointer to store the size into. Use NULL if not required + * @param translate Indicates whether to translate the returned value + * using the parent node's ranges property. * @return address, if found, or FDT_ADDR_T_NONE if not */ fdt_addr_t fdtdec_get_addr_size_fixed(const void *blob, int node, const char *prop_name, int index, int na, int ns, - fdt_size_t *sizep); + fdt_size_t *sizep, bool translate); /* * Look up an address property in a node and return the parsed address, and @@ -324,10 +326,13 @@ fdt_addr_t fdtdec_get_addr_size_fixed(const void *blob, int node, * @param prop_name name of property to find * @param index which address to retrieve from a list of addresses. Often 0. * @param sizep a pointer to store the size into. Use NULL if not required + * @param translate Indicates whether to translate the returned value + * using the parent node's ranges property. * @return address, if found, or FDT_ADDR_T_NONE if not */ fdt_addr_t fdtdec_get_addr_size_auto_parent(const void *blob, int parent, - int node, const char *prop_name, int index, fdt_size_t *sizep); + int node, const char *prop_name, int index, fdt_size_t *sizep, + bool translate); /* * Look up an address property in a node and return the parsed address, and @@ -347,10 +352,13 @@ fdt_addr_t fdtdec_get_addr_size_auto_parent(const void *blob, int parent, * @param prop_name name of property to find * @param index which address to retrieve from a list of addresses. Often 0. * @param sizep a pointer to store the size into. Use NULL if not required + * @param translate Indicates whether to translate the returned value + * using the parent node's ranges property. * @return address, if found, or FDT_ADDR_T_NONE if not */ fdt_addr_t fdtdec_get_addr_size_auto_noparent(const void *blob, int node, - const char *prop_name, int index, fdt_size_t *sizep); + const char *prop_name, int index, fdt_size_t *sizep, + bool translate); /* * Look up an address property in a node and return the parsed address. diff --git a/include/libfdt.h b/lib/libfdt/libfdt.h similarity index 99% rename from include/libfdt.h rename to lib/libfdt/libfdt.h index 74b1d149c2dd..35a70f2a999a 100644 --- a/include/libfdt.h +++ b/lib/libfdt/libfdt.h @@ -51,8 +51,8 @@ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include -#include +#include "libfdt_env.h" +#include "fdt.h" #define FDT_FIRST_SUPPORTED_VERSION 0x10 #define FDT_LAST_SUPPORTED_VERSION 0x11 diff --git a/include/libfdt_env.h b/lib/libfdt/libfdt_env.h similarity index 100% rename from include/libfdt_env.h rename to lib/libfdt/libfdt_env.h diff --git a/lib/libfdt/libfdt_internal.h b/lib/libfdt/libfdt_internal.h index 9a79fe85ddaf..453980b4a8f8 100644 --- a/lib/libfdt/libfdt_internal.h +++ b/lib/libfdt/libfdt_internal.h @@ -5,7 +5,7 @@ * Copyright (C) 2006 David Gibson, IBM Corporation. * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause */ -#include +#include "fdt.h" #define FDT_ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1)) #define FDT_TAGALIGN(x) (FDT_ALIGN((x), FDT_TAGSIZE)) diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c index 5d9716f01349..dc6d5707f579 100644 --- a/lib/rsa/rsa-sign.c +++ b/lib/rsa/rsa-sign.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -19,6 +20,19 @@ #define HAVE_ERR_REMOVE_THREAD_STATE #endif +#if OPENSSL_VERSION_NUMBER < 0x10100000L +void RSA_get0_key(const RSA *r, + const BIGNUM **n, const BIGNUM **e, const BIGNUM **d) +{ + if (n != NULL) + *n = r->n; + if (e != NULL) + *e = r->e; + if (d != NULL) + *d = r->d; +} +#endif + static int rsa_err(const char *msg) { unsigned long sslErr = ERR_get_error(); @@ -134,22 +148,29 @@ static int rsa_init(void) { int ret; +#if OPENSSL_VERSION_NUMBER < 0x10100000L ret = SSL_library_init(); +#else + ret = OPENSSL_init_ssl(0, NULL); +#endif if (!ret) { fprintf(stderr, "Failure to init SSL library\n"); return -1; } +#if OPENSSL_VERSION_NUMBER < 0x10100000L SSL_load_error_strings(); OpenSSL_add_all_algorithms(); OpenSSL_add_all_digests(); OpenSSL_add_all_ciphers(); +#endif return 0; } static void rsa_remove(void) { +#if OPENSSL_VERSION_NUMBER < 0x10100000L CRYPTO_cleanup_all_ex_data(); ERR_free_strings(); #ifdef HAVE_ERR_REMOVE_THREAD_STATE @@ -158,6 +179,7 @@ static void rsa_remove(void) ERR_remove_state(0); #endif EVP_cleanup(); +#endif } static int rsa_sign_with_key(RSA *rsa, struct checksum_algo *checksum_algo, @@ -210,7 +232,11 @@ static int rsa_sign_with_key(RSA *rsa, struct checksum_algo *checksum_algo, ret = rsa_err("Could not obtain signature"); goto err_sign; } +#if OPENSSL_VERSION_NUMBER < 0x10100000L EVP_MD_CTX_cleanup(context); +#else + EVP_MD_CTX_reset(context); +#endif EVP_MD_CTX_destroy(context); EVP_PKEY_free(key); @@ -268,6 +294,7 @@ static int rsa_get_exponent(RSA *key, uint64_t *e) { int ret; BIGNUM *bn_te; + const BIGNUM *key_e; uint64_t te; ret = -EINVAL; @@ -276,17 +303,19 @@ static int rsa_get_exponent(RSA *key, uint64_t *e) if (!e) goto cleanup; - if (BN_num_bits(key->e) > 64) + RSA_get0_key(key, NULL, &key_e, NULL); + if (BN_num_bits(key_e) > 64) + goto cleanup; - *e = BN_get_word(key->e); + *e = BN_get_word(key_e); - if (BN_num_bits(key->e) < 33) { + if (BN_num_bits(key_e) < 33) { ret = 0; goto cleanup; } - bn_te = BN_dup(key->e); + bn_te = BN_dup(key_e); if (!bn_te) goto cleanup; @@ -316,6 +345,7 @@ int rsa_get_params(RSA *key, uint64_t *exponent, uint32_t *n0_invp, { BIGNUM *big1, *big2, *big32, *big2_32; BIGNUM *n, *r, *r_squared, *tmp; + const BIGNUM *key_n; BN_CTX *bn_ctx = BN_CTX_new(); int ret = 0; @@ -337,8 +367,9 @@ int rsa_get_params(RSA *key, uint64_t *exponent, uint32_t *n0_invp, if (0 != rsa_get_exponent(key, exponent)) ret = -1; - if (!BN_copy(n, key->n) || !BN_set_word(big1, 1L) || - !BN_set_word(big2, 2L) || !BN_set_word(big32, 32L)) + RSA_get0_key(key, &key_n, NULL, NULL); + if (!BN_copy(n, key_n) || !BN_set_word(big1, 1L) || + !BN_set_word(big2, 2L) || !BN_set_word(big32, 32L)) ret = -1; /* big2_32 = 2^32 */ diff --git a/net/bootp.c b/net/bootp.c index 42e14eda4174..afe4830b0bea 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -148,9 +148,14 @@ static void store_net_params(struct bootp_hdr *bp) { #if !defined(CONFIG_BOOTP_SERVERIP) struct in_addr tmp_ip; + bool overwrite_serverip = true; + +#if defined(CONFIG_BOOTP_PREFER_SERVERIP) + overwrite_serverip = false; +#endif net_copy_ip(&tmp_ip, &bp->bp_siaddr); - if (tmp_ip.s_addr != 0) + if (tmp_ip.s_addr != 0 && (overwrite_serverip || !net_server_ip.s_addr)) net_copy_ip(&net_server_ip, &bp->bp_siaddr); memcpy(net_server_ethaddr, ((struct ethernet_hdr *)net_rx_packet)->et_src, 6); diff --git a/net/eth-uclass.c b/net/eth-uclass.c index c15cc4d90bf4..c61d85fd6df3 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -523,6 +523,8 @@ static int eth_post_probe(struct udevice *dev) #endif } + eth_write_hwaddr(dev); + return 0; } diff --git a/test/dm/Makefile b/test/dm/Makefile index cad3374e43d6..1885e17c38d3 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_LED) += led.o obj-$(CONFIG_DM_MAILBOX) += mailbox.o obj-$(CONFIG_DM_MMC) += mmc.o obj-$(CONFIG_DM_PCI) += pci.o +obj-$(CONFIG_POWER_DOMAIN) += power-domain.o obj-$(CONFIG_RAM) += ram.o obj-y += regmap.o obj-$(CONFIG_REMOTEPROC) += remoteproc.o diff --git a/test/dm/power-domain.c b/test/dm/power-domain.c new file mode 100644 index 000000000000..379a8fa3d6e8 --- /dev/null +++ b/test/dm/power-domain.c @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include + +/* This must match the specifier for power-domains in the DT node */ +#define TEST_POWER_DOMAIN 2 + +static int dm_test_power_domain(struct unit_test_state *uts) +{ + struct udevice *dev_power_domain; + struct udevice *dev_test; + + ut_assertok(uclass_get_device_by_name(UCLASS_POWER_DOMAIN, + "power-domain", + &dev_power_domain)); + ut_asserteq(0, sandbox_power_domain_query(dev_power_domain, 0)); + ut_asserteq(0, sandbox_power_domain_query(dev_power_domain, + TEST_POWER_DOMAIN)); + + ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "power-domain-test", + &dev_test)); + ut_assertok(sandbox_power_domain_test_get(dev_test)); + + ut_assertok(sandbox_power_domain_test_on(dev_test)); + ut_asserteq(0, sandbox_power_domain_query(dev_power_domain, 0)); + ut_asserteq(1, sandbox_power_domain_query(dev_power_domain, + TEST_POWER_DOMAIN)); + + ut_assertok(sandbox_power_domain_test_off(dev_test)); + ut_asserteq(0, sandbox_power_domain_query(dev_power_domain, 0)); + ut_asserteq(0, sandbox_power_domain_query(dev_power_domain, + TEST_POWER_DOMAIN)); + + ut_assertok(sandbox_power_domain_test_free(dev_test)); + + return 0; +} +DM_TEST(dm_test_power_domain, DM_TESTF_SCAN_FDT); diff --git a/tools/Makefile b/tools/Makefile index f72294a98a58..137de126569c 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -221,7 +221,7 @@ LICENSE-$(CONFIG_CMD_LICENSE) += $(LICENSE_H) # Define __KERNEL_STRICT_NAMES to prevent typedef overlaps # Define _GNU_SOURCE to obtain the getline prototype from stdio.h # -HOST_EXTRACFLAGS += -include $(srctree)/include/libfdt_env.h \ +HOST_EXTRACFLAGS += -include $(srctree)/lib/libfdt/libfdt_env.h \ $(patsubst -I%,-idirafter%, $(filter -I%, $(UBOOTINCLUDE))) \ -I$(srctree)/lib/libfdt \ -I$(srctree)/tools \ diff --git a/tools/fdt_host.h b/tools/fdt_host.h index 134d9657139b..5b5b685e81ab 100644 --- a/tools/fdt_host.h +++ b/tools/fdt_host.h @@ -7,9 +7,10 @@ #ifndef __FDT_HOST_H__ #define __FDT_HOST_H__ +#include /* Make sure to include u-boot version of libfdt include files */ -#include "../include/libfdt.h" -#include "../include/fdt_support.h" +#include "../lib/libfdt/libfdt.h" +#include "../lib/libfdt/fdt_support.h" int fit_check_sign(const void *working_fdt, const void *key); diff --git a/tools/fdtgrep.c b/tools/fdtgrep.c index 8d3fef40279a..60c094dbb761 100644 --- a/tools/fdtgrep.c +++ b/tools/fdtgrep.c @@ -15,9 +15,10 @@ #include #include #include +#include -#include <../include/libfdt.h> -#include +#include "../lib/libfdt/libfdt.h" +#include "../lib/libfdt/libfdt_internal.h" /* Define DEBUG to get some debugging output on stderr */ #ifdef DEBUG diff --git a/tools/ifdtool.c b/tools/ifdtool.c index 48059c02b550..2a0d66ecf645 100644 --- a/tools/ifdtool.c +++ b/tools/ifdtool.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include "../lib/libfdt/libfdt.h" #include "ifdtool.h" #undef DEBUG