From db991f402f232ed31be8532c9c28a834ca9e10bb Mon Sep 17 00:00:00 2001 From: Gautier Hattenberger Date: Fri, 3 May 2019 23:05:16 +0200 Subject: [PATCH 1/6] [mcu] add support for I2C4 and SPI4 --- sw/airborne/arch/chibios/halconf.h | 2 +- .../arch/chibios/mcu_periph/i2c_arch.c | 63 +++++++++++++++++-- .../arch/chibios/mcu_periph/i2c_arch.h | 4 ++ .../arch/chibios/mcu_periph/spi_arch.c | 45 ++++++++++++- sw/airborne/mcu.c | 8 ++- sw/airborne/mcu_periph/i2c.c | 48 ++++++++++++++ sw/airborne/mcu_periph/i2c.h | 8 +++ sw/airborne/mcu_periph/spi.c | 11 ++++ sw/airborne/mcu_periph/spi.h | 12 ++++ 9 files changed, 193 insertions(+), 8 deletions(-) diff --git a/sw/airborne/arch/chibios/halconf.h b/sw/airborne/arch/chibios/halconf.h index 4072bf13511..430261b3398 100644 --- a/sw/airborne/arch/chibios/halconf.h +++ b/sw/airborne/arch/chibios/halconf.h @@ -105,7 +105,7 @@ * @brief Enables the I2C subsystem. */ #if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) -#if USE_I2C1 || USE_I2C2 || USE_I2C3 +#if USE_I2C1 || USE_I2C2 || USE_I2C3 || USE_I2C4 #define HAL_USE_I2C TRUE #else #define HAL_USE_I2C FALSE diff --git a/sw/airborne/arch/chibios/mcu_periph/i2c_arch.c b/sw/airborne/arch/chibios/mcu_periph/i2c_arch.c index e3deb9f2436..51e557bd41f 100644 --- a/sw/airborne/arch/chibios/mcu_periph/i2c_arch.c +++ b/sw/airborne/arch/chibios/mcu_periph/i2c_arch.c @@ -46,7 +46,7 @@ #define I2C_THREAD_STACK_SIZE 512 #endif -#if USE_I2C1 || USE_I2C2 || USE_I2C3 +#if USE_I2C1 || USE_I2C2 || USE_I2C3 || USE_I2C4 // private I2C init structure struct i2c_init { @@ -177,7 +177,7 @@ static void handle_i2c_thd(struct i2c_periph *p) break; } } -#endif /* USE_I2C1 || USE_I2C2 || USE_I2C3 */ +#endif /* USE_I2C1 || USE_I2C2 || USE_I2C3 || USE_I2C4 */ #if USE_I2C1 // I2C1 config @@ -342,6 +342,61 @@ static void thd_i2c3(void *arg) } #endif /* USE_I2C3 */ +#if USE_I2C4 +// I2C4 config +PRINT_CONFIG_VAR(I2C4_CLOCK_SPEED) +static SEMAPHORE_DECL(i2c4_sem, 0); +static I2CConfig i2cfg4 = I2C4_CFG_DEF; +#if defined STM32F7 +// We need a special buffer for DMA operations +static IN_DMA_SECTION(uint8_t i2c4_dma_buf[I2C_BUF_LEN]); +static struct i2c_init i2c4_init_s = { + .sem = &i2c4_sem, + .cfg = &i2cfg4, + .dma_buf = i2c4_dma_buf +}; +#else +static struct i2c_init i2c4_init_s = { + .sem = &i2c4_sem, + .cfg = &i2cfg4 +}; +#endif +// Errors +struct i2c_errors i2c4_errors; +// Thread +static __attribute__((noreturn)) void thd_i2c4(void *arg); +static THD_WORKING_AREA(wa_thd_i2c4, 128); + +/* + * I2C4 init + */ +void i2c4_hw_init(void) +{ + i2cStart(&I2CD4, &i2cfg4); + i2c4.reg_addr = &I2CD4; + i2c4.init_struct = NULL; + i2c4.errors = &i2c4_errors; + i2c4.init_struct = &i2c4_init_s; + // Create thread + chThdCreateStatic(wa_thd_i2c4, sizeof(wa_thd_i2c4), + NORMALPRIO + 1, thd_i2c4, NULL); +} + +/* + * I2C4 thread + * + */ +static void thd_i2c4(void *arg) +{ + (void) arg; + chRegSetThreadName("i2c4"); + + while (TRUE) { + handle_i2c_thd(&i2c4); + } +} +#endif /* USE_I2C4 */ + /** * i2c_event() function @@ -377,7 +432,7 @@ void i2c_setbitrate(struct i2c_periph *p __attribute__((unused)), int bitrate __ */ bool i2c_submit(struct i2c_periph *p, struct i2c_transaction *t) { -#if USE_I2C1 || USE_I2C2 || USE_I2C3 +#if USE_I2C1 || USE_I2C2 || USE_I2C3 || USE_I2C4 // sys lock chSysLock(); uint8_t temp; @@ -406,7 +461,7 @@ bool i2c_submit(struct i2c_periph *p, struct i2c_transaction *t) (void)p; (void)t; return FALSE; -#endif /* USE_I2C1 || USE_I2C2 || USE_I2C3 */ +#endif /* USE_I2C1 || USE_I2C2 || USE_I2C3 || USE_I2C4 */ } /** diff --git a/sw/airborne/arch/chibios/mcu_periph/i2c_arch.h b/sw/airborne/arch/chibios/mcu_periph/i2c_arch.h index c10a767dd4e..94d33396f7f 100644 --- a/sw/airborne/arch/chibios/mcu_periph/i2c_arch.h +++ b/sw/airborne/arch/chibios/mcu_periph/i2c_arch.h @@ -45,4 +45,8 @@ extern void i2c2_hw_init(void); extern void i2c3_hw_init(void); #endif /* USE_I2C3 */ +#if USE_I2C4 +extern void i2c4_hw_init(void); +#endif /* USE_I2C4 */ + #endif /* I2C_HW_H */ diff --git a/sw/airborne/arch/chibios/mcu_periph/spi_arch.c b/sw/airborne/arch/chibios/mcu_periph/spi_arch.c index d7e6f7ccf01..27bdbfae142 100644 --- a/sw/airborne/arch/chibios/mcu_periph/spi_arch.c +++ b/sw/airborne/arch/chibios/mcu_periph/spi_arch.c @@ -167,10 +167,12 @@ static inline uint16_t spi_resolve_slave_pin(uint8_t slave) static inline uint16_t spi_resolve_CR1(struct spi_transaction *t __attribute__((unused))) { uint16_t CR1 = 0; -#if defined(STM32F1) || defined(STM32F4) || defined(STM32F7) +#if defined(STM32F1) || defined(STM32F4) if (t->dss == SPIDss16bit) { - CR1 |= SPI_CR1_DFF; + CR1 |= SPI_CR1_DFF; // FIXME for F7 } +#endif +#if defined(STM32F1) || defined(STM32F4) || defined(STM32F7) if (t->bitorder == SPILSBFirst) { CR1 |= SPI_CR1_LSBFIRST; } @@ -443,6 +445,45 @@ void spi3_arch_init(void) } #endif +#if USE_SPI4 +static SEMAPHORE_DECL(spi4_sem, 0); +#if defined STM32F7 +// We need a special buffer for DMA operations +static IN_DMA_SECTION(uint8_t spi4_dma_buf_out[SPI_DMA_BUF_LEN]); +static IN_DMA_SECTION(uint8_t spi4_dma_buf_in[SPI_DMA_BUF_LEN]); +static struct spi_init spi4_init_s = { + .sem = &spi4_sem, + .dma_buf_out = spi4_dma_buf_out, + .dma_buf_in = spi4_dma_buf_in +}; +#else +static struct spi_init spi4_init_s = { + .sem = &spi4_sem, +}; +#endif + +static __attribute__((noreturn)) void thd_spi4(void *arg) +{ + (void) arg; + chRegSetThreadName("spi4"); + + while (TRUE) { + handle_spi_thd(&spi4); + } +} + +static THD_WORKING_AREA(wa_thd_spi4, 256); + +void spi4_arch_init(void) +{ + spi4.reg_addr = &SPID4; + spi4.init_struct = &spi4_init_s; + // Create thread + chThdCreateStatic(wa_thd_spi4, sizeof(wa_thd_spi4), + NORMALPRIO + 1, thd_spi4, NULL); +} +#endif + /** * Submit SPI transaction diff --git a/sw/airborne/mcu.c b/sw/airborne/mcu.c index 0a8ec2a9047..50afbee51c9 100644 --- a/sw/airborne/mcu.c +++ b/sw/airborne/mcu.c @@ -43,7 +43,7 @@ #define USING_UART 1 #include "mcu_periph/uart.h" #endif -#if USE_I2C0 || USE_I2C1 || USE_I2C2 || USE_I2C3 +#if USE_I2C0 || USE_I2C1 || USE_I2C2 || USE_I2C3 || USE_I2C4 #define USING_I2C 1 #include "mcu_periph/i2c.h" #endif @@ -173,6 +173,9 @@ void mcu_init(void) #ifdef USE_I2C3 i2c3_init(); #endif +#ifdef USE_I2C4 + i2c4_init(); +#endif #if USE_ADC adc_init(); #endif @@ -194,6 +197,9 @@ void mcu_init(void) #endif #if USE_SPI3 spi3_init(); +#endif +#if USE_SPI4 + spi4_init(); #endif spi_init_slaves(); #endif // SPI_MASTER diff --git a/sw/airborne/mcu_periph/i2c.c b/sw/airborne/mcu_periph/i2c.c index b84769b087c..d298633cc79 100644 --- a/sw/airborne/mcu_periph/i2c.c +++ b/sw/airborne/mcu_periph/i2c.c @@ -206,6 +206,49 @@ static void send_i2c3_err(struct transport_tx *trans, struct link_device *dev) #endif /* USE_I2C3 */ +#if USE_I2C4 + +struct i2c_periph i2c4; + +void i2c4_init(void) +{ + i2c_init(&i2c4); + i2c4_hw_init(); +} + +#if PERIODIC_TELEMETRY +static void send_i2c4_err(struct transport_tx *trans, struct link_device *dev) +{ + uint16_t i2c4_wd_reset_cnt = i2c4.errors->wd_reset_cnt; + uint16_t i2c4_queue_full_cnt = i2c4.errors->queue_full_cnt; + uint16_t i2c4_ack_fail_cnt = i2c4.errors->ack_fail_cnt; + uint16_t i2c4_miss_start_stop_cnt = i2c4.errors->miss_start_stop_cnt; + uint16_t i2c4_arb_lost_cnt = i2c4.errors->arb_lost_cnt; + uint16_t i2c4_over_under_cnt = i2c4.errors->over_under_cnt; + uint16_t i2c4_pec_recep_cnt = i2c4.errors->pec_recep_cnt; + uint16_t i2c4_timeout_tlow_cnt = i2c4.errors->timeout_tlow_cnt; + uint16_t i2c4_smbus_alert_cnt = i2c4.errors->smbus_alert_cnt; + uint16_t i2c4_unexpected_event_cnt = i2c4.errors->unexpected_event_cnt; + uint32_t i2c4_last_unexpected_event = i2c4.errors->last_unexpected_event; + uint8_t _bus4 = 4; + pprz_msg_send_I2C_ERRORS(trans, dev, AC_ID, + &i2c4_wd_reset_cnt, + &i2c4_queue_full_cnt, + &i2c4_ack_fail_cnt, + &i2c4_miss_start_stop_cnt, + &i2c4_arb_lost_cnt, + &i2c4_over_under_cnt, + &i2c4_pec_recep_cnt, + &i2c4_timeout_tlow_cnt, + &i2c4_smbus_alert_cnt, + &i2c4_unexpected_event_cnt, + &i2c4_last_unexpected_event, + &_bus4); +} +#endif + +#endif /* USE_I2C4 */ + #if PERIODIC_TELEMETRY static void send_i2c_err(struct transport_tx *trans __attribute__((unused)), struct link_device *dev __attribute__((unused))) @@ -230,6 +273,11 @@ static void send_i2c_err(struct transport_tx *trans __attribute__((unused)), case 3: #if USE_I2C3 send_i2c3_err(trans, dev); +#endif + break; + case 4: +#if USE_I2C4 + send_i2c4_err(trans, dev); #endif break; default: diff --git a/sw/airborne/mcu_periph/i2c.h b/sw/airborne/mcu_periph/i2c.h index c1051b831f8..352a0ac2667 100644 --- a/sw/airborne/mcu_periph/i2c.h +++ b/sw/airborne/mcu_periph/i2c.h @@ -215,6 +215,14 @@ extern void i2c3_init(void); #endif /* USE_I2C3 */ +#if USE_I2C4 + +extern struct i2c_periph i2c4; +extern void i2c4_init(void); + +#endif /* USE_I2C4 */ + + /** Initialize I2C peripheral */ extern void i2c_init(struct i2c_periph *p); diff --git a/sw/airborne/mcu_periph/spi.c b/sw/airborne/mcu_periph/spi.c index 1e78d0df216..c26eecff134 100644 --- a/sw/airborne/mcu_periph/spi.c +++ b/sw/airborne/mcu_periph/spi.c @@ -75,6 +75,17 @@ void spi3_init(void) #endif // USE_SPI3 +#if USE_SPI4 +struct spi_periph spi4; + +void spi4_init(void) +{ + spi_init(&spi4); + spi4_arch_init(); +} +#endif // USE_SPI4 + + void spi_init(struct spi_periph *p) { p->trans_insert_idx = 0; diff --git a/sw/airborne/mcu_periph/spi.h b/sw/airborne/mcu_periph/spi.h index a82b164d37f..4e6305f4491 100644 --- a/sw/airborne/mcu_periph/spi.h +++ b/sw/airborne/mcu_periph/spi.h @@ -241,6 +241,18 @@ extern void spi3_arch_init(void); #endif // USE_SPI3 +#if USE_SPI4 + +extern struct spi_periph spi4; +extern void spi4_init(void); + +/** Architecture dependent SPI4 initialization. + * Must be implemented by underlying architecture + */ +extern void spi4_arch_init(void); + +#endif // USE_SPI4 + /** Initialize a spi peripheral. * @param p spi peripheral to be configured */ From 698bd24853b64cf5ae4067c7dc3e70b00838b632 Mon Sep 17 00:00:00 2001 From: Gautier Hattenberger Date: Fri, 7 Jun 2019 11:03:40 +0200 Subject: [PATCH 2/6] [imu] add support of ICM imu sensors to the mpu60x0 driver register map is almost the same, the WHO_I_AM value can tell which sensor is being used --- sw/airborne/peripherals/mpu60x0.c | 16 ++++++ sw/airborne/peripherals/mpu60x0.h | 20 ++++++- sw/airborne/peripherals/mpu60x0_regs.h | 36 ++++++++---- sw/airborne/peripherals/mpu60x0_spi.c | 32 ++++++++--- sw/airborne/subsystems/imu/imu_mpu6000.c | 72 ++++++++++++++++++++++-- 5 files changed, 152 insertions(+), 24 deletions(-) diff --git a/sw/airborne/peripherals/mpu60x0.c b/sw/airborne/peripherals/mpu60x0.c index 5eb535fa2b8..e094243fe05 100644 --- a/sw/airborne/peripherals/mpu60x0.c +++ b/sw/airborne/peripherals/mpu60x0.c @@ -59,9 +59,11 @@ const int32_t MPU60X0_ACCEL_SENS_FRAC[4][2] = { void mpu60x0_set_default_config(struct Mpu60x0Config *c) { + c->type = MPU60X0; c->clk_sel = MPU60X0_DEFAULT_CLK_SEL; c->smplrt_div = MPU60X0_DEFAULT_SMPLRT_DIV; c->dlpf_cfg = MPU60X0_DEFAULT_DLPF_CFG; + c->dlpf_cfg_acc = MPU60X0_DEFAULT_DLPF_CFG_ACC; c->gyro_range = MPU60X0_DEFAULT_FS_SEL; c->accel_range = MPU60X0_DEFAULT_AFS_SEL; c->drdy_int_enable = false; @@ -117,6 +119,13 @@ void mpu60x0_send_config(Mpu60x0ConfigSet mpu_set, void *mpu, struct Mpu60x0Conf mpu_set(mpu, MPU60X0_REG_ACCEL_CONFIG, (config->accel_range << 3)); config->init_status++; break; + case MPU60X0_CONF_ACCEL2: + /* configure accelerometer DLPF (for ICM devices) */ + if (config->type != MPU60X0) { + mpu_set(mpu, MPU60X0_REG_ACCEL_CONFIG2, config->dlpf_cfg_acc); + } + config->init_status++; + break; case MPU60X0_CONF_I2C_SLAVES: /* if any, set MPU for I2C slaves and configure them*/ if (config->nb_slaves > 0) { @@ -133,6 +142,13 @@ void mpu60x0_send_config(Mpu60x0ConfigSet mpu_set, void *mpu, struct Mpu60x0Conf mpu_set(mpu, MPU60X0_REG_INT_ENABLE, (config->drdy_int_enable << 0)); config->init_status++; break; + case MPU60X0_CONF_UNDOC1: + /* configure undocumented register (for ICM devices) to remove 2.7m/s^2 y-acc bias */ + if (config->type != MPU60X0) { + mpu_set(mpu, MPU60X0_REG_UNDOC1, 0xC9); + } + config->init_status++; + break; case MPU60X0_CONF_DONE: config->initialized = true; break; diff --git a/sw/airborne/peripherals/mpu60x0.h b/sw/airborne/peripherals/mpu60x0.h index 3c88d1c3edc..fe7032f2200 100644 --- a/sw/airborne/peripherals/mpu60x0.h +++ b/sw/airborne/peripherals/mpu60x0.h @@ -39,8 +39,10 @@ #define MPU60X0_DEFAULT_FS_SEL MPU60X0_GYRO_RANGE_2000 /// Default accel full scale range +- 16g #define MPU60X0_DEFAULT_AFS_SEL MPU60X0_ACCEL_RANGE_16G -/// Default internal sampling (1kHz, 42Hz LP Bandwidth) -#define MPU60X0_DEFAULT_DLPF_CFG MPU60X0_DLPF_42HZ +/// Default internal sampling (1kHz, 98Hz LP Bandwidth) +#define MPU60X0_DEFAULT_DLPF_CFG MPU60X0_DLPF_98HZ +/// Default internal sampling for accelerometer ICM devices only (1kHz, 99Hz LP Bandwidth) +#define MPU60X0_DEFAULT_DLPF_CFG_ACC MPU60X0_DLPF_ACC_99HZ /// Default interrupt config: DATA_RDY_EN #define MPU60X0_DEFAULT_INT_CFG 1 /// Default clock: PLL with X gyro reference @@ -97,6 +99,16 @@ extern const float MPU60X0_ACCEL_SENS[4]; // Get default sensitivity numerator and denominator from a table extern const int32_t MPU60X0_ACCEL_SENS_FRAC[4][2]; +/** MPU60x0 sensor type + */ +enum Mpu60x0Type { + MPU60X0, + ICM20600, + ICM20608, + ICM20602, + ICM20689 +}; + enum Mpu60x0ConfStatus { MPU60X0_CONF_UNINIT, MPU60X0_CONF_RESET, @@ -106,8 +118,10 @@ enum Mpu60x0ConfStatus { MPU60X0_CONF_DLPF, MPU60X0_CONF_GYRO, MPU60X0_CONF_ACCEL, + MPU60X0_CONF_ACCEL2, MPU60X0_CONF_I2C_SLAVES, MPU60X0_CONF_INT_ENABLE, + MPU60X0_CONF_UNDOC1, MPU60X0_CONF_DONE }; @@ -122,8 +136,10 @@ struct Mpu60x0I2cSlave { }; struct Mpu60x0Config { + enum Mpu60x0Type type; ///< The type of sensor (MPU60x0, ICM20608, ...) uint8_t smplrt_div; ///< Sample rate divider enum Mpu60x0DLPF dlpf_cfg; ///< Digital Low Pass Filter + enum Mpu60x0ACCDLPF dlpf_cfg_acc; ///< Digital Low Pass Filter for acceleremoter (ICM devices only) enum Mpu60x0GyroRanges gyro_range; ///< deg/s Range enum Mpu60x0AccelRanges accel_range; ///< g Range bool drdy_int_enable; ///< Enable Data Ready Interrupt diff --git a/sw/airborne/peripherals/mpu60x0_regs.h b/sw/airborne/peripherals/mpu60x0_regs.h index d7c19d2b63c..f382bcc0c2f 100644 --- a/sw/airborne/peripherals/mpu60x0_regs.h +++ b/sw/airborne/peripherals/mpu60x0_regs.h @@ -43,14 +43,16 @@ // FIFO #define MPU60X0_REG_FIFO_EN 0x23 #define MPU60X0_REG_FIFO_COUNT_H 0x72 -#define MPU60X0_REG_FIFO_COUNT_L 0x73 -#define MPU60X0_REG_FIFO_R_W 0x74 +#define MPU60X0_REG_FIFO_COUNT_L 0x73 +#define MPU60X0_REG_FIFO_R_W 0x74 // Measurement Settings #define MPU60X0_REG_SMPLRT_DIV 0x19 #define MPU60X0_REG_CONFIG 0x1A #define MPU60X0_REG_GYRO_CONFIG 0x1B #define MPU60X0_REG_ACCEL_CONFIG 0x1C +#define MPU60X0_REG_ACCEL_CONFIG2 0x1D +#define MPU60X0_REG_UNDOC1 0x11 // I2C Slave settings #define MPU60X0_REG_I2C_MST_CTRL 0x24 @@ -112,13 +114,13 @@ #define MPU60X0_EXT_SENS_DATA 0x49 #define MPU60X0_EXT_SENS_DATA_SIZE 24 - +// Different sensor WHOAMI replies #define MPU60X0_REG_WHO_AM_I 0x75 -#ifdef ICM20608 -#define MPU60X0_WHOAMI_REPLY 0xAF -#else -#define MPU60X0_WHOAMI_REPLY 0x68 -#endif +#define MPU60X0_WHOAMI_REPLY 0x68 +#define ICM20600_WHOAMI_REPLY 0x11 +#define ICM20608_WHOAMI_REPLY 0xAF +#define ICM20602_WHOAMI_REPLY 0x12 +#define ICM20689_WHOAMI_REPLY 0x98 // Bit positions #define MPU60X0_I2C_BYPASS_EN 1 @@ -128,14 +130,14 @@ #define MPU60X0_I2C_MST_RESET 1 #define MPU60X0_FIFO_RESET 2 #define MPU60X0_I2C_IF_DIS 4 -#define MPU60X0_I2C_MST_EN 5 +#define MPU60X0_I2C_MST_EN 5 #define MPU60X0_FIFO_EN 6 // in MPU60X0_REG_I2C_MST_STATUS #define MPU60X0_I2C_SLV4_DONE 6 /** Digital Low Pass Filter Options - * DLFP is affecting both gyro and accels, + * DLFP is affecting both gyro and accels (on MPU not ICM), * with slightly different bandwidth */ enum Mpu60x0DLPF { @@ -148,6 +150,20 @@ enum Mpu60x0DLPF { MPU60X0_DLPF_05HZ = 0x6 }; +/** Digital Low Pass Filter Options + * DLFP specifically for the ICM device accelerometer + */ +enum Mpu60x0ACCDLPF { + MPU60X0_DLPF_ACC_1046HZ = 0x0, // internal sampling rate 4kHz + MPU60X0_DLPF_ACC_218HZ = 0x1, // internal sampling rate 1kHz + MPU60X0_DLPF_ACC_99HZ = 0x2, + MPU60X0_DLPF_ACC_44HZ = 0x3, + MPU60X0_DLPF_ACC_21HZ = 0x4, + MPU60X0_DLPF_ACC_10HZ = 0x5, + MPU60X0_DLPF_ACC_05HZ = 0x6, + MPU60X0_DLPF_ACC_420HZ = 0x7 +}; + /** * Selectable gyro range */ diff --git a/sw/airborne/peripherals/mpu60x0_spi.c b/sw/airborne/peripherals/mpu60x0_spi.c index ae9c3860314..2c16b98b83b 100644 --- a/sw/airborne/peripherals/mpu60x0_spi.c +++ b/sw/airborne/peripherals/mpu60x0_spi.c @@ -79,13 +79,31 @@ void mpu60x0_spi_start_configure(struct Mpu60x0_Spi *mpu) if (mpu->config.init_status == MPU60X0_CONF_UNINIT) { // First check if we found the chip (succesfull WHO_AM_I response) - if(mpu->spi_trans.status == SPITransSuccess && mpu->rx_buf[1] == MPU60X0_WHOAMI_REPLY) { + if (mpu->spi_trans.status == SPITransSuccess && + (mpu->rx_buf[1] == MPU60X0_WHOAMI_REPLY || + mpu->rx_buf[1] == ICM20600_WHOAMI_REPLY || + mpu->rx_buf[1] == ICM20608_WHOAMI_REPLY || + mpu->rx_buf[1] == ICM20602_WHOAMI_REPLY || + mpu->rx_buf[1] == ICM20689_WHOAMI_REPLY)) { + + if (mpu->rx_buf[1] == MPU60X0_WHOAMI_REPLY) { + mpu->config.type = MPU60X0; + } else if (mpu->rx_buf[1] == ICM20600_WHOAMI_REPLY) { + mpu->config.type = ICM20600; + } else if (mpu->rx_buf[1] == ICM20608_WHOAMI_REPLY) { + mpu->config.type = ICM20608; + } else if (mpu->rx_buf[1] == ICM20602_WHOAMI_REPLY) { + mpu->config.type = ICM20602; + } else if (mpu->rx_buf[1] == ICM20689_WHOAMI_REPLY) { + mpu->config.type = ICM20689; + } + mpu->config.init_status++; mpu->spi_trans.status = SPITransDone; mpu60x0_send_config(mpu60x0_spi_write_to_reg, (void *)mpu, &(mpu->config)); } // Send WHO_AM_I to check if chip is there - else if(mpu->spi_trans.status != SPITransRunning && mpu->spi_trans.status != SPITransPending) { + else if (mpu->spi_trans.status != SPITransRunning && mpu->spi_trans.status != SPITransPending) { mpu->spi_trans.output_length = 1; mpu->spi_trans.input_length = 2; mpu->tx_buf[0] = MPU60X0_REG_WHO_AM_I | MPU60X0_SPI_READ; @@ -124,11 +142,11 @@ void mpu60x0_spi_event(struct Mpu60x0_Spi *mpu) mpu->data_rates.rates.r = Int16FromBuf(mpu->rx_buf, 14); int16_t temp_raw = Int16FromBuf(mpu->rx_buf, 8); -#if ICM20608 - mpu->temp = (float)temp_raw / 326.8f + 25.0f; -#else - mpu->temp = (float)temp_raw / 340.0f + 36.53f; -#endif + if (mpu->config.type == MPU60X0) { + mpu->temp = (float)temp_raw / 361.0f + 35.0f; + } else { + mpu->temp = (float)temp_raw / 326.8f + 25.0f; + } // if we are reading slaves, copy the ext_sens_data if (mpu->config.nb_slaves > 0) { diff --git a/sw/airborne/subsystems/imu/imu_mpu6000.c b/sw/airborne/subsystems/imu/imu_mpu6000.c index 7cd3af302fb..0d831b0448d 100644 --- a/sw/airborne/subsystems/imu/imu_mpu6000.c +++ b/sw/airborne/subsystems/imu/imu_mpu6000.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2013-2015 Felix Ruess + * Copyright (C) 2019 Gautier Hattenberger * * This file is part of paparazzi. * @@ -35,30 +36,72 @@ PRINT_CONFIG_VAR(IMU_MPU_SPI_DEV) /* MPU60x0 gyro/accel internal lowpass frequency */ #if !defined IMU_MPU_LOWPASS_FILTER && !defined IMU_MPU_SMPLRT_DIV -#if (PERIODIC_FREQUENCY == 60) || (PERIODIC_FREQUENCY == 120) +#if (PERIODIC_FREQUENCY >= 60) && (PERIODIC_FREQUENCY <= 120) /* Accelerometer: Bandwidth 44Hz, Delay 4.9ms * Gyroscope: Bandwidth 42Hz, Delay 4.8ms sampling 1kHz */ #define IMU_MPU_LOWPASS_FILTER MPU60X0_DLPF_42HZ #define IMU_MPU_SMPLRT_DIV 9 PRINT_CONFIG_MSG("Gyro/Accel output rate is 100Hz at 1kHz internal sampling") -#elif PERIODIC_FREQUENCY == 512 +#ifndef IMU_MPU_ACCEL_LOWPASS_FILTER +#define IMU_MPU_ACCEL_LOWPASS_FILTER MPU60X0_DLPF_ACC_44HZ // for ICM sensors +#endif +#elif (PERIODIC_FREQUENCY == 512) || (PERIODIC_FREQUENCY == 500) /* Accelerometer: Bandwidth 260Hz, Delay 0ms * Gyroscope: Bandwidth 256Hz, Delay 0.98ms sampling 8kHz */ #define IMU_MPU_LOWPASS_FILTER MPU60X0_DLPF_256HZ #define IMU_MPU_SMPLRT_DIV 3 PRINT_CONFIG_MSG("Gyro/Accel output rate is 2kHz at 8kHz internal sampling") +#ifndef IMU_MPU_ACCEL_LOWPASS_FILTER +#define IMU_MPU_ACCEL_LOWPASS_FILTER MPU60X0_DLPF_ACC_218HZ // for ICM sensors +#endif #else -#error Non-default PERIODIC_FREQUENCY: please define IMU_MPU_LOWPASS_FILTER and IMU_MPU_SMPLRT_DIV. +/* By default, don't go too fast */ +#define IMU_MPU_LOWPASS_FILTER MPU60X0_DLPF_42HZ +#define IMU_MPU_SMPLRT_DIV 9 +PRINT_CONFIG_MSG("Gyro/Accel output rate is 100Hz at 1kHz internal sampling") +#ifndef IMU_MPU_ACCEL_LOWPASS_FILTER +#define IMU_MPU_ACCEL_LOWPASS_FILTER MPU60X0_DLPF_ACC_44HZ // for ICM sensors +#endif +INFO("Non-default PERIODIC_FREQUENCY: using default IMU_MPU_LOWPASS_FILTER and IMU_MPU_SMPLRT_DIV.") #endif #endif PRINT_CONFIG_VAR(IMU_MPU_LOWPASS_FILTER) +PRINT_CONFIG_VAR(IMU_MPU_ACCEL_LOWPASS_FILTER) PRINT_CONFIG_VAR(IMU_MPU_SMPLRT_DIV) PRINT_CONFIG_VAR(IMU_MPU_GYRO_RANGE) PRINT_CONFIG_VAR(IMU_MPU_ACCEL_RANGE) +// Default channels order +#ifndef IMU_MPU_CHAN_X +#define IMU_MPU_CHAN_X 0 +#endif +PRINT_CONFIG_VAR(IMU_MPU_CHAN_X) +#ifndef IMU_MPU_CHAN_Y +#define IMU_MPU_CHAN_Y 1 +#endif +PRINT_CONFIG_VAR(IMU_MPU_CHAN_Y) +#ifndef IMU_MPU_CHAN_Z +#define IMU_MPU_CHAN_Z 2 +#endif +PRINT_CONFIG_VAR(IMU_MPU_CHAN_Z) + +// Default channel signs +#ifndef IMU_MPU_X_SIGN +#define IMU_MPU_X_SIGN 1 +#endif +PRINT_CONFIG_VAR(IMU_MPU_X_SIGN) +#ifndef IMU_MPU_Y_SIGN +#define IMU_MPU_Y_SIGN 1 +#endif +PRINT_CONFIG_VAR(IMU_MPU_Y_SIGN) +#ifndef IMU_MPU_Z_SIGN +#define IMU_MPU_Z_SIGN 1 +#endif +PRINT_CONFIG_VAR(IMU_MPU_Z_SIGN) + struct ImuMpu6000 imu_mpu_spi; @@ -68,6 +111,7 @@ void imu_mpu_spi_init(void) // change the default configuration imu_mpu_spi.mpu.config.smplrt_div = IMU_MPU_SMPLRT_DIV; imu_mpu_spi.mpu.config.dlpf_cfg = IMU_MPU_LOWPASS_FILTER; + imu_mpu_spi.mpu.config.dlpf_cfg_acc = IMU_MPU_ACCEL_LOWPASS_FILTER; // only for ICM sensors imu_mpu_spi.mpu.config.gyro_range = IMU_MPU_GYRO_RANGE; imu_mpu_spi.mpu.config.accel_range = IMU_MPU_ACCEL_RANGE; } @@ -83,11 +127,29 @@ void imu_mpu_spi_event(void) mpu60x0_spi_event(&imu_mpu_spi.mpu); if (imu_mpu_spi.mpu.data_available) { uint32_t now_ts = get_sys_time_usec(); - RATES_COPY(imu.gyro_unscaled, imu_mpu_spi.mpu.data_rates.rates); - VECT3_COPY(imu.accel_unscaled, imu_mpu_spi.mpu.data_accel.vect); + + // set channel order + struct Int32Vect3 accel = { + IMU_MPU_X_SIGN * (int32_t)(imu_mpu_spi.mpu.data_accel.value[IMU_MPU_CHAN_X]), + IMU_MPU_Y_SIGN * (int32_t)(imu_mpu_spi.mpu.data_accel.value[IMU_MPU_CHAN_Y]), + IMU_MPU_Z_SIGN * (int32_t)(imu_mpu_spi.mpu.data_accel.value[IMU_MPU_CHAN_Z]) + }; + struct Int32Rates rates = { + IMU_MPU_X_SIGN * (int32_t)(imu_mpu_spi.mpu.data_rates.value[IMU_MPU_CHAN_X]), + IMU_MPU_Y_SIGN * (int32_t)(imu_mpu_spi.mpu.data_rates.value[IMU_MPU_CHAN_Y]), + IMU_MPU_Z_SIGN * (int32_t)(imu_mpu_spi.mpu.data_rates.value[IMU_MPU_CHAN_Z]) + }; + // unscaled vector + VECT3_COPY(imu.accel_unscaled, accel); + RATES_COPY(imu.gyro_unscaled, rates); + imu_mpu_spi.mpu.data_available = false; + + // Scale the gyro and accelerometer imu_scale_gyro(&imu); imu_scale_accel(&imu); + + // Send the scaled values over ABI AbiSendMsgIMU_GYRO_INT32(IMU_MPU6000_ID, now_ts, &imu.gyro); AbiSendMsgIMU_ACCEL_INT32(IMU_MPU6000_ID, now_ts, &imu.accel); } From 949d88e822675e58e7f2fa15915864719c50d97b Mon Sep 17 00:00:00 2001 From: Gautier Hattenberger Date: Fri, 3 May 2019 23:11:00 +0200 Subject: [PATCH 3/6] small corrections for baro bmp and sd log --- conf/modules/logger_sd_chibios.xml | 3 ++- sw/airborne/modules/sensors/baro_bmp3.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/conf/modules/logger_sd_chibios.xml b/conf/modules/logger_sd_chibios.xml index 3bb25956823..437d448772a 100644 --- a/conf/modules/logger_sd_chibios.xml +++ b/conf/modules/logger_sd_chibios.xml @@ -30,8 +30,9 @@ + - + diff --git a/sw/airborne/modules/sensors/baro_bmp3.c b/sw/airborne/modules/sensors/baro_bmp3.c index 37896ef44a9..3119daea8cb 100644 --- a/sw/airborne/modules/sensors/baro_bmp3.c +++ b/sw/airborne/modules/sensors/baro_bmp3.c @@ -56,8 +56,9 @@ void baro_bmp3_event(void) bmp3_i2c_event(&baro_bmp3); if (baro_bmp3.data_available) { + uint32_t now_ts = get_sys_time_usec(); // send ABI message - AbiSendMsgBARO_ABS(BARO_BMP3_SENDER_ID, baro_bmp3.pressure); + AbiSendMsgBARO_ABS(BARO_BMP3_SENDER_ID, now_ts, baro_bmp3.pressure); AbiSendMsgTEMPERATURE(BARO_BMP3_SENDER_ID, baro_bmp3.temperature); baro_bmp3.data_available = false; From d6765a5a933e341c595a15614dc27a6b388675d9 Mon Sep 17 00:00:00 2001 From: Gautier Hattenberger Date: Fri, 3 May 2019 23:15:12 +0200 Subject: [PATCH 4/6] [board] add new board TAWAKI based on STM32F7 with ChibiOS --- conf/boards/tawaki_1.0.makefile | 99 ++ conf/flash_modes.xml | 3 + conf/modules/board_tawaki.xml | 34 + sw/airborne/boards/tawaki/baro_board.h | 19 + .../boards/tawaki/chibios/v1.0/Makefile | 9 + .../boards/tawaki/chibios/v1.0/board.c | 266 +++ .../boards/tawaki/chibios/v1.0/board.h | 1559 +++++++++++++++++ .../boards/tawaki/chibios/v1.0/board.mk | 20 + .../boards/tawaki/chibios/v1.0/ffconf.h | 270 +++ .../boards/tawaki/chibios/v1.0/mcuconf.h | 483 +++++ .../boards/tawaki/chibios/v1.0/tawaki.cfg | 139 ++ .../boards/tawaki/chibios/v1.0/tawaki.h | 609 +++++++ 12 files changed, 3510 insertions(+) create mode 100644 conf/boards/tawaki_1.0.makefile create mode 100644 conf/modules/board_tawaki.xml create mode 100644 sw/airborne/boards/tawaki/baro_board.h create mode 100644 sw/airborne/boards/tawaki/chibios/v1.0/Makefile create mode 100644 sw/airborne/boards/tawaki/chibios/v1.0/board.c create mode 100644 sw/airborne/boards/tawaki/chibios/v1.0/board.h create mode 100644 sw/airborne/boards/tawaki/chibios/v1.0/board.mk create mode 100644 sw/airborne/boards/tawaki/chibios/v1.0/ffconf.h create mode 100644 sw/airborne/boards/tawaki/chibios/v1.0/mcuconf.h create mode 100644 sw/airborne/boards/tawaki/chibios/v1.0/tawaki.cfg create mode 100644 sw/airborne/boards/tawaki/chibios/v1.0/tawaki.h diff --git a/conf/boards/tawaki_1.0.makefile b/conf/boards/tawaki_1.0.makefile new file mode 100644 index 00000000000..a1445a7f1c2 --- /dev/null +++ b/conf/boards/tawaki_1.0.makefile @@ -0,0 +1,99 @@ +# Hey Emacs, this is a -*- makefile -*- +# +# tawaki_1.0.makefile +# +# based on STM32F7 +# only compatible with ChibiOS +# + +BOARD=tawaki +BOARD_VERSION=1.0 +BOARD_DIR=$(BOARD)/chibios/v$(BOARD_VERSION) +BOARD_CFG=\"boards/$(BOARD_DIR)/$(BOARD).h\" + +ARCH=chibios +$(TARGET).ARCHDIR = $(ARCH) + +RTOS=chibios +MCU=cortex-m7 + +## FPU on F7 +USE_FPU=softfp +USE_FPU_OPT= -mfpu=fpv5-d16 + +USE_LTO=yes + +$(TARGET).CFLAGS += -DSTM32F7 -DPPRZLINK_ENABLE_FD -DUSE_HARD_FAULT_RECOVERY + +############################################################################## +# Architecture or project specific options +# +# Define project name here (target) +PROJECT = $(TARGET) + +# Project specific files and paths (see Makefile.chibios for details) +CHIBIOS_BOARD_PLATFORM = STM32F7xx/platform.mk +CHIBIOS_BOARD_PORT = ARMCMx/STM32F7xx/port.mk +CHIBIOS_BOARD_LINKER = STM32F76xxI.ld +CHIBIOS_BOARD_STARTUP = startup_stm32f7xx.mk + +# ITCM flash is a special flash that allow faster operations +# At the moment it is not possible to flash the code in this mode using dfu-util +# but it should work with the BlackMagicProbe or STLINK +# By default, normal flash is used +ifeq ($(USE_ITCM),1) +$(TARGET).CFLAGS += -DUSE_ITCM=1 +DFU_ADDR = 0x00200000 +else +$(TARGET).CFLAGS += -DUSE_ITCM=0 +DFU_ADDR = 0x08000000 +endif + +############################################################################## +# Compiler settings +# + +# default flash mode is via usb dfu bootloader +# possibilities: DFU-UTIL, SWD, STLINK +FLASH_MODE ?= DFU-UTIL + +HAS_LUFTBOOT = FALSE + +# +# default LED configuration +# +RADIO_CONTROL_LED ?= 4 +BARO_LED ?= none +AHRS_ALIGNER_LED ?= 2 +GPS_LED ?= 3 +SYS_TIME_LED ?= 1 + +# +# default UART configuration (modem, gps, spektrum) +# + +MODEM_PORT ?= UART2 +MODEM_BAUD ?= B57600 + +GPS_PORT ?= UART7 +GPS_BAUD ?= B57600 + +RADIO_CONTROL_SPEKTRUM_PRIMARY_PORT ?= UART6 +RADIO_CONTROL_SPEKTRUM_SECONDARY_PORT ?= UART8 + +# single mode +SBUS_PORT ?= UART8 +# dual mode +SBUS1_PORT ?= UART8 +SBUS2_PORT ?= UART6 + +# +# default actuator configuration +# +# you can use different actuators by adding a configure option to your firmware section +# e.g. +# +ACTUATORS ?= actuators_pwm + diff --git a/conf/flash_modes.xml b/conf/flash_modes.xml index db1cd3409f4..f9ae7258c39 100644 --- a/conf/flash_modes.xml +++ b/conf/flash_modes.xml @@ -60,6 +60,7 @@ + @@ -73,6 +74,7 @@ + @@ -91,6 +93,7 @@ + diff --git a/conf/modules/board_tawaki.xml b/conf/modules/board_tawaki.xml new file mode 100644 index 00000000000..19edf3972fc --- /dev/null +++ b/conf/modules/board_tawaki.xml @@ -0,0 +1,34 @@ + + + + + + Autoload several onboard sensors for the Tawaki board with proper configuration + - IMU (icm206xx) (auto-detected from MPU6000 driver) + - Baro (BMP3) + - Mag (LIS3MDL) + Normal front of the board is on USB connector side + Normal up of the board is on the Molex connector side + + + + + + + + + + + + + + + + + + + + + + + diff --git a/sw/airborne/boards/tawaki/baro_board.h b/sw/airborne/boards/tawaki/baro_board.h new file mode 100644 index 00000000000..aa0b868c5ab --- /dev/null +++ b/sw/airborne/boards/tawaki/baro_board.h @@ -0,0 +1,19 @@ + +/* + * board specific functions for the tawaki board + * + */ + +#ifndef BOARDS_TAWAKI_BARO_H +#define BOARDS_TAWAKI_BARO_H + +// only for printing the baro type during compilation +#ifndef BARO_BOARD +#define BARO_BOARD BARO_BMP3_I2C +#endif + +extern void baro_event(void); +#define BaroEvent baro_event + +#endif /* BOARDS_TAWAKI_BARO_H */ + diff --git a/sw/airborne/boards/tawaki/chibios/v1.0/Makefile b/sw/airborne/boards/tawaki/chibios/v1.0/Makefile new file mode 100644 index 00000000000..5255ffaf953 --- /dev/null +++ b/sw/airborne/boards/tawaki/chibios/v1.0/Makefile @@ -0,0 +1,9 @@ +# file board.h is generated from file board.cfg by a script which is hosted here : +# https://github.com/alex31/chibios_enac_various_common/blob/master/TOOLS/boardGen.pl + +# documentation is here : +# https://github.com/alex31/chibios_enac_various_common/blob/master/TOOLS/DOC/boardGen.pdf + +board.h: board.cfg Makefile + boardGen.pl --no-pp-pin --no-pp-line $< $@ + diff --git a/sw/airborne/boards/tawaki/chibios/v1.0/board.c b/sw/airborne/boards/tawaki/chibios/v1.0/board.c new file mode 100644 index 00000000000..f6b930ff91f --- /dev/null +++ b/sw/airborne/boards/tawaki/chibios/v1.0/board.c @@ -0,0 +1,266 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" +#include "stm32_gpio.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Type of STM32 GPIO port setup. + */ +typedef struct { + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t odr; + uint32_t afrl; + uint32_t afrh; +} gpio_setup_t; + +/** + * @brief Type of STM32 GPIO initialization data. + */ +typedef struct { +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) + gpio_setup_t PAData; +#endif +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) + gpio_setup_t PBData; +#endif +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) + gpio_setup_t PCData; +#endif +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) + gpio_setup_t PDData; +#endif +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) + gpio_setup_t PEData; +#endif +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) + gpio_setup_t PFData; +#endif +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) + gpio_setup_t PGData; +#endif +#if STM32_HAS_GPIOH || defined(__DOXYGEN__) + gpio_setup_t PHData; +#endif +#if STM32_HAS_GPIOI || defined(__DOXYGEN__) + gpio_setup_t PIData; +#endif +#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) + gpio_setup_t PJData; +#endif +#if STM32_HAS_GPIOK || defined(__DOXYGEN__) + gpio_setup_t PKData; +#endif +} gpio_config_t; + +/** + * @brief STM32 GPIO static initialization data. + */ +static const gpio_config_t gpio_default_config = { +#if STM32_HAS_GPIOA + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, +#endif +#if STM32_HAS_GPIOJ + {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, + VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, +#endif +#if STM32_HAS_GPIOK + {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, + VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} +#endif +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { + + gpiop->OTYPER = config->otyper; + gpiop->OSPEEDR = config->ospeedr; + gpiop->PUPDR = config->pupdr; + gpiop->ODR = config->odr; + gpiop->AFRL = config->afrl; + gpiop->AFRH = config->afrh; + gpiop->MODER = config->moder; +} + +static void stm32_gpio_init(void) { + + /* Enabling GPIO-related clocks, the mask comes from the + registry header file.*/ + rccResetAHB1(STM32_GPIO_EN_MASK); + rccEnableAHB1(STM32_GPIO_EN_MASK, true); + + /* Initializing all the defined GPIO ports.*/ +#if STM32_HAS_GPIOA + gpio_init(GPIOA, &gpio_default_config.PAData); +#endif +#if STM32_HAS_GPIOB + gpio_init(GPIOB, &gpio_default_config.PBData); +#endif +#if STM32_HAS_GPIOC + gpio_init(GPIOC, &gpio_default_config.PCData); +#endif +#if STM32_HAS_GPIOD + gpio_init(GPIOD, &gpio_default_config.PDData); +#endif +#if STM32_HAS_GPIOE + gpio_init(GPIOE, &gpio_default_config.PEData); +#endif +#if STM32_HAS_GPIOF + gpio_init(GPIOF, &gpio_default_config.PFData); +#endif +#if STM32_HAS_GPIOG + gpio_init(GPIOG, &gpio_default_config.PGData); +#endif +#if STM32_HAS_GPIOH + gpio_init(GPIOH, &gpio_default_config.PHData); +#endif +#if STM32_HAS_GPIOI + gpio_init(GPIOI, &gpio_default_config.PIData); +#endif +#if STM32_HAS_GPIOJ + gpio_init(GPIOJ, &gpio_default_config.PJData); +#endif +#if STM32_HAS_GPIOK + gpio_init(GPIOK, &gpio_default_config.PKData); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Early initialization code. + * @details GPIO ports and system clocks are initialized before everything + * else. + */ +void __early_init(void) { + + stm32_gpio_init(); + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { + (void)sdcp; + /* assume card is inserted as there is no SD_DETECT pin + * actual detection will be done by the software + */ + return true; +} + +/** + * @brief SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + return false; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { + +} diff --git a/sw/airborne/boards/tawaki/chibios/v1.0/board.h b/sw/airborne/boards/tawaki/chibios/v1.0/board.h new file mode 100644 index 00000000000..4c22451f04d --- /dev/null +++ b/sw/airborne/boards/tawaki/chibios/v1.0/board.h @@ -0,0 +1,1559 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#pragma once + +/* + * Board identifier. + */ +#define BOARD_TAWAKI +#define BOARD_NAME "Tawaki Autopilot" + +/* + * Board oscillators-related settings. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 32768U +#endif + +#define STM32_LSEDRV (3U << 3U) + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 16000000U +#endif + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 300U + +/* + * MCU type as defined in the ST header. + */ +#define STM32F777xx + +/* + * IO pins assignments. + */ +#define PA00_AUX_A1 0U +#define PA01_AUX_A2 1U +#define PA02_AUX_A3 2U +#define PA03_AUX_B1 3U +#define PA04 4U +#define PA05 5U +#define PA06_AUX_A4 6U +#define PA07_AUX_B2 7U +#define PA08 8U +#define PA09_USB_VBUS 9U +#define PA10_LED2 10U +#define PA11_OTG_FS_DM 11U +#define PA12_OTG_FS_DP 12U +#define PA13_SWDIO 13U +#define PA14_SWCLK 14U +#define PA15_UART7_TX 15U + +#define PB00_AUX_B3 0U +#define PB01_AUX_B4 1U +#define PB02 2U +#define PB03_UART7_RX 3U +#define PB04 4U +#define PB05_DSHOT_RX 5U +#define PB06_SRVB1 6U +#define PB07_SRVB2 7U +#define PB08_SRVB3 8U +#define PB09_SRVB4 9U +#define PB10_I2C2_SCL_EXTERNAL 10U +#define PB11_I2C2_SDA_EXTERNAL 11U +#define PB12_SPI2_CS_EXTERNAL 12U +#define PB13 13U +#define PB14_SPI2_EXTERNAL_MISO 14U +#define PB15_SPI2_EXTERNAL_MOSI 15U + +#define PC00_VBAT_MEAS 0U +#define PC01 1U +#define PC02 2U +#define PC03 3U +#define PC04 4U +#define PC05 5U +#define PC06_RC2 6U +#define PC07_LED3 7U +#define PC08_SDMMC1_D0 8U +#define PC09_SDMMC1_D1 9U +#define PC10_SDMMC1_D2 10U +#define PC11_SDMMC1_D3 11U +#define PC12_SDMMC1_CK 12U +#define PC13_APSW 13U +#define PC14_OSC32_IN 14U +#define PC15_OSC32_OUT 15U + +#define PD00_CAN_RX 0U +#define PD01_CAN_TX 1U +#define PD02_SDMMC1_CMD 2U +#define PD03_SPI2_EXTERNAL_CLK 3U +#define PD04 4U +#define PD05_UART_TX2 5U +#define PD06_UART_RX2 6U +#define PD07 7U +#define PD08_UART_TX3 8U +#define PD09_UART_RX3 9U +#define PD10_LED4 10U +#define PD11 11U +#define PD12_I2C4_SCL_EXTERNAL 12U +#define PD13_I2C4_SDA_EXTERNAL 13U +#define PD14 14U +#define PD15_LED1 15U + +#define PE00_RC1 0U +#define PE01 1U +#define PE02_SPI4_INTERNAL_CLK 2U +#define PE03 3U +#define PE04_SPI4_CS_INTERNAL 4U +#define PE05_SPI4_INTERNAL_MISO 5U +#define PE06_SPI4_INTERNAL_MOSI 6U +#define PE07 7U +#define PE08 8U +#define PE09_SRVA1 9U +#define PE10 10U +#define PE11_SRVA2 11U +#define PE12 12U +#define PE13_SRVA3 13U +#define PE14_SRVA4 14U +#define PE15 15U + +#define PF00 0U +#define PF01 1U +#define PF02 2U +#define PF03 3U +#define PF04 4U +#define PF05 5U +#define PF06 6U +#define PF07 7U +#define PF08 8U +#define PF09 9U +#define PF10 10U +#define PF11 11U +#define PF12 12U +#define PF13 13U +#define PF14 14U +#define PF15 15U + +#define PG00 0U +#define PG01 1U +#define PG02 2U +#define PG03 3U +#define PG04 4U +#define PG05 5U +#define PG06 6U +#define PG07 7U +#define PG08 8U +#define PG09 9U +#define PG10 10U +#define PG11 11U +#define PG12 12U +#define PG13 13U +#define PG14 14U +#define PG15 15U + +#define PH00_OSC_IN 0U +#define PH01_OSC_OUT 1U +#define PH02 2U +#define PH03 3U +#define PH04 4U +#define PH05 5U +#define PH06 6U +#define PH07 7U +#define PH08 8U +#define PH09 9U +#define PH10 10U +#define PH11 11U +#define PH12 12U +#define PH13 13U +#define PH14 14U +#define PH15 15U + +#define PI00 0U +#define PI01 1U +#define PI02 2U +#define PI03 3U +#define PI04 4U +#define PI05 5U +#define PI06 6U +#define PI07 7U +#define PI08 8U +#define PI09 9U +#define PI10 10U +#define PI11 11U +#define PI12 12U +#define PI13 13U +#define PI14 14U +#define PI15 15U + +#define PJ00 0U +#define PJ01 1U +#define PJ02 2U +#define PJ03 3U +#define PJ04 4U +#define PJ05 5U +#define PJ06 6U +#define PJ07 7U +#define PJ08 8U +#define PJ09 9U +#define PJ10 10U +#define PJ11 11U +#define PJ12 12U +#define PJ13 13U +#define PJ14 14U +#define PJ15 15U + +#define PK00 0U +#define PK01 1U +#define PK02 2U +#define PK03 3U +#define PK04 4U +#define PK05 5U +#define PK06 6U +#define PK07 7U +#define PK08 8U +#define PK09 9U +#define PK10 10U +#define PK11 11U +#define PK12 12U +#define PK13 13U +#define PK14 14U +#define PK15 15U + +/* + * IO lines assignments. + */ +#define LINE_A00_AUX_A1 PAL_LINE(GPIOA, 0U) +#define LINE_A01_AUX_A2 PAL_LINE(GPIOA, 1U) +#define LINE_A02_AUX_A3 PAL_LINE(GPIOA, 2U) +#define LINE_A03_AUX_B1 PAL_LINE(GPIOA, 3U) +#define LINE_A06_AUX_A4 PAL_LINE(GPIOA, 6U) +#define LINE_A07_AUX_B2 PAL_LINE(GPIOA, 7U) +#define LINE_A09_USB_VBUS PAL_LINE(GPIOA, 9U) +#define LINE_A10_LED2 PAL_LINE(GPIOA, 10U) +#define LINE_A11_OTG_FS_DM PAL_LINE(GPIOA, 11U) +#define LINE_A12_OTG_FS_DP PAL_LINE(GPIOA, 12U) +#define LINE_A13_SWDIO PAL_LINE(GPIOA, 13U) +#define LINE_A14_SWCLK PAL_LINE(GPIOA, 14U) +#define LINE_A15_UART7_TX PAL_LINE(GPIOA, 15U) + +#define LINE_B00_AUX_B3 PAL_LINE(GPIOB, 0U) +#define LINE_B01_AUX_B4 PAL_LINE(GPIOB, 1U) +#define LINE_B03_UART7_RX PAL_LINE(GPIOB, 3U) +#define LINE_B05_DSHOT_RX PAL_LINE(GPIOB, 5U) +#define LINE_B06_SRVB1 PAL_LINE(GPIOB, 6U) +#define LINE_B07_SRVB2 PAL_LINE(GPIOB, 7U) +#define LINE_B08_SRVB3 PAL_LINE(GPIOB, 8U) +#define LINE_B09_SRVB4 PAL_LINE(GPIOB, 9U) +#define LINE_B10_I2C2_SCL_EXTERNAL PAL_LINE(GPIOB, 10U) +#define LINE_B11_I2C2_SDA_EXTERNAL PAL_LINE(GPIOB, 11U) +#define LINE_B12_SPI2_CS_EXTERNAL PAL_LINE(GPIOB, 12U) +#define LINE_B14_SPI2_EXTERNAL_MISO PAL_LINE(GPIOB, 14U) +#define LINE_B15_SPI2_EXTERNAL_MOSI PAL_LINE(GPIOB, 15U) + +#define LINE_C00_VBAT_MEAS PAL_LINE(GPIOC, 0U) +#define LINE_C06_RC2 PAL_LINE(GPIOC, 6U) +#define LINE_C07_LED3 PAL_LINE(GPIOC, 7U) +#define LINE_C08_SDMMC1_D0 PAL_LINE(GPIOC, 8U) +#define LINE_C09_SDMMC1_D1 PAL_LINE(GPIOC, 9U) +#define LINE_C10_SDMMC1_D2 PAL_LINE(GPIOC, 10U) +#define LINE_C11_SDMMC1_D3 PAL_LINE(GPIOC, 11U) +#define LINE_C12_SDMMC1_CK PAL_LINE(GPIOC, 12U) +#define LINE_C13_APSW PAL_LINE(GPIOC, 13U) +#define LINE_C14_OSC32_IN PAL_LINE(GPIOC, 14U) +#define LINE_C15_OSC32_OUT PAL_LINE(GPIOC, 15U) + +#define LINE_D00_CAN_RX PAL_LINE(GPIOD, 0U) +#define LINE_D01_CAN_TX PAL_LINE(GPIOD, 1U) +#define LINE_D02_SDMMC1_CMD PAL_LINE(GPIOD, 2U) +#define LINE_D03_SPI2_EXTERNAL_CLK PAL_LINE(GPIOD, 3U) +#define LINE_D05_UART_TX2 PAL_LINE(GPIOD, 5U) +#define LINE_D06_UART_RX2 PAL_LINE(GPIOD, 6U) +#define LINE_D08_UART_TX3 PAL_LINE(GPIOD, 8U) +#define LINE_D09_UART_RX3 PAL_LINE(GPIOD, 9U) +#define LINE_D10_LED4 PAL_LINE(GPIOD, 10U) +#define LINE_D12_I2C4_SCL_EXTERNAL PAL_LINE(GPIOD, 12U) +#define LINE_D13_I2C4_SDA_EXTERNAL PAL_LINE(GPIOD, 13U) +#define LINE_D15_LED1 PAL_LINE(GPIOD, 15U) + +#define LINE_E00_RC1 PAL_LINE(GPIOE, 0U) +#define LINE_E02_SPI4_INTERNAL_CLK PAL_LINE(GPIOE, 2U) +#define LINE_E04_SPI4_CS_INTERNAL PAL_LINE(GPIOE, 4U) +#define LINE_E05_SPI4_INTERNAL_MISO PAL_LINE(GPIOE, 5U) +#define LINE_E06_SPI4_INTERNAL_MOSI PAL_LINE(GPIOE, 6U) +#define LINE_E09_SRVA1 PAL_LINE(GPIOE, 9U) +#define LINE_E11_SRVA2 PAL_LINE(GPIOE, 11U) +#define LINE_E13_SRVA3 PAL_LINE(GPIOE, 13U) +#define LINE_E14_SRVA4 PAL_LINE(GPIOE, 14U) + +#define LINE_H00_OSC_IN PAL_LINE(GPIOH, 0U) +#define LINE_H01_OSC_OUT PAL_LINE(GPIOH, 1U) + + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) +#define PIN_ODR_LEVEL_LOW(n) (0U << (n)) +#define PIN_ODR_LEVEL_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_SPEED_VERYLOW(n) (0U << ((n) * 2U)) +#define PIN_OSPEED_SPEED_LOW(n) (1U << ((n) * 2U)) +#define PIN_OSPEED_SPEED_MEDIUM(n) (2U << ((n) * 2U)) +#define PIN_OSPEED_SPEED_HIGH(n) (3U << ((n) * 2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) + +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(PA00_AUX_A1) | \ + PIN_MODE_INPUT(PA01_AUX_A2) | \ + PIN_MODE_INPUT(PA02_AUX_A3) | \ + PIN_MODE_INPUT(PA03_AUX_B1) | \ + PIN_MODE_INPUT(PA04) | \ + PIN_MODE_INPUT(PA05) | \ + PIN_MODE_INPUT(PA06_AUX_A4) | \ + PIN_MODE_INPUT(PA07_AUX_B2) | \ + PIN_MODE_INPUT(PA08) | \ + PIN_MODE_INPUT(PA09_USB_VBUS) | \ + PIN_MODE_OUTPUT(PA10_LED2) | \ + PIN_MODE_ALTERNATE(PA11_OTG_FS_DM) | \ + PIN_MODE_ALTERNATE(PA12_OTG_FS_DP) | \ + PIN_MODE_ALTERNATE(PA13_SWDIO) | \ + PIN_MODE_ALTERNATE(PA14_SWCLK) | \ + PIN_MODE_ALTERNATE(PA15_UART7_TX)) + +#define VAL_GPIOA_OTYPER (PIN_OTYPE_OPENDRAIN(PA00_AUX_A1) | \ + PIN_OTYPE_OPENDRAIN(PA01_AUX_A2) | \ + PIN_OTYPE_OPENDRAIN(PA02_AUX_A3) | \ + PIN_OTYPE_OPENDRAIN(PA03_AUX_B1) | \ + PIN_OTYPE_PUSHPULL(PA04) | \ + PIN_OTYPE_PUSHPULL(PA05) | \ + PIN_OTYPE_OPENDRAIN(PA06_AUX_A4) | \ + PIN_OTYPE_OPENDRAIN(PA07_AUX_B2) | \ + PIN_OTYPE_PUSHPULL(PA08) | \ + PIN_OTYPE_OPENDRAIN(PA09_USB_VBUS) | \ + PIN_OTYPE_PUSHPULL(PA10_LED2) | \ + PIN_OTYPE_PUSHPULL(PA11_OTG_FS_DM) | \ + PIN_OTYPE_PUSHPULL(PA12_OTG_FS_DP) | \ + PIN_OTYPE_PUSHPULL(PA13_SWDIO) | \ + PIN_OTYPE_PUSHPULL(PA14_SWCLK) | \ + PIN_OTYPE_PUSHPULL(PA15_UART7_TX)) + +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_SPEED_VERYLOW(PA00_AUX_A1) | \ + PIN_OSPEED_SPEED_VERYLOW(PA01_AUX_A2) | \ + PIN_OSPEED_SPEED_VERYLOW(PA02_AUX_A3) | \ + PIN_OSPEED_SPEED_VERYLOW(PA03_AUX_B1) | \ + PIN_OSPEED_SPEED_VERYLOW(PA04) | \ + PIN_OSPEED_SPEED_VERYLOW(PA05) | \ + PIN_OSPEED_SPEED_VERYLOW(PA06_AUX_A4) | \ + PIN_OSPEED_SPEED_VERYLOW(PA07_AUX_B2) | \ + PIN_OSPEED_SPEED_VERYLOW(PA08) | \ + PIN_OSPEED_SPEED_VERYLOW(PA09_USB_VBUS) | \ + PIN_OSPEED_SPEED_VERYLOW(PA10_LED2) | \ + PIN_OSPEED_SPEED_HIGH(PA11_OTG_FS_DM) | \ + PIN_OSPEED_SPEED_HIGH(PA12_OTG_FS_DP) | \ + PIN_OSPEED_SPEED_HIGH(PA13_SWDIO) | \ + PIN_OSPEED_SPEED_HIGH(PA14_SWCLK) | \ + PIN_OSPEED_SPEED_HIGH(PA15_UART7_TX)) + +#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLDOWN(PA00_AUX_A1) | \ + PIN_PUPDR_PULLDOWN(PA01_AUX_A2) | \ + PIN_PUPDR_PULLDOWN(PA02_AUX_A3) | \ + PIN_PUPDR_PULLDOWN(PA03_AUX_B1) | \ + PIN_PUPDR_PULLDOWN(PA04) | \ + PIN_PUPDR_PULLDOWN(PA05) | \ + PIN_PUPDR_PULLDOWN(PA06_AUX_A4) | \ + PIN_PUPDR_PULLDOWN(PA07_AUX_B2) | \ + PIN_PUPDR_PULLDOWN(PA08) | \ + PIN_PUPDR_PULLDOWN(PA09_USB_VBUS) | \ + PIN_PUPDR_FLOATING(PA10_LED2) | \ + PIN_PUPDR_FLOATING(PA11_OTG_FS_DM) | \ + PIN_PUPDR_FLOATING(PA12_OTG_FS_DP) | \ + PIN_PUPDR_FLOATING(PA13_SWDIO) | \ + PIN_PUPDR_FLOATING(PA14_SWCLK) | \ + PIN_PUPDR_FLOATING(PA15_UART7_TX)) + +#define VAL_GPIOA_ODR (PIN_ODR_LEVEL_HIGH(PA00_AUX_A1) | \ + PIN_ODR_LEVEL_HIGH(PA01_AUX_A2) | \ + PIN_ODR_LEVEL_HIGH(PA02_AUX_A3) | \ + PIN_ODR_LEVEL_HIGH(PA03_AUX_B1) | \ + PIN_ODR_LEVEL_LOW(PA04) | \ + PIN_ODR_LEVEL_LOW(PA05) | \ + PIN_ODR_LEVEL_HIGH(PA06_AUX_A4) | \ + PIN_ODR_LEVEL_HIGH(PA07_AUX_B2) | \ + PIN_ODR_LEVEL_LOW(PA08) | \ + PIN_ODR_LEVEL_LOW(PA09_USB_VBUS) | \ + PIN_ODR_LEVEL_LOW(PA10_LED2) | \ + PIN_ODR_LEVEL_HIGH(PA11_OTG_FS_DM) | \ + PIN_ODR_LEVEL_HIGH(PA12_OTG_FS_DP) | \ + PIN_ODR_LEVEL_HIGH(PA13_SWDIO) | \ + PIN_ODR_LEVEL_HIGH(PA14_SWCLK) | \ + PIN_ODR_LEVEL_HIGH(PA15_UART7_TX)) + +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(PA00_AUX_A1, 0) | \ + PIN_AFIO_AF(PA01_AUX_A2, 0) | \ + PIN_AFIO_AF(PA02_AUX_A3, 0) | \ + PIN_AFIO_AF(PA03_AUX_B1, 0) | \ + PIN_AFIO_AF(PA04, 0) | \ + PIN_AFIO_AF(PA05, 0) | \ + PIN_AFIO_AF(PA06_AUX_A4, 0) | \ + PIN_AFIO_AF(PA07_AUX_B2, 0)) + +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(PA08, 0) | \ + PIN_AFIO_AF(PA09_USB_VBUS, 0) | \ + PIN_AFIO_AF(PA10_LED2, 0) | \ + PIN_AFIO_AF(PA11_OTG_FS_DM, 10) | \ + PIN_AFIO_AF(PA12_OTG_FS_DP, 10) | \ + PIN_AFIO_AF(PA13_SWDIO, 0) | \ + PIN_AFIO_AF(PA14_SWCLK, 0) | \ + PIN_AFIO_AF(PA15_UART7_TX, 12)) + +#define VAL_GPIOB_MODER (PIN_MODE_INPUT(PB00_AUX_B3) | \ + PIN_MODE_INPUT(PB01_AUX_B4) | \ + PIN_MODE_INPUT(PB02) | \ + PIN_MODE_ALTERNATE(PB03_UART7_RX) | \ + PIN_MODE_INPUT(PB04) | \ + PIN_MODE_ALTERNATE(PB05_DSHOT_RX) | \ + PIN_MODE_ALTERNATE(PB06_SRVB1) | \ + PIN_MODE_ALTERNATE(PB07_SRVB2) | \ + PIN_MODE_ALTERNATE(PB08_SRVB3) | \ + PIN_MODE_ALTERNATE(PB09_SRVB4) | \ + PIN_MODE_ALTERNATE(PB10_I2C2_SCL_EXTERNAL) | \ + PIN_MODE_ALTERNATE(PB11_I2C2_SDA_EXTERNAL) | \ + PIN_MODE_OUTPUT(PB12_SPI2_CS_EXTERNAL) | \ + PIN_MODE_INPUT(PB13) | \ + PIN_MODE_ALTERNATE(PB14_SPI2_EXTERNAL_MISO) | \ + PIN_MODE_ALTERNATE(PB15_SPI2_EXTERNAL_MOSI)) + +#define VAL_GPIOB_OTYPER (PIN_OTYPE_OPENDRAIN(PB00_AUX_B3) | \ + PIN_OTYPE_OPENDRAIN(PB01_AUX_B4) | \ + PIN_OTYPE_PUSHPULL(PB02) | \ + PIN_OTYPE_PUSHPULL(PB03_UART7_RX) | \ + PIN_OTYPE_PUSHPULL(PB04) | \ + PIN_OTYPE_PUSHPULL(PB05_DSHOT_RX) | \ + PIN_OTYPE_PUSHPULL(PB06_SRVB1) | \ + PIN_OTYPE_PUSHPULL(PB07_SRVB2) | \ + PIN_OTYPE_PUSHPULL(PB08_SRVB3) | \ + PIN_OTYPE_PUSHPULL(PB09_SRVB4) | \ + PIN_OTYPE_OPENDRAIN(PB10_I2C2_SCL_EXTERNAL) | \ + PIN_OTYPE_OPENDRAIN(PB11_I2C2_SDA_EXTERNAL) | \ + PIN_OTYPE_PUSHPULL(PB12_SPI2_CS_EXTERNAL) | \ + PIN_OTYPE_PUSHPULL(PB13) | \ + PIN_OTYPE_PUSHPULL(PB14_SPI2_EXTERNAL_MISO) | \ + PIN_OTYPE_PUSHPULL(PB15_SPI2_EXTERNAL_MOSI)) + +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_SPEED_VERYLOW(PB00_AUX_B3) | \ + PIN_OSPEED_SPEED_VERYLOW(PB01_AUX_B4) | \ + PIN_OSPEED_SPEED_VERYLOW(PB02) | \ + PIN_OSPEED_SPEED_HIGH(PB03_UART7_RX) | \ + PIN_OSPEED_SPEED_VERYLOW(PB04) | \ + PIN_OSPEED_SPEED_HIGH(PB05_DSHOT_RX) | \ + PIN_OSPEED_SPEED_HIGH(PB06_SRVB1) | \ + PIN_OSPEED_SPEED_HIGH(PB07_SRVB2) | \ + PIN_OSPEED_SPEED_HIGH(PB08_SRVB3) | \ + PIN_OSPEED_SPEED_HIGH(PB09_SRVB4) | \ + PIN_OSPEED_SPEED_HIGH(PB10_I2C2_SCL_EXTERNAL) | \ + PIN_OSPEED_SPEED_HIGH(PB11_I2C2_SDA_EXTERNAL) | \ + PIN_OSPEED_SPEED_HIGH(PB12_SPI2_CS_EXTERNAL) | \ + PIN_OSPEED_SPEED_VERYLOW(PB13) | \ + PIN_OSPEED_SPEED_HIGH(PB14_SPI2_EXTERNAL_MISO) | \ + PIN_OSPEED_SPEED_HIGH(PB15_SPI2_EXTERNAL_MOSI)) + +#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLDOWN(PB00_AUX_B3) | \ + PIN_PUPDR_PULLDOWN(PB01_AUX_B4) | \ + PIN_PUPDR_PULLDOWN(PB02) | \ + PIN_PUPDR_FLOATING(PB03_UART7_RX) | \ + PIN_PUPDR_PULLDOWN(PB04) | \ + PIN_PUPDR_FLOATING(PB05_DSHOT_RX) | \ + PIN_PUPDR_FLOATING(PB06_SRVB1) | \ + PIN_PUPDR_FLOATING(PB07_SRVB2) | \ + PIN_PUPDR_FLOATING(PB08_SRVB3) | \ + PIN_PUPDR_FLOATING(PB09_SRVB4) | \ + PIN_PUPDR_PULLUP(PB10_I2C2_SCL_EXTERNAL) | \ + PIN_PUPDR_PULLUP(PB11_I2C2_SDA_EXTERNAL) | \ + PIN_PUPDR_FLOATING(PB12_SPI2_CS_EXTERNAL) | \ + PIN_PUPDR_PULLDOWN(PB13) | \ + PIN_PUPDR_FLOATING(PB14_SPI2_EXTERNAL_MISO) | \ + PIN_PUPDR_FLOATING(PB15_SPI2_EXTERNAL_MOSI)) + +#define VAL_GPIOB_ODR (PIN_ODR_LEVEL_HIGH(PB00_AUX_B3) | \ + PIN_ODR_LEVEL_HIGH(PB01_AUX_B4) | \ + PIN_ODR_LEVEL_LOW(PB02) | \ + PIN_ODR_LEVEL_HIGH(PB03_UART7_RX) | \ + PIN_ODR_LEVEL_LOW(PB04) | \ + PIN_ODR_LEVEL_HIGH(PB05_DSHOT_RX) | \ + PIN_ODR_LEVEL_LOW(PB06_SRVB1) | \ + PIN_ODR_LEVEL_LOW(PB07_SRVB2) | \ + PIN_ODR_LEVEL_LOW(PB08_SRVB3) | \ + PIN_ODR_LEVEL_LOW(PB09_SRVB4) | \ + PIN_ODR_LEVEL_HIGH(PB10_I2C2_SCL_EXTERNAL) | \ + PIN_ODR_LEVEL_HIGH(PB11_I2C2_SDA_EXTERNAL) | \ + PIN_ODR_LEVEL_HIGH(PB12_SPI2_CS_EXTERNAL) | \ + PIN_ODR_LEVEL_LOW(PB13) | \ + PIN_ODR_LEVEL_HIGH(PB14_SPI2_EXTERNAL_MISO) | \ + PIN_ODR_LEVEL_HIGH(PB15_SPI2_EXTERNAL_MOSI)) + +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(PB00_AUX_B3, 0) | \ + PIN_AFIO_AF(PB01_AUX_B4, 0) | \ + PIN_AFIO_AF(PB02, 0) | \ + PIN_AFIO_AF(PB03_UART7_RX, 12) | \ + PIN_AFIO_AF(PB04, 0) | \ + PIN_AFIO_AF(PB05_DSHOT_RX, 1) | \ + PIN_AFIO_AF(PB06_SRVB1, 2) | \ + PIN_AFIO_AF(PB07_SRVB2, 2)) + +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(PB08_SRVB3, 2) | \ + PIN_AFIO_AF(PB09_SRVB4, 2) | \ + PIN_AFIO_AF(PB10_I2C2_SCL_EXTERNAL, 4) | \ + PIN_AFIO_AF(PB11_I2C2_SDA_EXTERNAL, 4) | \ + PIN_AFIO_AF(PB12_SPI2_CS_EXTERNAL, 0) | \ + PIN_AFIO_AF(PB13, 0) | \ + PIN_AFIO_AF(PB14_SPI2_EXTERNAL_MISO, 5) | \ + PIN_AFIO_AF(PB15_SPI2_EXTERNAL_MOSI, 5)) + +#define VAL_GPIOC_MODER (PIN_MODE_ANALOG(PC00_VBAT_MEAS) | \ + PIN_MODE_INPUT(PC01) | \ + PIN_MODE_INPUT(PC02) | \ + PIN_MODE_INPUT(PC03) | \ + PIN_MODE_INPUT(PC04) | \ + PIN_MODE_INPUT(PC05) | \ + PIN_MODE_INPUT(PC06_RC2) | \ + PIN_MODE_OUTPUT(PC07_LED3) | \ + PIN_MODE_ALTERNATE(PC08_SDMMC1_D0) | \ + PIN_MODE_ALTERNATE(PC09_SDMMC1_D1) | \ + PIN_MODE_ALTERNATE(PC10_SDMMC1_D2) | \ + PIN_MODE_ALTERNATE(PC11_SDMMC1_D3) | \ + PIN_MODE_ALTERNATE(PC12_SDMMC1_CK) | \ + PIN_MODE_OUTPUT(PC13_APSW) | \ + PIN_MODE_ALTERNATE(PC14_OSC32_IN) | \ + PIN_MODE_ALTERNATE(PC15_OSC32_OUT)) + +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(PC00_VBAT_MEAS) | \ + PIN_OTYPE_PUSHPULL(PC01) | \ + PIN_OTYPE_PUSHPULL(PC02) | \ + PIN_OTYPE_PUSHPULL(PC03) | \ + PIN_OTYPE_PUSHPULL(PC04) | \ + PIN_OTYPE_PUSHPULL(PC05) | \ + PIN_OTYPE_OPENDRAIN(PC06_RC2) | \ + PIN_OTYPE_PUSHPULL(PC07_LED3) | \ + PIN_OTYPE_PUSHPULL(PC08_SDMMC1_D0) | \ + PIN_OTYPE_PUSHPULL(PC09_SDMMC1_D1) | \ + PIN_OTYPE_PUSHPULL(PC10_SDMMC1_D2) | \ + PIN_OTYPE_PUSHPULL(PC11_SDMMC1_D3) | \ + PIN_OTYPE_PUSHPULL(PC12_SDMMC1_CK) | \ + PIN_OTYPE_PUSHPULL(PC13_APSW) | \ + PIN_OTYPE_PUSHPULL(PC14_OSC32_IN) | \ + PIN_OTYPE_PUSHPULL(PC15_OSC32_OUT)) + +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_SPEED_VERYLOW(PC00_VBAT_MEAS) | \ + PIN_OSPEED_SPEED_VERYLOW(PC01) | \ + PIN_OSPEED_SPEED_VERYLOW(PC02) | \ + PIN_OSPEED_SPEED_VERYLOW(PC03) | \ + PIN_OSPEED_SPEED_VERYLOW(PC04) | \ + PIN_OSPEED_SPEED_VERYLOW(PC05) | \ + PIN_OSPEED_SPEED_VERYLOW(PC06_RC2) | \ + PIN_OSPEED_SPEED_VERYLOW(PC07_LED3) | \ + PIN_OSPEED_SPEED_HIGH(PC08_SDMMC1_D0) | \ + PIN_OSPEED_SPEED_HIGH(PC09_SDMMC1_D1) | \ + PIN_OSPEED_SPEED_HIGH(PC10_SDMMC1_D2) | \ + PIN_OSPEED_SPEED_HIGH(PC11_SDMMC1_D3) | \ + PIN_OSPEED_SPEED_HIGH(PC12_SDMMC1_CK) | \ + PIN_OSPEED_SPEED_VERYLOW(PC13_APSW) | \ + PIN_OSPEED_SPEED_HIGH(PC14_OSC32_IN) | \ + PIN_OSPEED_SPEED_HIGH(PC15_OSC32_OUT)) + +#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(PC00_VBAT_MEAS) | \ + PIN_PUPDR_PULLDOWN(PC01) | \ + PIN_PUPDR_PULLDOWN(PC02) | \ + PIN_PUPDR_PULLDOWN(PC03) | \ + PIN_PUPDR_PULLDOWN(PC04) | \ + PIN_PUPDR_PULLDOWN(PC05) | \ + PIN_PUPDR_PULLDOWN(PC06_RC2) | \ + PIN_PUPDR_FLOATING(PC07_LED3) | \ + PIN_PUPDR_PULLUP(PC08_SDMMC1_D0) | \ + PIN_PUPDR_PULLUP(PC09_SDMMC1_D1) | \ + PIN_PUPDR_PULLUP(PC10_SDMMC1_D2) | \ + PIN_PUPDR_PULLUP(PC11_SDMMC1_D3) | \ + PIN_PUPDR_PULLUP(PC12_SDMMC1_CK) | \ + PIN_PUPDR_FLOATING(PC13_APSW) | \ + PIN_PUPDR_FLOATING(PC14_OSC32_IN) | \ + PIN_PUPDR_FLOATING(PC15_OSC32_OUT)) + +#define VAL_GPIOC_ODR (PIN_ODR_LEVEL_LOW(PC00_VBAT_MEAS) | \ + PIN_ODR_LEVEL_LOW(PC01) | \ + PIN_ODR_LEVEL_LOW(PC02) | \ + PIN_ODR_LEVEL_LOW(PC03) | \ + PIN_ODR_LEVEL_LOW(PC04) | \ + PIN_ODR_LEVEL_LOW(PC05) | \ + PIN_ODR_LEVEL_HIGH(PC06_RC2) | \ + PIN_ODR_LEVEL_LOW(PC07_LED3) | \ + PIN_ODR_LEVEL_HIGH(PC08_SDMMC1_D0) | \ + PIN_ODR_LEVEL_HIGH(PC09_SDMMC1_D1) | \ + PIN_ODR_LEVEL_HIGH(PC10_SDMMC1_D2) | \ + PIN_ODR_LEVEL_HIGH(PC11_SDMMC1_D3) | \ + PIN_ODR_LEVEL_HIGH(PC12_SDMMC1_CK) | \ + PIN_ODR_LEVEL_HIGH(PC13_APSW) | \ + PIN_ODR_LEVEL_HIGH(PC14_OSC32_IN) | \ + PIN_ODR_LEVEL_HIGH(PC15_OSC32_OUT)) + +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(PC00_VBAT_MEAS, 0) | \ + PIN_AFIO_AF(PC01, 0) | \ + PIN_AFIO_AF(PC02, 0) | \ + PIN_AFIO_AF(PC03, 0) | \ + PIN_AFIO_AF(PC04, 0) | \ + PIN_AFIO_AF(PC05, 0) | \ + PIN_AFIO_AF(PC06_RC2, 0) | \ + PIN_AFIO_AF(PC07_LED3, 0)) + +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(PC08_SDMMC1_D0, 12) | \ + PIN_AFIO_AF(PC09_SDMMC1_D1, 12) | \ + PIN_AFIO_AF(PC10_SDMMC1_D2, 12) | \ + PIN_AFIO_AF(PC11_SDMMC1_D3, 12) | \ + PIN_AFIO_AF(PC12_SDMMC1_CK, 12) | \ + PIN_AFIO_AF(PC13_APSW, 0) | \ + PIN_AFIO_AF(PC14_OSC32_IN, 0) | \ + PIN_AFIO_AF(PC15_OSC32_OUT, 0)) + +#define VAL_GPIOD_MODER (PIN_MODE_ALTERNATE(PD00_CAN_RX) | \ + PIN_MODE_ALTERNATE(PD01_CAN_TX) | \ + PIN_MODE_ALTERNATE(PD02_SDMMC1_CMD) | \ + PIN_MODE_ALTERNATE(PD03_SPI2_EXTERNAL_CLK) | \ + PIN_MODE_INPUT(PD04) | \ + PIN_MODE_ALTERNATE(PD05_UART_TX2) | \ + PIN_MODE_ALTERNATE(PD06_UART_RX2) | \ + PIN_MODE_INPUT(PD07) | \ + PIN_MODE_ALTERNATE(PD08_UART_TX3) | \ + PIN_MODE_ALTERNATE(PD09_UART_RX3) | \ + PIN_MODE_OUTPUT(PD10_LED4) | \ + PIN_MODE_INPUT(PD11) | \ + PIN_MODE_ALTERNATE(PD12_I2C4_SCL_EXTERNAL) | \ + PIN_MODE_ALTERNATE(PD13_I2C4_SDA_EXTERNAL) | \ + PIN_MODE_INPUT(PD14) | \ + PIN_MODE_OUTPUT(PD15_LED1)) + +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(PD00_CAN_RX) | \ + PIN_OTYPE_PUSHPULL(PD01_CAN_TX) | \ + PIN_OTYPE_PUSHPULL(PD02_SDMMC1_CMD) | \ + PIN_OTYPE_PUSHPULL(PD03_SPI2_EXTERNAL_CLK) | \ + PIN_OTYPE_PUSHPULL(PD04) | \ + PIN_OTYPE_PUSHPULL(PD05_UART_TX2) | \ + PIN_OTYPE_PUSHPULL(PD06_UART_RX2) | \ + PIN_OTYPE_PUSHPULL(PD07) | \ + PIN_OTYPE_PUSHPULL(PD08_UART_TX3) | \ + PIN_OTYPE_PUSHPULL(PD09_UART_RX3) | \ + PIN_OTYPE_PUSHPULL(PD10_LED4) | \ + PIN_OTYPE_PUSHPULL(PD11) | \ + PIN_OTYPE_OPENDRAIN(PD12_I2C4_SCL_EXTERNAL) | \ + PIN_OTYPE_OPENDRAIN(PD13_I2C4_SDA_EXTERNAL) | \ + PIN_OTYPE_PUSHPULL(PD14) | \ + PIN_OTYPE_PUSHPULL(PD15_LED1)) + +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_SPEED_HIGH(PD00_CAN_RX) | \ + PIN_OSPEED_SPEED_HIGH(PD01_CAN_TX) | \ + PIN_OSPEED_SPEED_HIGH(PD02_SDMMC1_CMD) | \ + PIN_OSPEED_SPEED_HIGH(PD03_SPI2_EXTERNAL_CLK) | \ + PIN_OSPEED_SPEED_VERYLOW(PD04) | \ + PIN_OSPEED_SPEED_HIGH(PD05_UART_TX2) | \ + PIN_OSPEED_SPEED_HIGH(PD06_UART_RX2) | \ + PIN_OSPEED_SPEED_VERYLOW(PD07) | \ + PIN_OSPEED_SPEED_HIGH(PD08_UART_TX3) | \ + PIN_OSPEED_SPEED_HIGH(PD09_UART_RX3) | \ + PIN_OSPEED_SPEED_VERYLOW(PD10_LED4) | \ + PIN_OSPEED_SPEED_VERYLOW(PD11) | \ + PIN_OSPEED_SPEED_HIGH(PD12_I2C4_SCL_EXTERNAL) | \ + PIN_OSPEED_SPEED_HIGH(PD13_I2C4_SDA_EXTERNAL) | \ + PIN_OSPEED_SPEED_VERYLOW(PD14) | \ + PIN_OSPEED_SPEED_VERYLOW(PD15_LED1)) + +#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(PD00_CAN_RX) | \ + PIN_PUPDR_FLOATING(PD01_CAN_TX) | \ + PIN_PUPDR_PULLUP(PD02_SDMMC1_CMD) | \ + PIN_PUPDR_FLOATING(PD03_SPI2_EXTERNAL_CLK) | \ + PIN_PUPDR_PULLDOWN(PD04) | \ + PIN_PUPDR_FLOATING(PD05_UART_TX2) | \ + PIN_PUPDR_FLOATING(PD06_UART_RX2) | \ + PIN_PUPDR_PULLDOWN(PD07) | \ + PIN_PUPDR_FLOATING(PD08_UART_TX3) | \ + PIN_PUPDR_FLOATING(PD09_UART_RX3) | \ + PIN_PUPDR_FLOATING(PD10_LED4) | \ + PIN_PUPDR_PULLDOWN(PD11) | \ + PIN_PUPDR_PULLUP(PD12_I2C4_SCL_EXTERNAL) | \ + PIN_PUPDR_PULLUP(PD13_I2C4_SDA_EXTERNAL) | \ + PIN_PUPDR_PULLDOWN(PD14) | \ + PIN_PUPDR_FLOATING(PD15_LED1)) + +#define VAL_GPIOD_ODR (PIN_ODR_LEVEL_HIGH(PD00_CAN_RX) | \ + PIN_ODR_LEVEL_HIGH(PD01_CAN_TX) | \ + PIN_ODR_LEVEL_HIGH(PD02_SDMMC1_CMD) | \ + PIN_ODR_LEVEL_HIGH(PD03_SPI2_EXTERNAL_CLK) | \ + PIN_ODR_LEVEL_LOW(PD04) | \ + PIN_ODR_LEVEL_HIGH(PD05_UART_TX2) | \ + PIN_ODR_LEVEL_HIGH(PD06_UART_RX2) | \ + PIN_ODR_LEVEL_LOW(PD07) | \ + PIN_ODR_LEVEL_HIGH(PD08_UART_TX3) | \ + PIN_ODR_LEVEL_HIGH(PD09_UART_RX3) | \ + PIN_ODR_LEVEL_LOW(PD10_LED4) | \ + PIN_ODR_LEVEL_LOW(PD11) | \ + PIN_ODR_LEVEL_HIGH(PD12_I2C4_SCL_EXTERNAL) | \ + PIN_ODR_LEVEL_HIGH(PD13_I2C4_SDA_EXTERNAL) | \ + PIN_ODR_LEVEL_LOW(PD14) | \ + PIN_ODR_LEVEL_LOW(PD15_LED1)) + +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(PD00_CAN_RX, 9) | \ + PIN_AFIO_AF(PD01_CAN_TX, 9) | \ + PIN_AFIO_AF(PD02_SDMMC1_CMD, 12) | \ + PIN_AFIO_AF(PD03_SPI2_EXTERNAL_CLK, 5) | \ + PIN_AFIO_AF(PD04, 0) | \ + PIN_AFIO_AF(PD05_UART_TX2, 7) | \ + PIN_AFIO_AF(PD06_UART_RX2, 7) | \ + PIN_AFIO_AF(PD07, 0)) + +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(PD08_UART_TX3, 7) | \ + PIN_AFIO_AF(PD09_UART_RX3, 7) | \ + PIN_AFIO_AF(PD10_LED4, 0) | \ + PIN_AFIO_AF(PD11, 0) | \ + PIN_AFIO_AF(PD12_I2C4_SCL_EXTERNAL, 4) | \ + PIN_AFIO_AF(PD13_I2C4_SDA_EXTERNAL, 4) | \ + PIN_AFIO_AF(PD14, 0) | \ + PIN_AFIO_AF(PD15_LED1, 0)) + +#define VAL_GPIOE_MODER (PIN_MODE_ALTERNATE(PE00_RC1) | \ + PIN_MODE_INPUT(PE01) | \ + PIN_MODE_ALTERNATE(PE02_SPI4_INTERNAL_CLK) | \ + PIN_MODE_INPUT(PE03) | \ + PIN_MODE_OUTPUT(PE04_SPI4_CS_INTERNAL) | \ + PIN_MODE_ALTERNATE(PE05_SPI4_INTERNAL_MISO) | \ + PIN_MODE_ALTERNATE(PE06_SPI4_INTERNAL_MOSI) | \ + PIN_MODE_INPUT(PE07) | \ + PIN_MODE_INPUT(PE08) | \ + PIN_MODE_ALTERNATE(PE09_SRVA1) | \ + PIN_MODE_INPUT(PE10) | \ + PIN_MODE_ALTERNATE(PE11_SRVA2) | \ + PIN_MODE_INPUT(PE12) | \ + PIN_MODE_ALTERNATE(PE13_SRVA3) | \ + PIN_MODE_ALTERNATE(PE14_SRVA4) | \ + PIN_MODE_INPUT(PE15)) + +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(PE00_RC1) | \ + PIN_OTYPE_PUSHPULL(PE01) | \ + PIN_OTYPE_PUSHPULL(PE02_SPI4_INTERNAL_CLK) | \ + PIN_OTYPE_PUSHPULL(PE03) | \ + PIN_OTYPE_PUSHPULL(PE04_SPI4_CS_INTERNAL) | \ + PIN_OTYPE_PUSHPULL(PE05_SPI4_INTERNAL_MISO) | \ + PIN_OTYPE_PUSHPULL(PE06_SPI4_INTERNAL_MOSI) | \ + PIN_OTYPE_PUSHPULL(PE07) | \ + PIN_OTYPE_PUSHPULL(PE08) | \ + PIN_OTYPE_PUSHPULL(PE09_SRVA1) | \ + PIN_OTYPE_PUSHPULL(PE10) | \ + PIN_OTYPE_PUSHPULL(PE11_SRVA2) | \ + PIN_OTYPE_PUSHPULL(PE12) | \ + PIN_OTYPE_PUSHPULL(PE13_SRVA3) | \ + PIN_OTYPE_PUSHPULL(PE14_SRVA4) | \ + PIN_OTYPE_PUSHPULL(PE15)) + +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_SPEED_HIGH(PE00_RC1) | \ + PIN_OSPEED_SPEED_VERYLOW(PE01) | \ + PIN_OSPEED_SPEED_HIGH(PE02_SPI4_INTERNAL_CLK) | \ + PIN_OSPEED_SPEED_VERYLOW(PE03) | \ + PIN_OSPEED_SPEED_HIGH(PE04_SPI4_CS_INTERNAL) | \ + PIN_OSPEED_SPEED_HIGH(PE05_SPI4_INTERNAL_MISO) | \ + PIN_OSPEED_SPEED_HIGH(PE06_SPI4_INTERNAL_MOSI) | \ + PIN_OSPEED_SPEED_VERYLOW(PE07) | \ + PIN_OSPEED_SPEED_VERYLOW(PE08) | \ + PIN_OSPEED_SPEED_HIGH(PE09_SRVA1) | \ + PIN_OSPEED_SPEED_VERYLOW(PE10) | \ + PIN_OSPEED_SPEED_HIGH(PE11_SRVA2) | \ + PIN_OSPEED_SPEED_VERYLOW(PE12) | \ + PIN_OSPEED_SPEED_HIGH(PE13_SRVA3) | \ + PIN_OSPEED_SPEED_HIGH(PE14_SRVA4) | \ + PIN_OSPEED_SPEED_VERYLOW(PE15)) + +#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(PE00_RC1) | \ + PIN_PUPDR_PULLDOWN(PE01) | \ + PIN_PUPDR_FLOATING(PE02_SPI4_INTERNAL_CLK) | \ + PIN_PUPDR_PULLDOWN(PE03) | \ + PIN_PUPDR_FLOATING(PE04_SPI4_CS_INTERNAL) | \ + PIN_PUPDR_FLOATING(PE05_SPI4_INTERNAL_MISO) | \ + PIN_PUPDR_FLOATING(PE06_SPI4_INTERNAL_MOSI) | \ + PIN_PUPDR_PULLDOWN(PE07) | \ + PIN_PUPDR_PULLDOWN(PE08) | \ + PIN_PUPDR_FLOATING(PE09_SRVA1) | \ + PIN_PUPDR_PULLDOWN(PE10) | \ + PIN_PUPDR_FLOATING(PE11_SRVA2) | \ + PIN_PUPDR_PULLDOWN(PE12) | \ + PIN_PUPDR_FLOATING(PE13_SRVA3) | \ + PIN_PUPDR_FLOATING(PE14_SRVA4) | \ + PIN_PUPDR_PULLDOWN(PE15)) + +#define VAL_GPIOE_ODR (PIN_ODR_LEVEL_HIGH(PE00_RC1) | \ + PIN_ODR_LEVEL_LOW(PE01) | \ + PIN_ODR_LEVEL_HIGH(PE02_SPI4_INTERNAL_CLK) | \ + PIN_ODR_LEVEL_LOW(PE03) | \ + PIN_ODR_LEVEL_HIGH(PE04_SPI4_CS_INTERNAL) | \ + PIN_ODR_LEVEL_HIGH(PE05_SPI4_INTERNAL_MISO) | \ + PIN_ODR_LEVEL_HIGH(PE06_SPI4_INTERNAL_MOSI) | \ + PIN_ODR_LEVEL_LOW(PE07) | \ + PIN_ODR_LEVEL_LOW(PE08) | \ + PIN_ODR_LEVEL_LOW(PE09_SRVA1) | \ + PIN_ODR_LEVEL_LOW(PE10) | \ + PIN_ODR_LEVEL_LOW(PE11_SRVA2) | \ + PIN_ODR_LEVEL_LOW(PE12) | \ + PIN_ODR_LEVEL_LOW(PE13_SRVA3) | \ + PIN_ODR_LEVEL_LOW(PE14_SRVA4) | \ + PIN_ODR_LEVEL_LOW(PE15)) + +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(PE00_RC1, 8) | \ + PIN_AFIO_AF(PE01, 0) | \ + PIN_AFIO_AF(PE02_SPI4_INTERNAL_CLK, 5) | \ + PIN_AFIO_AF(PE03, 0) | \ + PIN_AFIO_AF(PE04_SPI4_CS_INTERNAL, 0) | \ + PIN_AFIO_AF(PE05_SPI4_INTERNAL_MISO, 5) | \ + PIN_AFIO_AF(PE06_SPI4_INTERNAL_MOSI, 5) | \ + PIN_AFIO_AF(PE07, 0)) + +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(PE08, 0) | \ + PIN_AFIO_AF(PE09_SRVA1, 1) | \ + PIN_AFIO_AF(PE10, 0) | \ + PIN_AFIO_AF(PE11_SRVA2, 1) | \ + PIN_AFIO_AF(PE12, 0) | \ + PIN_AFIO_AF(PE13_SRVA3, 1) | \ + PIN_AFIO_AF(PE14_SRVA4, 1) | \ + PIN_AFIO_AF(PE15, 0)) + +#define VAL_GPIOF_MODER (PIN_MODE_INPUT(PF00) | \ + PIN_MODE_INPUT(PF01) | \ + PIN_MODE_INPUT(PF02) | \ + PIN_MODE_INPUT(PF03) | \ + PIN_MODE_INPUT(PF04) | \ + PIN_MODE_INPUT(PF05) | \ + PIN_MODE_INPUT(PF06) | \ + PIN_MODE_INPUT(PF07) | \ + PIN_MODE_INPUT(PF08) | \ + PIN_MODE_INPUT(PF09) | \ + PIN_MODE_INPUT(PF10) | \ + PIN_MODE_INPUT(PF11) | \ + PIN_MODE_INPUT(PF12) | \ + PIN_MODE_INPUT(PF13) | \ + PIN_MODE_INPUT(PF14) | \ + PIN_MODE_INPUT(PF15)) + +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(PF00) | \ + PIN_OTYPE_PUSHPULL(PF01) | \ + PIN_OTYPE_PUSHPULL(PF02) | \ + PIN_OTYPE_PUSHPULL(PF03) | \ + PIN_OTYPE_PUSHPULL(PF04) | \ + PIN_OTYPE_PUSHPULL(PF05) | \ + PIN_OTYPE_PUSHPULL(PF06) | \ + PIN_OTYPE_PUSHPULL(PF07) | \ + PIN_OTYPE_PUSHPULL(PF08) | \ + PIN_OTYPE_PUSHPULL(PF09) | \ + PIN_OTYPE_PUSHPULL(PF10) | \ + PIN_OTYPE_PUSHPULL(PF11) | \ + PIN_OTYPE_PUSHPULL(PF12) | \ + PIN_OTYPE_PUSHPULL(PF13) | \ + PIN_OTYPE_PUSHPULL(PF14) | \ + PIN_OTYPE_PUSHPULL(PF15)) + +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_SPEED_VERYLOW(PF00) | \ + PIN_OSPEED_SPEED_VERYLOW(PF01) | \ + PIN_OSPEED_SPEED_VERYLOW(PF02) | \ + PIN_OSPEED_SPEED_VERYLOW(PF03) | \ + PIN_OSPEED_SPEED_VERYLOW(PF04) | \ + PIN_OSPEED_SPEED_VERYLOW(PF05) | \ + PIN_OSPEED_SPEED_VERYLOW(PF06) | \ + PIN_OSPEED_SPEED_VERYLOW(PF07) | \ + PIN_OSPEED_SPEED_VERYLOW(PF08) | \ + PIN_OSPEED_SPEED_VERYLOW(PF09) | \ + PIN_OSPEED_SPEED_VERYLOW(PF10) | \ + PIN_OSPEED_SPEED_VERYLOW(PF11) | \ + PIN_OSPEED_SPEED_VERYLOW(PF12) | \ + PIN_OSPEED_SPEED_VERYLOW(PF13) | \ + PIN_OSPEED_SPEED_VERYLOW(PF14) | \ + PIN_OSPEED_SPEED_VERYLOW(PF15)) + +#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLDOWN(PF00) | \ + PIN_PUPDR_PULLDOWN(PF01) | \ + PIN_PUPDR_PULLDOWN(PF02) | \ + PIN_PUPDR_PULLDOWN(PF03) | \ + PIN_PUPDR_PULLDOWN(PF04) | \ + PIN_PUPDR_PULLDOWN(PF05) | \ + PIN_PUPDR_PULLDOWN(PF06) | \ + PIN_PUPDR_PULLDOWN(PF07) | \ + PIN_PUPDR_PULLDOWN(PF08) | \ + PIN_PUPDR_PULLDOWN(PF09) | \ + PIN_PUPDR_PULLDOWN(PF10) | \ + PIN_PUPDR_PULLDOWN(PF11) | \ + PIN_PUPDR_PULLDOWN(PF12) | \ + PIN_PUPDR_PULLDOWN(PF13) | \ + PIN_PUPDR_PULLDOWN(PF14) | \ + PIN_PUPDR_PULLDOWN(PF15)) + +#define VAL_GPIOF_ODR (PIN_ODR_LEVEL_LOW(PF00) | \ + PIN_ODR_LEVEL_LOW(PF01) | \ + PIN_ODR_LEVEL_LOW(PF02) | \ + PIN_ODR_LEVEL_LOW(PF03) | \ + PIN_ODR_LEVEL_LOW(PF04) | \ + PIN_ODR_LEVEL_LOW(PF05) | \ + PIN_ODR_LEVEL_LOW(PF06) | \ + PIN_ODR_LEVEL_LOW(PF07) | \ + PIN_ODR_LEVEL_LOW(PF08) | \ + PIN_ODR_LEVEL_LOW(PF09) | \ + PIN_ODR_LEVEL_LOW(PF10) | \ + PIN_ODR_LEVEL_LOW(PF11) | \ + PIN_ODR_LEVEL_LOW(PF12) | \ + PIN_ODR_LEVEL_LOW(PF13) | \ + PIN_ODR_LEVEL_LOW(PF14) | \ + PIN_ODR_LEVEL_LOW(PF15)) + +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(PF00, 0) | \ + PIN_AFIO_AF(PF01, 0) | \ + PIN_AFIO_AF(PF02, 0) | \ + PIN_AFIO_AF(PF03, 0) | \ + PIN_AFIO_AF(PF04, 0) | \ + PIN_AFIO_AF(PF05, 0) | \ + PIN_AFIO_AF(PF06, 0) | \ + PIN_AFIO_AF(PF07, 0)) + +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(PF08, 0) | \ + PIN_AFIO_AF(PF09, 0) | \ + PIN_AFIO_AF(PF10, 0) | \ + PIN_AFIO_AF(PF11, 0) | \ + PIN_AFIO_AF(PF12, 0) | \ + PIN_AFIO_AF(PF13, 0) | \ + PIN_AFIO_AF(PF14, 0) | \ + PIN_AFIO_AF(PF15, 0)) + +#define VAL_GPIOG_MODER (PIN_MODE_INPUT(PG00) | \ + PIN_MODE_INPUT(PG01) | \ + PIN_MODE_INPUT(PG02) | \ + PIN_MODE_INPUT(PG03) | \ + PIN_MODE_INPUT(PG04) | \ + PIN_MODE_INPUT(PG05) | \ + PIN_MODE_INPUT(PG06) | \ + PIN_MODE_INPUT(PG07) | \ + PIN_MODE_INPUT(PG08) | \ + PIN_MODE_INPUT(PG09) | \ + PIN_MODE_INPUT(PG10) | \ + PIN_MODE_INPUT(PG11) | \ + PIN_MODE_INPUT(PG12) | \ + PIN_MODE_INPUT(PG13) | \ + PIN_MODE_INPUT(PG14) | \ + PIN_MODE_INPUT(PG15)) + +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(PG00) | \ + PIN_OTYPE_PUSHPULL(PG01) | \ + PIN_OTYPE_PUSHPULL(PG02) | \ + PIN_OTYPE_PUSHPULL(PG03) | \ + PIN_OTYPE_PUSHPULL(PG04) | \ + PIN_OTYPE_PUSHPULL(PG05) | \ + PIN_OTYPE_PUSHPULL(PG06) | \ + PIN_OTYPE_PUSHPULL(PG07) | \ + PIN_OTYPE_PUSHPULL(PG08) | \ + PIN_OTYPE_PUSHPULL(PG09) | \ + PIN_OTYPE_PUSHPULL(PG10) | \ + PIN_OTYPE_PUSHPULL(PG11) | \ + PIN_OTYPE_PUSHPULL(PG12) | \ + PIN_OTYPE_PUSHPULL(PG13) | \ + PIN_OTYPE_PUSHPULL(PG14) | \ + PIN_OTYPE_PUSHPULL(PG15)) + +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_SPEED_VERYLOW(PG00) | \ + PIN_OSPEED_SPEED_VERYLOW(PG01) | \ + PIN_OSPEED_SPEED_VERYLOW(PG02) | \ + PIN_OSPEED_SPEED_VERYLOW(PG03) | \ + PIN_OSPEED_SPEED_VERYLOW(PG04) | \ + PIN_OSPEED_SPEED_VERYLOW(PG05) | \ + PIN_OSPEED_SPEED_VERYLOW(PG06) | \ + PIN_OSPEED_SPEED_VERYLOW(PG07) | \ + PIN_OSPEED_SPEED_VERYLOW(PG08) | \ + PIN_OSPEED_SPEED_VERYLOW(PG09) | \ + PIN_OSPEED_SPEED_VERYLOW(PG10) | \ + PIN_OSPEED_SPEED_VERYLOW(PG11) | \ + PIN_OSPEED_SPEED_VERYLOW(PG12) | \ + PIN_OSPEED_SPEED_VERYLOW(PG13) | \ + PIN_OSPEED_SPEED_VERYLOW(PG14) | \ + PIN_OSPEED_SPEED_VERYLOW(PG15)) + +#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLDOWN(PG00) | \ + PIN_PUPDR_PULLDOWN(PG01) | \ + PIN_PUPDR_PULLDOWN(PG02) | \ + PIN_PUPDR_PULLDOWN(PG03) | \ + PIN_PUPDR_PULLDOWN(PG04) | \ + PIN_PUPDR_PULLDOWN(PG05) | \ + PIN_PUPDR_PULLDOWN(PG06) | \ + PIN_PUPDR_PULLDOWN(PG07) | \ + PIN_PUPDR_PULLDOWN(PG08) | \ + PIN_PUPDR_PULLDOWN(PG09) | \ + PIN_PUPDR_PULLDOWN(PG10) | \ + PIN_PUPDR_PULLDOWN(PG11) | \ + PIN_PUPDR_PULLDOWN(PG12) | \ + PIN_PUPDR_PULLDOWN(PG13) | \ + PIN_PUPDR_PULLDOWN(PG14) | \ + PIN_PUPDR_PULLDOWN(PG15)) + +#define VAL_GPIOG_ODR (PIN_ODR_LEVEL_LOW(PG00) | \ + PIN_ODR_LEVEL_LOW(PG01) | \ + PIN_ODR_LEVEL_LOW(PG02) | \ + PIN_ODR_LEVEL_LOW(PG03) | \ + PIN_ODR_LEVEL_LOW(PG04) | \ + PIN_ODR_LEVEL_LOW(PG05) | \ + PIN_ODR_LEVEL_LOW(PG06) | \ + PIN_ODR_LEVEL_LOW(PG07) | \ + PIN_ODR_LEVEL_LOW(PG08) | \ + PIN_ODR_LEVEL_LOW(PG09) | \ + PIN_ODR_LEVEL_LOW(PG10) | \ + PIN_ODR_LEVEL_LOW(PG11) | \ + PIN_ODR_LEVEL_LOW(PG12) | \ + PIN_ODR_LEVEL_LOW(PG13) | \ + PIN_ODR_LEVEL_LOW(PG14) | \ + PIN_ODR_LEVEL_LOW(PG15)) + +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(PG00, 0) | \ + PIN_AFIO_AF(PG01, 0) | \ + PIN_AFIO_AF(PG02, 0) | \ + PIN_AFIO_AF(PG03, 0) | \ + PIN_AFIO_AF(PG04, 0) | \ + PIN_AFIO_AF(PG05, 0) | \ + PIN_AFIO_AF(PG06, 0) | \ + PIN_AFIO_AF(PG07, 0)) + +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(PG08, 0) | \ + PIN_AFIO_AF(PG09, 0) | \ + PIN_AFIO_AF(PG10, 0) | \ + PIN_AFIO_AF(PG11, 0) | \ + PIN_AFIO_AF(PG12, 0) | \ + PIN_AFIO_AF(PG13, 0) | \ + PIN_AFIO_AF(PG14, 0) | \ + PIN_AFIO_AF(PG15, 0)) + +#define VAL_GPIOH_MODER (PIN_MODE_ALTERNATE(PH00_OSC_IN) | \ + PIN_MODE_ALTERNATE(PH01_OSC_OUT) | \ + PIN_MODE_INPUT(PH02) | \ + PIN_MODE_INPUT(PH03) | \ + PIN_MODE_INPUT(PH04) | \ + PIN_MODE_INPUT(PH05) | \ + PIN_MODE_INPUT(PH06) | \ + PIN_MODE_INPUT(PH07) | \ + PIN_MODE_INPUT(PH08) | \ + PIN_MODE_INPUT(PH09) | \ + PIN_MODE_INPUT(PH10) | \ + PIN_MODE_INPUT(PH11) | \ + PIN_MODE_INPUT(PH12) | \ + PIN_MODE_INPUT(PH13) | \ + PIN_MODE_INPUT(PH14) | \ + PIN_MODE_INPUT(PH15)) + +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(PH00_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(PH01_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(PH02) | \ + PIN_OTYPE_PUSHPULL(PH03) | \ + PIN_OTYPE_PUSHPULL(PH04) | \ + PIN_OTYPE_PUSHPULL(PH05) | \ + PIN_OTYPE_PUSHPULL(PH06) | \ + PIN_OTYPE_PUSHPULL(PH07) | \ + PIN_OTYPE_PUSHPULL(PH08) | \ + PIN_OTYPE_PUSHPULL(PH09) | \ + PIN_OTYPE_PUSHPULL(PH10) | \ + PIN_OTYPE_PUSHPULL(PH11) | \ + PIN_OTYPE_PUSHPULL(PH12) | \ + PIN_OTYPE_PUSHPULL(PH13) | \ + PIN_OTYPE_PUSHPULL(PH14) | \ + PIN_OTYPE_PUSHPULL(PH15)) + +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_SPEED_HIGH(PH00_OSC_IN) | \ + PIN_OSPEED_SPEED_HIGH(PH01_OSC_OUT) | \ + PIN_OSPEED_SPEED_VERYLOW(PH02) | \ + PIN_OSPEED_SPEED_VERYLOW(PH03) | \ + PIN_OSPEED_SPEED_VERYLOW(PH04) | \ + PIN_OSPEED_SPEED_VERYLOW(PH05) | \ + PIN_OSPEED_SPEED_VERYLOW(PH06) | \ + PIN_OSPEED_SPEED_VERYLOW(PH07) | \ + PIN_OSPEED_SPEED_VERYLOW(PH08) | \ + PIN_OSPEED_SPEED_VERYLOW(PH09) | \ + PIN_OSPEED_SPEED_VERYLOW(PH10) | \ + PIN_OSPEED_SPEED_VERYLOW(PH11) | \ + PIN_OSPEED_SPEED_VERYLOW(PH12) | \ + PIN_OSPEED_SPEED_VERYLOW(PH13) | \ + PIN_OSPEED_SPEED_VERYLOW(PH14) | \ + PIN_OSPEED_SPEED_VERYLOW(PH15)) + +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(PH00_OSC_IN) | \ + PIN_PUPDR_FLOATING(PH01_OSC_OUT) | \ + PIN_PUPDR_PULLDOWN(PH02) | \ + PIN_PUPDR_PULLDOWN(PH03) | \ + PIN_PUPDR_PULLDOWN(PH04) | \ + PIN_PUPDR_PULLDOWN(PH05) | \ + PIN_PUPDR_PULLDOWN(PH06) | \ + PIN_PUPDR_PULLDOWN(PH07) | \ + PIN_PUPDR_PULLDOWN(PH08) | \ + PIN_PUPDR_PULLDOWN(PH09) | \ + PIN_PUPDR_PULLDOWN(PH10) | \ + PIN_PUPDR_PULLDOWN(PH11) | \ + PIN_PUPDR_PULLDOWN(PH12) | \ + PIN_PUPDR_PULLDOWN(PH13) | \ + PIN_PUPDR_PULLDOWN(PH14) | \ + PIN_PUPDR_PULLDOWN(PH15)) + +#define VAL_GPIOH_ODR (PIN_ODR_LEVEL_HIGH(PH00_OSC_IN) | \ + PIN_ODR_LEVEL_HIGH(PH01_OSC_OUT) | \ + PIN_ODR_LEVEL_LOW(PH02) | \ + PIN_ODR_LEVEL_LOW(PH03) | \ + PIN_ODR_LEVEL_LOW(PH04) | \ + PIN_ODR_LEVEL_LOW(PH05) | \ + PIN_ODR_LEVEL_LOW(PH06) | \ + PIN_ODR_LEVEL_LOW(PH07) | \ + PIN_ODR_LEVEL_LOW(PH08) | \ + PIN_ODR_LEVEL_LOW(PH09) | \ + PIN_ODR_LEVEL_LOW(PH10) | \ + PIN_ODR_LEVEL_LOW(PH11) | \ + PIN_ODR_LEVEL_LOW(PH12) | \ + PIN_ODR_LEVEL_LOW(PH13) | \ + PIN_ODR_LEVEL_LOW(PH14) | \ + PIN_ODR_LEVEL_LOW(PH15)) + +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(PH00_OSC_IN, 0) | \ + PIN_AFIO_AF(PH01_OSC_OUT, 0) | \ + PIN_AFIO_AF(PH02, 0) | \ + PIN_AFIO_AF(PH03, 0) | \ + PIN_AFIO_AF(PH04, 0) | \ + PIN_AFIO_AF(PH05, 0) | \ + PIN_AFIO_AF(PH06, 0) | \ + PIN_AFIO_AF(PH07, 0)) + +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(PH08, 0) | \ + PIN_AFIO_AF(PH09, 0) | \ + PIN_AFIO_AF(PH10, 0) | \ + PIN_AFIO_AF(PH11, 0) | \ + PIN_AFIO_AF(PH12, 0) | \ + PIN_AFIO_AF(PH13, 0) | \ + PIN_AFIO_AF(PH14, 0) | \ + PIN_AFIO_AF(PH15, 0)) + +#define VAL_GPIOI_MODER (PIN_MODE_INPUT(PI00) | \ + PIN_MODE_INPUT(PI01) | \ + PIN_MODE_INPUT(PI02) | \ + PIN_MODE_INPUT(PI03) | \ + PIN_MODE_INPUT(PI04) | \ + PIN_MODE_INPUT(PI05) | \ + PIN_MODE_INPUT(PI06) | \ + PIN_MODE_INPUT(PI07) | \ + PIN_MODE_INPUT(PI08) | \ + PIN_MODE_INPUT(PI09) | \ + PIN_MODE_INPUT(PI10) | \ + PIN_MODE_INPUT(PI11) | \ + PIN_MODE_INPUT(PI12) | \ + PIN_MODE_INPUT(PI13) | \ + PIN_MODE_INPUT(PI14) | \ + PIN_MODE_INPUT(PI15)) + +#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(PI00) | \ + PIN_OTYPE_PUSHPULL(PI01) | \ + PIN_OTYPE_PUSHPULL(PI02) | \ + PIN_OTYPE_PUSHPULL(PI03) | \ + PIN_OTYPE_PUSHPULL(PI04) | \ + PIN_OTYPE_PUSHPULL(PI05) | \ + PIN_OTYPE_PUSHPULL(PI06) | \ + PIN_OTYPE_PUSHPULL(PI07) | \ + PIN_OTYPE_PUSHPULL(PI08) | \ + PIN_OTYPE_PUSHPULL(PI09) | \ + PIN_OTYPE_PUSHPULL(PI10) | \ + PIN_OTYPE_PUSHPULL(PI11) | \ + PIN_OTYPE_PUSHPULL(PI12) | \ + PIN_OTYPE_PUSHPULL(PI13) | \ + PIN_OTYPE_PUSHPULL(PI14) | \ + PIN_OTYPE_PUSHPULL(PI15)) + +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_SPEED_VERYLOW(PI00) | \ + PIN_OSPEED_SPEED_VERYLOW(PI01) | \ + PIN_OSPEED_SPEED_VERYLOW(PI02) | \ + PIN_OSPEED_SPEED_VERYLOW(PI03) | \ + PIN_OSPEED_SPEED_VERYLOW(PI04) | \ + PIN_OSPEED_SPEED_VERYLOW(PI05) | \ + PIN_OSPEED_SPEED_VERYLOW(PI06) | \ + PIN_OSPEED_SPEED_VERYLOW(PI07) | \ + PIN_OSPEED_SPEED_VERYLOW(PI08) | \ + PIN_OSPEED_SPEED_VERYLOW(PI09) | \ + PIN_OSPEED_SPEED_VERYLOW(PI10) | \ + PIN_OSPEED_SPEED_VERYLOW(PI11) | \ + PIN_OSPEED_SPEED_VERYLOW(PI12) | \ + PIN_OSPEED_SPEED_VERYLOW(PI13) | \ + PIN_OSPEED_SPEED_VERYLOW(PI14) | \ + PIN_OSPEED_SPEED_VERYLOW(PI15)) + +#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLDOWN(PI00) | \ + PIN_PUPDR_PULLDOWN(PI01) | \ + PIN_PUPDR_PULLDOWN(PI02) | \ + PIN_PUPDR_PULLDOWN(PI03) | \ + PIN_PUPDR_PULLDOWN(PI04) | \ + PIN_PUPDR_PULLDOWN(PI05) | \ + PIN_PUPDR_PULLDOWN(PI06) | \ + PIN_PUPDR_PULLDOWN(PI07) | \ + PIN_PUPDR_PULLDOWN(PI08) | \ + PIN_PUPDR_PULLDOWN(PI09) | \ + PIN_PUPDR_PULLDOWN(PI10) | \ + PIN_PUPDR_PULLDOWN(PI11) | \ + PIN_PUPDR_PULLDOWN(PI12) | \ + PIN_PUPDR_PULLDOWN(PI13) | \ + PIN_PUPDR_PULLDOWN(PI14) | \ + PIN_PUPDR_PULLDOWN(PI15)) + +#define VAL_GPIOI_ODR (PIN_ODR_LEVEL_LOW(PI00) | \ + PIN_ODR_LEVEL_LOW(PI01) | \ + PIN_ODR_LEVEL_LOW(PI02) | \ + PIN_ODR_LEVEL_LOW(PI03) | \ + PIN_ODR_LEVEL_LOW(PI04) | \ + PIN_ODR_LEVEL_LOW(PI05) | \ + PIN_ODR_LEVEL_LOW(PI06) | \ + PIN_ODR_LEVEL_LOW(PI07) | \ + PIN_ODR_LEVEL_LOW(PI08) | \ + PIN_ODR_LEVEL_LOW(PI09) | \ + PIN_ODR_LEVEL_LOW(PI10) | \ + PIN_ODR_LEVEL_LOW(PI11) | \ + PIN_ODR_LEVEL_LOW(PI12) | \ + PIN_ODR_LEVEL_LOW(PI13) | \ + PIN_ODR_LEVEL_LOW(PI14) | \ + PIN_ODR_LEVEL_LOW(PI15)) + +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(PI00, 0) | \ + PIN_AFIO_AF(PI01, 0) | \ + PIN_AFIO_AF(PI02, 0) | \ + PIN_AFIO_AF(PI03, 0) | \ + PIN_AFIO_AF(PI04, 0) | \ + PIN_AFIO_AF(PI05, 0) | \ + PIN_AFIO_AF(PI06, 0) | \ + PIN_AFIO_AF(PI07, 0)) + +#define VAL_GPIOI_AFRH (PIN_AFIO_AF(PI08, 0) | \ + PIN_AFIO_AF(PI09, 0) | \ + PIN_AFIO_AF(PI10, 0) | \ + PIN_AFIO_AF(PI11, 0) | \ + PIN_AFIO_AF(PI12, 0) | \ + PIN_AFIO_AF(PI13, 0) | \ + PIN_AFIO_AF(PI14, 0) | \ + PIN_AFIO_AF(PI15, 0)) + +#define VAL_GPIOJ_MODER (PIN_MODE_INPUT(PJ00) | \ + PIN_MODE_INPUT(PJ01) | \ + PIN_MODE_INPUT(PJ02) | \ + PIN_MODE_INPUT(PJ03) | \ + PIN_MODE_INPUT(PJ04) | \ + PIN_MODE_INPUT(PJ05) | \ + PIN_MODE_INPUT(PJ06) | \ + PIN_MODE_INPUT(PJ07) | \ + PIN_MODE_INPUT(PJ08) | \ + PIN_MODE_INPUT(PJ09) | \ + PIN_MODE_INPUT(PJ10) | \ + PIN_MODE_INPUT(PJ11) | \ + PIN_MODE_INPUT(PJ12) | \ + PIN_MODE_INPUT(PJ13) | \ + PIN_MODE_INPUT(PJ14) | \ + PIN_MODE_INPUT(PJ15)) + +#define VAL_GPIOJ_OTYPER (PIN_OTYPE_PUSHPULL(PJ00) | \ + PIN_OTYPE_PUSHPULL(PJ01) | \ + PIN_OTYPE_PUSHPULL(PJ02) | \ + PIN_OTYPE_PUSHPULL(PJ03) | \ + PIN_OTYPE_PUSHPULL(PJ04) | \ + PIN_OTYPE_PUSHPULL(PJ05) | \ + PIN_OTYPE_PUSHPULL(PJ06) | \ + PIN_OTYPE_PUSHPULL(PJ07) | \ + PIN_OTYPE_PUSHPULL(PJ08) | \ + PIN_OTYPE_PUSHPULL(PJ09) | \ + PIN_OTYPE_PUSHPULL(PJ10) | \ + PIN_OTYPE_PUSHPULL(PJ11) | \ + PIN_OTYPE_PUSHPULL(PJ12) | \ + PIN_OTYPE_PUSHPULL(PJ13) | \ + PIN_OTYPE_PUSHPULL(PJ14) | \ + PIN_OTYPE_PUSHPULL(PJ15)) + +#define VAL_GPIOJ_OSPEEDR (PIN_OSPEED_SPEED_VERYLOW(PJ00) | \ + PIN_OSPEED_SPEED_VERYLOW(PJ01) | \ + PIN_OSPEED_SPEED_VERYLOW(PJ02) | \ + PIN_OSPEED_SPEED_VERYLOW(PJ03) | \ + PIN_OSPEED_SPEED_VERYLOW(PJ04) | \ + PIN_OSPEED_SPEED_VERYLOW(PJ05) | \ + PIN_OSPEED_SPEED_VERYLOW(PJ06) | \ + PIN_OSPEED_SPEED_VERYLOW(PJ07) | \ + PIN_OSPEED_SPEED_VERYLOW(PJ08) | \ + PIN_OSPEED_SPEED_VERYLOW(PJ09) | \ + PIN_OSPEED_SPEED_VERYLOW(PJ10) | \ + PIN_OSPEED_SPEED_VERYLOW(PJ11) | \ + PIN_OSPEED_SPEED_VERYLOW(PJ12) | \ + PIN_OSPEED_SPEED_VERYLOW(PJ13) | \ + PIN_OSPEED_SPEED_VERYLOW(PJ14) | \ + PIN_OSPEED_SPEED_VERYLOW(PJ15)) + +#define VAL_GPIOJ_PUPDR (PIN_PUPDR_PULLDOWN(PJ00) | \ + PIN_PUPDR_PULLDOWN(PJ01) | \ + PIN_PUPDR_PULLDOWN(PJ02) | \ + PIN_PUPDR_PULLDOWN(PJ03) | \ + PIN_PUPDR_PULLDOWN(PJ04) | \ + PIN_PUPDR_PULLDOWN(PJ05) | \ + PIN_PUPDR_PULLDOWN(PJ06) | \ + PIN_PUPDR_PULLDOWN(PJ07) | \ + PIN_PUPDR_PULLDOWN(PJ08) | \ + PIN_PUPDR_PULLDOWN(PJ09) | \ + PIN_PUPDR_PULLDOWN(PJ10) | \ + PIN_PUPDR_PULLDOWN(PJ11) | \ + PIN_PUPDR_PULLDOWN(PJ12) | \ + PIN_PUPDR_PULLDOWN(PJ13) | \ + PIN_PUPDR_PULLDOWN(PJ14) | \ + PIN_PUPDR_PULLDOWN(PJ15)) + +#define VAL_GPIOJ_ODR (PIN_ODR_LEVEL_LOW(PJ00) | \ + PIN_ODR_LEVEL_LOW(PJ01) | \ + PIN_ODR_LEVEL_LOW(PJ02) | \ + PIN_ODR_LEVEL_LOW(PJ03) | \ + PIN_ODR_LEVEL_LOW(PJ04) | \ + PIN_ODR_LEVEL_LOW(PJ05) | \ + PIN_ODR_LEVEL_LOW(PJ06) | \ + PIN_ODR_LEVEL_LOW(PJ07) | \ + PIN_ODR_LEVEL_LOW(PJ08) | \ + PIN_ODR_LEVEL_LOW(PJ09) | \ + PIN_ODR_LEVEL_LOW(PJ10) | \ + PIN_ODR_LEVEL_LOW(PJ11) | \ + PIN_ODR_LEVEL_LOW(PJ12) | \ + PIN_ODR_LEVEL_LOW(PJ13) | \ + PIN_ODR_LEVEL_LOW(PJ14) | \ + PIN_ODR_LEVEL_LOW(PJ15)) + +#define VAL_GPIOJ_AFRL (PIN_AFIO_AF(PJ00, 0) | \ + PIN_AFIO_AF(PJ01, 0) | \ + PIN_AFIO_AF(PJ02, 0) | \ + PIN_AFIO_AF(PJ03, 0) | \ + PIN_AFIO_AF(PJ04, 0) | \ + PIN_AFIO_AF(PJ05, 0) | \ + PIN_AFIO_AF(PJ06, 0) | \ + PIN_AFIO_AF(PJ07, 0)) + +#define VAL_GPIOJ_AFRH (PIN_AFIO_AF(PJ08, 0) | \ + PIN_AFIO_AF(PJ09, 0) | \ + PIN_AFIO_AF(PJ10, 0) | \ + PIN_AFIO_AF(PJ11, 0) | \ + PIN_AFIO_AF(PJ12, 0) | \ + PIN_AFIO_AF(PJ13, 0) | \ + PIN_AFIO_AF(PJ14, 0) | \ + PIN_AFIO_AF(PJ15, 0)) + +#define VAL_GPIOK_MODER (PIN_MODE_INPUT(PK00) | \ + PIN_MODE_INPUT(PK01) | \ + PIN_MODE_INPUT(PK02) | \ + PIN_MODE_INPUT(PK03) | \ + PIN_MODE_INPUT(PK04) | \ + PIN_MODE_INPUT(PK05) | \ + PIN_MODE_INPUT(PK06) | \ + PIN_MODE_INPUT(PK07) | \ + PIN_MODE_INPUT(PK08) | \ + PIN_MODE_INPUT(PK09) | \ + PIN_MODE_INPUT(PK10) | \ + PIN_MODE_INPUT(PK11) | \ + PIN_MODE_INPUT(PK12) | \ + PIN_MODE_INPUT(PK13) | \ + PIN_MODE_INPUT(PK14) | \ + PIN_MODE_INPUT(PK15)) + +#define VAL_GPIOK_OTYPER (PIN_OTYPE_PUSHPULL(PK00) | \ + PIN_OTYPE_PUSHPULL(PK01) | \ + PIN_OTYPE_PUSHPULL(PK02) | \ + PIN_OTYPE_PUSHPULL(PK03) | \ + PIN_OTYPE_PUSHPULL(PK04) | \ + PIN_OTYPE_PUSHPULL(PK05) | \ + PIN_OTYPE_PUSHPULL(PK06) | \ + PIN_OTYPE_PUSHPULL(PK07) | \ + PIN_OTYPE_PUSHPULL(PK08) | \ + PIN_OTYPE_PUSHPULL(PK09) | \ + PIN_OTYPE_PUSHPULL(PK10) | \ + PIN_OTYPE_PUSHPULL(PK11) | \ + PIN_OTYPE_PUSHPULL(PK12) | \ + PIN_OTYPE_PUSHPULL(PK13) | \ + PIN_OTYPE_PUSHPULL(PK14) | \ + PIN_OTYPE_PUSHPULL(PK15)) + +#define VAL_GPIOK_OSPEEDR (PIN_OSPEED_SPEED_VERYLOW(PK00) | \ + PIN_OSPEED_SPEED_VERYLOW(PK01) | \ + PIN_OSPEED_SPEED_VERYLOW(PK02) | \ + PIN_OSPEED_SPEED_VERYLOW(PK03) | \ + PIN_OSPEED_SPEED_VERYLOW(PK04) | \ + PIN_OSPEED_SPEED_VERYLOW(PK05) | \ + PIN_OSPEED_SPEED_VERYLOW(PK06) | \ + PIN_OSPEED_SPEED_VERYLOW(PK07) | \ + PIN_OSPEED_SPEED_VERYLOW(PK08) | \ + PIN_OSPEED_SPEED_VERYLOW(PK09) | \ + PIN_OSPEED_SPEED_VERYLOW(PK10) | \ + PIN_OSPEED_SPEED_VERYLOW(PK11) | \ + PIN_OSPEED_SPEED_VERYLOW(PK12) | \ + PIN_OSPEED_SPEED_VERYLOW(PK13) | \ + PIN_OSPEED_SPEED_VERYLOW(PK14) | \ + PIN_OSPEED_SPEED_VERYLOW(PK15)) + +#define VAL_GPIOK_PUPDR (PIN_PUPDR_PULLDOWN(PK00) | \ + PIN_PUPDR_PULLDOWN(PK01) | \ + PIN_PUPDR_PULLDOWN(PK02) | \ + PIN_PUPDR_PULLDOWN(PK03) | \ + PIN_PUPDR_PULLDOWN(PK04) | \ + PIN_PUPDR_PULLDOWN(PK05) | \ + PIN_PUPDR_PULLDOWN(PK06) | \ + PIN_PUPDR_PULLDOWN(PK07) | \ + PIN_PUPDR_PULLDOWN(PK08) | \ + PIN_PUPDR_PULLDOWN(PK09) | \ + PIN_PUPDR_PULLDOWN(PK10) | \ + PIN_PUPDR_PULLDOWN(PK11) | \ + PIN_PUPDR_PULLDOWN(PK12) | \ + PIN_PUPDR_PULLDOWN(PK13) | \ + PIN_PUPDR_PULLDOWN(PK14) | \ + PIN_PUPDR_PULLDOWN(PK15)) + +#define VAL_GPIOK_ODR (PIN_ODR_LEVEL_LOW(PK00) | \ + PIN_ODR_LEVEL_LOW(PK01) | \ + PIN_ODR_LEVEL_LOW(PK02) | \ + PIN_ODR_LEVEL_LOW(PK03) | \ + PIN_ODR_LEVEL_LOW(PK04) | \ + PIN_ODR_LEVEL_LOW(PK05) | \ + PIN_ODR_LEVEL_LOW(PK06) | \ + PIN_ODR_LEVEL_LOW(PK07) | \ + PIN_ODR_LEVEL_LOW(PK08) | \ + PIN_ODR_LEVEL_LOW(PK09) | \ + PIN_ODR_LEVEL_LOW(PK10) | \ + PIN_ODR_LEVEL_LOW(PK11) | \ + PIN_ODR_LEVEL_LOW(PK12) | \ + PIN_ODR_LEVEL_LOW(PK13) | \ + PIN_ODR_LEVEL_LOW(PK14) | \ + PIN_ODR_LEVEL_LOW(PK15)) + +#define VAL_GPIOK_AFRL (PIN_AFIO_AF(PK00, 0) | \ + PIN_AFIO_AF(PK01, 0) | \ + PIN_AFIO_AF(PK02, 0) | \ + PIN_AFIO_AF(PK03, 0) | \ + PIN_AFIO_AF(PK04, 0) | \ + PIN_AFIO_AF(PK05, 0) | \ + PIN_AFIO_AF(PK06, 0) | \ + PIN_AFIO_AF(PK07, 0)) + +#define VAL_GPIOK_AFRH (PIN_AFIO_AF(PK08, 0) | \ + PIN_AFIO_AF(PK09, 0) | \ + PIN_AFIO_AF(PK10, 0) | \ + PIN_AFIO_AF(PK11, 0) | \ + PIN_AFIO_AF(PK12, 0) | \ + PIN_AFIO_AF(PK13, 0) | \ + PIN_AFIO_AF(PK14, 0) | \ + PIN_AFIO_AF(PK15, 0)) + +#define AF_PA11_OTG_FS_DM 10U +#define AF_LINE_A11_OTG_FS_DM 10U +#define AF_PA12_OTG_FS_DP 10U +#define AF_LINE_A12_OTG_FS_DP 10U +#define AF_PA13_SWDIO 0U +#define AF_LINE_A13_SWDIO 0U +#define AF_PA14_SWCLK 0U +#define AF_LINE_A14_SWCLK 0U +#define AF_PA15_UART7_TX 12U +#define AF_LINE_A15_UART7_TX 12U +#define AF_PB03_UART7_RX 12U +#define AF_LINE_B03_UART7_RX 12U +#define AF_PB05_DSHOT_RX 1U +#define AF_LINE_B05_DSHOT_RX 1U +#define AF_PB06_SRVB1 2U +#define AF_LINE_B06_SRVB1 2U +#define AF_PB07_SRVB2 2U +#define AF_LINE_B07_SRVB2 2U +#define AF_PB08_SRVB3 2U +#define AF_LINE_B08_SRVB3 2U +#define AF_PB09_SRVB4 2U +#define AF_LINE_B09_SRVB4 2U +#define AF_PB10_I2C2_SCL_EXTERNAL 4U +#define AF_LINE_B10_I2C2_SCL_EXTERNAL 4U +#define AF_PB11_I2C2_SDA_EXTERNAL 4U +#define AF_LINE_B11_I2C2_SDA_EXTERNAL 4U +#define AF_PB14_SPI2_EXTERNAL_MISO 5U +#define AF_LINE_B14_SPI2_EXTERNAL_MISO 5U +#define AF_PB15_SPI2_EXTERNAL_MOSI 5U +#define AF_LINE_B15_SPI2_EXTERNAL_MOSI 5U +#define AF_PC08_SDMMC1_D0 12U +#define AF_LINE_C08_SDMMC1_D0 12U +#define AF_PC09_SDMMC1_D1 12U +#define AF_LINE_C09_SDMMC1_D1 12U +#define AF_PC10_SDMMC1_D2 12U +#define AF_LINE_C10_SDMMC1_D2 12U +#define AF_PC11_SDMMC1_D3 12U +#define AF_LINE_C11_SDMMC1_D3 12U +#define AF_PC12_SDMMC1_CK 12U +#define AF_LINE_C12_SDMMC1_CK 12U +#define AF_PC14_OSC32_IN 0U +#define AF_LINE_C14_OSC32_IN 0U +#define AF_PC15_OSC32_OUT 0U +#define AF_LINE_C15_OSC32_OUT 0U +#define AF_PD00_CAN_RX 9U +#define AF_LINE_D00_CAN_RX 9U +#define AF_PD01_CAN_TX 9U +#define AF_LINE_D01_CAN_TX 9U +#define AF_PD02_SDMMC1_CMD 12U +#define AF_LINE_D02_SDMMC1_CMD 12U +#define AF_PD03_SPI2_EXTERNAL_CLK 5U +#define AF_LINE_D03_SPI2_EXTERNAL_CLK 5U +#define AF_PD05_UART_TX2 7U +#define AF_LINE_D05_UART_TX2 7U +#define AF_PD06_UART_RX2 7U +#define AF_LINE_D06_UART_RX2 7U +#define AF_PD08_UART_TX3 7U +#define AF_LINE_D08_UART_TX3 7U +#define AF_PD09_UART_RX3 7U +#define AF_LINE_D09_UART_RX3 7U +#define AF_PD12_I2C4_SCL_EXTERNAL 4U +#define AF_LINE_D12_I2C4_SCL_EXTERNAL 4U +#define AF_PD13_I2C4_SDA_EXTERNAL 4U +#define AF_LINE_D13_I2C4_SDA_EXTERNAL 4U +#define AF_PE00_RC1 8U +#define AF_LINE_E00_RC1 8U +#define AF_PE02_SPI4_INTERNAL_CLK 5U +#define AF_LINE_E02_SPI4_INTERNAL_CLK 5U +#define AF_PE05_SPI4_INTERNAL_MISO 5U +#define AF_LINE_E05_SPI4_INTERNAL_MISO 5U +#define AF_PE06_SPI4_INTERNAL_MOSI 5U +#define AF_LINE_E06_SPI4_INTERNAL_MOSI 5U +#define AF_PE09_SRVA1 1U +#define AF_LINE_E09_SRVA1 1U +#define AF_PE11_SRVA2 1U +#define AF_LINE_E11_SRVA2 1U +#define AF_PE13_SRVA3 1U +#define AF_LINE_E13_SRVA3 1U +#define AF_PE14_SRVA4 1U +#define AF_LINE_E14_SRVA4 1U +#define AF_PH00_OSC_IN 0U +#define AF_LINE_H00_OSC_IN 0U +#define AF_PH01_OSC_OUT 0U +#define AF_LINE_H01_OSC_OUT 0U + + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + diff --git a/sw/airborne/boards/tawaki/chibios/v1.0/board.mk b/sw/airborne/boards/tawaki/chibios/v1.0/board.mk new file mode 100644 index 00000000000..5a109515f46 --- /dev/null +++ b/sw/airborne/boards/tawaki/chibios/v1.0/board.mk @@ -0,0 +1,20 @@ +# +# ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Required include directories +BOARDINC = $(CHIBIOS_BOARD_DIR) + +# List of all the board related files. +BOARDSRC = ${BOARDINC}/board.c diff --git a/sw/airborne/boards/tawaki/chibios/v1.0/ffconf.h b/sw/airborne/boards/tawaki/chibios/v1.0/ffconf.h new file mode 100644 index 00000000000..f6c9dafc1c3 --- /dev/null +++ b/sw/airborne/boards/tawaki/chibios/v1.0/ffconf.h @@ -0,0 +1,270 @@ +/* CHIBIOS FIX */ +#include "ch.h" + +/*---------------------------------------------------------------------------/ +/ FatFs - FAT file system module configuration file +/---------------------------------------------------------------------------*/ + +#define FFCONF_DEF 87030 /* Revision ID */ + +/*---------------------------------------------------------------------------/ +/ Function Configurations +/---------------------------------------------------------------------------*/ + +#define FF_FS_READONLY 0 +/* This option switches read-only configuration. (0:Read/Write or 1:Read-only) +/ Read-only configuration removes writing API functions, f_write(), f_sync(), +/ f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree() +/ and optional writing functions as well. */ + + +#define FF_FS_MINIMIZE 0 +/* This option defines minimization level to remove some basic API functions. +/ +/ 0: All basic functions are enabled. +/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename() +/ are removed. +/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1. +/ 3: f_lseek() function is removed in addition to 2. */ + + +#define FF_USE_STRFUNC 0 +/* This option switches string functions, f_gets(), f_putc(), f_puts() and +/ f_printf(). +/ +/ 0: Disable string functions. +/ 1: Enable without LF-CRLF conversion. +/ 2: Enable with LF-CRLF conversion. */ + + +#define FF_USE_FIND 1 +/* This option switches filtered directory read functions, f_findfirst() and +/ f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */ + + +#define FF_USE_MKFS 1 +/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */ + + +#define FF_USE_FASTSEEK 1 +/* This option switches fast seek function. (0:Disable or 1:Enable) */ + + +#define FF_USE_EXPAND 1 +/* This option switches f_expand function. (0:Disable or 1:Enable) */ + + +#define FF_USE_CHMOD 1 +/* This option switches attribute manipulation functions, f_chmod() and f_utime(). +/ (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */ + + +#define FF_USE_LABEL 1 +/* This option switches volume label functions, f_getlabel() and f_setlabel(). +/ (0:Disable or 1:Enable) */ + + +#define FF_USE_FORWARD 1 +/* This option switches f_forward() function. (0:Disable or 1:Enable) */ + + +/*---------------------------------------------------------------------------/ +/ Locale and Namespace Configurations +/---------------------------------------------------------------------------*/ + +#define FF_CODE_PAGE 850 +/* This option specifies the OEM code page to be used on the target system. +/ Incorrect setting of the code page can cause a file open failure. +/ +/ 1 - ASCII (No extended character. Non-LFN cfg. only) +/ 437 - U.S. +/ 720 - Arabic +/ 737 - Greek +/ 771 - KBL +/ 775 - Baltic +/ 850 - Latin 1 +/ 852 - Latin 2 +/ 855 - Cyrillic +/ 857 - Turkish +/ 860 - Portuguese +/ 861 - Icelandic +/ 862 - Hebrew +/ 863 - Canadian French +/ 864 - Arabic +/ 865 - Nordic +/ 866 - Russian +/ 869 - Greek 2 +/ 932 - Japanese (DBCS) +/ 936 - Simplified Chinese (DBCS) +/ 949 - Korean (DBCS) +/ 950 - Traditional Chinese (DBCS) +*/ + + +#define FF_USE_LFN 3 +#define FF_MAX_LFN 255 +/* The FF_USE_LFN switches the support of long file name (LFN). +/ +/ 0: Disable support of LFN. _MAX_LFN has no effect. +/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe. +/ 2: Enable LFN with dynamic working buffer on the STACK. +/ 3: Enable LFN with dynamic working buffer on the HEAP. +/ +/ To enable the LFN, Unicode handling functions (option/unicode.c) must be added +/ to the project. The working buffer occupies (_MAX_LFN + 1) * 2 bytes and +/ additional 608 bytes at exFAT enabled. _MAX_LFN can be in range from 12 to 255. +/ It should be set 255 to support full featured LFN operations. +/ When use stack for the working buffer, take care on stack overflow. When use heap +/ memory for the working buffer, memory management functions, ff_memalloc() and +/ ff_memfree(), must be added to the project. */ + + +#define FF_LFN_UNICODE 0 +/* This option switches character encoding on the API. (0:ANSI/OEM or 1:UTF-16) +/ To use Unicode string for the path name, enable LFN and set _LFN_UNICODE = 1. +/ This option also affects behavior of string I/O functions. */ + + +#define FF_STRF_ENCODE 3 +/* When _LFN_UNICODE == 1, this option selects the character encoding ON THE FILE to +/ be read/written via string I/O functions, f_gets(), f_putc(), f_puts and f_printf(). +/ +/ 0: ANSI/OEM +/ 1: UTF-16LE +/ 2: UTF-16BE +/ 3: UTF-8 +/ +/ This option has no effect when _LFN_UNICODE == 0. */ + + +#define FF_FS_RPATH 1 +/* This option configures support of relative path. +/ +/ 0: Disable relative path and remove related functions. +/ 1: Enable relative path. f_chdir() and f_chdrive() are available. +/ 2: f_getcwd() function is available in addition to 1. +*/ + + +/*---------------------------------------------------------------------------/ +/ Drive/Volume Configurations +/---------------------------------------------------------------------------*/ + +#define FF_VOLUMES 1 +/* Number of volumes (logical drives) to be used. */ + + +#define FF_STR_VOLUME_ID 0 +#define FF_VOLUME_STRS "RAM","NAND","CF","SD","SD2","USB","USB2","USB3" +/* _STR_VOLUME_ID switches string support of volume ID. +/ When _STR_VOLUME_ID is set to 1, also pre-defined strings can be used as drive +/ number in the path name. _VOLUME_STRS defines the drive ID strings for each +/ logical drives. Number of items must be equal to _VOLUMES. Valid characters for +/ the drive ID strings are: A-Z and 0-9. */ + + +#define FF_MULTI_PARTITION 0 +/* This option switches support of multi-partition on a physical drive. +/ By default (0), each logical drive number is bound to the same physical drive +/ number and only an FAT volume found on the physical drive will be mounted. +/ When multi-partition is enabled (1), each logical drive number can be bound to +/ arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk() +/ funciton will be available. */ + + +#define FF_MIN_SS 512 +#define FF_MAX_SS 512 +/* These options configure the range of sector size to be supported. (512, 1024, +/ 2048 or 4096) Always set both 512 for most systems, all type of memory cards and +/ harddisk. But a larger value may be required for on-board flash memory and some +/ type of optical media. When _MAX_SS is larger than _MIN_SS, FatFs is configured +/ to variable sector size and GET_SECTOR_SIZE command must be implemented to the +/ disk_ioctl() function. */ + + +#define FF_USE_TRIM 0 +/* This option switches support of ATA-TRIM. (0:Disable or 1:Enable) +/ To enable Trim function, also CTRL_TRIM command should be implemented to the +/ disk_ioctl() function. */ + + +#define FF_FS_NOFSINFO 0 +/* If you need to know correct free space on the FAT32 volume, set bit 0 of this +/ option, and f_getfree() function at first time after volume mount will force +/ a full FAT scan. Bit 1 controls the use of last allocated cluster number. +/ +/ bit0=0: Use free cluster count in the FSINFO if available. +/ bit0=1: Do not trust free cluster count in the FSINFO. +/ bit1=0: Use last allocated cluster number in the FSINFO if available. +/ bit1=1: Do not trust last allocated cluster number in the FSINFO. +*/ + + + +/*---------------------------------------------------------------------------/ +/ System Configurations +/---------------------------------------------------------------------------*/ + +#define FF_FS_TINY 0 +/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny) +/ At the tiny configuration, size of file object (FIL) is reduced _MAX_SS bytes. +/ Instead of private sector buffer eliminated from the file object, common sector +/ buffer in the file system object (FATFS) is used for the file data transfer. */ + + +#define FF_FS_EXFAT 1 +/* This option switches support of exFAT file system. (0:Disable or 1:Enable) +/ When enable exFAT, also LFN needs to be enabled. (FF_USE_LFN >= 1) +/ Note that enabling exFAT discards C89 compatibility. */ + + +#define FF_FS_NORTC 0 +#define FF_NORTC_MON 1 +#define FF_NORTC_MDAY 1 +#define FF_NORTC_YEAR 2016 +/* The option FF_FS_NORTC switches timestamp functiton. If the system does not have +/ any RTC function or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable +/ the timestamp function. All objects modified by FatFs will have a fixed timestamp +/ defined by _NORTC_MON, _NORTC_MDAY and _NORTC_YEAR in local time. +/ To enable timestamp function (FF_FS_NORTC = 0), get_fattime() function need to be +/ added to the project to get current time form real-time clock. _NORTC_MON, +/ _NORTC_MDAY and _NORTC_YEAR have no effect. +/ These options have no effect at read-only configuration (FF_FS_READONLY = 1). */ + + +#define FF_FS_LOCK 0 +/* The option FF_FS_LOCK switches file lock function to control duplicated file open +/ and illegal operation to open objects. This option must be 0 when FF_FS_READONLY +/ is 1. +/ +/ 0: Disable file lock function. To avoid volume corruption, application program +/ should avoid illegal open, remove and rename to the open objects. +/ >0: Enable file lock function. The value defines how many files/sub-directories +/ can be opened simultaneously under file lock control. Note that the file +/ lock control is independent of re-entrancy. */ + + +#define FF_FS_REENTRANT 1 +#define FF_FS_TIMEOUT TIME_MS2I(1000) +#define FF_SYNC_t semaphore_t* +/* The option FF_FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs +/ module itself. Note that regardless of this option, file access to different +/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs() +/ and f_fdisk() function, are always not re-entrant. Only file/directory access +/ to the same volume is under control of this function. +/ +/ 0: Disable re-entrancy. FF_FS_TIMEOUT and _SYNC_t have no effect. +/ 1: Enable re-entrancy. Also user provided synchronization handlers, +/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj() +/ function, must be added to the project. Samples are available in +/ option/syscall.c. +/ +/ The FF_FS_TIMEOUT defines timeout period in unit of time tick. +/ The _SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*, +/ SemaphoreHandle_t and etc.. A header file for O/S definitions needs to be +/ included somewhere in the scope of ff.h. */ + +/* #include // O/S definitions */ + + +/*--- End of configuration options ---*/ diff --git a/sw/airborne/boards/tawaki/chibios/v1.0/mcuconf.h b/sw/airborne/boards/tawaki/chibios/v1.0/mcuconf.h new file mode 100644 index 00000000000..144ed5d58b3 --- /dev/null +++ b/sw/airborne/boards/tawaki/chibios/v1.0/mcuconf.h @@ -0,0 +1,483 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _MCUCONF_H_ +#define _MCUCONF_H_ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F7xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE +#define STM32_HSI_ENABLED TRUE +#if HAL_USE_RTC +#define STM32_LSI_ENABLED TRUE +#else +#define STM32_LSI_ENABLED FALSE +#endif +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 16 +#define STM32_PLLN_VALUE 432 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#if HAL_USE_RTC +#define STM32_RTCSEL STM32_RTCSEL_LSI +#else +#define STM32_RTCSEL STM32_RTCSEL_NOCLOCK +#endif +#define STM32_RTCPRE_VALUE 25 +#define STM32_MCO1SEL STM32_MCO1SEL_HSE +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_I2SSRC STM32_I2SSRC_PLLI2S +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SP_VALUE 4 +#define STM32_PLLI2SQ_VALUE 4 +#define STM32_PLLI2SR_VALUE 4 +#define STM32_PLLSAIN_VALUE 192 +#define STM32_PLLSAIP_VALUE 4 +#define STM32_PLLSAIQ_VALUE 4 +#define STM32_PLLSAIR_VALUE 4 +#define STM32_PLLSAIDIVR_VALUE 2 +#define STM32_SAI1SEL STM32_SAI1SEL_OFF +#define STM32_SAI2SEL STM32_SAI2SEL_OFF +#define STM32_USART1SEL STM32_USART1SEL_PCLK2 +#define STM32_USART2SEL STM32_USART2SEL_PCLK1 +#define STM32_USART3SEL STM32_USART3SEL_PCLK1 +#define STM32_UART4SEL STM32_UART4SEL_PCLK1 +#define STM32_UART5SEL STM32_UART5SEL_PCLK1 +#define STM32_USART6SEL STM32_USART6SEL_PCLK2 +#define STM32_UART7SEL STM32_UART7SEL_PCLK1 +#define STM32_UART8SEL STM32_UART8SEL_PCLK1 +#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1 // STM32_I2C1SEL_SYSCLK +#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1 +#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1 +#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1 +#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 +#define STM32_CECSEL STM32_CECSEL_LSE +#define STM32_CK48MSEL STM32_CK48MSEL_PLL +#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK +#define STM32_SRAM2_NOCACHE FALSE + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#if USE_CAN1 +#define STM32_CAN_USE_CAN1 TRUE +#else +#define STM32_CAN_USE_CAN1 FALSE +#endif +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +//#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE // keep free if in tickless mode +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +//#if USE_I2C1 +//#define STM32_I2C_USE_I2C1 TRUE +//#else +#define STM32_I2C_USE_I2C1 FALSE // incompatible with I2C2 and I2C4 +//#endif +#if USE_I2C2 +#define STM32_I2C_USE_I2C2 TRUE +#else +#define STM32_I2C_USE_I2C2 FALSE +#endif +#define STM32_I2C_USE_I2C3 FALSE +#if USE_I2C4 +#define STM32_I2C_USE_I2C4 TRUE +#else +#define STM32_I2C_USE_I2C4 FALSE +#endif +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +//#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +//#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) // FIXME check if 5 is really not possible +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C4_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C4_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#ifdef USE_PWM_INPUT1 +#define STM32_ICU_USE_TIM2 TRUE +#else +#define STM32_ICU_USE_TIM2 FALSE // keep free if in tickless mode +#endif +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#if RADIO_CONTROL_TYPE_PPM +#define STM32_ICU_USE_TIM5 TRUE +#else +#define STM32_ICU_USE_TIM5 FALSE +#endif +#ifdef USE_PWM_INPUT2 +#define STM32_ICU_USE_TIM8 TRUE +#else +#define STM32_ICU_USE_TIM8 FALSE +#endif +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#ifndef STM32_PWM_USE_TIM1 +#define STM32_PWM_USE_TIM1 TRUE +#endif +#ifndef STM32_PWM_USE_TIM2 +#define STM32_PWM_USE_TIM2 FALSE // keep free if in tickless mode, can be used in systick mode +#endif +#define STM32_PWM_USE_TIM3 FALSE +#ifndef STM32_PWM_USE_TIM4 +#define STM32_PWM_USE_TIM4 TRUE +#endif +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +#define STM32_PWM1_UP_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_PWM1_UP_DMA_CHANNEL 6 +#define STM32_PWM1_UP_DMA_IRQ_PRIORITY 6 +#define STM32_PWM1_UP_DMA_PRIORITY 2 + +/* + * SERIAL driver system settings. + */ +#if USE_UART1 +#define STM32_SERIAL_USE_USART1 TRUE +#else +#define STM32_SERIAL_USE_USART1 FALSE +#endif +#if USE_UART2 +#define STM32_SERIAL_USE_USART2 TRUE +#else +#define STM32_SERIAL_USE_USART2 FALSE +#endif +#if USE_UART3 +#define STM32_SERIAL_USE_USART3 TRUE +#else +#define STM32_SERIAL_USE_USART3 FALSE +#endif +#if USE_UART4 +#define STM32_SERIAL_USE_UART4 TRUE +#else +#define STM32_SERIAL_USE_UART4 FALSE +#endif +#if USE_UART5 +#define STM32_SERIAL_USE_UART5 TRUE +#else +#define STM32_SERIAL_USE_UART5 FALSE +#endif +#if USE_UART6 +#define STM32_SERIAL_USE_USART6 TRUE +#else +#define STM32_SERIAL_USE_USART6 FALSE +#endif +#if USE_UART7 +#define STM32_SERIAL_USE_UART7 TRUE +#else +#define STM32_SERIAL_USE_UART7 FALSE +#endif +#if USE_UART8 +#define STM32_SERIAL_USE_UART8 TRUE +#else +#define STM32_SERIAL_USE_UART8 FALSE +#endif +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 +#define STM32_SERIAL_UART7_PRIORITY 12 +#define STM32_SERIAL_UART8_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#if USE_SPI2 +#define STM32_SPI_USE_SPI2 TRUE +#else +#define STM32_SPI_USE_SPI2 FALSE +#endif +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_USE_SPI4 TRUE +#define STM32_SPI_USE_SPI5 FALSE +#define STM32_SPI_USE_SPI6 FALSE +//#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +//#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +//#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +//#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +//#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +//#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +//#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +//#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI5_DMA_PRIORITY 1 +#define STM32_SPI_SPI6_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI4_IRQ_PRIORITY 10 +#define STM32_SPI_SPI5_IRQ_PRIORITY 10 +#define STM32_SPI_SPI6_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE /* DMA OK */ +#define STM32_UART_USE_USART2 FALSE /* NO DMA AVAIL */ +#define STM32_UART_USE_USART3 FALSE /* DMA OK */ +#define STM32_UART_USE_UART4 FALSE /* NO DMA AVAIL */ +#define STM32_UART_USE_UART5 FALSE /* NO DMA AVAIL */ +#define STM32_UART_USE_USART6 FALSE /* NO DMA AVAIL */ +#define STM32_UART_USE_UART7 FALSE /* NO DMA AVAIL */ +#define STM32_UART_USE_UART8 FALSE /* NO DMA AVAIL */ +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +/* #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) */ +/* #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) */ +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +/* #define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) */ +/* #define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) */ +/* #define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) */ +/* #define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) */ +/* #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) */ +/* #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) */ +/* #define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) */ +/* #define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) */ +/* #define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) */ +/* #define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) */ +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_UART7_DMA_PRIORITY 0 +#define STM32_UART_UART8_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 TRUE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_USE_SDMMC1 TRUE +#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDMMC_WRITE_TIMEOUT 250 +#define STM32_SDC_SDMMC_READ_TIMEOUT 25 +#define STM32_SDC_SDMMC_CLOCK_DELAY 10 +#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_SDC_SDMMC1_DMA_PRIORITY 3 +#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 + +/* + sdlog message buffer and queue configuration + */ +#define SDLOG_QUEUE_BUCKETS 1024 +#define SDLOG_MAX_MESSAGE_LEN 300 +#define SDLOG_NUM_FILES 2 +#define SDLOG_ALL_BUFFERS_SIZE (SDLOG_NUM_FILES*16*1024) + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + + +//#define CH_HEAP_SIZE (32*1024) +//#define CH_HEAP_USE_TLSF 1 // if 0 or undef, chAlloc will be used + + + +#endif /* _MCUCONF_H_ */ diff --git a/sw/airborne/boards/tawaki/chibios/v1.0/tawaki.cfg b/sw/airborne/boards/tawaki/chibios/v1.0/tawaki.cfg new file mode 100644 index 00000000000..ff2e26b20aa --- /dev/null +++ b/sw/airborne/boards/tawaki/chibios/v1.0/tawaki.cfg @@ -0,0 +1,139 @@ +MCU_MODEL = STM32F777VIHx +CHIBIOS_VERSION = 3.0 + +HEADER +/* + * Board identifier. + */ +#define BOARD_TAWAKI +#define BOARD_NAME "Tawaki Autopilot" + +/* + * Board oscillators-related settings. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 32768U +#endif + +#define STM32_LSEDRV (3U << 3U) + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 16000000U +#endif + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 300U + +/* + * MCU type as defined in the ST header. + */ +#define STM32F777xx + +CONFIG + + +# PIN NAME PERIPH_TYPE AF_NUMBER or +# PIN NAME FUNCTION PP_or_OPENDRAIN PIN_SPEED PULL_RESISTOR INITIAL_LEVEL AF_NUMBER +# SPEED : SPEED_VERYLOW, SPEED_LOW, SPEED_MEDIUM, SPEED_HIGH +# +# DEFAULT AND SYS +# +# 'SYS' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'], +# 'ADC' => ['ANALOG', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_LOW'], +# 'PWM' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_LOW'], +# 'ICU' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'], +# 'I2C' => ['ALTERNATE', 'OPENDRAIN', 'SPEED_HIGH', 'PULLUP', 'LEVEL_HIGH'], +# 'SPI' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'], +# 'UART' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'PULLUP', 'LEVEL_HIGH'], +# 'OTG' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'], +# 'ETH' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'], +# 'FSMC' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'], +# 'SDIO' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'PULLUP', 'LEVEL_HIGH'], +# 'SDIOCK' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'], +# 'CAN' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'], +# 'DCMI' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'], +# 'LED' => ['OUTPUT', 'PUSHPULL', 'SPEED_VERYLOW', 'FLOATING', 'LEVEL_LOW'], +# 'PASSIVE' => ['INPUT', 'PUSHPULL', 'SPEED_VERYLOW', 'FLOATING', 'LEVEL_LOW']); +# +# SYSTEM +A13 SWDIO SYS AF:SYS_JTMS-SWDIO +A14 SWCLK SYS AF:SYS_JTCK-SWCLK +C14 OSC32_IN SYS AF0 +C15 OSC32_OUT SYS AF0 +H00 OSC_IN SYS AF0 +H01 OSC_OUT SYS AF0 + +#DEFAULT +DEFAULT INPUT PUSHPULL SPEED_VERYLOW PULLDOWN LEVEL_LOW AF0 + + + +# ACTIVE PINS + + + +PA00 AUX_A1 PASSIVE #AF:USART2_CTS +PA01 AUX_A2 PASSIVE #AF:USART2_RTS +PA02 AUX_A3 PASSIVE #AF:TIM9_CH1 +PA03 AUX_B1 PASSIVE #AF:TIM9_CH2 +PA06 AUX_A4 PASSIVE #AF:TIM13_CH1 +PA07 AUX_B2 PASSIVE #AF:TIM14_CH1 +PA09 USB_VBUS INPUT PULLDOWN +PA10 LED2 LED +PA11 OTG_FS_DM OTG AF:USB_OTG_FS_DM +PA12 OTG_FS_DP OTG AF:USB_OTG_FS_DP +PA15 UART7_TX UART AF:UART7_TX + +PB00 AUX_B3 PASSIVE +PB01 AUX_B4 PASSIVE +PB03 UART7_RX UART AF:UART7_RX +PB05 DSHOT_RX UART AF:UART5_RX +PB06 SRVB1 PWM AF:TIM4_CH1 +PB07 SRVB2 PWM AF:TIM4_CH2 +PB08 SRVB3 PWM AF:TIM4_CH3 +PB09 SRVB4 PWM AF:TIM4_CH4 +PB10 I2C2_SCL_EXTERNAL I2C AF:I2C2_SCL +PB11 I2C2_SDA_EXTERNAL I2C AF:I2C2_SDA +PB12 SPI2_CS_EXTERNAL OUTPUT PUSHPULL SPEED_HIGH FLOATING LEVEL_HIGH +PB14 SPI2_EXTERNAL_MISO SPI AF:SPI2_MISO +PB15 SPI2_EXTERNAL_MOSI SPI AF:SPI2_MOSI + +PC00 VBAT_MEAS ADC ADC1_IN10 +PC06 RC2 PASSIVE #TLMF_TX6 UART AF:USART6_TX +PC07 LED3 LED +PC08 SDMMC1_D0 SDIO AF:SDMMC1_D0 +PC09 SDMMC1_D1 SDIO AF:SDMMC1_D1 +PC10 SDMMC1_D2 SDIO AF:SDMMC1_D2 +PC11 SDMMC1_D3 SDIO AF:SDMMC1_D3 +PC12 SDMMC1_CK SDIO AF:SDMMC1_CK +PC13 APSW OUTPUT PUSHPULL SPEED_VERYLOW FLOATING LEVEL_HIGH + + +PD00 CAN_RX CAN AF:CAN1_RX +PD01 CAN_TX CAN AF:CAN1_TX +PD02 SDMMC1_CMD SDIO AF:SDMMC1_CMD +PD03 SPI2_EXTERNAL_CLK SPI AF:SPI2_SCK +PD05 UART_TX2 UART AF:USART2_TX +PD06 UART_RX2 UART AF:USART2_RX +PD08 UART_TX3 UART AF:USART3_TX +PD09 UART_RX3 UART AF:USART3_RX +PD10 LED4 LED +PD12 I2C4_SCL_EXTERNAL I2C AF:I2C4_SCL +PD13 I2C4_SDA_EXTERNAL I2C AF:I2C4_SDA +PD15 LED1 LED + +PE00 RC1 UART AF:UART8_RX +PE02 SPI4_INTERNAL_CLK SPI AF:SPI4_SCK +PE04 SPI4_CS_INTERNAL OUTPUT PUSHPULL SPEED_HIGH FLOATING LEVEL_HIGH +PE05 SPI4_INTERNAL_MISO SPI AF:SPI4_MISO +PE06 SPI4_INTERNAL_MOSI SPI AF:SPI4_MOSI +PE09 SRVA1 PWM AF:TIM1_CH1 +PE11 SRVA2 PWM AF:TIM1_CH2 +PE13 SRVA3 PWM AF:TIM1_CH3 +PE14 SRVA4 PWM AF:TIM1_CH4 + + + diff --git a/sw/airborne/boards/tawaki/chibios/v1.0/tawaki.h b/sw/airborne/boards/tawaki/chibios/v1.0/tawaki.h new file mode 100644 index 00000000000..8d53b68964d --- /dev/null +++ b/sw/airborne/boards/tawaki/chibios/v1.0/tawaki.h @@ -0,0 +1,609 @@ +#ifndef CONFIG_TAWAKI_1_00_H +#define CONFIG_TAWAKI_1_00_H + +#define BOARD_TAWAKI + +/** + * ChibiOS board file + */ +#include "boards/tawaki/chibios/v1.0/board.h" + +/** + * PPRZ definitions + */ + +/* + * AHB_CLK + */ +#define AHB_CLK STM32_HCLK + + +/* + * LEDs + */ +/* red, on PD15, 1 on LED_ON, 0 on LED_OFF */ +#ifndef USE_LED_1 +#define USE_LED_1 1 +#endif +#define LED_1_GPIO GPIOD +#define LED_1_GPIO_PIN GPIO15 +#define LED_1_GPIO_ON gpio_set +#define LED_1_GPIO_OFF gpio_clear + +/* orange, on PA10, 1 on LED_ON, 0 on LED_OFF */ +#ifndef USE_LED_2 +#define USE_LED_2 1 +#endif +#define LED_2_GPIO GPIOA +#define LED_2_GPIO_PIN GPIO10 +#define LED_2_GPIO_ON gpio_set +#define LED_2_GPIO_OFF gpio_clear + +/* green, on PC7, 1 on LED_ON, 0 on LED_OFF */ +#ifndef USE_LED_3 +#define USE_LED_3 1 +#endif +#define LED_3_GPIO GPIOC +#define LED_3_GPIO_PIN GPIO7 +#define LED_3_GPIO_ON gpio_set +#define LED_3_GPIO_OFF gpio_clear + +/* yellow, on PD10, 1 on LED_ON, 0 on LED_OFF */ +#ifndef USE_LED_4 +#define USE_LED_4 1 +#endif +#define LED_4_GPIO GPIOD +#define LED_4_GPIO_PIN GPIO10 +#define LED_4_GPIO_ON gpio_set +#define LED_4_GPIO_OFF gpio_clear + +/* + * ADCs + */ +// AUXa1 +#if USE_ADC_1 +#define AD1_1_CHANNEL ADC_CHANNEL_IN0 +#define ADC_1 AD1_1 +#define ADC_1_GPIO_PORT GPIOA +#define ADC_1_GPIO_PIN GPIO0 +#endif + +// AUXa2 +#if USE_ADC_2 +#define AD1_2_CHANNEL ADC_CHANNEL_IN1 +#define ADC_2 AD1_2 +#define ADC_2_GPIO_PORT GPIOA +#define ADC_2_GPIO_PIN GPIO1 +#endif + +// AUXa3 +#if USE_ADC_3 +#define AD1_3_CHANNEL ADC_CHANNEL_IN2 +#define ADC_3 AD1_3 +#define ADC_3_GPIO_PORT GPIOA +#define ADC_3_GPIO_PIN GPIO2 +#endif + +// AUXa4 +#if USE_ADC_4 +#define AD1_4_CHANNEL ADC_CHANNEL_IN6 +#define ADC_4 AD1_4 +#define ADC_4_GPIO_PORT GPIOA +#define ADC_4_GPIO_PIN GPIO6 +#endif + +// AUXb1 +#if USE_ADC_5 +#define AD1_5_CHANNEL ADC_CHANNEL_IN3 +#define ADC_5 AD1_5 +#define ADC_5_GPIO_PORT GPIOA +#define ADC_5_GPIO_PIN GPIO3 +#endif + +// AUXb2 +#if USE_ADC_6 +#define AD1_6_CHANNEL ADC_CHANNEL_IN7 +#define ADC_6 AD1_6 +#define ADC_6_GPIO_PORT GPIOA +#define ADC_6_GPIO_PIN GPIO7 +#endif + +// AUXb3 +#if USE_ADC_7 +#define AD1_7_CHANNEL ADC_CHANNEL_IN8 +#define ADC_7 AD1_7 +#define ADC_7_GPIO_PORT GPIOB +#define ADC_7_GPIO_PIN GPIO0 +#endif + +// AUXb4 +#if USE_ADC_8 +#define AD1_8_CHANNEL ADC_CHANNEL_IN9 +#define ADC_8 AD1_8 +#define ADC_8_GPIO_PORT GPIOB +#define ADC_8_GPIO_PIN GPIO1 +#endif + +// Internal ADC for battery enabled by default +#ifndef USE_ADC_9 +#define USE_ADC_9 1 +#endif +#if USE_ADC_9 +#define AD1_9_CHANNEL ADC_CHANNEL_IN10 +#define ADC_9 AD1_9 +#define ADC_9_GPIO_PORT GPIOC +#define ADC_9_GPIO_PIN GPIO0 +#endif + +/* allow to define ADC_CHANNEL_VSUPPLY in the airframe file*/ +#ifndef ADC_CHANNEL_VSUPPLY +#define ADC_CHANNEL_VSUPPLY ADC_9 +#endif + +/* + * R1 = 2.2k + * R2 = 12k + * adc * (3.3 / 2^12) * ((R1 + R2) / R1) + */ +#define VBAT_R1 2200.0f +#define VBAT_R2 12000.0f +#define DefaultVoltageOfAdc(adc) ((3.3f/4096.0f)*((VBAT_R1+VBAT_R2)/VBAT_R1)*adc) + +/* + * PWM defines + */ +#ifndef USE_PWM1 +#define USE_PWM1 1 +#endif +#if USE_PWM1 +#define PWM_SERVO_1 1 +#define PWM_SERVO_1_GPIO GPIOE +#define PWM_SERVO_1_PIN GPIO9 +#define PWM_SERVO_1_AF GPIO_AF1 +#define PWM_SERVO_1_DRIVER PWMD1 +#define PWM_SERVO_1_CHANNEL 0 +#define PWM_SERVO_1_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_1_ACTIVE PWM_OUTPUT_DISABLED +#endif + +#ifndef USE_PWM2 +#define USE_PWM2 1 +#endif +#if USE_PWM2 +#define PWM_SERVO_2 2 +#define PWM_SERVO_2_GPIO GPIOE +#define PWM_SERVO_2_PIN GPIO11 +#define PWM_SERVO_2_AF GPIO_AF1 +#define PWM_SERVO_2_DRIVER PWMD1 +#define PWM_SERVO_2_CHANNEL 1 +#define PWM_SERVO_2_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_2_ACTIVE PWM_OUTPUT_DISABLED +#endif + +#ifndef USE_PWM3 +#define USE_PWM3 1 +#endif +#if USE_PWM3 +#define PWM_SERVO_3 3 +#define PWM_SERVO_3_GPIO GPIOE +#define PWM_SERVO_3_PIN GPIO13 +#define PWM_SERVO_3_AF GPIO_AF1 +#define PWM_SERVO_3_DRIVER PWMD1 +#define PWM_SERVO_3_CHANNEL 2 +#define PWM_SERVO_3_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_3_ACTIVE PWM_OUTPUT_DISABLED +#endif + +#ifndef USE_PWM4 +#define USE_PWM4 1 +#endif +#if USE_PWM4 +#define PWM_SERVO_4 4 +#define PWM_SERVO_4_GPIO GPIOE +#define PWM_SERVO_4_PIN GPIO14 +#define PWM_SERVO_4_AF GPIO_AF1 +#define PWM_SERVO_4_DRIVER PWMD1 +#define PWM_SERVO_4_CHANNEL 3 +#define PWM_SERVO_4_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_4_ACTIVE PWM_OUTPUT_DISABLED +#endif + +#ifndef USE_PWM5 +#define USE_PWM5 1 +#endif +#if USE_PWM5 +#define PWM_SERVO_5 5 +#define PWM_SERVO_5_GPIO GPIOB +#define PWM_SERVO_5_PIN GPIO6 +#define PWM_SERVO_5_AF GPIO_AF2 +#define PWM_SERVO_5_DRIVER PWMD4 +#define PWM_SERVO_5_CHANNEL 0 +#define PWM_SERVO_5_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_5_ACTIVE PWM_OUTPUT_DISABLED +#endif + +#ifndef USE_PWM6 +#define USE_PWM6 1 +#endif +#if USE_PWM6 +#define PWM_SERVO_6 6 +#define PWM_SERVO_6_GPIO GPIOB +#define PWM_SERVO_6_PIN GPIO7 +#define PWM_SERVO_6_AF GPIO_AF2 +#define PWM_SERVO_6_DRIVER PWMD4 +#define PWM_SERVO_6_CHANNEL 1 +#define PWM_SERVO_6_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_6_ACTIVE PWM_OUTPUT_DISABLED +#endif + +#ifndef USE_PWM6 +#define USE_PWM6 1 +#endif +#if USE_PWM7 +#define PWM_SERVO_7 7 +#define PWM_SERVO_7_GPIO GPIOB +#define PWM_SERVO_7_PIN GPIO8 +#define PWM_SERVO_7_AF GPIO_AF2 +#define PWM_SERVO_7_DRIVER PWMD4 +#define PWM_SERVO_7_CHANNEL 2 +#define PWM_SERVO_7_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_7_ACTIVE PWM_OUTPUT_DISABLED +#endif + +#ifndef USE_PWM8 +#define USE_PWM8 1 +#endif +#if USE_PWM8 +#define PWM_SERVO_8 8 +#define PWM_SERVO_8_GPIO GPIOB +#define PWM_SERVO_8_PIN GPIO9 +#define PWM_SERVO_8_AF GPIO_AF2 +#define PWM_SERVO_8_DRIVER PWMD4 +#define PWM_SERVO_8_CHANNEL 3 +#define PWM_SERVO_8_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_8_ACTIVE PWM_OUTPUT_DISABLED +#endif + +// TODO PWM on AUX pins + +// servo index starting at 1, so NB = 8+1 +#define ACTUATORS_PWM_NB 9 + + +#ifdef STM32_PWM_USE_TIM1 +#define PWM_CONF_TIM1 STM32_PWM_USE_TIM1 +#else +#define PWM_CONF_TIM1 1 +#endif +#define PWM_CONF1_DEF { \ + PWM_FREQUENCY, \ + PWM_FREQUENCY/TIM1_SERVO_HZ, \ + NULL, \ + { \ + { PWM_SERVO_1_ACTIVE, NULL }, \ + { PWM_SERVO_2_ACTIVE, NULL }, \ + { PWM_SERVO_3_ACTIVE, NULL }, \ + { PWM_SERVO_4_ACTIVE, NULL }, \ + }, \ + 0, \ + 0 \ +} + +#ifdef STM32_PWM_USE_TIM4 +#define PWM_CONF_TIM4 STM32_PWM_USE_TIM4 +#else +#define PWM_CONF_TIM4 1 +#endif +#define PWM_CONF4_DEF { \ + PWM_FREQUENCY, \ + PWM_FREQUENCY/TIM4_SERVO_HZ, \ + NULL, \ + { \ + { PWM_SERVO_5_ACTIVE, NULL }, \ + { PWM_SERVO_6_ACTIVE, NULL }, \ + { PWM_SERVO_7_ACTIVE, NULL }, \ + { PWM_SERVO_8_ACTIVE, NULL }, \ + }, \ + 0, \ + 0 \ +} + +/** + * DSHOT + */ +#define DSHOT_SERVO_1 0 +#define DSHOT_SERVO_1_GPIO GPIOE +#define DSHOT_SERVO_1_PIN GPIO9 +#define DSHOT_SERVO_1_AF GPIO_AF1 +#define DSHOT_SERVO_1_DRIVER DSHOTD1 +#define DSHOT_SERVO_1_CHANNEL 0 + +#define DSHOT_SERVO_2 1 +#define DSHOT_SERVO_2_GPIO GPIOE +#define DSHOT_SERVO_2_PIN GPIO11 +#define DSHOT_SERVO_2_AF GPIO_AF1 +#define DSHOT_SERVO_2_DRIVER DSHOTD1 +#define DSHOT_SERVO_2_CHANNEL 1 + +#define DSHOT_SERVO_3 2 +#define DSHOT_SERVO_3_GPIO GPIOE +#define DSHOT_SERVO_3_PIN GPIO13 +#define DSHOT_SERVO_3_AF GPIO_AF1 +#define DSHOT_SERVO_3_DRIVER DSHOTD1 +#define DSHOT_SERVO_3_CHANNEL 2 + +#define DSHOT_SERVO_4 3 +#define DSHOT_SERVO_4_GPIO GPIOE +#define DSHOT_SERVO_4_PIN GPIO14 +#define DSHOT_SERVO_4_AF GPIO_AF1 +#define DSHOT_SERVO_4_DRIVER DSHOTD1 +#define DSHOT_SERVO_4_CHANNEL 3 + +#ifndef DSHOT_TELEMETRY_DEV +#define DSHOT_TELEMETRY_DEV NULL +#endif + +#define DSHOT_CONF_TIM1 1 +#define DSHOT_CONF1_DEF { \ + .dma_stream = STM32_PWM1_UP_DMA_STREAM, \ + .dma_channel = STM32_PWM1_UP_DMA_CHANNEL, \ + .pwmp = &PWMD1, \ + .tlm_sd = DSHOT_TELEMETRY_DEV \ +} + +/** + * UART2 (Modem with optional flow control on AUXa disabled by default) + */ +#define UART2_GPIO_PORT_TX GPIOD +#define UART2_GPIO_TX GPIO5 +#define UART2_GPIO_PORT_RX GPIOD +#define UART2_GPIO_RX GPIO6 +#define UART2_GPIO_AF 7 +#ifndef UART2_HW_FLOW_CONTROL +#define UART2_HW_FLOW_CONTROL FALSE +#endif + +/** + * UART7 (GPS) and UART3 (Companion) + * are configured as UART from ChibiOS board file by default + */ + +#define UART3_GPIO_PORT_TX GPIOD +#define UART3_GPIO_TX GPIO8 +#define UART3_GPIO_PORT_RX GPIOD +#define UART3_GPIO_RX GPIO9 +#define UART3_GPIO_AF 7 + +#define UART7_GPIO_PORT_TX GPIOA +#define UART7_GPIO_TX GPIO15 +#define UART7_GPIO_PORT_RX GPIOB +#define UART7_GPIO_RX GPIO3 +#define UART7_GPIO_AF 12 + +/** + * UART4 on AUXa (not configured by default) + */ + +#define UART4_GPIO_PORT_TX GPIOA +#define UART4_GPIO_TX GPIO0 +#define UART4_GPIO_PORT_RX GPIOA +#define UART4_GPIO_RX GPIO1 +#define UART4_GPIO_AF 8 + +/** + * SBUS / Spektrum port + * + * Recommended config: + * + * primary SBUS port is UART8, a.k.a. RC1 on Tawaki board + * secondary port (in dual driver) is UART6, a.k.a. RC2 on Tawaki board + * + * primary Spektrum port is UART6, a.k.a. RC2 on Tawaki board + * secondary port is UART8, a.k.a. RC1 on Tawaki board + */ + +// In case, do dynamic config of UARTs +#define USE_UART8_RX TRUE +#ifndef USE_UART8_TX // may be used in half duplex mode +#define USE_UART8_TX FALSE +#endif +#define UART8_GPIO_PORT_RX GPIOE +#define UART8_GPIO_RX GPIO0 +#define UART8_GPIO_AF 8 + +// FIXME when RC2 is used for FrSky telemetry +#define USE_UART6_RX TRUE +#define USE_UART6_TX FALSE +#define UART6_GPIO_PORT_RX GPIOC +#define UART6_GPIO_RX GPIO6 +#define UART6_GPIO_AF 8 + +/* The line that is pulled low at power up to initiate the bind process + * PB1: AUXb4 + */ +#define SPEKTRUM_BIND_PIN GPIO1 +#define SPEKTRUM_BIND_PIN_PORT GPIOB + +// no wait with chibios as the RTC oscillator takes longer to stabilize +#define SPEKTRUM_BIND_WAIT 30000 + +/** + * PPM radio defines + * + * available on RC2 + */ +#define RC_PPM_TICKS_PER_USEC 6 +#define PPM_TIMER_FREQUENCY 6000000 +#define PPM_CHANNEL ICU_CHANNEL_1 +#define PPM_TIMER ICUD8 + +/* + * PWM input + */ +// PWM_INPUT 1 on PA0 (AUXa1) +#define PWM_INPUT1_ICU ICUD2 +#define PWM_INPUT1_CHANNEL ICU_CHANNEL_1 +#define PWM_INPUT1_GPIO_PORT GPIOA +#define PWM_INPUT1_GPIO_PIN GPIO0 +#define PWM_INPUT1_GPIO_AF GPIO_AF1 + +// PWM_INPUT 2 on PA1 (AUXa2) +#define PWM_INPUT2_ICU ICUD5 +#define PWM_INPUT2_CHANNEL ICU_CHANNEL_2 +#define PWM_INPUT2_GPIO_PORT GPIOA +#define PWM_INPUT2_GPIO_PIN GPIO1 +#define PWM_INPUT2_GPIO_AF GPIO_AF2 + +/** + * I2C defines + */ +// Digital noise filter: 0 disabled, [0x1 - 0xF] enable up to n t_I2CCLK +#define STM32_CR1_DNF(n) ((n & 0x0f) << 8) +// Timing register +#define I2C_FAST_400KHZ_DNF0_100NS_PCLK54MHZ_TIMINGR (STM32_TIMINGR_PRESC(0U) | \ + STM32_TIMINGR_SCLDEL(10U) | STM32_TIMINGR_SDADEL(0U) | \ + STM32_TIMINGR_SCLH(34U) | STM32_TIMINGR_SCLL(86U)) +#define I2C_STD_100KHZ_DNF0_100NS_PCLK54MHZ_TIMINGR (STM32_TIMINGR_PRESC(1U) | \ + STM32_TIMINGR_SCLDEL(9U) | STM32_TIMINGR_SDADEL(0U) | \ + STM32_TIMINGR_SCLH(105U) | STM32_TIMINGR_SCLL(153U)) + + +// Internal I2C (baro, magneto) + +#ifndef I2C4_CLOCK_SPEED +#define I2C4_CLOCK_SPEED 400000 +#endif + +#if I2C4_CLOCK_SPEED == 400000 +#define I2C4_CFG_DEF { \ + .timingr = I2C_FAST_400KHZ_DNF0_100NS_PCLK54MHZ_TIMINGR, \ + .cr1 = STM32_CR1_DNF(0), \ + .cr2 = 0 \ +} +#elif I2C4_CLOCK_SPEED == 100000 +#define I2C4_CFG_DEF { \ + .timingr = I2C_STD_100KHZ_DNF0_100NS_PCLK54MHZ_TIMINGR, \ + .cr1 = STM32_CR1_DNF(0), \ + .cr2 = 0 \ +} +#else +#error "Unknown I2C4 clock speed" +#endif + +// External I2C + +#ifndef I2C2_CLOCK_SPEED +#define I2C2_CLOCK_SPEED 400000 +#endif + +#if I2C2_CLOCK_SPEED == 400000 +#define I2C2_CFG_DEF { \ + .timingr = I2C_FAST_400KHZ_DNF0_100NS_PCLK54MHZ_TIMINGR, \ + .cr1 = STM32_CR1_DNF(0), \ + .cr2 = 0 \ +} +#elif I2C2_CLOCK_SPEED == 100000 +#define I2C2_CFG_DEF { \ + .timingr = I2C_STD_100KHZ_DNF0_100NS_PCLK54MHZ_TIMINGR, \ + .cr1 = STM32_CR1_DNF(0), \ + .cr2 = 0 \ +} +#else +#error "Unknown I2C2 clock speed" +#endif + +/** + * SPI Config + */ + +// Internal SPI (IMU) +#define SPI4_GPIO_AF GPIO_AF5 +#define SPI4_GPIO_PORT_MISO GPIOE +#define SPI4_GPIO_MISO GPIO5 +#define SPI4_GPIO_PORT_MOSI GPIOE +#define SPI4_GPIO_MOSI GPIO6 +#define SPI4_GPIO_PORT_SCK GPIOE +#define SPI4_GPIO_SCK GPIO2 + +// External SPI +#define SPI2_GPIO_AF GPIO_AF5 +#define SPI2_GPIO_PORT_MISO GPIOB +#define SPI2_GPIO_MISO GPIO14 +#define SPI2_GPIO_PORT_MOSI GPIOB +#define SPI2_GPIO_MOSI GPIO15 +#define SPI2_GPIO_PORT_SCK GPIOD +#define SPI2_GPIO_SCK GPIO3 + +// SLAVE0 on SPI connector (NSS possible) +#define SPI_SELECT_SLAVE0_PORT GPIOB +#define SPI_SELECT_SLAVE0_PIN GPIO12 +// SLAVE1 on AUXb1 +#define SPI_SELECT_SLAVE1_PORT GPIOA +#define SPI_SELECT_SLAVE1_PIN GPIO3 +// SLAVE2 on AUXb2 +#define SPI_SELECT_SLAVE2_PORT GPIOA +#define SPI_SELECT_SLAVE2_PIN GPIO7 +// SLAVE3 on AUXb3 +#define SPI_SELECT_SLAVE3_PORT GPIOB +#define SPI_SELECT_SLAVE3_PIN GPIO0 +// SLAVE4 on AUXb4 +#define SPI_SELECT_SLAVE4_PORT GPIOB +#define SPI_SELECT_SLAVE4_PIN GPIO1 +// SLAVE5 on PE4 (internal IMU) +#define SPI_SELECT_SLAVE5_PORT GPIOE +#define SPI_SELECT_SLAVE5_PIN GPIO4 + +/** + * Baro + * + * Apparently needed for backwards compatibility + * with the ancient onboard baro boards + */ +#ifndef USE_BARO_BOARD +#define USE_BARO_BOARD 0 +#endif + +/** + * SDIO + */ +#define SDIO_D0_PORT GPIOC +#define SDIO_D0_PIN GPIO8 +#define SDIO_D1_PORT GPIOC +#define SDIO_D1_PIN GPIO9 +#define SDIO_D2_PORT GPIOC +#define SDIO_D2_PIN GPIO10 +#define SDIO_D3_PORT GPIOC +#define SDIO_D3_PIN GPIO11 +#define SDIO_CK_PORT GPIOC +#define SDIO_CK_PIN GPIO12 +#define SDIO_CMD_PORT GPIOD +#define SDIO_CMD_PIN GPIO2 +#define SDIO_AF 12 +// bat monitoring for file closing +#define SDLOG_BAT_ADC ADCD1 +#define SDLOG_BAT_CHAN ADC_CHANNEL_IN10 +// usb led status +#define SDLOG_USB_LED 4 +#define SDLOG_USB_VBUS_PORT GPIOA +#define SDLOG_USB_VBUS_PIN GPIO9 + + +/* + * Actuators for fixedwing + */ + /* Default actuators driver */ +#define DEFAULT_ACTUATORS "subsystems/actuators/actuators_pwm.h" +#define ActuatorDefaultSet(_x,_y) ActuatorPwmSet(_x,_y) +#define ActuatorsDefaultInit() ActuatorsPwmInit() +#define ActuatorsDefaultCommit() ActuatorsPwmCommit() + +#endif /* CONFIG_TAWAKI_1_00_H */ + From c93a84e76819d39a1dbb41d4ec157255f32d1caf Mon Sep 17 00:00:00 2001 From: Gautier Hattenberger Date: Fri, 14 Jun 2019 10:36:07 +0200 Subject: [PATCH 5/6] [chibios] fix LED_ON/OFF to take board conf into account --- sw/airborne/arch/chibios/led_hw.h | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/sw/airborne/arch/chibios/led_hw.h b/sw/airborne/arch/chibios/led_hw.h index dde17006c12..ba353fa3a62 100644 --- a/sw/airborne/arch/chibios/led_hw.h +++ b/sw/airborne/arch/chibios/led_hw.h @@ -34,23 +34,24 @@ * hal.h is needed for palXXX functions */ #include -#include "mcu_periph/gpio_def.h" +#include "mcu_periph/gpio.h" #include BOARD_CONFIG /* * Regular GPIO driven LEDs */ -#define _LED_GPIO(i) i -#define _LED_GPIO_PIN(i) i +#define _LED_EVAL(i) i -#define LED_GPIO(i) _LED_GPIO(LED_ ## i ## _GPIO) -#define LED_GPIO_PIN(i) _LED_GPIO_PIN(LED_ ## i ## _GPIO_PIN) +#define LED_GPIO(i) _LED_EVAL(LED_ ## i ## _GPIO) +#define LED_GPIO_PIN(i) _LED_EVAL(LED_ ## i ## _GPIO_PIN) +#define LED_GPIO_ON(i) _LED_EVAL(LED_ ## i ## _GPIO_ON) +#define LED_GPIO_OFF(i) _LED_EVAL(LED_ ## i ## _GPIO_OFF) -#define LED_INIT(i) palSetPadMode(LED_GPIO(i), LED_GPIO_PIN(i), PAL_MODE_OUTPUT_PUSHPULL) -#define LED_ON(i) palClearPad(LED_GPIO(i), LED_GPIO_PIN(i)) -#define LED_OFF(i) palSetPad(LED_GPIO(i), LED_GPIO_PIN(i)) -#define LED_TOGGLE(i) palTogglePad(LED_GPIO(i), LED_GPIO_PIN(i)) -#define LED_DISABLE(i) palSetPadMode(LED_GPIO(i), LED_GPIO_PIN(i), PAL_MODE_INPUT) +#define LED_INIT(i) gpio_setup_output(LED_GPIO(i), LED_GPIO_PIN(i)) +#define LED_ON(i) LED_GPIO_ON(i)(LED_GPIO(i), LED_GPIO_PIN(i)) +#define LED_OFF(i) LED_GPIO_OFF(i)(LED_GPIO(i), LED_GPIO_PIN(i)) +#define LED_TOGGLE(i) gpio_toggle(LED_GPIO(i), LED_GPIO_PIN(i)) +#define LED_DISABLE(i) gpio_setup_input(LED_GPIO(i), LED_GPIO_PIN(i)) #define LED_PERIODIC() {} #endif /* LED_HW_H */ From 5ed41ced723b6dc524ad4917fcb36d4eff635d97 Mon Sep 17 00:00:00 2001 From: Gautier Hattenberger Date: Fri, 14 Jun 2019 11:31:13 +0200 Subject: [PATCH 6/6] [test] compile gpio_arch for chibios test progs --- conf/firmwares/test_chibios.makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/conf/firmwares/test_chibios.makefile b/conf/firmwares/test_chibios.makefile index ffc023bc961..1efa3f04727 100644 --- a/conf/firmwares/test_chibios.makefile +++ b/conf/firmwares/test_chibios.makefile @@ -64,6 +64,7 @@ COMMON_TEST_CFLAGS += -DPERIODIC_FREQUENCY=$(PERIODIC_FREQUENCY) COMMON_TEST_SRCS += mcu_periph/sys_time.c $(SRC_ARCH)/mcu_periph/sys_time_arch.c COMMON_TEST_CFLAGS += -DUSE_LED +COMMON_TEST_SRCS += $(SRC_ARCH)/mcu_periph/gpio_arch.c # pprz downlink/datalink COMMON_TELEMETRY_CFLAGS = -DDOWNLINK -DDOWNLINK_TRANSPORT=pprz_tp -DDATALINK=PPRZ