Shatur
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written in Verilog
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Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
Hardware implementation of the SHA-256 cryptographic hash function
Free collection of hardware modules written in Verilog for FPGAs and embedded systems.
A Standalone Structural Verilog Parser
Re-coded Xilinx primitives for Verilator use