From c8e0cf4d2493974d87d944b899491bcb262d1efb Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 30 Jan 2024 09:37:05 +0100 Subject: [PATCH 1/4] Add latch register file fakeRatio parameter as a ASIC RF workaround --- src/main/scala/naxriscv/misc/RegFilePlugin.scala | 15 ++++++++++----- .../scala/naxriscv/platform/asic/NaxAsicGen.scala | 3 +++ .../scala/naxriscv/platform/asic/test_rf.scala | 3 ++- 3 files changed, 15 insertions(+), 6 deletions(-) diff --git a/src/main/scala/naxriscv/misc/RegFilePlugin.scala b/src/main/scala/naxriscv/misc/RegFilePlugin.scala index abdf3a9..d5fa304 100644 --- a/src/main/scala/naxriscv/misc/RegFilePlugin.scala +++ b/src/main/scala/naxriscv/misc/RegFilePlugin.scala @@ -139,7 +139,9 @@ class RegFileLatch(addressWidth : Int, dataWidth : Int, readsParameter : Seq[RegFileReadParameter], writesParameter : Seq[RegFileWriteParameter], - headZero : Boolean) extends Component { + headZero : Boolean, + fakeRatio : Int) extends Component { + assert(isPow2(fakeRatio)) val io = RegFileIo(addressWidth, dataWidth, readsParameter, writesParameter) io.reads.foreach(e => assert(!e.withReady)) @@ -152,7 +154,7 @@ class RegFileLatch(addressWidth : Int, // val buffers = for (port <- io.writes) yield RegNext(port.data) } - val latches = for (i <- headZero.toInt until 1 << addressWidth) yield new Area { + val latches = for (i <- headZero.toInt until (1 << addressWidth)/fakeRatio) yield new Area { val write = new Area { val mask = B(io.writes.map(port => port.valid && port.address === i)) val maskReg = LatchWhen(mask, writeFrontend.clock) @@ -182,7 +184,7 @@ class RegFileLatch(addressWidth : Int, // Tristate based mux implementation val oh = UIntToOh(r.address) val tri = Analog(Bits(dataWidth bits)) - mem.onMask(oh){ value => + mem.onMask(oh.resize(mem.size)){ value => tri := value } r.data := tri @@ -192,13 +194,15 @@ class RegFileLatch(addressWidth : Int, } } +//fakeRatio > 1 allows the latchregister file to be n time smaller by faking registers class RegFilePlugin(var spec : RegfileSpec, var physicalDepth : Int, var bankCount : Int, var preferedWritePortForInit : String, var asyncReadBySyncReadRevertedClk : Boolean = false, var allOne : Boolean = false, - var latchBased : Boolean = false) extends Plugin with RegfileService with InitCycles { + var latchBased : Boolean = false, + var fakeRatio : Int = 1) extends Plugin with RegfileService with InitCycles { withPrefix(spec.getName()) override def getPhysicalDepth = physicalDepth @@ -301,7 +305,8 @@ class RegFilePlugin(var spec : RegfileSpec, dataWidth = dataWidth, readsParameter = reads.map(e => RegFileReadParameter(withReady = e.withReady, e.forceNoBypass)), writesParameter = writeMerges.map(e => RegFileWriteParameter(withReady = false)).toList, - headZero = spec.x0AlwaysZero + headZero = spec.x0AlwaysZero, + fakeRatio = fakeRatio ) diff --git a/src/main/scala/naxriscv/platform/asic/NaxAsicGen.scala b/src/main/scala/naxriscv/platform/asic/NaxAsicGen.scala index 35f0802..d36a7d6 100644 --- a/src/main/scala/naxriscv/platform/asic/NaxAsicGen.scala +++ b/src/main/scala/naxriscv/platform/asic/NaxAsicGen.scala @@ -13,10 +13,12 @@ import spinal.lib.eda.bench.Rtl object NaxAsicGen extends App{ var target = "asic" + var regFileFakeRatio = 1 assert(new scopt.OptionParser[Unit]("NaxAsicGen") { help("help").text("prints this usage text") opt[Unit]("sky130") action { (v, c) => target = "sky130" } + opt[Int]("regfile-fake-ratio") action { (v, c) => regFileFakeRatio = v } }.parse(args, Unit).nonEmpty) @@ -43,6 +45,7 @@ object NaxAsicGen extends App{ dispatchSlots = 8, robSize = 16, branchCount = 4, + regFileFakeRatio = regFileFakeRatio, // withCoherency = true, ioRange = a => a(31 downto 28) === 0x1// || !a(12)//(a(5, 6 bits) ^ a(12, 6 bits)) === 51 ) diff --git a/src/main/scala/naxriscv/platform/asic/test_rf.scala b/src/main/scala/naxriscv/platform/asic/test_rf.scala index 3ec34e0..4b84c62 100644 --- a/src/main/scala/naxriscv/platform/asic/test_rf.scala +++ b/src/main/scala/naxriscv/platform/asic/test_rf.scala @@ -19,7 +19,8 @@ object TestRfGen extends App { dataWidth = 2, readsParameter = List.fill(1)(RegFileReadParameter(false, false)), writesParameter = List.fill(1)(RegFileWriteParameter(false)), - headZero = false + headZero = false, + fakeRatio = 1 ).setDefinitionName("rf") } } From 87642e686c23989d53691c11efb67bbdc76eb858 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 30 Jan 2024 09:37:16 +0100 Subject: [PATCH 2/4] Add missing change --- src/main/scala/naxriscv/Gen.scala | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/main/scala/naxriscv/Gen.scala b/src/main/scala/naxriscv/Gen.scala index 031ce67..fe539e8 100644 --- a/src/main/scala/naxriscv/Gen.scala +++ b/src/main/scala/naxriscv/Gen.scala @@ -69,7 +69,8 @@ object Config{ robSize : Int = 64, withCoherency : Boolean = false, hartId : Int = 0, - asic : Boolean = false): ArrayBuffer[Plugin] ={ + asic : Boolean = false, + regFileFakeRatio : Int = 1): ArrayBuffer[Plugin] ={ val plugins = ArrayBuffer[Plugin]() val fpu = withFloat || withDouble @@ -297,7 +298,8 @@ object Config{ physicalDepth = 64, bankCount = 1, preferedWritePortForInit = "ALU0", - latchBased = asic + latchBased = asic, + fakeRatio = regFileFakeRatio ) plugins += new CommitDebugFilterPlugin(List(4, 8, 12)) plugins += new CsrRamPlugin() From 93356b4fafa1971b917b120ebdf6ddf713f3e800 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 30 Jan 2024 09:37:35 +0100 Subject: [PATCH 3/4] Fix datacache without coherency --- src/main/scala/naxriscv/lsu/DataCache.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/main/scala/naxriscv/lsu/DataCache.scala b/src/main/scala/naxriscv/lsu/DataCache.scala index 178c42f..04186d5 100644 --- a/src/main/scala/naxriscv/lsu/DataCache.scala +++ b/src/main/scala/naxriscv/lsu/DataCache.scala @@ -132,7 +132,7 @@ case class DataMemBusParameter( addressWidth: Int, M2sAgent( name = name, M2sSource( - id = SizeMapping(log2Up(readIdCount max writeIdCount), readIdCount), + id = SizeMapping(1 << log2Up(readIdCount max writeIdCount), readIdCount), emits = tilelink.M2sTransfers( get = SizeRange(lineSize) ) @@ -517,6 +517,7 @@ case class DataMemBus(p : DataMemBusParameter) extends Bundle with IMasterSlave val beat = bus.a.beatCounter() bus.a.address(log2Up(p.dataWidth/8), widthOf(beat) bits) := beat + bus.a.source.allowOverride() bus.a.source.msb := sel write.cmd.ready := !sel && bus.a.ready From 54cf78af83f3f04aa1af032bd3215b4bf36954e5 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 30 Jan 2024 10:00:10 +0100 Subject: [PATCH 4/4] add --no-lsu arguement --- src/main/scala/naxriscv/platform/asic/NaxAsicGen.scala | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/main/scala/naxriscv/platform/asic/NaxAsicGen.scala b/src/main/scala/naxriscv/platform/asic/NaxAsicGen.scala index d36a7d6..3cc539f 100644 --- a/src/main/scala/naxriscv/platform/asic/NaxAsicGen.scala +++ b/src/main/scala/naxriscv/platform/asic/NaxAsicGen.scala @@ -14,11 +14,13 @@ import spinal.lib.eda.bench.Rtl object NaxAsicGen extends App{ var target = "asic" var regFileFakeRatio = 1 + var withLsu = true assert(new scopt.OptionParser[Unit]("NaxAsicGen") { help("help").text("prints this usage text") opt[Unit]("sky130") action { (v, c) => target = "sky130" } opt[Int]("regfile-fake-ratio") action { (v, c) => regFileFakeRatio = v } + opt[Unit]("no-lsu") action { (v, c) => withLsu = false } }.parse(args, Unit).nonEmpty) @@ -32,7 +34,7 @@ object NaxAsicGen extends App{ debugTriggers = 4, withDedicatedLoadAgu = false, withRvc = false, - withLoadStore = false, + withLoadStore = withLsu, withMmu = false, withDebug = false, withEmbeddedJtagTap = false,