L1 & L2 cache memory architecture of Nax core

[SoCScholar]

Dear Charles,

I'd like to know how the Nax core's L1 & L2 cache memory architecture is organized, though L1 is an inclusive cache of the L2 cache. Is L2 a 16 KB, 4-way associative cache?

I also wonder how Writeback, PLRU line eviction, and MESI protocol will be implemented in multicore. MESI protocol does not define the L1 + L2 interplay transitions if we include an L2 cache.

https://spinalhdl.github.io/NaxRiscv-Rtd/main/NaxRiscv/memory/index.html#l2-cache

Thank you very much.

With best regards
Himal Subedi

[Dolu1990]

though L1 is an inclusive cache of the L2 cache. Is L2 a 16 KB, 4-way associative cache?

L2 is a inclusive cache, meaning it has a copy of every L1 data + some spare.

default L2 is currently 128 KB 4 ways

I also wonder how Writeback, PLRU line eviction, and MESI protocol will be implemented in multicore.

?

Each L1 cache line can have a few states :

• invalid
• shared clean
• unique clean
• unique dirty

What transactions do you mean ?

[SoCScholar]

What transactions do you mean ?

what happens if a dirty cacheline is evicted from the L1 cache. Will it be kept as dirty cacheline in the L2 cache or written back to memory? And what happens then if two cores do a LOAD to this cacheline.

[Dolu1990]

what happens if a dirty cacheline is evicted from the L1 cache. Will it be kept as dirty cacheline in the L2 cache or written back to memory?

It will be keept in the L2

And what happens then if two cores do a LOAD to this cacheline.

First CPU will get it in a unique "clean" state
Second CPU will then trigger the L2 to downgrade the first CPU permission to shared clean
Then second CPU get it in shared clean state

[SoCScholar]

Does this mean that only the L2 cache knows that the caheline is actually dirty?

[Dolu1990]

Yes, that's a specificty of tilelink

[SoCScholar]

Hi Charles, this again Question make me think deeply

when two cores L1 caches' dirty cache line written to L2. L2 keep each core Cache Line as dirty in L2.

in future if there is need for refill in L2 cache, will these data would be written back to Main memory as dirty from each core ?

From MESI coherency protocol till L2 cache, it is fine as L1 can do multiple write to L2. L2 can keep each core Cache Line dirty as dirty without posting to Main memory but if refill to L2 and Write back required from L2 cache to Main memory, How those dirty Cache Line will be updated in Main Memory from L2. I know it will cause dirty eviction but L2 cache but how it will keep inside main memory

[Dolu1990]

when two cores L1 caches' dirty cache line written to L2. L2 keep each core Cache Line as dirty in L2.

Yes

in future if there is need for refill in L2 cache, will these data would be written back to Main memory as dirty from each core ?

There is no other choices

How those dirty Cache Line will be updated in Main Memory from L2

I don't get it, it will just write things back to main memory. L2 -> main memory

[SoCScholar]

I don't get it, it will just write things back to main memory. L2 -> main memory

If each core dirty cache line in the L2 cache is written as dirty in the main memory, won't there be any conflict while writing to the main memory? I guess there should be some consistency in those two cache lines' data when it is written back to the main memory.

[Dolu1990]

won't there be any conflict while writing to the main memory

No because the l2 will never store multiple copy of the same memory clock.
To modify a memory block in l1, the l1 need to get it in a exclusive mode => no other copy anywere else.