From 22c2f4d5dcd171ec85d0abb8475688c7de81e5bc Mon Sep 17 00:00:00 2001 From: Bohan Hu Date: Mon, 3 Aug 2020 08:06:33 +0800 Subject: [PATCH] bad bpd --- .../ip/blk_mem_gen_0/blk_mem_gen_0.xci | 319 ++++++++++++++++++ source/sources_1/new/Commit.sv | 8 + source/sources_1/new/MyCPU.sv | 1 + source/sources_1/new/decode.sv | 1 + source/sources_1/new/defines/defines.svh | 33 +- source/sources_1/new/ifu/CtrlUnit.sv | 7 +- source/sources_1/new/ifu/IFU.sv | 26 +- source/sources_1/new/ifu/IF_3.sv | 32 +- source/sources_1/new/ifu/TAGE.sv | 21 +- source/sources_1/new/ifu/TAGE_Phase0.sv | 2 +- source/sources_1/new/ifu/TAGE_Phase1.sv | 46 +-- source/sources_1/new/ifu/TageBank.sv | 42 ++- source/sources_1/new/interface.sv | 9 +- 13 files changed, 483 insertions(+), 64 deletions(-) create mode 100644 source/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0.xci diff --git a/source/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0.xci b/source/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0.xci new file mode 100644 index 0000000..3dfdc6c --- /dev/null +++ b/source/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0.xci @@ -0,0 +1,319 @@ + + + xilinx.com + xci + unknown + 1.0 + + + blk_mem_gen_0 + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + 100000000 + 0 + 0.000 + 0 + 10 + 10 + 1 + 4 + 0 + 1 + 9 + 1 + 1 + 0 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 2.5696 mW + artix7 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + blk_mem_gen_0.mem + no_coe_file_loaded + 0 + 0 + 1 + 0 + 1 + 1024 + 1024 + 1 + 1 + 11 + 11 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1024 + 1024 + NO_CHANGE + READ_FIRST + 11 + 11 + artix7 + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + true + 9 + NONE + no_coe_file_loaded + ALL + blk_mem_gen_0 + false + false + false + false + false + false + false + false + false + Use_ENA_Pin + Use_ENB_Pin + Single_Bit_Error_Injection + true + Native + false + no_mem_loaded + Simple_Dual_Port_RAM + NO_CHANGE + READ_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 100 + 100 + 0 + 8kx2 + false + false + 1 + 1 + 11 + 11 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 1024 + 11 + 11 + No_ECC + false + false + false + Stand_Alone + artix7 + + + xc7a200t + fbg676 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2019.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/source/sources_1/new/Commit.sv b/source/sources_1/new/Commit.sv index f32d3d8..ea133b5 100644 --- a/source/sources_1/new/Commit.sv +++ b/source/sources_1/new/Commit.sv @@ -206,6 +206,14 @@ module Commit( end end + always_comb begin + backend_bpd.updValid <= inst0Good && rob_commit.uOP0.branchType != typeNormal && rob_commit.uOP0.branchType != typeJ; + backend_bpd.updTarget <= rob_commit.uOP0.pc; + backend_bpd.updInfo <= rob_commit.uOP0.predInfo; + backend_bpd.updMisPred <= rob_commit.uOP0.branchTaken != rob_commit.uOP0.predTaken; + backend_bpd.updTaken <= rob_commit.uOP0.branchTaken; + end + always_comb begin ctrl_commit.flushReq = `FALSE; backend_if0.redirect = `FALSE; diff --git a/source/sources_1/new/MyCPU.sv b/source/sources_1/new/MyCPU.sv index 5bfc549..6732532 100644 --- a/source/sources_1/new/MyCPU.sv +++ b/source/sources_1/new/MyCPU.sv @@ -94,6 +94,7 @@ module mycpu_top( Ctrl ctrl_if0_1_regs(); Ctrl ctrl_if2_3_regs(); Ctrl ctrl_iCache(); + Ctrl ctrl_tage(); Ctrl ctrl_if3(); Ctrl ctrl_if3_output_regs(); Ctrl ctrl_instBuffer(); diff --git a/source/sources_1/new/decode.sv b/source/sources_1/new/decode.sv index 45ea09c..362e8a1 100644 --- a/source/sources_1/new/decode.sv +++ b/source/sources_1/new/decode.sv @@ -48,6 +48,7 @@ module decode( uOP0.pc = inst.pc; uOP0.predTaken = inst.predTaken; uOP0.predAddr = inst.predAddr; + uOP0.predInfo = inst.bpdInfo; uOP0.isDS = inst.isDs; uOP0.committed = `FALSE; uOP1.pc = inst.pc; diff --git a/source/sources_1/new/defines/defines.svh b/source/sources_1/new/defines/defines.svh index e3eb641..c9a2908 100644 --- a/source/sources_1/new/defines/defines.svh +++ b/source/sources_1/new/defines/defines.svh @@ -265,6 +265,23 @@ typedef logic [5:0] ARFNum; // 逻辑寄存器编号(共34个) `define NOP_U 8'b01000010 `define WAIT_U 8'b01000101 +typedef logic [9:0] TAGEIndex; +typedef logic [2:0] TAGECtr; +typedef logic [7:0] TAGETag; +typedef logic [1:0] TAGEUseful; + +typedef struct packed { + logic hit; // 预测命中 + TAGEIndex hit_index; // 预测的index，以防历史记录改变 + TAGEIndex on_mispred_index; // 预测错误时，要分配的新项的index + logic [1:0] on_mispred_bank; // 预测错误时，需要分配哪个Bank + TAGETag hit_tag; // 命中的Tag + TAGETag on_mispred_tag; // 错误预测时，更新的新项的Tag + logic has_free_to_alloc; // 预测错误时，有新项可以分配 + TAGECtr ctr; // 三位饱和计数器 + logic [1:0] provider; // + logic has_alter; +} TAGEPred; typedef struct packed { logic [31:0] inst; @@ -544,23 +561,7 @@ typedef struct packed { // TODO } UOPBundle; -typedef logic [9:0] TAGEIndex; -typedef logic [2:0] TAGECtr; -typedef logic [7:0] TAGETag; -typedef logic [1:0] TAGEUseful; -typedef struct packed { - logic hit; // 预测命中 - TAGEIndex hit_index; // 预测的index，以防历史记录改变 - TAGEIndex on_mispred_index; // 预测错误时，要分配的新项的index - logic [1:0] on_mispred_bank; // 预测错误时，需要分配哪个Bank - TAGETag hit_tag; // 命中的Tag - TAGETag on_mispred_tag; // 错误预测时，更新的新项的Tag - logic has_free_to_alloc; // 预测错误时，有新项可以分配 - TAGECtr ctr; // 三位饱和计数器 - logic [1:0] provider; // - logic has_alter; -} TAGEPred; interface Ctrl; logic pauseReq; diff --git a/source/sources_1/new/ifu/CtrlUnit.sv b/source/sources_1/new/ifu/CtrlUnit.sv index 22fb7e7..8d43b21 100644 --- a/source/sources_1/new/ifu/CtrlUnit.sv +++ b/source/sources_1/new/ifu/CtrlUnit.sv @@ -10,7 +10,8 @@ module CtrlUnit( Ctrl.master ctrl_iCache, Ctrl.master ctrl_if3, Ctrl.master ctrl_if3_output_regs, - Ctrl.master ctrl_instBuffer + Ctrl.master ctrl_instBuffer, + Ctrl.master ctrl_tage ); logic delayIF3Flush, if3Flush; @@ -19,14 +20,16 @@ module CtrlUnit( assign if3Flush = delayIF3Flush || ctrl_if3.flushReq; - assign ctrl_if0_1_regs.pause = ctrl_instBuffer.pauseReq ||ctrl_iCache.pauseReq; + assign ctrl_if0_1_regs.pause = ctrl_instBuffer.pauseReq || ctrl_iCache.pauseReq; assign ctrl_if2_3_regs.pause = ctrl_instBuffer.pauseReq; assign ctrl_iCache.pause = ctrl_instBuffer.pauseReq; + assign ctrl_tage.pause = ctrl_instBuffer.pauseReq || ctrl_iCache.pauseReq; assign ctrl_if3.pause = ctrl_instBuffer.pauseReq; assign ctrl_if3_output_regs.pause = ctrl_instBuffer.pauseReq; assign ctrl_if0_1_regs.flush = `FALSE; //backend_ctrl.flush || ctrl_if3.flushReq; assign ctrl_iCache.flush = backend_ctrl.flush || ctrl_if3.flushReq; + assign ctrl_tage.flush = backend_ctrl.flush; assign ctrl_if2_3_regs.flush = backend_ctrl.flush || ctrl_if3.flushReq; assign ctrl_if3.flush = backend_ctrl.flush; assign ctrl_if3_output_regs.flush = backend_ctrl.flush; diff --git a/source/sources_1/new/ifu/IFU.sv b/source/sources_1/new/ifu/IFU.sv index 84b4523..0376f3b 100644 --- a/source/sources_1/new/ifu/IFU.sv +++ b/source/sources_1/new/ifu/IFU.sv @@ -14,7 +14,7 @@ module IFU( Ctrl ctrl_if3, Ctrl ctrl_if3_output_regs, Ctrl ctrl_nlp, - + Ctrl ctrl_tage, ICache_TLB iCache_tlb, BackendRedirect backend_if0, BPDUpdate backend_bpd, @@ -48,5 +48,29 @@ module IFU( IF2_3_reg if23reg(.*); IF_3 if3(.*); IF3_Output_reg if3OutputReg(.*); + logic IF3_isBranch, IF3_isJ; + wire [31:0] pred_target; + wire pred_valid, pred_taken; + TAGEPred pred_info; + TAGE u_TAGE( + .clk (clk ), + .rst (rst ), + .pause (ctrl_tage.pause ), + .recover (ctrl_tage.flush ), + .IF3_isBranch (IF3_isBranch ), + .IF3_isJ (IF3_isJ ), + .br_pc (regs_iCache.PC ), + // 送出的结果 + .pred_valid (pred_valid ), + .pred_taken (pred_taken ), + .pred_target (pred_target ), + .pred_info (pred_info ), + // 从commit阶段来的 + .commit_valid (backend_bpd.updValid ), + .committed_target (backend_bpd.updTarget ), + .committed_pred_info (backend_bpd.updInfo ), + .committed_branch_taken (backend_bpd.updTaken ), + .committed_mispred (backend_bpd.updMisPred ) + ); endmodule \ No newline at end of file diff --git a/source/sources_1/new/ifu/IF_3.sv b/source/sources_1/new/ifu/IF_3.sv index d9b9290..a3c9b63 100644 --- a/source/sources_1/new/ifu/IF_3.sv +++ b/source/sources_1/new/ifu/IF_3.sv @@ -16,7 +16,9 @@ module IF_3( input wire pred_valid, // from bpd input wire pred_taken, // from bpd input wire [31:0] pred_target, - input TAGEPred pred_info + input TAGEPred pred_info, + output IF3_isBranch, // To BPD, update the global history + output IF3_isJ ); logic inst0Jr; logic inst1Jr; @@ -36,7 +38,12 @@ module IF_3( logic waitDS, lastWaitDS; logic [31:0] waitDSRedirectTarget; - + wire isJ, isBranch; + assign isBranch = inst0Jr | inst0J | inst0Br | + inst1Jr | inst1J | inst1Br ; + assign isJ = inst0J | inst1J ; + assign IF3_isBranch = isBranch; + assign IF3_isJ = isJ; Predecoder pre0( .pc (regs_if3.inst0.pc ), .inst (regs_if3.inst0.inst ), @@ -101,6 +108,12 @@ module IF_3( if(pred_valid) begin if3_regs.inst0.predTaken = pred_taken; if3_regs.inst0.predAddr = decodeTarget0; + end else if(if3_regs.inst0.nlpInfo.valid) begin + if3_regs.inst0.predTaken = inst0NLPTaken; + if3_regs.inst0.predAddr = decodeTarget0; + end else begin + if3_regs.inst0.predTaken = `FALSE; + if3_regs.inst0.predAddr = decodeTarget0; end end @@ -123,6 +136,17 @@ module IF_3( if3_regs.inst1.predTaken = `TRUE; if3_regs.inst1.predAddr = decodeTarget1; end + end else begin + if(pred_valid) begin + if3_regs.inst1.predTaken = pred_taken; + if3_regs.inst1.predAddr = decodeTarget1; + end else if(if3_regs.inst1.nlpInfo.valid) begin + if3_regs.inst1.predTaken = inst1NLPTaken; + if3_regs.inst1.predAddr = decodeTarget1; + end else begin + if3_regs.inst1.predTaken = `FALSE; + if3_regs.inst1.predAddr = decodeTarget1; + end end // redirect control @@ -204,13 +228,13 @@ module IF_3( // nlp update info always_comb begin if3_nlp.update = 0; - if(if3_regs.inst0.valid && (if3_regs.inst0.bpdInfo.valid || (if3_regs.inst0.isJ && (!inst0Jr || (inst0Jr && if3_regs.inst0.nlpInfo.valid))))) begin + if(if3_regs.inst0.valid && (pred_valid && inst0IsCtrl || (if3_regs.inst0.isJ && (!inst0Jr || (inst0Jr && if3_regs.inst0.nlpInfo.valid))))) begin if3_nlp.update.pc = if3_regs.inst0.pc; if3_nlp.update.target = if3_regs.inst0.predAddr; if3_nlp.update.bimState = if3_regs.inst0.nlpInfo.valid ? if3_regs.inst0.nlpInfo.bimState : 2'b01; if3_nlp.update.shouldTake = if3_regs.inst0.predTaken; if3_nlp.update.valid = `TRUE; - end else if(if3_regs.inst1.valid && (if3_regs.inst1.bpdInfo.valid || (if3_regs.inst1.isJ && (!inst1Jr || (inst1Jr && if3_regs.inst1.nlpInfo.valid))))) begin + end else if(if3_regs.inst1.valid && (pred_valid && inst1IsCtrl || (if3_regs.inst1.isJ && (!inst1Jr || (inst1Jr && if3_regs.inst1.nlpInfo.valid))))) begin if3_nlp.update.pc = if3_regs.inst1.pc; if3_nlp.update.target = if3_regs.inst1.predAddr; if3_nlp.update.bimState = if3_regs.inst1.nlpInfo.valid ? if3_regs.inst1.nlpInfo.bimState : 2'b01; diff --git a/source/sources_1/new/ifu/TAGE.sv b/source/sources_1/new/ifu/TAGE.sv index 71b7f66..706d692 100644 --- a/source/sources_1/new/ifu/TAGE.sv +++ b/source/sources_1/new/ifu/TAGE.sv @@ -9,8 +9,9 @@ module TAGE( input rst, input pause, input recover, - input new_branch_happen, - input new_branch_taken, + input IF3_isBranch, + input IF3_isJ, + // input new_branch_taken, // For branch prediction input [31:0] br_pc, output pred_valid, @@ -19,23 +20,25 @@ module TAGE( output TAGEPred pred_info, // For branch prediction update input commit_valid, - input [31:0] committed_pc, + input [31:0] committed_target, input TAGEPred committed_pred_info, input committed_branch_taken, input committed_mispred ); - + assign pred_target = 0; TAGEIndex [3:0] index_01; TAGETag [3:0] PCTags_01; TAGEIndex [3:0] index_01_r; TAGETag [3:0] PCTags_01_r; + wire new_branch_taken; + assign new_branch_taken = pred_taken || (IF3_isBranch && IF3_isJ); wire flush_ubits_hi_01, flush_ubits_lo_01; TAGE_Phase0 phase0( .clk(clk), .rst(rst), .pause(pause), .recover(recover), - .new_branch_happen(new_branch_happen), + .new_branch_happen(IF3_isBranch), .new_branch_taken(new_branch_taken), .br_pc(br_pc), .commit_valid(commit_valid), @@ -65,17 +68,20 @@ module TAGE( // Phase 1/2 Regs TAGEPred TAGEResp_o, TAGEResp_r; wire PredTaken_o; + wire pred_valid_o; + reg pred_valid_r; reg PredTaken_r; TAGE_Phase1 phase1( .clk(clk), .rst(rst), .pause(pause), .recover(recover), + .PredValid(pred_valid_o), // 是否需要Flush Useful Bit .flush_ubits_hi(flush_ubits_hi_01), .flush_ubits_lo(flush_ubits_lo_01), // 访问Tage的四个Index - .indexes(index_01_r), + .indexes(index_01), // For branch prediction .PCTags(PCTags_01_r), .TAGEResp(TAGEResp_o), @@ -92,12 +98,15 @@ module TAGE( if(rst) begin TAGEResp_r <= 0; PredTaken_r <= 0; + pred_valid_r <= 0; end else begin TAGEResp_r <= TAGEResp_o; PredTaken_r <= PredTaken_o; + pred_valid_r <= pred_valid; end end assign pred_taken = PredTaken_r; assign pred_info = TAGEResp_r; + assign pred_valid = pred_valid_r; endmodule diff --git a/source/sources_1/new/ifu/TAGE_Phase0.sv b/source/sources_1/new/ifu/TAGE_Phase0.sv index 619b21f..0208635 100644 --- a/source/sources_1/new/ifu/TAGE_Phase0.sv +++ b/source/sources_1/new/ifu/TAGE_Phase0.sv @@ -26,8 +26,8 @@ module TAGE_Phase0( wire [9:0] folded_hist_10; wire [9:0] folded_hist_20; - wire [9:0] folded_hist_30; wire [9:0] folded_hist_40; + wire [9:0] folded_hist_80; // Predict Phase 0: Index generation logic diff --git a/source/sources_1/new/ifu/TAGE_Phase1.sv b/source/sources_1/new/ifu/TAGE_Phase1.sv index e4b2e42..0e12b50 100644 --- a/source/sources_1/new/ifu/TAGE_Phase1.sv +++ b/source/sources_1/new/ifu/TAGE_Phase1.sv @@ -2,7 +2,7 @@ ////////////////////////////////////////////////////////////////////////////////// // Tage分支预测器，历史长度10，20，40，80 ////////////////////////////////////////////////////////////////////////////////// -`include "../defines.svh" +`include "../defines/defines.svh" module TAGE_Phase1( input clk, @@ -17,6 +17,7 @@ module TAGE_Phase1( output TAGETag [3:0] PCTags, output TAGEPred TAGEResp, output PredTaken, + output PredValid, // For branch prediction update input committed_branch_taken, input [31:0] committed_pc, @@ -78,7 +79,7 @@ module TAGE_Phase1( ); end endgenerate - + wire hit; assign hit = |TAGE_hit ; assign provider = TAGE_hit[3] ? 3 : @@ -87,7 +88,7 @@ module TAGE_Phase1( TAGE_hit[0] ? 0 : 0; wire [3:0] alter_mask; wire alter_hit; - assign alter_mask = ( hit & ~(1 << provider) ); + assign alter_mask = ( TAGE_hit & ~(1 << provider) ); assign alter_hit = |alter_mask; assign alter = alter_mask[3] ? 3 : alter_mask[2] ? 2 : @@ -100,7 +101,7 @@ module TAGE_Phase1( wire not_useful_1 = ( useful[1] == 0 ); wire not_useful_2 = ( useful[2] == 0 ); wire not_useful_3 = ( useful[3] == 0 ); - wire [3:0] free_useful_vec = ~{ not_useful_3, not_useful_2, not_useful_1, not_useful_0 }; + wire [3:0] free_useful_vec = { not_useful_3, not_useful_2, not_useful_1, not_useful_0 }; wire [3:0] provider_mask = provider == 2'b00 ? 4'b1110 : provider == 2'b01 ? 4'b1100 : provider == 2'b10 ? 4'b1000 : 4'b0000 ; @@ -164,6 +165,8 @@ module TAGE_Phase1( new_to_allocate = 0; update_index = 0; update_tag = 0; + update_ctr = 0; + update_useful = 0; if(commit_valid) begin if(committed_pred_info.hit) begin // 如果预测的结果是从预测器出来的 // 对于Provider的更新 @@ -171,6 +174,7 @@ module TAGE_Phase1( update_index[committed_pred_info.provider] = committed_pred_info.hit_index; // Useful bit if(committed_pred_info.has_alter) begin // 需要更新useful bit + update_useful[committed_pred_info.provider] = 1'b1; inc_useful[committed_pred_info.provider] = ~committed_mispred; dec_useful[committed_pred_info.provider] = committed_mispred; end @@ -181,26 +185,26 @@ module TAGE_Phase1( update_ctr[committed_pred_info.provider] = committed_pred_info.ctr == 2'b11 ? 2'b11 : committed_pred_info.ctr + 2'b01; end update_tag[committed_pred_info.provider] = committed_pred_info.hit_tag; - end - if(committed_mispred && committed_pred_info.provider != 2'b11) begin - // 如果预测失败，并且不是使用最长历史，还需要尝试分配一个新的项 - if(committed_pred_info.has_free_to_alloc) begin // 分配一个新的项 - update_en[committed_pred_info.on_mispred_bank] = 1; - reset_useful[committed_pred_info.on_mispred_bank] = 1; - update_ctr[committed_pred_info.on_mispred_bank] = committed_branch_taken ? 3'b100 : 3'b011; - end else begin // 对于i>j，将所有的useful减1，并不分配 - for( integer i = 0; i<4; i++ ) begin - if( i>committed_pred_info.provider ) dec_useful[i] = 1; + if(committed_mispred && committed_pred_info.provider != 2'b11) begin + // 如果预测失败，并且不是使用最长历史，还需要尝试分配一个新的项 + if(committed_pred_info.has_free_to_alloc) begin // 分配一个新的项 + update_en[committed_pred_info.on_mispred_bank] = 1; + reset_useful[committed_pred_info.on_mispred_bank] = 1; + update_ctr[committed_pred_info.on_mispred_bank] = committed_branch_taken ? 3'b100 : 3'b011; + end else begin // 对于i>j，将所有的useful减1，并不分配 + for( integer i = 0; i<4; i++ ) begin + if( i>committed_pred_info.provider ) dec_useful[i] = 1; + end end end + end else begin // 如果没有Hit，就分配第0个 + update_en[0] = 1; + update_ctr[0] = committed_branch_taken ? 3'b100 : 3'b011; + update_index[0] = committed_pred_info.on_mispred_index; + update_tag[0] = committed_pred_info.on_mispred_tag; + reset_useful[0] = 1; end - end else begin // 如果没有Hit，就分配第0个 - update_en[0] = 1; - update_ctr[0] = committed_branch_taken ? 3'b100 : 3'b011; - update_index[0] = committed_pred_info.on_mispred_index; - update_tag[0] = committed_pred_info.on_mispred_tag; - reset_useful[0] = 1; end end - + assign PredValid = hit; endmodule diff --git a/source/sources_1/new/ifu/TageBank.sv b/source/sources_1/new/ifu/TageBank.sv index f479a0c..a2ebe2c 100644 --- a/source/sources_1/new/ifu/TageBank.sv +++ b/source/sources_1/new/ifu/TageBank.sv @@ -48,10 +48,11 @@ always_ff @(posedge clk) begin UsefulBits[update_index] <= 0; end end +assign bypass = update_index == index_in; wire [10:0] dout; -assign tag_read = dout[10:3]; -assign ctr_read = dout[2:0]; -assign hit_out = tag_read == tag_in; +assign tag_read = ~bypass ? dout[10:3] : update_tag; +assign ctr_out = ~bypass ? dout[2:0] : update_ctr; +assign hit_out = ~bypass ? (tag_read == tag_in) : (update_tag == tag_in); assign useful_out = UsefulBits[index_in]; assign wen = update_en; wire [10:0] din; @@ -59,12 +60,33 @@ wire [10:0] din; assign din[10:3] = update_tag; assign din[2:0] = update_ctr; -dist_mem_gen_0 tag_ctr ( - .a(update_index), // Write address - .d(din), // input wire [10 : 0] d - .dpra(index_in), // Read address - .clk(clk), // input wire clk - .we(update_en), // input wire we - .dpo(dout) // output wire [10 : 0] dpo + +// dist_mem_gen_0 tag_ctr ( +// .a(update_index), // Write address +// .d(din), // input wire [10 : 0] d +// .dpra(index_in), // Read address +// .clk(clk), // input wire clk +// .we(update_en), // input wire we +// .dpo(dout) // output wire [10 : 0] dpo +// ); + +// TAGEHist history ( +// .clk(clk), // input wire clka +// .wea(update_en), // input wire [0 : 0] wea +// .addra(update_index), // input wire [9 : 0] addra +// .dina(din), // input wire [10 : 0] dina +// .addrb(index_in), // input wire [9 : 0] addrb +// .doutb(dout) // output wire [10 : 0] doutb +// ); + +blk_mem_gen_0 history ( + .clka(clk), // input wire clka + .wea(update_en), // input wire [0 : 0] wea + .addra(update_index), // input wire [9 : 0] addra + .dina(din), // input wire [10 : 0] dina + .clkb(clk), // input wire clkb + .enb(~bypass), + .addrb(index_in), // input wire [9 : 0] addrb + .doutb(dout) // output wire [10 : 0] doutb ); endmodule diff --git a/source/sources_1/new/interface.sv b/source/sources_1/new/interface.sv index 0deab6a..0097868 100644 --- a/source/sources_1/new/interface.sv +++ b/source/sources_1/new/interface.sv @@ -349,11 +349,14 @@ interface IF3_Regs; endinterface //Regs_IF3 interface BPDUpdate; - BPDUpdateInfo update; logic updValid; + Word updTarget; + TAGEPred updInfo; + logic updTaken; + logic updMisPred; - modport backend(output update, updValid); - modport bpd(input update, updValid); + modport backend(output updValid, updInfo, updTaken, updMisPred, updTarget); + modport bpd(input updValid, updInfo, updTaken, updMisPred, updTarget); endinterface interface NLP_IF0;