From f798669130db64bdcdb0a0addce22f4e0ac2653e Mon Sep 17 00:00:00 2001 From: Bohan Hu Date: Thu, 20 Aug 2020 21:18:09 +0800 Subject: [PATCH] remove unnecessary files --- src/ip/axi_test_blk_mem/axi_test_blk_mem.xci | 314 ------------------ src/ip/axi_test_blk_mem/ip.coe | 2 - src/ip/blk_mem_gen_0/blk_mem_gen_0.xci | 319 ------------------- src/rtl/exu/MDUTest.sv | 144 --------- src/rtl/exu/RF_FU_regs.sv | 44 --- src/rtl/ifu/IFU.sv | 3 +- src/rtl/ifu/TargetBuffer.sv | 14 - src/rtl/issue/issue_arbiter_4.sv | 23 -- src/rtl/issue/scoreboard.sv | 52 --- 9 files changed, 1 insertion(+), 914 deletions(-) delete mode 100644 src/ip/axi_test_blk_mem/axi_test_blk_mem.xci delete mode 100644 src/ip/axi_test_blk_mem/ip.coe delete mode 100644 src/ip/blk_mem_gen_0/blk_mem_gen_0.xci delete mode 100644 src/rtl/exu/MDUTest.sv delete mode 100644 src/rtl/ifu/TargetBuffer.sv delete mode 100644 src/rtl/issue/issue_arbiter_4.sv diff --git a/src/ip/axi_test_blk_mem/axi_test_blk_mem.xci b/src/ip/axi_test_blk_mem/axi_test_blk_mem.xci deleted file mode 100644 index bb7f9a7..0000000 --- a/src/ip/axi_test_blk_mem/axi_test_blk_mem.xci +++ /dev/null @@ -1,314 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - axi_test_blk_mem - - - 4096 - 32 - 0 - 0 - 0 - - 32 - 100000000 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 4 - 0 - 256 - 2 - 1 - 2 - 1 - 0.000 - AXI4 - READ_WRITE - 0 - 0 - 1 - 0 - 0 - 32 - 0 - 0 - 0 - - 32 - 100000000 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 4 - 0 - 256 - 2 - 1 - 2 - 1 - 0.000 - AXI4 - READ_WRITE - 0 - 0 - 1 - 0 - 0 - OTHER - NONE - 8192 - 32 - 1 - - OTHER - NONE - 8192 - 32 - 1 - - - 100000000 - 0 - 0.000 - 0 - 18 - 18 - 1 - 4 - 0 - 1 - 8 - 1 - 0 - 256 - NONE - 0 - 0 - 0 - ./ - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - Estimated Power for IP : 21.018106 mW - artix7 - 1 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - axi_test_blk_mem.mem - axi_test_blk_mem.mif - 1 - 1 - 1 - 0 - 1 - 262144 - 262144 - 1 - 1 - 32 - 32 - 0 - 0 - CE - CE - ALL - 0 - 1 - 1 - 1 - 0 - 0 - 0 - 4 - 4 - 262144 - 262144 - READ_FIRST - READ_FIRST - 32 - 32 - artix7 - 4 - Memory_Slave - AXI4_Full - false - Minimum_Area - true - 8 - NONE - C:/nscscc/SHIT-Core/source/ifuTest.txt - ALL - axi_test_blk_mem - false - false - false - false - false - true - false - false - false - Use_ENA_Pin - Use_ENB_Pin - Single_Bit_Error_Injection - true - AXI4 - true - no_mem_loaded - Simple_Dual_Port_RAM - READ_FIRST - READ_FIRST - 0 - 0 - BRAM - 0 - 100 - 100 - 50 - 100 - 100 - 0 - 8kx2 - false - false - 1 - 1 - 32 - 32 - false - false - false - false - 0 - false - false - CE - CE - ASYNC - true - true - false - false - false - false - true - 262144 - 32 - 32 - No_ECC - false - false - false - Stand_Alone - artix7 - - - xc7a200t - fbg676 - VERILOG - - MIXED - -2 - - - TRUE - TRUE - IP_Flow - 4 - TRUE - . - - . - 2019.2 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git 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a/src/ip/blk_mem_gen_0/blk_mem_gen_0.xci b/src/ip/blk_mem_gen_0/blk_mem_gen_0.xci deleted file mode 100644 index 3dfdc6c..0000000 --- a/src/ip/blk_mem_gen_0/blk_mem_gen_0.xci +++ /dev/null @@ -1,319 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - blk_mem_gen_0 - - - 4096 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - OTHER - NONE - 8192 - 32 - 1 - - OTHER - NONE - 8192 - 32 - 1 - - - 100000000 - 0 - 0.000 - 0 - 10 - 10 - 1 - 4 - 0 - 1 - 9 - 1 - 1 - 0 - NONE - 0 - 0 - 0 - ./ - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Estimated Power for IP : 2.5696 mW - artix7 - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - blk_mem_gen_0.mem - no_coe_file_loaded - 0 - 0 - 1 - 0 - 1 - 1024 - 1024 - 1 - 1 - 11 - 11 - 0 - 0 - CE - CE - ALL - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 1 - 1 - 1024 - 1024 - NO_CHANGE - READ_FIRST - 11 - 11 - artix7 - 4 - Memory_Slave - AXI4_Full - false - Minimum_Area - true - 9 - NONE - no_coe_file_loaded - ALL - blk_mem_gen_0 - false - false - false - false - false - false - false - false - false - Use_ENA_Pin - Use_ENB_Pin - Single_Bit_Error_Injection - true - Native - false - no_mem_loaded - Simple_Dual_Port_RAM - NO_CHANGE - READ_FIRST - 0 - 0 - BRAM - 0 - 100 - 100 - 50 - 100 - 100 - 0 - 8kx2 - false - false - 1 - 1 - 11 - 11 - false - false - false - false - 0 - false - false - CE - CE - SYNC - false - false - false - false - false - false - false - 1024 - 11 - 11 - No_ECC - false - false - false - Stand_Alone - artix7 - - - xc7a200t - fbg676 - VERILOG - - MIXED - -2 - - - TRUE - TRUE - IP_Flow - 4 - TRUE - . - - . - 2019.2 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/src/rtl/exu/MDUTest.sv b/src/rtl/exu/MDUTest.sv deleted file mode 100644 index cb289e8..0000000 --- a/src/rtl/exu/MDUTest.sv +++ /dev/null @@ -1,144 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2020/07/21 00:12:38 -// Design Name: -// Module Name: MDUTest -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// -`include "../defines/defines.svh" - - -module MDUTest( - -); - - logic clk; - logic rst; - UOPBundle uopHi; - UOPBundle uopLo; - PRFrData rdata; - PRFwInfo wbData; - logic mulBusy; - logic divBusy; - - FU_ROB mdu_rob(); - MDUTestInterface_MUL mul(); - MDUTestInterface_DIV div(); - - assign mul.clk = clk; - assign div.clk = clk; - assign uopHi.uOP = mul.uopHi.valid === `TRUE ? mul.uopHi.uOP : div.uopHi.uOP; - assign uopLo.uOP = mul.uopLo.valid === `TRUE ? mul.uopLo.uOP : div.uopLo.uOP; - assign uopHi.id = mul.uopHi.valid === `TRUE ? mul.uopHi.id : div.uopHi.id ; - assign uopLo.id = mul.uopLo.valid === `TRUE ? mul.uopLo.id : div.uopLo.id ; - assign uopHi.valid = mul.uopHi.valid === `TRUE | div.uopHi.valid === `TRUE; - assign uopLo.valid = mul.uopLo.valid === `TRUE | div.uopLo.valid === `TRUE; - assign rdata = mul.uopLo.valid === `TRUE ? mul.rdata : div.rdata; - assign mul.mulBusy = mulBusy; - assign div.divBusy = divBusy; - - always #10 clk = ~clk; - - MDU mdu(.*); - - initial begin - mul.init(); - div.init(); - clk = 1'b0; - rst = 1'b1; - #115 - rst = 1'b0; - - mul.sendMul( 2, 3, 12'h000); - mul.sendMul( 2000000, 3000000, 12'h002); - mul.sendMul( 2, 3, 12'h004); - mul.sendMul( 2000000, 3000000, 12'h006); - mul.sendMul( 2, 3, 12'h008); - mul.sendMul( 2000000, 3000000, 12'h00a); - mul.sendMul( 2, 3, 12'h00c); - mul.sendMul( 2000000, 3000000, 12'h01e); - mul.sendMul( 2, 3, 12'h010); - mul.sendMul( 2000000, 3000000, 12'h012); - mul.sendMul( 2, 3, 12'h014); - mul.sendMul( 2000000, 3000000, 12'h016); - mul.sendMul( 2, 3, 12'h018); - mul.sendMul( 2000000, 3000000, 12'h01a); - mul.sendMul( 2, 3, 12'h01c); - mul.sendMul( 2000000, 3000000, 12'h01e); - mul.sendMul( 2, 3, 12'h020); - mul.sendMul( 2000000, 3000000, 12'h022); - mul.sendMul( 2, 3, 12'h024); - mul.sendMul( 2000000, 3000000, 12'h026); - mul.sendMul( 2, 3, 12'h028); - mul.sendMul( 2000000, 3000000, 12'h02a); - mul.sendMul( 2, 3, 12'h02c); - mul.sendMul( 2000000, 3000000, 12'h02e); - mul.sendMul( 2, 3, 12'h030); - mul.sendMul( 2000000, 3000000, 12'h032); - mul.sendMul( 2, 3, 12'h034); - mul.sendMul( 2000000, 3000000, 12'h036); - mul.sendMul( 2, 3, 12'h038); - mul.sendMul( 2000000, 3000000, 12'h03a); - mul.sendMul( 2, 3, 12'h03c); - mul.sendMul( 2000000, 3000000, 12'h03e); - mul.sendMul( 2, 3, 12'h040); - mul.sendMul( 2000000, 3000000, 12'h042); - mul.sendMul( 2, 3, 12'h044); - mul.sendMul( 2000000, 3000000, 12'h046); - mul.sendMul( 2, 3, 12'h048); - mul.sendMul( 2000000, 3000000, 12'h04a); - mul.sendMul( 2, 3, 12'h04c); - mul.sendMul( 2000000, 3000000, 12'h04e); - end - - initial begin - #115 - - div.sendDiv(23, 7, 12'h100, mul.uopHi.valid); - div.sendDiv(51, 9, 12'h102, mul.uopHi.valid); - div.sendDiv(23, 7, 12'h104, mul.uopHi.valid); - div.sendDiv(51, 9, 12'h106, mul.uopHi.valid); - div.sendDiv(23, 7, 12'h108, mul.uopHi.valid); - div.sendDiv(51, 9, 12'h10a, mul.uopHi.valid); - div.sendDiv(23, 7, 12'h10c, mul.uopHi.valid); - div.sendDiv(51, 9, 12'h11e, mul.uopHi.valid); - div.sendDiv(23, 7, 12'h110, mul.uopHi.valid); - div.sendDiv(51, 9, 12'h112, mul.uopHi.valid); - div.sendDiv(23, 7, 12'h114, mul.uopHi.valid); - div.sendDiv(51, 9, 12'h116, mul.uopHi.valid); - div.sendDiv(23, 7, 12'h118, mul.uopHi.valid); - div.sendDiv(51, 9, 12'h11a, mul.uopHi.valid); - div.sendDiv(23, 7, 12'h11c, mul.uopHi.valid); - div.sendDiv(51, 9, 12'h11e, mul.uopHi.valid); - div.sendDiv(23, 7, 12'h120, mul.uopHi.valid); - div.sendDiv(51, 9, 12'h122, mul.uopHi.valid); - div.sendDiv(23, 7, 12'h124, mul.uopHi.valid); - div.sendDiv(51, 9, 12'h126, mul.uopHi.valid); - div.sendDiv(23, 7, 12'h128, mul.uopHi.valid); - div.sendDiv(51, 9, 12'h12a, mul.uopHi.valid); - div.sendDiv(23, 7, 12'h12c, mul.uopHi.valid); - div.sendDiv(51, 9, 12'h12e, mul.uopHi.valid); - div.sendDiv(23, 7, 12'h130, mul.uopHi.valid); - div.sendDiv(51, 9, 12'h132, mul.uopHi.valid); - div.sendDiv(23, 7, 12'h134, mul.uopHi.valid); - div.sendDiv(51, 9, 12'h136, mul.uopHi.valid); - div.sendDiv(23, 7, 12'h138, mul.uopHi.valid); - div.sendDiv(51, 9, 12'h13a, mul.uopHi.valid); - div.sendDiv(23, 7, 12'h13c, mul.uopHi.valid); - div.sendDiv(51, 9, 12'h13e, mul.uopHi.valid); - end - -endmodule diff --git a/src/rtl/exu/RF_FU_regs.sv b/src/rtl/exu/RF_FU_regs.sv index 4ef47c0..af50e58 100644 --- a/src/rtl/exu/RF_FU_regs.sv +++ b/src/rtl/exu/RF_FU_regs.sv @@ -46,48 +46,4 @@ module RF_FU_regs( end end -endmodule - - - -module RF_LSU_regs( - input wire clk, - input wire rst, - - Ctrl.slave ctrl_rf_fu_regs, - input wire primPauseReq, - - input UOPBundle rfBundle, - input PRFrData rfRes, - input PRFwInfo bypass_alu0, - input PRFwInfo bypass_alu1, - - output UOPBundle fuBundle, - output PRFrData fuOprands -); - PRFrData currentOperands; - wire bypass_alu0_src0_en = bypass_alu0.wen && (bypass_alu0.rd == rfBundle.op0PAddr); - wire bypass_alu0_src1_en = bypass_alu0.wen && (bypass_alu0.rd == rfBundle.op1PAddr); - wire bypass_alu1_src0_en = bypass_alu1.wen && (bypass_alu1.rd == rfBundle.op0PAddr); - wire bypass_alu1_src1_en = bypass_alu1.wen && (bypass_alu1.rd == rfBundle.op1PAddr); - Word src0, src1; - assign src0 = bypass_alu0_src0_en ? bypass_alu0.wdata : - ( bypass_alu1_src0_en ? bypass_alu1.wdata : rfRes.rs0_data ); - assign src1 = bypass_alu0_src1_en ? bypass_alu0.wdata : - ( bypass_alu1_src1_en ? bypass_alu1.wdata : rfRes.rs1_data ); - assign currentOperands.rs0_data = src0; - assign currentOperands.rs1_data = src1; - always_ff @ (posedge clk) begin - if(rst || ctrl_rf_fu_regs.flush) begin - fuBundle <= 0; - fuOprands <= 0; - end else if(primPauseReq || ctrl_rf_fu_regs.pause) begin - fuBundle <= fuBundle; - fuOprands <= fuOprands; - end else begin - fuBundle <= rfBundle; - fuOprands <= currentOperands; - end - end - endmodule \ No newline at end of file diff --git a/src/rtl/ifu/IFU.sv b/src/rtl/ifu/IFU.sv index f622369..6afb65f 100644 --- a/src/rtl/ifu/IFU.sv +++ b/src/rtl/ifu/IFU.sv @@ -44,7 +44,6 @@ module IFU( IF_0 if0(.*); IF0_1_reg if01reg(.*); NLP nlp(.*); - BPD bpd(.*); ICache iCache(.*); IF2_3_reg if23reg(.*); IF_3 if3(.*); @@ -59,7 +58,7 @@ module IFU( // .IF3_isBranch (IF3_isBranch ), // .IF3_isJ (IF3_isJ ), // .br_pc (regs_iCache.PC ), - // // 送出的结果 + // // 送出的结? // .pred_valid (pred_valid ), // .pred_taken (pred_taken ), // .pred_target (pred_target ), diff --git a/src/rtl/ifu/TargetBuffer.sv b/src/rtl/ifu/TargetBuffer.sv deleted file mode 100644 index 6e60284..0000000 --- a/src/rtl/ifu/TargetBuffer.sv +++ /dev/null @@ -1,14 +0,0 @@ -`timescale 1ns / 1ps -`include "../defs.sv" -`include "../defines/defines.svh" -module TargetBuffer( - input clk, - input rst, - input [31:0] br_PC, - output [31:0] target_PC, - input [79:0] ghist -); - - - -endmodule \ No newline at end of file diff --git a/src/rtl/issue/issue_arbiter_4.sv b/src/rtl/issue/issue_arbiter_4.sv deleted file mode 100644 index e17b7e4..0000000 --- a/src/rtl/issue/issue_arbiter_4.sv +++ /dev/null @@ -1,23 +0,0 @@ -`timescale 1ns / 1ps -// 用于发射仲裁的逻辑（队列容量4） -module issue_arbiter_4( - input [3:0] rdys, - output reg [1:0] sel0, - output reg sel0_valid - ); - -wire [3:0] rdys_0 = rdys; -always_comb begin - sel0_valid = 1; - casez(rdys_0) - 4'b???1: sel0 = 2'b00; - 4'b??10: sel0 = 2'b01; - 4'b?100: sel0 = 2'b10; - 4'b1000: sel0 = 2'b11; - default: begin - sel0 = 2'b00 ; - sel0_valid = 0; - end - endcase -end -endmodule \ No newline at end of file diff --git a/src/rtl/issue/scoreboard.sv b/src/rtl/issue/scoreboard.sv index 21a5388..5c6e9b7 100644 --- a/src/rtl/issue/scoreboard.sv +++ b/src/rtl/issue/scoreboard.sv @@ -156,55 +156,3 @@ busy_table_6w4r bank4( ); endmodule - -module scoreboard_4r6w( - input clk, - input rst, - input flush, - // dispatched instructions - input set_busy_0, - input set_busy_1, - PRFNum set_busy_num_0, - PRFNum set_busy_num_1, - // issued instructions(at most 4 instructions issue at a time) - input clr_busy_ALU0, - input clr_busy_ALU1, - input clr_busy_LSU, - input clr_busy_MDU, - PRFNum clr_busy_num_ALU0, - PRFNum clr_busy_num_ALU1, - PRFNum clr_busy_num_LSU, - PRFNum clr_busy_num_MDU, - PRFNum [1:0] rd_num_l , - PRFNum [1:0] rd_num_r , - output [1:0] busyvec_l, - output [1:0] busyvec_r - ); - -busy_table_6w4r bank0( - .clk (clk), - .rst (rst), - .flush (flush), - .rd_port0 (rd_num_l[0]), - .rd_port1 (rd_num_l[1]), - .rd_port2 (rd_num_r[0]), - .rd_port3 (rd_num_r[1]), - .set_busy_0 (set_busy_0), - .set_busy_1 (set_busy_1), - .set_busy_num_0 (set_busy_num_0), - .set_busy_num_1 (set_busy_num_1), - .clr_busy_0 (clr_busy_ALU0), - .clr_busy_1 (clr_busy_ALU1), - .clr_busy_2 (clr_busy_LSU), - .clr_busy_3 (clr_busy_MDU), - .clr_busy_num_0 (clr_busy_num_ALU0), - .clr_busy_num_1 (clr_busy_num_ALU1), - .clr_busy_num_2 (clr_busy_num_LSU), - .clr_busy_num_3 (clr_busy_num_MDU), - .busy0 (busyvec_l[0]), - .busy1 (busyvec_l[1]), - .busy2 (busyvec_r[0]), - .busy3 (busyvec_r[1]) - ); - -endmodule