opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

SERV - The SErial RISC-V CPU

A Pi emulating a GameBoy sounds cheap. What about an FPGA?

It's a core. Made on Twitch.

SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. The design, the interface, and its capabilities and limitatio…

Verilog implementation of various types of CPUs

RISCV-32 based CPU made by the Fauxrje