From cef7fa0ff1b1edf5b3713bb6eeb4c305144d7744 Mon Sep 17 00:00:00 2001 From: Thomas Lively Date: Tue, 31 Mar 2020 20:03:24 -0700 Subject: [PATCH 1/8] Opcode renumbering This PR is for discussion only and should not be merged. Once we have reached consensus on the renumbering, the existing documents should be updated to reflect the new opcodes. The goals of this renumbering are: 1. To maintain consistency with the ordering of MVP operations 2. To organize sets of similar operations into tables such that the offset from an operation for one type to the same operation for the next type is constant for all operations in that set. 3. To use round hexadeciml numbers for offsets where not too wasteful. --- proposals/simd/NewOpcodes.md | 124 +++++++++++++++++++++++++++++++++++ 1 file changed, 124 insertions(+) create mode 100644 proposals/simd/NewOpcodes.md diff --git a/proposals/simd/NewOpcodes.md b/proposals/simd/NewOpcodes.md new file mode 100644 index 000000000..f556f22c1 --- /dev/null +++ b/proposals/simd/NewOpcodes.md @@ -0,0 +1,124 @@ +| Memory instruction | opcode | +| ------------------ | ------ | +| v128.load | 0x00 | +| i16x8.load8x8_s | 0x01 | +| i16x8.load8x8_u | 0x02 | +| i32x4.load16x4_s | 0x03 | +| i32x4.load16x4_u | 0x04 | +| i64x2.load32x2_s | 0x05 | +| i64x2.load32x2_u | 0x06 | +| v8x16.load_splat | 0x07 | +| v16x8.load_splat | 0x08 | +| v32x4.load_splat | 0x09 | +| v64x2.load_splat | 0x0a | +| v128.store | 0x0b | + +| Basic instruction | opcode | +| -------------------- | ------ | +| v128.const | 0x0c | +| v8x16.shuffle | 0x0d | +| v8x16.swizzle | 0x0e | +| i8x16.splat | 0x0f | +| i8x16.extract_lane_s | 0x10 | +| i8x16.extract_lane_u | 0x11 | +| i8x16.replace_lane | 0x12 | +| i16x8.splat | 0x13 | +| i16x8.extract_lane_s | 0x14 | +| i16x8.extract_lane_u | 0x15 | +| i16x8.replace_lane | 0x16 | +| i32x4.splat | 0x17 | +| i32x4.extract_lane | 0x18 | +| i32x4.replace_lane | 0x19 | +| i64x2.splat | 0x1a | +| i64x2.extract_lane | 0x1b | +| i64x2.replace_lane | 0x1c | +| f32x4.splat | 0x1d | +| f32x4.extract_lane | 0x1e | +| f32x4.replace_lane | 0x1f | +| f64x2.splat | 0x20 | +| f64x2.extract_lane | 0x21 | +| f64x2.replace_lane | 0x22 | + +| i8x16 Cmp | opcode | i16x8 Cmp | opcode | i32x4 Cmp | opcode | +| ---------- | ------ | ---------- | ------ | ---------- | ------ | +| i8x16.eq | 0x23 | i16x8.eq | 0x2d | i32x4.eq | 0x37 | +| i8x16.ne | 0x24 | i16x8.ne | 0x2e | i32x4.ne | 0x38 | +| i8x16.lt_s | 0x25 | i16x8.lt_s | 0x2f | i32x4.lt_s | 0x39 | +| i8x16.lt_u | 0x26 | i16x8.lt_u | 0x30 | i32x4.lt_u | 0x3a | +| i8x16.gt_s | 0x27 | i16x8.gt_s | 0x31 | i32x4.gt_s | 0x3b | +| i8x16.gt_u | 0x28 | i16x8.gt_u | 0x32 | i32x4.gt_u | 0x3c | +| i8x16.le_s | 0x29 | i16x8.le_s | 0x33 | i32x4.le_s | 0x3d | +| i8x16.le_u | 0x2a | i16x8.le_u | 0x34 | i32x4.le_u | 0x3e | +| i8x16.ge_s | 0x2b | i16x8.ge_s | 0x35 | i32x4.ge_s | 0x3f | +| i8x16.ge_u | 0x2c | i16x8.ge_u | 0x36 | i32x4.ge_u | 0x40 | + +| f32x4 Cmp | opcode | f64x2 Cmp | opcode | +| --------- | ------ | --------- | ------ | +| f32x4.eq | 0x41 | f64x2.eq | 0x47 | +| f32x4.ne | 0x42 | f64x2.ne | 0x48 | +| f32x4.lt | 0x43 | f64x2.lt | 0x49 | +| f32x4.gt | 0x44 | f64x2.gt | 0x4a | +| f32x4.le | 0x45 | f64x2.le | 0x4b | +| f32x4.ge | 0x46 | f64x2.ge | 0x4c | + +| v128 Op | opcode | +| -------------- | ------ | +| v128.not | 0x4d | +| v128.and | 0x4e | +| v128.andnot | 0x4f | +| v128.or | 0x50 | +| v128.xor | 0x51 | +| v128.bitselect | 0x52 | + +| i8x16 Op | opcode | i16x8 Op | opcode | i32x4 Op | opcode | i64x2 Op | opcode | +| -------------------- | ------ | ------------------------ | ------ | ------------------------ | ------ | ----------- | ------ | +| i8x16.abs | 0x60 | i16x8.abs | 0x80 | i32x4.abs | 0xa0 | ---- | 0xc0 | +| i8x16.neg | 0x61 | i16x8.neg | 0x81 | i32x4.neg | 0xa1 | i64x2.neg | 0xc1 | +| i8x16.any_true | 0x62 | i16x8.any_true | 0x82 | i32x4.any_true | 0xa2 | ---- | 0xc2 | +| i8x16.all_true | 0x63 | i16x8.all_true | 0x83 | i32x4.all_true | 0xa3 | ---- | 0xc3 | +| ---- bitmask ---- | 0x64 | ---- bitmask ---- | 0x84 | ---- bitmask ---- | 0xa4 | ---- | 0xc4 | +| i8x16.narrow_i16x8_s | 0x65 | i16x8.narrow_i32x4_s | 0x85 | ---- narrow ---- | 0xa5 | ---- | 0xc5 | +| i8x16.narrow_i16x8_u | 0x66 | i16x8.narrow_i32x4_u | 0x86 | ---- narrow ---- | 0xa6 | ---- | 0xc6 | +| ---- widen ---- | 0x67 | i16x8.widen_low_i8x16_s | 0x87 | i32x4.widen_low_i16x8_s | 0xa7 | ---- | 0xc7 | +| ---- widen ---- | 0x68 | i16x8.widen_high_i8x16_s | 0x88 | i32x4.widen_high_i16x8_s | 0xa8 | ---- | 0xc8 | +| ---- widen ---- | 0x69 | i16x8.widen_low_i8x16_u | 0x89 | i32x4.widen_low_i16x8_u | 0xa9 | ---- | 0xc9 | +| ---- widen ---- | 0x6a | i16x8.widen_high_i8x16_u | 0x8a | i32x4.widen_high_i16x8_u | 0xaa | ---- | 0xca | +| i8x16.shl | 0x6b | i16x8.shl | 0x8b | i32x4.shl | 0xab | i64x2.shl | 0xcb | +| i8x16.shr_s | 0x6c | i16x8.shr_s | 0x8c | i32x4.shr_s | 0xac | i64x2.shr_s | 0xcc | +| i8x16.shr_u | 0x6d | i16x8.shr_u | 0x8d | i32x4.shr_u | 0xad | i64x2.shr_u | 0xcd | +| i8x16.add | 0x6e | i16x8.add | 0x8e | i32x4.add | 0xae | i64x2.add | 0xce | +| i8x16.add_saturate_s | 0x6f | i16x8.add_saturate_s | 0x8f | ---- add_sat ---- | 0xaf | ---- | 0xcf | +| i8x16.add_saturate_u | 0x70 | i16x8.add_saturate_u | 0x90 | ---- add_sat ---- | 0xb0 | ---- | 0xd0 | +| i8x16.sub | 0x71 | i16x8.sub | 0x91 | i32x4.sub | 0xb1 | i64x2.sub | 0xd1 | +| i8x16.sub_saturate_s | 0x72 | i16x8.sub_saturate_s | 0x92 | ---- sub_sat ---- | 0xb2 | ---- | 0xd2 | +| i8x16.sub_saturate_u | 0x73 | i16x8.sub_saturate_u | 0x93 | ---- sub_sat ---- | 0xb3 | ---- | 0xd3 | +| ---- dot ---- | 0x74 | ---- dot ---- | 0x94 | i32x4.dot_i16x8_s | 0xb4 | ---- | 0xd4 | +| ---- mul ---- | 0x75 | i16x8.mul | 0x95 | i32x4.mul | 0xb5 | i64x2.mul | 0xd5 | +| i8x16.min_s | 0x76 | i16x8.min_s | 0x96 | i32x4.min_s | 0xb6 | ---- | 0xd6 | +| i8x16.min_u | 0x77 | i16x8.min_u | 0x97 | i32x4.min_u | 0xb7 | ---- | 0xd7 | +| i8x16.max_s | 0x78 | i16x8.max_s | 0x98 | i32x4.max_s | 0xb8 | ---- | 0xd8 | +| i8x16.max_u | 0x79 | i16x8.max_u | 0x99 | i32x4.max_u | 0xb9 | ---- | 0xd9 | +| ---- avgr_s ---- | 0x7a | ---- avgr_s ---- | 0x9a | ---- avgr_s ---- | 0xba | ---- | 0xda | +| i8x16.avgr_u | 0x7b | i16x8.avgr_u | 0x9b | ---- avgr_u ---- | 0xbb | ---- | 0xdb | + +| f32x4 Op | opcode | f64x2 Op | opcode | +| --------------- | ------ | --------------- | ------ | +| f32x4.abs | 0xe0 | f64x2.abs | 0xf0 | +| f32x4.neg | 0xe1 | f64x2.neg | 0xf1 | +| ---- round ---- | 0xe2 | ---- round ---- | 0xf2 | +| f32x4.sqrt | 0xe3 | f64x2.sqrt | 0xf3 | +| f32x4.add | 0xe4 | f64x2.add | 0xf4 | +| f32x4.sub | 0xe5 | f64x2.sub | 0xf5 | +| f32x4.mul | 0xe6 | f64x2.mul | 0xf6 | +| f32x4.div | 0xe7 | f64x2.div | 0xf7 | +| f32x4.min | 0xe8 | f64x2.min | 0xf8 | +| f32x4.max | 0xe9 | f64x2.max | 0xf9 | +| ---- pmin ---- | 0xea | ---- pmin ---- | 0xfa | +| ---- pmax ---- | 0xeb | ---- pmax ---- | 0xfb | + +| Conversion Op | opcode | +| ----------------------- | ------ | +| i32x4.trunc_sat_f32x4_s | 0x100 | +| i32x4.trunc_sat_f32x4_u | 0x101 | +| f32x4.convert_i32x4_s | 0x102 | +| f32x4.convert_i32x4_u | 0x103 | From 7bb6c88bf62cd4a50c50b9a037f78713cf90f4a8 Mon Sep 17 00:00:00 2001 From: Thomas Lively Date: Tue, 31 Mar 2020 21:56:23 -0700 Subject: [PATCH 2/8] Add leading zeroes to conversion ops --- proposals/simd/NewOpcodes.md | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/proposals/simd/NewOpcodes.md b/proposals/simd/NewOpcodes.md index f556f22c1..de7809fed 100644 --- a/proposals/simd/NewOpcodes.md +++ b/proposals/simd/NewOpcodes.md @@ -116,9 +116,9 @@ | ---- pmin ---- | 0xea | ---- pmin ---- | 0xfa | | ---- pmax ---- | 0xeb | ---- pmax ---- | 0xfb | -| Conversion Op | opcode | -| ----------------------- | ------ | -| i32x4.trunc_sat_f32x4_s | 0x100 | -| i32x4.trunc_sat_f32x4_u | 0x101 | -| f32x4.convert_i32x4_s | 0x102 | -| f32x4.convert_i32x4_u | 0x103 | +| Conversion Op | opcode | +| ----------------------- | -------- | +| i32x4.trunc_sat_f32x4_s | 0x0100 | +| i32x4.trunc_sat_f32x4_u | 0x0101 | +| f32x4.convert_i32x4_s | 0x0102 | +| f32x4.convert_i32x4_u | 0x0103 | From be3e177277fc607b884d6062e5174b8cb3c970e3 Mon Sep 17 00:00:00 2001 From: Thomas Lively Date: Wed, 8 Apr 2020 19:01:03 -0700 Subject: [PATCH 3/8] Separate splats from lane operations --- proposals/simd/NewOpcodes.md | 50 ++++++++++++++++++++---------------- 1 file changed, 28 insertions(+), 22 deletions(-) diff --git a/proposals/simd/NewOpcodes.md b/proposals/simd/NewOpcodes.md index de7809fed..d431e122c 100644 --- a/proposals/simd/NewOpcodes.md +++ b/proposals/simd/NewOpcodes.md @@ -13,29 +13,35 @@ | v64x2.load_splat | 0x0a | | v128.store | 0x0b | -| Basic instruction | opcode | +| Basic operation | opcode | +| ----------------| ------ | +| v128.const | 0x0c | +| v8x16.shuffle | 0x0d | +| v8x16.swizzle | 0x0e | + +| Splat operation | opcode | +| --------------- | ------ | +| i8x16.splat | 0x0f | +| i16x8.splat | 0x10 | +| i32x4.splat | 0x11 | +| i64x2.splat | 0x12 | +| f32x4.splat | 0x13 | +| f64x2.splat | 0x14 | + +| Lane operation | opcode | | -------------------- | ------ | -| v128.const | 0x0c | -| v8x16.shuffle | 0x0d | -| v8x16.swizzle | 0x0e | -| i8x16.splat | 0x0f | -| i8x16.extract_lane_s | 0x10 | -| i8x16.extract_lane_u | 0x11 | -| i8x16.replace_lane | 0x12 | -| i16x8.splat | 0x13 | -| i16x8.extract_lane_s | 0x14 | -| i16x8.extract_lane_u | 0x15 | -| i16x8.replace_lane | 0x16 | -| i32x4.splat | 0x17 | -| i32x4.extract_lane | 0x18 | -| i32x4.replace_lane | 0x19 | -| i64x2.splat | 0x1a | -| i64x2.extract_lane | 0x1b | -| i64x2.replace_lane | 0x1c | -| f32x4.splat | 0x1d | -| f32x4.extract_lane | 0x1e | -| f32x4.replace_lane | 0x1f | -| f64x2.splat | 0x20 | +| i8x16.extract_lane_s | 0x15 | +| i8x16.extract_lane_u | 0x16 | +| i8x16.replace_lane | 0x17 | +| i16x8.extract_lane_s | 0x18 | +| i16x8.extract_lane_u | 0x19 | +| i16x8.replace_lane | 0x1a | +| i32x4.extract_lane | 0x1b | +| i32x4.replace_lane | 0x1c | +| i64x2.extract_lane | 0x1d | +| i64x2.replace_lane | 0x1e | +| f32x4.extract_lane | 0x1f | +| f32x4.replace_lane | 0x20 | | f64x2.extract_lane | 0x21 | | f64x2.replace_lane | 0x22 | From 3ef2bfa17ef1abad69a09f70159a4ed19974b670 Mon Sep 17 00:00:00 2001 From: Thomas Lively Date: Thu, 30 Apr 2020 11:35:14 -0700 Subject: [PATCH 4/8] Condense float and conversion opcode space --- proposals/simd/NewOpcodes.md | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/proposals/simd/NewOpcodes.md b/proposals/simd/NewOpcodes.md index d431e122c..5dc7a81d1 100644 --- a/proposals/simd/NewOpcodes.md +++ b/proposals/simd/NewOpcodes.md @@ -109,22 +109,22 @@ | f32x4 Op | opcode | f64x2 Op | opcode | | --------------- | ------ | --------------- | ------ | -| f32x4.abs | 0xe0 | f64x2.abs | 0xf0 | -| f32x4.neg | 0xe1 | f64x2.neg | 0xf1 | -| ---- round ---- | 0xe2 | ---- round ---- | 0xf2 | -| f32x4.sqrt | 0xe3 | f64x2.sqrt | 0xf3 | -| f32x4.add | 0xe4 | f64x2.add | 0xf4 | -| f32x4.sub | 0xe5 | f64x2.sub | 0xf5 | -| f32x4.mul | 0xe6 | f64x2.mul | 0xf6 | -| f32x4.div | 0xe7 | f64x2.div | 0xf7 | -| f32x4.min | 0xe8 | f64x2.min | 0xf8 | -| f32x4.max | 0xe9 | f64x2.max | 0xf9 | -| ---- pmin ---- | 0xea | ---- pmin ---- | 0xfa | -| ---- pmax ---- | 0xeb | ---- pmax ---- | 0xfb | +| f32x4.abs | 0xe0 | f64x2.abs | 0xec | +| f32x4.neg | 0xe1 | f64x2.neg | 0xed | +| ---- round ---- | 0xe2 | ---- round ---- | 0xee | +| f32x4.sqrt | 0xe3 | f64x2.sqrt | 0xef | +| f32x4.add | 0xe4 | f64x2.add | 0xf0 | +| f32x4.sub | 0xe5 | f64x2.sub | 0xf1 | +| f32x4.mul | 0xe6 | f64x2.mul | 0xf2 | +| f32x4.div | 0xe7 | f64x2.div | 0xf3 | +| f32x4.min | 0xe8 | f64x2.min | 0xf4 | +| f32x4.max | 0xe9 | f64x2.max | 0xf5 | +| ---- pmin ---- | 0xea | ---- pmin ---- | 0xf6 | +| ---- pmax ---- | 0xeb | ---- pmax ---- | 0xf7 | -| Conversion Op | opcode | -| ----------------------- | -------- | -| i32x4.trunc_sat_f32x4_s | 0x0100 | -| i32x4.trunc_sat_f32x4_u | 0x0101 | -| f32x4.convert_i32x4_s | 0x0102 | -| f32x4.convert_i32x4_u | 0x0103 | +| Conversion Op | opcode | +| ----------------------- | ------ | +| i32x4.trunc_sat_f32x4_s | 0xf8 | +| i32x4.trunc_sat_f32x4_u | 0xf9 | +| f32x4.convert_i32x4_s | 0xfa | +| f32x4.convert_i32x4_u | 0xfb | From b524435612c4d0018957000f348884d3b9ac56a2 Mon Sep 17 00:00:00 2001 From: Thomas Lively <7121787+tlively@users.noreply.github.com> Date: Thu, 7 May 2020 11:06:23 -0700 Subject: [PATCH 5/8] Stub out the dot product instruction --- proposals/simd/NewOpcodes.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/proposals/simd/NewOpcodes.md b/proposals/simd/NewOpcodes.md index 5dc7a81d1..b7aaae2c0 100644 --- a/proposals/simd/NewOpcodes.md +++ b/proposals/simd/NewOpcodes.md @@ -98,7 +98,7 @@ | i8x16.sub | 0x71 | i16x8.sub | 0x91 | i32x4.sub | 0xb1 | i64x2.sub | 0xd1 | | i8x16.sub_saturate_s | 0x72 | i16x8.sub_saturate_s | 0x92 | ---- sub_sat ---- | 0xb2 | ---- | 0xd2 | | i8x16.sub_saturate_u | 0x73 | i16x8.sub_saturate_u | 0x93 | ---- sub_sat ---- | 0xb3 | ---- | 0xd3 | -| ---- dot ---- | 0x74 | ---- dot ---- | 0x94 | i32x4.dot_i16x8_s | 0xb4 | ---- | 0xd4 | +| ---- dot ---- | 0x74 | ---- dot ---- | 0x94 | ---- dot ---- | 0xb4 | ---- | 0xd4 | | ---- mul ---- | 0x75 | i16x8.mul | 0x95 | i32x4.mul | 0xb5 | i64x2.mul | 0xd5 | | i8x16.min_s | 0x76 | i16x8.min_s | 0x96 | i32x4.min_s | 0xb6 | ---- | 0xd6 | | i8x16.min_u | 0x77 | i16x8.min_u | 0x97 | i32x4.min_u | 0xb7 | ---- | 0xd7 | From ad902649b6a890bf1f8d9122869ac92cb2addb71 Mon Sep 17 00:00:00 2001 From: Thomas Lively Date: Wed, 20 May 2020 12:56:06 -0700 Subject: [PATCH 6/8] Update docs to reflect new opcode ordering --- proposals/simd/BinarySIMD.md | 348 ++++++++++++------------ proposals/simd/ImplementationStatus.md | 362 ++++++++++++------------- 2 files changed, 355 insertions(+), 355 deletions(-) diff --git a/proposals/simd/BinarySIMD.md b/proposals/simd/BinarySIMD.md index a43dd8d05..232ee1a23 100644 --- a/proposals/simd/BinarySIMD.md +++ b/proposals/simd/BinarySIMD.md @@ -28,177 +28,177 @@ The `v8x16.shuffle` instruction has 16 bytes after `simdop`. | Instruction | `simdop` | Immediate operands | | ---------------------------|---------:|--------------------| | `v128.load` | `0x00`| m:memarg | -| `v128.store` | `0x01`| m:memarg | -| `v128.const` | `0x02`| i:ImmByte[16] | -| `i8x16.splat` | `0x04`| - | -| `i8x16.extract_lane_s` | `0x05`| i:LaneIdx16 | -| `i8x16.extract_lane_u` | `0x06`| i:LaneIdx16 | -| `i8x16.replace_lane` | `0x07`| i:LaneIdx16 | -| `i16x8.splat` | `0x08`| - | -| `i16x8.extract_lane_s` | `0x09`| i:LaneIdx8 | -| `i16x8.extract_lane_u` | `0x0a`| i:LaneIdx8 | -| `i16x8.replace_lane` | `0x0b`| i:LaneIdx8 | -| `i32x4.splat` | `0x0c`| - | -| `i32x4.extract_lane` | `0x0d`| i:LaneIdx4 | -| `i32x4.replace_lane` | `0x0e`| i:LaneIdx4 | -| `i64x2.splat` | `0x0f`| - | -| `i64x2.extract_lane` | `0x10`| i:LaneIdx2 | -| `i64x2.replace_lane` | `0x11`| i:LaneIdx2 | -| `f32x4.splat` | `0x12`| - | -| `f32x4.extract_lane` | `0x13`| i:LaneIdx4 | -| `f32x4.replace_lane` | `0x14`| i:LaneIdx4 | -| `f64x2.splat` | `0x15`| - | -| `f64x2.extract_lane` | `0x16`| i:LaneIdx2 | -| `f64x2.replace_lane` | `0x17`| i:LaneIdx2 | -| `i8x16.eq` | `0x18`| - | -| `i8x16.ne` | `0x19`| - | -| `i8x16.lt_s` | `0x1a`| - | -| `i8x16.lt_u` | `0x1b`| - | -| `i8x16.gt_s` | `0x1c`| - | -| `i8x16.gt_u` | `0x1d`| - | -| `i8x16.le_s` | `0x1e`| - | -| `i8x16.le_u` | `0x1f`| - | -| `i8x16.ge_s` | `0x20`| - | -| `i8x16.ge_u` | `0x21`| - | -| `i16x8.eq` | `0x22`| - | -| `i16x8.ne` | `0x23`| - | -| `i16x8.lt_s` | `0x24`| - | -| `i16x8.lt_u` | `0x25`| - | -| `i16x8.gt_s` | `0x26`| - | -| `i16x8.gt_u` | `0x27`| - | -| `i16x8.le_s` | `0x28`| - | -| `i16x8.le_u` | `0x29`| - | -| `i16x8.ge_s` | `0x2a`| - | -| `i16x8.ge_u` | `0x2b`| - | -| `i32x4.eq` | `0x2c`| - | -| `i32x4.ne` | `0x2d`| - | -| `i32x4.lt_s` | `0x2e`| - | -| `i32x4.lt_u` | `0x2f`| - | -| `i32x4.gt_s` | `0x30`| - | -| `i32x4.gt_u` | `0x31`| - | -| `i32x4.le_s` | `0x32`| - | -| `i32x4.le_u` | `0x33`| - | -| `i32x4.ge_s` | `0x34`| - | -| `i32x4.ge_u` | `0x35`| - | -| `f32x4.eq` | `0x40`| - | -| `f32x4.ne` | `0x41`| - | -| `f32x4.lt` | `0x42`| - | -| `f32x4.gt` | `0x43`| - | -| `f32x4.le` | `0x44`| - | -| `f32x4.ge` | `0x45`| - | -| `f64x2.eq` | `0x46`| - | -| `f64x2.ne` | `0x47`| - | -| `f64x2.lt` | `0x48`| - | -| `f64x2.gt` | `0x49`| - | -| `f64x2.le` | `0x4a`| - | -| `f64x2.ge` | `0x4b`| - | -| `v128.not` | `0x4c`| - | -| `v128.and` | `0x4d`| - | -| `v128.or` | `0x4e`| - | -| `v128.xor` | `0x4f`| - | -| `v128.bitselect` | `0x50`| - | -| `i8x16.neg` | `0x51`| - | -| `i8x16.any_true` | `0x52`| - | -| `i8x16.all_true` | `0x53`| - | -| `i8x16.shl` | `0x54`| - | -| `i8x16.shr_s` | `0x55`| - | -| `i8x16.shr_u` | `0x56`| - | -| `i8x16.add` | `0x57`| - | -| `i8x16.add_saturate_s` | `0x58`| - | -| `i8x16.add_saturate_u` | `0x59`| - | -| `i8x16.sub` | `0x5a`| - | -| `i8x16.sub_saturate_s` | `0x5b`| - | -| `i8x16.sub_saturate_u` | `0x5c`| - | -| `i8x16.min_s` | `0x5e`| - | -| `i8x16.min_u` | `0x5f`| - | -| `i8x16.max_s` | `0x60`| - | -| `i8x16.max_u` | `0x61`| - | -| `i16x8.neg` | `0x62`| - | -| `i16x8.any_true` | `0x63`| - | -| `i16x8.all_true` | `0x64`| - | -| `i16x8.shl` | `0x65`| - | -| `i16x8.shr_s` | `0x66`| - | -| `i16x8.shr_u` | `0x67`| - | -| `i16x8.add` | `0x68`| - | -| `i16x8.add_saturate_s` | `0x69`| - | -| `i16x8.add_saturate_u` | `0x6a`| - | -| `i16x8.sub` | `0x6b`| - | -| `i16x8.sub_saturate_s` | `0x6c`| - | -| `i16x8.sub_saturate_u` | `0x6d`| - | -| `i16x8.mul` | `0x6e`| - | -| `i16x8.min_s` | `0x6f`| - | -| `i16x8.min_u` | `0x70`| - | -| `i16x8.max_s` | `0x71`| - | -| `i16x8.max_u` | `0x72`| - | -| `i32x4.neg` | `0x73`| - | -| `i32x4.any_true` | `0x74`| - | -| `i32x4.all_true` | `0x75`| - | -| `i32x4.shl` | `0x76`| - | -| `i32x4.shr_s` | `0x77`| - | -| `i32x4.shr_u` | `0x78`| - | -| `i32x4.add` | `0x79`| - | -| `i32x4.sub` | `0x7c`| - | -| `i32x4.mul` | `0x7f`| - | -| `i32x4.min_s` | `0x80`| - | -| `i32x4.min_u` | `0x81`| - | -| `i32x4.max_s` | `0x82`| - | -| `i32x4.max_u` | `0x83`| - | -| `i64x2.neg` | `0x84`| - | -| `i64x2.shl` | `0x87`| - | -| `i64x2.shr_s` | `0x88`| - | -| `i64x2.shr_u` | `0x89`| - | -| `i64x2.add` | `0x8a`| - | -| `i64x2.sub` | `0x8d`| - | -| `i64x2.mul` | `0x90`| - | -| `f32x4.abs` | `0x95`| - | -| `f32x4.neg` | `0x96`| - | -| `f32x4.sqrt` | `0x97`| - | -| `f32x4.add` | `0x9a`| - | -| `f32x4.sub` | `0x9b`| - | -| `f32x4.mul` | `0x9c`| - | -| `f32x4.div` | `0x9d`| - | -| `f32x4.min` | `0x9e`| - | -| `f32x4.max` | `0x9f`| - | -| `f64x2.abs` | `0xa0`| - | -| `f64x2.neg` | `0xa1`| - | -| `f64x2.sqrt` | `0xa2`| - | -| `f64x2.add` | `0xa5`| - | -| `f64x2.sub` | `0xa6`| - | -| `f64x2.mul` | `0xa7`| - | -| `f64x2.div` | `0xa8`| - | -| `f64x2.min` | `0xa9`| - | -| `f64x2.max` | `0xaa`| - | -| `i32x4.trunc_sat_f32x4_s` | `0xab`| - | -| `i32x4.trunc_sat_f32x4_u` | `0xac`| - | -| `f32x4.convert_i32x4_s` | `0xaf`| - | -| `f32x4.convert_i32x4_u` | `0xb0`| - | -| `v8x16.swizzle` | `0xc0`| - | -| `v8x16.shuffle` | `0xc1`| s:LaneIdx32[16] | -| `v8x16.load_splat` | `0xc2`| - | -| `v16x8.load_splat` | `0xc3`| - | -| `v32x4.load_splat` | `0xc4`| - | -| `v64x2.load_splat` | `0xc5`| - | -| `i8x16.narrow_i16x8_s` | `0xc6`| - | -| `i8x16.narrow_i16x8_u` | `0xc7`| - | -| `i16x8.narrow_i32x4_s` | `0xc8`| - | -| `i16x8.narrow_i32x4_u` | `0xc9`| - | -| `i16x8.widen_low_i8x16_s` | `0xca`| - | -| `i16x8.widen_high_i8x16_s` | `0xcb`| - | -| `i16x8.widen_low_i8x16_u` | `0xcc`| - | -| `i16x8.widen_high_i8x16_u` | `0xcd`| - | -| `i32x4.widen_low_i16x8_s` | `0xce`| - | -| `i32x4.widen_high_i16x8_s` | `0xcf`| - | -| `i32x4.widen_low_i16x8_u` | `0xd0`| - | -| `i32x4.widen_high_i16x8_u` | `0xd1`| - | -| `i16x8.load8x8_s` | `0xd2`| m:memarg | -| `i16x8.load8x8_u` | `0xd3`| m:memarg | -| `i32x4.load16x4_s` | `0xd4`| m:memarg | -| `i32x4.load16x4_u` | `0xd5`| m:memarg | -| `i64x2.load32x2_s` | `0xd6`| m:memarg | -| `i64x2.load32x2_u` | `0xd7`| m:memarg | -| `v128.andnot` | `0xd8`| - | -| `i8x16.avgr_u` | `0xd9`| | -| `i16x8.avgr_u` | `0xda`| | -| `i8x16.abs` | `0xe1`| - | -| `i16x8.abs` | `0xe2`| - | -| `i32x4.abs` | `0xe3`| - | +| `i16x8.load8x8_s` | `0x01`| m:memarg | +| `i16x8.load8x8_u` | `0x02`| m:memarg | +| `i32x4.load16x4_s` | `0x03`| m:memarg | +| `i32x4.load16x4_u` | `0x04`| m:memarg | +| `i64x2.load32x2_s` | `0x05`| m:memarg | +| `i64x2.load32x2_u` | `0x06`| m:memarg | +| `v8x16.load_splat` | `0x07`| m:memarg | +| `v16x8.load_splat` | `0x08`| m:memarg | +| `v32x4.load_splat` | `0x09`| m:memarg | +| `v64x2.load_splat` | `0x0a`| m:memarg | +| `v128.store` | `0x0b`| m:memarg | +| `v128.const` | `0x0c`| i:ImmByte[16] | +| `v8x16.swizzle` | `0x0d`| - | +| `v8x16.shuffle` | `0x0e`| s:LaneIdx32[16] | +| `i8x16.splat` | `0x0f`| - | +| `i16x8.splat` | `0x10`| - | +| `i32x4.splat` | `0x11`| - | +| `i64x2.splat` | `0x12`| - | +| `f32x4.splat` | `0x13`| - | +| `f64x2.splat` | `0x14`| - | +| `i8x16.extract_lane_s` | `0x15`| i:LaneIdx16 | +| `i8x16.extract_lane_u` | `0x16`| i:LaneIdx16 | +| `i8x16.replace_lane` | `0x17`| i:LaneIdx16 | +| `i16x8.extract_lane_s` | `0x18`| i:LaneIdx8 | +| `i16x8.extract_lane_u` | `0x19`| i:LaneIdx8 | +| `i16x8.replace_lane` | `0x1a`| i:LaneIdx8 | +| `i32x4.extract_lane` | `0x1b`| i:LaneIdx4 | +| `i32x4.replace_lane` | `0x1c`| i:LaneIdx4 | +| `i64x2.extract_lane` | `0x1d`| i:LaneIdx2 | +| `i64x2.replace_lane` | `0x1e`| i:LaneIdx2 | +| `f32x4.extract_lane` | `0x1f`| i:LaneIdx4 | +| `f32x4.replace_lane` | `0x20`| i:LaneIdx4 | +| `f64x2.extract_lane` | `0x21`| i:LaneIdx2 | +| `f64x2.replace_lane` | `0x22`| i:LaneIdx2 | +| `i8x16.eq` | `0x23`| - | +| `i8x16.ne` | `0x24`| - | +| `i8x16.lt_s` | `0x25`| - | +| `i8x16.lt_u` | `0x26`| - | +| `i8x16.gt_s` | `0x27`| - | +| `i8x16.gt_u` | `0x28`| - | +| `i8x16.le_s` | `0x29`| - | +| `i8x16.le_u` | `0x2a`| - | +| `i8x16.ge_s` | `0x2b`| - | +| `i8x16.ge_u` | `0x2c`| - | +| `i16x8.eq` | `0x2d`| - | +| `i16x8.ne` | `0x2e`| - | +| `i16x8.lt_s` | `0x2f`| - | +| `i16x8.lt_u` | `0x30`| - | +| `i16x8.gt_s` | `0x31`| - | +| `i16x8.gt_u` | `0x32`| - | +| `i16x8.le_s` | `0x33`| - | +| `i16x8.le_u` | `0x34`| - | +| `i16x8.ge_s` | `0x35`| - | +| `i16x8.ge_u` | `0x36`| - | +| `i32x4.eq` | `0x37`| - | +| `i32x4.ne` | `0x38`| - | +| `i32x4.lt_s` | `0x39`| - | +| `i32x4.lt_u` | `0x3a`| - | +| `i32x4.gt_s` | `0x3b`| - | +| `i32x4.gt_u` | `0x3c`| - | +| `i32x4.le_s` | `0x3d`| - | +| `i32x4.le_u` | `0x3e`| - | +| `i32x4.ge_s` | `0x3f`| - | +| `i32x4.ge_u` | `0x40`| - | +| `f32x4.eq` | `0x41`| - | +| `f32x4.ne` | `0x42`| - | +| `f32x4.lt` | `0x43`| - | +| `f32x4.gt` | `0x44`| - | +| `f32x4.le` | `0x45`| - | +| `f32x4.ge` | `0x46`| - | +| `f64x2.eq` | `0x47`| - | +| `f64x2.ne` | `0x48`| - | +| `f64x2.lt` | `0x49`| - | +| `f64x2.gt` | `0x4a`| - | +| `f64x2.le` | `0x4b`| - | +| `f64x2.ge` | `0x4c`| - | +| `v128.not` | `0x4d`| - | +| `v128.and` | `0x4e`| - | +| `v128.andnot` | `0x4f`| - | +| `v128.or` | `0x50`| - | +| `v128.xor` | `0x51`| - | +| `v128.bitselect` | `0x52`| - | +| `i8x16.abs` | `0x60`| - | +| `i8x16.neg` | `0x61`| - | +| `i8x16.any_true` | `0x62`| - | +| `i8x16.all_true` | `0x63`| - | +| `i8x16.narrow_i16x8_s` | `0x65`| - | +| `i8x16.narrow_i16x8_u` | `0x66`| - | +| `i8x16.shl` | `0x6b`| - | +| `i8x16.shr_s` | `0x6c`| - | +| `i8x16.shr_u` | `0x6d`| - | +| `i8x16.add` | `0x6e`| - | +| `i8x16.add_saturate_s` | `0x6f`| - | +| `i8x16.add_saturate_u` | `0x70`| - | +| `i8x16.sub` | `0x71`| - | +| `i8x16.sub_saturate_s` | `0x72`| - | +| `i8x16.sub_saturate_u` | `0x73`| - | +| `i8x16.min_s` | `0x76`| - | +| `i8x16.min_u` | `0x77`| - | +| `i8x16.max_s` | `0x78`| - | +| `i8x16.max_u` | `0x79`| - | +| `i8x16.avgr_u` | `0x7b`| - | +| `i16x8.abs` | `0x80`| - | +| `i16x8.neg` | `0x81`| - | +| `i16x8.any_true` | `0x82`| - | +| `i16x8.all_true` | `0x83`| - | +| `i16x8.narrow_i32x4_s` | `0x85`| - | +| `i16x8.narrow_i32x4_u` | `0x86`| - | +| `i16x8.widen_low_i8x16_s` | `0x87`| - | +| `i16x8.widen_high_i8x16_s` | `0x88`| - | +| `i16x8.widen_low_i8x16_u` | `0x89`| - | +| `i16x8.widen_high_i8x16_u` | `0x8a`| - | +| `i16x8.shl` | `0x8b`| - | +| `i16x8.shr_s` | `0x8c`| - | +| `i16x8.shr_u` | `0x8d`| - | +| `i16x8.add` | `0x8e`| - | +| `i16x8.add_saturate_s` | `0x8f`| - | +| `i16x8.add_saturate_u` | `0x90`| - | +| `i16x8.sub` | `0x91`| - | +| `i16x8.sub_saturate_s` | `0x92`| - | +| `i16x8.sub_saturate_u` | `0x93`| - | +| `i16x8.mul` | `0x95`| - | +| `i16x8.min_s` | `0x96`| - | +| `i16x8.min_u` | `0x97`| - | +| `i16x8.max_s` | `0x98`| - | +| `i16x8.max_u` | `0x99`| - | +| `i16x8.avgr_u` | `0x9b`| | +| `i32x4.abs` | `0xa0`| - | +| `i32x4.neg` | `0xa1`| - | +| `i32x4.any_true` | `0xa2`| - | +| `i32x4.all_true` | `0xa3`| - | +| `i32x4.widen_low_i16x8_s` | `0xa7`| - | +| `i32x4.widen_high_i16x8_s` | `0xa8`| - | +| `i32x4.widen_low_i16x8_u` | `0xa9`| - | +| `i32x4.widen_high_i16x8_u` | `0xaa`| - | +| `i32x4.shl` | `0xab`| - | +| `i32x4.shr_s` | `0xac`| - | +| `i32x4.shr_u` | `0xad`| - | +| `i32x4.add` | `0xae`| - | +| `i32x4.sub` | `0xb1`| - | +| `i32x4.mul` | `0xb5`| - | +| `i32x4.min_s` | `0xb6`| - | +| `i32x4.min_u` | `0xb7`| - | +| `i32x4.max_s` | `0xb8`| - | +| `i32x4.max_u` | `0xb9`| - | +| `i64x2.neg` | `0xc1`| - | +| `i64x2.shl` | `0xcb`| - | +| `i64x2.shr_s` | `0xcc`| - | +| `i64x2.shr_u` | `0xcd`| - | +| `i64x2.add` | `0xce`| - | +| `i64x2.sub` | `0xd1`| - | +| `i64x2.mul` | `0xd5`| - | +| `f32x4.abs` | `0xe0`| - | +| `f32x4.neg` | `0xe1`| - | +| `f32x4.sqrt` | `0xe3`| - | +| `f32x4.add` | `0xe4`| - | +| `f32x4.sub` | `0xe5`| - | +| `f32x4.mul` | `0xe6`| - | +| `f32x4.div` | `0xe7`| - | +| `f32x4.min` | `0xe8`| - | +| `f32x4.max` | `0xe9`| - | +| `f64x2.abs` | `0xec`| - | +| `f64x2.neg` | `0xed`| - | +| `f64x2.sqrt` | `0xef`| - | +| `f64x2.add` | `0xf0`| - | +| `f64x2.sub` | `0xf1`| - | +| `f64x2.mul` | `0xf2`| - | +| `f64x2.div` | `0xf3`| - | +| `f64x2.min` | `0xf4`| - | +| `f64x2.max` | `0xf5`| - | +| `i32x4.trunc_sat_f32x4_s` | `0xf8`| - | +| `i32x4.trunc_sat_f32x4_u` | `0xf9`| - | +| `f32x4.convert_i32x4_s` | `0xfa`| - | +| `f32x4.convert_i32x4_u` | `0xfb`| - | diff --git a/proposals/simd/ImplementationStatus.md b/proposals/simd/ImplementationStatus.md index 58444f0c6..65ae4c67f 100644 --- a/proposals/simd/ImplementationStatus.md +++ b/proposals/simd/ImplementationStatus.md @@ -1,185 +1,185 @@ -| Instruction | LLVM[1] | V8[2] | WAVM[3] | ChakraCore[4] | -| ---------------------------|---------------------------|-----------------------|--------------------|--------------------| -| `v128.load` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `v128.store` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `v128.const` | `-munimplemented-simd128` | | :heavy_check_mark: | :heavy_check_mark: | -| `i8x16.splat` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `v8x16.load_splat` | `-munimplemented-simd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i8x16.extract_lane_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i8x16.extract_lane_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i8x16.replace_lane` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i16x8.splat` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `v16x8.load_splat` | `-munimplemented-simd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i16x8.extract_lane_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i16x8.extract_lane_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i16x8.replace_lane` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i32x4.splat` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `v32x4.load_splat` | `-munimplemented-simd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i32x4.extract_lane` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i32x4.replace_lane` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i64x2.splat` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i64x2.extract_lane` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i64x2.replace_lane` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f32x4.splat` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f32x4.extract_lane` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f32x4.replace_lane` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f64x2.splat` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `v64x2.load_splat` | `-munimplemented-simd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `f64x2.extract_lane` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f64x2.replace_lane` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i8x16.eq` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i8x16.ne` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i8x16.lt_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i8x16.lt_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i8x16.gt_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i8x16.gt_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i8x16.le_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i8x16.le_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i8x16.ge_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i8x16.ge_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i16x8.eq` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i16x8.ne` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i16x8.lt_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i16x8.lt_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i16x8.gt_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i16x8.gt_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i16x8.le_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i16x8.le_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i16x8.ge_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i16x8.ge_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i32x4.eq` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i32x4.ne` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i32x4.lt_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i32x4.lt_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i32x4.gt_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i32x4.gt_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i32x4.le_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i32x4.le_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i32x4.ge_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i32x4.ge_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f32x4.eq` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f32x4.ne` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f32x4.lt` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f32x4.gt` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f32x4.le` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f32x4.ge` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f64x2.eq` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f64x2.ne` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f64x2.lt` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f64x2.gt` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f64x2.le` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f64x2.ge` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `v128.not` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `v128.and` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `v128.andnot` | `-munimplemented-simd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `v128.or` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `v128.xor` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `v128.bitselect` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i8x16.neg` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i8x16.any_true` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i8x16.all_true` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i8x16.shl` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i8x16.shr_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i8x16.shr_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i8x16.add` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i8x16.add_saturate_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i8x16.add_saturate_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i8x16.sub` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i8x16.sub_saturate_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i8x16.sub_saturate_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i8x16.min_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i8x16.min_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i8x16.max_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i8x16.max_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i8x16.avgr_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i8x16.abs` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i16x8.neg` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i16x8.any_true` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i16x8.all_true` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i16x8.shl` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i16x8.shr_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i16x8.shr_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i16x8.add` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i16x8.add_saturate_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i16x8.add_saturate_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i16x8.sub` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i16x8.sub_saturate_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i16x8.sub_saturate_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i16x8.mul` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i16x8.min_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i16x8.min_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i16x8.max_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i16x8.max_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i16x8.avgr_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i16x8.abs` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i32x4.neg` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i32x4.any_true` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i32x4.all_true` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i32x4.shl` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i32x4.shr_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i32x4.shr_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i32x4.add` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i32x4.sub` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i32x4.mul` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i32x4.min_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i32x4.min_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i32x4.max_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i32x4.max_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i32x4.abs` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i64x2.neg` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i64x2.shl` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i64x2.shr_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i64x2.shr_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i64x2.add` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i64x2.sub` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i64x2.mul` | | :heavy_check_mark: | :heavy_check_mark: | | -| `f32x4.abs` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f32x4.neg` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f32x4.sqrt` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f32x4.add` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f32x4.sub` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f32x4.mul` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f32x4.div` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f32x4.min` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f32x4.max` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f64x2.abs` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f64x2.neg` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f64x2.sqrt` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f64x2.add` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f64x2.sub` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f64x2.mul` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f64x2.div` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f64x2.min` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f64x2.max` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i32x4.trunc_sat_f32x4_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i32x4.trunc_sat_f32x4_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f32x4.convert_i32x4_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `f32x4.convert_i32x4_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `v8x16.swizzle` | `-munimplemented-simd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `v8x16.shuffle` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| `i16x8.load8x8_s` | `-munimplemented-simd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i16x8.load8x8_u` | `-munimplemented-simd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i32x4.load16x4_s` | `-munimplemented-simd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i32x4.load16x4_u` | `-munimplemented-simd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i64x2.load32x2_s` | `-munimplemented-simd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i64x2.load32x2_u` | `-munimplemented-simd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i8x16.narrow_i16x8_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i8x16.narrow_i16x8_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i16x8.narrow_i32x4_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i16x8.narrow_i32x4_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i16x8.widen_low_i8x16_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i16x8.widen_high_i8x16_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i16x8.widen_low_i8x16_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i16x8.widen_high_i8x16_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i32x4.widen_low_i16x8_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i32x4.widen_high_i16x8_s` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i32x4.widen_low_i16x8_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | | -| `i32x4.widen_high_i16x8_u` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | | +| Instruction | LLVM[1] | V8[2] | WAVM[3] | ChakraCore[4] | +| ---------------------------|---------------------------|--------------------|--------------------|--------------------| +| `v128.load` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.load8x8_s` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.load8x8_u` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.load16x4_s` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.load16x4_u` | `-msimd128` | :heavy_check_mark: | | | +| `i64x2.load32x2_s` | `-msimd128` | :heavy_check_mark: | | | +| `i64x2.load32x2_u` | `-msimd128` | :heavy_check_mark: | | | +| `v8x16.load_splat` | `-msimd128` | :heavy_check_mark: | | | +| `v16x8.load_splat` | `-msimd128` | :heavy_check_mark: | | | +| `v32x4.load_splat` | `-msimd128` | :heavy_check_mark: | | | +| `v64x2.load_splat` | `-msimd128` | :heavy_check_mark: | | | +| `v128.store` | `-msimd128` | :heavy_check_mark: | | | +| `v128.const` | `-munimplemented-simd128` | | | | +| `v8x16.shuffle` | `-msimd128` | :heavy_check_mark: | | | +| `v8x16.swizzle` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.splat` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.splat` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.splat` | `-msimd128` | :heavy_check_mark: | | | +| `i64x2.splat` | `-msimd128` | :heavy_check_mark: | | | +| `f32x4.splat` | `-msimd128` | :heavy_check_mark: | | | +| `f64x2.splat` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.extract_lane_s` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.extract_lane_u` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.replace_lane` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.extract_lane_s` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.extract_lane_u` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.replace_lane` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.extract_lane` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.replace_lane` | `-msimd128` | :heavy_check_mark: | | | +| `i64x2.extract_lane` | `-msimd128` | :heavy_check_mark: | | | +| `i64x2.replace_lane` | `-msimd128` | :heavy_check_mark: | | | +| `f32x4.extract_lane` | `-msimd128` | :heavy_check_mark: | | | +| `f32x4.replace_lane` | `-msimd128` | :heavy_check_mark: | | | +| `f64x2.extract_lane` | `-msimd128` | :heavy_check_mark: | | | +| `f64x2.replace_lane` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.eq` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.ne` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.lt_s` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.lt_u` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.gt_s` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.gt_u` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.le_s` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.le_u` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.ge_s` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.ge_u` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.eq` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.ne` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.lt_s` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.lt_u` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.gt_s` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.gt_u` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.le_s` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.le_u` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.ge_s` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.ge_u` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.eq` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.ne` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.lt_s` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.lt_u` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.gt_s` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.gt_u` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.le_s` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.le_u` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.ge_s` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.ge_u` | `-msimd128` | :heavy_check_mark: | | | +| `f32x4.eq` | `-msimd128` | :heavy_check_mark: | | | +| `f32x4.ne` | `-msimd128` | :heavy_check_mark: | | | +| `f32x4.lt` | `-msimd128` | :heavy_check_mark: | | | +| `f32x4.gt` | `-msimd128` | :heavy_check_mark: | | | +| `f32x4.le` | `-msimd128` | :heavy_check_mark: | | | +| `f32x4.ge` | `-msimd128` | :heavy_check_mark: | | | +| `f64x2.eq` | `-msimd128` | :heavy_check_mark: | | | +| `f64x2.ne` | `-msimd128` | :heavy_check_mark: | | | +| `f64x2.lt` | `-msimd128` | :heavy_check_mark: | | | +| `f64x2.gt` | `-msimd128` | :heavy_check_mark: | | | +| `f64x2.le` | `-msimd128` | :heavy_check_mark: | | | +| `f64x2.ge` | `-msimd128` | :heavy_check_mark: | | | +| `v128.not` | `-msimd128` | :heavy_check_mark: | | | +| `v128.and` | `-msimd128` | :heavy_check_mark: | | | +| `v128.andnot` | `-msimd128` | :heavy_check_mark: | | | +| `v128.or` | `-msimd128` | :heavy_check_mark: | | | +| `v128.xor` | `-msimd128` | :heavy_check_mark: | | | +| `v128.bitselect` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.abs` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.neg` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.any_true` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.all_true` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.narrow_i16x8_s` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.narrow_i16x8_u` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.shl` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.shr_s` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.shr_u` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.add` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.add_saturate_s` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.add_saturate_u` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.sub` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.sub_saturate_s` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.sub_saturate_u` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.min_s` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.min_u` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.max_s` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.max_u` | `-msimd128` | :heavy_check_mark: | | | +| `i8x16.avgr_u` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.abs` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.neg` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.any_true` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.all_true` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.narrow_i32x4_s` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.narrow_i32x4_u` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.widen_low_i8x16_s` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.widen_high_i8x16_s` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.widen_low_i8x16_u` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.widen_high_i8x16_u` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.shl` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.shr_s` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.shr_u` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.add` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.add_saturate_s` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.add_saturate_u` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.sub` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.sub_saturate_s` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.sub_saturate_u` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.mul` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.min_s` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.min_u` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.max_s` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.max_u` | `-msimd128` | :heavy_check_mark: | | | +| `i16x8.avgr_u` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.abs` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.neg` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.any_true` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.all_true` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.widen_low_i16x8_s` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.widen_high_i16x8_s` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.widen_low_i16x8_u` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.widen_high_i16x8_u` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.shl` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.shr_s` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.shr_u` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.add` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.sub` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.mul` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.min_s` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.min_u` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.max_s` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.max_u` | `-msimd128` | :heavy_check_mark: | | | +| `i64x2.neg` | `-msimd128` | :heavy_check_mark: | | | +| `i64x2.shl` | `-msimd128` | :heavy_check_mark: | | | +| `i64x2.shr_s` | `-msimd128` | :heavy_check_mark: | | | +| `i64x2.shr_u` | `-msimd128` | :heavy_check_mark: | | | +| `i64x2.add` | `-msimd128` | :heavy_check_mark: | | | +| `i64x2.sub` | `-msimd128` | :heavy_check_mark: | | | +| `i64x2.mul` | `-msimd128` | :heavy_check_mark: | | | +| `f32x4.abs` | `-msimd128` | :heavy_check_mark: | | | +| `f32x4.neg` | `-msimd128` | :heavy_check_mark: | | | +| `f32x4.sqrt` | `-msimd128` | :heavy_check_mark: | | | +| `f32x4.add` | `-msimd128` | :heavy_check_mark: | | | +| `f32x4.sub` | `-msimd128` | :heavy_check_mark: | | | +| `f32x4.mul` | `-msimd128` | :heavy_check_mark: | | | +| `f32x4.div` | `-msimd128` | :heavy_check_mark: | | | +| `f32x4.min` | `-msimd128` | :heavy_check_mark: | | | +| `f32x4.max` | `-msimd128` | :heavy_check_mark: | | | +| `f64x2.abs` | `-msimd128` | :heavy_check_mark: | | | +| `f64x2.neg` | `-msimd128` | :heavy_check_mark: | | | +| `f64x2.sqrt` | `-msimd128` | :heavy_check_mark: | | | +| `f64x2.add` | `-msimd128` | :heavy_check_mark: | | | +| `f64x2.sub` | `-msimd128` | :heavy_check_mark: | | | +| `f64x2.mul` | `-msimd128` | :heavy_check_mark: | | | +| `f64x2.div` | `-msimd128` | :heavy_check_mark: | | | +| `f64x2.min` | `-msimd128` | :heavy_check_mark: | | | +| `f64x2.max` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.trunc_sat_f32x4_s` | `-msimd128` | :heavy_check_mark: | | | +| `i32x4.trunc_sat_f32x4_u` | `-msimd128` | :heavy_check_mark: | | | +| `f32x4.convert_i32x4_s` | `-msimd128` | :heavy_check_mark: | | | +| `f32x4.convert_i32x4_u` | `-msimd128` | :heavy_check_mark: | | | -[1] Tip of tree LLVM as of May 6, 2020 +[1] Tip of tree LLVM as of May 20, 2020 -[2] Tested on V8 8.4.272. Requires flag `--experimental-wasm-simd` +[2] V8 8.4.268. Requires flag `--experimental-wasm-simd` -[3] Tip of tree WAVM as of Feb 16, 2020. Requires flag `--enable simd` +[3] Not known to be updated after latest renumbering. Requires flag `--enable simd` -[4] Requires (case-insensitive) flag `-wasmsimd` +[4] Not known to be updated after latest renumbering. Requires (case-insensitive) flag `-wasmsimd` From 31f9e5c15345892ff171fb1f85777f91d3ff8e37 Mon Sep 17 00:00:00 2001 From: Deepti Gandluri Date: Wed, 20 May 2020 15:18:12 -0700 Subject: [PATCH 7/8] Update simd_const.wast (#233) --- test/core/simd/simd_const.wast | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/test/core/simd/simd_const.wast b/test/core/simd/simd_const.wast index 41fb608d8..8080cfb0f 100644 --- a/test/core/simd/simd_const.wast +++ b/test/core/simd/simd_const.wast @@ -1571,7 +1571,7 @@ "\07\0f\01\0b" ;; export section "\70\61\72\73\65\5f\69\38\78\31\36\00\00" ;; export name (parse_i8x16) "\0a\16\01" ;; code section - "\14\00\fd\02" ;; func body + "\14\00\fd\0c" ;; func body "\00\00\00\00" ;; data lane 0~3 (0, 0, 0, 0) "\80\80\80\80" ;; data lane 4~7 (-128, -128, -128, -128) "\ff\ff\ff\ff" ;; data lane 8~11 (0xff, 0xff, 0xff, 0xff) @@ -1588,7 +1588,7 @@ "\07\0f\01\0b" ;; export section "\70\61\72\73\65\5f\69\31\36\78\38\00\00" ;; export name (parse_i16x8) "\0a\16\01" ;; code section - "\14\00\fd\02" ;; func body + "\14\00\fd\0c" ;; func body "\00\00\00\00" ;; data lane 0, 1 (0, 0) "\00\80\00\80" ;; data lane 2, 3 (-32768, -32768) "\ff\ff\ff\ff" ;; data lane 4, 5 (65535, 65535) @@ -1605,7 +1605,7 @@ "\07\0f\01\0b" ;; export section "\70\61\72\73\65\5f\69\33\32\78\34\00\00" ;; export name (parse_i32x4) "\0a\16\01" ;; code section - "\14\00\fd\02" ;; func body + "\14\00\fd\0c" ;; func body "\d1\ff\ff\ff" ;; data lane 0 (4294967249) "\d1\ff\ff\ff" ;; data lane 1 (4294967249) "\d1\ff\ff\ff" ;; data lane 2 (4294967249) @@ -1622,7 +1622,7 @@ "\07\0f\01\0b" ;; export section "\70\61\72\73\65\5f\69\36\34\78\32\00\00" ;; export name (parse_i64x2) "\0a\16\01" ;; code section - "\14\00\fd\02" ;; func body + "\14\00\fd\0c" ;; func body "\ff\ff\ff\ff\ff\ff\ff\7f" ;; data lane 0 (9223372036854775807) "\ff\ff\ff\ff\ff\ff\ff\7f" ;; data lane 1 (9223372036854775807) "\0b" ;; end @@ -1639,7 +1639,7 @@ "\07\0f\01\0b" ;; export section "\70\61\72\73\65\5f\66\33\32\78\34\00\00" ;; export name (parse_f32x4) "\0a\16\01" ;; code section - "\14\00\fd\02" ;; func body + "\14\00\fd\0c" ;; func body "\00\00\80\4f" ;; data lane 0 (4294967249) "\00\00\80\4f" ;; data lane 1 (4294967249) "\00\00\80\4f" ;; data lane 2 (4294967249) @@ -1656,9 +1656,9 @@ "\07\0f\01\0b" ;; export section "\70\61\72\73\65\5f\66\36\34\78\32\00\00" ;; export name (parse_f64x2) "\0a\16\01" ;; code section - "\14\00\fd\02" ;; func body + "\14\00\fd\0c" ;; func body "\ff\ff\ff\ff\ff\ff\ef\7f" ;; data lane 0 (0x1.fffffffffffffp+1023) "\ff\ff\ff\ff\ff\ff\ef\7f" ;; data lane 1 (0x1.fffffffffffffp+1023) "\0b" ;; end ) -(assert_return (invoke "parse_f64x2") (v128.const f64x2 0x1.fffffffffffffp+1023 0x1.fffffffffffffp+1023)) \ No newline at end of file +(assert_return (invoke "parse_f64x2") (v128.const f64x2 0x1.fffffffffffffp+1023 0x1.fffffffffffffp+1023)) From 60568d8a12525d6450b86d08ffb55e44751aa8fe Mon Sep 17 00:00:00 2001 From: Thomas Lively Date: Wed, 20 May 2020 16:41:54 -0700 Subject: [PATCH 8/8] Fix shuffle/swizzle mixup --- proposals/simd/BinarySIMD.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/proposals/simd/BinarySIMD.md b/proposals/simd/BinarySIMD.md index 232ee1a23..ab88336bc 100644 --- a/proposals/simd/BinarySIMD.md +++ b/proposals/simd/BinarySIMD.md @@ -40,8 +40,8 @@ The `v8x16.shuffle` instruction has 16 bytes after `simdop`. | `v64x2.load_splat` | `0x0a`| m:memarg | | `v128.store` | `0x0b`| m:memarg | | `v128.const` | `0x0c`| i:ImmByte[16] | -| `v8x16.swizzle` | `0x0d`| - | -| `v8x16.shuffle` | `0x0e`| s:LaneIdx32[16] | +| `v8x16.shuffle` | `0x0d`| s:LaneIdx32[16] | +| `v8x16.swizzle` | `0x0e`| - | | `i8x16.splat` | `0x0f`| - | | `i16x8.splat` | `0x10`| - | | `i32x4.splat` | `0x11`| - |