-
Notifications
You must be signed in to change notification settings - Fork 874
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
shift self unproven circuit #2728
Comments
The problem disappears if the |
You really do not want to run
If you leave out the |
Thank you @nakengelhardt I will test proposed solution over more cases. |
well some tests that where failing with |
It does look like there is a bug in |
As it turns out, #641 did not in fact fix anything, but instead disabled a necessary step in |
This reverts commit 08be796, reversing changes made to 38dbb44. This fixes YosysHQ#2728. PR YosysHQ#641 did not actually "fix" YosysHQ#639. The actual issue in YosysHQ#639 is not equiv_make, but assumptions in equiv_simple that are not true for the test case provided in YosysHQ#639.
This reverts commit 08be796, reversing changes made to 38dbb44. This fixes YosysHQ#2728. PR YosysHQ#641 did not actually "fix" YosysHQ#639. The actual issue in YosysHQ#639 is not equiv_make, but assumptions in equiv_simple that are not true for the test case provided in YosysHQ#639.
Steps to reproduce the issue
The following Verilog have:
ERROR: Found 12 unproven $equiv cells in 'equiv_status -assert'.
with itself.Yosys 0.9+3911 (git sha1 58a57551, clang 11.0.1 -fPIC -Os)
Expected behavior
to be equivalent with itself
ERROR: Found 12 unproven $equiv cells in 'equiv_status -assert'.
Actual behavior
not equivalent to itself
The text was updated successfully, but these errors were encountered: