The bootcode is hosted in this directory. An RTL/ASIC and FPGA SystemVerilog
boot ROMs are auto-generated from the compiled boot code. The autogenerated
ASIC boot ROM can be found under:
asic_autogen_rom.sv
fpga_autogen_rom.sv
It's size is currently 8KiB (32 x 2048 bits).
Currently there are 2 bits available to select the boot mode.
bootsel value |
Meaning |
|---|---|
| 2'h0 | zforth boot |
| 2'h1 | JTAG boot for openocd (busy loop) |
| 2'h2 | QSPI boot (read from flash and jump to entry) |
| 2'h3 | preloaded boot (jump to address in bootaddr register) |
Boot a zforth shell. Interaction over uart.
In this mode we just send the fabric controller into a busy loop. The debug module then can take it from there. It will sent a debug request interrupt that redirect the control flow of the core to the debug rom.
The core will issue a series of commands to fetch the elf from a flash module attached to qspi. Afterwards it will jump to the entry point (information is also in the flash image).
The cores will read the boot address register and directly jump there. This assumes that the elf image has been written to the L2 previously and the boot address is set correctly.
To compile the bootcode run make all.
Check the Makefile for features. You can disable bootmodes to shirnk the
bootrom.