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Commits on Jul 19, 2023

• Fix FIFO-related parameters to use DEPTH instead of ADDR_WIDTH

  alexforencich

  committedJul 19, 2023
  e7a2681

Commits on Jun 11, 2023

• Add I2C single reg module

  alexforencich

  committedJun 11, 2023
  4a41d47

Commits on Jun 22, 2021

• Add delay command

  alexforencich

  committedJun 22, 2021
  ad307a0

Commits on Jan 3, 2021

• Convert latching status bits to write 1 to clear

  alexforencich

  committedJan 3, 2021
  ca6688c

Commits on Jan 2, 2021

• Rename ports

  alexforencich

  committedJan 2, 2021
  d8a7f9f

• Rewrite resets

  alexforencich

  committedJan 2, 2021
  5ec6599

• Update FIFO

  alexforencich

  committedJan 2, 2021
  4eccd3d

Commits on May 28, 2019

• Update readme

  alexforencich

  committedMay 28, 2019
  b6ebb7d

• Add I2C slave AXI lite master module and testbench

  alexforencich

  committedMay 28, 2019
  0d8e224

• Add I2C slave wishbone master module and testbench

  alexforencich

  committedMay 28, 2019
  94bbc39

• Add I2C slave module and testbench

  alexforencich

  committedMay 28, 2019
  22212fa

Commits on May 13, 2019

• Add I2C master AXI lite wrapper module and testbench

  alexforencich

  committedMay 13, 2019
  4c1bb2c

• Add read data valid bit

  alexforencich

  committedMay 13, 2019
  840b912

• Remove race condition

  alexforencich

  committedMay 13, 2019
  3da782e

• Update AXI stream FIFO

  alexforencich

  committedMay 13, 2019
  fc25907

• Update wishbone model

  alexforencich

  committedMay 13, 2019
  5a1fd48

Commits on Jul 3, 2018

• Update AXI stream endpoint

  alexforencich

  committedJul 3, 2018
  0e7631a

Commits on Jun 14, 2018

• Update testbenches to use instances()

  alexforencich

  committedJun 14, 2018
  17b1f25

• Update axis_ep.py

  alexforencich

  committedJun 14, 2018
  a28eeae

Commits on May 31, 2017

• Fix assign

  alexforencich

  committedMay 31, 2017
  261d800

Commits on Feb 10, 2017

• Update documentation

  alexforencich

  committedFeb 10, 2017
  13788eb

Commits on Feb 9, 2017

• Add I2C master 26 bit wishbone slave wrapper module and testbench

  alexforencich

  committedFeb 9, 2017
  d24098d

• Add register documentation

  alexforencich

  committedFeb 9, 2017
  6b3d6b1

• Add nonexistent device test

  alexforencich

  committedFeb 9, 2017
  57111a8

• Add parameter to make prescale read-only

  alexforencich

  committedFeb 9, 2017
  e2496aa

• Check ACK bits in I2C master model

  alexforencich

  committedFeb 9, 2017
  499dbbd

Commits on Feb 8, 2017

• Happy new year

  alexforencich

  committedFeb 8, 2017
  e4dee90

Commits on Sep 12, 2016

• Update and rework endpoints, update testbenches

  alexforencich

  committedSep 12, 2016
  9e8c93e

Commits on Sep 7, 2016

• Update readme

  alexforencich

  committedSep 7, 2016
  46fedf6

• Add I2C master wishbone slave wrapper module and testbench

  alexforencich

  committedSep 7, 2016
  a9eff42

• Add AXI stream FIFO

  alexforencich

  committedSep 7, 2016
  e72c817

• Add Wishbone cosimulation endpoints

  alexforencich

  committedSep 7, 2016
  2b7cd48

• Update busy output to reflect PHY state

  alexforencich

  committedSep 7, 2016
  cf4e343

Commits on Aug 2, 2016

• Add explicit I2C stop command

  alexforencich

  committedAug 2, 2016
  36c0e9b

• Update readme

  alexforencich

  committedAug 2, 2016
  c229dcb

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