dram.cfg

//-size (bytes) 16777216
//-size (bytes) 33554432
-size (bytes) 134217728
//-size (bytes) 67108864
//-size (bytes) 1073741824

-block size (bytes) 64
-associativity 1
-read-write port 1
-exclusive read port 0
-exclusive write port 0
-single ended read ports 0
-UCA bank count 1
//-technology (u) 0.032
//-technology (u) 0.045
-technology (u) 0.068
//-technology (u) 0.078

# following three parameters are meaningful only for main memories
-page size (bits)  8192
-burst length 8
-internal prefetch width 8

# following parameter can have one of the five values -- (itrs-hp, itrs-lstp, itrs-lop, lp-dram, comm-dram)
-Data array cell type - "comm-dram"

# following parameter can have one of the three values -- (itrs-hp, itrs-lstp, itrs-lop)
-Data array peripheral type - "itrs-hp"

# following parameter can have one of the five values -- (itrs-hp, itrs-lstp, itrs-lop, lp-dram, comm-dram)
-Tag array cell type - "itrs-hp"

# following parameter can have one of the three values -- (itrs-hp, itrs-lstp, itrs-lop)
-Tag array peripheral type - "itrs-hp"

# Bus width include data bits and address bits required by the decoder
//-output/input bus width 512
-output/input bus width 64

-operating temperature (K) 350

-cache type "main memory"

# to model special structure like branch target buffers, directory, etc. 
# change the tag size parameter
# if you want cacti to calculate the tagbits, set the tag size to "default"
-tag size (b) "default"
//-tag size (b) 45

# fast - data and tag access happen in parallel
# sequential - data array is accessed after accessing the tag array
# normal - data array lookup and tag access happen in parallel
#          final data block is broadcasted in data array h-tree 
#          after getting the signal from the tag array
//-access mode (normal, sequential, fast) - "fast"
-access mode (normal, sequential, fast) - "normal"
//-access mode (normal, sequential, fast) - "sequential"

# DESIGN OBJECTIVE for UCA (or banks in NUCA)
//-design objective (weight delay, dynamic power, leakage power, cycle time, area) 100:100:0:0:0
-design objective (weight delay, dynamic power, leakage power, cycle time, area) 0:0:0:100:0
-deviate (delay, dynamic power, leakage power, cycle time, area) 20:100000:100000:100000:1000000
//-deviate (delay, dynamic power, leakage power, cycle time, area) 200:100000:100000:100000:20

-Optimize ED or ED^2 (ED, ED^2, NONE): "NONE"

-Cache model (NUCA, UCA)  - "UCA"

//-Wire signalling (fullswing, lowswing, default) - "default"
-Wire signalling (fullswing, lowswing, default) - "Global_10"

-Wire inside mat - "global"
//-Wire inside mat - "semi-global"
-Wire outside mat - "global"

-Interconnect projection - "conservative"
//-Interconnect projection - "aggressive"

-Add ECC - "true"

-Print level (DETAILED, CONCISE) - "DETAILED"

# for debugging
-Print input parameters - "true"
# force CACTI to model the cache with the 
# following Ndbl, Ndwl, Nspd, Ndsam,
# and Ndcm values
//-Force cache config - "true"
-Force cache config - "false"
-Ndwl 1
-Ndbl 1
-Nspd 0
-Ndcm 1
-Ndsam1 0
-Ndsam2 0

########### NUCA Params ############

# Objective for NUCA
-NUCAdesign objective (weight delay, dynamic power, leakage power, cycle time, area) 100:100:0:0:100
-NUCAdeviate (delay, dynamic power, leakage power, cycle time, area) 10:10000:10000:10000:10000

# Contention in network (which is a function of core count and cache level) is one of
# the critical factor used for deciding the optimal bank count value
# core count can be 4, 8, or 16
//-Core count 4
-Core count 8
//-Core count 16
-Cache level (L2/L3) - "L3"

# In order for CACTI to find the optimal NUCA bank value the following
# variable should be assigned 0.
-NUCA bank count 0