Don't vectorize if the vectorization width is 1

[simoll]

This is a reminder for the vectorization width == 1 corner case.

RV will run the full vectorization pipeline if the vectorization width is 1. Since the divergence analysis implicitly assumes that there are at least two threads per vector, this leads to inefficient code and even breakage in LLVM's x86 backend if gathers on <1 x T*> are emitted.

Solution: make the divergence analysis report all instructions as uniform if the vectorization width is 1 and copy the scalar instructions in RV's vector code backend.