From 2b217b603af444ecebc87c1277b5926c5f5232dc Mon Sep 17 00:00:00 2001 From: Henner Zeller Date: Tue, 4 Feb 2020 16:13:57 -0800 Subject: [PATCH] PR #177: Start a new line on genvar Fixes #151. GitHub PR https://github.com/google/verible/pull/177 Copybara import of the project: - 8b4632cff99166fb53f3b5fa2828712604714b7d Start a new line on genvar by Rafal Kapuscik Closes #177 PiperOrigin-RevId: 293252505 --- verilog/formatting/formatter_test.cc | 44 +++++++++++++++ verilog/formatting/tree_unwrapper.cc | 1 + verilog/formatting/tree_unwrapper_test.cc | 69 +++++++++++++++++++++++ 3 files changed, 114 insertions(+) diff --git a/verilog/formatting/formatter_test.cc b/verilog/formatting/formatter_test.cc index c0c26bc7c..64a09e13b 100644 --- a/verilog/formatting/formatter_test.cc +++ b/verilog/formatting/formatter_test.cc @@ -1082,6 +1082,50 @@ static const std::initializer_list kFormatterTestCases = { " end\n" "endmodule\n", }, + { + // standalone genvar statement + "module m ;" + "genvar f;" + "for(f=0; f0; g -- )begin " + "end endmodule", + "module m;\n" + " genvar f, g;\n" + " for (f = 0; f < N; f++) begin\n" + " end\n" + " for (g = N; g > 0; g--) begin\n" + " end\n" + "endmodule\n", + }, + { + // multiple genvar statements + "module m ;" + "genvar f;" + "genvar g;" + "for(f=0; f0; g -- )begin " + "end endmodule", + "module m;\n" + " genvar f;\n" + " genvar g;\n" + " for (f = 0; f < N; f++) begin\n" + " end\n" + " for (g = N; g > 0; g--) begin\n" + " end\n" + "endmodule\n", + }, { "module event_control ;" "always@ ( posedge clk )z<=y;" diff --git a/verilog/formatting/tree_unwrapper.cc b/verilog/formatting/tree_unwrapper.cc index 8c36e4572..75047c5de 100644 --- a/verilog/formatting/tree_unwrapper.cc +++ b/verilog/formatting/tree_unwrapper.cc @@ -593,6 +593,7 @@ void TreeUnwrapper::Visit(const verible::SyntaxTreeNode& node) { case NodeEnum::kParamDeclaration: case NodeEnum::kClockingDeclaration: case NodeEnum::kClockingItem: + case NodeEnum::kGenvarDeclaration: case NodeEnum::kDescriptionList: case NodeEnum::kForwardDeclaration: { VisitNewUnwrappedLine(node); diff --git a/verilog/formatting/tree_unwrapper_test.cc b/verilog/formatting/tree_unwrapper_test.cc index ff06dae75..9158becfd 100644 --- a/verilog/formatting/tree_unwrapper_test.cc +++ b/verilog/formatting/tree_unwrapper_test.cc @@ -1101,6 +1101,75 @@ const TreeUnwrapperTestData kUnwrapModuleTestCases[] = { L(0, {"endmodule"}), }, + { + "module with standalone genvar statement", + "module loop_standalone_genvar;\n" + "genvar i;" + "for (i=1;i0;--j) begin\n" + "end\n" + "endmodule", + ModuleHeader(0, L(0, {"module", "loop_multiarg_genvar", ";"})), + ModuleItemList( + 1, L(1, {"genvar", "i", ",", "j", ";"}), + LoopHeader(1, L(1, {"for", "("}), + ForSpec(3, L(3, {"i", "=", "1", ";"}), + L(3, {"i", "<", "N", ";"}), L(3, {"++", "i"})), + L(1, {")", "begin"})), + L(1, {"end"}), + LoopHeader(1, L(1, {"for", "("}), + ForSpec(3, L(3, {"j", "=", "N", ";"}), + L(3, {"j", ">", "0", ";"}), L(3, {"--", "j"})), + L(1, {")", "begin"})), + L(1, {"end"})), + L(0, {"endmodule"}), + }, + + { + "module with multiple genvar statements", + "module loop_multi_genvar;\n" + "genvar i;" + "genvar j;" + "for (i=1;i0;--j) begin\n" + "end\n" + "endmodule", + ModuleHeader(0, L(0, {"module", "loop_multi_genvar", ";"})), + ModuleItemList( + 1, L(1, {"genvar", "i", ";"}), L(1, {"genvar", "j", ";"}), + LoopHeader(1, L(1, {"for", "("}), + ForSpec(3, L(3, {"i", "=", "1", ";"}), + L(3, {"i", "<", "N", ";"}), L(3, {"++", "i"})), + L(1, {")", "begin"})), + L(1, {"end"}), + LoopHeader(1, L(1, {"for", "("}), + ForSpec(3, L(3, {"j", "=", "N", ";"}), + L(3, {"j", ">", "0", ";"}), L(3, {"--", "j"})), + L(1, {")", "begin"})), + L(1, {"end"})), + L(0, {"endmodule"}), + }, + { "module with multiple loop generate statements", "module loop_generates;\n"