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Describe the bug
Is it correct, that the preprocessor removes all spaces from defines?
To Reproduce
`define SVTEST(_NAME_) task automatic TEST_GITHUB(); `define SVTEST_END endtask module github_issue; `SVTEST(get_root) `SVTEST_END endmodule
Command to execute verible-verilog-preprocessor preprocess github.sv
verible-verilog-preprocessor preprocess github.sv
Actual behavior:
`defineSVTEST(_NAME_)task automatic TEST_GITHUB(); `defineSVTEST_ENDendtask module github_issue; taskautomaticTEST_GITHUB(); endtask endmodule
Expected behavior
I would expect that the spaces are preserved in define's after reading #1528.
`define SVTEST(_NAME_) task automatic TEST_GITHUB(); `define SVTEST_END endtask module github_issue; task automatic TEST_GITHUB(); endtask endmodule
The text was updated successfully, but these errors were encountered:
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Describe the bug
Is it correct, that the preprocessor removes all spaces from defines?
To Reproduce
Command to execute
verible-verilog-preprocessor preprocess github.sv
Actual behavior:
Expected behavior
I would expect that the spaces are preserved in define's after reading #1528.
The text was updated successfully, but these errors were encountered: