systemverilog interface module definitions can not be found

[bhappel-ciena]

A couple of questions first

• Visual Studio Code
• IDE version: 1.90.0
• What other SystemVerilog plugins are active alongside ?
• • mshr-h.veriloghdl - for hylighting
• • chipsalliance.verible - for verible with support for commandline args

---

What activity failed
(what functionality did not work as expected (e.g. Linting, Formatting, AUTO-expansion, go-to-definition, outline, hover,...)
go-to-definition of interfaces

Expectation
Goes to the definition in the workspace of the interface, just the same as modules.

What actually happened
"No definition found for interface"

Test case

If needed, include SystemVerilog sample file(s) that show the code you want to do an operation on

// Sample SystemVerilog file in case

interface something_if #() ();
endinterface

something_if #() my_instantiated_interface_if ();

Logfiles

export VERIBLE_LOGTHRESHOLD=0
code foo.sv

How to see the log output

• vscode: go to View -> Output, then choose Verible Language Server in the dropdown
• emacs: there is a buffer *verible-ls::stderr* that contains the log output
• kate: output is printed on the terminal

(paste log output here)

Platform: 'linux'
Using executable from path: verible-verilog-ls
Starting Language Server
Verible Verilog Language Server built at v0.0-3667-g88d12889
commandline: verible-verilog-ls --rules_config_search=true