diff --git a/verilog/parser/verilog.y b/verilog/parser/verilog.y
index 72162214b..5cff4b5fa 100644
--- a/verilog/parser/verilog.y
+++ b/verilog/parser/verilog.y
@@ -772,6 +772,8 @@ KeywordIdentifier
     { $$ = std::move($1); }
   | TK_discrete
     { $$ = std::move($1); }
+  | TK_analog
+    { $$ = std::move($1); }
   /* TK_sample is in SystemVerilog coverage_event */
   | TK_sample
     { $$ = std::move($1); }
diff --git a/verilog/parser/verilog_parser_unittest.cc b/verilog/parser/verilog_parser_unittest.cc
index 82ae75ec4..724cdf1bc 100644
--- a/verilog/parser/verilog_parser_unittest.cc
+++ b/verilog/parser/verilog_parser_unittest.cc
@@ -1770,6 +1770,7 @@ static constexpr ParserTestCaseArray kModuleTests = {
     // keyword tests
     "module keyword_identifiers;\n"
     "reg branch;  // branch is a Verilog-AMS keyword\n"
+    "reg analog;  // analog is a Verilog-AMS keyword\n"
     "input from;  // from is a Verilog-AMS keyword\n"
     "wire access;  // access is a Verilog-AMS keyword\n"
     "wire exclude;  // exclude is a Verilog-AMS keyword\n"