Outlining the state of programming languages for hardware design and to announce the first workshop on languages, tools, and techniques for accelerator design (co-located with ASPLOS): https://capra.cs.cornell.edu/latte21/
There has been a renewed interest in applying programming languages ideas to enable productive hardware design: Spatial [PLDI 18], Aetherling [PLDI 20], Dahlia [PLDI 20], Koika [PLDI 20], Calyx [ASPLOS 21], etc. Building such domain specific languages is an exciting area with the potential for a lot of innovation—from the design of type systems down to the interfaces for integrating hardware. This area also has a lot of unsolved challenges that the PL community is well positioned to solve: giving semantics to programs with physical constraints, building verified compilation tools, and building new abstractions that capture the complexity of design spaces for hardware accelerators.
I will provide a broad overview of space by drawing on published research as well as ongoing industry efforts.
Previous writing for broad audiences:
- Compiling for the Reconfigurable Future: https://rachitnigam.com/post/reconf-future/
- I'm the first author for two of the aforementioned papers in the area (Dahlia and Calyx).
If possible, I would like the blog post to be cross-published with the SIGARCH blog: https://www.sigarch.org/blog/