Please add topics/questions you'd like to have discussed during the workshop.
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Challenges in end-to-end compilation (from "PyTorch to FPGA")
- Meaningful error messages (What does "failed to route" mean for a C++ program)
- Compilation times (What does
-O0compilation look like?)
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Interface design and integration into larger Systems-on-Chip.
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Status and future of C based HLS tools
- What is preventing wider adoption?
- Are there any success areas?
- Is C the right abstraction for HLS tools?
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Discussion on the open-source LLVM front-end of Vitis HLS tool.
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Future of FPGAs as accelerators vs. other technologies (e.g. GPUs).
- How is HLS helping to popularise FPGAs? What still needs work? What comes after HLS?
- How will technologies such as HBM2 affect FPGA performance/adoption?
- Will "harder" concepts such as multi-FPGA, FPGA networking, and near-memory gain traction?
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FPGA overlays and encapsulating hardware programmability for software developers.
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For languages that generate verilog, what are the challenges involved in taking output from EDA tools and putting it back into the context of the original language.
- How should failing timing paths be presented?
- What should waveforms looks like?