{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":37792242,"defaultBranch":"master","name":"CoreFreq","ownerLogin":"cyring","currentUserCanPush":false,"isFork":false,"isEmpty":false,"createdAt":"2015-06-21T01:22:28.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/11563789?v=4","public":true,"private":false,"isOrgOwned":false},"refInfo":{"name":"","listCacheKey":"v0:1715799730.0","currentOid":""},"activityList":{"items":[{"before":"fc3fa800cbf9ac06157272ae6b000ad96dd9c597","after":"927ae0b9dd3f4bd35999b8f3c313a7a018aa59ee","ref":"refs/heads/develop","pushedAt":"2024-06-23T10:55:26.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"cyring","name":"CyrIng","path":"/cyring","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/11563789?s=80&v=4"},"commit":{"message":"[Intel] Mitigation mechanism: GDS_NO; RFDS_NO; MONITOR_MITG_NO\n* Intel SDM Documentation Changes","shortMessageHtmlLink":"[Intel] Mitigation mechanism: GDS_NO; RFDS_NO; MONITOR_MITG_NO"}},{"before":"7c8d354aeed79bcde59d2fcadbab899b60137a74","after":"fc3fa800cbf9ac06157272ae6b000ad96dd9c597","ref":"refs/heads/develop","pushedAt":"2024-06-22T17:40:51.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"cyring","name":"CyrIng","path":"/cyring","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/11563789?s=80&v=4"},"commit":{"message":"[AMD][Family 19h] PStateDef specification: Adding `VID[8]` bit 32\n* Specification of MSR `HW_PSTATE_STATUS`","shortMessageHtmlLink":"[AMD][Family 19h] PStateDef specification: Adding <code>VID[8]</code> bit 32"}},{"before":"8ce563e331678f1f878fb50482525860eaa69bd1","after":"7c8d354aeed79bcde59d2fcadbab899b60137a74","ref":"refs/heads/master","pushedAt":"2024-06-16T15:13:13.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"cyring","name":"CyrIng","path":"/cyring","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/11563789?s=80&v=4"},"commit":{"message":"[CR] Fix memory allocation in kernel pages for the SysGate","shortMessageHtmlLink":"[CR] Fix memory allocation in kernel pages for the SysGate"}},{"before":"e6d383a5ac9a3e415dbd8baccba732dc3cf5030a","after":"7c8d354aeed79bcde59d2fcadbab899b60137a74","ref":"refs/heads/develop","pushedAt":"2024-06-16T14:14:11.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"cyring","name":"CyrIng","path":"/cyring","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/11563789?s=80&v=4"},"commit":{"message":"[CR] Fix memory allocation in kernel pages for the SysGate","shortMessageHtmlLink":"[CR] Fix memory allocation in kernel pages for the SysGate"}},{"before":"8ce563e331678f1f878fb50482525860eaa69bd1","after":"e6d383a5ac9a3e415dbd8baccba732dc3cf5030a","ref":"refs/heads/develop","pushedAt":"2024-06-16T10:55:11.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"cyring","name":"CyrIng","path":"/cyring","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/11563789?s=80&v=4"},"commit":{"message":"[Build] Workaround to `musl` change in `basename` (#494)","shortMessageHtmlLink":"[Build] Workaround to <code>musl</code> change in <code>basename</code> (<a class=\"issue-link js-issue-link\" data-error-text=\"Failed to load title\" data-id=\"2341869344\" data-permission-text=\"Title is private\" data-url=\"https://github.com/cyring/CoreFreq/issues/494\" data-hovercard-type=\"issue\" data-hovercard-url=\"/cyring/CoreFreq/issues/494/hovercard\" href=\"https://github.com/cyring/CoreFreq/issues/494\">#494</a>)"}},{"before":"5b9dc1124a1d2d508396389036e1456edb9ffa2b","after":"8ce563e331678f1f878fb50482525860eaa69bd1","ref":"refs/heads/master","pushedAt":"2024-06-15T16:28:11.000Z","pushType":"push","commitsCount":3,"pusher":{"login":"cyring","name":"CyrIng","path":"/cyring","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/11563789?s=80&v=4"},"commit":{"message":"[CLI] Display the state of the Memory Management Unit (MMU)","shortMessageHtmlLink":"[CLI] Display the state of the Memory Management Unit (MMU)"}},{"before":"9a82942ccdd5df551c80eea895c4c0ace657bab4","after":"8ce563e331678f1f878fb50482525860eaa69bd1","ref":"refs/heads/develop","pushedAt":"2024-06-15T16:07:30.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"cyring","name":"CyrIng","path":"/cyring","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/11563789?s=80&v=4"},"commit":{"message":"[CLI] Display the state of the Memory Management Unit (MMU)","shortMessageHtmlLink":"[CLI] Display the state of the Memory Management Unit (MMU)"}},{"before":"d58f420aae68c990cc43e74be6fcbb39f2473366","after":"9a82942ccdd5df551c80eea895c4c0ace657bab4","ref":"refs/heads/develop","pushedAt":"2024-06-15T13:32:22.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"cyring","name":"CyrIng","path":"/cyring","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/11563789?s=80&v=4"},"commit":{"message":"[Kernel] Created `C2U_Enable` as a parameter alias of `C1U_Enable`","shortMessageHtmlLink":"[Kernel] Created <code>C2U_Enable</code> as a parameter alias of <code>C1U_Enable</code>"}},{"before":"5b9dc1124a1d2d508396389036e1456edb9ffa2b","after":"d58f420aae68c990cc43e74be6fcbb39f2473366","ref":"refs/heads/develop","pushedAt":"2024-06-15T07:46:32.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"cyring","name":"CyrIng","path":"/cyring","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/11563789?s=80&v=4"},"commit":{"message":"[CLI] State of Instruction Cache Unit `I$` and Data Cache Unit `D$`","shortMessageHtmlLink":"[CLI] State of Instruction Cache Unit <code>I$</code> and Data Cache Unit <code>D$</code>"}},{"before":"332dbdac52918ff5c3ca17ce315fd7ef92a40726","after":"5b9dc1124a1d2d508396389036e1456edb9ffa2b","ref":"refs/heads/master","pushedAt":"2024-06-09T17:16:28.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"cyring","name":"CyrIng","path":"/cyring","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/11563789?s=80&v=4"},"commit":{"message":"[Doc] `UI_RULER_MINIMUM` & `UI_RULER_MAXIMUM` Makefile macros","shortMessageHtmlLink":"[Doc] <code>UI_RULER_MINIMUM</code> &amp; <code>UI_RULER_MAXIMUM</code> Makefile macros"}},{"before":"9b644fd5097e7895ac9d92750984b923be071762","after":"5b9dc1124a1d2d508396389036e1456edb9ffa2b","ref":"refs/heads/develop","pushedAt":"2024-06-09T16:12:26.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"cyring","name":"CyrIng","path":"/cyring","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/11563789?s=80&v=4"},"commit":{"message":"[Doc] `UI_RULER_MINIMUM` & `UI_RULER_MAXIMUM` Makefile macros","shortMessageHtmlLink":"[Doc] <code>UI_RULER_MINIMUM</code> &amp; <code>UI_RULER_MAXIMUM</code> Makefile macros"}},{"before":"332dbdac52918ff5c3ca17ce315fd7ef92a40726","after":"9b644fd5097e7895ac9d92750984b923be071762","ref":"refs/heads/develop","pushedAt":"2024-06-09T09:34:59.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"cyring","name":"CyrIng","path":"/cyring","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/11563789?s=80&v=4"},"commit":{"message":"[CLI] `UI_RULER_MINIMUM` & `UI_RULER_MAXIMUM` building constraints","shortMessageHtmlLink":"[CLI] <code>UI_RULER_MINIMUM</code> &amp; <code>UI_RULER_MAXIMUM</code> building constraints"}},{"before":"71deb150abaa12ffad61edf0bd687dab2f05b194","after":"332dbdac52918ff5c3ca17ce315fd7ef92a40726","ref":"refs/heads/master","pushedAt":"2024-06-08T22:22:24.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"cyring","name":"CyrIng","path":"/cyring","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/11563789?s=80&v=4"},"commit":{"message":"Revert \"[CLI] Responsive ruler to architectural context\"\n\nThis reverts commit 4bc38d696fa739d7fcd7a8f542b8069a93bcbbc4.","shortMessageHtmlLink":"Revert \"[CLI] Responsive ruler to architectural context\""}},{"before":"c462e2f351fc03622018c90de2b02de91b32d985","after":"332dbdac52918ff5c3ca17ce315fd7ef92a40726","ref":"refs/heads/develop","pushedAt":"2024-06-08T20:58:33.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"cyring","name":"CyrIng","path":"/cyring","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/11563789?s=80&v=4"},"commit":{"message":"Revert \"[CLI] Responsive ruler to architectural context\"\n\nThis reverts commit 4bc38d696fa739d7fcd7a8f542b8069a93bcbbc4.","shortMessageHtmlLink":"Revert \"[CLI] Responsive ruler to architectural context\""}},{"before":"71deb150abaa12ffad61edf0bd687dab2f05b194","after":"c462e2f351fc03622018c90de2b02de91b32d985","ref":"refs/heads/develop","pushedAt":"2024-06-08T19:33:12.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"cyring","name":"CyrIng","path":"/cyring","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/11563789?s=80&v=4"},"commit":{"message":"[x86_64] AMD Boost and P-States redesigned","shortMessageHtmlLink":"[x86_64] AMD Boost and P-States redesigned"}},{"before":"3e136b3cb2b25d1eef6b23034d580f28aad9286c","after":"71deb150abaa12ffad61edf0bd687dab2f05b194","ref":"refs/heads/master","pushedAt":"2024-06-08T07:02:51.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"cyring","name":"CyrIng","path":"/cyring","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/11563789?s=80&v=4"},"commit":{"message":"[Intel][MTL] Fix CMD Stretch bit range width","shortMessageHtmlLink":"[Intel][MTL] Fix CMD Stretch bit range width"}},{"before":"b8a6c5e850841f265b474a6724d9d198dbd50a9b","after":"71deb150abaa12ffad61edf0bd687dab2f05b194","ref":"refs/heads/develop","pushedAt":"2024-06-08T06:05:29.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"cyring","name":"CyrIng","path":"/cyring","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/11563789?s=80&v=4"},"commit":{"message":"[Intel][MTL] Fix CMD Stretch bit range width","shortMessageHtmlLink":"[Intel][MTL] Fix CMD Stretch bit range width"}},{"before":"3e136b3cb2b25d1eef6b23034d580f28aad9286c","after":"b8a6c5e850841f265b474a6724d9d198dbd50a9b","ref":"refs/heads/develop","pushedAt":"2024-06-08T04:50:43.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"cyring","name":"CyrIng","path":"/cyring","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/11563789?s=80&v=4"},"commit":{"message":"[UI] Hardening missing console/terminal size","shortMessageHtmlLink":"[UI] Hardening missing console/terminal size"}},{"before":"4bc38d696fa739d7fcd7a8f542b8069a93bcbbc4","after":"3e136b3cb2b25d1eef6b23034d580f28aad9286c","ref":"refs/heads/master","pushedAt":"2024-06-07T19:31:30.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"cyring","name":"CyrIng","path":"/cyring","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/11563789?s=80&v=4"},"commit":{"message":"[AArch64] Build with Redhat RHEL version 9","shortMessageHtmlLink":"[AArch64] Build with Redhat RHEL version 9"}},{"before":"4bc38d696fa739d7fcd7a8f542b8069a93bcbbc4","after":"3e136b3cb2b25d1eef6b23034d580f28aad9286c","ref":"refs/heads/develop","pushedAt":"2024-06-07T19:15:47.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"cyring","name":"CyrIng","path":"/cyring","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/11563789?s=80&v=4"},"commit":{"message":"[AArch64] Build with Redhat RHEL version 9","shortMessageHtmlLink":"[AArch64] Build with Redhat RHEL version 9"}},{"before":"f622261545aec2f3d9ef441a7e9959109f664a1c","after":"4bc38d696fa739d7fcd7a8f542b8069a93bcbbc4","ref":"refs/heads/master","pushedAt":"2024-06-07T07:18:21.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"cyring","name":"CyrIng","path":"/cyring","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/11563789?s=80&v=4"},"commit":{"message":"[CLI] Responsive ruler to architectural context","shortMessageHtmlLink":"[CLI] Responsive ruler to architectural context"}},{"before":"82b9709fd2c735bcea5a2a314f742d0dfb58f4f0","after":"4bc38d696fa739d7fcd7a8f542b8069a93bcbbc4","ref":"refs/heads/develop","pushedAt":"2024-06-06T06:16:53.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"cyring","name":"CyrIng","path":"/cyring","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/11563789?s=80&v=4"},"commit":{"message":"[CLI] Responsive ruler to architectural context","shortMessageHtmlLink":"[CLI] Responsive ruler to architectural context"}},{"before":"f622261545aec2f3d9ef441a7e9959109f664a1c","after":"82b9709fd2c735bcea5a2a314f742d0dfb58f4f0","ref":"refs/heads/develop","pushedAt":"2024-06-06T06:06:55.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"cyring","name":"CyrIng","path":"/cyring","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/11563789?s=80&v=4"},"commit":{"message":"[CLI] Responsive ruler to architectural context","shortMessageHtmlLink":"[CLI] Responsive ruler to architectural context"}},{"before":"cf26a206d5330a9d3f899962748892798329296d","after":"f622261545aec2f3d9ef441a7e9959109f664a1c","ref":"refs/heads/master","pushedAt":"2024-06-03T05:39:21.000Z","pushType":"push","commitsCount":3,"pusher":{"login":"cyring","name":"CyrIng","path":"/cyring","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/11563789?s=80&v=4"},"commit":{"message":"[Intel] Added method `CLOCK_FLEX_MAX` with Xeon's Nehalem & Core 2\n* Grants full `MSR_FLEX_RATIO` access to tested architectures:\n- Alder Lake/S\n- Tiger Lake/U\n- Westmere/Gulftown","shortMessageHtmlLink":"[Intel] Added method <code>CLOCK_FLEX_MAX</code> with Xeon's Nehalem &amp; Core 2"}},{"before":"db15a83fb87856e095a3925f8b83205cd2eef1d5","after":"f622261545aec2f3d9ef441a7e9959109f664a1c","ref":"refs/heads/develop","pushedAt":"2024-06-02T14:46:38.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"cyring","name":"CyrIng","path":"/cyring","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/11563789?s=80&v=4"},"commit":{"message":"[Intel] Added method `CLOCK_FLEX_MAX` with Xeon's Nehalem & Core 2\n* Grants full `MSR_FLEX_RATIO` access to tested architectures:\n- Alder Lake/S\n- Tiger Lake/U\n- Westmere/Gulftown","shortMessageHtmlLink":"[Intel] Added method <code>CLOCK_FLEX_MAX</code> with Xeon's Nehalem &amp; Core 2"}},{"before":"dbc0e1efb3b3addfdd4d27bd69edaace4a00a522","after":"db15a83fb87856e095a3925f8b83205cd2eef1d5","ref":"refs/heads/develop","pushedAt":"2024-06-01T20:56:15.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"cyring","name":"CyrIng","path":"/cyring","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/11563789?s=80&v=4"},"commit":{"message":"[Intel] Provides the overclocking bins with unlocked processors","shortMessageHtmlLink":"[Intel] Provides the overclocking bins with unlocked processors"}},{"before":"cf26a206d5330a9d3f899962748892798329296d","after":"dbc0e1efb3b3addfdd4d27bd69edaace4a00a522","ref":"refs/heads/develop","pushedAt":"2024-06-01T00:36:32.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"cyring","name":"CyrIng","path":"/cyring","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/11563789?s=80&v=4"},"commit":{"message":"[Intel] Query the Overclocking bit (OC) from Capabilities","shortMessageHtmlLink":"[Intel] Query the Overclocking bit (OC) from Capabilities"}},{"before":"4705b327404ff96fa00736fdad571e4ec5381268","after":"cf26a206d5330a9d3f899962748892798329296d","ref":"refs/heads/master","pushedAt":"2024-05-31T10:38:02.000Z","pushType":"push","commitsCount":3,"pusher":{"login":"cyring","name":"CyrIng","path":"/cyring","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/11563789?s=80&v=4"},"commit":{"message":"[CLI] Make HDCP meaning string shorter","shortMessageHtmlLink":"[CLI] Make HDCP meaning string shorter"}},{"before":"18d3229183748b7074edf0afc2c122c3984d5fec","after":"cf26a206d5330a9d3f899962748892798329296d","ref":"refs/heads/develop","pushedAt":"2024-05-31T07:01:49.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"cyring","name":"CyrIng","path":"/cyring","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/11563789?s=80&v=4"},"commit":{"message":"[CLI] Make HDCP meaning string shorter","shortMessageHtmlLink":"[CLI] Make HDCP meaning string shorter"}},{"before":"23a01f498c0965dbf3834273d389b047894aac38","after":"18d3229183748b7074edf0afc2c122c3984d5fec","ref":"refs/heads/develop","pushedAt":"2024-05-29T21:16:35.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"cyring","name":"CyrIng","path":"/cyring","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/11563789?s=80&v=4"},"commit":{"message":"[Intel] Adding technologies: VMD, HDCP, IPU and VPU\n* Volume Management Device\n* High-Bandwidth Digital Content Protection\n* Image Processing Unit\n* Vision Processing Unit","shortMessageHtmlLink":"[Intel] Adding technologies: VMD, HDCP, IPU and VPU"}}],"hasNextPage":true,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"djE6ks8AAAAEbLO1ggA","startCursor":null,"endCursor":null}},"title":"Activity · cyring/CoreFreq"}