diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml new file mode 100644 index 00000000..7c7ec7c0 --- /dev/null +++ b/.github/workflows/build.yml @@ -0,0 +1,177 @@ +name: Build Multi Arch + +on: + push: + # Allows you to run this workflow manually from the Actions tab + workflow_dispatch: + +jobs: + build_job: + runs-on: ubuntu-latest + name: Build on ${{ matrix.distro }} ${{ matrix.arch }} + + strategy: + fail-fast: false + # base_image: https://hub.docker.com + matrix: + include: + - arch: amd64 + distro: debian-testing + base_image: amd64/debian:testing + packages: linux-headers-amd64 + - arch: amd64 + distro: debian-10-buster + base_image: amd64/debian:10 + packages: linux-headers-amd64 + - arch: amd64 + distro: ubuntu-rolling + base_image: amd64/ubuntu:rolling + packages: linux-headers-generic + - arch: amd64 + distro: ubuntu-16.04-xenial + base_image: amd64/ubuntu:16.04 + packages: linux-headers-generic + - arch: amd64 + distro: ubuntu-14.04-lucid + base_image: amd64/ubuntu:14.04 + packages: linux-headers-generic + - arch: amd64 + distro: alpine-latest + base_image: amd64/alpine:latest + packages: linux-virt-dev + #- arch: amd64 + # distro: alpine-3.10 + # base_image: amd64/alpine:3.10 + # packages: linux-virt-dev + # - arch: amd64 + # distro: centos7 + # base_image: amd64/centos:7 + # packages: kernel-devel + # - arch: amd64 + # distro: fedora-latest + # base_image: amd64/fedora:latest + # packages: kernel-devel + # - arch: amd64 + # distro: fedora-26 + # base_image: amd64/fedora:26 + # packages: kernel-devel + + - arch: aarch64 + distro: debian-testing + base_image: arm64v8/debian:testing + packages: linux-headers-arm64 + - arch: aarch64 + distro: debian-10-buster + base_image: arm64v8/debian:10 + packages: linux-headers-arm64 + - arch: aarch64 + distro: ubuntu-rolling + base_image: arm64v8/ubuntu:rolling + packages: linux-headers-generic + - arch: aarch64 + distro: ubuntu-16.04-xenial + base_image: arm64v8/ubuntu:16.04 + packages: linux-headers-generic + - arch: aarch64 + distro: ubuntu-14.04-trusty + base_image: arm64v8/ubuntu:14.04 + packages: linux-headers-generic + - arch: aarch64 + distro: alpine-latest + base_image: arm64v8/alpine:latest + packages: linux-virt-dev + #- arch: aarch64 + # distro: alpine-3.10 + # base_image: arm64v8/alpine:3.10 + # packages: linux-virt-dev + # - arch: aarch64 + # distro: centos7 + # base_image: arm64v8/centos:7 + # packages: kernel-devel + # - arch: aarch64 + # distro: fedora-latest + # base_image: arm64v8/fedora:latest + # packages: kernel-devel + # - arch: aarch64 + # distro: fedora-26 + # base_image: arm64v8/fedora:26 + # packages: kernel-devel + + steps: + - uses: actions/checkout@v4 + - uses: uraimo/run-on-arch-action@v2.7.1 + name: Build + id: build + with: + arch: ${{ matrix.arch }} + distro: ${{ matrix.distro }} + base_image: ${{ matrix.base_image }} + + # Not required, but speeds up builds + # githubToken: ${{ github.token }} + + # Create an artifacts directory + setup: | + mkdir -p "${PWD}/artifacts" + + # Mount the artifacts directory as /artifacts in the container + dockerRunArgs: | + --volume "${PWD}/artifacts:/artifacts" + + # Pass some environment variables to the container + env: | # YAML, but pipe character is necessary + artifact_name: git-${{ matrix.distro }}_${{ matrix.arch }} + + # The shell to run commands with in the container + shell: /bin/sh + + # Install some dependencies in the container. This speeds up builds if + # you are also using githubToken. Any dependencies installed here will + # be part of the container image that gets cached, so subsequent + # builds don't have to re-install them. The image layer is cached + # publicly in your project's package repository, so it is vital that + # no secrets are present in the container state or logs. + # https://command-not-found.com/lscpu + install: | + case "${{ matrix.distro }}" in + ubuntu*|debian*|kali*) + apt-get update -q -y + apt-get install -q -y util-linux build-essential ${{ matrix.packages }} + ;; + arch*) + pacman -Syu --noconfirm util-linux base-devel ${{ matrix.packages }} + ;; + centos*) + yum -y update + yum -y install util-linux ${{ matrix.packages }} + yum -y groupinstall "Development Tools" + ;; + fedora*) + dnf -y update + dnf -y install util-linux ${{ matrix.packages }} + dnf -y groupinstall "Development Tools" + ;; + alpine*) + apk update + apk add alpine-sdk util-linux ${{ matrix.packages }} + ;; + esac + + + # Produce a binary artifact and place it in the mounted volume + run: | + echo "--------------------------------------------------------------------------------" + cat /etc/os-release + echo "--------------------------------------------------------------------------------" + uname -a + echo "--------------------------------------------------------------------------------" + lscpu + echo "--------------------------------------------------------------------------------" + gcc -E -v - CoreFreq 2015-2023CoreFreq 2015-2024` * GNU Make tool * Linux Kernel Header files to build modules * Mandatory : `CONFIG_MODULES, CONFIG_SMP, CONFIG_X86_MSR` - * Optionally: `CONFIG_HOTPLUG_CPU, CONFIG_CPU_IDLE, CONFIG_CPU_FREQ, CONFIG_PM_SLEEP, CONFIG_DMI, CONFIG_XEN, CONFIG_AMD_NB, CONFIG_SCHED_MUQSS, CONFIG_SCHED_BMQ, CONFIG_SCHED_PDS, CONFIG_SCHED_ALT, CONFIG_SCHED_BORE, CONFIG_CACHY, CONFIG_ACPI, CONFIG_ACPI_CPPC_LIB` + * Optionally: `CONFIG_HOTPLUG_CPU, CONFIG_CPU_IDLE, CONFIG_CPU_FREQ, CONFIG_PM_SLEEP, CONFIG_DMI, CONFIG_HAVE_NMI, CONFIG_XEN, CONFIG_AMD_NB, CONFIG_SCHED_MUQSS, CONFIG_SCHED_BMQ, CONFIG_SCHED_PDS, CONFIG_SCHED_ALT, CONFIG_SCHED_BORE, CONFIG_CACHY, CONFIG_ACPI, CONFIG_ACPI_CPPC_LIB` 2. Clone the source code into a working directory. - `git clone https://github.com/cyring/CoreFreq.git` - +```sh +git clone https://github.com/cyring/CoreFreq.git +``` + 3. Build the programs. -`cd CoreFreq` -`make` +```sh +cd CoreFreq +make -j ``` -cc -Wall -pthread -c corefreqd.c -o corefreqd.o -cc -Wall -c corefreqm.c -o corefreqm.o -cc corefreqd.c corefreqm.c -o corefreqd -lpthread -lm -lrt -cc -Wall -c corefreq-cli.c -o corefreq-cli.o -cc -Wall -c corefreq-ui.c -o corefreq-ui.o -cc corefreq-cli.c corefreq-ui.c -o corefreq-cli -lm -lrt -make -C /lib/modules/x.y.z/build M=/workdir/CoreFreq modules +```console +cc -Wall -Wfatal-errors -Wno-unused-variable -pthread -c x86_64/corefreqd.c \ + -D CORE_COUNT=256 -D TASK_ORDER=5 -D MAX_FREQ_HZ=7125000000 -D UBENCH=0 -D DELAY_TSC=1 \ + -o build/corefreqd.o +cc -Wall -Wfatal-errors -Wno-unused-variable -c x86_64/corefreqm.c \ + -D CORE_COUNT=256 -D TASK_ORDER=5 -D MAX_FREQ_HZ=7125000000 -D UBENCH=0 -D DELAY_TSC=1 \ + -o build/corefreqm.o +cc -Wall -Wfatal-errors -Wno-unused-variable -c x86_64/corefreq-cli.c \ + -D CORE_COUNT=256 -D TASK_ORDER=5 -D MAX_FREQ_HZ=7125000000 -D UBENCH=0 -D DELAY_TSC=1 \ + -o build/corefreq-cli.o +cc -Wall -Wfatal-errors -Wno-unused-variable -c x86_64/corefreq-ui.c \ + -D CORE_COUNT=256 -D TASK_ORDER=5 -D MAX_FREQ_HZ=7125000000 -D UBENCH=0 -D DELAY_TSC=1 \ + -o build/corefreq-ui.o +cc -Wall -Wfatal-errors -Wno-unused-variable -c x86_64/corefreq-cli-rsc.c \ + -D CORE_COUNT=256 -D TASK_ORDER=5 -D MAX_FREQ_HZ=7125000000 -D UBENCH=0 -D DELAY_TSC=1 \ + -o build/corefreq-cli-rsc.o +cc -Wall -Wfatal-errors -Wno-unused-variable -c x86_64/corefreq-cli-json.c \ + -D CORE_COUNT=256 -D TASK_ORDER=5 -D MAX_FREQ_HZ=7125000000 -D UBENCH=0 -D DELAY_TSC=1 \ + -o build/corefreq-cli-json.o +cc -Wall -Wfatal-errors -Wno-unused-variable -c x86_64/corefreq-cli-extra.c \ + -D CORE_COUNT=256 -D TASK_ORDER=5 -D MAX_FREQ_HZ=7125000000 -D UBENCH=0 -D DELAY_TSC=1 \ + -o build/corefreq-cli-extra.o +cc -Wall -Wfatal-errors -Wno-unused-variable x86_64/corefreqd.c x86_64/corefreqm.c \ + -D CORE_COUNT=256 -D TASK_ORDER=5 -D MAX_FREQ_HZ=7125000000 -D UBENCH=0 -D DELAY_TSC=1 \ + -o build/corefreqd -lpthread -lm -lrt +cc -Wall -Wfatal-errors -Wno-unused-variable \ + x86_64/corefreq-cli.c x86_64/corefreq-ui.c x86_64/corefreq-cli-rsc.c \ + x86_64/corefreq-cli-json.c x86_64/corefreq-cli-extra.c \ + -D CORE_COUNT=256 -D TASK_ORDER=5 -D MAX_FREQ_HZ=7125000000 -D UBENCH=0 -D DELAY_TSC=1 \ + -o build/corefreq-cli -lm -lrt make[1]: Entering directory '/usr/lib/modules/x.y.z/build' - CC [M] /workdir/CoreFreq/corefreqk.o - Building modules, stage 2. - MODPOST 1 modules - CC /workdir/CoreFreq/corefreqk.mod.o - LD [M] /workdir/CoreFreq/corefreqk.ko -make[1]: Leaving directory '/usr/lib/modules/x.y.z/build' + CC [M] CoreFreq/build/module/corefreqk.o + LD [M] CoreFreq/build/corefreqk.o + MODPOST CoreFreq/build/Module.symvers + CC [M] CoreFreq/build/corefreqk.mod.o + LD [M] CoreFreq/build/corefreqk.ko + BTF [M] CoreFreq/build/corefreqk.ko +make[1]: Leaving directory '/usr/lib/modules/x.y.z/build ``` 4. (Optionally) Sign the driver If module signature verification is enabled into Kernel, you will have to sign the `corefreqk.ko` driver. @@ -103,31 +130,47 @@ If module signature verification is enabled into Kernel, you will have to sign t #### Manual 5. Copying _CoreFreq_ into the binaries directory -`make install` +```sh +make install +``` #### Distribution package 6. Although _CoreFreq_ is released in the ArchLinux AUR ; other sources of distribution may require to reload the systemd daemons: -`systemctl daemon-reload` +```sh +systemctl daemon-reload +``` ### Start 7. When built from source code: * Load the kernel module, from current directory, as root. -`insmod corefreqk.ko` +```sh +insmod build/corefreqk.ko +``` * Start the daemon, as root. -`corefreqd` +```sh +./build/corefreqd +``` * Start the client, as a user (_in another terminal or console_). -`corefreq-cli` +```sh +./build/corefreq-cli +``` 8. When manually installed or from a distribution package: * Load the kernel module, as root. -`modprobe corefreqk` +```sh +modprobe corefreqk +``` * Start the daemon, as root. -`systemctl start corefreqd` +```sh +systemctl start corefreqd +``` * Start the client, as a user. -`corefreq-cli` +```sh +corefreq-cli +``` ### Stop @@ -136,7 +179,9 @@ If module signature verification is enabled into Kernel, you will have to sign t 10. Press Ctrl+c to stop the daemon (in foreground) or kill its background job. 11. Unload the kernel module -`rmmod corefreqk.ko` +```sh +rmmod corefreqk.ko +``` ### Try Download the _CoreFreq_ Live CD from the [Wiki](http://github.com/cyring/CoreFreq/wiki/Live-CD) @@ -145,32 +190,39 @@ Download the _CoreFreq_ Live CD from the [Wiki](http://github.com/cyring/CoreFre ## Screenshots ### Linux kernel module Use `lsmod`, `dmesg` or `journalctl -k` to check if the module is started: -``` -CoreFreq: Processor [06_1A] Architecture [Nehalem/Bloomfield] CPU [8/8] +```console +CoreFreq(14:30:-1): Processor [ 8F_71] Architecture [Zen2/Matisse] SMT [32/32] ``` ### Daemon -``` -CoreFreq Daemon. Copyright (C) 2015-2023 CYRIL COURTIAT +```console +CoreFreq Daemon #.##.# Copyright (C) 2015-2024 CYRIL COURTIAT - Processor [Intel(R) Core(TM) i7 CPU 920 @ 2.67GHz] - Architecture [Nehalem/Bloomfield] 8/8 CPU Online. + Processor [AMD Ryzen 9 3950X 16-Core Processor] + Architecture [Zen2/Matisse] 32/32 CPU Online. ``` ### Client Without arguments, the corefreq-cli program displays Top Monitoring ![alt text](http://blog.cyring.free.fr/images/CoreFreq_Tour_2017-12-06.gif "CoreFreq UI") - _Remark_: Drawing will stall if the terminal width is lower than 80 columns, or its height is less than required. + _Remark_: Drawing will stall if the terminal width is lower than 80 columns, or its height is less than required. + +* Memory Controller + +![alt text](http://blog.cyring.free.fr/images/CoreFreq_MC.png "IMC") + +* With the option `-c`, the client traces counters -* With the option '-c', the client traces counters. ![alt text](http://blog.cyring.free.fr/images/CoreFreq_Counters.gif "CoreFreq Counters") -* Using option '-m' corefreq-cli shows the CPU topology +* Using option `-m` corefreq-cli shows the CPU topology + ![alt text](http://blog.cyring.free.fr/images/CoreFreq_Topology.png "CoreFreq CPU & caches topology") -* With the option '-i' corefreq-cli traces the number of instructions per second / cycle +* With the option `-i` corefreq-cli traces the number of instructions per second / cycle + ``` CPU IPS IPC CPI #00 0.000579/s 0.059728/c 16.742698/i @@ -183,7 +235,7 @@ CPU IPS IPC CPI #07 0.000088/s 0.150406/c 6.648674/i ``` -* Use the option '-s' to show the Processor information (BSP) +* Use the option `-s` to show the Processor information (BSP) ![alt text](http://blog.cyring.free.fr/images/CoreFreq_SysInfo.png "CoreFreq System Info") @@ -193,16 +245,22 @@ CPU IPS IPC CPI ## Gentoo Linux * In [GURU overlay](https://wiki.gentoo.org/wiki/Project:GURU/Information_for_End_Users) CoreFreq [package](https://github.com/gentoo/guru/tree/master/sys-apps/corefreq), please contact [vitaly-zdanevich](https://github.com/vitaly-zdanevich) -## Debian, Ubuntu +## Debian, Ubuntu, TUXEDO * Installing the DKMS package will pull the Kernel development packages -`apt-get install dkms` - * Or, install selectively the development packages prerequisites. -`apt-get install libpthread-stubs0-dev` +```sh +apt install dkms +``` + * Or install the kernel development prerequisites. +```sh +apt list git build-essential gawk fakeroot linux-headers* +``` -## Red Hat, CentOS +## Red Hat, CentOS, AlmaLinux * Development packages prerequisites. -`yum install kernel-devel` -`yum group install "Development Tools"` +```sh +yum install kernel-devel +yum group install "Development Tools" +``` ## openSUSE * Packages @@ -212,17 +270,20 @@ CPU IPS IPC CPI ## ProxMox Install Tools -`apt-get install build-essential dkms git libpthread-stubs0-dev` +```sh +apt-get install build-essential dkms git libpthread-stubs0-dev +``` Install headers related to your kernel -``` +```sh apt install pve-headers-`uname -r` git clone https://github.com/cyring/CoreFreq.git -cd CoreFreq/ && make +cd CoreFreq && make ``` + Install the module in the system, refresh it and start it -``` +```sh make install depmod modprobe corefreqk @@ -234,6 +295,26 @@ systemctl start corefreqd 1. `corefreq.plg` from [ich777/unraid-corefreq](https://github.com/ich777/unraid-corefreq) 2. Based on latest developments, please contact [ich777](https://github.com/ich777) +## Alpine +```sh +## Install the kernel development packages +apk add alpine-sdk sed installkernel bc nawk diffutils findutils pahole openssl-dev python3 linux-virt linux-virt-dev +``` + +## Chimera +```sh +## Install the kernel development packages +doas apk add git ckms gmake clang linux-headers linux-lts-devel +## Add the CoreFreq directory containing the ckms.ini file +doas ckms add CoreFreq/ +## Build the CoreFreq version M.m.r +doas ckms build corefreqk=M.m.r +## Or manually if using the Clang compiler +gmake CC=clang +``` + +## [Buildroot](https://github.com/cyring/CoreFreq-buildroot) + ## Q&A * Q: How many CPUs are supported by _CoreFreq_ ? @@ -518,8 +599,18 @@ parm: Custom_TDC_Offset:TDC Limit Offset (amp) (short) parm: Activate_TDC_Limit:Activate TDC Limiting (short) parm: L1_HW_PREFETCH_Disable:Disable L1 HW Prefetcher (short) parm: L1_HW_IP_PREFETCH_Disable:Disable L1 HW IP Prefetcher (short) +parm: L1_NPP_PREFETCH_Disable:Disable L1 NPP Prefetcher (short) +parm: L1_Scrubbing_Enable:Enable L1 Scrubbing (short) parm: L2_HW_PREFETCH_Disable:Disable L2 HW Prefetcher (short) parm: L2_HW_CL_PREFETCH_Disable:Disable L2 HW CL Prefetcher (short) +parm: L2_AMP_PREFETCH_Disable:Adaptive Multipath Probability (short) +parm: L2_NLP_PREFETCH_Disable:Disable L2 NLP Prefetcher (short) +parm: L1_STRIDE_PREFETCH_Disable:Disable L1 Stride Prefetcher (short) +parm: L1_REGION_PREFETCH_Disable:Disable L1 Region Prefetcher (short) +parm: L1_BURST_PREFETCH_Disable:Disable L1 Burst Prefetcher (short) +parm: L2_STREAM_PREFETCH_Disable:Disable L2 Stream Prefetcher (short) +parm: L2_UPDOWN_PREFETCH_Disable:Disable L2 Up/Down Prefetcher (short) +parm: LLC_Streamer_Disable:Disable LLC Streamer (short) parm: SpeedStep_Enable:Enable SpeedStep (short) parm: C1E_Enable:Enable SpeedStep C1E (short) parm: TurboBoost_Enable:Enable Turbo Boost (array of short) @@ -561,15 +652,30 @@ parm: Mech_IBPB:Mitigation Mechanism IBPB (short) parm: Mech_L1D_FLUSH:Mitigation Mechanism Cache L1D Flush (short) parm: Mech_PSFD:Mitigation Mechanism PSFD (short) parm: Mech_BTC_NOBR:Mitigation Mechanism BTC-NOBR (short) +parm: Mech_XPROC_LEAK:Mitigation Mech. Cross Processor Leak (short) +parm: Mech_AGENPICK:Mitigation Mech. LsCfgDisAgenPick (short) parm: WDT_Enable:Watchdog Hardware Timer (short) parm: HSMP_Attempt:Attempt the HSMP interface (short) ``` +## Arm [AArch64] +### Screenshots + +![alt text](http://blog.cyring.free.fr/images/CoreFreq_RK3588.png "RK3588 OPi 5 Plus") + +### Q&A + +* Q: Counters are stuck to zero + + A: Add parameter `nohlt` to the kernel boot command line. + +---- + ## Algorithm ![alt text](http://blog.cyring.free.fr/images/CoreFreq-algorithm.png "CoreFreq algorithm") # About [CyrIng](https://github.com/cyring) -Copyright (C) 2015-2023 CYRIL COURTIAT +Copyright (C) 2015-2024 CYRIL COURTIAT ------- diff --git a/aarch64/arm_reg.h b/aarch64/arm_reg.h new file mode 100644 index 00000000..868f7c17 --- /dev/null +++ b/aarch64/arm_reg.h @@ -0,0 +1,844 @@ +/* + * CoreFreq + * Copyright (C) 2015-2024 CYRIL COURTIAT + * Licenses: GPL2 + */ + +#define CPUPWRCTLR_EL1 sys_reg(0b11, 0b000, 0b1111, 0b0010, 0b111) +#define ID_AA64ISAR2_EL1 sys_reg(0b11, 0b000, 0b0000, 0b0110, 0b010) +#define ID_AA64MMFR2_EL1 sys_reg(0b11, 0b000, 0b0000, 0b0111, 0b010) +#define ID_AA64MMFR3_EL1 sys_reg(0b11, 0b000, 0b0000, 0b0111, 0b011) +#define ID_AA64SMFR0_EL1 sys_reg(0b11, 0b000, 0b0000, 0b0100, 0b101) +#define ID_AA64ZFR0_EL1 sys_reg(0b11, 0b000, 0b0000, 0b0100, 0b100) +#define SCTLR2_EL1 sys_reg(0b11, 0b000, 0b0001, 0b0000, 0b011) +#define MRS_SSBS2 sys_reg(0b11, 0b011, 0b0100, 0b0010, 0b110) +#define MRS_PAN sys_reg(0b11, 0b000, 0b0100, 0b0010, 0b011) +#define MRS_UAO sys_reg(0b11, 0b000, 0b0100, 0b0010, 0b100) +#define MRS_DIT sys_reg(0b11, 0b011, 0b0100, 0b0010, 0b101) +#define MRS_TCO sys_reg(0b11, 0b011, 0b0100, 0b0010, 0b111) +#define MRS_ALLINT sys_reg(0b11, 0b000, 0b0100, 0b0011, 0b000) +#define MRS_PM sys_reg(0b11, 0b000, 0b0100, 0b0011, 0b001) +#define MRS_SVCR sys_reg(0b11, 0b011, 0b0100, 0b0010, 0b010) +#define AMCGCR_EL0 sys_reg(0b11, 0b011, 0b1101, 0b0010, 0b010) +#define CLUSTERCFR_EL1 sys_reg(0b11, 0b000, 0b1111, 0b0011, 0b000) +#define CLUSTERIDR_EL1 sys_reg(0b11, 0b000, 0b1111, 0b0011, 0b001) + +typedef union +{ + unsigned long long value; /* CPU0:0x412fd050 ; CPU4:0x414fd0b0 */ + struct + { + unsigned long long + Revision : 4-0, + PartNum : 16-4, + Architecture : 20-16, /* 0b1111=by CPUID scheme */ + Variant : 24-20, + Implementer : 32-24, + RES0 : 64-32; + }; +} MIDR; + +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + Aff0 : 8-0, /* Thread ID */ + Aff1 : 16-8, /* Core ID: CPUID[12-8] L1 */ + Aff2 : 24-16, /* Cluster ID - Level2 */ + MT : 25-24, /* Multithreading */ + UNK : 30-25, + U : 31-30, /* 0=Uniprocessor */ + RES1 : 32-31, + Aff3 : 40-32, /* Cluster ID - Level3 */ + RES0 : 64-40; + }; +} MPIDR; +/* +CPU:MPIDR + 0:0x81000000 + 1:0x81000100 + 2:0x81000200 + 3:0x81000300 + 4:0x81000400 + 5:0x81000500 + 6:0x81000600 + 7:0x81000700 +*/ + +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + Revision : 32-0, + RES0 : 64-32; + }; +} REVIDR; + +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + EnableAll : 1-0, + ResetEvent : 2-1, + ResetCycle : 3-2, + ClockDiv : 4-3, /* 1:PMCCNTR counts once / 64 cycles */ + ExportEvent : 5-4, + DisableCycle : 6-5, /* 1:PMCCNTR is disabled */ + EnableLongCycle : 7-6, + EnableLongEvent : 8-7, + RES0 : 9-8, + FZO : 10-9, /* 1:Freeze-on-overflow */ + RES1 : 11-10, + NumEvtCtrs : 16-11, + IDcode : 24-16, + Implementer : 32-24, + Freeze_On_SPE : 33-32, + RES2 : 64-33; + }; +} PMCR; + +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + SEL : 5-0, + RES0 : 64-5; + }; +} PMSELR; + +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + CFILTR_EVTYPER : 64-0; + }; +} PMXEVTYPER; + +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + RES0 : 20-0, + RLH : 21-20, + RLU : 22-21, + RLK : 23-22, + T : 24-23, + SH : 25-24, + RES1 : 26-25, + M : 27-26, + NSH : 28-27, + NSU : 29-28, + NSK : 30-29, + U : 31-30, + P : 32-31, + RES2 : 56-32, + VS : 58-56, + RES3 : 64-58; + }; +} PMCCFILTR; + +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + EvtCount : 16-0, + RES0 : 20-16, + RLH : 21-20, + RLU : 22-21, + RLK : 23-22, + T : 24-23, + SH : 25-24, + MT : 26-25, + M : 27-26, + NSH : 28-27, + NSU : 29-28, + NSK : 30-29, + U : 31-30, + P : 32-31, + TH : 44-32, + RES1 : 54-44, + TLC : 56-54, + VS : 58-56, + SYNC : 59-58, + RES2 : 60-59, + TE : 61-60, + TC : 64-61; + }; +} PMEVTYPER; + +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + Pm : 31-0, + C : 32-31, + F0 : 33-32, + RES0 : 64-33; + }; +} PMCNTENSET; + +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + Pm : 31-0, + C : 32-31, + F0 : 33-32, + RES0 : 64-33; + }; +} PMCNTENCLR; + + +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + EN : 1-0, + SW : 2-1, + CR : 3-2, + ER : 4-3, + UEN : 5-4, + IR : 6-5, + TID : 7-6, + RES0 : 64-7; + }; +} PMUSERENR; + +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + ClockFreq_Hz : 32-0, + RES0 : 64-32; + }; +} CNTFRQ; + +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + PhysicalCount : 64-0; + }; +} CNTPCT; + +typedef union +{ + unsigned long long value; /* SMT=0x0000000000000000 */ + struct + { + unsigned long long + CORE_PWRDN_EN : 1-0, + RES0 : 4-1, + WFI_RET_CTRL : 7-4, + WFE_RET_CTRL : 10-7, + RES1 : 32-10, + RES2 : 64-32; + }; +} CPUPWRCTLR; + +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + InD : 1-0, + Level : 4-1, + RES0 : 32-4, + RES1 : 64-32; + }; +} CSSELR; + +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + Ctype1 : 3-0, + Ctype2 : 6-3, + Ctype3 : 9-6, + RES0 : 21-9, + LoUIS : 24-21, + LoC : 27-24, + LoUU : 30-27, + ICB : 33-30, + RES1 : 64-33; + }; +} CLIDR; + +typedef union +{ /* CPU0:0x00000000003033ff ; CPU4:0x0000000000300000 */ + unsigned long long value; + struct + { + unsigned long long + RES0 : 16-0, + ZEN : 18-16, + RES1 : 20-18, + FPEN : 22-20, + RES2 : 24-22, + SMEN : 26-24, + RES3 : 28-26, + TTA : 29-28, + E0POE : 30-29, + RES4 : 64-30; + }; +} CPACR; + +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + CG0NC : 8-0, + CG1NC : 16-8, + RES0 : 64-16; + }; +} AMCGCR; + +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + DebugVer : 4-0, + TraceVer : 8-4, + PMUVer : 12-8, + BRPs : 16-12, + PMSS : 20-16, + WRPs : 24-20, + SEBEP : 28-24, + CTX_CMPs : 32-28, + PMSVer : 36-32, + DoubleLock : 40-36, + TraceFilt : 44-40, + TraceBuffer : 48-40, + MTPMU : 52-48, + BRBE : 56-52, + ExtTrcBuff : 60-56, + HPMN0 : 64-60; + }; +} AA64DFR0; + +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + SYSPMUID : 8-0, + BRPs : 16-8, + WRPs : 24-16, + CTX_CMPs : 32-24, + SPMU : 36-32, + PMICNTR : 40-36, + ABLE : 44-40, + ITE : 48-44, + EBEP : 52-48, + DPFZS : 56-52, + ABL_CMPs : 64-56; + }; +} AA64DFR1; + +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + STEP : 4-0, + BWE : 8-4, + RES0 : 64-8; + }; +} AA64DFR2; + +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + RES0 : 4-0, + AES : 8-4, + SHA1 : 12-8, + SHA2 : 16-12, + CRC32 : 20-16, + CAS : 24-20, + TME : 28-24, + RDM : 32-28, + SHA3 : 36-32, + SM3 : 40-36, + SM4 : 44-40, + DP : 48-44, + FHM : 52-48, + TS : 56-52, + TLB : 60-56, + RNDR : 64-60; + }; +} AA64ISAR0; + +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + DPB : 4-0, + APA : 8-4, + API : 12-8, + JSCVT : 16-12, + FCMA : 20-16, + LRCPC : 24-20, + GPA : 28-24, + GPI : 32-28, + FRINTTS : 36-32, + SB : 40-36, + SPECRES : 44-40, + BF16 : 48-44, + DGH : 52-48, + I8MM : 56-52, + XS : 60-56, + LS64 : 64-60; + }; +} AA64ISAR1; + +typedef union +{ + unsigned long long value; /* CPU0:0x00000000 ; CPU4:0x00000000 */ + struct + { + unsigned long long + WFxT : 4-0, + RPRES : 8-4, + GPA3 : 12-8, + APA3 : 16-12, + MOPS : 20-16, + BC : 24-20, + PAC_frac : 28-24, + CLRBHB : 32-28, + SYSREG_128 : 36-32, + SYSINSTR_128 : 40-36, + PRFMSLC : 48-40, + RPRFM : 52-48, + CSSC : 56-52, + LUT : 60-56, + ATS1A : 64-60; + }; +} AA64ISAR2; + +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + CPA : 4-0, + FAMINMAX : 8-4, + TLBIW : 12-8, + PACM : 16-12, + RES0 : 64-16; + }; +} AA64ISAR3; + +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + PARange : 4-0, + ASID_Bits : 8-4, + BigEnd : 12-8, + SNSMem : 16-12, + BigEnd_EL0 : 20-16, + TGran16 : 24-20, + TGran64 : 28-24, + TGran4 : 32-28, + TGran16_2 : 36-32, + TGran64_2 : 40-36, + TGran4_2 : 44-40, + ExS : 48-44, + RES0 : 56-48, + FGT : 60-56, + ECV : 64-60; + }; +} AA64MMFR0; + +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + HAFDBS : 4-0, + VMID_Bits : 8-4, + VH : 12-8, + HPDS : 16-12, + LO : 20-16, + PAN : 24-20, + SpecSEI : 28-24, + XNX : 32-28, + TWED : 36-32, + ETS : 40-36, + HCX : 44-40, + AFP : 48-44, + nTLBPA : 52-48, + TIDCP1 : 56-52, + CMOW : 60-56, + ECBHB : 64-60; + }; +} AA64MMFR1; + +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + CnP : 4-0, + UAO : 8-4, + LSM : 12-8, + IESB : 16-12, + VARange : 20-16, + CCIDX : 24-20, + NV : 28-24, + ST : 32-28, + AT : 36-32, + IDS : 40-36, + FWB : 44-40, + RES0 : 48-44, + TTL : 52-48, + BBM : 56-52, + EVT : 60-56, + E0PD : 64-60; + }; +} AA64MMFR2; + +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + TCRX : 4-0, + SCTLRX : 8-4, + S1PIE : 12-8, + S2PIE : 16-12, + S1POE : 20-16, + S2POE : 24-20, + AIE : 28-24, + MEC : 32-28, + D128 : 36-32, + D128_2 : 40-36, + SNERR : 44-40, + ANERR : 48-44, + RES0 : 52-48, + SDERR : 56-52, + ADERR : 60-56, + Spec_FPACC : 64-60; + }; +} AA64MMFR3; + +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + EIESB : 8-4, + ASID2 : 12-8, + HACDBS : 16-12, + FGWTE3 : 20-16, + NV_frac : 24-20, + E2H0 : 28-24, + RES0 : 36-28, + E3DSE : 40-36, + RES1 : 64-40; + }; +} AA64MMFR4; + +typedef union +{ /* CPU0:0x11112222 ; CPU4:0x1100000011111112 */ + unsigned long long value; + struct + { + unsigned long long + EL0 : 4-0, /*0b0001=AArch64;0b0010=AArch{32,64}*/ + EL1 : 8-4, + EL2 : 12-8, + EL3 : 16-12, + FP : 20-16, + AdvSIMD : 24-20, + GIC : 28-24, + RAS : 32-28, + SVE : 36-32, + SEL2 : 40-36, + MPAM : 44-40, + AMU : 48-44, + DIT : 52-48, + RME : 56-52, + CSV2 : 60-56, + CSV3 : 64-60; + }; +} AA64PFR0; +/* +CPU:AA64PFR0 + 1:0x0000000011112222 + 0:0x0000000011112222 + 2:0x0000000011112222 + 3:0x0000000011112222 + 4:0x1100000011111112 + 5:0x1100000011111112 + 6:0x1100000011111112 + 7:0x1100000011111112 +*/ +typedef union +{ + unsigned long long value; /* Pkg:0x00000010 */ + struct + { + unsigned long long + BT : 4-0, + SSBS : 8-4, + MTE : 12-8, + RAS_frac : 16-12, + MPAM_frac : 20-16, + SME : 28-24, + RNDR_trap : 32-28, + CSV2_frac : 36-32, + NMI : 40-36, + MTE_frac : 44-40, + GCS : 48-44, + THE : 52-48, + MTEX : 56-52, + DF2 : 60-56, + PFAR : 64-60; + }; +} AA64PFR1; + +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + MTEPERM : 4-0, + MTESTOREONLY : 8-4, + MTEFAR : 12-8, + RES0 : 32-12, + FPMR : 36-32, + RES1 : 64-36; + }; +} AA64PFR2; + +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + RES0 : 28-0, + SF8DP2 : 29-28, + SF8DP4 : 30-29, + SF8FMA : 31-30, + RES1 : 32-31, + F32F32 : 33-32, + BI32I32 : 34-33, + B16F32 : 35-34, + F16F32 : 36-35, + I8I32 : 40-36, + F8F32 : 41-40, + F8F16 : 42-41, + F16F16 : 43-42, + B16B16 : 44-43, + I16I32 : 48-44, + F64F64 : 49-48, + RES2 : 52-49, + I16I64 : 56-52, + SMEver : 60-56, + LUTv2 : 61-60, + RES3 : 63-61, + FA64 : 64-63; + }; +} AA64SMFR0; + +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + SVE_Ver : 4-0, + SVE_AES : 8-4, + RES0 : 16-8, + BitPerm : 20-16, + SVE_BF16 : 24-20, + B16B16 : 28-24, + RES1 : 32-28, + SVE_SHA3 : 36-32, + RES2 : 40-36, + SVE_SM4 : 44-40, + SVE_I8MM : 48-44, + RES3 : 52-48, + SVE_F32MM : 56-52, + SVE_F64MM : 60-56, + RES4 : 64-60; + }; +} AA64ZFR0; + +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + RES0 : 12-0, + SSBS : 13-12, + RES1 : 32-13, + RES2 : 64-32; + }; +} SSBS2; + +typedef union +{ /* R82; A55; A75; A76; A76AE; A77; A78; A78AE; A78C; X1; X1C; N3; V1 */ + unsigned long long value; /* Pkg:0x0000000007bfda77 */ + struct + { + unsigned long long + NUMCORE : 4-0, + NUMPE : 9-4, + L3 : 10-9, + WRLAT : 12-10, + RDLAT : 13-12, + RDSLC : 14-13, + ECC : 15-14, + NUMMAS : 17-15, + MAS : 18-17, + RAZ1 : 19-18, + ACPW : 20-19, + ACP : 21-20, + RAZ2 : 22-21, + PPW : 23-22, + PP : 24-23, + RAZ3 : 25-24, + TRSH : 29-25, + TRSV : 33-29, + RAZ4 : 51-33, + L3SLC : 54-51, + RAZ5 : 55-24, + SFIDX : 59-55, + SFWAY : 61-59, + NODES : 64-61; + } IMP; + struct + { + unsigned long long + NUMCORE : 3-0, + RAZ1 : 4-3, + L3 : 5-4, + WRLAT : 6-5, + RDLAT : 7-6, + RDSLC : 8-7, + ECC : 9-8, + MAS : 11-9, + ACP : 12-11, + PP : 13-12, + MAS_Ext : 14-13, + CPUSLC : 22-14, + RAZ2 : 23-22, + WRDLY : 24-23, + NUMPE : 28-24, + RAZ3 : 30-28, + SafetyMode : 32-30, + RSVD : 64-32; + } DSU; +} CLUSTERCFR; + +typedef union +{ + unsigned long long value; /* Pkg:0x0000000000000041 */ + struct + { + unsigned long long + Revision : 4-0, + Variant : 8-4, + RAZ : 32-8, + RSVD : 64-32; + }; +} CLUSTERIDR; + +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + Highest : 8-0, + Guaranteed : 16-8, + Most_Efficient : 24-16, + Lowest : 32-24, + ReservedBits : 64-32; /* **Must be zero** */ + }; +} HWP_CAPABILITIES; + +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + EN_Guarantee_Chg: 1-0, + EN_Excursion_Min: 2-1, + EN_Highest_Chg : 3-2, + EN_PECI_OVERRIDE: 4-3, + ReservedBits : 64-4; /* **Must be zero** */ + }; +} HWP_INTERRUPT; + +typedef union +{ + unsigned long long value; + struct + { + unsigned long long + Minimum_Perf : 8-0, + Maximum_Perf : 16-8, + Desired_Perf : 24-16, + Energy_Pref : 32-24, + Activity_Window : 42-32, + Package_Control : 43-42, + ReservedBits : 59-43, + Act_Window_Valid: 60-59, /* Activity_Window Valid; Default=0 */ + EPP_Valid : 61-60, /*1:[HWP_REQUEST];0:[HWP_REQUEST_PKG]*/ + Desired_Valid : 62-61, /* -> Desired_Perf */ + Maximum_Valid : 63-62, /* -> Maximum_Perf */ + Minimum_Valid : 64-63; /* -> Minimum_Perf */ + }; +} HWP_REQUEST; diff --git a/aarch64/bitasm.h b/aarch64/bitasm.h new file mode 100644 index 00000000..18bc77cf --- /dev/null +++ b/aarch64/bitasm.h @@ -0,0 +1,844 @@ +/* + * CoreFreq + * Copyright (C) 2015-2024 CYRIL COURTIAT + * Licenses: GPL2 + */ + +#define FEAT_MESSAGE(_msg) _Pragma(#_msg) +#define FEAT_MSG(_msg) FEAT_MESSAGE(message(#_msg)) + +enum { + SYNC = 0, + SYNC0 = 10, + SYNC1 = 11, + BURN = 31, + COMP0 = 40, + COMP1 = 41, + NTFY0 = 50, + NTFY1 = 51, + NTFY = 63 +}; + +#define BIT_MASK_SYNC \ + 0b0000000000000000000000000000000000000000000000000000110000000000LLU + +#define BIT_MASK_COMP \ + 0b0000000000000000000000110000000000000000000000000000000000000000LLU + +#define BIT_MASK_NTFY \ + 0b0000000000001100000000000000000000000000000000000000000000000000LLU + +#define MAXCOUNTER(M, m) ((M) > (m) ? (M) : (m)) +#define MINCOUNTER(m, M) ((m) < (M) ? (m) : (M)) + +#define CORE_COUNT_MASK(_cc) (_cc - 1) +#define CORE_WORD_TOP(_cc) (CORE_COUNT_MASK(_cc) >> 6) +#define CORE_WORD_MOD(_cc_,_offset_) ((_offset_ & CORE_COUNT_MASK(_cc_)) & 0x3f) +#define CORE_WORD_POS(_cc_,_offset_) ((_offset_ & CORE_COUNT_MASK(_cc_)) >> 6) + +typedef unsigned long long int Bit1024[16]; +typedef unsigned long long int Bit512[8]; +typedef unsigned long long int Bit256[4]; +typedef unsigned long long int Bit128[2]; +typedef unsigned long long int Bit64; +typedef unsigned int Bit32; + +#define BitT2(_cc) Bit##_cc +#define BitT1(_cc) BitT2(_cc) +#define BitCC BitT1(CORE_COUNT) + +#if (CORE_COUNT == 64) +#define InitCC(_val) (_val) +#else +#define InitCC(_val) {[0 ... CORE_WORD_TOP(CORE_COUNT) - 1] = _val} +#endif + +#define LOCKLESS " " +#define BUS_LOCK "lock " + +#define BARRIER(pfx) \ +__asm__ volatile \ +( \ + "dsb" "\n\t" \ + "isb" \ + : \ + : \ + : "memory" \ +) + +#define WBINVD() \ +__asm__ volatile \ +( \ + "ic iallu" \ + : \ + : \ + : "memory" \ +) + +#define SERIALIZE() \ +__asm__ volatile \ +( \ + "isb" \ + : \ + : \ + : "memory" \ +) + +#define RDTSC64(_mem64) \ +__asm__ volatile \ +( \ + "mrs %0 , cntvct_el0" \ + : "=r" (_mem64) \ + : \ + : "cc", "memory" \ +) + +#define ASM_RDTSC(_reg) \ + "# Read variant TSC." "\n\t" \ + "mrs " #_reg ", cntvct_el0" "\n\t" + +#define ASM_CODE_RDPMC(_ctr, _reg) \ + "# Read PMC counter." "\n\t" \ +/*TODO "movq $" #_ctr ", %%rcx" "\n\t" \ + "rdpmc" "\n\t" \ + "shlq $32 , %%rdx" "\n\t" \ + "orq %%rdx , %%rax" "\n\t" */ \ + "# Save counter value." "\n\t" \ +/*TODO "movq %%rax , %%" #_reg "\n\t" */ + +#define ASM_RDPMC(_ctr, _reg) ASM_CODE_RDPMC(_ctr, _reg) + +#define RDPMC(_ctr, _reg, _mem) \ +__asm__ volatile \ +( \ + ASM_CODE_RDPMC(_ctr, _reg) \ + "# Store values into memory." "\n\t" \ + "str " #_reg ", %0" \ + : "=m" (_mem) \ + : \ + : "%" #_reg"", \ + "cc", "memory" \ +) + +#define ASM_RDTSC_PMCx1(_reg0, _reg1, \ + _tsc_inst, mem_tsc, \ + _ctr1, _mem1) \ +__asm__ volatile \ +( \ + _tsc_inst(_reg0) \ + ASM_RDPMC(_ctr1, _reg1) \ + "# Store values into memory." "\n\t" \ + "str " #_reg0 ", %0" "\n\t" \ + "str " #_reg1 ", %1" \ + : "=m" (mem_tsc), "=m" (_mem1) \ + : \ + : "%" #_reg0"" , "%" #_reg1"", \ + "cc", "memory" \ +) + +#define RDTSC_PMCx1(mem_tsc, ...) \ +ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__) + +#if defined(LEGACY) && LEGACY > 0 + +#define _BITSET_GPR(_lock, _base, _offset) \ +({ \ + const __typeof__(_base) _shl = 1LLU << _offset; \ + const unsigned char _ret = ((_base) & (_shl)) != 0; \ + _base = (_base) | (_shl); \ + _ret; \ +}) + +#define _BITSET_IMM(_lock, _base, _imm6) \ +({ \ + const __typeof__(_base) _shl = 1LLU << _imm6; \ + const unsigned char _ret = ((_base) & (_shl)) != 0; \ + _base = (_base) | (_shl); \ + _ret; \ +}) + +#define _BITCLR_GPR(_lock, _base, _offset) \ +({ \ + const __typeof__(_base) _shl = 1LLU << _offset; \ + const unsigned char _ret = ((_base) & (_shl)) != 0; \ + _base = (_base) & ~(_shl); \ + _ret; \ +}) + +#define _BITCLR_IMM(_lock, _base, _imm6) \ +({ \ + const __typeof__(_base) _shl = 1LLU << _imm6; \ + const unsigned char _ret = ((_base) & (_shl)) != 0; \ + _base = (_base) & ~(_shl); \ + _ret; \ +}) + +#define _BIT_TEST_GPR(_base, _offset) \ +({ \ + const unsigned char _ret = ((_base) & (1LLU << _offset)) != 0; \ + _ret; \ +}) + +#define _BIT_TEST_IMM(_base, _imm6) \ +({ \ + const unsigned char _ret = ((_base) & (1LLU << _imm6)) != 0; \ + _ret; \ +}) + +#define _BITWISEAND(_lock, _opl, _opr) \ +({ \ + const Bit64 _dest __attribute__ ((aligned (8)))=(_opl) & (_opr);\ + _dest; \ +}) + +#define _BITWISEOR(_lock, _opl, _opr) \ +({ \ + const Bit64 _dest __attribute__ ((aligned (8)))=(_opl) | (_opr);\ + _dest; \ +}) + +#define _BITWISEXOR(_lock, _opl, _opr) \ +({ \ + const Bit64 _dest __attribute__ ((aligned (8)))=(_opl) ^ (_opr);\ + _dest; \ +}) + +#else /* LEGACY */ + +#define _BITSET_GPR(_lock, _base, _offset) \ +({ \ + const __typeof__(_base) *_adr = &_base; \ + volatile unsigned char _ret; \ + \ + __asm__ volatile \ + ( \ + "mov x12, #1" "\n\t" \ + "lsl x12, x12, %[offset]" "\n\t" \ + "ldr x13, %[base]" "\n\t" \ + "ldr x11, [x13]" "\n\t" \ + "tst x11, x12" "\n\t" \ + "cset w10, ne" "\n\t" \ + "orr x11, x11, x12" "\n\t" \ + "str x11, [x13]" "\n\t" \ + "strb w10, %[ret]" \ + : [ret] "=m" (_ret) \ + : [base] "m" (_adr), \ + [offset] "r" (_offset) \ + : "cc", "memory", "%w10", "%x11", "%x12", "%x13" \ + ); \ + _ret; \ +}) + +#define _BITSET_IMM(_lock, _base, _imm6) \ +({ \ + const __typeof__(_base) *_adr = &_base; \ + volatile unsigned char _ret; \ + \ + __asm__ volatile \ + ( \ + "mov x12, #1" "\n\t" \ + "lsl x12, x12, %[imm6]" "\n\t" \ + "ldr x13, %[base]" "\n\t" \ + "ldr x11, [x13]" "\n\t" \ + "tst x11, x12" "\n\t" \ + "cset w10, ne" "\n\t" \ + "orr x11, x11, x12" "\n\t" \ + "str x11, [x13]" "\n\t" \ + "strb w10, %[ret]" \ + : [ret] "=m" (_ret) \ + : [base] "m" (_adr), \ + [imm6] "i" (_imm6) \ + : "cc", "memory", "%w10", "%x11", "%x12", "%x13" \ + ); \ + _ret; \ +}) + +#define _BITCLR_GPR(_lock, _base, _offset) \ +({ \ + const __typeof__(_base) *_adr = &_base; \ + volatile unsigned char _ret; \ + \ + __asm__ volatile \ + ( \ + "mov x12, #1" "\n\t" \ + "lsl x12, x12, %[offset]" "\n\t" \ + "ldr x13, %[base]" "\n\t" \ + "ldr x11, [x13]" "\n\t" \ + "tst x11, x12" "\n\t" \ + "cset w10, ne" "\n\t" \ + "bic x11, x11, x12" "\n\t" \ + "str x11, [x13]" "\n\t" \ + "strb w10, %[ret]" \ + : [ret] "=m" (_ret) \ + : [base] "m" (_adr), \ + [offset] "r" (_offset) \ + : "cc", "memory", "%w10", "%x11", "%x12", "%x13" \ + ); \ + _ret; \ +}) + +#define _BITCLR_IMM(_lock, _base, _imm6) \ +({ \ + const __typeof__(_base) *_adr = &_base; \ + volatile unsigned char _ret; \ + \ + __asm__ volatile \ + ( \ + "mov x12, #1" "\n\t" \ + "lsl x12, x12, %[imm6]" "\n\t" \ + "ldr x13, %[base]" "\n\t" \ + "ldr x11, [x13]" "\n\t" \ + "tst x11, x12" "\n\t" \ + "cset w10, ne" "\n\t" \ + "bic x11, x11, x12" "\n\t" \ + "str x11, [x13]" "\n\t" \ + "strb w10, %[ret]" \ + : [ret] "=m" (_ret) \ + : [base] "m" (_adr), \ + [imm6] "i" (_imm6) \ + : "cc", "memory", "%w10", "%x11", "%x12", "%x13" \ + ); \ + _ret; \ +}) + +#define _BIT_TEST_GPR(_base, _offset) \ +({ \ + const __typeof__(_base) *_adr = &_base; \ + volatile unsigned char _ret; \ + \ + __asm__ volatile \ + ( \ + "mov x12, #1" "\n\t" \ + "lsl x12, x12, %[offset]" "\n\t" \ + "ldr x13, %[base]" "\n\t" \ + "ldr x11, [x13]" "\n\t" \ + "tst x11, x12" "\n\t" \ + "cset w10, ne" "\n\t" \ + "strb w10, %[ret]" \ + : [ret] "=m" (_ret) \ + : [base] "m" (_adr), \ + [offset] "r" (_offset) \ + : "cc", "memory", "%w10", "%x11", "%x12", "%x13" \ + ); \ + _ret; \ +}) + +#define _BIT_TEST_IMM(_base, _imm6) \ +({ \ + const __typeof__(_base) *_adr = &_base; \ + volatile unsigned char _ret; \ + \ + __asm__ volatile \ + ( \ + "mov x12, #1" "\n\t" \ + "lsl x12, x12, %[imm6]" "\n\t" \ + "ldr x13, %[base]" "\n\t" \ + "ldr x11, [x13]" "\n\t" \ + "tst x11, x12" "\n\t" \ + "cset w10, ne" "\n\t" \ + "strb w10, %[ret]" \ + : [ret] "=m" (_ret) \ + : [base] "m" (_adr), \ + [imm6] "i" (_imm6) \ + : "cc", "memory", "%w10", "%x11", "%x12", "%x13" \ + ); \ + _ret; \ +}) + +#define _BITWISEAND(_lock, _opl, _opr) \ +({ \ + volatile Bit64 _dest __attribute__ ((aligned (8))); \ + \ + __asm__ volatile \ + ( \ + "and x10, %[opl], %[opr]" "\n\t" \ + "str x10, %[dest]" \ + : [dest] "=m" (_dest) \ + : [opl] "Jr" (_opl), \ + [opr] "Jr" (_opr) \ + : "memory", "%x10" \ + ); \ + _dest; \ +}) + +#define _BITWISEOR(_lock, _opl, _opr) \ +({ \ + volatile Bit64 _dest __attribute__ ((aligned (8))); \ + \ + __asm__ volatile \ + ( \ + "orr x10, %[opl], %[opr]" "\n\t" \ + "str x10, %[dest]" \ + : [dest] "=m" (_dest) \ + : [opl] "Jr" (_opl), \ + [opr] "Jr" (_opr) \ + : "memory", "%x10" \ + ); \ + _dest; \ +}) + +#define _BITWISEXOR(_lock, _opl, _opr) \ +({ \ + volatile Bit64 _dest __attribute__ ((aligned (8))); \ + \ + __asm__ volatile \ + ( \ + "eor x10, %[opl], %[opr]" "\n\t" \ + "str x10, %[dest]" \ + : [dest] "=m" (_dest) \ + : [opl] "Jr" (_opl), \ + [opr] "Jr" (_opr) \ + : "memory", "%x10" \ + ); \ + _dest; \ +}) + +#endif /* LEGACY */ + +#define BITSET(_lock, _base, _offset) \ +( \ + __builtin_constant_p(_offset) ? \ + _BITSET_IMM(_lock, _base, _offset) \ + : _BITSET_GPR(_lock, _base, _offset) \ +) + +#define BITCLR(_lock, _base, _offset) \ +( \ + __builtin_constant_p(_offset) ? \ + _BITCLR_IMM(_lock, _base, _offset) \ + : _BITCLR_GPR(_lock, _base, _offset) \ +) + +#define BITVAL_2xPARAM(_base, _offset) \ +( \ + __builtin_constant_p(_offset) ? \ + _BIT_TEST_IMM(_base, _offset) \ + : _BIT_TEST_GPR(_base, _offset) \ +) + +#define BITVAL(...) BITVAL_2xPARAM( __VA_ARGS__ ) + +#define BITCPL(_src) \ +({ \ + unsigned long long _dest; \ + \ + __asm__ volatile \ + ( \ + "neg %x[dest], %x[src]" \ + : [dest] "=rQ" (_dest) \ + : [src] "Jr" (_src) \ + : "cc", "memory" \ + ); \ + _dest; \ +}) + +#define BITWISEAND(_lock, _opl, _opr) _BITWISEAND(_lock, _opl, _opr) +#define BITWISEOR(_lock, _opl, _opr) _BITWISEOR(_lock, _opl, _opr) +#define BITWISEXOR(_lock, _opl, _opr) _BITWISEXOR(_lock, _opl, _opr) + +#define BITSTOR(_lock, _dest, _src) \ +({ \ + __asm__ volatile \ + ( \ + "str %[src], %[dest]" \ + : [dest] "=Q" (_dest) \ + : [src] "r" (_src) \ + : "cc", "memory" \ + ); \ +}) + +#define BITZERO(_lock, _src) \ +({ \ + volatile unsigned char _ret = 0; \ + \ + __asm__ volatile \ + ( \ + "clz %x[ret], %x[src]" "\n\t" \ + "cmp %x[ret], #64" "\n\t" \ + "cset %x[ret], eq" \ + : [ret] "+r" (_ret) \ + : [src] "r" (_src) \ + : "cc", "memory" \ + ); \ + _ret; \ +}) + +#define BITBSF(_base, _index) \ +({ \ + register unsigned char _ret; \ + if (_base) { \ + _index = 0; \ + while (BITVAL(_base, _index) == 0) { \ + if (_index < (8 * sizeof(_base)) - 1) { \ + _index = _index + 1; \ + } else { \ + break; \ + } \ + } \ + _ret = 0; \ + } else { \ + _index = 0; \ + _ret = 1; \ + } \ + _ret; \ +}) + +#define BITBSR(_base, _index) \ +({ \ + register unsigned char _ret; \ + if (_base) { \ + _index = (8 * sizeof(_base)) - 1; \ + while (BITVAL(_base, _index) == 0) { \ + if (_index > 0) { \ + _index = _index - 1; \ + } else { \ + break; \ + } \ + } \ + _ret = 0; \ + } else { \ + _index = 0; \ + _ret = 1; \ + } \ + _ret; \ +}) + +#define BITEXTRZ(_src, _offset, _length) \ +({ \ + unsigned long long _dest = ((1 << _length) - 1) \ + & (_src >> _offset); \ + _dest; \ +}) + +#define BITWISESET(_lock, _opl, _opr) \ +({ \ + __asm__ volatile \ + ( \ + "ldr x10, %[opl]" "\n\t" \ + "orr x10, x10, %[opr]" "\n\t" \ + "str x10, %[opl]" "\n\t" \ + : [opl] "+m" (_opl) \ + : [opr] "Jr" (_opr) \ + : "memory", "%x10" \ + ); \ +}) + +#define BITWISECLR(_lock, _dest) \ +({ \ + __asm__ volatile \ + ( \ + "str xzr, %[dest]" \ + : [dest] "=m" (_dest) \ + : \ + : "memory" \ + ); \ +}) + +#if (CORE_COUNT == 64) +#define BITSET_CC(_lock, _base, _offset) BITSET(_lock, _base, _offset) +#else +#define BITSET_CC(_lock, _base, _offset) \ +( \ + BITSET(_lock, _base[ CORE_WORD_TOP(CORE_COUNT) \ + - CORE_WORD_POS(CORE_COUNT, _offset) ] ,\ + CORE_WORD_MOD(CORE_COUNT, _offset) ) \ +) +#endif + +#if (CORE_COUNT == 64) +#define BITCLR_CC(_lock, _base, _offset) BITCLR(_lock, _base, _offset) +#else +#define BITCLR_CC(_lock, _base, _offset) \ +( \ + BITCLR(_lock, _base[ CORE_WORD_TOP(CORE_COUNT) \ + - CORE_WORD_POS(CORE_COUNT, _offset) ] ,\ + CORE_WORD_MOD(CORE_COUNT, _offset) ) \ +) +#endif + +#if (CORE_COUNT == 64) +#define BITVAL_CC(_base, _offset) BITVAL(_base, _offset) +#else +#define BITVAL_CC(_base, _offset) \ +( \ + BITVAL(_base[CORE_WORD_TOP(CORE_COUNT) \ + - CORE_WORD_POS(CORE_COUNT, _offset)], \ + CORE_WORD_MOD(CORE_COUNT, _offset) ) \ +) +#endif + +#if (CORE_COUNT == 64) +#define BITWISEAND_CC(_lock, _opl, _opr) BITWISEAND(_lock, _opl, _opr) +#else +#define BITWISEAND_CC(_lock, _opl, _opr) \ +({ \ + volatile Bit64 _ret __attribute__ ((aligned (8))) = 0; \ + unsigned int cw = 0; \ + do { \ + _ret |= _BITWISEAND(_lock, _opl[cw], _opr[cw]) ; \ + } while (++cw <= CORE_WORD_TOP(CORE_COUNT)); \ + _ret; \ +}) +#endif + +#if (CORE_COUNT == 64) +#define BITSTOR_CC(_lock, _dest, _src) BITSTOR(_lock, _dest, _src) +#else +#define BITSTOR_CC(_lock, _dest, _src) \ +({ \ + unsigned int cw = 0; \ + do { \ + BITSTOR(_lock, _dest[cw], _src[cw]); \ + } while (++cw <= CORE_WORD_TOP(CORE_COUNT)); \ +}) +#endif + +#define ASM_CMPXCHG16B( _lock, _ret, _tmp, \ + _val0, _val1, _reg0, _reg1, _off0, _off1 ) \ + "add " #_tmp " , " #_reg0 ", #" #_off0"\n\t" \ + "ldr " #_val0 " , [" #_tmp "]" "\n\t" \ + \ + "add " #_tmp " , " #_reg1 ", #" #_off0"\n\t" \ + "ldr " #_val1 " , [" #_tmp "]" "\n\t" \ + \ + "cmp " #_val0 " , " #_val1 "\n\t" \ + "cset " #_ret " , eq" "\n\t" \ + \ + "add " #_tmp " , " #_reg0 ", #" #_off1"\n\t" \ + "ldr " #_val0 " , [" #_tmp "]" "\n\t" \ + \ + "add " #_tmp " , " #_reg1 ", #" #_off1"\n\t" \ + "ldr " #_val1 " , [" #_tmp "]" "\n\t" \ + \ + "cmp " #_val0 " , " #_val1 "\n\t" \ + "cset " #_tmp " , eq" "\n\t" \ + \ + "and " #_ret " , " #_ret ", " #_tmp "\n\t" + +#if defined(LEGACY) && (LEGACY > 0) +FEAT_MSG("LEGACY Level 1: BITCMP_CC() built without asm cmpxchg16b") + +#if (CORE_COUNT == 64) +#error "LEGACY Level 1: Unimplemented BITCMP_CC() and CORE_COUNT(64)" +#else +#define BITCMP_CC(_lock, _opl, _opr) \ +({ \ + unsigned char ret = 1; \ + unsigned int cw = 0; \ + do { \ + volatile unsigned char _ret; \ + \ + __asm__ volatile \ + ( \ + "cmp %[opr] , %[opl]" "\n\t" \ + "cset %[ret] , eq" \ + : [ret] "=r" (_ret) \ + : [opl] "r" (_opl[cw]), \ + [opr] "r" (_opr[cw]) \ + : "cc", "memory" \ + ); \ + ret &= _ret; \ + } while (++cw <= CORE_WORD_TOP(CORE_COUNT)); \ + ret; \ +}) +#endif +/* --- --- --- cmpxchg16b --- --- --- */ +#elif (CORE_COUNT == 64) + +#define BITCMP_CC(_lock, _opl, _opr) \ +({ \ + volatile unsigned char _ret; \ + \ + __asm__ volatile \ + ( \ + "ldr x14 , %[opr]" "\n\t" \ + "ldr x15 , %[opl]" "\n\t" \ + "cmp x14 , x15" "\n\t" \ + "cset %[ret] , eq" \ + : [ret] "=r" (_ret) \ + : [opl] "m" (_opl), \ + [opr] "m" (_opr) \ + : "cc", "memory", "%x14", "%x15" \ + ); \ + _ret; \ +}) + +#elif (CORE_COUNT == 128) + +#define BITCMP_CC(_lock, _opl, _opr) \ +({ \ + volatile unsigned char _ret; \ + \ + __asm__ volatile \ + ( \ + "mov x14 , %[opr]" "\n\t" \ + "mov x15 , %[opl]" "\n\t" \ + ASM_CMPXCHG16B(_lock, x12,x11,x9,x10,x14,x15, 0, 8)"\n\t"\ + "str x12 , %[ret]" \ + : [ ret] "+m" (_ret) \ + : [ opl] "r" (_opl), \ + [ opr] "r" (_opr) \ + : "cc", "memory", \ + "%x9", "%x10", "%x11", "%x12", "%x14", "%x15" \ + ); \ + _ret; \ +}) + +#elif (CORE_COUNT == 256) + +#define BITCMP_CC(_lock, _opl, _opr) \ +({ \ + volatile unsigned char _ret; \ + \ + __asm__ volatile \ + ( \ + "mov x14 , %[opr]" "\n\t" \ + "mov x15 , %[opl]" "\n\t" \ + ASM_CMPXCHG16B(_lock, x13,x11,x9,x10,x14,x15,16,24)"\n\t"\ + ASM_CMPXCHG16B(_lock, x12,x11,x9,x10,x14,x15, 0, 8)"\n\t"\ + "and x12 , x12 , x13" "\n\t" \ + "str x12 , %[ret]" \ + : [ ret] "+m" (_ret) \ + : [ opl] "r" (_opl), \ + [ opr] "r" (_opr) \ + : "cc", "memory", \ + "%x9", "%x10", "%x11", "%x12", "%x13", "%x14", "%x15" \ + ); \ + _ret; \ +}) + +#elif (CORE_COUNT == 512) + +#define BITCMP_CC(_lock, _opl, _opr) \ +({ \ + volatile unsigned char _ret; \ + \ + __asm__ volatile \ + ( \ + "mov x14 , %[opr]" "\n\t" \ + "mov x15 , %[opl]" "\n\t" \ + ASM_CMPXCHG16B(_lock, x13,x11,x9,x10,x14,x15,48,56)"\n\t"\ + ASM_CMPXCHG16B(_lock, x12,x11,x9,x10,x14,x15,32,40)"\n\t"\ + "and x12 , x12 , x13" "\n\t" \ + ASM_CMPXCHG16B(_lock, x13,x11,x9,x10,x14,x15,16,24)"\n\t"\ + "and x12 , x12 , x13" "\n\t" \ + ASM_CMPXCHG16B(_lock, x13,x11,x9,x10,x14,x15, 0, 8)"\n\t"\ + "and x12 , x12 , x13" "\n\t" \ + "str x12 , %[ret]" \ + : [ ret] "+m" (_ret) \ + : [ opl] "r" (_opl), \ + [ opr] "r" (_opr) \ + : "cc", "memory", \ + "%x9", "%x10", "%x11", "%x12", "%x13", "%x14", "%x15" \ + ); \ + _ret; \ +}) + +#elif (CORE_COUNT == 1024) + +#define BITCMP_CC(_lock, _opl, _opr) \ +({ \ + volatile unsigned char _ret; \ + \ + __asm__ volatile \ + ( \ + "mov x14 , %[opr]" "\n\t" \ + "mov x15 , %[opl]" "\n\t" \ + ASM_CMPXCHG16B(_lock, x13,x11,x9,x10,x14,x15,112,120)"\n\t"\ + ASM_CMPXCHG16B(_lock, x12,x11,x9,x10,x14,x15,96,104) "\n\t"\ + "and x12 , x12 , x13" "\n\t" \ + ASM_CMPXCHG16B(_lock, x13,x11,x9,x10,x14,x15,80,88)"\n\t"\ + "and x12 , x12 , x13" "\n\t" \ + ASM_CMPXCHG16B(_lock, x13,x11,x9,x10,x14,x15,64,72)"\n\t"\ + "and x12 , x12 , x13" "\n\t" \ + ASM_CMPXCHG16B(_lock, x13,x11,x9,x10,x14,x15,48,56)"\n\t"\ + "and x12 , x12 , x13" "\n\t" \ + ASM_CMPXCHG16B(_lock, x13,x11,x9,x10,x14,x15,32,40)"\n\t"\ + "and x12 , x12 , x13" "\n\t" \ + ASM_CMPXCHG16B(_lock, x13,x11,x9,x10,x14,x15,16,24)"\n\t"\ + "and x12 , x12 , x13" "\n\t" \ + ASM_CMPXCHG16B(_lock, x13,x11,x9,x10,x14,x15, 0, 8)"\n\t"\ + "and x12 , x12 , x13" "\n\t" \ + "str x12 , %[ret]" \ + : [ ret] "+m" (_ret) \ + : [ opl] "r" (_opl), \ + [ opr] "r" (_opr) \ + : "cc", "memory", \ + "%x9", "%x10", "%x11", "%x12", "%x13", "%x14", "%x15" \ + ); \ + _ret; \ +}) + +#endif /* LEGACY */ + +/* Micro-benchmark. Prerequisites: CPU affinity, RDTSC[P] optionnaly RDPMC */ +#if defined(UBENCH) && UBENCH == 1 + +#define UBENCH_DECLARE() \ +static unsigned long long uBenchCounter[2][4] __attribute__((aligned(8)))=\ +{ \ +/* TSC*/{0, 0, 0, 0}, \ +/*INST*/{0, 0, 0, 0} \ +/* [0]DELTA, [1]PREV, [2]LAST, [3]OVERHEAD */ \ +}; \ + \ +inline static void UBENCH_RDCOUNTER_VOID(unsigned int idx) {} \ + \ +inline static void UBENCH_With_RDTSC_No_RDPMC(unsigned int idx) \ +{ \ + RDTSC64(uBenchCounter[0][idx]) ; SERIALIZE(); \ +} \ + \ +inline static void UBENCH_With_RDTSCP_RDPMC(unsigned int idx) \ +{ \ + RDTSCP_PMCx1( uBenchCounter[0][idx], \ + 0x40000000, \ + uBenchCounter[1][idx]) ; \ +} \ + \ + \ +inline static void UBENCH_With_RDTSC_RDPMC(unsigned int idx) \ +{ \ + RDTSC_PMCx1( uBenchCounter[0][idx], \ + 0x40000000, \ + uBenchCounter[1][idx]) ; \ +} \ + \ +static void (*UBENCH_RDCOUNTER)(unsigned int) = UBENCH_RDCOUNTER_VOID; + +#define UBENCH_COMPUTE() \ +({ \ + uBenchCounter[0][0] = uBenchCounter[0][2] - uBenchCounter[0][1];\ + uBenchCounter[1][0] = uBenchCounter[1][2] - uBenchCounter[1][1];\ + uBenchCounter[0][0] -= uBenchCounter[0][3]; \ + uBenchCounter[1][0] -= uBenchCounter[1][3]; \ +}) + +#define UBENCH_METRIC(metric) (uBenchCounter[metric][0]) + +#define UBENCH_SETUP(withRDTSCP , withRDPMC) \ +({ \ + void (*MatrixCallFunc[2][2])(unsigned int) = { \ + {UBENCH_With_RDTSC_No_RDPMC, UBENCH_With_RDTSC_RDPMC}, \ + {UBENCH_With_RDTSCP_No_RDPMC,UBENCH_With_RDTSCP_RDPMC} \ + }; \ + UBENCH_RDCOUNTER = MatrixCallFunc[withRDTSCP][withRDPMC]; \ + \ + UBENCH_RDCOUNTER(0); \ + UBENCH_RDCOUNTER(3); \ + \ + uBenchCounter[0][0] = uBenchCounter[0][3]- uBenchCounter[0][0]; \ + uBenchCounter[1][0] = uBenchCounter[1][3]- uBenchCounter[1][0]; \ + uBenchCounter[0][3] = uBenchCounter[0][0]; \ + uBenchCounter[1][3] = uBenchCounter[1][0]; \ +}) + +#else /* UBENCH == 1 */ + +#define UBENCH_DECLARE() /* UBENCH_DECLARE() */ +#define UBENCH_RDCOUNTER(idx) /* UBENCH_RDCOUNTER() */ +#define UBENCH_COMPUTE() /* UBENCH_COMPUTE() */ +#define UBENCH_METRIC(metric) /* UBENCH_METRIC() */ +#define UBENCH_SETUP(withTSCP , withPMC) /* UBENCH_SETUP() */ + +#endif /* UBENCH == 1 */ diff --git a/aarch64/corefreq-api.h b/aarch64/corefreq-api.h new file mode 100644 index 00000000..24e48297 --- /dev/null +++ b/aarch64/corefreq-api.h @@ -0,0 +1,406 @@ +/* + * CoreFreq + * Copyright (C) 2015-2024 CYRIL COURTIAT + * Licenses: GPL2 + */ + +#define DRV_DEVNAME "corefreqk" +#define DRV_FILENAME "/dev/"DRV_DEVNAME + +#define ID_RO_VMA_PROC (CORE_COUNT + 0) +#define ID_RW_VMA_PROC (CORE_COUNT + ID_RO_VMA_PROC) +#define ID_RO_VMA_GATE (CORE_COUNT + ID_RW_VMA_PROC) +#define ID_RO_VMA_CORE (CORE_COUNT + ID_RO_VMA_GATE) +#define ID_RW_VMA_CORE (CORE_COUNT + ID_RO_VMA_CORE) +#define ID_ANY_VMA_JAIL (CORE_COUNT + ID_RW_VMA_CORE) + +#define WAKEUP_RATIO 4 +#define LOOP_MIN_MS 100 +#define LOOP_MAX_MS ((1000 - 1) * WAKEUP_RATIO) +#define LOOP_DEF_MS 1000 +#define TICK_DEF_MS 2000 + +typedef struct +{ + struct { + unsigned int PN : 12-0, + BSP : 32-12; + }; + signed int MPID, + CoreID, + ThreadID, + PackageID; + struct CLUSTER_ST Cluster; + struct CACHE_INFO + { + union CCSIDR + { + unsigned long long value; + struct + { + unsigned long long + LineSz : 3-0, + Assoc : 13-3, + Set : 28-13, + WrAlloc : 29-28, + RdAlloc : 30-29, + WrBack : 31-30, + WrThrough : 32-31, + RES0 : 64-32; + }; + } ccsid; + unsigned int Size; + } Cache[CACHE_MAX_LEVEL]; +} CACHE_TOPOLOGY; + +typedef struct +{ + THERMAL_PARAM Param; + unsigned int Sensor; + signed int VID; + struct { + enum THERM_PWR_EVENTS Events[eDIM]; + }; + HWP_CAPABILITIES HWP_Capabilities; + HWP_INTERRUPT HWP_Interrupt; + HWP_REQUEST HWP_Request; + struct ACPI_CPPC_STRUCT { + unsigned short Highest, + Guaranteed, + Efficient, + Lowest, + Minimum, + Maximum, + Desired, + Energy; + } ACPI_CPPC; +} POWER_THERMAL; + +/* ACPI/OSPM + + Highest Performance ... .------, + |######| + |######| + Nominal Performance ... |------| .. + |//////| \ + |//////| : + |//////| : + |//////| : + |//////| --- Guaranteed Performance +Lowest Nonlinear Performance .. -------- : Allowed Range + |OOOOOO| : + |OOOOOO| : + |OOOOOO| : + Lowest Performance .... -------- ../ + |++++++| + |++++++| + |++++++| + 0 ..... `------' +*/ + +typedef struct +{ + Bit64 OffLine __attribute__ ((aligned (8))); + + struct + { + unsigned long long TSC; + } Overhead __attribute__ ((aligned (8))); + + struct + { + unsigned long long INST; + struct + { + unsigned long long + UCC, + URC; + } C0; + unsigned long long + C3, + C6, + C7, + TSC; + + unsigned long long C1; + + struct + { + unsigned long long ACCU; + } Power; + } Counter[2] __attribute__ ((aligned (8))); + + struct + { + unsigned long long + C1, + C2, + C3, + C4, + C5, + C6, + C7; + } VPMC __attribute__ ((aligned (8))); + + struct + { + unsigned long long + INST; + struct + { + unsigned long long + UCC, + URC; + } C0; + unsigned long long + C3, + C6, + C7, + TSC, + C1; + + struct + { + unsigned long long ACCU; + } Power; + + unsigned int SMI; + } Delta __attribute__ ((aligned (8))); + + POWER_THERMAL PowerThermal; + THERMAL_POINT ThermalPoint; + + struct + { + unsigned int SMI; + struct { + unsigned int + LOCAL, + UNKNOWN, + PCISERR, + IOCHECK; + } NMI; + } Interrupt; + + struct + { + struct { + unsigned long long + CfgLock : 1-0, /* Core */ + IORedir : 2-1, /* Core */ + SCTLRX : 3-2, /* Thread */ + Unused : 32-3, + Revision: 64-32; + }; + unsigned short int CStateLimit; + unsigned short int CStateBaseAddr; /* Any I/O BAR */ + } Query; + + CACHE_TOPOLOGY T; + + struct { + Bit64 FLAGS __attribute__ ((aligned (8))); + Bit64 SCTLR __attribute__ ((aligned (8))); + Bit64 SCTLR2 __attribute__ ((aligned (8))); + Bit64 EL __attribute__ ((aligned (8))); + Bit64 FPSR __attribute__ ((aligned (8))); + Bit64 SVCR __attribute__ ((aligned (8))); + } SystemRegister; + + unsigned int Bind; + + CLOCK Clock; + + unsigned int Boost[BOOST(SIZE)]; + + COF_UNION Ratio; +} CORE_RO; + +typedef struct +{ + struct /* 64-byte cache line size. */ + { + Bit64 V, + _pad[7]; + } Sync __attribute__ ((aligned (8))); + +} CORE_RW; + +typedef struct +{ + struct { + union { + } DIMM[MC_MAX_DIMM]; + } Channel[MC_MAX_CHA]; + + union { + } MaxDIMMs; + + unsigned short SlotCount, ChannelCount; +} MC_REGISTERS; + +typedef struct +{ +} BUS_REGISTERS; + + +typedef struct { + int taskCount; + TASK_MCB taskList[TASK_LIMIT]; + + unsigned int kernelVersionNumber; + + char sysname[MAX_UTS_LEN], + release[MAX_UTS_LEN], + version[MAX_UTS_LEN], + machine[MAX_UTS_LEN]; +} SYSGATE_RO; /* RO Pages */ + +#define CHIP_MAX_PCI 24 + +typedef struct +{ + struct + { + unsigned long long PCLK; /* Contextual Clock [TSC|UCLK|MCLK] */ + struct { + unsigned long long PC02, + PC03, + PC04, + PC06, + PC07, + PC08, + PC09, + PC10; + }; + unsigned long long MC6; + + struct { + unsigned long long FC0; /* Uncore fixed counter #0 */ + } Uncore; + + struct { + unsigned long long ACCU[PWR_DOMAIN(SIZE)]; + } Power; + } Counter[2] __attribute__ ((aligned (8))); + + struct + { + unsigned long long PCLK; + struct { + unsigned long long PC02, + PC03, + PC04, + PC06, + PC07, + PC08, + PC09, + PC10; + }; + unsigned long long MC6; + + struct { + unsigned long long FC0; + } Uncore; + } Delta __attribute__ ((aligned (8))); + + FEATURES Features; + + BitCC CR_Mask __attribute__ ((aligned (16))); + BitCC HWP_Mask __attribute__ ((aligned (16))); + BitCC SPEC_CTRL_Mask __attribute__ ((aligned (16))); + + enum THERMAL_FORMULAS thermalFormula; + enum VOLTAGE_FORMULAS voltageFormula; + enum POWER_FORMULAS powerFormula; + + unsigned int SleepInterval, + tickReset, + tickStep; + + struct { + unsigned int Count, + OnLine; + } CPU; + + SERVICE_PROC Service; + + signed int ArchID; + + struct { + CLUSTERCFR ClusterCfg; + CLUSTERIDR ClusterRev; + + unsigned int Boost[UNCORE_BOOST(SIZE)]; + BUS_REGISTERS Bus; + MC_REGISTERS MC[MC_MAX_CTRL]; + unsigned short CtrlCount; + struct CHIP_ST { + unsigned short VID, DID; + } Chip[CHIP_MAX_PCI]; + } Uncore; + + struct { + THERMAL_PARAM Param; + unsigned int Sensor; + struct { + signed int CPU, SOC; + } VID; + + enum THERM_PWR_EVENTS Events[eDIM]; + + struct { + unsigned short Minimum, + Maximum; + } ACPI_CPPC; + } PowerThermal; + + THERMAL_POINT ThermalPoint; + + struct { + struct { + size_t Size; + int Order; + } ReqMem; + } Gate; + + OS_DRIVER OS; + + struct { + Bit64 NMI; + signed int AutoClock, + Experimental, + HotPlug, + PCI; + KERNEL_DRIVER Driver; + } Registration; + + enum HYPERVISOR HypervisorID; + char Architecture[CODENAME_LEN]; + + SMBIOS_ST SMB; + + FOOTPRINT FootPrint; +} PROC_RO; /* RO Pages */ + +typedef struct +{ + struct + { + struct { + unsigned long long ACCU[PWR_DOMAIN(SIZE)]; + } Power; + } Delta __attribute__ ((aligned (8))); + + BitCC HWP __attribute__ ((aligned (16))); + BitCC VM __attribute__ ((aligned (16))); + BitCC CLRBHB __attribute__ ((aligned (16))); + BitCC CSV2_1 __attribute__ ((aligned (16))); + BitCC CSV2_2 __attribute__ ((aligned (16))); + BitCC CSV2_3 __attribute__ ((aligned (16))); + BitCC CSV3 __attribute__ ((aligned (16))); + BitCC SSBS __attribute__ ((aligned (16))); + struct { + Bit64 Signal __attribute__ ((aligned (8))); + } OS; +} PROC_RW; /* RW Pages */ diff --git a/corefreq-cli-extra.c b/aarch64/corefreq-cli-extra.c similarity index 99% rename from corefreq-cli-extra.c rename to aarch64/corefreq-cli-extra.c index 290a581a..2d832e92 100644 --- a/corefreq-cli-extra.c +++ b/aarch64/corefreq-cli-extra.c @@ -1,5 +1,5 @@ /* - * CoreFreq (C) 2015-2023 CYRIL COURTIAT + * CoreFreq (C) 2015-2024 CYRIL COURTIAT * Contributors: Andrew Gurinovich ; CyrIng * Licenses: GPL2 * diff --git a/corefreq-cli-extra.h b/aarch64/corefreq-cli-extra.h similarity index 95% rename from corefreq-cli-extra.h rename to aarch64/corefreq-cli-extra.h index f443528a..48854e9f 100644 --- a/corefreq-cli-extra.h +++ b/aarch64/corefreq-cli-extra.h @@ -1,5 +1,5 @@ /* - * CoreFreq (C) 2015-2023 CYRIL COURTIAT + * CoreFreq (C) 2015-2024 CYRIL COURTIAT * Contributors: Andrew Gurinovich ; CyrIng * Licenses: GPL2 * diff --git a/aarch64/corefreq-cli-json.c b/aarch64/corefreq-cli-json.c new file mode 100644 index 00000000..0b3e3272 --- /dev/null +++ b/aarch64/corefreq-cli-json.c @@ -0,0 +1,1446 @@ +/* + * CoreFreq (C) 2015-2024 CYRIL COURTIAT + * Contributors: CyrIng + * Licenses: GPL2 + */ + +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include + +#include "bitasm.h" +#include "coretypes.h" +#include "corefreq.h" +#include "corefreq-ui.h" +#include "corefreq-cli-rsc.h" +#include "corefreq-cli.h" +#include "corefreq-cli-json.h" +#include "corefreq-cli-extra.h" + +double timespecFloat(struct timespec time) +{ + return (double) time.tv_sec + (time.tv_nsec / 1000000000.0); +} + +void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm)) +{ + char hexStr[32]; + signed int i = 0, i2 = 0, i3 = 0; + unsigned int cpu; + struct json_state s = { .depth = 0, .nested_state = {0}, + .write = json_writer_stdout }; + json_start_object(&s); + json_key(&s, "Registration"); + { + json_start_object(&s); + json_key(&s, "AutoClock"); + json_literal(&s, "%d", RO(Shm)->Registration.AutoClock); + json_key(&s, "Experimental"); + json_literal(&s, "%d", RO(Shm)->Registration.Experimental); + json_key(&s, "HotPlug"); + json_literal(&s, "%d", !(RO(Shm)->Registration.HotPlug < 0)); + json_key(&s, "PCI"); + json_literal(&s, "%d", RO(Shm)->Registration.PCI); + json_key(&s, "Interrupt"); + { + json_start_object(&s); + json_key(&s, "NMI_LOCAL"); + json_literal(&s, "%u", BITVAL(RO(Shm)->Registration.NMI, BIT_NMI_LOCAL)); + json_key(&s, "NMI_UNKNOWN"); + json_literal(&s, "%u", BITVAL(RO(Shm)->Registration.NMI, BIT_NMI_UNKNOWN)); + json_key(&s, "NMI_SERR"); + json_literal(&s, "%u", BITVAL(RO(Shm)->Registration.NMI, BIT_NMI_SERR)); + json_key(&s, "NMI_IO_CHECK"); + json_literal(&s, "%u", BITVAL(RO(Shm)->Registration.NMI, BIT_NMI_IO_CHECK)); + json_end_object(&s); + } + json_key(&s, "IdleRoute"); + json_literal(&s, "%d", RO(Shm)->Registration.Driver.Route); + json_key(&s, "CPUidle"); + json_literal(&s, "%hu", RO(Shm)->Registration.Driver.CPUidle); + json_key(&s, "CPUfreq"); + json_literal(&s, "%hu", RO(Shm)->Registration.Driver.CPUfreq); + json_key(&s, "Governor"); + json_literal(&s, "%hu", RO(Shm)->Registration.Driver.Governor); + json_key(&s, "ClockSource"); + json_literal(&s, "%hu", RO(Shm)->Registration.Driver.CS); + json_key(&s, "Scope"); + { + json_start_object(&s); + snprintf(hexStr, 32, "0x%x", RO(Shm)->Proc.thermalFormula); + json_key(&s, "Thermal"); + json_string(&s, hexStr); + snprintf(hexStr, 32, "0x%x", RO(Shm)->Proc.voltageFormula); + json_key(&s, "Voltage"); + json_string(&s, hexStr); + snprintf(hexStr, 32, "0x%x", RO(Shm)->Proc.powerFormula); + json_key(&s, "Power"); + json_string(&s, hexStr); + json_end_object(&s); + } + json_end_object(&s); + } + if (BITWISEAND(LOCKLESS, RO(Shm)->SysGate.Operation, 0x1)) + { + json_key(&s, "SysGate"); + { + json_start_object(&s); + + json_key(&s, "tickReset"); + json_literal(&s, "%u", RO(Shm)->SysGate.tickReset); + json_key(&s, "tickStep"); + json_literal(&s, "%u", RO(Shm)->SysGate.tickStep); + json_key(&s, "trackTask"); + json_literal(&s, "%d", RO(Shm)->SysGate.trackTask); + json_key(&s, "sortByField"); + json_literal(&s, "%d", RO(Shm)->SysGate.sortByField); + json_key(&s, "reverseOrder"); + json_literal(&s, "%d", RO(Shm)->SysGate.reverseOrder); + json_key(&s, "taskCount"); + json_literal(&s, "%d", RO(Shm)->SysGate.taskCount); + json_key(&s, "taskList"); + + json_start_arr(&s); + for (i = 0; i < RO(Shm)->SysGate.taskCount; i++) { + json_start_object(&s); + + json_key(&s, "runtime"); + json_literal(&s, "%llu", RO(Shm)->SysGate.taskList[i].runtime); + json_key(&s, "usertime"); + json_literal(&s, "%llu", RO(Shm)->SysGate.taskList[i].usertime); + json_key(&s, "systime"); + json_literal(&s, "%llu", RO(Shm)->SysGate.taskList[i].systime); + + json_key(&s, "pid"); + json_literal(&s, "%d", RO(Shm)->SysGate.taskList[i].pid); + json_key(&s, "tgid"); + json_literal(&s, "%d", RO(Shm)->SysGate.taskList[i].tgid); + json_key(&s, "ppid"); + json_literal(&s, "%d", RO(Shm)->SysGate.taskList[i].ppid); + + json_key(&s, "state"); + json_literal(&s, "%hu", RO(Shm)->SysGate.taskList[i].state); + json_key(&s, "wake_cpu"); + json_literal(&s, "%hu", RO(Shm)->SysGate.taskList[i].wake_cpu); + json_key(&s, "comm"); + json_string(&s, RO(Shm)->SysGate.taskList[i].comm); + + json_end_object(&s); + } + json_end_arr(&s); + + json_key(&s, "memInfo"); + { + json_start_object(&s); + json_key(&s, "totalram"); + json_literal(&s, "%llu", RO(Shm)->SysGate.memInfo.totalram); + json_key(&s, "sharedram"); + json_literal(&s, "%llu", RO(Shm)->SysGate.memInfo.sharedram); + json_key(&s, "freeram"); + json_literal(&s, "%llu", RO(Shm)->SysGate.memInfo.freeram); + json_key(&s, "bufferram"); + json_literal(&s, "%llu", RO(Shm)->SysGate.memInfo.bufferram); + json_key(&s, "totalhigh"); + json_literal(&s, "%llu", RO(Shm)->SysGate.memInfo.totalhigh); + json_key(&s, "freehigh"); + json_literal(&s, "%llu", RO(Shm)->SysGate.memInfo.freehigh); + json_end_object(&s); + } + + json_key(&s, "kernel"); + { + json_start_object(&s); + json_key(&s, "version"); + json_literal(&s, "%u", RO(Shm)->SysGate.kernel.version); + json_key(&s, "major"); + json_literal(&s, "%u", RO(Shm)->SysGate.kernel.major); + json_key(&s, "minor"); + json_literal(&s, "%u", RO(Shm)->SysGate.kernel.minor); + json_end_object(&s); + } + json_key(&s, "sysname"); + json_string(&s, RO(Shm)->SysGate.sysname); + json_key(&s, "release"); + json_string(&s, RO(Shm)->SysGate.release); + json_key(&s, "version"); + json_string(&s, RO(Shm)->SysGate.version); + json_key(&s, "machine"); + json_string(&s, RO(Shm)->SysGate.machine); + + json_key(&s, "SubDriver"); + { + json_start_object(&s); + + if (strlen(RO(Shm)->CS.array) > 0) { + json_key(&s, "Clock_Source"); + json_string(&s, RO(Shm)->CS.array); + } + if (strlen(RO(Shm)->SysGate.OS.FreqDriver.Name) > 0) { + json_key(&s, "CPU_Freq"); + json_string(&s, RO(Shm)->SysGate.OS.FreqDriver.Name); + } + if (strlen(RO(Shm)->SysGate.OS.FreqDriver.Governor) > 0) { + json_key(&s, "Governor"); + json_string(&s, RO(Shm)->SysGate.OS.FreqDriver.Governor); + } + if (strlen(RO(Shm)->SysGate.OS.IdleDriver.Name) > 0) { + json_key(&s, "CPU_Idle"); + json_string(&s, RO(Shm)->SysGate.OS.IdleDriver.Name); + } + + json_end_object(&s); + } + + json_end_object(&s); + } + } + json_key(&s, "Sleep"); + { + json_start_object(&s); + json_key(&s, "Interval"); + json_literal(&s, "%u", RO(Shm)->Sleep.Interval); + json_key(&s, "pollingWait"); + json_literal(&s, "%f", timespecFloat(RO(Shm)->Sleep.pollingWait)); + json_key(&s, "ringWaiting"); + json_literal(&s, "%f", timespecFloat(RO(Shm)->Sleep.ringWaiting)); + json_key(&s, "childWaiting"); + json_literal(&s, "%f", timespecFloat(RO(Shm)->Sleep.childWaiting)); + json_key(&s, "sliceWaiting"); + json_literal(&s, "%f", timespecFloat(RO(Shm)->Sleep.sliceWaiting)); + json_end_object(&s); + } + + json_key(&s, "ShmName"); + json_string(&s, RO(Shm)->ShmName); + json_key(&s, "App"); + { + json_start_object(&s); + json_key(&s, "Svr"); + json_literal(&s, "%d", RO(Shm)->App.Svr); + json_key(&s, "Cli"); + json_literal(&s, "%d", RO(Shm)->App.Cli); + json_key(&s, "GUI"); + json_literal(&s, "%d", RO(Shm)->App.GUI); + json_end_object(&s); + } + json_key(&s, "Uncore"); + { + json_start_object(&s); + json_key(&s, "Boost"); + { + json_start_arr(&s); + for (i = 0; i < UNCORE_RATIO_SIZE; i++) { + json_literal(&s, "%u", RO(Shm)->Uncore.Boost[i]); + } + json_end_arr(&s); + } + json_key(&s, "Bus"); + { + json_start_object(&s); + json_key(&s, "Speed"); + json_literal(&s, "%u", RO(Shm)->Uncore.Bus.Speed); + json_key(&s, "Rate"); + json_literal(&s, "%u", RO(Shm)->Uncore.Bus.Rate); + json_end_object(&s); + } + + json_key(&s, "MC"); + json_start_arr(&s); + for (i = 0; i < MC_MAX_CTRL; i++) { + { + json_start_object(&s); + json_key(&s, "Channel"); + json_start_arr(&s); + { + for (i2 = 0; i2 < MC_MAX_CHA; i2++) { + json_start_object(&s); + json_key(&s, "Timing"); + { + json_start_object(&s); + json_key(&s, "tCL"); + json_literal(&s, "%u", RO(Shm)->Uncore.MC[i].Channel[i2].Timing.tCL); + json_key(&s, "tRCD_R"); + json_literal(&s, "%u", RO(Shm)->Uncore.MC[i].Channel[i2].Timing.tRCD_RD); + json_key(&s, "tRCD_W"); + json_literal(&s, "%u", RO(Shm)->Uncore.MC[i].Channel[i2].Timing.tRCD_WR); + json_key(&s, "tRP"); + json_literal(&s, "%u", RO(Shm)->Uncore.MC[i].Channel[i2].Timing.tRP); + json_key(&s, "tRAS"); + json_literal(&s, "%u", RO(Shm)->Uncore.MC[i].Channel[i2].Timing.tRAS); + json_key(&s, "tRRD"); + json_literal(&s, "%u", RO(Shm)->Uncore.MC[i].Channel[i2].Timing.tRRD); + json_key(&s, "tRFC"); + json_literal(&s, "%u", RO(Shm)->Uncore.MC[i].Channel[i2].Timing.tRFC); + json_key(&s, "tWR"); + json_literal(&s, "%u", RO(Shm)->Uncore.MC[i].Channel[i2].Timing.tWR); + json_key(&s, "tRTPr"); + json_literal(&s, "%u", RO(Shm)->Uncore.MC[i].Channel[i2].Timing.tRTPr); + json_key(&s, "tWTPr"); + json_literal(&s, "%u", RO(Shm)->Uncore.MC[i].Channel[i2].Timing.tWTPr); + json_key(&s, "tFAW"); + json_literal(&s, "%u", RO(Shm)->Uncore.MC[i].Channel[i2].Timing.tFAW); + json_key(&s, "B2B"); + json_literal(&s, "%u", RO(Shm)->Uncore.MC[i].Channel[i2].Timing.B2B); + json_key(&s, "tCWL"); + json_literal(&s, "%u", RO(Shm)->Uncore.MC[i].Channel[i2].Timing.tCWL); + json_key(&s, "CMD_Rate"); + json_literal(&s, "%u", RO(Shm)->Uncore.MC[i].Channel[i2].Timing.CMD_Rate); + json_key(&s, "tsrRdTRd"); + json_literal(&s, "%u", RO(Shm)->Uncore.MC[i].Channel[i2].Timing.tsrRdTRd); + json_key(&s, "tdrRdTRd"); + json_literal(&s, "%u", RO(Shm)->Uncore.MC[i].Channel[i2].Timing.tdrRdTRd); + json_key(&s, "tddRdTRd"); + json_literal(&s, "%u", RO(Shm)->Uncore.MC[i].Channel[i2].Timing.tddRdTRd); + json_key(&s, "tsrRdTWr"); + json_literal(&s, "%u", RO(Shm)->Uncore.MC[i].Channel[i2].Timing.tsrRdTWr); + json_key(&s, "tdrRdTWr"); + json_literal(&s, "%u", RO(Shm)->Uncore.MC[i].Channel[i2].Timing.tdrRdTWr); + json_key(&s, "tddRdTWr"); + json_literal(&s, "%u", RO(Shm)->Uncore.MC[i].Channel[i2].Timing.tddRdTWr); + json_key(&s, "tsrWrTRd"); + json_literal(&s, "%u", RO(Shm)->Uncore.MC[i].Channel[i2].Timing.tsrWrTRd); + json_key(&s, "tdrWrTRd"); + json_literal(&s, "%u", RO(Shm)->Uncore.MC[i].Channel[i2].Timing.tdrWrTRd); + json_key(&s, "tddWrTRd"); + json_literal(&s, "%u", RO(Shm)->Uncore.MC[i].Channel[i2].Timing.tddWrTRd); + json_key(&s, "tsrWrTWr"); + json_literal(&s, "%u", RO(Shm)->Uncore.MC[i].Channel[i2].Timing.tsrWrTWr); + json_key(&s, "tdrWrTWr"); + json_literal(&s, "%u", RO(Shm)->Uncore.MC[i].Channel[i2].Timing.tdrWrTWr); + json_key(&s, "tddWrTWr"); + json_literal(&s, "%u", RO(Shm)->Uncore.MC[i].Channel[i2].Timing.tddWrTWr); + json_key(&s, "ECC"); + json_literal(&s, "%u", RO(Shm)->Uncore.MC[i].Channel[i2].Timing.ECC); + + json_end_object(&s); + } + json_key(&s, "DIMM"); + json_start_arr(&s); + for (i3 = 0; i3 < MC_MAX_DIMM; i3++) { + json_start_object(&s); + json_key(&s, "Size"); + json_literal(&s, "%u", RO(Shm)->Uncore.MC[i].Channel[i2].DIMM[i3].Size); + json_key(&s, "Rows"); + json_literal(&s, "%u", RO(Shm)->Uncore.MC[i].Channel[i2].DIMM[i3].Rows); + json_key(&s, "Cols"); + json_literal(&s, "%u", RO(Shm)->Uncore.MC[i].Channel[i2].DIMM[i3].Cols); + json_key(&s, "Banks"); + json_literal(&s, "%hu", RO(Shm)->Uncore.MC[i].Channel[i2].DIMM[i3].Banks); + json_key(&s, "Ranks"); + json_literal(&s, "%hu", RO(Shm)->Uncore.MC[i].Channel[i2].DIMM[i3].Ranks); + json_end_object(&s); + } + json_end_arr(&s); + json_end_object(&s); + } + } + json_end_arr(&s); + json_key(&s, "SlotCount"); + json_literal(&s, "%hu", RO(Shm)->Uncore.MC[i].SlotCount); + json_key(&s, "ChannelCount"); + json_literal(&s, "%hu", RO(Shm)->Uncore.MC[i].ChannelCount); + json_end_object(&s); + } + } + json_end_arr(&s); + + json_key(&s, "CtrlSpeed"); + json_literal(&s, "%llu", RO(Shm)->Uncore.CtrlSpeed); + json_key(&s, "CtrlCount"); + json_literal(&s, "%llu", RO(Shm)->Uncore.CtrlCount); + json_key(&s, "Unit"); + { + json_start_object(&s); + json_key(&s, "Bus_Rate"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Uncore.Unit.Bus_Rate); + json_key(&s, "BusSpeed"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Uncore.Unit.BusSpeed); + json_key(&s, "DDR_Rate"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Uncore.Unit.DDR_Rate); + json_key(&s, "DDRSpeed"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Uncore.Unit.DDRSpeed); + json_key(&s, "DDR_Ver"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Uncore.Unit.DDR_Ver); + json_key(&s, "DDR_Std"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Uncore.Unit.DDR_Std); + json_end_object(&s); + } + json_end_object(&s); + } + json_key(&s, "Proc"); + { + json_start_object(&s); + + json_key(&s, "Features"); + { + json_start_object(&s); + json_key(&s, "Info"); + { + json_start_object(&s); + json_key(&s, "Vendor"); + { + json_start_object(&s); + json_key(&s, "CRC"); + json_literal(&s, "%u", RO(Shm)->Proc.Features.Info.Vendor.CRC); + json_key(&s, "ID"); + json_string(&s, RO(Shm)->Proc.Features.Info.Vendor.ID); + json_end_object(&s); + } + json_key(&s, "Hypervisor"); + { + json_start_object(&s); + json_key(&s, "CRC"); + json_literal(&s, "%u", RO(Shm)->Proc.Features.Info.Hypervisor.CRC); + json_key(&s, "ID"); + json_string(&s, RO(Shm)->Proc.Features.Info.Hypervisor.ID); + json_end_object(&s); + } + + json_end_object(&s); + } + json_key(&s, "Std"); + { + json_start_object(&s); + json_key(&s, "MIDR"); + { + json_start_object(&s); + json_key(&s, "Stepping"); + { + json_start_object(&s); + snprintf(hexStr, 32, "0x%x", RO(Shm)->Proc.Features.Info.Signature.Stepping); + json_key(&s, "Revision"); + json_string(&s, hexStr); + json_end_object(&s); + } + json_key(&s, "Model"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Info.Signature.Model); + json_key(&s, "Family"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Info.Signature.Family); + json_key(&s, "ExtModel"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Info.Signature.ExtModel); + json_key(&s, "ExtFamily"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Info.Signature.ExtFamily); + json_end_object(&s); + } + json_key(&s, "DFR1"); + { + json_start_object(&s); + json_key(&s, "EBEP"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.EBEP); + json_end_object(&s); + } + json_key(&s, "ISAR0"); + { + json_start_object(&s); + json_key(&s, "AES"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AES); + json_key(&s, "PMULL"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.PMULL); + json_key(&s, "SHA1"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SHA1); + json_key(&s, "SHA256"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SHA256); + json_key(&s, "SHA512"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SHA512); + json_key(&s, "SHA3"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SHA3); + json_key(&s, "CRC32"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.CRC32); + json_key(&s, "LSE"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.LSE); + json_key(&s, "LSE128"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.LSE128); + json_key(&s, "DP"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.DP); + json_key(&s, "SM3"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SM3); + json_key(&s, "SM4"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SM4); + json_key(&s, "RAND"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.RAND); + json_key(&s, "TME"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.TME); + json_key(&s, "FHM"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FHM); + json_key(&s, "FlagM"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FlagM); + json_key(&s, "FlagM2"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FlagM2); + json_key(&s, "TLBIOS"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.TLBIOS); + json_key(&s, "TLBIRANGE"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.TLBIRANGE); + json_key(&s, "RDMA"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.RDMA); + json_end_object(&s); + } + json_key(&s, "ISAR1"); + { + json_start_object(&s); + json_key(&s, "FCMA"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FCMA); + json_key(&s, "PACIMP"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.PACIMP); + json_key(&s, "PACQARMA5"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.PACQARMA5); + json_key(&s, "LRCPC"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.LRCPC); + json_key(&s, "LRCPC2"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.LRCPC2); + json_key(&s, "LRCPC3"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.LRCPC3); + json_key(&s, "JSCVT"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.JSCVT); + json_key(&s, "FRINTTS"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FRINTTS); + json_key(&s, "SPECRES"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SPECRES); + json_key(&s, "SPECRES2"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SPECRES2); + json_key(&s, "BF16"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.BF16); + json_key(&s, "EBF16"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.EBF16); + json_key(&s, "I8MM"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.I8MM); + json_key(&s, "SB"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SB); + json_key(&s, "XS"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.XS); + json_key(&s, "LS64"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.LS64); + json_key(&s, "LS64_V"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.LS64_V); + json_key(&s, "LS64_ACCDATA"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.LS64_ACCDATA); + json_key(&s, "DGH"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.DGH); + json_key(&s, "DPB"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.DPB); + json_key(&s, "DPB2"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.DPB2); + json_end_object(&s); + } + json_key(&s, "ISAR2"); + { + json_start_object(&s); + json_key(&s, "PACQARMA3"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.PACQARMA3); + json_key(&s, "PAuth"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.PAuth); + json_key(&s, "EPAC"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.EPAC); + json_key(&s, "PAuth2"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.PAuth2); + json_key(&s, "FPAC"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FPAC); + json_key(&s, "FPACCOMBINE"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FPACCOMBINE); + json_key(&s, "PAuth_LR"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.PAuth_LR); + json_key(&s, "WFxT"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.WFxT); + json_key(&s, "RPRES"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.RPRES); + json_key(&s, "MOPS"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.MOPS); + json_key(&s, "HBC"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.HBC); + json_key(&s, "SYSREG128"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SYSREG128); + json_key(&s, "SYSINSTR128"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SYSINSTR128); + json_key(&s, "PRFMSLC"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.PRFMSLC); + json_key(&s, "RPRFM"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.RPRFM); + json_key(&s, "CSSC"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.CSSC); + json_key(&s, "LUT"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.LUT); + json_key(&s, "ATS1A"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ATS1A); + json_key(&s, "CONSTPACFIELD"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.CONSTPACFIELD); + json_end_object(&s); + } + json_key(&s, "MMFR0"); + { + json_start_object(&s); + json_key(&s, "ECV"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ECV); + json_key(&s, "FGT"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FGT); + json_key(&s, "FGT2"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FGT2); + json_key(&s, "ExS"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExS); + json_key(&s, "BigEnd_EL0"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.BigEnd_EL0); + json_key(&s, "PARange"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.PARange); + json_end_object(&s); + } + json_key(&s, "MMFR1"); + { + json_start_object(&s); + json_key(&s, "ECBHB"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ECBHB); + json_key(&s, "PAN"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.PAN); + json_key(&s, "VHE"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.VHE); + json_end_object(&s); + } + json_key(&s, "MMFR2"); + { + json_start_object(&s); + json_key(&s, "VARange"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.VARange); + json_key(&s, "UAO"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.UAO); + json_end_object(&s); + } + json_key(&s, "PFR0"); + { + json_start_object(&s); + json_key(&s, "FP"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FP); + json_key(&s, "SIMD"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SIMD); + json_key(&s, "GIC_vers"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.GIC_vers); + json_key(&s, "GIC_frac"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.GIC_frac); + json_key(&s, "SVE"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE); + json_key(&s, "DIT"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.DIT); + json_key(&s, "RAS"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.RAS); + json_key(&s, "MPAM_vers"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.MPAM_vers); + json_key(&s, "AMU_vers"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AMU_vers); + json_key(&s, "AMU_frac"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AMU_frac); + json_key(&s, "RME"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.RME); + json_key(&s, "SEL2"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SEL2); + json_end_object(&s); + } + json_key(&s, "PFR1"); + { + json_start_object(&s); + json_key(&s, "BTI"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.BTI); + json_key(&s, "GCS"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.GCS); + json_key(&s, "MTE"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.MTE); + json_key(&s, "NMI"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.NMI); + json_key(&s, "SME"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME); + json_key(&s, "RNG_TRAP"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.RNG_TRAP); + json_key(&s, "RAS_frac"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.RAS_frac); + json_key(&s, "MPAM_frac"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.MPAM_frac); + json_key(&s, "THE"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.THE); + json_key(&s, "DF2"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.DF2); + json_key(&s, "PFAR"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.PFAR); + json_end_object(&s); + } + json_key(&s, "ZFR0"); + { + json_start_object(&s); + json_key(&s, "SVE_F64MM"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE_F64MM); + json_key(&s, "SVE_F32MM"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE_F32MM); + json_key(&s, "SVE_I8MM"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE_I8MM); + json_key(&s, "SVE_SM4"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE_SM4); + json_key(&s, "SVE_SHA3"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE_SHA3); + json_key(&s, "SVE_BF16"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE_BF16); + json_key(&s, "SVE_EBF16"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE_EBF16); + json_key(&s, "SVE_BitPerm"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE_BitPerm); + json_key(&s, "SVE_AES"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE_AES); + json_key(&s, "SVE_PMULL128"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE_PMULL128); + json_key(&s, "SVE2"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SVE2); + json_end_object(&s); + } + json_key(&s, "SMFR0"); + { + json_start_object(&s); + json_key(&s, "SME_FA64"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_FA64); + json_key(&s, "SME_LUTv2"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_LUTv2); + json_key(&s, "SME2"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME2); + json_key(&s, "SME2p1"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME2p1); + json_key(&s, "SME_I16I64"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_I16I64); + json_key(&s, "SME_F64F64"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_F64F64); + json_key(&s, "SME_I16I32"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_I16I32); + json_key(&s, "SME_B16B16"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_B16B16); + json_key(&s, "SME_F16F16"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_F16F16); + json_key(&s, "SME_F8F16"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_F8F16); + json_key(&s, "SME_F8F32"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_F8F32); + json_key(&s, "SME_I8I32"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_I8I32); + json_key(&s, "SME_F16F32"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_F16F32); + json_key(&s, "SME_B16F32"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_B16F32); + json_key(&s, "SME_BI32I32"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_BI32I32); + json_key(&s, "SME_F32F32"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_F32F32); + json_key(&s, "SME_SF8FMA"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_SF8FMA); + json_key(&s, "SME_SF8DP4"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_SF8DP4); + json_key(&s, "SME_SF8DP2"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_SF8DP2); + json_end_object(&s); + } + json_key(&s, "MISC"); + { + json_start_object(&s); + json_key(&s, "HTT"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.HTT); + json_key(&s, "TSC"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.TSC); + json_key(&s, "MONITOR"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.MONITOR); + json_key(&s, "Hybrid"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Hybrid); + json_key(&s, "ACPI"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ACPI); + json_key(&s, "Hyperv"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Hyperv); + json_end_object(&s); + } + json_end_object(&s); + } + json_key(&s, "MWait"); + { + json_start_object(&s); + + json_key(&s, "SubCstate_C0_MWAIT"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.MWait.SubCstate_MWAIT0); + json_key(&s, "SubCstate_C1_MWAIT"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.MWait.SubCstate_MWAIT1); + json_key(&s, "SubCstate_C2_MWAIT"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.MWait.SubCstate_MWAIT2); + json_key(&s, "SubCstate_C3_MWAIT"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.MWait.SubCstate_MWAIT3); + json_key(&s, "SubCstate_C4_MWAIT"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.MWait.SubCstate_MWAIT4); + json_key(&s, "SubCstate_C5_MWAIT"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.MWait.SubCstate_MWAIT5); + json_key(&s, "SubCstate_C6_MWAIT"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.MWait.SubCstate_MWAIT6); + json_key(&s, "SubCstate_C7_MWAIT"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.MWait.SubCstate_MWAIT7); + + json_end_object(&s); + } + json_key(&s, "Power"); + { + json_start_object(&s); + + json_key(&s, "DTS"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.DTS); + json_key(&s, "PLN"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.PLN); + json_key(&s, "PTM"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.PTM); + json_key(&s, "HWP_Registers"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.HWP_Reg); + + json_end_object(&s); + } + json_key(&s, "PerfMon"); + { + json_start_object(&s); + + json_key(&s, "Version"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.PerfMon.Version); + json_key(&s, "MonCtrs"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.PerfMon.MonCtrs); + json_key(&s, "MonWidth"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.PerfMon.MonWidth); + json_key(&s, "FixCtrs"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.PerfMon.FixCtrs); + json_key(&s, "FixWidth"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.PerfMon.FixWidth); + json_key(&s, "CoreCycles"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.PerfMon.CoreCycles); + json_key(&s, "InstrRetired"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.PerfMon.InstrRetired); + json_key(&s, "AMU_CG0NC"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AMU.CG0NC); + json_key(&s, "AMU_CG1NC"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AMU.CG1NC); + + json_end_object(&s); + } + json_key(&s, "FactoryFreq"); + json_literal(&s, "%u", RO(Shm)->Proc.Features.Factory.Freq); + + json_key(&s, "InvariantTSC"); + json_literal(&s, "%u", RO(Shm)->Proc.Features.InvariantTSC); + json_key(&s, "HyperThreading"); + json_literal(&s, "%u", RO(Shm)->Proc.Features.HyperThreading); + json_key(&s, "HTT_Enable"); + json_literal(&s, "%u", RO(Shm)->Proc.Features.HTT_Enable); + json_key(&s, "Turbo_Unlock"); + json_literal(&s, "%u", RO(Shm)->Proc.Features.Turbo_Unlock); + json_key(&s, "TDP_Unlock"); + json_literal(&s, "%u", RO(Shm)->Proc.Features.TDP_Unlock); + json_key(&s, "TDP_Levels"); + json_literal(&s, "%u", RO(Shm)->Proc.Features.TDP_Levels); + json_key(&s, "TDP_Cfg_Lock"); + json_literal(&s, "%u", RO(Shm)->Proc.Features.TDP_Cfg_Lock); + json_key(&s, "TDP_Cfg_Level"); + json_literal(&s, "%u", RO(Shm)->Proc.Features.TDP_Cfg_Level); + json_key(&s, "Turbo_OPP"); + json_literal(&s, "%u", RO(Shm)->Proc.Features.Turbo_OPP); + json_key(&s, "TargetRatio_Unlock"); + json_literal(&s, "%u", RO(Shm)->Proc.Features.TgtRatio_Unlock); + json_key(&s, "ClockRatio_Unlock"); + json_literal(&s, "%u", RO(Shm)->Proc.Features.ClkRatio_Unlock); + json_key(&s, "Uncore_Unlock"); + json_literal(&s, "%u", RO(Shm)->Proc.Features.Uncore_Unlock); + json_key(&s, "ACPI_CPPC"); + json_literal(&s, "%u", RO(Shm)->Proc.Features.ACPI_CPPC); + json_key(&s, "HWP_Enable"); + json_literal(&s, "%u", RO(Shm)->Proc.Features.HWP_Enable); + json_key(&s, "Other_Capable"); + json_literal(&s, "%u", RO(Shm)->Proc.Features.Other_Capable); + json_key(&s, "SpecTurboRatio"); + json_literal(&s, "%u", RO(Shm)->Proc.Features.SpecTurboRatio); + json_key(&s, "SSBS"); + json_literal(&s, "%u", RO(Shm)->Proc.Features.SSBS); + + json_end_object(&s); + } + json_key(&s, "HypervisorID"); + json_literal(&s, "%llu", RO(Shm)->Proc.HypervisorID); + json_key(&s, "Technology"); + { + json_start_object(&s); + json_key(&s, "Hybrid"); + json_literal(&s, "%llu", RO(Shm)->Proc.Features.Hybrid); + json_key(&s, "VM"); + json_literal(&s, "%llu", RO(Shm)->Proc.Technology.VM); + json_key(&s, "IOMMU"); + json_literal(&s, "%llu", RO(Shm)->Proc.Technology.IOMMU); + json_key(&s, "IOMMU_Ver_Major"); + json_literal(&s, "%llu", RO(Shm)->Proc.Technology.IOMMU_Ver_Major); + json_key(&s, "IOMMU_Ver_Minor"); + json_literal(&s, "%llu", RO(Shm)->Proc.Technology.IOMMU_Ver_Minor); + + json_end_object(&s); + } + json_key(&s, "CPU"); + { + json_start_object(&s); + json_key(&s, "Count"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.CPU.Count); + json_key(&s, "Online"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.CPU.OnLine); + json_end_object(&s); + } + json_key(&s, "Service"); + { + json_start_object(&s); + json_key(&s, "Proc"); + json_literal(&s, "%llu", RO(Shm)->Proc.Service.Proc); + json_key(&s, "Service"); + { + json_start_object(&s); + json_key(&s, "Core"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Service.Core); + json_key(&s, "Thread"); + json_literal(&s, "%d", RO(Shm)->Proc.Service.Thread); + json_key(&s, "Hybrid"); + json_literal(&s, "%d", RO(Shm)->Proc.Service.Hybrid); + json_end_object(&s); + } + json_end_object(&s); + } + json_key(&s, "Boost"); + { + json_start_arr(&s); + for (i = 0; i < RATIO_SIZE; i++) + { + json_literal(&s, "%u", RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Boost[i]); + } + json_end_arr(&s); + } + + json_key(&s, "PM_version"); + json_literal(&s, "%u", RO(Shm)->Proc.PM_version); + + json_key(&s, "Top"); + { + json_start_object(&s); + json_key(&s, "Relative"); + json_literal(&s, "%u", RO(Shm)->Proc.Top.Rel); + json_key(&s, "Absolute"); + json_literal(&s, "%u", RO(Shm)->Proc.Top.Abs); + json_end_object(&s); + } + + json_key(&s, "Toggle"); + json_literal(&s, "%u", RO(Shm)->Proc.Toggle); + + json_key(&s, "FlipFlop"); + json_start_arr(&s); + for (i = 0; i < 2; i++) { + json_start_object(&s); + json_key(&s, "Delta"); + { + json_start_object(&s); + + json_key(&s, "PTSC"); + json_literal(&s, "%llu", RO(Shm)->Proc.FlipFlop[i].Delta.PCLK); + json_key(&s, "PC02"); + json_literal(&s, "%llu", RO(Shm)->Proc.FlipFlop[i].Delta.PC02); + json_key(&s, "PC03"); + json_literal(&s, "%llu", RO(Shm)->Proc.FlipFlop[i].Delta.PC03); + json_key(&s, "PC04"); + json_literal(&s, "%llu", RO(Shm)->Proc.FlipFlop[i].Delta.PC04); + json_key(&s, "PC06"); + json_literal(&s, "%llu", RO(Shm)->Proc.FlipFlop[i].Delta.PC06); + json_key(&s, "PC07"); + json_literal(&s, "%llu", RO(Shm)->Proc.FlipFlop[i].Delta.PC07); + json_key(&s, "PC08"); + json_literal(&s, "%llu", RO(Shm)->Proc.FlipFlop[i].Delta.PC08); + json_key(&s, "PC09"); + json_literal(&s, "%llu", RO(Shm)->Proc.FlipFlop[i].Delta.PC09); + json_key(&s, "PC10"); + json_literal(&s, "%llu", RO(Shm)->Proc.FlipFlop[i].Delta.PC10); + json_key(&s, "MC6"); + json_literal(&s, "%llu", RO(Shm)->Proc.FlipFlop[i].Delta.MC6); + json_key(&s, "ACCU"); + json_start_arr(&s); + for (i2 = 0; i2 < DOMAIN_SIZE; i2++) { + json_literal(&s, "%llu", RO(Shm)->Proc.FlipFlop[i].Delta.ACCU[i2]); + } + json_end_arr(&s); + + json_end_object(&s); + } + + json_key(&s, "Uncore"); + { + json_start_object(&s); + json_key(&s, "FC0"); + json_literal(&s, "%llu", RO(Shm)->Proc.FlipFlop[i].Uncore.FC0); + json_end_object(&s); + } + + json_end_object(&s); + } + json_end_arr(&s); + + json_key(&s, "State"); + { + json_start_object(&s); + json_key(&s, "PC02"); + json_literal(&s, "%f", RO(Shm)->Proc.State.PC02); + json_key(&s, "PC03"); + json_literal(&s, "%f", RO(Shm)->Proc.State.PC03); + json_key(&s, "PC04"); + json_literal(&s, "%f", RO(Shm)->Proc.State.PC04); + json_key(&s, "PC06"); + json_literal(&s, "%f", RO(Shm)->Proc.State.PC06); + json_key(&s, "PC07"); + json_literal(&s, "%f", RO(Shm)->Proc.State.PC07); + json_key(&s, "PC08"); + json_literal(&s, "%f", RO(Shm)->Proc.State.PC08); + json_key(&s, "PC09"); + json_literal(&s, "%f", RO(Shm)->Proc.State.PC09); + json_key(&s, "PC10"); + json_literal(&s, "%f", RO(Shm)->Proc.State.PC10); + json_key(&s, "MC6"); + json_literal(&s, "%f", RO(Shm)->Proc.State.MC6); + json_key(&s, "Energy"); + json_start_arr(&s); + for (i = 0; i < DOMAIN_SIZE; i++) { + json_literal(&s, "%f", RO(Shm)->Proc.State.Energy[i].Current); + } + json_end_arr(&s); + json_key(&s, "Power"); + json_start_arr(&s); + for (i = 0; i < DOMAIN_SIZE; i++) { + json_literal(&s, "%f", RO(Shm)->Proc.State.Power[i].Current); + } + json_end_arr(&s); + json_end_object(&s); + } + json_key(&s, "Avg"); + { + json_start_object(&s); + json_key(&s, "Turbo"); + json_literal(&s, "%f", RO(Shm)->Proc.Avg.Turbo); + json_key(&s, "C0"); + json_literal(&s, "%f", RO(Shm)->Proc.Avg.C0); + json_key(&s, "C3"); + json_literal(&s, "%f", RO(Shm)->Proc.Avg.C3); + json_key(&s, "C6"); + json_literal(&s, "%f", RO(Shm)->Proc.Avg.C6); + json_key(&s, "C7"); + json_literal(&s, "%f", RO(Shm)->Proc.Avg.C7); + json_key(&s, "C1"); + json_literal(&s, "%f", RO(Shm)->Proc.Avg.C1); + + json_end_object(&s); + } + json_key(&s, "Power"); + { + json_start_object(&s); + json_key(&s, "TDP"); + json_literal(&s, "%u", RO(Shm)->Proc.Power.TDP); + json_key(&s, "Min"); + json_literal(&s, "%u", RO(Shm)->Proc.Power.Min); + json_key(&s, "Max"); + json_literal(&s, "%u", RO(Shm)->Proc.Power.Max); + { + enum PWR_DOMAIN pw; + json_key(&s, "PL1"); + { + json_start_arr(&s); + for (pw = PWR_DOMAIN(PKG); pw < PWR_DOMAIN(SIZE); pw++) + { + json_literal(&s, "%u", RO(Shm)->Proc.Power.Domain[pw].PWL[PL1]); + } + json_end_arr(&s); + } + json_key(&s, "PL2"); + { + json_start_arr(&s); + for (pw = PWR_DOMAIN(PKG); pw < PWR_DOMAIN(SIZE); pw++) + { + json_literal(&s, "%u", RO(Shm)->Proc.Power.Domain[pw].PWL[PL2]); + } + json_end_arr(&s); + } + } + json_key(&s, "EDC"); + json_literal(&s, "%u", RO(Shm)->Proc.Power.EDC); + json_key(&s, "TDC"); + json_literal(&s, "%u", RO(Shm)->Proc.Power.TDC); + json_key(&s, "Unit"); + { + json_start_object(&s); + json_key(&s, "Watts"); + json_literal(&s, "%f", RO(Shm)->Proc.Power.Unit.Watts); + json_key(&s, "Joules"); + json_literal(&s, "%f", RO(Shm)->Proc.Power.Unit.Joules); + json_key(&s, "Times"); + json_literal(&s, "%f", RO(Shm)->Proc.Power.Unit.Times); + json_end_object(&s); + } + + json_end_object(&s); + } + json_key(&s, "Current"); + { + json_start_object(&s); + json_key(&s, "EDC"); + json_literal(&s, "%u", RO(Shm)->Proc.Power.EDC); + json_key(&s, "TDC"); + json_literal(&s, "%u", RO(Shm)->Proc.Power.TDC); + json_end_object(&s); + } + json_key(&s, "Brand"); + json_string(&s, RO(Shm)->Proc.Brand); + + json_key(&s, "Architecture"); + json_string(&s, RO(Shm)->Proc.Architecture); + + json_key(&s, "Mechanisms"); + { + json_start_object(&s); + json_key(&s, "CLRBHB"); + json_literal(&s, "%llu", RO(Shm)->Proc.Mechanisms.CLRBHB); + json_key(&s, "CSV2"); + json_literal(&s, "%llu", RO(Shm)->Proc.Mechanisms.CSV2); + json_key(&s, "CSV3"); + json_literal(&s, "%llu", RO(Shm)->Proc.Mechanisms.CSV3); + json_key(&s, "SSBS"); + json_literal(&s, "%llu", RO(Shm)->Proc.Mechanisms.SSBS); + json_end_object(&s); + } + json_end_object(&s); + } + + json_key(&s, "Cpu"); + json_start_arr(&s); + for (cpu = 0; (cpu < RO(Shm)->Proc.CPU.Count); cpu++) + { + struct FLIP_FLOP *CFlop = &RO(Shm)->Cpu[cpu].FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + + json_start_object(&s); + json_key(&s, "OffLine"); + json_literal(&s, "%llu", RO(Shm)->Cpu[cpu].OffLine); + json_key(&s, "Clock"); + { + json_start_object(&s); + json_key(&s, "Q"); + json_literal(&s, "%llu", CFlop->Clock.Q); + json_key(&s, "R"); + json_literal(&s, "%llu", CFlop->Clock.R); + json_key(&s, "Hz"); + json_literal(&s, "%llu", CFlop->Clock.Hz); + json_end_object(&s); + } + json_key(&s, "Toggle"); + json_literal(&s, "%u", RO(Shm)->Cpu[cpu].Toggle); + + json_key(&s, "Boost"); + { + json_start_arr(&s); + for (i = 0; i < RATIO_SIZE; i++) + { + json_literal(&s, "%u", RO(Shm)->Cpu[cpu].Boost[i]); + } + json_end_arr(&s); + } + json_key(&s, "Topology"); + { + json_start_object(&s); + json_key(&s, "PN"); + json_literal(&s, "%d", RO(Shm)->Cpu[cpu].Topology.PN); + json_key(&s, "BSP"); + json_literal(&s, "%d", RO(Shm)->Cpu[cpu].Topology.BSP); + json_key(&s, "MPID"); + json_literal(&s, "%d", RO(Shm)->Cpu[cpu].Topology.MPID); + json_key(&s, "PackageID"); + json_literal(&s, "%d", RO(Shm)->Cpu[cpu].Topology.PackageID); + json_key(&s, "Hybrid_ID"); + json_literal(&s, "%d", RO(Shm)->Cpu[cpu].Topology.Cluster.Hybrid_ID); + json_key(&s, "CoreID"); + json_literal(&s, "%d", RO(Shm)->Cpu[cpu].Topology.CoreID); + json_key(&s, "ThreadID"); + json_literal(&s, "%d", RO(Shm)->Cpu[cpu].Topology.ThreadID); + json_key(&s, "Cache"); + json_start_arr(&s); + for (i2 = 0; i2 < CACHE_MAX_LEVEL; i2++) { + json_start_object(&s); + json_key(&s, "Set"); + json_literal(&s, "%u", RO(Shm)->Cpu[cpu].Topology.Cache[i2].Set); + json_key(&s, "Size"); + json_literal(&s, "%u", RO(Shm)->Cpu[cpu].Topology.Cache[i2].Size); + json_key(&s, "LineSz"); + json_literal(&s, "%hu", RO(Shm)->Cpu[cpu].Topology.Cache[i2].LineSz); + json_key(&s, "Way"); + json_literal(&s, "%hu", RO(Shm)->Cpu[cpu].Topology.Cache[i2].Way); + json_key(&s, "Feature"); + { + json_start_object(&s); + json_key(&s, "WriteBack"); + json_literal(&s, "%hu", RO(Shm)->Cpu[cpu].Topology.Cache[i2].Feature.WriteBack); + json_key(&s, "Inclusive"); + json_literal(&s, "%hu", RO(Shm)->Cpu[cpu].Topology.Cache[i2].Feature.Inclusive); + json_end_object(&s); + } + json_end_object(&s); + } + + json_end_arr(&s); + json_end_object(&s); + } + json_key(&s, "PowerThermal"); + { + json_start_object(&s); + json_key(&s, "Limit"); + json_start_arr(&s); + { + json_literal(&s, "%u", RO(Shm)->Cpu[cpu].PowerThermal.Limit[SENSOR_LOWEST]); + json_literal(&s, "%u", RO(Shm)->Cpu[cpu].PowerThermal.Limit[SENSOR_HIGHEST]); + } + json_end_arr(&s); + json_key(&s, "DutyCycle"); + { + json_start_object(&s); + json_key(&s, "ClockMod"); + json_literal(&s, "%u", RO(Shm)->Cpu[cpu].PowerThermal.DutyCycle.ClockMod); + json_key(&s, "Extended"); + json_literal(&s, "%u", RO(Shm)->Cpu[cpu].PowerThermal.DutyCycle.Extended); + json_end_object(&s); + } + json_key(&s, "PowerPolicy"); + json_literal(&s, "%u", RO(Shm)->Cpu[cpu].PowerThermal.PowerPolicy); + json_key(&s, "HWP"); + { + json_start_object(&s); + json_key(&s, "Capabilities"); + { + json_start_object(&s); + json_key(&s, "Lowest"); + json_literal(&s, "%u", RO(Shm)->Cpu[cpu].PowerThermal.HWP.Capabilities.Lowest); + json_key(&s, "Efficient"); + json_literal(&s, "%u", RO(Shm)->Cpu[cpu].PowerThermal.HWP.Capabilities.Most_Efficient); + json_key(&s, "Guaranteed"); + json_literal(&s, "%u", RO(Shm)->Cpu[cpu].PowerThermal.HWP.Capabilities.Guaranteed); + json_key(&s, "Highest"); + json_literal(&s, "%u", RO(Shm)->Cpu[cpu].PowerThermal.HWP.Capabilities.Highest); + json_end_object(&s); + } + json_key(&s, "Request"); + { + json_start_object(&s); + json_key(&s, "Minimum_Perf"); + json_literal(&s, "%u", RO(Shm)->Cpu[cpu].PowerThermal.HWP.Request.Minimum_Perf); + json_key(&s, "Maximum_Perf"); + json_literal(&s, "%u", RO(Shm)->Cpu[cpu].PowerThermal.HWP.Request.Maximum_Perf); + json_key(&s, "Desired_Perf"); + json_literal(&s, "%u", RO(Shm)->Cpu[cpu].PowerThermal.HWP.Request.Desired_Perf); + json_key(&s, "Energy_Pref"); + json_literal(&s, "%u", RO(Shm)->Cpu[cpu].PowerThermal.HWP.Request.Energy_Pref); + json_end_object(&s); + } + json_end_object(&s); + } + + json_end_object(&s); + } + json_key(&s, "FlipFlop"); + json_start_arr(&s); + for (i2 = 0; i2 < 2; i2++) { + json_start_object(&s); + json_key(&s, "Delta"); + { + json_start_object(&s); + json_key(&s, "INST"); + json_literal(&s, "%llu", RO(Shm)->Cpu[cpu].FlipFlop[i2].Delta.INST); + json_key(&s, "C0"); + { + json_start_object(&s); + json_key(&s, "UCC"); + json_literal(&s, "%llu", RO(Shm)->Cpu[cpu].FlipFlop[i2].Delta.C0.UCC); + json_key(&s, "URC"); + json_literal(&s, "%llu", RO(Shm)->Cpu[cpu].FlipFlop[i2].Delta.C0.URC); + json_end_object(&s); + } + json_key(&s, "C3"); + json_literal(&s, "%llu", RO(Shm)->Cpu[cpu].FlipFlop[i2].Delta.C3); + json_key(&s, "C6"); + json_literal(&s, "%llu", RO(Shm)->Cpu[cpu].FlipFlop[i2].Delta.C6); + json_key(&s, "C7"); + json_literal(&s, "%llu", RO(Shm)->Cpu[cpu].FlipFlop[i2].Delta.C7); + json_key(&s, "TSC"); + json_literal(&s, "%llu", RO(Shm)->Cpu[cpu].FlipFlop[i2].Delta.TSC); + json_key(&s, "C1"); + json_literal(&s, "%llu", RO(Shm)->Cpu[cpu].FlipFlop[i2].Delta.C1); + + json_end_object(&s); + } + json_key(&s, "State"); + { + json_start_object(&s); + json_key(&s, "IPS"); + json_literal(&s, "%f", RO(Shm)->Cpu[cpu].FlipFlop[i2].State.IPS); + json_key(&s, "IPC"); + json_literal(&s, "%f", RO(Shm)->Cpu[cpu].FlipFlop[i2].State.IPC); + json_key(&s, "CPI"); + json_literal(&s, "%f", RO(Shm)->Cpu[cpu].FlipFlop[i2].State.CPI); + json_key(&s, "Turbo"); + json_literal(&s, "%f", RO(Shm)->Cpu[cpu].FlipFlop[i2].State.Turbo); + json_key(&s, "C0"); + json_literal(&s, "%f", RO(Shm)->Cpu[cpu].FlipFlop[i2].State.C0); + json_key(&s, "C3"); + json_literal(&s, "%f", RO(Shm)->Cpu[cpu].FlipFlop[i2].State.C3); + json_key(&s, "C6"); + json_literal(&s, "%f", RO(Shm)->Cpu[cpu].FlipFlop[i2].State.C6); + json_key(&s, "C7"); + json_literal(&s, "%f", RO(Shm)->Cpu[cpu].FlipFlop[i2].State.C7); + json_key(&s, "C1"); + json_literal(&s, "%f", RO(Shm)->Cpu[cpu].FlipFlop[i2].State.C1); + + json_end_object(&s); + } + json_key(&s, "Relative"); + { + json_start_object(&s); + json_key(&s, "Ratio"); + json_literal(&s, "%f", RO(Shm)->Cpu[cpu].FlipFlop[i2].Relative.Ratio); + json_key(&s, "Freq"); + json_literal(&s, "%f", RO(Shm)->Cpu[cpu].FlipFlop[i2].Relative.Freq); + json_end_object(&s); + } + json_key(&s, "Absolute"); + { + json_start_object(&s); + json_key(&s, "Ratio"); + json_literal(&s, "%f", RO(Shm)->Cpu[cpu].FlipFlop[i2].Absolute.Ratio.Perf); + json_key(&s, "Freq"); + json_literal(&s, "%f", RO(Shm)->Cpu[cpu].FlipFlop[i2].Absolute.Freq); + json_end_object(&s); + } + json_key(&s, "Thermal"); + { + json_start_object(&s); + json_key(&s, "Sensor"); + json_literal(&s, "%u", RO(Shm)->Cpu[cpu].FlipFlop[i2].Thermal.Sensor); + json_key(&s, "Temp"); + json_literal(&s, "%u", RO(Shm)->Cpu[cpu].FlipFlop[i2].Thermal.Temp); + json_key(&s, "Events"); + json_literal(&s, "%u", RO(Shm)->Cpu[cpu].FlipFlop[i2].Thermal.Events); + json_key(&s, "Target"); + json_start_arr(&s); + { + json_literal(&s, "%u", RO(Shm)->Cpu[cpu].FlipFlop[i2].Thermal.Param.Offset[THERMAL_TARGET]); + json_literal(&s, "%u", RO(Shm)->Cpu[cpu].FlipFlop[i2].Thermal.Param.Offset[THERMAL_OFFSET_P1]); + json_literal(&s, "%u", RO(Shm)->Cpu[cpu].FlipFlop[i2].Thermal.Param.Offset[THERMAL_OFFSET_P2]); + } + json_end_arr(&s); + json_end_object(&s); + } + json_key(&s, "Voltage"); + { + json_start_object(&s); + json_key(&s, "VID"); + json_literal(&s, "%u", RO(Shm)->Cpu[cpu].FlipFlop[i2].Voltage.VID); + json_key(&s, "Vcore"); + json_literal(&s, "%f", RO(Shm)->Cpu[cpu].FlipFlop[i2].Voltage.Vcore); + + json_end_object(&s); + } + json_key(&s, "Counter"); + { + json_start_object(&s); + json_key(&s, "SMI"); + json_literal(&s, "%u", RO(Shm)->Cpu[cpu].FlipFlop[i2].Counter.SMI); + json_key(&s, "NMI"); + { + json_start_object(&s); + json_key(&s, "LOCAL"); + json_literal(&s, "%u", RO(Shm)->Cpu[cpu].FlipFlop[i2].Counter.NMI.LOCAL); + json_key(&s, "UNKNOWN"); + json_literal(&s, "%u", RO(Shm)->Cpu[cpu].FlipFlop[i2].Counter.NMI.UNKNOWN); + json_key(&s, "PCISERR"); + json_literal(&s, "%u", RO(Shm)->Cpu[cpu].FlipFlop[i2].Counter.NMI.PCISERR); + json_key(&s, "IOCHECK"); + json_literal(&s, "%u", RO(Shm)->Cpu[cpu].FlipFlop[i2].Counter.NMI.IOCHECK); + json_end_object(&s); + } + json_end_object(&s); + } + json_end_object(&s); + } + json_end_arr(&s); + + json_key(&s, "Frequency"); + { + json_start_object(&s); + json_key(&s, "Relative"); + json_start_arr(&s); + { + json_literal(&s, "%f", RO(Shm)->Cpu[cpu].Relative.Freq[SENSOR_LOWEST]); + json_literal(&s, "%f", RO(Shm)->Cpu[cpu].Relative.Freq[SENSOR_HIGHEST]); + } + json_end_arr(&s); + json_key(&s, "Absolute"); + json_start_arr(&s); + { + json_literal(&s, "%f", RO(Shm)->Cpu[cpu].Absolute.Freq[SENSOR_LOWEST]); + json_literal(&s, "%f", RO(Shm)->Cpu[cpu].Absolute.Freq[SENSOR_HIGHEST]); + } + json_end_arr(&s); + json_end_object(&s); + } + + json_key(&s, "SystemRegister"); + { + json_start_object(&s); + snprintf(hexStr, 32, "0x%llx", RO(Shm)->Cpu[cpu].SystemRegister.FLAGS); + json_key(&s, "FLAGS"); + json_string(&s, hexStr); + + snprintf(hexStr, 32, "0x%llx", RO(Shm)->Cpu[cpu].SystemRegister.SCTLR); + json_key(&s, "SCTLR"); + json_string(&s, hexStr); + + snprintf(hexStr, 32, "0x%llx", RO(Shm)->Cpu[cpu].SystemRegister.SCTLR2); + json_key(&s, "SCTLR2"); + json_string(&s, hexStr); + + snprintf(hexStr, 32, "0x%llx", RO(Shm)->Cpu[cpu].SystemRegister.EL); + json_key(&s, "EL"); + json_string(&s, hexStr); + + snprintf(hexStr, 32, "0x%llx", RO(Shm)->Cpu[cpu].SystemRegister.FPSR); + json_key(&s, "FPSR"); + json_string(&s, hexStr); + + snprintf(hexStr, 32, "0x%llx", RO(Shm)->Cpu[cpu].SystemRegister.SVCR); + json_key(&s, "SVCR"); + json_string(&s, hexStr); + json_end_object(&s); + } + json_key(&s, "Slice"); + { + json_start_object(&s); + json_key(&s, "Delta"); + { + json_start_object(&s); + json_key(&s, "TSC"); + json_literal(&s, "%llu", RO(Shm)->Cpu[cpu].Slice.Delta.TSC); + json_key(&s, "INST"); + json_literal(&s, "%llu", RO(Shm)->Cpu[cpu].Slice.Delta.INST); + json_end_object(&s); + } + json_key(&s, "Counter"); + json_start_arr(&s); + for (i3 = 0; i3 < 3; i3++) { + json_start_object(&s); + json_key(&s, "TSC"); + json_literal(&s, "%u", RO(Shm)->Cpu[cpu].Slice.Counter[i3].TSC); + json_key(&s, "INST"); + json_literal(&s, "%u", RO(Shm)->Cpu[cpu].Slice.Counter[i3].INST); + json_end_object(&s); + } + json_end_arr(&s); + json_end_object(&s); + } + + json_end_object(&s); + } + json_end_arr(&s); + + json_end_object(&s); +} diff --git a/corefreq-cli-json.h b/aarch64/corefreq-cli-json.h similarity index 73% rename from corefreq-cli-json.h rename to aarch64/corefreq-cli-json.h index 7de36dc7..39de3675 100644 --- a/corefreq-cli-json.h +++ b/aarch64/corefreq-cli-json.h @@ -1,5 +1,5 @@ /* - * CoreFreq (C) 2015-2023 CYRIL COURTIAT + * CoreFreq (C) 2015-2024 CYRIL COURTIAT * Contributors: Andrew Gurinovich ; CyrIng * Licenses: GPL2 */ diff --git a/aarch64/corefreq-cli-rsc-en.h b/aarch64/corefreq-cli-rsc-en.h new file mode 100644 index 00000000..ed1629e3 --- /dev/null +++ b/aarch64/corefreq-cli-rsc-en.h @@ -0,0 +1,2087 @@ +/* + * CoreFreq + * Copyright (C) 2015-2024 CYRIL COURTIAT + * Licenses: GPL2 + */ + +#define RSC_COPY0_CODE_EN " by CyrIng " +#define RSC_COPY1_CODE_EN " " +#define RSC_COPY2_CODE_EN " (C)2015-2024 CYRIL COURTIAT " + +#define RSC_LAYOUT_LCD_RESET_CODE "::::" + +#define RSC_LAYOUT_HEADER_PROC_CODE_EN \ +{ \ + ' ','P','r','o','c','e','s','s','o','r',' ','[' \ +} + +#define RSC_LAYOUT_HEADER_CPU_CODE_EN \ +{ \ + ']',' ',' ',' ',' ','/',' ',' ',' ',' ','C','P','U' \ +} + +#define RSC_LAYOUT_HEADER_ARCH_CODE_EN \ +{ \ + ' ','A','r','c','h','i','t','e','c','t','u','r','e',' ','[' \ +} + +#define RSC_LAYOUT_HEADER_CACHE_L1_CODE_EN \ +{ \ + ']',' ','C','a','c','h','e','s',' ', \ + 'L','1',' ','I','n','s','t','=',' ',' ',' ', \ + 'D','a','t','a','=',' ',' ',' ','K','B' \ +} + +#define RSC_LAYOUT_HEADER_BCLK_CODE_EN \ +{ \ + ' ','B','a','s','e',' ','C','l','o','c','k',' ', \ + '~',' ','0','0','0',',','0','0','0',',','0','0','0',' ','H','z' \ +} + +#define RSC_LAYOUT_HEADER_CACHES_CODE_EN \ +{ \ + 'L','2','=',' ',' ',' ',' ',' ',' ',' ', \ + 'L','3','=',' ',' ',' ',' ',' ',' ','K','B' \ +} + +#define RSC_LAYOUT_RULER_LOAD_CODE_EN \ +{ \ + '-','-','-',' ', '!',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-' \ +} + +#define RSC_LAYOUT_RULER_REL_LOAD_CODE_EN \ +{ \ + 'R','e','l','a','t','i','v','e',' ','f','r','e','q','u','e','n',\ + 'c','y' \ +} + +#define RSC_LAYOUT_RULER_ABS_LOAD_CODE_EN \ +{ \ + 'A','b','s','o','l','u','t','e',' ','f','r','e','q','u','e','n',\ + 'c','y' \ +} + +#define RSC_LAYOUT_MONITOR_FREQUENCY_CODE_EN \ +{ \ + ' ',' ',' ',' ',' ',0x0,' ',' ',' ',0x0,' ',' ',0x0,' ',' ',0x0,\ + ' ',' ',' ',' ',0x0,' ',' ',0x0,' ',' ',' ',' ',0x0,' ',' ',0x0,\ + ' ',' ',' ',' ',0x0,' ',' ',0x0,' ',' ',' ',' ',0x0,' ',' ',0x0,\ + ' ',' ',' ',' ',0x0,' ',' ',0x0,' ',' ',' ',' ',0x0,' ',' ',0x0,\ + ' ',' ',' ',' ',' ',0x0,' ',' ',' ',0x0,' ',' ',' ' \ +} + +#define RSC_LAYOUT_MONITOR_INST_CODE_EN \ +{ \ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',0x0,' ',' ',' ',' ',\ + ' ',' ',0x0,0x0,' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',0x0,' ',\ + ' ',' ',' ',' ',' ',0x0,0x0,' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',0x0,' ',' ',' ',' ',' ',' ',0x0,0x0,' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ' \ +} + +#define RSC_LAYOUT_MONITOR_COMMON_CODE_EN \ +{ \ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ' \ +} + +#define RSC_LAYOUT_MONITOR_TASKS_CODE_EN \ +{ \ + ' ',' ',' ',' ',' ',0x0,' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ' \ +} + +#define RSC_LAYOUT_MONITOR_SLICE_CODE_EN \ +{ \ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ' \ +} + +#define RSC_LAYOUT_CUSTOM_FIELD_CODE_EN \ +{ \ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ' \ +} + +#define RSC_LAYOUT_RULER_FREQUENCY_CODE_EN \ +{ \ + '-','-','-',' ','F','r','e','q','(','M','H','z',')',' ','R','a',\ + 't','i','o',' ','-',' ','T','u','r','b','o',' ','-','-',' ','C',\ + '0',' ','-','-','-','-',' ','C','1',' ','-','-',' ','C','2',':',\ + 'C','3',' ','-',' ','C','4',':','C','6',' ','-','-','-',' ','C',\ + '7',' ','-','-',' ','M','i','n',' ','T','M','P',' ','M','a','x',\ + ' ','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-' \ +} + +#define RSC_LAYOUT_RULER_FREQUENCY_AVG_CODE_EN \ +{ \ + '-','-','-','-','-','-',' ','%',' ','A','v','e','r','a','g','e',\ + 's',' ','[',' ',' ',' ',' ',0x0,' ',' ',0x0,' ',' ',' ',' ',0x0,\ + ' ',' ',0x0,' ',' ',' ',' ',0x0,' ',' ',0x0,' ',' ',' ',' ',0x0,\ + ' ',' ',0x0,' ',' ',' ',' ',0x0,' ',' ',0x0,' ',' ',' ',' ',0x0,\ + ' ',' ',0x0,' ',']','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-' \ +} + +#define RSC_LAYOUT_RULER_FREQUENCY_PKG_CODE_EN \ +{ \ + '%',' ','P','k','g',' ','[',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',']',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-' \ +} + +#define RSC_LAYOUT_RULER_INST_CODE_EN \ +{ \ + '-','-','-','-','-','-','-','-','-','-','-','-',' ','I','P','S',\ + ' ','-','-','-','-','-','-','-','-','-','-','-','-','-','-',' ',\ + 'I','P','C',' ','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-',' ','C','P','I',' ','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-',' ','I','N','S','T',' ','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-' \ +} + +#define RSC_LAYOUT_RULER_CYCLES_CODE_EN \ +{ \ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-',' ','C',\ + '0',':','U','C','C',' ','-','-','-','-','-','-','-','-','-','-',\ + ' ','C','0',':','U','R','C',' ','-','-','-','-','-','-','-','-',\ + '-','-','-','-',' ','C','1',' ','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-',' ','T','S','C',' ','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-' \ +} + +#define RSC_LAYOUT_RULER_CSTATES_CODE_EN \ +{ \ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + ' ','C','1',' ','-','-','-','-','-','-','-','-','-','-','-','-',\ + ' ','C','2',':','C','3',' ','-','-','-','-','-','-','-','-','-',\ + '-','-',' ','C','4',':','C','6',' ','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-',' ','C','7',' ','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-' \ +} + +#define RSC_LAYOUT_RULER_INTERRUPTS_CODE_EN \ +{ \ + '-','-','-','-','-','-','-','-','-','-',' ','S','M','I',' ','-',\ + '-','-','-','-','-','-','-','-','-','-','-',' ','N','M','I','[',\ + ' ','L','O','C','A','L',' ',' ',' ','U','N','K','N','O','W','N',\ + ' ',' ','P','C','I','_','S','E','R','R','#',' ',' ','I','O','_',\ + 'C','H','E','C','K',']',' ','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-' \ +} + +#define RSC_LAYOUT_RULER_PACKAGE_CODE_EN \ + "------------ Cycles ---- State ------------------ Clock Rati" \ + "o ----------------------------------------------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "--------------------" + +#define RSC_LAYOUT_RULER_TASKS_CODE_EN \ + "--- Freq(MHz) --- Tasks -----------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "--------------------" + +#define RSC_LAYOUT_PACKAGE_PC_CODE_EN \ +{ \ + ' ',' ','0','0',':',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ' \ +} + +#define RSC_LAYOUT_PACKAGE_PC02_CODE_EN {'P', 'C', '0', '2'} +#define RSC_LAYOUT_PACKAGE_PC03_CODE_EN {'P', 'C', '0', '3'} +#define RSC_LAYOUT_PACKAGE_PC04_CODE_EN {'P', 'C', '0', '4'} +#define RSC_LAYOUT_PACKAGE_PC06_CODE_EN {'P', 'C', '0', '6'} +#define RSC_LAYOUT_PACKAGE_PC07_CODE_EN {'P', 'C', '0', '7'} +#define RSC_LAYOUT_PACKAGE_PC08_CODE_EN {'P', 'C', '0', '8'} +#define RSC_LAYOUT_PACKAGE_PC09_CODE_EN {'P', 'C', '0', '9'} +#define RSC_LAYOUT_PACKAGE_PC10_CODE_EN {'P', 'C', '1', '0'} +#define RSC_LAYOUT_PACKAGE_MC06_CODE_EN {'M', 'C', '0', '6'} + +#define RSC_LAYOUT_PACKAGE_UNCORE_CODE_EN \ +{ \ + ' ','T','S','C',':',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ','U','N','C','O','R','E',':',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\ + ' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ' \ +} + +#define RSC_LAYOUT_TASKS_STATE_SORTED_CODE_EN \ +{ \ + '(','s','o','r','t','e','d',' ', 'b','y', \ + ' ','S','t','a','t','e',')',' ', '-','-','-' \ +} + +#define RSC_LAYOUT_TASKS_RUNTIME_SORTED_CODE_EN \ +{ \ + '(','s','o','r','t','e','d',' ', 'b','y', \ + ' ','R','u','n','T','i','m','e', ')',' ','-' \ +} + +#define RSC_LAYOUT_TASKS_USRTIME_SORTED_CODE_EN \ +{ \ + '(','s','o','r','t','e','d',' ', 'b','y', \ + ' ','U','s','e','r','T','i','m', 'e',')',' ' \ +} + +#define RSC_LAYOUT_TASKS_SYSTIME_SORTED_CODE_EN \ +{ \ + '(','s','o','r','t','e','d',' ', 'b','y', \ + ' ','S','y','s','T','i','m','e', ')',' ','-' \ +} + +#define RSC_LAYOUT_TASKS_PROCESS_SORTED_CODE_EN \ +{ \ + '(','s','o','r','t','e','d',' ', 'b','y', \ + ' ','P','I','D',')',' ','-','-', '-','-','-' \ +} + +#define RSC_LAYOUT_TASKS_COMMAND_SORTED_CODE_EN \ +{ \ + '(','s','o','r','t','e','d',' ', 'b','y', \ + ' ','C','o','m','m','a','n','d', ')',' ','-' \ +} + +#define RSC_LAYOUT_TASKS_REVERSE_SORT_OFF_CODE_EN \ +{ \ + ' ', 'I','n','v','e','r','s','e',' ','[','O','F','F',']',' ' \ +} + +#define RSC_LAYOUT_TASKS_REVERSE_SORT_ON_CODE_EN \ +{ \ + ' ', 'I','n','v','e','r','s','e',' ','[',' ','O','N',']',' ' \ +} + +#define RSC_LAYOUT_TASKS_VALUE_SWITCH_CODE_EN \ +{ \ + ' ', 'V','a','l','u','e',' ','[',' ',' ',' ',']',' ' \ +} + +#define RSC_LAYOUT_TASKS_VALUE_OFF_CODE_EN \ +{ \ + 'O','F','F' \ +} + +#define RSC_LAYOUT_TASKS_VALUE_ON_CODE_EN \ +{ \ + ' ','O','N' \ +} + +#define RSC_LAYOUT_TASKS_TRACKING_CODE_EN \ +{ \ + ' ','T','r','a','c','k','i', 'n','g',' ','P','I','D',' ','[',' ',\ + ' ','O','F','F',' ',' ',']',' ' \ +} + +#define RSC_LAYOUT_RULER_SENSORS_CODE_EN \ + "--- Freq(MHz) --- Vcore --- TMP( ) --- Energy(J) --- Power(W" \ + ") ----------------------------------------------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "--------------------" + +#define RSC_LAYOUT_RULER_PWR_SOC_CODE_EN \ + "-RAM: . ( ) --- SoC : . ( ) -- Pkg[ ]: . ( ) " \ + "- Cores: . ( )-----------------------------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "--------------------" + +#define RSC_LAYOUT_RULER_VOLTAGE_CODE_EN \ + "--- Freq(MHz) - VID --- Min(V) - Vcore -- Max(V) -----------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "--------------------" + +#define RSC_LAYOUT_RULER_VPKG_SOC_CODE_EN \ + "- Processor[ ] ----- SoC " \ + "[ ] [ V]-----------------------------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "--------------------" + +#define RSC_LAYOUT_RULER_ENERGY_CODE_EN \ + "--- Freq(MHz) -- Accumulator -------- Min ------ Energy(J) -" \ + "- Max ------------------------------------------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "--------------------" + +#define RSC_LAYOUT_RULER_POWER_CODE_EN \ + "--- Freq(MHz) -- Accumulator -------- Min ------- Power(W) -" \ + "- Max ------------------------------------------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "--------------------" + +#define RSC_LAYOUT_RULER_SLICE_CODE_EN \ + "--- Freq(MHz) ------ Cycles -- Instructions ------------ TSC" \ + " ------------ PMC0 ----------- Error -----------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "--------------------" + +#define RSC_LAYOUT_RULER_CUSTOM_CODE_EN \ + "----- Min - Relative - Max ---- Min - Absolute - Max - Min T" \ + "MP Max - Min(V) - Vcore - Max(V) - Min( ) - Power -- Max( ) " \ + "- Turbo -- C0 -- C1 -- C2:C3 C4:C6 -- C7 --- IPS ----- IPC " \ + "----- CPI --------------------------------------------------" \ + "------------------------------------------------------------" \ + "--------------------" + +#define RSC_LAYOUT_FOOTER_TECH_TSC_CODE_EN \ +{ \ + 'T','e','c','h',' ','[',' ',' ','T','S','C',' ',' ',',' \ +} + +#define RSC_LAYOUT_FOOTER_VOLT_TEMP_CODE_EN \ +{ \ + 'V','[',' ','.',' ',' ',']',' ','T','[',' ',' ',' ',' ',']' \ +} + +#define RSC_LAYOUT_FOOTER_SYSTEM_CODE_EN \ +{ \ + 'T','a','s','k','s',' ','[',' ',' ',' ',' ',' ',' ',']', \ + ' ','M','e','m',' ','[',' ',' ',' ',' ',' ',' ',' ',' ', \ + ' ','/',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ','B',']' \ +} + +#define RSC_LAYOUT_FOOTER_TSC_NONE_CODE " TSC " +#define RSC_LAYOUT_FOOTER_TSC_VAR_CODE "TSC-VAR" +#define RSC_LAYOUT_FOOTER_TSC_INV_CODE "TSC-INV" + +#define RSC_LAYOUT_CARD_CORE_ONLINE_COND0_CODE_EN \ +{ \ + '[',' ',' ',' ',' ',' ',' ',' ',' ','C',' ',']' \ +} + +#define RSC_LAYOUT_CARD_CORE_ONLINE_COND1_CODE_EN \ +{ \ + '[',' ',' ',' ',' ',' ',' ',' ',' ','F',' ',']' \ +} + +#define RSC_LAYOUT_CARD_CORE_OFFLINE_CODE_EN \ +{ \ + '[',' ',' ',' ',' ',' ',' ','O','F','F',' ',']' \ +} + +#define RSC_LAYOUT_CARD_CLK_CODE_EN \ +{ \ + '[',' ','0','0','0','.','0',' ','M','H','z',']' \ +} + +#define RSC_LAYOUT_CARD_UNCORE_CODE_EN \ +{ \ + '[','U','N','C','O','R','E',' ',' ',' ',' ',']' \ +} + +#define RSC_LAYOUT_CARD_BUS_CODE_EN \ +{ \ + '[','B','u','s',' ',' ',' ',' ',' ',' ',' ',']' \ +} + +#define RSC_LAYOUT_CARD_MC_CODE_EN \ +{ \ + '[',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',']' \ +} + +#define RSC_LAYOUT_CARD_LOAD_CODE_EN \ +{ \ + '[',' ',' ','%','L','O','A','D',' ',' ',' ',']' \ +} + +#define RSC_LAYOUT_CARD_IDLE_CODE_EN \ +{ \ + '[',' ',' ','%','I','D','L','E',' ',' ',' ',']' \ +} + +#define RSC_LAYOUT_CARD_RAM_CODE_EN \ +{ \ + '[',' ',' ',' ',' ',' ',' ','/',' ',' ',' ',']' \ +} + +#define RSC_LAYOUT_CARD_TASK_CODE_EN \ +{ \ + '[','T','a','s','k','s',' ',' ',' ',' ',' ',']' \ +} + +#define RSC_CREATE_HOTPLUG_CPU_TITLE_CODE " CPU " +#define RSC_CREATE_HOTPLUG_CPU_ENABLE_CODE_EN "< ENABLE >" +#define RSC_CREATE_HOTPLUG_CPU_DISABLE_CODE_EN "< DISABLE >" +#define RSC_CREATE_HOTPLUG_CPU_ONLINE_CODE_EN " %03u On " +#define RSC_CREATE_HOTPLUG_CPU_OFFLINE_CODE_EN " %03u Off " + +#define RSC_COREFREQ_TITLE_CODE " CoreFreq " +#define RSC_PROCESSOR_TITLE_CODE_EN " Processor " +#define RSC_PROCESSOR_CODE_EN "Processor" +#define RSC_ARCHITECTURE_CODE_EN "Architecture" +#define RSC_VENDOR_ID_CODE_EN "Vendor ID" +#define RSC_REVISION_CODE_EN "Revision" +#define RSC_SIGNATURE_CODE_EN "Signature" +#define RSC_STEPPING_CODE_EN "Stepping" +#define RSC_ONLINE_CPU_CODE_EN "Online CPU" +#define RSC_BASE_CLOCK_CODE_EN "Base Clock" +#define RSC_FREQUENCY_CODE_EN "Frequency" +#define RSC_RATIO_CODE_EN "Ratio" +#define RSC_FACTORY_CODE_EN "Factory" +#define RSC_PERFORMANCE_CODE_EN "Performance" +#define RSC_TARGET_CODE_EN "Target" +#define RSC_UNLOCK_CODE_EN "UNLOCK" +#define RSC_LOCK_CODE_EN " LOCK" +#define RSC_ENABLE_CODE_EN " Enable" +#define RSC_DISABLE_CODE_EN "Disable" +#define RSC_CAPABILITIES_CODE_EN "Capabilities" +#define RSC_LOWEST_CODE_EN "Lowest" +#define RSC_EFFICIENT_CODE_EN "Efficient" +#define RSC_GUARANTEED_CODE_EN "Guaranteed" +#define RSC_HIGHEST_CODE_EN "Highest" +#define RSC_RECORDER_CODE_EN "Recorder" +#define RSC_STRESS_CODE_EN "Stress" +#define RSC_SYSGATE_CODE "SysGate" + +#define RSC_SCOPE_NONE_CODE_EN "None" +#define RSC_SCOPE_THREAD_CODE_EN " SMT" +#define RSC_SCOPE_CORE_CODE_EN "Core" +#define RSC_SCOPE_PACKAGE_CODE_EN " Pkg" + +#define RSC_SYS_REGS_TITLE_CODE_EN " System Registers " +#define RSC_SYS_REG_PSTATE_CODE_EN " Process State (PSTATE) " +#define RSC_SYS_REG_FLAG_N_CODE_EN " Negative " +#define RSC_SYS_REG_FLAG_Z_CODE_EN " Zero Flag " +#define RSC_SYS_REG_FLAG_C_CODE_EN " Carry Flag " +#define RSC_SYS_REG_FLAG_V_CODE_EN " Overflow " +#define RSC_SYS_REG_FLAG_D_CODE_EN " Endianness " +#define RSC_SYS_REG_FLAG_A_CODE_EN " SError " +#define RSC_SYS_REG_FLAG_I_CODE_EN " IRQ " +#define RSC_SYS_REG_FLAG_F_CODE_EN " FIQ " +#define RSC_SYS_REG_FLAG_EL_CODE_EN " Current EL " +#define RSC_SYS_REG_FLAG_SM_CODE_EN " SME ZA storage : Streaming SVE " + +#define RSC_SYS_REG_FLAG_SSBS_CODE_EN \ + " Speculative Store Bypass Safe (MSR & MRS) " + +#define RSC_SYS_REG_FLAG_NMI_CODE_EN " Non-maskable Interrupt " +#define RSC_SYS_REG_FLAG_PAN_CODE_EN " Privileged Access Never " +#define RSC_SYS_REG_FLAG_UAO_CODE_EN " User Access Override " +#define RSC_SYS_REG_FLAG_DIT_CODE_EN " Data Independent Timing " +#define RSC_SYS_REG_FLAG_TCO_CODE_EN " Tag Check Override " +#define RSC_SYS_REG_FLAG_PM_CODE_EN " PMU Exception Mask " + +#define RSC_SYS_REG_SCTL_CODE_EN " System Control Register (SCTLR_EL1) " +#define RSC_SYS_REG_TIDCP_CODE_EN " Implementation Defined System instructions " +#define RSC_SYS_REG_SPINT_CODE_EN " SP Interrupt Mask enable " +#define RSC_SYS_REG_NMI_CODE_EN " Non-Maskable Interrupt enable " +#define RSC_SYS_REG_EnTP2_CODE_EN " Read/Write Software Thread ID (TPIDR2_EL0) " +#define RSC_SYS_REG_TCSO_CODE_EN " Tag Checking Store Only " +#define RSC_SYS_REG_TCSO1_CODE_EN " Tag Checking Store Only (EL1) " +#define RSC_SYS_REG_TCSO0_CODE_EN " Tag Checking Store Only (EL0) " +#define RSC_SYS_REG_EPAN_CODE_EN " Enhanced Privileged Access Never " +#define RSC_SYS_REG_EnALS_CODE_EN " LD64B and ST64B instructions " +#define RSC_SYS_REG_EnAS0_CODE_EN " ST64BV0 instruction " +#define RSC_SYS_REG_EnASR_CODE_EN " ST64BV instruction " +#define RSC_SYS_REG_TME_CODE_EN " Transactional Memory Extension " +#define RSC_SYS_REG_TME1_CODE_EN " Transactional Memory Extension (EL1) " +#define RSC_SYS_REG_TME0_CODE_EN " Transactional Memory Extension (EL0) " +#define RSC_SYS_REG_TMT_CODE_EN " Trivial implementation of TME " +#define RSC_SYS_REG_TMT1_CODE_EN " TMT (EL1) " +#define RSC_SYS_REG_TMT0_CODE_EN " TMT (EL0) " +#define RSC_SYS_REG_TWE_D_CODE_EN " TWE Delay " +#define RSC_SYS_REG_TWE_C_CODE_EN " TWE Delay cycles " +#define RSC_SYS_REG_TWE_E_CODE_EN " TWE Delay enable " +#define RSC_SYS_REG_DSSBS_CODE_EN " Speculative Store Bypass Safe (Exception) " +#define RSC_SYS_REG_ATA_CODE_EN " Allocation Tag Access " +#define RSC_SYS_REG_ATA1_CODE_EN " Allocation Tag Access (EL1) " +#define RSC_SYS_REG_ATA0_CODE_EN " Allocation Tag Access (EL0) " +#define RSC_SYS_REG_TCF_CODE_EN " Tag Check Fault " +#define RSC_SYS_REG_TCF1_CODE_EN " Tag Check Fault (EL1) " +#define RSC_SYS_REG_TCF0_CODE_EN " Tag Check Fault (EL0) " +#define RSC_SYS_REG_ITFSB_CODE_EN " Tag Fault Status (TFSRE0_EL1 & TFSR_EL1) " +#define RSC_SYS_REG_BT_CODE_EN " Branch Target Identification " +#define RSC_SYS_REG_BT1_CODE_EN " PAC Branch Type compatibility (EL1) " +#define RSC_SYS_REG_BT0_CODE_EN " PAC Branch Type compatibility (EL0) " +#define RSC_SYS_REG_EnFPM_CODE_EN " Floating-Point Mode enable " +#define RSC_SYS_REG_MSCEn_CODE_EN " Memory Copy and Memory Set instructions " +#define RSC_SYS_REG_CMOW_CODE_EN " Control for Cache Maintenance permission " +#define RSC_SYS_REG_EnIA_CODE_EN " Pointer Authentication (APIAKey_EL1) " +#define RSC_SYS_REG_EnIB_CODE_EN " Pointer Authentication (APIBKey_EL1) " +#define RSC_SYS_REG_LSM_CODE_EN " Load Multiple and Store Multiple " +#define RSC_SYS_REG_LSMA_CODE_EN " LSM Atomicity and Ordering " +#define RSC_SYS_REG_LSMD_CODE_EN " LSM to Device-{nGRE,nGnRE,nGnRnE} memory " +#define RSC_SYS_REG_EnDA_CODE_EN " Pointer Authentication (APDAKey_EL1) " +#define RSC_SYS_REG_UCI_CODE_EN " Cache Maintenance Instructions " +#define RSC_SYS_REG_EE_CODE_EN " Exception Endianness (EL1) " +#define RSC_SYS_REG_E0E_CODE_EN " Exception Endianness (EL0) " +#define RSC_SYS_REG_SPAN_CODE_EN " Set Privileged Access Never " +#define RSC_SYS_REG_EIS_CODE_EN " Context Synchronizing Exception Entry " +#define RSC_SYS_REG_IESB_CODE_EN " Implicit Error Synchronization Event " +#define RSC_SYS_REG_TSCXT_CODE_EN " Read/Write Software Context Number " +#define RSC_SYS_REG_WXN_CODE_EN " Write Execute-Never " +#define RSC_SYS_REG_nTWE_CODE_EN " WFE instructions " +#define RSC_SYS_REG_nTWI_CODE_EN " WFI instructions " +#define RSC_SYS_REG_UCT_CODE_EN " Cache Type Register (CTR_EL0) " +#define RSC_SYS_REG_DZE_CODE_EN " Data Cache Zero instructions " +#define RSC_SYS_REG_EnDB_CODE_EN " Pointer Authentication (APDBKey_EL1) " +#define RSC_SYS_REG_I_CODE_EN " Instruction access Cacheability control " +#define RSC_SYS_REG_EOS_CODE_EN " Context Synchronizing Exception Exit " +#define RSC_SYS_REG_RCTX_CODE_EN " Restriction by Context system instructions " +#define RSC_SYS_REG_UMA_CODE_EN " User Mask Access " +#define RSC_SYS_REG_SED_CODE_EN " SETEND instruction disable " +#define RSC_SYS_REG_ITD_CODE_EN " IT instructions disable " +#define RSC_SYS_REG_nAA_CODE_EN " Non-Aligned Access " +#define RSC_SYS_REG_CP15B_CODE_EN " Memory Barrier system instructions " +#define RSC_SYS_REG_SA0_CODE_EN " SP Alignment check (EL0) " +#define RSC_SYS_REG_SA1_CODE_EN " SP Alignment check (EL1) " +#define RSC_SYS_REG_C_CODE_EN " Cacheability control for data accesses " +#define RSC_SYS_REG_A_CODE_EN " Alignment check enable " +#define RSC_SYS_REG_M_CODE_EN " Memory Management Unit enable " + +#define RSC_SYS_REG_SCTL2_CODE_EN " System Control Register (SCTLR2_EL1) " +#define RSC_SYS_REG_CPTM_CODE_EN " Check Pointer Arithmetic for Multiplication " +#define RSC_SYS_REG_CPTM0_CODE_EN " CPTM (EL0) " +#define RSC_SYS_REG_CPTM1_CODE_EN " CPTM (EL1) " +#define RSC_SYS_REG_CPTA_CODE_EN " Check Pointer Arithmetic for Addition " +#define RSC_SYS_REG_CPTA0_CODE_EN " CPTA (EL0) " +#define RSC_SYS_REG_CPTA1_CODE_EN " CPTA (EL1) " +#define RSC_SYS_REG_PACM_CODE_EN " Pointer Authentication Modifier " +#define RSC_SYS_REG_PACM0_CODE_EN " PACM (EL0) " +#define RSC_SYS_REG_PACM1_CODE_EN " PACM (EL1) " +#define RSC_SYS_REG_128SR_CODE_EN " Enable 128-bit System registers " +#define RSC_SYS_REG_EASE_CODE_EN " External Aborts to SError Exception " +#define RSC_SYS_REG_ANERR_CODE_EN " Asynchronous Normal Read Error " +#define RSC_SYS_REG_ADERR_CODE_EN " Asynchronous Device Read Error " +#define RSC_SYS_REG_NMEA_CODE_EN " Non-Maskable External Aborts " + +#define RSC_SYS_REG_FPSR_CODE_EN " Floating-point Status Register " +#define RSC_SYS_REG_FPSR_QC_CODE_EN " Cumulative Saturation " +#define RSC_SYS_REG_FPSR_IDC_CODE_EN " Input Denormal Cumulative " +#define RSC_SYS_REG_FPSR_IXC_CODE_EN " Inexact Cumulative " +#define RSC_SYS_REG_FPSR_UFC_CODE_EN " Underflow Cumulative " +#define RSC_SYS_REG_FPSR_OFC_CODE_EN " Overflow Cumulative " +#define RSC_SYS_REG_FPSR_DZC_CODE_EN " Divide by Zero Cumulative " +#define RSC_SYS_REG_FPSR_IOC_CODE_EN " Invalid Operation Cumulative " + +#define RSC_SYS_REG_EL_CODE_EN " Exception Level " +#define RSC_SYS_REG_EL_EXEC_CODE_EN " Executes in AArch64 or AArch32 " +#define RSC_SYS_REG_EL_SEC_CODE_EN " Secure Exception Level " + +#define RSC_ISA_TITLE_CODE_EN " Instruction Set Extensions " + +#define RSC_ISA_AES_COMM_CODE_EN " Advanced Encryption Standard " +#define RSC_ISA_LSE_COMM_CODE_EN " Atomic instructions " +#define RSC_ISA_CRC32_COMM_CODE_EN " Cyclic Redundancy Check " +#define RSC_ISA_DP_COMM_CODE_EN " Dot Product instructions " +#define RSC_ISA_EPAC_COMM_CODE_EN " Enhanced Pointer Authentication " +#define RSC_ISA_FCMA_COMM_CODE_EN \ + " Floating-point Complex Multiplication & Addition " + +#define RSC_ISA_FHM_COMM_CODE_EN \ + " Floating-point Half-precision Multiplication " + +#define RSC_ISA_FP_COMM_CODE_EN " Floating Point " +#define RSC_ISA_FPAC_COMM_CODE_EN " Faulting Pointer Authentication Code " +#define RSC_ISA_FPACCOMBINE_COMM_CODE_EN \ + " Faulting on Combined Pointer Authentication " + +#define RSC_ISA_JSCVT_COMM_CODE_EN " JavaScript Conversion " +#define RSC_ISA_LRCPC_COMM_CODE_EN " Load-Acquire RCpc instructions " + +#define RSC_ISA_LUT_COMM_CODE_EN \ + " ASIMD & SVE2 LookUp Table instructions " + +#define RSC_ISA_MOPS_COMM_CODE_EN \ + " Memory Copy and Memory Set instructions " + +#define RSC_ISA_PACIMP_COMM_CODE_EN \ + " Pointer Authentication Code, using Generic key " + +#define RSC_ISA_PACQARMA3_COMM_CODE_EN \ + " Pointer Authentication Code, using the QARMA3 algorithm " + +#define RSC_ISA_PACQARMA5_COMM_CODE_EN \ + " Pointer Authentication Code, using the QARMA5 algorithm " + +#define RSC_ISA_PAUTH_COMM_CODE_EN " Pointer Authentication " +#define RSC_ISA_PAUTH2_COMM_CODE_EN " Enhanced Pointer Authentication " +#define RSC_ISA_PAUTH_LR_COMM_CODE_EN " Pointer Authentication Link Register " +#define RSC_ISA_PRFMSLC_COMM_CODE_EN " PRFM instructions support SLC target " +#define RSC_ISA_FRINTTS_COMM_CODE_EN " Floating-point to Integer " +#define RSC_ISA_SPECRES_COMM_CODE_EN " Prediction Invalidation " +#define RSC_ISA_ATS1A_COMM_CODE_EN " Address Translation Stage 1 " +#define RSC_ISA_BF16_COMM_CODE_EN " BFloat16 instructions " +#define RSC_ISA_EBF16_COMM_CODE_EN " Extended BFloat16 " +#define RSC_ISA_CONSTPACFLD_COMM_CODE_EN \ + " Determine the size of the PAC Field " + +#define RSC_ISA_CSSC_COMM_CODE_EN " Common Short Sequence Compression " +#define RSC_ISA_HBC_COMM_CODE_EN " Hinted Conditional Branch " +#define RSC_ISA_I8MM_COMM_CODE_EN " Int8 Matrix Multiplication " +#define RSC_ISA_RPRES_COMM_CODE_EN \ + " Reciprocal Estimate & Reciprocal Square Root Estimate " + +#define RSC_ISA_SB_COMM_CODE_EN " Speculation Barrier " +#define RSC_ISA_SYSREG128_COMM_CODE_EN \ + " Instructions to access 128-bit System Registers " + +#define RSC_ISA_SYSINSTR128_COMM_CODE_EN \ + " System instructions that can take 128-bit inputs " + +#define RSC_ISA_WFxT_COMM_CODE_EN " WFE & WFI instructions with timeout " +#define RSC_ISA_XS_COMM_CODE_EN " XS attribute for memory " +#define RSC_ISA_LS64_COMM_CODE_EN " Atomic 64-byte loads and stores " +#define RSC_ISA_DGH_COMM_CODE_EN " Data Gathering Hint " +#define RSC_ISA_DPB_COMM_CODE_EN " Data Persistence writeback " +#define RSC_ISA_RAND_COMM_CODE_EN " Read Random Number " +#define RSC_ISA_RDMA_COMM_CODE_EN " Rounding Double Multiply Accumulate " +#define RSC_ISA_RNG_TRAP_COMM_CODE_EN " Trapping support for RNDR and RNDRRS " +#define RSC_ISA_RPRFM_COMM_CODE_EN " RPRFM hint instruction " +#define RSC_ISA_SHA_COMM_CODE_EN " Secure Hash Algorithms extensions " +#define RSC_ISA_SM_COMM_CODE_EN " Chinese cryptography algorithm " +#define RSC_ISA_SIMD_COMM_CODE_EN " Advanced SIMD Extensions " +#define RSC_ISA_SME_COMM_CODE_EN " Scalable Matrix Extension " +#define RSC_ISA_SVE_COMM_CODE_EN " Scalable Vector Extension " +#define RSC_ISA_FlagM_COMM_CODE_EN " Flag manipulation instructions " + +#define RSC_FEATURES_TITLE_CODE_EN " Features " +#define RSC_ON_CODE_EN " ON" +#define RSC_OFF_CODE_EN "OFF" +#define RSC_FMW_CODE_EN "FMW" +#define RSC_NOT_AVAILABLE_CODE_EN "N/A" +#define RSC_AUTOMATIC_CODE_EN "AUTO" +#define RSC_UNABLE_CODE_EN "Unable" +#define RSC_MISSING_CODE_EN "Missing" +#define RSC_PRESENT_CODE_EN "Capable" +#define RSC_VARIANT_CODE_EN "Variant" +#define RSC_INVARIANT_CODE_EN "Invariant" + +#define RSC_FEATURES_ACPI_CODE_EN "Advanced Configuration & Power Interface" +#define RSC_FEATURES_AMU_CODE_EN "Activity Monitor Unit" +#define RSC_FEATURES_BIG_END_CODE_EN "Mixed-Endianness" +#define RSC_FEATURES_BTI_CODE_EN "Branch Target Identification" +#define RSC_FEATURES_EBEP_CODE_EN "Exception-based event profiling" +#define RSC_FEATURES_ECBHB_CODE_EN \ + "Exploitative Control w/ Branch History Buffer" + +#define RSC_FEATURES_ECV_CODE_EN "Enhanced Counter Virtualization" +#define RSC_FEATURES_DF2_CODE_EN "Double Fault Extension" +#define RSC_FEATURES_DIT_CODE_EN "Data Independent Timing" +#define RSC_FEATURES_EXS_CODE_EN "Context Synchronization & Exception Handling" +#define RSC_FEATURES_FGT_CODE_EN "Fine-Grained Trap controls" +#define RSC_FEATURES_PFAR_CODE_EN "Physical Fault Address Registers" +#define RSC_FEATURES_GCS_CODE_EN "Guarded Control Stack" +#define RSC_FEATURES_GIC_CODE_EN "Generic Interrupt Controller" +#define RSC_FEATURES_MPAM_CODE_EN "Memory Partitioning and Monitoring" +#define RSC_FEATURES_MTE_CODE_EN "Memory Tagging Extension" +#define RSC_FEATURES_NMI_CODE_EN "Non Maskable Interrupt" +#define RSC_FEATURES_PA_CODE_EN "Physical Address range" +#define RSC_FEATURES_PAN_CODE_EN "Privileged Access Never" +#define RSC_FEATURES_RAS_CODE_EN "Reliability Availability & Serviceability" +#define RSC_FEATURES_RME_CODE_EN "Realm Management Extension" +#define RSC_FEATURES_SEL2_CODE_EN "Secure EL2 Implementation" +#define RSC_FEATURES_THE_CODE_EN "Translation Hardening Extension" +#define RSC_FEATURES_TLB_CODE_EN "TLB maintenance instructions" +#define RSC_FEATURES_TME_CODE_EN "Transactional Memory Extension" +#define RSC_FEATURES_TSC_CODE_EN "Time Stamp Counter" +#define RSC_FEATURES_UAO_CODE_EN "User Access Override" +#define RSC_FEATURES_VA_CODE_EN "Virtual Address range" +#define RSC_FEATURES_VHE_CODE_EN "Virtualization Host Extensions" +#define RSC_FEAT_SECTION_MECH_CODE_EN "Mitigation mechanisms" +#define RSC_FEAT_SECTION_SEC_CODE_EN "Security Features" + +#define RSC_TECHNOLOGIES_TITLE_CODE_EN " Technologies " +#define RSC_TECHNOLOGIES_DCU_CODE_EN "Data Cache Unit" +#define RSC_TECHNOLOGIES_ICU_CODE_EN "Instruction Cache Unit" +#define RSC_TECHNOLOGIES_VM_CODE_EN "Virtualization" +#define RSC_TECHNOLOGIES_IOMMU_CODE_EN "I/O MMU" +#define RSC_TECHNOLOGIES_SMT_CODE_EN "Simultaneous Multithreading" +#define RSC_TECHNOLOGIES_HYBRID_CODE_EN "big.LITTLE technology" +#define RSC_TECHNOLOGIES_HYPERV_CODE_EN "Hypervisor" +#define RSC_TECHNOLOGIES_VM_COMM_CODE_EN " Virtual Machine Hypervisor " +#define RSC_TECHNOLOGIES_IOMMU_COMM_CODE_EN " I/O MMU virtualization " + +#define RSC_PERF_MON_TITLE_CODE_EN " Performance Monitoring " +#define RSC_PERF_CAPS_TITLE_CODE_EN " Performance Capabilities " +#define RSC_VERSION_CODE_EN "Version" +#define RSC_COUNTERS_CODE_EN "Counters" +#define RSC_GENERAL_CTRS_CODE_EN "General" +#define RSC_FIXED_CTRS_CODE_EN "Fixed" +#define RSC_PERF_MON_UNIT_BIT_CODE_EN "bits" +#define RSC_PERF_MON_CPPC_CODE_EN "Collaborative Processor Performance Control" +#define RSC_PERF_MON_PCT_CODE_EN "Processor Performance Control" +#define RSC_PERF_MON_PSS_CODE_EN "Performance Supported States" +#define RSC_PERF_MON_PPC_CODE_EN "Performance Present Capabilities" +#define RSC_PERF_MON_CPC_CODE_EN "Continuous Performance Control" +#define RSC_PERF_MON_CST_CODE_EN "ACPI Processor C-States" +#define RSC_PERF_MON_HWP_CODE_EN "Hardware-Controlled Performance States" +#define RSC_PERF_MON_CORE_CSTATE_CODE_EN "Core C-States" +#define RSC_PERF_MON_CSTATE_BAR_CODE_EN "C-States Base Address" + +#define RSC_PERF_MON_MONITOR_MWAIT_CODE_EN "MONITOR/MWAIT" +#define RSC_PERF_MON_MWAIT_IDX_CSTATE_CODE_EN "State index" +#define RSC_PERF_MON_MWAIT_SUB_CSTATE_CODE_EN "Sub C-State" + +#define RSC_PERF_MON_CORE_CYCLE_CODE_EN "Core Cycles Counter" +#define RSC_PERF_MON_INST_RET_CODE_EN "Instructions Counter" + +#define RSC_PERF_MON_PMC_COMM_CODE_EN \ + " { Core performance monitoring, AMU-CG0NC, AMU-CG1NC } " + +#define RSC_PERF_MON_CPPC_COMM_CODE_EN " Firmware " + +#define RSC_POWER_THERMAL_TITLE_CODE_EN " Power, Current & Thermal " +#define RSC_POWER_THERMAL_CPPC_CODE_EN "CPPC Energy Preference" +#define RSC_POWER_THERMAL_TJMAX_CODE_EN "Temperature Offset:Junction" +#define RSC_POWER_THERMAL_DTS_CODE_EN "Digital Thermal Sensor" +#define RSC_POWER_THERMAL_PLN_CODE_EN "Power Limit Notification" +#define RSC_POWER_THERMAL_PTM_CODE_EN "Package Thermal Management" +#define RSC_POWER_THERMAL_UNITS_CODE_EN "Units" +#define RSC_POWER_THERMAL_POWER_CODE_EN "Power" +#define RSC_POWER_THERMAL_ENERGY_CODE_EN "Energy" +#define RSC_POWER_THERMAL_WINDOW_CODE_EN "Window" +#define RSC_POWER_THERMAL_WATT_CODE_EN "watt" +#define RSC_POWER_THERMAL_JOULE_CODE_EN "joule" +#define RSC_POWER_THERMAL_SECOND_CODE_EN "second" +#define RSC_POWER_THERMAL_TDP_CODE_EN "Thermal Design Power" +#define RSC_POWER_THERMAL_MIN_CODE_EN "Minimum Power" +#define RSC_POWER_THERMAL_MAX_CODE_EN "Maximum Power" +#define RSC_POWER_THERMAL_TPL_CODE_EN "Power Limit" +#define RSC_POWER_THERMAL_TW_CODE_EN "Time Window" +#define RSC_POWER_THERMAL_EDC_CODE_EN "Electrical Design Current" +#define RSC_POWER_THERMAL_TDC_CODE_EN "Thermal Design Current" +#define RSC_POWER_THERMAL_POINT_CODE_EN "Thermal Point" + +#define RSC_THERMAL_POINT_THRESHOLD_CODE_EN "Threshold" +#define RSC_THERMAL_POINT_LIMIT_CODE_EN "Limit" +#define RSC_THERMAL_POINT_THRESHOLD_1_CODE_EN "DTS Threshold #1" +#define RSC_THERMAL_POINT_THRESHOLD_2_CODE_EN "DTS Threshold #2" +#define RSC_THERMAL_POINT_TRIP_LIMIT_CODE_EN "Thermal Monitor Trip" +#define RSC_THERMAL_POINT_HTC_LIMIT_CODE_EN "HTC Temperature Limit" +#define RSC_THERMAL_POINT_HTC_HYST_CODE_EN "HTC Temperature Hysteresis" + +#define RSC_THERMAL_OFFSET_TITLE_CODE_EN " Thermal Offset " + +#define RSC_KERNEL_TITLE_CODE_EN " Kernel " +#define RSC_KERNEL_TOTAL_RAM_CODE_EN "Total RAM" +#define RSC_KERNEL_SHARED_RAM_CODE_EN "Shared RAM" +#define RSC_KERNEL_FREE_RAM_CODE_EN "Free RAM" +#define RSC_KERNEL_BUFFER_RAM_CODE_EN "Buffer RAM" +#define RSC_KERNEL_TOTAL_HIGH_CODE_EN "Total High" +#define RSC_KERNEL_FREE_HIGH_CODE_EN "Free High" +#define RSC_KERNEL_GOVERNOR_CODE_EN "Governor" +#define RSC_KERNEL_FREQ_DRIVER_CODE_EN "CPU-Freq driver" +#define RSC_KERNEL_IDLE_DRIVER_CODE_EN "CPU-Idle driver" +#define RSC_KERNEL_CLOCK_SOURCE_CODE_EN "Clock Source" +#define RSC_KERNEL_RELEASE_CODE_EN "Release" +#define RSC_KERNEL_VERSION_CODE_EN "Version" +#define RSC_KERNEL_MACHINE_CODE_EN "Machine" +#define RSC_KERNEL_MEMORY_CODE_EN "Memory" +#define RSC_KERNEL_STATE_CODE_EN "State" +#define RSC_KERNEL_POWER_CODE_EN "Power" +#define RSC_KERNEL_LATENCY_CODE_EN "Latency" +#define RSC_KERNEL_RESIDENCY_CODE_EN "Residency" +#define RSC_KERNEL_LIMIT_CODE_EN "Idle Limit" + +#define RSC_TOPOLOGY_TITLE_CODE_EN " Topology " + +#define RSC_MEM_CTRL_TITLE_CODE_EN " Memory Controller " +#define RSC_MEM_CTRL_SUBSECT1_0_CODE_EN "Contr" +#define RSC_MEM_CTRL_SUBSECT1_1_CODE_EN "oller" +#define RSC_MEM_CTRL_SUBSECT1_2_CODE_EN " #%-3u" +#define RSC_MEM_CTRL_SINGLE_CHA_0_CODE_EN "Singl" +#define RSC_MEM_CTRL_SINGLE_CHA_1_CODE_EN "e Cha" +#define RSC_MEM_CTRL_SINGLE_CHA_2_CODE_EN "nnel " +#define RSC_MEM_CTRL_DUAL_CHA_0_CODE_EN " Dual" +#define RSC_MEM_CTRL_DUAL_CHA_1_CODE_EN " Chan" +#define RSC_MEM_CTRL_DUAL_CHA_2_CODE_EN "nel " +#define RSC_MEM_CTRL_TRIPLE_CHA_0_CODE_EN "Tripl" +#define RSC_MEM_CTRL_TRIPLE_CHA_1_CODE_EN "e Cha" +#define RSC_MEM_CTRL_TRIPLE_CHA_2_CODE_EN "nnel " +#define RSC_MEM_CTRL_QUAD_CHA_0_CODE_EN " Quad" +#define RSC_MEM_CTRL_QUAD_CHA_1_CODE_EN " Chan" +#define RSC_MEM_CTRL_QUAD_CHA_2_CODE_EN "nel " +#define RSC_MEM_CTRL_SIX_CHA_0_CODE_EN " Six" +#define RSC_MEM_CTRL_SIX_CHA_1_CODE_EN " Chan" +#define RSC_MEM_CTRL_SIX_CHA_2_CODE_EN "nel " +#define RSC_MEM_CTRL_EIGHT_CHA_0_CODE_EN "Eight" +#define RSC_MEM_CTRL_EIGHT_CHA_1_CODE_EN " Chan" +#define RSC_MEM_CTRL_EIGHT_CHA_2_CODE_EN "nel " +#define RSC_MEM_CTRL_DISABLED_0_CODE_EN " " +#define RSC_MEM_CTRL_DISABLED_1_CODE_EN "Disab" +#define RSC_MEM_CTRL_DISABLED_2_CODE_EN "led " +#define RSC_MEM_CTRL_BUS_RATE_0_CODE_EN " Bus " +#define RSC_MEM_CTRL_BUS_RATE_1_CODE_EN "Rate " +#define RSC_MEM_CTRL_BUS_SPEED_0_CODE_EN " Bus " +#define RSC_MEM_CTRL_BUS_SPEED_1_CODE_EN "Speed" +#define RSC_MEM_CTRL_RAM_STD_0_CODE_EN " " +#define RSC_MEM_CTRL_RAM_STD_1_CODE_EN " " +#define RSC_MEM_CTRL_RAM_STD_2_CODE_EN " LP" +#define RSC_MEM_CTRL_RAM_STD_3_CODE_EN " REG " +#define RSC_MEM_CTRL_DRAM_DDR2_0_CODE_EN "DDR2 " +#define RSC_MEM_CTRL_DRAM_DDR3_0_CODE_EN "DDR3 " +#define RSC_MEM_CTRL_DRAM_DDR4_0_CODE_EN "DDR4 " +#define RSC_MEM_CTRL_DRAM_DDR5_0_CODE_EN "DDR5 " +#define RSC_MEM_CTRL_DRAM_SPEED_0_CODE_EN "DRAM " +#define RSC_MEM_CTRL_DRAM_SPEED_1_CODE_EN "Speed" +#define RSC_MEM_CTRL_SUBSECT2_0_CODE_EN " DIMM" +#define RSC_MEM_CTRL_SUBSECT2_1_CODE_EN " Geom" +#define RSC_MEM_CTRL_SUBSECT2_2_CODE_EN "etry " +#define RSC_MEM_CTRL_SUBSECT2_3_CODE_EN "for c" +#define RSC_MEM_CTRL_SUBSECT2_4_CODE_EN "hanne" +#define RSC_MEM_CTRL_SUBSECT2_5_CODE_EN "l #%-2u" +#define RSC_MEM_CTRL_DIMM_SLOT_CODE_EN " Slot" +#define RSC_MEM_CTRL_DIMM_BANK_CODE_EN " Bank" +#define RSC_MEM_CTRL_DIMM_RANK_CODE_EN " Rank" +#define RSC_MEM_CTRL_DIMM_ROW_CODE_EN "Rows " +#define RSC_MEM_CTRL_DIMM_COLUMN0_CODE_EN " Col" +#define RSC_MEM_CTRL_DIMM_COLUMN1_CODE_EN "umns " +#define RSC_MEM_CTRL_DIMM_SIZE_0_CODE_EN " Me" +#define RSC_MEM_CTRL_DIMM_SIZE_1_CODE_EN "mory " +#define RSC_MEM_CTRL_DIMM_SIZE_2_CODE_EN "Size " +#define RSC_MEM_CTRL_DIMM_SIZE_3_CODE_EN "(MB) " + +#define RSC_DDR3_CL_COMM_CODE_EN " tCL ( CAS Latency ) " +#define RSC_DDR3_RCD_COMM_CODE_EN " tRCD ( Activate to CAS ) " +#define RSC_DDR3_RP_COMM_CODE_EN " tRP ( RAS Precharge to Activate ) " +#define RSC_DDR3_RAS_COMM_CODE_EN " tRAS ( Activate to Precharge ) " +#define RSC_DDR3_RRD_COMM_CODE_EN " tRRD ( Activate to Activate, Same Rank ) " +#define RSC_DDR3_RFC_COMM_CODE_EN " tRFC ( Refresh to Refresh ) " +#define RSC_DDR3_WR_COMM_CODE_EN " tWR ( Write Recovery ) " +#define RSC_DDR3_RTP_COMM_CODE_EN " tRTPr ( Read CAS to Precharge ) " +#define RSC_DDR3_WTP_COMM_CODE_EN " tWTPr ( Write CAS to Precharge ) " +#define RSC_DDR3_FAW_COMM_CODE_EN " tFAW ( Four Activate Window ) " +#define RSC_DDR3_B2B_COMM_CODE_EN " tCCD ( CAS commands spacing ) " +#define RSC_DDR3_CWL_COMM_CODE_EN " tCWL ( CAS Write Latency ) " +#define RSC_DDR3_CMD_COMM_CODE_EN " CMD ( Command Rate ) " +#define RSC_DDR3_REFI_COMM_CODE_EN " tREFI ( Refresh Interval ) " + +#define RSC_DDR3_DDWRTRD_COMM_CODE_EN \ + " tddWrTRd ( Write to Read, Different DIMM ) " + +#define RSC_DDR3_DRWRTRD_COMM_CODE_EN \ + " tdrWrTRd ( Write to Read, Different Rank, Same DIMM ) " + +#define RSC_DDR3_SRWRTRD_COMM_CODE_EN " tsrWrTRd ( Write to Read, Same Rank ) " + +#define RSC_DDR3_DDRDTWR_COMM_CODE_EN \ + " tddRdTWr ( Read to Write, Different DIMM ) " + +#define RSC_DDR3_DRRDTWR_COMM_CODE_EN \ + " tdrRdTWr ( Read to Write, Different Rank, Same DIMM ) " + +#define RSC_DDR3_SRRDTWR_COMM_CODE_EN " tsrRdTWr ( Read to Write, Same Rank ) " + +#define RSC_DDR3_DDRDTRD_COMM_CODE_EN \ + " tddRdTRd ( Read to Read, Different DIMM ) " + +#define RSC_DDR3_DRRDTRD_COMM_CODE_EN \ + " tdrRdTRd ( Read to Read, Different Rank, Same DIMM ) " + +#define RSC_DDR3_SRRDTRD_COMM_CODE_EN " tsrRdTRd ( Read to Read, Same Rank ) " + +#define RSC_DDR3_DDWRTWR_COMM_CODE_EN \ + " tddWrTWr ( Write to Write, Different DIMM ) " + +#define RSC_DDR3_DRWRTWR_COMM_CODE_EN \ + " tdrWrTWr ( Write to Write, Different Rank, Same DIMM ) " + +#define RSC_DDR3_SRWRTWR_COMM_CODE_EN " tsrWrTWr ( Write to Write, Same Rank ) " + +#define RSC_DDR3_XS_COMM_CODE_EN " tXS ( Exit Self refresh to commands" \ + " not requiring a locked DLL ) " + +#define RSC_DDR3_XP_COMM_CODE_EN " tXP ( Exit Power-down with DLL on " \ + "to any valid command ) " + +#define RSC_DDR3_CKE_COMM_CODE_EN " tCKE ( ClocK Enable ) " +#define RSC_DDR3_ECC_COMM_CODE_EN " ECC ( Error Correcting Code ) " + +#define RSC_DDR4_RCD_R_COMM_CODE_EN " tRCD_R ( Activate to Read CAS ) " +#define RSC_DDR4_RCD_W_COMM_CODE_EN " tRCD_W ( Activate to Write CAS ) " +#define RSC_DDR4_RDRD_SCL_COMM_CODE_EN " tRDRD ( Read to Read, Same Bank ) " +#define RSC_DDR4_RDRD_SC_COMM_CODE_EN " tRDRD ( Read to Read, Different Bank ) " +#define RSC_DDR4_RDRD_SD_COMM_CODE_EN " tRDRD ( Read to Read, Different Rank ) " +#define RSC_DDR4_RDRD_DD_COMM_CODE_EN " tRDRD ( Read to Read, Different DIMM ) " +#define RSC_DDR4_RDWR_SCL_COMM_CODE_EN " tRDWR ( Read to Write, Same Bank ) " + +#define RSC_DDR4_RDWR_SC_COMM_CODE_EN \ + " tRDWR ( Read to Write, Different Bank ) " + +#define RSC_DDR4_RDWR_SD_COMM_CODE_EN \ + " tRDWR ( Read to Write, Different Rank ) " + +#define RSC_DDR4_RDWR_DD_COMM_CODE_EN \ + " tRDWR ( Read to Write, Different DIMM ) " + +#define RSC_DDR4_WRRD_SCL_COMM_CODE_EN " tWRRD ( Write to Read, Same Bank ) " + +#define RSC_DDR4_WRRD_SC_COMM_CODE_EN \ + " tWRRD ( Write to Read, Different Bank ) " + +#define RSC_DDR4_WRRD_SD_COMM_CODE_EN \ + " tWRRD ( Write to Read, Different Rank ) " + +#define RSC_DDR4_WRRD_DD_COMM_CODE_EN \ + " tWRRD ( Write to Read, Different DIMM ) " + +#define RSC_DDR4_WRWR_SCL_COMM_CODE_EN " tWRWR ( Write to Write, Same Bank ) " + +#define RSC_DDR4_WRWR_SC_COMM_CODE_EN \ + " tWRWR ( Write to Write, Different Bank ) " + +#define RSC_DDR4_WRWR_SD_COMM_CODE_EN \ + " tWRWR ( Write to Write, Different Rank ) " + +#define RSC_DDR4_WRWR_DD_COMM_CODE_EN \ + " tWRWR ( Write to Write, Different DIMM ) " + +#define RSC_DDR4_RRD_S_COMM_CODE_EN \ + " tRRD_S ( Activate to Activate, Different Bank Group ) " + +#define RSC_DDR4_RRD_L_COMM_CODE_EN \ + " tRRD_L ( Activate to Activate, Same Bank Group ) " + +#define RSC_DDR4_CPDED_COMM_CODE_EN " tCPDED ( Command Pass Disable Delay ) " +#define RSC_DDR4_GEAR_COMM_CODE_EN " GEAR ( Clock Gear Mode ) " + +#define RSC_DDR4_ZEN_RC_COMM_CODE_EN " tRC ( Activate to Activate ) " + +#define RSC_DDR4_ZEN_WTR_S_COMM_CODE_EN \ + " tWTR_S ( Write to Read, Different Bank Group ) " + +#define RSC_DDR4_ZEN_WTR_L_COMM_CODE_EN \ + " tWTR_L ( Write to Read, Same Bank Group ) " + +#define RSC_DDR4_ZEN_RDRD_SCL_COMM_CODE_EN \ + " tRDRD[SCL] ( Read to Read, Same Bank Group ) " + +#define RSC_DDR4_ZEN_WRWR_SCL_COMM_CODE_EN \ + " tWRWR[SCL] ( Write to Write, Same Bank Group ) " + +#define RSC_DDR4_ZEN_RTP_COMM_CODE_EN " tRTP ( Read To Precharge ) " +#define RSC_DDR4_ZEN_RDWR_COMM_CODE_EN " tRDWR ( Read Write Command Spacing ) " +#define RSC_DDR4_ZEN_WRRD_COMM_CODE_EN " tWRRD ( Write Read Command Spacing ) " + +#define RSC_DDR4_ZEN_WRWR_SC_COMM_CODE_EN \ + " tWRWR[SC] ( tWRWR, Different Bank Group ) " + +#define RSC_DDR4_ZEN_WRWR_SD_COMM_CODE_EN \ + " tWRWR[SD] ( tWRWR, Different Rank) " + +#define RSC_DDR4_ZEN_WRWR_DD_COMM_CODE_EN \ + " tWRWR[DD] ( tWRWR, Different DIMM ) " + +#define RSC_DDR4_ZEN_RDRD_SC_COMM_CODE_EN \ + " tRDRD[SC] ( tRDRD, Different Bank Group ) " + +#define RSC_DDR4_ZEN_RDRD_SD_COMM_CODE_EN \ + " tRDRD[SD] ( tRDRD, Different Rank ) " + +#define RSC_DDR4_ZEN_RDRD_DD_COMM_CODE_EN \ + " tRDRD[DD] ( tRDRD, Different DIMM ) " + +#define RSC_DDR4_ZEN_RTR_DLR_COMM_CODE_EN \ + " tRTR[DLR] ( tRTR, Different Logical Rank ) " + +#define RSC_DDR4_ZEN_WTW_DLR_COMM_CODE_EN \ + " tWTW[DLR] ( tWTW, Different Logical Rank ) " + +#define RSC_DDR4_ZEN_WTR_DLR_COMM_CODE_EN \ + " tWTR[DLR] ( tWTR, Different Logical Rank ) " + +#define RSC_DDR4_ZEN_RRD_DLR_COMM_CODE_EN \ + " tRRD[DLR] ( tRRD, Different Logical Rank ) " + +#define RSC_DDR4_ZEN_RFC1_COMM_CODE_EN " tRFC1 ( Refresh to Refresh, 1X mode ) " +#define RSC_DDR4_ZEN_RFC2_COMM_CODE_EN " tRFC2 ( Refresh to Refresh, 2X mode ) " +#define RSC_DDR4_ZEN_RFC4_COMM_CODE_EN " tRFC4 ( Refresh to Refresh, 4X mode ) " +#define RSC_DDR4_ZEN_RCPB_COMM_CODE_EN " tRCPB ( Row Cycle Time, Per-Bank ) " + +#define RSC_DDR4_ZEN_RPPB_COMM_CODE_EN \ + " tRPPB ( Row Precharge Time, Per-Bank ) " + +#define RSC_DDR4_ZEN_BGS_COMM_CODE_EN " BGS ( BankGroupSwap ) " + +#define RSC_DDR4_ZEN_BGS_ALT_COMM_CODE_EN \ + " BGS Alt ( BankGroupSwap Alternate ) " + +#define RSC_DDR4_ZEN_BAN_COMM_CODE_EN " tBAN ( Timing Ban, RTR | WTW ) " +#define RSC_DDR4_ZEN_RCPAGE_COMM_CODE_EN " tRCPage ( Row Cycle Page Time ) " +#define RSC_DDR4_ZEN_GDM_COMM_CODE_EN " GDM ( Gear Down Mode ) " + +#define RSC_DDR4_ZEN_MRD_COMM_CODE_EN \ + " tMRD ( MRS to another MRS command, Same CS ) " + +#define RSC_DDR4_ZEN_MOD_COMM_CODE_EN \ + " tMOD ( MRS to another non-MRS command, Same CS ) " + +#define RSC_DDR4_ZEN_MRD_PDA_COMM_CODE_EN \ + " tMRD_PDA ( MRS PDA to another MRS command, Same CS ) " + +#define RSC_DDR4_ZEN_MOD_PDA_COMM_CODE_EN \ + " tMOD_PDA ( MRS PDA to another non-MRS command, Same CS ) " + +#define RSC_DDR4_ZEN_WRMPR_COMM_CODE_EN \ + " tWRMPR ( Number of clocks greater than tMOD ) " + +#define RSC_DDR4_ZEN_STAG_COMM_CODE_EN \ + " tSTAG ( Min timing between REF commands, Different CS ) " + +#define RSC_DDR4_ZEN_PDM_COMM_CODE_EN " PDM ( DRAM Power Down Mode ) " \ + " [ Aggressive:Full|Partial:Enable ] " + +#define RSC_DDR4_ZEN_RDDATA_COMM_CODE_EN \ + " tRDDATA ( Read command to dfi_rddata_en delay ) " + +#define RSC_DDR4_ZEN_PHYWRD_COMM_CODE_EN \ + " tPHYWRD ( dfi_wrdata_en to dfi_wrdata delay ) " + +#define RSC_DDR4_ZEN_PHYWRL_COMM_CODE_EN \ + " tPHYWRL ( Write command to dfi_wrdata_en delay ) " + +#define RSC_DDR4_ZEN_PHYRDL_COMM_CODE_EN \ + " tPHYRDL ( dfi_rddata_en to dfi_rddata_vld delay ) " + +#define RSC_DDR5_ZEN_RFC_SB_COMM_CODE_EN \ + " tRFCsb ( Refresh Recovery, Same Bank ) " + +#define RSC_TASKS_SORTBY_STATE_CODE_EN " State " +#define RSC_TASKS_SORTBY_RTIME_CODE_EN " RunTime " +#define RSC_TASKS_SORTBY_UTIME_CODE_EN " UserTime " +#define RSC_TASKS_SORTBY_STIME_CODE_EN " SysTime " +#define RSC_TASKS_SORTBY_PID_CODE_EN " PID " +#define RSC_TASKS_SORTBY_COMM_CODE_EN " Command " + +#define RSC_MENU_ITEM_MENU_CODE_EN " [F2] Menu " +#define RSC_MENU_ITEM_VIEW_CODE_EN " [F3] View " +#define RSC_MENU_ITEM_WINDOW_CODE_EN " [F4] Window " +#define RSC_MENU_ITEM_SPACER_CODE_EN "\x020\x020\x020" +#define RSC_MENU_ITEM_DATE_TIME_CODE_EN "%x %k:%M:%S" +#define RSC_MENU_ITEM_FULL_TIME_CODE_EN "%k:%M:%S" +#define RSC_MENU_ITEM_TINY_TIME_CODE_EN "%k:%M" +#define RSC_MENU_ITEM_SETTINGS_CODE_EN " Settings [s] " +#define RSC_MENU_ITEM_SMBIOS_CODE_EN " SMBIOS data [B] " +#define RSC_MENU_ITEM_KERNEL_CODE_EN " Kernel data [k] " +#define RSC_MENU_ITEM_HOTPLUG_CODE_EN " HotPlug CPU [#] " +#define RSC_MENU_ITEM_TOOLS_CODE_EN " Tools [O] " +#define RSC_MENU_ITEM_THEME_CODE_EN " Theme [E] " +#define RSC_MENU_ITEM_ABOUT_CODE_EN " About [a] " +#define RSC_MENU_ITEM_HELP_CODE_EN " Help [h] " +#define RSC_MENU_ITEM_KEYS_CODE_EN " Shortcuts [F1] " +#define RSC_MENU_ITEM_LANG_CODE_EN " Languages [L] " +#define RSC_MENU_ITEM_QUIT_CODE_EN " Quit [Ctrl]+[x] " +#define RSC_MENU_ITEM_DASHBOARD_CODE_EN " Dashboard [d] " +#define RSC_MENU_ITEM_FREQUENCY_CODE_EN " Frequency [f] " +#define RSC_MENU_ITEM_INST_CYCLES_CODE_EN " Inst cycles [i] " +#define RSC_MENU_ITEM_CORE_CYCLES_CODE_EN " Core cycles [c] " +#define RSC_MENU_ITEM_IDLE_STATES_CODE_EN " Idle C-States [l] " +#define RSC_MENU_ITEM_PKG_CYCLES_CODE_EN " Package cycles [g] " +#define RSC_MENU_ITEM_TASKS_MON_CODE_EN " Tasks Monitoring [x] " +#define RSC_MENU_ITEM_SYS_INTER_CODE_EN " System Interrupts [q] " +#define RSC_MENU_ITEM_SENSORS_CODE_EN " Sensors [C] " +#define RSC_MENU_ITEM_VOLTAGE_CODE_EN " Voltage [V] " +#define RSC_MENU_ITEM_POWER_CODE_EN " Power [W] " +#define RSC_MENU_ITEM_SLICE_CTRS_CODE_EN " Slice counters [T] " +#define RSC_MENU_ITEM_CUSTOM_CODE_EN " Custom view [y] " +#define RSC_MENU_ITEM_PROCESSOR_CODE_EN " Processor [p] " +#define RSC_MENU_ITEM_TOPOLOGY_CODE_EN " Topology [m] " +#define RSC_MENU_ITEM_FEATURES_CODE_EN " Features [e] " +#define RSC_MENU_ITEM_ISA_EXT_CODE_EN " ISA Extensions [I] " +#define RSC_MENU_ITEM_TECH_CODE_EN " Technologies [t] " +#define RSC_MENU_ITEM_PERF_MON_CODE_EN " Perf. Monitoring [o] " +#define RSC_MENU_ITEM_PERF_CAPS_CODE_EN " Perf. Capabilities [z] " +#define RSC_MENU_ITEM_POW_THERM_CODE_EN " Power & Thermal [w] " +#define RSC_MENU_ITEM_SYS_REGS_CODE_EN " System Registers [R] " +#define RSC_MENU_ITEM_MEM_CTRL_CODE_EN " Memory Controller [M] " +#define RSC_MENU_ITEM_EVENTS_CODE_EN " Processor Events [H] " + +#define RSC_SETTINGS_TITLE_CODE_EN " Settings " +#define RSC_SETTINGS_DAEMON_CODE_EN " Daemon gate " +#define RSC_SETTINGS_INTERVAL_CODE_EN " Interval(ms) < > " +#define RSC_SETTINGS_SYS_TICK_CODE_EN " Sys. Tick(ms) " +#define RSC_SETTINGS_POLL_WAIT_CODE_EN " Poll Wait(ms) " +#define RSC_SETTINGS_RING_WAIT_CODE_EN " Ring Wait(ms) " +#define RSC_SETTINGS_CHILD_WAIT_CODE_EN " Child Wait(ms) " +#define RSC_SETTINGS_SLICE_WAIT_CODE_EN " Slice Wait(ms) " +#define RSC_SETTINGS_RECORDER_CODE_EN " Duration(sec) < > " +#define RSC_SETTINGS_AUTO_CLOCK_CODE_EN " Auto Clock < > " +#define RSC_SETTINGS_EXPERIMENTAL_CODE_EN " Experimental < > " +#define RSC_SETTINGS_CPU_HOTPLUG_CODE_EN " CPU Hot-Plug [ ] " +#define RSC_SETTINGS_PCI_ENABLED_CODE_EN " PCI enablement [ ] " +#define RSC_SETTINGS_NMI_REGISTERED_CODE_EN " NMI registered < > " +#define RSC_SETTINGS_CPUIDLE_REGISTERED_CODE_EN \ + " CPU-IDLE driver < > " + +#define RSC_SETTINGS_CPUFREQ_REGISTERED_CODE_EN \ + " CPU-FREQ driver < > " + +#define RSC_SETTINGS_GOVERNOR_REGISTERED_CODE_EN \ + " Governor driver < > " + +#define RSC_SETTINGS_CS_REGISTERED_CODE_EN " Clock Source < > " +#define RSC_SETTINGS_THERMAL_SCOPE_CODE_EN " Thermal scope < > " +#define RSC_SETTINGS_VOLTAGE_SCOPE_CODE_EN " Voltage scope < > " +#define RSC_SETTINGS_POWER_SCOPE_CODE_EN " Power scope < > " +#define RSC_SETTINGS_IDLE_ROUTE_CODE_EN " CPU-IDLE route " + +#define RSC_HELP_TITLE_CODE_EN " Help " +#define RSC_HELP_KEY_ESCAPE_CODE_EN " [Escape] " +#define RSC_HELP_KEY_SHIFT_TAB_CODE_EN " [Shift]+[Tab] " +#define RSC_HELP_KEY_TAB_CODE_EN " [Tab] " +#define RSC_HELP_KEY_UP_CODE_EN " [Up] " +#define RSC_HELP_KEY_LEFT_RIGHT_CODE_EN " [Left] [Right]" +#define RSC_HELP_KEY_DOWN_CODE_EN " [Down] " +#define RSC_HELP_KEY_END_CODE_EN " [End] " +#define RSC_HELP_KEY_HOME_CODE_EN " [Home] " +#define RSC_HELP_KEY_ENTER_CODE_EN " [Enter] " +#define RSC_HELP_KEY_PAGE_UP_CODE_EN " [Page-Up] " +#define RSC_HELP_KEY_PAGE_DOWN_CODE_EN " [Page-Dw] " +#define RSC_HELP_KEY_MINUS_CODE_EN " [Minus] " +#define RSC_HELP_KEY_PLUS_CODE_EN " [Plus] " +#define RSC_HELP_KEY_MENU_CODE_EN " [F2] " +#define RSC_HELP_MENU_CODE_EN " Menu " +#define RSC_HELP_CLOSE_WINDOW_CODE_EN " Close window " +#define RSC_HELP_PREV_WINDOW_CODE_EN " Previous window " +#define RSC_HELP_NEXT_WINDOW_CODE_EN " Next window " +#define RSC_HELP_KEY_SHIFT_GR1_CODE_EN " [s] " +#define RSC_HELP_KEY_SHIFT_GR2_CODE_EN " [a|q] [x] [d] +" +#define RSC_HELP_MOVE_WINDOW_CODE_EN " [Shift] Move Win " +#define RSC_HELP_KEY_ALT_GR3_CODE_EN " +" +#define RSC_HELP_SIZE_WINDOW_CODE_EN " [Alt] Size Win " +#define RSC_HELP_MOVE_SELECT_CODE_EN " Move selection " +#define RSC_HELP_LAST_CELL_CODE_EN " Last cell " +#define RSC_HELP_FIRST_CELL_CODE_EN " First cell " +#define RSC_HELP_TRIGGER_SELECT_CODE_EN "Trigger selection " +#define RSC_HELP_PREV_PAGE_CODE_EN " Previous page " +#define RSC_HELP_NEXT_PAGE_CODE_EN " Next page " +#define RSC_HELP_SCROLL_DOWN_CODE_EN " Scroll CPU down " +#define RSC_HELP_SCROLL_UP_CODE_EN " Scroll CPU up " + +#define RSC_ADV_HELP_TITLE_CODE_EN " Shortcuts " +#define RSC_ADV_HELP_SECT_FREQ_CODE_EN " Frequency view: " +#define RSC_ADV_HELP_ITEM_AVG_CODE_EN " % Averages | Package C-States" +#define RSC_ADV_HELP_SECT_TASK_CODE_EN " Task Monitoring view: " +#define RSC_ADV_HELP_ITEM_ORDER_CODE_EN " b Sorting tasks order " +#define RSC_ADV_HELP_ITEM_RST_CODE_EN " N Reset task tracking " +#define RSC_ADV_HELP_ITEM_SEL_CODE_EN " n Select task tracking " +#define RSC_ADV_HELP_ITEM_REV_CODE_EN " r Reverse tasks sorting " +#define RSC_ADV_HELP_ITEM_HIDE_CODE_EN " v Show | Hide Kernel values " +#define RSC_ADV_HELP_SECT_ANY_CODE_EN " Any view: " +#define RSC_ADV_HELP_ITEM_POWER_CODE_EN " $ Energy in Joule or Watt " +#define RSC_ADV_HELP_ITEM_TOP_CODE_EN " . Top frequency or Usage " +#define RSC_ADV_HELP_ITEM_UPD_CODE_EN " * Refresh CoreFreq Machine " +#define RSC_ADV_HELP_ITEM_START_CODE_EN " { Start CoreFreq Machine " +#define RSC_ADV_HELP_ITEM_STOP_CODE_EN " } Stop CoreFreq Machine " +#define RSC_ADV_HELP_ITEM_TOOLS_CODE_EN " F10 Stop tools processing " +#define RSC_ADV_HELP_ITEM_GO_UP_CODE_EN " Up PgUp Scroll " +#define RSC_ADV_HELP_ITEM_GO_DW_CODE_EN " Down PgDw CPU " +#define RSC_ADV_HELP_ITEM_TERMINAL_CODE_EN \ + " Terminal: " + +#define RSC_ADV_HELP_ITEM_PRT_SCR_CODE_EN \ + " [Ctrl]+[p] Screenshot " + +#define RSC_ADV_HELP_ITEM_REC_SCR_CODE_EN \ + " [Alt]+[p] Screencast " + +#define RSC_ADV_HELP_ITEM_FAHR_CELS_CODE_EN \ + " F Fahrenheit or Celsius " + +#define RSC_ADV_HELP_ITEM_SYSGATE_CODE_EN \ + " G Toggle SysGate state " + +#define RSC_ADV_HELP_ITEM_PROC_EVENT_CODE_EN \ + " H Manage Processor Events " + +#define RSC_ADV_HELP_ITEM_SECRET_CODE_EN \ + " Y Show | Hide Secret Data " + +#define RSC_TURBO_CLOCK_TITLE_CODE_EN " Turbo Clock %1dC " +#define RSC_RATIO_CLOCK_TITLE_CODE_EN " %s Clock Ratio " +#define RSC_UNCORE_CLOCK_TITLE_CODE_EN " %s Clock Uncore " + +#define RSC_SELECT_CPU_TITLE_CODE_EN " CPU Pkg Core Thread Scheduled " +#define RSC_SELECT_FREQ_TITLE_CODE_EN " CPU Pkg Core Thread " \ + " Frequency Ratio " + +#define RSC_BOX_DISABLE_COND0_CODE_EN " Disable " +#define RSC_BOX_DISABLE_COND1_CODE_EN " < Disable > " +#define RSC_BOX_ENABLE_COND0_CODE_EN " Enable " +#define RSC_BOX_ENABLE_COND1_CODE_EN " < Enable > " + +#define RSC_BOX_INTERVAL_TITLE_CODE_EN "Interval" +#define RSC_BOX_AUTO_CLOCK_TITLE_CODE_EN " Auto Clock " +#define RSC_BOX_MODE_TITLE_CODE_EN " Experimental " + +#define RSC_BOX_MODE_DESC_CODE_EN " CoreFreq Operation Mode " +#define RSC_BOX_HWP_DESC_CODE_EN " Hardware-Controlled Performance " +#define RSC_BOX_FMW_DESC_CODE_EN " Firmware Controlled Performance " + +#define RSC_BOX_NOMINAL_MODE_COND0_CODE_EN \ + " Nominal operating mode " + +#define RSC_BOX_NOMINAL_MODE_COND1_CODE_EN \ + " < Nominal operating mode > " + +#define RSC_BOX_EXPERIMENT_MODE_COND0_CODE_EN \ + " Experimental operating mode " + +#define RSC_BOX_EXPERIMENT_MODE_COND1_CODE_EN \ + " < Experimental operating mode > " + +#define RSC_BOX_INTERRUPT_TITLE_CODE_EN " NMI Interrupts " +#define RSC_BOX_CPU_IDLE_TITLE_CODE_EN " CPU-IDLE driver " +#define RSC_BOX_CPU_FREQ_TITLE_CODE_EN " CPU-FREQ driver " +#define RSC_BOX_GOVERNOR_TITLE_CODE_EN " Governor driver " +#define RSC_BOX_CLOCK_SOURCE_TITLE_CODE_EN " Clock Source " + +#define RSC_BOX_OPS_REGISTER_COND0_CODE_EN \ + " Register " + +#define RSC_BOX_OPS_REGISTER_COND1_CODE_EN \ + " < Register > " + +#define RSC_BOX_OPS_UNREGISTER_COND0_CODE_EN \ + " Unregister " + +#define RSC_BOX_OPS_UNREGISTER_COND1_CODE_EN \ + " < Unregister > " + +#define RSC_BOX_EVENT_TITLE_CODE_EN \ + " DTS ------------ Core ----------- GFX ------------ Ring " + +#define RSC_BOX_EVENT_SPACE_CODE_EN " " +#define RSC_BOX_EVENT_THERMAL_SENSOR_CODE_EN " Thermal Sensor " +#define RSC_BOX_EVENT_PROCHOT_STS_CODE_EN " PROCHOT " +#define RSC_BOX_EVENT_CRITICAL_TEMP_CODE_EN " Critical Temp. " +#define RSC_BOX_EVENT_THOLD1_STS_CODE_EN " Th. Threshold1 " +#define RSC_BOX_EVENT_THOLD2_STS_CODE_EN " Th. Threshold2 " +#define RSC_BOX_EVENT_POWER_LIMIT_CODE_EN " Power Limit. " +#define RSC_BOX_EVENT_CURRENT_LIMIT_CODE_EN " Current Limit. " +#define RSC_BOX_EVENT_CROSS_DOM_LIMIT_CODE_EN " XDomain Limit. " +#define RSC_BOX_EVENT_RESIDENCY_CODE_EN " Residency " +#define RSC_BOX_EVENT_AVG_THERMAL_CODE_EN " Avg Thermal " +#define RSC_BOX_EVENT_VR_THERMAL_CODE_EN " VR Thermal " +#define RSC_BOX_EVENT_VR_TDC_CODE_EN " VR TDC " +#define RSC_BOX_EVENT_POWER_PL1_CODE_EN " Package PL1 " +#define RSC_BOX_EVENT_POWER_PL2_CODE_EN " Package PL2 " +#define RSC_BOX_EVENT_ELECTRICAL_CODE_EN " Electrical EDP " +#define RSC_BOX_EVENT_INEFFICIENCY_CODE_EN " Inefficiency " +#define RSC_BOX_EVENT_MAX_TURBO_CODE_EN " Max Turbo " +#define RSC_BOX_EVENT_TURBO_ATTEN_CODE_EN " Turbo Atten. " +#define RSC_BOX_EVENT_THERMAL_TVB_CODE_EN " Thermal TVB " +#define RSC_BOX_EVENT_ALL_OF_THEM_CODE_EN "< Clear All >" + +#define RSC_BOX_POWER_POLICY_TITLE_CODE_EN " Energy Policy " +#define RSC_BOX_POWER_POLICY_LOW_CODE_EN " 0 LOW " +#define RSC_BOX_POWER_POLICY_HIGH_CODE_EN " 15 HIGH " + +#define RSC_BOX_HWP_POLICY_MIN_CODE_EN " Minimum:0 " +#define RSC_BOX_HWP_POLICY_020_CODE_EN " 32 " +#define RSC_BOX_HWP_POLICY_040_CODE_EN " 64 " +#define RSC_BOX_HWP_POLICY_060_CODE_EN " 96 " +#define RSC_BOX_HWP_POLICY_MED_CODE_EN " Medium:128 " +#define RSC_BOX_HWP_POLICY_0A0_CODE_EN " 160 " +#define RSC_BOX_HWP_POLICY_PWR_CODE_EN " Power:192 " +#define RSC_BOX_HWP_POLICY_0E0_CODE_EN " 224 " +#define RSC_BOX_HWP_POLICY_MAX_CODE_EN " Maximum:255 " + +#define RSC_BOX_TOOLS_TITLE_CODE_EN " Tools " +#define RSC_BOX_TOOLS_STOP_BURN_CODE_EN " STOP " +#define RSC_BOX_TOOLS_ATOMIC_BURN_CODE_EN " Atomic Burn " +#define RSC_BOX_TOOLS_CRC32_BURN_CODE_EN " CRC32 Compute " +#define RSC_BOX_TOOLS_CONIC_BURN_CODE_EN " < Conic Compute > " +#define RSC_BOX_TOOLS_RANDOM_CPU_CODE_EN " Turbo Random CPU " +#define RSC_BOX_TOOLS_ROUND_ROBIN_CPU_CODE_EN " Turbo Round Robin " +#define RSC_BOX_TOOLS_USER_CPU_CODE_EN " Turbo < Select CPU > " +#define RSC_BOX_TOOLS_MONTE_CARLO_CODE_EN " Estimate PI / Monte Carlo " + +#define RSC_BOX_CONIC_TITLE_CODE_EN " Conic variations " +#define RSC_BOX_CONIC_ITEM_1_CODE_EN " Ellipsoid " +#define RSC_BOX_CONIC_ITEM_2_CODE_EN " Hyperboloid of one sheet " +#define RSC_BOX_CONIC_ITEM_3_CODE_EN " Hyperboloid of two sheets " +#define RSC_BOX_CONIC_ITEM_4_CODE_EN " Elliptical cylinder " +#define RSC_BOX_CONIC_ITEM_5_CODE_EN " Hyperbolic cylinder " +#define RSC_BOX_CONIC_ITEM_6_CODE_EN " Two parallel planes " + +#define RSC_BOX_LANG_TITLE_CODE_EN " Languages " +#define RSC_BOX_LANG_ENGLISH_CODE_EN " English " +#define RSC_BOX_LANG_FRENCH_CODE_EN " French " +#define RSC_BOX_LANG_BLANK_CODE " " + +#define RSC_BOX_THEME_TITLE_CODE_EN " Themes " +#define RSC_BOX_THEME_BLANK_CODE \ +" " + +#define RSC_BOX_SCOPE_THERMAL_TITLE_CODE_EN " Thermal scope " +#define RSC_BOX_SCOPE_VOLTAGE_TITLE_CODE_EN " Voltage scope " +#define RSC_BOX_SCOPE_POWER_TITLE_CODE_EN " Power scope " +#define RSC_BOX_SCOPE_NONE_CODE_EN " None " +#define RSC_BOX_SCOPE_THREAD_CODE_EN " Thread " +#define RSC_BOX_SCOPE_CORE_CODE_EN " Core " +#define RSC_BOX_SCOPE_PACKAGE_CODE_EN " Package " + +#define RSC_BOX_CFG_TDP_TITLE_CODE_EN " Config TDP " +#define RSC_BOX_CFG_TDP_DESC_CODE_EN " System BIOS limit " +#define RSC_BOX_CFG_TDP_LVL0_CODE_EN " Level 0 " +#define RSC_BOX_CFG_TDP_LVL1_CODE_EN " Level 1 " +#define RSC_BOX_CFG_TDP_LVL2_CODE_EN " Level 2 " + +#define RSC_BOX_TDP_PKG_TITLE_CODE_EN " TDP Package " +#define RSC_BOX_TDP_CORES_TITLE_CODE_EN " TDP Core " +#define RSC_BOX_TDP_UNCORE_TITLE_CODE_EN " TDP Uncore " +#define RSC_BOX_TDP_RAM_TITLE_CODE_EN " TDP DRAM " +#define RSC_BOX_TDP_PLATFORM_TITLE_CODE_EN " TDP Platform " +#define RSC_BOX_PL1_DESC_CODE_EN " PL1 Power Limit " +#define RSC_BOX_PL2_DESC_CODE_EN " PL2 Power Limit " + +#define RSC_BOX_TDC_TITLE_CODE_EN " TDC Current " +#define RSC_BOX_TDC_DESC_CODE_EN " TDC Current Limit " + +#define RSC_ERROR_CMD_SYNTAX_CODE_EN \ + "CoreFreq." \ + " Copyright (C) 2015-2024 CYRIL COURTIAT\n\n" \ + "Usage:\t%s [-Option ] [-Command ]\n"\ + "\n Interface options\n" \ + "\t-Oa\tAbsolute frequency\n" \ + "\t-Op\tShow Package C-States\n" \ + "\t-Ok\tMemory unit in kilobyte\n" \ + "\t-Om\tMemory unit in megabyte\n" \ + "\t-Og\tMemory unit in gigabyte\n" \ + "\t-OW\tToggle Energy units\n" \ + "\t-OF\tTemperature in Fahrenheit\n" \ + "\t-OJ #\tSMBIOS string index number\n" \ + "\t-OE #\tColor theme index number\n" \ + "\t-OY\tShow Secret Data\n" \ + "\n Command options\n" \ + "\t-t \tShow Top (default) with optional iew:\n" \ + "\t\t{\tfrequency, instructions, core, idle, package, tasks,\n"\ + "\t\t\tinterrupts, sensors, voltage, power, slices, custom }\n"\ + "\t-d\tShow Dashboard\n" \ + "\t-C <#>\tMonitor Sensors\n" \ + "\t-V <#>\tMonitor Voltage\n" \ + "\t-W <#>\tMonitor Power\n" \ + "\t-g <#>\tMonitor Package\n" \ + "\t-c <#>\tMonitor Counters\n" \ + "\t-i <#>\tMonitor Instructions\n" \ + "\t-s\tPrint System Information\n" \ + "\t-j\tPrint System Information (json-encoded)\n" \ + "\t-z\tPrint Performance Capabilities\n" \ + "\t-M\tPrint Memory Controller\n" \ + "\t-R\tPrint System Registers\n" \ + "\t-m\tPrint Topology\n" \ + "\t-B\tPrint SMBIOS\n" \ + "\t-k\tPrint Kernel\n" \ + "\t-n\tNew line\n" \ + "\t-h\tPrint out this message\n" \ + "\t-v\tPrint the version number\n" \ + "\nExit status:\n" \ + "\t%u\tSUCCESS\t\tSuccessful execution\n" \ + "\t%u\tCMD_SYNTAX\tCommand syntax error\n" \ + "\t%u\tSHM_FILE\tShared memory file error\n" \ + "\t%u\tSHM_MMAP\tShared memory mapping error\n" \ + "\t%u\tPERM_ERR\tExecution not permitted\n" \ + "\t%u\tMEM_ERR\t\tMemory operation error\n" \ + "\t%u\tEXEC_ERR\tGeneral execution error\n" \ + "\t%u\tSYS_CALL\tSystem call error\n" \ + "\nReport bugs to labs[at]cyring.fr\n" + +#define RSC_ERROR_SHARED_MEM_CODE_EN \ + "Daemon connection error code %d\n%s: '%s' @ line %d\n" + +#define RSC_ERROR_SYS_CALL_CODE_EN "System error code %d\n%s @ line %d\n" +#define RSC_ERROR_UNIMPLEMENTED_CODE_EN "Feature is not implemented" +#define RSC_ERROR_EXPERIMENTAL_CODE_EN "Experimental mode is required" + +#define RSC_ERROR_TURBO_PREREQ_CODE_EN "Turbo Boost | Core Performance Boost"\ + " must be disabled" + +#define RSC_ERROR_UNCORE_PREREQ_CODE_EN "Invalid Uncore prerequisites" + +#define RSC_ERROR_PSTATE_NOT_FOUND_CODE_EN \ + "This Frequency P-State was not found" + +#define RSC_ERROR_CLOCKSOURCE_CODE_EN "Incompatible clock source" + +#define RSC_BOX_IDLE_LIMIT_TITLE_CODE_EN " CPU-Idle Limit " + +#define RSC_BOX_RECORDER_TITLE_CODE_EN " Duration " + +#define RSC_SMBIOS_TITLE_CODE_EN " SMBIOS " + +#define RSC_MECH_CLRBHB_CODE_EN "Clear Branch History instruction" +#define RSC_MECH_SSBD_CODE_EN "Speculative Store Bypass Disable" +#define RSC_MECH_SSBS_CODE_EN "Speculative Store Bypass Safe" + +#define RSC_CREATE_SELECT_AUTO_TURBO_CODE_EN " %3s Processor " \ + " %s %c%4u %c " + +#define RSC_CREATE_SELECT_FREQ_TURBO_CODE_EN " %3s Processor " \ + "%7.2f MHz %c%4u %c " + +#define RSC_CREATE_SELECT_FREQ_TGT_CODE_EN " TGT Processor " +#define RSC_CREATE_SELECT_FREQ_HWP_TGT_CODE_EN " HWP-TGT Processor " +#define RSC_CREATE_SELECT_FREQ_HWP_MAX_CODE_EN " HWP-MAX Processor " +#define RSC_CREATE_SELECT_FREQ_HWP_MIN_CODE_EN " HWP-MIN Processor " +#define RSC_CREATE_SELECT_FREQ_MAX_CODE_EN " MAX Processor " +#define RSC_CREATE_SELECT_FREQ_MIN_CODE_EN " MIN Processor " + +#define RSC_CREATE_SELECT_FREQ_OFFLINE_CODE_EN " %03u " \ + " Off " + +#define RSC_POPUP_DRIVER_TITLE_CODE_EN " Driver Message " + +#define RSC_EXIT_TITLE_CODE_EN " Exit " +#define RSC_EXIT_HEADER_CODE_EN " The following services are still running " +#define RSC_EXIT_CONFIRM_CODE_EN " < Force-Quit > " +#define RSC_EXIT_FOOTER_CODE_EN " [ESC] to cancel " + +#define RSC_CREATE_SETTINGS_COND_CODE_EN \ + " " + +#define RSC_CREATE_SETTINGS_COND0_CODE_EN RSC_CREATE_SETTINGS_COND_CODE_EN +#define RSC_CREATE_SETTINGS_COND1_CODE_EN RSC_CREATE_SETTINGS_COND_CODE_EN + +#define RSC_HELP_BLANK_CODE " " + +#define RSC_CREATE_ADV_HELP_BLANK_CODE_EN \ + " " + +#define RSC_CREATE_ADV_HELP_COND0_CODE_EN RSC_CREATE_ADV_HELP_BLANK_CODE_EN +#define RSC_CREATE_ADV_HELP_COND1_CODE_EN RSC_CREATE_ADV_HELP_BLANK_CODE_EN + +#define RSC_BOX_BLANK_DESC_CODE " " + +#define RSC_BOX_INTERVAL_STEP1_CODE " 100 " +#define RSC_BOX_INTERVAL_STEP2_CODE " 150 " +#define RSC_BOX_INTERVAL_STEP3_CODE " 250 " +#define RSC_BOX_INTERVAL_STEP4_CODE " 500 " +#define RSC_BOX_INTERVAL_STEP5_CODE " 750 " +#define RSC_BOX_INTERVAL_STEP6_CODE " 1000 " +#define RSC_BOX_INTERVAL_STEP7_CODE " 1500 " +#define RSC_BOX_INTERVAL_STEP8_CODE " 2000 " +#define RSC_BOX_INTERVAL_STEP9_CODE " 2500 " +#define RSC_BOX_INTERVAL_STEP10_CODE " 3000 " + +#define RSC_SETTINGS_ROUTE_TITLE_CODE_EN "Route" +#define RSC_SETTINGS_ROUTE_DFLT_CODE "DEFAULT" +#define RSC_SETTINGS_ROUTE_IO_CODE " I/O" +#define RSC_SETTINGS_ROUTE_HALT_CODE " HALT" +#define RSC_SETTINGS_ROUTE_MWAIT_CODE " MWAIT" + +#define RSC_BOX_CPPC_TITLE_CODE " CPPC " +#define RSC_BOX_HWP_TITLE_CODE " HWP " + +#define RSC_BOX_CFG_TDP_BLANK_CODE " " + +#define RSC_BOX_PWR_OFFSET_00_CODE " +50 watts " +#define RSC_BOX_PWR_OFFSET_01_CODE " +10 watts " +#define RSC_BOX_PWR_OFFSET_02_CODE " +5 watts " +#define RSC_BOX_PWR_OFFSET_03_CODE " +4 watts " +#define RSC_BOX_PWR_OFFSET_04_CODE " +3 watts " +#define RSC_BOX_PWR_OFFSET_05_CODE " +2 watts " +#define RSC_BOX_PWR_OFFSET_06_CODE " +1 watt " +#define RSC_BOX_PWR_OFFSET_07_CODE " -1 watt " +#define RSC_BOX_PWR_OFFSET_08_CODE " -2 watts " +#define RSC_BOX_PWR_OFFSET_09_CODE " -3 watts " +#define RSC_BOX_PWR_OFFSET_10_CODE " -4 watts " +#define RSC_BOX_PWR_OFFSET_11_CODE " -5 watts " +#define RSC_BOX_PWR_OFFSET_12_CODE " -10 watts " +#define RSC_BOX_PWR_OFFSET_13_CODE " -50 watts " + +#define RSC_BOX_CLAMPING_OFF_COND0_CODE " Clamping OFF " +#define RSC_BOX_CLAMPING_OFF_COND1_CODE " < Clamping OFF > " +#define RSC_BOX_CLAMPING_ON_COND0_CODE " Clamping ON " +#define RSC_BOX_CLAMPING_ON_COND1_CODE " < Clamping ON > " + +#define RSC_BOX_AMP_OFFSET_00_CODE " +50 amps " +#define RSC_BOX_AMP_OFFSET_01_CODE " +10 amps " +#define RSC_BOX_AMP_OFFSET_02_CODE " +5 amps " +#define RSC_BOX_AMP_OFFSET_03_CODE " +4 amps " +#define RSC_BOX_AMP_OFFSET_04_CODE " +3 amps " +#define RSC_BOX_AMP_OFFSET_05_CODE " +2 amps " +#define RSC_BOX_AMP_OFFSET_06_CODE " +1 amp " +#define RSC_BOX_AMP_OFFSET_07_CODE " -1 amp " +#define RSC_BOX_AMP_OFFSET_08_CODE " -2 amp " +#define RSC_BOX_AMP_OFFSET_09_CODE " -3 amp " +#define RSC_BOX_AMP_OFFSET_10_CODE " -4 amp " +#define RSC_BOX_AMP_OFFSET_11_CODE " -5 amps " +#define RSC_BOX_AMP_OFFSET_12_CODE " -10 amps " +#define RSC_BOX_AMP_OFFSET_13_CODE " -50 amps " + +#define RSC_BOX_IDLE_LIMIT_RESET_CODE " 0 RESET " + +#define RSC_CF0_CODE " ______ ______ " +#define RSC_CF1_CODE " / ____/___ ________ / ____/_______ ____ _ " +#define RSC_CF2_CODE " / / / __ \\/ ___/ _ \\/ /_ / ___/ _ \\/ __ `/ " +#define RSC_CF3_CODE " / /___/ /_/ / / / __/ __/ / / / __/ /_/ / " +#define RSC_CF4_CODE " \\____/\\____/_/ \\___/_/ /_/ \\___/\\__, / " +#define RSC_CF5_CODE " /_/ " + +#define RSC_FREQ_UNIT_MHZ_CODE "(MHz)" +#define RSC_PPIN_CODE "PPIN#" +#define RSC_OPP_CODE "OPP" +#define RSC_UNCORE_CODE "Uncore" +#define RSC_TURBO_CODE "Turbo" +#define RSC_CPPC_CODE "CPPC" +#define RSC_MAX_CODE "Max" +#define RSC_MIN_CODE "Min" +#define RSC_TGT_CODE "TGT" +#define RSC_TBH_CODE "TBH" +#define RSC_TBO_CODE "TBO" +#define RSC_ACT_CODE "Activ" +#define RSC_HYBRID_CODE "Hybrid" + +#define RSC_TOPOLOGY_FMT0_CODE "%03u:\x20\x20-\x20\x20\x20\x20-\x20" +#define RSC_TOPOLOGY_FMT1_CODE "\x20\x20\x20\x20\x20\x20\x20-\x20\x20-\x20\x20" +#define RSC_TOPOLOGY_OFF_0_CODE "\x20\x20\x20\x20-\x20\x20\x20\x20\x20\x20-\x20" +#define RSC_TOPOLOGY_OFF_1_CODE "\x20\x20-\x20\x20\x20-\x20\x20\x20\x20\x20-" +#define RSC_TOPOLOGY_OFF_2_CODE "\x20\x20-\x20\x20-\x20\x20\x20-\x20\x20-" +#define RSC_TOPOLOGY_OFF_3_CODE "\x20-\x20\x20\x20-\x20\x20\x20-\x20\x20-" +#define RSC_TOPOLOGY_HDR_PKG_CODE "CPU Pkg Main" +#define RSC_TOPOLOGY_HDR_SMT_CODE " Core/Thread" +#define RSC_TOPOLOGY_HDR_CACHE_CODE " Caches " +#define RSC_TOPOLOGY_HDR_WRBAK_CODE " (w)rite-Back" +#define RSC_TOPOLOGY_HDR_INCL_CODE " (i)nclusive " +#define RSC_TOPOLOGY_HDR_EMPTY_CODE " " +#define RSC_TOPOLOGY_SUB_ITEM1_CODE " # ID ID " +#define RSC_TOPOLOGY_SUB_ITEM3_CODE " L1-Inst Way " +#define RSC_TOPOLOGY_SUB_ITEM4_CODE " L1-Data Way " +#define RSC_TOPOLOGY_SUB_ITEM5_CODE " L2 Way " +#define RSC_TOPOLOGY_SUB_ITEM6_CODE " L3 Way " +#define RSC_TOPOLOGY_ALT_ITEM1_CODE " ID ID " +#define RSC_TOPOLOGY_ALT_ITEM2_CODE " CMP ID ID" +#define RSC_TOPOLOGY_ALT_ITEM3_CODE "CCD CCX ID/ID" +#define RSC_TOPOLOGY_ALT_ITEM4_CODE " Hybrid ID/ID" +#define RSC_TOPOLOGY_BSP_COMM_CODE " Boot Strap Processor " + +#define RSC_TECH_HYPERV_NONE_CODE " " +#define RSC_TECH_BARE_METAL_CODE "Bare-Metal" +#define RSC_TECH_HYPERV_XEN_CODE " Xen" +#define RSC_TECH_HYPERV_KVM_CODE " KVM" +#define RSC_TECH_HYPERV_VBOX_CODE "VirtualBox" +#define RSC_TECH_HYPERV_KBOX_CODE " KVM/VBox" +#define RSC_TECH_HYPERV_VMWARE_CODE " VMware" +#define RSC_TECH_HYPERV_HYPERV_CODE "MS Hyper-V" + +#define RSC_PERF_LABEL_VER_CODE "PM" +#define RSC_PERF_LABEL_HWCF_CODE "MPERF/APERF" +#define RSC_PERF_LABEL_CPPC_CODE "CPPC" +#define RSC_PERF_LABEL_PCT_CODE "_PCT" +#define RSC_PERF_LABEL_PSS_CODE "_PSS" +#define RSC_PERF_LABEL_PPC_CODE "_PPC" +#define RSC_PERF_LABEL_CPC_CODE "_CPC" +#define RSC_PERF_LABEL_CST_CODE "_CST" +#define RSC_PERF_LABEL_HWP_CODE "HWP" +#define RSC_PERF_LABEL_CST_BAR_CODE "BAR" +#define RSC_PERF_LABEL_MWAIT_IDX_CODE \ + "#0 #1 #2 #3 #4 #5 #6 #7" + +#define RSC_PERF_ENCODING_C0_CODE " C0" +#define RSC_PERF_ENCODING_C1_CODE " C1" +#define RSC_PERF_ENCODING_C2_CODE " C2" +#define RSC_PERF_ENCODING_C3_CODE " C3" +#define RSC_PERF_ENCODING_C4_CODE " C4" +#define RSC_PERF_ENCODING_C6_CODE " C6" +#define RSC_PERF_ENCODING_C6R_CODE "C6R" +#define RSC_PERF_ENCODING_C7_CODE " C7" +#define RSC_PERF_ENCODING_C7S_CODE "C7S" +#define RSC_PERF_ENCODING_C8_CODE " C8" +#define RSC_PERF_ENCODING_C9_CODE " C9" +#define RSC_PERF_ENCODING_C10_CODE "C10" +#define RSC_PERF_ENCODING_UNS_CODE "UNS" + +#define RSC_POWER_LABEL_CPPC_CODE "EPP" +#define RSC_POWER_LABEL_TJ_CODE "TjMax" +#define RSC_POWER_LABEL_DTS_CODE "DTS" +#define RSC_POWER_LABEL_PLN_CODE "PLN" +#define RSC_POWER_LABEL_PTM_CODE "PTM" +#define RSC_POWER_LABEL_TDP_CODE "TDP" +#define RSC_POWER_LABEL_MIN_CODE "Min" +#define RSC_POWER_LABEL_MAX_CODE "Max" +#define RSC_POWER_LABEL_PL1_CODE "PL1" +#define RSC_POWER_LABEL_PL2_CODE "PL2" +#define RSC_POWER_LABEL_TW1_CODE "TW1" +#define RSC_POWER_LABEL_TW2_CODE "TW2" +#define RSC_POWER_LABEL_EDC_CODE "EDC" +#define RSC_POWER_LABEL_TDC_CODE "TDC" +#define RSC_POWER_LABEL_PKG_CODE "Package" +#define RSC_POWER_LABEL_CORE_CODE "Core" +#define RSC_POWER_LABEL_UNCORE_CODE "Uncore" +#define RSC_POWER_LABEL_DRAM_CODE "DRAM" +#define RSC_POWER_LABEL_PLATFORM_CODE "Platform" + +#define RSC_MEM_CTRL_UNIT_MHZ_CODE " MHz " +#define RSC_MEM_CTRL_UNIT_MTS_CODE " MT/s" +#define RSC_MEM_CTRL_UNIT_MBS_CODE " MB/s" + +#define RSC_MEM_CTRL_MTY_CELL_CODE " " +#define RSC_MEM_CTRL_CHANNEL_CODE " Cha " + +#define RSC_DDR3_CL_CODE " CL" +#define RSC_DDR3_RCD_CODE " RCD" +#define RSC_DDR3_RP_CODE " RP" +#define RSC_DDR3_RAS_CODE " RAS" +#define RSC_DDR3_RRD_CODE " RRD" +#define RSC_DDR3_RFC_CODE " RFC" +#define RSC_DDR3_WR_CODE " WR" +#define RSC_DDR3_RTP_CODE " RTPr" +#define RSC_DDR3_WTP_CODE " WTPr" +#define RSC_DDR3_FAW_CODE " FAW" +#define RSC_DDR3_B2B_CODE " B2B" +#define RSC_DDR3_CWL_CODE " CWL" +#define RSC_DDR3_CMD_CODE " CMD " +#define RSC_DDR3_REFI_CODE " REFI" +#define RSC_DDR3_DDWRTRD_CODE " ddWR" +#define RSC_DDR3_DRWRTRD_CODE " drWR" +#define RSC_DDR3_SRWRTRD_CODE " srWR" +#define RSC_DDR3_DDRDTWR_CODE " ddRW" +#define RSC_DDR3_DRRDTWR_CODE " drRW" +#define RSC_DDR3_SRRDTWR_CODE " srRW" +#define RSC_DDR3_DDRDTRD_CODE " ddRR" +#define RSC_DDR3_DRRDTRD_CODE " drRR" +#define RSC_DDR3_SRRDTRD_CODE " srRR" +#define RSC_DDR3_DDWRTWR_CODE " ddWW" +#define RSC_DDR3_DRWRTWR_CODE " drWW" +#define RSC_DDR3_SRWRTWR_CODE " srWW" +#define RSC_DDR3_XS_CODE " XS " +#define RSC_DDR3_XP_CODE " XP " +#define RSC_DDR3_CKE_CODE " CKE " +#define RSC_DDR3_ECC_CODE " ECC" + +#define RSC_DDR4_CL_CODE " CL" +#define RSC_DDR4_RCD_R_CODE " RCDr" +#define RSC_DDR4_RCD_W_CODE " RCDw" +#define RSC_DDR4_RP_CODE " RP" +#define RSC_DDR4_RAS_CODE " RAS" +#define RSC_DDR4_RRD_CODE " RRD" +#define RSC_DDR4_RFC_CODE " RFC" +#define RSC_DDR4_WR_CODE " WR" +#define RSC_DDR4_RTP_CODE " RTPr" +#define RSC_DDR4_WTP_CODE " WTPr" +#define RSC_DDR4_FAW_CODE " FAW" +#define RSC_DDR4_GEAR_CODE " GEAR" +#define RSC_DDR4_CWL_CODE " CWL" +#define RSC_DDR4_CMD_CODE " CMD" +#define RSC_DDR4_REFI_CODE " REFI" +#define RSC_DDR4_RDRD_SCL_CODE " sgRR" +#define RSC_DDR4_RDRD_SC_CODE " dgRR" +#define RSC_DDR4_RDRD_SD_CODE " drRR" +#define RSC_DDR4_RDRD_DD_CODE " ddRR" +#define RSC_DDR4_RDWR_SCL_CODE " sgRW" +#define RSC_DDR4_RDWR_SC_CODE " dgRW" +#define RSC_DDR4_RDWR_SD_CODE " drRW" +#define RSC_DDR4_RDWR_DD_CODE " ddRW" +#define RSC_DDR4_WRRD_SCL_CODE " sgWR" +#define RSC_DDR4_WRRD_SC_CODE " dgWR" +#define RSC_DDR4_WRRD_SD_CODE " drWR" +#define RSC_DDR4_WRRD_DD_CODE " ddWR" +#define RSC_DDR4_WRWR_SCL_CODE " sgWW" +#define RSC_DDR4_WRWR_SC_CODE " dgWW" +#define RSC_DDR4_WRWR_SD_CODE " drWW" +#define RSC_DDR4_WRWR_DD_CODE " ddWW" +#define RSC_DDR4_RRD_S_CODE " RRDs" +#define RSC_DDR4_RRD_L_CODE " RRDl" +#define RSC_DDR4_CKE_CODE " CKE" +#define RSC_DDR4_CPDED_CODE "CPDED" +#define RSC_DDR4_ECC_CODE " ECC" + +#define RSC_DDR4_ZEN_CL_CODE " CL " +#define RSC_DDR4_ZEN_RP_CODE " RP " +#define RSC_DDR4_ZEN_RAS_CODE " RAS " +#define RSC_DDR4_ZEN_RC_CODE " RC " +#define RSC_DDR4_ZEN_FAW_CODE " FAW " +#define RSC_DDR4_ZEN_WTR_S_CODE " WTRs" +#define RSC_DDR4_ZEN_WTR_L_CODE " WTRl" +#define RSC_DDR4_ZEN_WR_CODE " WR " +#define RSC_DDR4_ZEN_RDRD_SCL_CODE " clRR" +#define RSC_DDR4_ZEN_WRWR_SCL_CODE " clWW" +#define RSC_DDR4_ZEN_CWL_CODE " CWL " +#define RSC_DDR4_ZEN_RTP_CODE " RTP " +#define RSC_DDR4_ZEN_RDWR_CODE "RdWr " +#define RSC_DDR4_ZEN_WRRD_CODE "WrRd " +#define RSC_DDR4_ZEN_WRWR_SC_CODE "scWW " +#define RSC_DDR4_ZEN_WRWR_SD_CODE "sdWW " +#define RSC_DDR4_ZEN_WRWR_DD_CODE "ddWW " +#define RSC_DDR4_ZEN_RDRD_SC_CODE "scRR " +#define RSC_DDR4_ZEN_RDRD_SD_CODE "sdRR " +#define RSC_DDR4_ZEN_RDRD_DD_CODE "ddRR " +#define RSC_DDR4_ZEN_RTR_DLR_CODE "drRR " +#define RSC_DDR4_ZEN_WTW_DLR_CODE "drWW " +#define RSC_DDR4_ZEN_WTR_DLR_CODE "drWR " +#define RSC_DDR4_ZEN_RRD_DLR_CODE "drRRD" +#define RSC_DDR4_ZEN_REFI_CODE " REFI" +#define RSC_DDR4_ZEN_RFC1_CODE " RFC1" +#define RSC_DDR4_ZEN_RFC2_CODE " RFC2" +#define RSC_DDR4_ZEN_RFC4_CODE " RFC4" +#define RSC_DDR4_ZEN_RCPB_CODE " RCPB" +#define RSC_DDR4_ZEN_RPPB_CODE " RPPB" +#define RSC_DDR4_ZEN_BGS_CODE " BGS" +#define RSC_DDR4_ZEN_BGS_ALT_CODE ":Alt " +#define RSC_DDR4_ZEN_BAN_CODE " Ban " +#define RSC_DDR4_ZEN_RCPAGE_CODE " Page" +#define RSC_DDR4_ZEN_GDM_CODE " GDM" +#define RSC_DDR4_ZEN_ECC_CODE " ECC" +#define RSC_DDR4_ZEN_MRD_CODE " MRD:" +#define RSC_DDR4_ZEN_MOD_CODE " MOD:" +#define RSC_DDR4_ZEN_MRD_PDA_CODE "PDA " +#define RSC_DDR4_ZEN_MOD_PDA_CODE "PDA " +#define RSC_DDR4_ZEN_WRMPR_CODE "WRMPR" +#define RSC_DDR4_ZEN_STAG_CODE " STAG" +#define RSC_DDR4_ZEN_PDM_CODE " PDM " +#define RSC_DDR4_ZEN_RDDATA_CODE "RDDAT" +#define RSC_DDR4_ZEN_PHYWRD_CODE "A WRD" +#define RSC_DDR4_ZEN_PHYWRL_CODE " WRL" +#define RSC_DDR4_ZEN_PHYRDL_CODE " RDL" +#define RSC_DDR5_ZEN_RFC_SB_CODE " RFCs" +#define RSC_DDR5_ZEN_RCPB_CODE "b RCP" +#define RSC_DDR5_ZEN_RPPB_CODE "B RPP" +#define RSC_DDR5_ZEN_BGS_CODE "B BGS" + +#define RSC_SYS_REGS_SPACE_CODE " " +#define RSC_SYS_REGS_NA_CODE " - " +#define RSC_SYS_REGS_HDR_CPU_CODE "CPU " + +#define RSC_SYS_REG_HDR_FLAGS_CODE \ + "FLAG\0 PM\0 N \0 Z \0 C \0 V \0 TCO\0 DIT\0" \ + " UAO\0 PAN\0 NMI\0 SSB\0S D \0 A \0 I \0 F \0 EL \0 M " + +#define RSC_SYS_REG_HDR11_SCTL_CODE \ + " \0 TID\0 SP\0 NMI\0 TPI\0 TC\0SO \0 PAN\0" \ + " ALS\0 AS0\0 ASR\0 T\0ME \0 T\0MT \0 T\0WE " + +#define RSC_SYS_REG_HDR12_SCTL_CODE \ + "SCTL\0 CP\0 INT\0 \0 DR2\0 EL1\0 EL0\0 \0" \ + " \0 \0 \0 EL1\0 EL0\0 EL1\0 EL0\0 DLY\0 En" + +#define RSC_SYS_REG_HDR21_SCTL_CODE \ + " \0SSBS\0 A\0TA \0 T\0CF \0 IT\0 B\0" \ + "TI \0 FPM\0 MC \0CMOW\0 IA \0 IB \0 L\0SM \0 DA " + +#define RSC_SYS_REG_HDR22_SCTL_CODE \ + "SCTL\0 \0 EL1\0 EL0\0 EL1\0 EL0\0 FSB\0 EL1\0" \ + " EL0\0 \0 MS \0 \0 \0 \0 AOE\0 DnT\0 " + +#define RSC_SYS_REG_HDR31_SCTL_CODE \ + "SCTL\0 UCI\0 EE \0E0E \0SPAN\0 EIS\0 IES\0 SCN\0" \ + " WXN\0 TWE\0 TWI\0 UCT\0 DZE\0 DB \0 I \0EOS \0RCTX" + +#define RSC_SYS_REG_HDR41_SCTL_CODE \ + "SCTL\0 UMA\0 SED\0 ITD\0 AA \0CP15\0 SA0\0 SA1\0 C \0 A \0 M " + +#define RSC_SYS_REG_HDR11_SCTL2_CODE \ + " \0 CP\0TM \0 CP\0TA \0 PA\0CM \0IDCP\0 EAS\0 AN \0 AD \0NMEA" + +#define RSC_SYS_REG_HDR12_SCTL2_CODE \ + "SCT2\0 EL0\0 EL1\0 EL0\0 EL1\0 EL0\0 EL1\0 128\0 \0ERR \0ERR \0 " + +#define RSC_SYS_REG_HDR_FPSR_CODE \ + "FPSR\0 N \0 Z \0 C \0 V \0 QC \0 IDC\0 IXC\0 UFC\0 OFC\0 DZC\0 IOC" + +#define RSC_SYS_REG_HDR11_EL_CODE \ + " EL \0 \0"" Lev\0el0 \0 \0 Lev\0el1 \0 \0" \ + " L\0evel\0""2 \0 \0 Lev\0el3 " + +#define RSC_SYS_REG_HDR12_EL_CODE \ + "Exec\0: \0 64 \0 32 \0 \0 64 \0 32 \0 \0" \ + " 64 \0 32 \0 SEC\0 \0 64 \0 32 " + +#define RSC_ISA_AES_CODE " AES [%c]" +#define RSC_ISA_PMULL_CODE " PMULL [%c]" +#define RSC_ISA_LSE_CODE " LSE [%c]" +#define RSC_ISA_LSE128_CODE " LSE128 [%c]" +#define RSC_ISA_CRC32_CODE " CRC32 [%c]" +#define RSC_ISA_DP_CODE " DP [%c]" +#define RSC_ISA_EPAC_CODE " EPAC [%c]" +#define RSC_ISA_FCMA_CODE " FCMA [%c]" +#define RSC_ISA_FHM_CODE " FHM [%c]" +#define RSC_ISA_FP_CODE " FP [%c]" +#define RSC_ISA_FPAC_CODE " FPAC [%c]" +#define RSC_ISA_FPACCOMBINE_CODE " FPACCOMBINE [%c]" +#define RSC_ISA_JSCVT_CODE " JSCVT [%c]" +#define RSC_ISA_LRCPC_CODE " LRCPC [%c]" +#define RSC_ISA_LRCPC2_CODE " LRCPC2 [%c]" +#define RSC_ISA_LRCPC3_CODE " LRCPC3 [%c]" +#define RSC_ISA_LUT_CODE " LUT [%c]" +#define RSC_ISA_MOPS_CODE " MOPS [%c]" +#define RSC_ISA_PACGA_CODE " PACGA [%c]" +#define RSC_ISA_PACQARMA3_CODE " PACQARMA3 [%c]" +#define RSC_ISA_PACQARMA5_CODE " PACQARMA5 [%c]" +#define RSC_ISA_PAUTH_CODE " PAuth [%c]" +#define RSC_ISA_PAUTH2_CODE " PAuth2 [%c]" +#define RSC_ISA_PAUTH_LR_CODE " PAuth_LR [%c]" +#define RSC_ISA_PRFMSLC_CODE " PRFMSLC [%c]" +#define RSC_ISA_FRINTTS_CODE " FRINTTS [%c]" +#define RSC_ISA_SPECRES_CODE " SPECRES [%c]" +#define RSC_ISA_SPECRES2_CODE " SPECRES2 [%c]" +#define RSC_ISA_ATS1A_CODE " ATS1A [%c]" +#define RSC_ISA_BF16_CODE " BF16 [%c]" +#define RSC_ISA_EBF16_CODE " EBF16 [%c]" +#define RSC_ISA_CONSTPACFLD_CODE " CONSTPACFLD [%c]" +#define RSC_ISA_CSSC_CODE " CSSC [%c]" +#define RSC_ISA_HBC_CODE " HBC [%c]" +#define RSC_ISA_I8MM_CODE " I8MM [%c]" +#define RSC_ISA_RPRES_CODE " RPRES [%c]" +#define RSC_ISA_SB_CODE " SB [%c]" +#define RSC_ISA_SYSREG128_CODE " SYSREG128 [%c]" +#define RSC_ISA_SYSINSTR128_CODE " SYSINSTR128 [%c]" +#define RSC_ISA_WFxT_CODE " WFxT [%c]" +#define RSC_ISA_XS_CODE " XS [%c]" +#define RSC_ISA_LS64_CODE " LS64 [%c]" +#define RSC_ISA_LS64_V_CODE " LS64_V [%c]" +#define RSC_ISA_LS64_ACCDATA_CODE " LS64_ACCDATA [%c]" +#define RSC_ISA_DGH_CODE " DGH [%c]" +#define RSC_ISA_DPB_CODE " DPB [%c]" +#define RSC_ISA_DPB2_CODE " DPB2 [%c]" +#define RSC_ISA_RAND_CODE " RAND [%c]" +#define RSC_ISA_RDMA_CODE " RDMA [%c]" +#define RSC_ISA_RNG_TRAP_CODE " RNG-TRAP [%c]" +#define RSC_ISA_RPRFM_CODE " RPRFM [%c]" +#define RSC_ISA_SHA1_CODE " SHA1 [%c]" +#define RSC_ISA_SHA256_CODE " SHA256 [%c]" +#define RSC_ISA_SHA512_CODE " SHA512 [%c]" +#define RSC_ISA_SHA3_CODE " SHA3 [%c]" +#define RSC_ISA_SIMD_CODE " ASIMD [%c]" +#define RSC_ISA_SM3_CODE " SM3 [%c]" +#define RSC_ISA_SM4_CODE " SM4 [%c]" +#define RSC_ISA_SME_CODE " SME [%c]" +#define RSC_ISA_SVE_CODE " SVE [%c]" +#define RSC_ISA_SVE_F64MM_CODE " SVE_F64MM [%c]" +#define RSC_ISA_SVE_F32MM_CODE " SVE_F32MM [%c]" +#define RSC_ISA_SVE_I8MM_CODE " SVE_I8MM [%c]" +#define RSC_ISA_SVE_SM4_CODE " SVE_SM4 [%c]" +#define RSC_ISA_SVE_SHA3_CODE " SVE_SHA3 [%c]" +#define RSC_ISA_SVE_BF16_CODE " SVE_BF16 [%c]" +#define RSC_ISA_SVE_EBF16_CODE " SVE_EBF16 [%c]" +#define RSC_ISA_SVE_BitPerm_CODE " SVE_BitPerm [%c]" +#define RSC_ISA_SVE_AES_CODE " SVE_AES [%c]" +#define RSC_ISA_SVE_PMULL128_CODE " SVE_PMULL128 [%c]" +#define RSC_ISA_SVE2_CODE " SVE2 [%c]" +#define RSC_ISA_SME2_CODE " SME2 [%c]" +#define RSC_ISA_SME2p1_CODE " SME2p1 [%c]" +#define RSC_ISA_SME_FA64_CODE " SME_FA64 [%c]" +#define RSC_ISA_SME_LUTv2_CODE " SME_LUTv2 [%c]" +#define RSC_ISA_SME_I16I64_CODE " SME_I16I64 [%c]" +#define RSC_ISA_SME_F64F64_CODE " SME_F64F64 [%c]" +#define RSC_ISA_SME_I16I32_CODE " SME_I16I32 [%c]" +#define RSC_ISA_SME_B16B16_CODE " SME_B16B16 [%c]" +#define RSC_ISA_SME_F16F16_CODE " SME_F16F16 [%c]" +#define RSC_ISA_SME_F8F16_CODE " SME_F8F16 [%c]" +#define RSC_ISA_SME_F8F32_CODE " SME_F8F32 [%c]" +#define RSC_ISA_SME_I8I32_CODE " SME_I8I32 [%c]" +#define RSC_ISA_SME_F16F32_CODE " SME_F16F32 [%c]" +#define RSC_ISA_SME_B16F32_CODE " SME_B16F32 [%c]" +#define RSC_ISA_SME_BI32I32_CODE " SME_BI32I32 [%c]" +#define RSC_ISA_SME_F32F32_CODE " SME_F32F32 [%c]" +#define RSC_ISA_SME_SF8FMA_CODE " SME_SF8FMA [%c]" +#define RSC_ISA_SME_SF8DP4_CODE " SME_SF8DP4 [%c]" +#define RSC_ISA_SME_SF8DP2_CODE " SME_SF8DP2 [%c]" +#define RSC_ISA_FlagM_CODE " FlagM [%c]" +#define RSC_ISA_FlagM2_CODE " FlagM2 [%c]" diff --git a/aarch64/corefreq-cli-rsc-fr.h b/aarch64/corefreq-cli-rsc-fr.h new file mode 100644 index 00000000..9fce744f --- /dev/null +++ b/aarch64/corefreq-cli-rsc-fr.h @@ -0,0 +1,1331 @@ +/* + * CoreFreq + * Copyright (C) 2015-2024 CYRIL COURTIAT + * Licenses: GPL2 + */ + +/* Shell tip to list French Unicode accents + * +for h in 8 9 a b; do for l in 0 1 2 3 4 5 6 7 8 9 a b c d e f; \ +do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo +* +*/ + +#define RSC_COPY0_CODE_FR " par CyrIng " +#define RSC_COPY1_CODE_FR " " +#define RSC_COPY2_CODE_FR " (C)2015-2024 " \ + "CYRIL COURTIAT " + +#define RSC_LAYOUT_HEADER_PROC_CODE_FR \ +{ \ + ' ','P','r','o','c','e','s','s','e','u','r','[' \ +} + +#define RSC_LAYOUT_HEADER_CPU_CODE_FR RSC_LAYOUT_HEADER_CPU_CODE_EN + +#define RSC_LAYOUT_HEADER_ARCH_CODE_FR RSC_LAYOUT_HEADER_ARCH_CODE_EN + +#define RSC_LAYOUT_HEADER_CACHE_L1_CODE_FR RSC_LAYOUT_HEADER_CACHE_L1_CODE_EN + +#define RSC_LAYOUT_HEADER_BCLK_CODE_FR \ +{ \ + ' ','H','o','r','l','o','g','e',' ',' ',' ',' ', \ + '~',' ','0','0','0',' ','0','0','0',' ','0','0','0',' ','H','z' \ +} + +#define RSC_LAYOUT_HEADER_CACHES_CODE_FR RSC_LAYOUT_HEADER_CACHES_CODE_EN + +#define RSC_LAYOUT_RULER_LOAD_CODE_FR RSC_LAYOUT_RULER_LOAD_CODE_EN + +#define RSC_LAYOUT_RULER_REL_LOAD_CODE_FR \ +{ \ + 'F','r',0xa9,'q','u','e','n','c','e',' ','r','e','l','a','t','i',\ + 'v','e' \ +} + +#define RSC_LAYOUT_RULER_ABS_LOAD_CODE_FR \ +{ \ + 'F','r',0xa9,'q','u','e','n','c','e',' ','a','b','s','o','l','u',\ + 'e',' ' \ +} + +#define RSC_LAYOUT_MONITOR_FREQUENCY_CODE_FR \ + RSC_LAYOUT_MONITOR_FREQUENCY_CODE_EN + +#define RSC_LAYOUT_MONITOR_INST_CODE_FR RSC_LAYOUT_MONITOR_INST_CODE_EN + +#define RSC_LAYOUT_MONITOR_COMMON_CODE_FR RSC_LAYOUT_MONITOR_COMMON_CODE_EN + +#define RSC_LAYOUT_MONITOR_TASKS_CODE_FR RSC_LAYOUT_MONITOR_TASKS_CODE_EN + +#define RSC_LAYOUT_MONITOR_SLICE_CODE_FR RSC_LAYOUT_MONITOR_SLICE_CODE_EN + +#define RSC_LAYOUT_CUSTOM_FIELD_CODE_FR RSC_LAYOUT_CUSTOM_FIELD_CODE_EN + +#define RSC_LAYOUT_RULER_FREQUENCY_CODE_FR \ +{ \ + '-','-','-',' ','F','r',0xa9,'q','(','M','H','z',')',' ','R','a',\ + 't','i','o',' ','-',' ','T','u','r','b','o',' ','-','-',' ','C',\ + '0',' ','-','-','-','-',' ','C','1',' ','-','-',' ','C','2',':',\ + 'C','3',' ','-',' ','C','4',':','C','6',' ','-','-','-',' ','C',\ + '7',' ','-','-',' ','M','i','n',' ','T','M','P',' ','M','a','x',\ + ' ','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-' \ +} + +#define RSC_LAYOUT_RULER_FREQUENCY_AVG_CODE_FR \ +{ \ + '-','-','-','-','-','-',' ','%',' ','M','o','y','e','n','n','e',\ + 's',' ','[',' ',' ',' ',' ',0x0,' ',' ',0x0,' ',' ',' ',' ',0x0,\ + ' ',' ',0x0,' ',' ',' ',' ',0x0,' ',' ',0x0,' ',' ',' ',' ',0x0,\ + ' ',' ',0x0,' ',' ',' ',' ',0x0,' ',' ',0x0,' ',' ',' ',' ',0x0,\ + ' ',' ',0x0,' ',']','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\ + '-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-' \ +} + +#define RSC_LAYOUT_RULER_FREQUENCY_PKG_CODE_FR \ + RSC_LAYOUT_RULER_FREQUENCY_PKG_CODE_EN + +#define RSC_LAYOUT_RULER_INST_CODE_FR RSC_LAYOUT_RULER_INST_CODE_EN + +#define RSC_LAYOUT_RULER_CYCLES_CODE_FR RSC_LAYOUT_RULER_CYCLES_CODE_EN + +#define RSC_LAYOUT_RULER_CSTATES_CODE_FR RSC_LAYOUT_RULER_CSTATES_CODE_EN + +#define RSC_LAYOUT_RULER_INTERRUPTS_CODE_FR \ + RSC_LAYOUT_RULER_INTERRUPTS_CODE_EN + +#define RSC_LAYOUT_RULER_PACKAGE_CODE_FR \ + "------------ Cycles ---- ""\x89""tat ------------------ Ratio Horl" \ + "oge --------------------------------------------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "--------------------" + +#define RSC_LAYOUT_RULER_TASKS_CODE_FR \ + "--- Fr""\xa9""q(MHz) ---T""\xa2""ches" \ + " -----------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "--------------------" + +#define RSC_LAYOUT_PACKAGE_PC_CODE_FR RSC_LAYOUT_PACKAGE_PC_CODE_EN + +#define RSC_LAYOUT_PACKAGE_PC02_CODE_FR RSC_LAYOUT_PACKAGE_PC02_CODE_EN +#define RSC_LAYOUT_PACKAGE_PC03_CODE_FR RSC_LAYOUT_PACKAGE_PC03_CODE_EN +#define RSC_LAYOUT_PACKAGE_PC04_CODE_FR RSC_LAYOUT_PACKAGE_PC04_CODE_EN +#define RSC_LAYOUT_PACKAGE_PC06_CODE_FR RSC_LAYOUT_PACKAGE_PC06_CODE_EN +#define RSC_LAYOUT_PACKAGE_PC07_CODE_FR RSC_LAYOUT_PACKAGE_PC07_CODE_EN +#define RSC_LAYOUT_PACKAGE_PC08_CODE_FR RSC_LAYOUT_PACKAGE_PC08_CODE_EN +#define RSC_LAYOUT_PACKAGE_PC09_CODE_FR RSC_LAYOUT_PACKAGE_PC09_CODE_EN +#define RSC_LAYOUT_PACKAGE_PC10_CODE_FR RSC_LAYOUT_PACKAGE_PC10_CODE_EN +#define RSC_LAYOUT_PACKAGE_MC06_CODE_FR RSC_LAYOUT_PACKAGE_MC06_CODE_EN + +#define RSC_LAYOUT_PACKAGE_UNCORE_CODE_FR RSC_LAYOUT_PACKAGE_UNCORE_CODE_EN + +#define RSC_LAYOUT_TASKS_STATE_SORTED_CODE_FR \ +{ \ + '(','t','r','i','e','r',' ','[', 'b',']', \ + ' ',0x89,'t','a','t',' ',')',' ', '-','-','-' \ +} + +#define RSC_LAYOUT_TASKS_RUNTIME_SORTED_CODE_FR \ +{ \ + '(','t','r','i','e','r',' ','[', 'b',']', \ + ' ','R','u','n','T','i','m','e', ')',' ','-' \ +} + +#define RSC_LAYOUT_TASKS_USRTIME_SORTED_CODE_FR \ +{ \ + '(','t','r','i','e','r',' ','[', 'b',']', \ + ' ','U','s','e','r','T','i','m', 'e',')',' ' \ +} + +#define RSC_LAYOUT_TASKS_SYSTIME_SORTED_CODE_FR \ +{ \ + '(','t','r','i','e','r',' ','[', 'b',']', \ + ' ','S','y','s','T','i','m','e', ')',' ','-' \ +} + +#define RSC_LAYOUT_TASKS_PROCESS_SORTED_CODE_FR \ +{ \ + '(','t','r','i','e','r',' ','[', 'b',']', \ + ' ','P','I','D',')',' ','-','-', '-','-','-' \ +} + +#define RSC_LAYOUT_TASKS_COMMAND_SORTED_CODE_FR \ +{ \ + '(','t','r','i','e','r',' ','[', 'b',']', \ + ' ','C','o','m','m','a','n','d', ')',' ','-' \ +} + +#define RSC_LAYOUT_TASKS_REVERSE_SORT_OFF_CODE_FR \ +{ \ + ' ', 'I','n','v','e','r','s','e','r','[','O','F','F',']',' ' \ +} + +#define RSC_LAYOUT_TASKS_REVERSE_SORT_ON_CODE_FR \ +{ \ + ' ', 'I','n','v','e','r','s','e','r','[',' ','O','N',']',' ' \ +} + +#define RSC_LAYOUT_TASKS_VALUE_SWITCH_CODE_FR \ +{ \ + ' ', 'V','a','l','e','u','r','[',' ',' ',' ',']',' ' \ +} + +#define RSC_LAYOUT_TASKS_VALUE_OFF_CODE_FR RSC_LAYOUT_TASKS_VALUE_OFF_CODE_EN + +#define RSC_LAYOUT_TASKS_VALUE_ON_CODE_FR RSC_LAYOUT_TASKS_VALUE_ON_CODE_EN + +#define RSC_LAYOUT_TASKS_TRACKING_CODE_FR \ +{ \ + 'S','u','i','v','i',' ','[', 'n',']',' ','P','I','D',' ','[',' ',\ + ' ','O','F','F',' ',' ',']',' ' \ +} + +#define RSC_LAYOUT_RULER_SENSORS_CODE_FR \ + "--- Fr""\xa9""q(MHz) --- Vcore --- TMP( ) -- " \ + "\x89""nergie(J) Puissance(W" \ + ") ----------------------------------------------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "--------------------" + +#define RSC_LAYOUT_RULER_PWR_SOC_CODE_FR RSC_LAYOUT_RULER_PWR_SOC_CODE_EN + +#define RSC_LAYOUT_RULER_VOLTAGE_CODE_FR \ + "--- Fr""\xa9""q(MHz) - VID --- Min(V)-- Vcore -- Max(V) -----------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "--------------------" + +#define RSC_LAYOUT_RULER_VPKG_SOC_CODE_FR \ + "-Processeur[ ] ----- SoC " \ + "[ ] [ V]-----------------------------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "--------------------" + +#define RSC_LAYOUT_RULER_ENERGY_CODE_FR \ + "--- Fr" "\xa9" "q(MHz) -- Accumulateur ------- Min ----- " \ + "\x89" "nergie(J) -- Max ------------------------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "--------------------------------------" + +#define RSC_LAYOUT_RULER_POWER_CODE_FR \ + "--- Fr" "\xa9" "q(MHz) -- Accumulateur ------- Min --- " \ + "Puissance(W) -- Max ----------------------------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "----------------------------------" + +#define RSC_LAYOUT_RULER_SLICE_CODE_FR \ + "--- Fr""\xa9""q(MHz) ------ Cycles -- Instructions ------------ TSC" \ + " ------------ PMC0 ---------- Erreur -----------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "------------------------------------------------------------" \ + "--------------------" + +#define RSC_LAYOUT_RULER_CUSTOM_CODE_FR RSC_LAYOUT_RULER_CUSTOM_CODE_EN + +#define RSC_LAYOUT_FOOTER_TECH_TSC_CODE_FR RSC_LAYOUT_FOOTER_TECH_TSC_CODE_EN + +#define RSC_LAYOUT_FOOTER_VOLT_TEMP_CODE_FR RSC_LAYOUT_FOOTER_VOLT_TEMP_CODE_EN + +#define RSC_LAYOUT_FOOTER_SYSTEM_CODE_FR \ +{ \ + 'T',0xa2,'c','h','e','s','[',' ',' ',' ',' ',' ',' ',']', \ + ' ','M',0xa9,'m',' ','[',' ',' ',' ',' ',' ',' ',' ',' ', \ + ' ','/',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ','B',']' \ +} + +#define RSC_LAYOUT_CARD_CORE_ONLINE_COND0_CODE_FR \ + RSC_LAYOUT_CARD_CORE_ONLINE_COND0_CODE_EN + +#define RSC_LAYOUT_CARD_CORE_ONLINE_COND1_CODE_FR \ + RSC_LAYOUT_CARD_CORE_ONLINE_COND1_CODE_EN + +#define RSC_LAYOUT_CARD_CORE_OFFLINE_CODE_FR \ + RSC_LAYOUT_CARD_CORE_OFFLINE_CODE_EN + +#define RSC_LAYOUT_CARD_CLK_CODE_FR RSC_LAYOUT_CARD_CLK_CODE_EN + +#define RSC_LAYOUT_CARD_UNCORE_CODE_FR RSC_LAYOUT_CARD_UNCORE_CODE_EN + +#define RSC_LAYOUT_CARD_BUS_CODE_FR RSC_LAYOUT_CARD_BUS_CODE_EN + +#define RSC_LAYOUT_CARD_MC_CODE_FR RSC_LAYOUT_CARD_MC_CODE_EN + +#define RSC_LAYOUT_CARD_LOAD_CODE_FR \ +{ \ + '[',' ',' ','%','A','C','T','I','F',' ',' ',']' \ +} + +#define RSC_LAYOUT_CARD_IDLE_CODE_FR \ +{ \ + '[',' ',' ','%','R','E','P','O','S',' ',' ',']' \ +} + +#define RSC_LAYOUT_CARD_RAM_CODE_FR RSC_LAYOUT_CARD_RAM_CODE_EN + +#define RSC_LAYOUT_CARD_TASK_CODE_FR \ +{ \ + '[','T',0xa2,'c','h','e',' ',' ',' ',' ',' ',']' \ +} + +#define RSC_CREATE_HOTPLUG_CPU_ENABLE_CODE_FR "< ACTIVER >" +#define RSC_CREATE_HOTPLUG_CPU_DISABLE_CODE_FR "" +#define RSC_CREATE_HOTPLUG_CPU_ONLINE_CODE_FR " %03u On " +#define RSC_CREATE_HOTPLUG_CPU_OFFLINE_CODE_FR " %03u Off " + +#define RSC_PROCESSOR_TITLE_CODE_FR " Processeur " +#define RSC_PROCESSOR_CODE_FR "Processeur" +#define RSC_ARCHITECTURE_CODE_FR "Architecture" +#define RSC_VENDOR_ID_CODE_FR "ID vendeur" +#define RSC_REVISION_CODE_FR "R""\xa9""vision" +#define RSC_SIGNATURE_CODE_FR "Signature" +#define RSC_STEPPING_CODE_FR "Stepping" +#define RSC_ONLINE_CPU_CODE_FR "CPU en ligne" +#define RSC_BASE_CLOCK_CODE_FR "Horloge de base" +#define RSC_FREQUENCY_CODE_FR "Fr""\xa9""quence" +#define RSC_RATIO_CODE_FR "Ratio" +#define RSC_FACTORY_CODE_FR "Usine" +#define RSC_PERFORMANCE_CODE_FR "Performance" +#define RSC_TARGET_CODE_FR "Cible" +#define RSC_UNLOCK_CODE_FR "OUVERT" +#define RSC_LOCK_CODE_FR "BLOQU""\x89" +#define RSC_ENABLE_CODE_FR " Actif" +#define RSC_DISABLE_CODE_FR "Inactif" +#define RSC_CAPABILITIES_CODE_FR "Capacit""\xa9""s" +#define RSC_LOWEST_CODE_FR "Faible" +#define RSC_EFFICIENT_CODE_FR "Efficace" +#define RSC_GUARANTEED_CODE_FR "Guarantie" +#define RSC_HIGHEST_CODE_FR "Elev""\xa9""e" +#define RSC_RECORDER_CODE_FR "Enregistreur" +#define RSC_STRESS_CODE_FR "Charge" + +#define RSC_SCOPE_NONE_CODE_FR "Sans" +#define RSC_SCOPE_THREAD_CODE_FR " SMT" +#define RSC_SCOPE_CORE_CODE_FR "Core" +#define RSC_SCOPE_PACKAGE_CODE_FR " Pkg" + +#define RSC_SYS_REGS_TITLE_CODE_FR " Registres Syst""\xa8""me " +#define RSC_SYS_REG_PSTATE_CODE_FR RSC_SYS_REG_PSTATE_CODE_EN +#define RSC_SYS_REG_FLAG_N_CODE_FR RSC_SYS_REG_FLAG_N_CODE_EN +#define RSC_SYS_REG_FLAG_Z_CODE_FR RSC_SYS_REG_FLAG_Z_CODE_EN +#define RSC_SYS_REG_FLAG_C_CODE_FR RSC_SYS_REG_FLAG_C_CODE_EN +#define RSC_SYS_REG_FLAG_V_CODE_FR RSC_SYS_REG_FLAG_V_CODE_EN +#define RSC_SYS_REG_FLAG_D_CODE_FR RSC_SYS_REG_FLAG_D_CODE_EN +#define RSC_SYS_REG_FLAG_A_CODE_FR RSC_SYS_REG_FLAG_A_CODE_EN +#define RSC_SYS_REG_FLAG_I_CODE_FR RSC_SYS_REG_FLAG_I_CODE_EN +#define RSC_SYS_REG_FLAG_F_CODE_FR RSC_SYS_REG_FLAG_F_CODE_EN +#define RSC_SYS_REG_FLAG_EL_CODE_FR RSC_SYS_REG_FLAG_EL_CODE_EN +#define RSC_SYS_REG_FLAG_SM_CODE_FR RSC_SYS_REG_FLAG_SM_CODE_EN +#define RSC_SYS_REG_FLAG_SSBS_CODE_FR RSC_SYS_REG_FLAG_SSBS_CODE_EN +#define RSC_SYS_REG_FLAG_NMI_CODE_FR RSC_SYS_REG_FLAG_NMI_CODE_EN +#define RSC_SYS_REG_FLAG_PAN_CODE_FR RSC_SYS_REG_FLAG_PAN_CODE_EN +#define RSC_SYS_REG_FLAG_UAO_CODE_FR RSC_SYS_REG_FLAG_UAO_CODE_EN +#define RSC_SYS_REG_FLAG_DIT_CODE_FR RSC_SYS_REG_FLAG_DIT_CODE_EN +#define RSC_SYS_REG_FLAG_TCO_CODE_FR RSC_SYS_REG_FLAG_TCO_CODE_EN +#define RSC_SYS_REG_FLAG_PM_CODE_FR RSC_SYS_REG_FLAG_PM_CODE_EN + +#define RSC_SYS_REG_SCTL_CODE_FR RSC_SYS_REG_SCTL_CODE_EN +#define RSC_SYS_REG_TIDCP_CODE_FR RSC_SYS_REG_TIDCP_CODE_EN +#define RSC_SYS_REG_SPINT_CODE_FR RSC_SYS_REG_SPINT_CODE_EN +#define RSC_SYS_REG_NMI_CODE_FR RSC_SYS_REG_NMI_CODE_EN +#define RSC_SYS_REG_EnTP2_CODE_FR RSC_SYS_REG_EnTP2_CODE_EN +#define RSC_SYS_REG_TCSO_CODE_FR RSC_SYS_REG_TCSO_CODE_EN +#define RSC_SYS_REG_TCSO1_CODE_FR RSC_SYS_REG_TCSO1_CODE_EN +#define RSC_SYS_REG_TCSO0_CODE_FR RSC_SYS_REG_TCSO0_CODE_EN +#define RSC_SYS_REG_EPAN_CODE_FR RSC_SYS_REG_EPAN_CODE_EN +#define RSC_SYS_REG_EnALS_CODE_FR RSC_SYS_REG_EnALS_CODE_EN +#define RSC_SYS_REG_EnAS0_CODE_FR RSC_SYS_REG_EnAS0_CODE_EN +#define RSC_SYS_REG_EnASR_CODE_FR RSC_SYS_REG_EnASR_CODE_EN +#define RSC_SYS_REG_TME_CODE_FR RSC_SYS_REG_TME_CODE_EN +#define RSC_SYS_REG_TME1_CODE_FR RSC_SYS_REG_TME1_CODE_EN +#define RSC_SYS_REG_TME0_CODE_FR RSC_SYS_REG_TME0_CODE_EN +#define RSC_SYS_REG_TMT_CODE_FR RSC_SYS_REG_TMT_CODE_EN +#define RSC_SYS_REG_TMT1_CODE_FR RSC_SYS_REG_TMT1_CODE_EN +#define RSC_SYS_REG_TMT0_CODE_FR RSC_SYS_REG_TMT0_CODE_EN +#define RSC_SYS_REG_TWE_D_CODE_FR RSC_SYS_REG_TWE_D_CODE_EN +#define RSC_SYS_REG_TWE_C_CODE_FR RSC_SYS_REG_TWE_C_CODE_EN +#define RSC_SYS_REG_TWE_E_CODE_FR RSC_SYS_REG_TWE_E_CODE_EN +#define RSC_SYS_REG_DSSBS_CODE_FR RSC_SYS_REG_DSSBS_CODE_EN +#define RSC_SYS_REG_ATA_CODE_FR RSC_SYS_REG_ATA_CODE_EN +#define RSC_SYS_REG_ATA1_CODE_FR RSC_SYS_REG_ATA1_CODE_EN +#define RSC_SYS_REG_ATA0_CODE_FR RSC_SYS_REG_ATA0_CODE_EN +#define RSC_SYS_REG_TCF_CODE_FR RSC_SYS_REG_TCF_CODE_EN +#define RSC_SYS_REG_TCF1_CODE_FR RSC_SYS_REG_TCF1_CODE_EN +#define RSC_SYS_REG_TCF0_CODE_FR RSC_SYS_REG_TCF0_CODE_EN +#define RSC_SYS_REG_ITFSB_CODE_FR RSC_SYS_REG_ITFSB_CODE_EN +#define RSC_SYS_REG_BT_CODE_FR RSC_SYS_REG_BT_CODE_EN +#define RSC_SYS_REG_BT1_CODE_FR RSC_SYS_REG_BT1_CODE_EN +#define RSC_SYS_REG_BT0_CODE_FR RSC_SYS_REG_BT0_CODE_EN +#define RSC_SYS_REG_EnFPM_CODE_FR RSC_SYS_REG_EnFPM_CODE_EN +#define RSC_SYS_REG_MSCEn_CODE_FR RSC_SYS_REG_MSCEn_CODE_EN +#define RSC_SYS_REG_CMOW_CODE_FR RSC_SYS_REG_CMOW_CODE_EN +#define RSC_SYS_REG_EnIA_CODE_FR RSC_SYS_REG_EnIA_CODE_EN +#define RSC_SYS_REG_EnIB_CODE_FR RSC_SYS_REG_EnIB_CODE_EN +#define RSC_SYS_REG_LSM_CODE_FR RSC_SYS_REG_LSM_CODE_EN +#define RSC_SYS_REG_LSMA_CODE_FR RSC_SYS_REG_LSMA_CODE_EN +#define RSC_SYS_REG_LSMD_CODE_FR RSC_SYS_REG_LSMD_CODE_EN +#define RSC_SYS_REG_EnDA_CODE_FR RSC_SYS_REG_EnDA_CODE_EN +#define RSC_SYS_REG_UCI_CODE_FR RSC_SYS_REG_UCI_CODE_EN +#define RSC_SYS_REG_EE_CODE_FR RSC_SYS_REG_EE_CODE_EN +#define RSC_SYS_REG_E0E_CODE_FR RSC_SYS_REG_E0E_CODE_EN +#define RSC_SYS_REG_SPAN_CODE_FR RSC_SYS_REG_SPAN_CODE_EN +#define RSC_SYS_REG_EIS_CODE_FR RSC_SYS_REG_EIS_CODE_EN +#define RSC_SYS_REG_IESB_CODE_FR RSC_SYS_REG_IESB_CODE_EN +#define RSC_SYS_REG_TSCXT_CODE_FR RSC_SYS_REG_TSCXT_CODE_EN +#define RSC_SYS_REG_WXN_CODE_FR RSC_SYS_REG_WXN_CODE_EN +#define RSC_SYS_REG_nTWE_CODE_FR RSC_SYS_REG_nTWE_CODE_EN +#define RSC_SYS_REG_nTWI_CODE_FR RSC_SYS_REG_nTWI_CODE_EN +#define RSC_SYS_REG_UCT_CODE_FR RSC_SYS_REG_UCT_CODE_EN +#define RSC_SYS_REG_DZE_CODE_FR RSC_SYS_REG_DZE_CODE_EN +#define RSC_SYS_REG_EnDB_CODE_FR RSC_SYS_REG_EnDB_CODE_EN +#define RSC_SYS_REG_I_CODE_FR RSC_SYS_REG_I_CODE_EN +#define RSC_SYS_REG_EOS_CODE_FR RSC_SYS_REG_EOS_CODE_EN +#define RSC_SYS_REG_RCTX_CODE_FR RSC_SYS_REG_RCTX_CODE_EN +#define RSC_SYS_REG_UMA_CODE_FR RSC_SYS_REG_UMA_CODE_EN +#define RSC_SYS_REG_SED_CODE_FR RSC_SYS_REG_SED_CODE_EN +#define RSC_SYS_REG_ITD_CODE_FR RSC_SYS_REG_ITD_CODE_EN +#define RSC_SYS_REG_nAA_CODE_FR RSC_SYS_REG_nAA_CODE_EN +#define RSC_SYS_REG_CP15B_CODE_FR RSC_SYS_REG_CP15B_CODE_EN +#define RSC_SYS_REG_SA0_CODE_FR RSC_SYS_REG_SA0_CODE_EN +#define RSC_SYS_REG_SA1_CODE_FR RSC_SYS_REG_SA1_CODE_EN +#define RSC_SYS_REG_C_CODE_FR RSC_SYS_REG_C_CODE_EN +#define RSC_SYS_REG_A_CODE_FR RSC_SYS_REG_A_CODE_EN +#define RSC_SYS_REG_M_CODE_FR RSC_SYS_REG_M_CODE_EN + +#define RSC_SYS_REG_SCTL2_CODE_FR RSC_SYS_REG_SCTL2_CODE_EN +#define RSC_SYS_REG_CPTM_CODE_FR RSC_SYS_REG_CPTM_CODE_EN +#define RSC_SYS_REG_CPTM0_CODE_FR RSC_SYS_REG_CPTM0_CODE_EN +#define RSC_SYS_REG_CPTM1_CODE_FR RSC_SYS_REG_CPTM1_CODE_EN +#define RSC_SYS_REG_CPTA_CODE_FR RSC_SYS_REG_CPTA_CODE_EN +#define RSC_SYS_REG_CPTA0_CODE_FR RSC_SYS_REG_CPTA0_CODE_EN +#define RSC_SYS_REG_CPTA1_CODE_FR RSC_SYS_REG_CPTA1_CODE_EN +#define RSC_SYS_REG_PACM_CODE_FR RSC_SYS_REG_PACM_CODE_EN +#define RSC_SYS_REG_PACM0_CODE_FR RSC_SYS_REG_PACM0_CODE_EN +#define RSC_SYS_REG_PACM1_CODE_FR RSC_SYS_REG_PACM1_CODE_EN +#define RSC_SYS_REG_128SR_CODE_FR RSC_SYS_REG_128SR_CODE_EN +#define RSC_SYS_REG_EASE_CODE_FR RSC_SYS_REG_EASE_CODE_EN +#define RSC_SYS_REG_ANERR_CODE_FR RSC_SYS_REG_ANERR_CODE_EN +#define RSC_SYS_REG_ADERR_CODE_FR RSC_SYS_REG_ADERR_CODE_EN +#define RSC_SYS_REG_NMEA_CODE_FR RSC_SYS_REG_NMEA_CODE_EN + +#define RSC_SYS_REG_FPSR_CODE_FR RSC_SYS_REG_FPSR_CODE_EN +#define RSC_SYS_REG_FPSR_QC_CODE_FR RSC_SYS_REG_FPSR_QC_CODE_EN +#define RSC_SYS_REG_FPSR_IDC_CODE_FR RSC_SYS_REG_FPSR_IDC_CODE_EN +#define RSC_SYS_REG_FPSR_IXC_CODE_FR RSC_SYS_REG_FPSR_IXC_CODE_EN +#define RSC_SYS_REG_FPSR_UFC_CODE_FR RSC_SYS_REG_FPSR_UFC_CODE_EN +#define RSC_SYS_REG_FPSR_OFC_CODE_FR RSC_SYS_REG_FPSR_OFC_CODE_EN +#define RSC_SYS_REG_FPSR_DZC_CODE_FR RSC_SYS_REG_FPSR_DZC_CODE_EN +#define RSC_SYS_REG_FPSR_IOC_CODE_FR RSC_SYS_REG_FPSR_IOC_CODE_EN + +#define RSC_SYS_REG_EL_CODE_FR RSC_SYS_REG_EL_CODE_EN +#define RSC_SYS_REG_EL_EXEC_CODE_FR RSC_SYS_REG_EL_EXEC_CODE_EN +#define RSC_SYS_REG_EL_SEC_CODE_FR RSC_SYS_REG_EL_SEC_CODE_EN + +#define RSC_ISA_TITLE_CODE_FR " Jeu d'instructions ""\xa9""tendu " + +#define RSC_ISA_AES_COMM_CODE_FR RSC_ISA_AES_COMM_CODE_EN +#define RSC_ISA_LSE_COMM_CODE_FR RSC_ISA_LSE_COMM_CODE_EN +#define RSC_ISA_CRC32_COMM_CODE_FR RSC_ISA_CRC32_COMM_CODE_EN +#define RSC_ISA_DP_COMM_CODE_FR RSC_ISA_DP_COMM_CODE_EN +#define RSC_ISA_EPAC_COMM_CODE_FR RSC_ISA_EPAC_COMM_CODE_EN +#define RSC_ISA_FCMA_COMM_CODE_FR RSC_ISA_FCMA_COMM_CODE_EN +#define RSC_ISA_FHM_COMM_CODE_FR RSC_ISA_FHM_COMM_CODE_EN +#define RSC_ISA_FP_COMM_CODE_FR RSC_ISA_FP_COMM_CODE_EN +#define RSC_ISA_FPAC_COMM_CODE_FR RSC_ISA_FPAC_COMM_CODE_EN +#define RSC_ISA_FPACCOMBINE_COMM_CODE_FR RSC_ISA_FPACCOMBINE_COMM_CODE_EN +#define RSC_ISA_JSCVT_COMM_CODE_FR RSC_ISA_JSCVT_COMM_CODE_EN +#define RSC_ISA_LRCPC_COMM_CODE_FR RSC_ISA_LRCPC_COMM_CODE_EN +#define RSC_ISA_LUT_COMM_CODE_FR RSC_ISA_LUT_COMM_CODE_EN +#define RSC_ISA_MOPS_COMM_CODE_FR RSC_ISA_MOPS_COMM_CODE_EN +#define RSC_ISA_PACIMP_COMM_CODE_FR RSC_ISA_PACIMP_COMM_CODE_EN +#define RSC_ISA_PACQARMA3_COMM_CODE_FR RSC_ISA_PACQARMA3_COMM_CODE_EN +#define RSC_ISA_PACQARMA5_COMM_CODE_FR RSC_ISA_PACQARMA5_COMM_CODE_EN +#define RSC_ISA_PAUTH_COMM_CODE_FR RSC_ISA_PAUTH_COMM_CODE_EN +#define RSC_ISA_PAUTH2_COMM_CODE_FR RSC_ISA_PAUTH2_COMM_CODE_EN +#define RSC_ISA_PAUTH_LR_COMM_CODE_FR RSC_ISA_PAUTH_LR_COMM_CODE_EN +#define RSC_ISA_PRFMSLC_COMM_CODE_FR RSC_ISA_PRFMSLC_COMM_CODE_EN +#define RSC_ISA_FRINTTS_COMM_CODE_FR RSC_ISA_FRINTTS_COMM_CODE_EN +#define RSC_ISA_SPECRES_COMM_CODE_FR RSC_ISA_SPECRES_COMM_CODE_EN +#define RSC_ISA_ATS1A_COMM_CODE_FR RSC_ISA_ATS1A_COMM_CODE_EN +#define RSC_ISA_BF16_COMM_CODE_FR RSC_ISA_BF16_COMM_CODE_EN +#define RSC_ISA_EBF16_COMM_CODE_FR RSC_ISA_EBF16_COMM_CODE_EN +#define RSC_ISA_CONSTPACFLD_COMM_CODE_FR RSC_ISA_CONSTPACFLD_COMM_CODE_EN +#define RSC_ISA_CSSC_COMM_CODE_FR RSC_ISA_CSSC_COMM_CODE_EN +#define RSC_ISA_HBC_COMM_CODE_FR RSC_ISA_HBC_COMM_CODE_EN +#define RSC_ISA_I8MM_COMM_CODE_FR RSC_ISA_I8MM_COMM_CODE_EN +#define RSC_ISA_RPRES_COMM_CODE_FR RSC_ISA_RPRES_COMM_CODE_EN +#define RSC_ISA_SB_COMM_CODE_FR RSC_ISA_SB_COMM_CODE_EN +#define RSC_ISA_SYSREG128_COMM_CODE_FR RSC_ISA_SYSREG128_COMM_CODE_EN +#define RSC_ISA_SYSINSTR128_COMM_CODE_FR RSC_ISA_SYSINSTR128_COMM_CODE_EN +#define RSC_ISA_WFxT_COMM_CODE_FR RSC_ISA_WFxT_COMM_CODE_EN +#define RSC_ISA_XS_COMM_CODE_FR RSC_ISA_XS_COMM_CODE_EN +#define RSC_ISA_LS64_COMM_CODE_FR RSC_ISA_LS64_COMM_CODE_EN +#define RSC_ISA_DGH_COMM_CODE_FR RSC_ISA_DGH_COMM_CODE_EN +#define RSC_ISA_DPB_COMM_CODE_FR RSC_ISA_DPB_COMM_CODE_EN +#define RSC_ISA_RAND_COMM_CODE_FR RSC_ISA_RAND_COMM_CODE_EN +#define RSC_ISA_RDMA_COMM_CODE_FR RSC_ISA_RDMA_COMM_CODE_EN +#define RSC_ISA_RNG_TRAP_COMM_CODE_FR RSC_ISA_RNG_TRAP_COMM_CODE_EN +#define RSC_ISA_RPRFM_COMM_CODE_FR RSC_ISA_RPRFM_COMM_CODE_EN +#define RSC_ISA_SHA_COMM_CODE_FR RSC_ISA_SHA_COMM_CODE_EN +#define RSC_ISA_SM_COMM_CODE_FR RSC_ISA_SM_COMM_CODE_EN +#define RSC_ISA_SIMD_COMM_CODE_FR RSC_ISA_SIMD_COMM_CODE_EN +#define RSC_ISA_SME_COMM_CODE_FR RSC_ISA_SME_COMM_CODE_EN +#define RSC_ISA_SVE_COMM_CODE_FR RSC_ISA_SVE_COMM_CODE_EN +#define RSC_ISA_FlagM_COMM_CODE_FR RSC_ISA_FlagM_COMM_CODE_EN + +#define RSC_FEATURES_TITLE_CODE_FR " Caract""\xa9""ristiques " +#define RSC_ON_CODE_FR " ON" +#define RSC_OFF_CODE_FR "OFF" +#define RSC_FMW_CODE_FR "FMW" +#define RSC_NOT_AVAILABLE_CODE_FR "N/A" +#define RSC_AUTOMATIC_CODE_FR "AUTO" +#define RSC_UNABLE_CODE_FR "Indispo" +#define RSC_MISSING_CODE_FR "Absent" +#define RSC_PRESENT_CODE_FR "Capable" +#define RSC_VARIANT_CODE_FR "Variant" +#define RSC_INVARIANT_CODE_FR "Invariant" + +#define RSC_FEATURES_ACPI_CODE_FR \ + "Configuration Avanc""\xa9""e & Interface d'Alimentation" + +#define RSC_FEATURES_AMU_CODE_FR \ + "Unit""\xa9"" de surveillance de l'activit""\xa9" + +#define RSC_FEATURES_BIG_END_CODE_FR "Endianisme Mixte" +#define RSC_FEATURES_BTI_CODE_FR "Validation des cibles de branche" + +#define RSC_FEATURES_EBEP_CODE_FR \ + "Profilage d'""\xa9""v""\xa9""nements bas""\xa9"" sur les exceptions" + +#define RSC_FEATURES_ECBHB_CODE_FR \ + "Contr. Exploit. avec Tampon Hist. Branchement" + +#define RSC_FEATURES_ECV_CODE_FR \ + "Virtualisation am""\xa9""lior""\xa9""e des compteurs" + +#define RSC_FEATURES_DF2_CODE_FR "Extension de Double D""\xa9""faut" +#define RSC_FEATURES_DIT_CODE_FR \ + "Chronom""\xa9""trage Ind""\xa9""pendant des Donn""\xa9""es" + +#define RSC_FEATURES_EXS_CODE_FR \ + "Sync. de Contexte & Gestion d'Exceptions" + +#define RSC_FEATURES_FGT_CODE_FR \ + "Contr""\xb4""les de Pi""\xa8""ges ""\xa0"" Granularit""\xa9"" Fine" + +#define RSC_FEATURES_PFAR_CODE_FR \ + "Registres de D""\xa9""faut d'Adresse Physique" + +#define RSC_FEATURES_GCS_CODE_FR \ + "Pile de Contr""\xb4""le Prot""\xa9""g""\xa9""e" + +#define RSC_FEATURES_GIC_CODE_FR \ + "Contr""\xb4""leur d'interruption g""\xa9""n""\xa9""rique" + +#define RSC_FEATURES_MTE_CODE_FR \ + "Extension de marquage de m""\xa9""moire" + +#define RSC_FEATURES_MPAM_CODE_FR \ + "Partitionnement et supervision de la m""\xa9""moire" + +#define RSC_FEATURES_NMI_CODE_FR "Interruption non masquable" +#define RSC_FEATURES_PA_CODE_FR "Plage d'Adressage Physique" +#define RSC_FEATURES_PAN_CODE_FR "Aucun privil""\xa8""ge d'acc""\xa8""s" +#define RSC_FEATURES_RAS_CODE_FR \ + "Fiabilit""\xa9"" Disponibilit""\xa9"" et Durabilit""\xa9" + +#define RSC_FEATURES_RME_CODE_FR "Extension de Gestion de Domaine" +#define RSC_FEATURES_SEL2_CODE_FR \ + "Impl""\xa9""mentation S""\xa9""curis""\xa9""e de l'EL2" + +#define RSC_FEATURES_THE_CODE_FR \ + "Endurcissement ""\x89""tendu de la Translation" + +#define RSC_FEATURES_TLB_CODE_FR "Instructions de gestion TLB" +#define RSC_FEATURES_TME_CODE_FR \ + "Extension de m""\xa9""moire transactionnelle" + +#define RSC_FEATURES_TSC_CODE_FR "Compteur d'horodatage" +#define RSC_FEATURES_UAO_CODE_FR \ + "Surcharge de l'acc""\xa8""s utilisateur" + +#define RSC_FEATURES_VA_CODE_FR "Plage d'adressage virtuel" +#define RSC_FEATURES_VHE_CODE_FR \ + "Extensions d'H""\xb4""te de Virtualisation" + +#define RSC_FEAT_SECTION_MECH_CODE_FR "M""\xa9""canismes d'att""\xa9""nuation" +#define RSC_FEAT_SECTION_SEC_CODE_FR "Fonctions de s""\xa9""curit""\xa9" + +#define RSC_TECHNOLOGIES_TITLE_CODE_FR " Technologies " +#define RSC_TECHNOLOGIES_DCU_CODE_FR "Unit""\xa9"" de cache de donn""\xa9""es" +#define RSC_TECHNOLOGIES_ICU_CODE_FR "Unit""\xa9"" de cache d'instructions" +#define RSC_TECHNOLOGIES_VM_CODE_FR "Virtualisation" +#define RSC_TECHNOLOGIES_IOMMU_CODE_FR "MMU E/S" +#define RSC_TECHNOLOGIES_SMT_CODE_FR "Multithreading simultan""\xa9" +#define RSC_TECHNOLOGIES_HYBRID_CODE_FR "Technologie big.LITTLE" +#define RSC_TECHNOLOGIES_HYPERV_CODE_FR "Hyperviseur" +#define RSC_TECHNOLOGIES_VM_COMM_CODE_FR RSC_TECHNOLOGIES_VM_COMM_CODE_EN +#define RSC_TECHNOLOGIES_IOMMU_COMM_CODE_FR RSC_TECHNOLOGIES_IOMMU_COMM_CODE_EN + +#define RSC_PERF_MON_TITLE_CODE_FR " Gestion de la performance " +#define RSC_PERF_CAPS_TITLE_CODE_FR " Capacit""\xa9""s de performances " +#define RSC_VERSION_CODE_FR "Version" +#define RSC_COUNTERS_CODE_FR "Compteurs" +#define RSC_GENERAL_CTRS_CODE_FR "G""\xa9""n""\xa9""raux" +#define RSC_FIXED_CTRS_CODE_FR "Fixes" +#define RSC_PERF_MON_UNIT_BIT_CODE_FR "bits" +#define RSC_PERF_MON_CPPC_CODE_FR \ + "Contr""\xb4""le collaboratif des performances du processeur" + +#define RSC_PERF_MON_PCT_CODE_FR RSC_PERF_MON_PCT_CODE_EN +#define RSC_PERF_MON_PSS_CODE_FR RSC_PERF_MON_PSS_CODE_EN +#define RSC_PERF_MON_PPC_CODE_FR RSC_PERF_MON_PPC_CODE_EN +#define RSC_PERF_MON_CPC_CODE_FR RSC_PERF_MON_CPC_CODE_EN +#define RSC_PERF_MON_CST_CODE_FR RSC_PERF_MON_CST_CODE_EN +#define RSC_PERF_MON_HWP_CODE_FR "Hardware-Controlled Performance States" +#define RSC_PERF_MON_CORE_CSTATE_CODE_FR "Core C-States" +#define RSC_PERF_MON_CSTATE_BAR_CODE_FR "Adresse Base C-States" + +#define RSC_PERF_MON_MONITOR_MWAIT_CODE_FR "MONITOR/MWAIT" +#define RSC_PERF_MON_MWAIT_IDX_CSTATE_CODE_FR "State index" +#define RSC_PERF_MON_MWAIT_SUB_CSTATE_CODE_FR "Sub C-State" + +#define RSC_PERF_MON_CORE_CYCLE_CODE_FR "Core Cycles Counter" +#define RSC_PERF_MON_INST_RET_CODE_FR "Instructions Counter" + +#define RSC_PERF_MON_PMC_COMM_CODE_FR RSC_PERF_MON_PMC_COMM_CODE_EN + +#define RSC_PERF_MON_CPPC_COMM_CODE_FR " Micrologiciel " + +#define RSC_POWER_THERMAL_TITLE_CODE_FR " Puissance, courant et thermique " +#define RSC_POWER_THERMAL_CPPC_CODE_FR "CPPC Pr""\xa9""f""\xa9""rence " \ + "\xa9""nerg""\xa9""tique" + +#define RSC_POWER_THERMAL_TJMAX_CODE_FR "Temp""\xa9""rature Offset:Jonction" +#define RSC_POWER_THERMAL_DTS_CODE_FR "Capteur thermique num""\xa9""rique" +#define RSC_POWER_THERMAL_PLN_CODE_FR "Notification de puissance" +#define RSC_POWER_THERMAL_PTM_CODE_FR "Gestion thermique du Package" +#define RSC_POWER_THERMAL_UNITS_CODE_FR "Unit""\xa9""s" +#define RSC_POWER_THERMAL_POWER_CODE_FR "Puissance" +#define RSC_POWER_THERMAL_ENERGY_CODE_FR "\x89""nergie" +#define RSC_POWER_THERMAL_WINDOW_CODE_FR "Intervalle" +#define RSC_POWER_THERMAL_WATT_CODE_FR "watt" +#define RSC_POWER_THERMAL_JOULE_CODE_FR "joule" +#define RSC_POWER_THERMAL_SECOND_CODE_FR "seconde" +#define RSC_POWER_THERMAL_TDP_CODE_FR "Dissipation thermique" +#define RSC_POWER_THERMAL_MIN_CODE_FR "Puissance minimale" +#define RSC_POWER_THERMAL_MAX_CODE_FR "Puissance maximale" +#define RSC_POWER_THERMAL_TPL_CODE_FR "Limite de puissance" +#define RSC_POWER_THERMAL_TW_CODE_FR "Fen""\xaa""tre temporelle" +#define RSC_POWER_THERMAL_EDC_CODE_FR "Limite de courant sup""\xa9""rieure" +#define RSC_POWER_THERMAL_TDC_CODE_FR "Limite de courant sup""\xa9""rieure" +#define RSC_POWER_THERMAL_POINT_CODE_FR "Seuil thermique" + +#define RSC_THERMAL_POINT_THRESHOLD_CODE_FR "Seuil" +#define RSC_THERMAL_POINT_LIMIT_CODE_FR "Limite" +#define RSC_THERMAL_POINT_THRESHOLD_1_CODE_FR "Seuil DTS #1" +#define RSC_THERMAL_POINT_THRESHOLD_2_CODE_FR "Seuil DTS #2" +#define RSC_THERMAL_POINT_TRIP_LIMIT_CODE_FR "D""\xa9""clencheur du" \ + " moniteur thermique" + +#define RSC_THERMAL_POINT_HTC_LIMIT_CODE_FR "Limite de temp" \ + "\xa9""rature HTC" + +#define RSC_THERMAL_POINT_HTC_HYST_CODE_FR "Hyst""\xa9""r""\xa9""sis" \ + " de temp""\xa9""rature HTC" + +#define RSC_THERMAL_OFFSET_TITLE_CODE_FR " Offset thermique " + +#define RSC_KERNEL_TITLE_CODE_FR " Noyau " +#define RSC_KERNEL_TOTAL_RAM_CODE_FR "RAM totale" +#define RSC_KERNEL_SHARED_RAM_CODE_FR "RAM partag""\xa9""e" +#define RSC_KERNEL_FREE_RAM_CODE_FR "RAM libre" +#define RSC_KERNEL_BUFFER_RAM_CODE_FR "RAM Tampon" +#define RSC_KERNEL_TOTAL_HIGH_CODE_FR "M""\xa9""moire haute totale" +#define RSC_KERNEL_FREE_HIGH_CODE_FR "M""\xa9""moire haute libre" +#define RSC_KERNEL_GOVERNOR_CODE_FR "Gouverneur" +#define RSC_KERNEL_FREQ_DRIVER_CODE_FR "Pilote CPU-Freq" +#define RSC_KERNEL_IDLE_DRIVER_CODE_FR "Pilote CPU-Idle" +#define RSC_KERNEL_CLOCK_SOURCE_CODE_FR "Source Horloge" +#define RSC_KERNEL_RELEASE_CODE_FR "\x89""dition" +#define RSC_KERNEL_VERSION_CODE_FR "Version" +#define RSC_KERNEL_MACHINE_CODE_FR "Machine" +#define RSC_KERNEL_MEMORY_CODE_FR "M""\xa9""moire" +#define RSC_KERNEL_STATE_CODE_FR "\x89""tat" +#define RSC_KERNEL_POWER_CODE_FR "Puissance" +#define RSC_KERNEL_LATENCY_CODE_FR "Latence" +#define RSC_KERNEL_RESIDENCY_CODE_FR "P""\xa9""riode" +#define RSC_KERNEL_LIMIT_CODE_FR "Limite Idle" + +#define RSC_TOPOLOGY_TITLE_CODE_FR " Topologie " + +#define RSC_MEM_CTRL_TITLE_CODE_FR " Contr""\xb4""leur M""\xa9""moire " +#define RSC_MEM_CTRL_SUBSECT1_0_CODE_FR "Contr" +#define RSC_MEM_CTRL_SUBSECT1_1_CODE_FR "\xb4""leur" +#define RSC_MEM_CTRL_SUBSECT1_2_CODE_FR " #%-3u" +#define RSC_MEM_CTRL_SINGLE_CHA_0_CODE_FR "Simpl" +#define RSC_MEM_CTRL_SINGLE_CHA_1_CODE_FR "e Can" +#define RSC_MEM_CTRL_SINGLE_CHA_2_CODE_FR "al " +#define RSC_MEM_CTRL_DUAL_CHA_0_CODE_FR " Doub" +#define RSC_MEM_CTRL_DUAL_CHA_1_CODE_FR "le Ca" +#define RSC_MEM_CTRL_DUAL_CHA_2_CODE_FR "nal " +#define RSC_MEM_CTRL_TRIPLE_CHA_0_CODE_FR "Tripl" +#define RSC_MEM_CTRL_TRIPLE_CHA_1_CODE_FR "e Can" +#define RSC_MEM_CTRL_TRIPLE_CHA_2_CODE_FR "al " +#define RSC_MEM_CTRL_QUAD_CHA_0_CODE_FR " Quat" +#define RSC_MEM_CTRL_QUAD_CHA_1_CODE_FR "re Ca" +#define RSC_MEM_CTRL_QUAD_CHA_2_CODE_FR "naux " +#define RSC_MEM_CTRL_SIX_CHA_0_CODE_FR " Six" +#define RSC_MEM_CTRL_SIX_CHA_1_CODE_FR " Cana" +#define RSC_MEM_CTRL_SIX_CHA_2_CODE_FR "ux " +#define RSC_MEM_CTRL_EIGHT_CHA_0_CODE_FR "Huit " +#define RSC_MEM_CTRL_EIGHT_CHA_1_CODE_FR "Canau" +#define RSC_MEM_CTRL_EIGHT_CHA_2_CODE_FR "x " +#define RSC_MEM_CTRL_DISABLED_0_CODE_FR " D" +#define RSC_MEM_CTRL_DISABLED_1_CODE_FR "\xa9""sact" +#define RSC_MEM_CTRL_DISABLED_2_CODE_FR "iv""\xa9"" " +#define RSC_MEM_CTRL_BUS_RATE_0_CODE_FR " D""\xa9""bi" +#define RSC_MEM_CTRL_BUS_RATE_1_CODE_FR "t Bus" +#define RSC_MEM_CTRL_BUS_SPEED_0_CODE_FR "Trans" +#define RSC_MEM_CTRL_BUS_SPEED_1_CODE_FR "fert " +#define RSC_MEM_CTRL_RAM_STD_0_CODE_FR " " +#define RSC_MEM_CTRL_RAM_STD_1_CODE_FR " " +#define RSC_MEM_CTRL_RAM_STD_2_CODE_FR " LP" +#define RSC_MEM_CTRL_RAM_STD_3_CODE_FR " REG " +#define RSC_MEM_CTRL_DRAM_DDR2_0_CODE_FR "DDR2 " +#define RSC_MEM_CTRL_DRAM_DDR3_0_CODE_FR "DDR3 " +#define RSC_MEM_CTRL_DRAM_DDR4_0_CODE_FR "DDR4 " +#define RSC_MEM_CTRL_DRAM_DDR5_0_CODE_FR "DDR5 " +#define RSC_MEM_CTRL_DRAM_SPEED_0_CODE_FR "DRAM " +#define RSC_MEM_CTRL_DRAM_SPEED_1_CODE_FR "Fr""\xa9""q." +#define RSC_MEM_CTRL_SUBSECT2_0_CODE_FR " G""\xa9""om" +#define RSC_MEM_CTRL_SUBSECT2_1_CODE_FR "\xa9""trie" +#define RSC_MEM_CTRL_SUBSECT2_2_CODE_FR " DIMM" +#define RSC_MEM_CTRL_SUBSECT2_3_CODE_FR " du c" +#define RSC_MEM_CTRL_SUBSECT2_4_CODE_FR "anal " +#define RSC_MEM_CTRL_SUBSECT2_5_CODE_FR "#%-2u " +#define RSC_MEM_CTRL_DIMM_SLOT_CODE_FR " Slot" +#define RSC_MEM_CTRL_DIMM_BANK_CODE_FR " Banq" +#define RSC_MEM_CTRL_DIMM_RANK_CODE_FR " Rang" +#define RSC_MEM_CTRL_DIMM_ROW_CODE_FR "Ligne" +#define RSC_MEM_CTRL_DIMM_COLUMN0_CODE_FR " Col" +#define RSC_MEM_CTRL_DIMM_COLUMN1_CODE_FR "onne " +#define RSC_MEM_CTRL_DIMM_SIZE_0_CODE_FR "Taill" +#define RSC_MEM_CTRL_DIMM_SIZE_1_CODE_FR "e M""\xa9""m" +#define RSC_MEM_CTRL_DIMM_SIZE_2_CODE_FR "oire " +#define RSC_MEM_CTRL_DIMM_SIZE_3_CODE_FR "(MB) " + +#define RSC_DDR3_CL_COMM_CODE_FR RSC_DDR3_CL_COMM_CODE_EN +#define RSC_DDR3_RCD_COMM_CODE_FR RSC_DDR3_RCD_COMM_CODE_EN +#define RSC_DDR3_RP_COMM_CODE_FR RSC_DDR3_RP_COMM_CODE_EN +#define RSC_DDR3_RAS_COMM_CODE_FR RSC_DDR3_RAS_COMM_CODE_EN +#define RSC_DDR3_RRD_COMM_CODE_FR RSC_DDR3_RRD_COMM_CODE_EN +#define RSC_DDR3_RFC_COMM_CODE_FR RSC_DDR3_RFC_COMM_CODE_EN +#define RSC_DDR3_WR_COMM_CODE_FR RSC_DDR3_WR_COMM_CODE_EN +#define RSC_DDR3_RTP_COMM_CODE_FR RSC_DDR3_RTP_COMM_CODE_EN +#define RSC_DDR3_WTP_COMM_CODE_FR RSC_DDR3_WTP_COMM_CODE_EN +#define RSC_DDR3_FAW_COMM_CODE_FR RSC_DDR3_FAW_COMM_CODE_EN +#define RSC_DDR3_B2B_COMM_CODE_FR RSC_DDR3_B2B_COMM_CODE_EN +#define RSC_DDR3_CWL_COMM_CODE_FR RSC_DDR3_CWL_COMM_CODE_EN +#define RSC_DDR3_CMD_COMM_CODE_FR RSC_DDR3_CMD_COMM_CODE_EN +#define RSC_DDR3_REFI_COMM_CODE_FR RSC_DDR3_REFI_COMM_CODE_EN +#define RSC_DDR3_DDWRTRD_COMM_CODE_FR RSC_DDR3_DDWRTRD_COMM_CODE_EN +#define RSC_DDR3_DRWRTRD_COMM_CODE_FR RSC_DDR3_DRWRTRD_COMM_CODE_EN +#define RSC_DDR3_SRWRTRD_COMM_CODE_FR RSC_DDR3_SRWRTRD_COMM_CODE_EN +#define RSC_DDR3_DDRDTWR_COMM_CODE_FR RSC_DDR3_DDRDTWR_COMM_CODE_EN +#define RSC_DDR3_DRRDTWR_COMM_CODE_FR RSC_DDR3_DRRDTWR_COMM_CODE_EN +#define RSC_DDR3_SRRDTWR_COMM_CODE_FR RSC_DDR3_SRRDTWR_COMM_CODE_EN +#define RSC_DDR3_DDRDTRD_COMM_CODE_FR RSC_DDR3_DDRDTRD_COMM_CODE_EN +#define RSC_DDR3_DRRDTRD_COMM_CODE_FR RSC_DDR3_DRRDTRD_COMM_CODE_EN +#define RSC_DDR3_SRRDTRD_COMM_CODE_FR RSC_DDR3_SRRDTRD_COMM_CODE_EN +#define RSC_DDR3_DDWRTWR_COMM_CODE_FR RSC_DDR3_DDWRTWR_COMM_CODE_EN +#define RSC_DDR3_DRWRTWR_COMM_CODE_FR RSC_DDR3_DRWRTWR_COMM_CODE_EN +#define RSC_DDR3_SRWRTWR_COMM_CODE_FR RSC_DDR3_SRWRTWR_COMM_CODE_EN +#define RSC_DDR3_XS_COMM_CODE_FR RSC_DDR3_XS_COMM_CODE_EN +#define RSC_DDR3_XP_COMM_CODE_FR RSC_DDR3_XP_COMM_CODE_EN +#define RSC_DDR3_CKE_COMM_CODE_FR RSC_DDR3_CKE_COMM_CODE_EN +#define RSC_DDR3_ECC_COMM_CODE_FR RSC_DDR3_ECC_COMM_CODE_EN + +#define RSC_DDR4_RCD_R_COMM_CODE_FR RSC_DDR4_RCD_R_COMM_CODE_EN +#define RSC_DDR4_RCD_W_COMM_CODE_FR RSC_DDR4_RCD_W_COMM_CODE_EN +#define RSC_DDR4_RDRD_SCL_COMM_CODE_FR RSC_DDR4_RDRD_SCL_COMM_CODE_EN +#define RSC_DDR4_RDRD_SC_COMM_CODE_FR RSC_DDR4_RDRD_SC_COMM_CODE_EN +#define RSC_DDR4_RDRD_SD_COMM_CODE_FR RSC_DDR4_RDRD_SD_COMM_CODE_EN +#define RSC_DDR4_RDRD_DD_COMM_CODE_FR RSC_DDR4_RDRD_DD_COMM_CODE_EN +#define RSC_DDR4_RDWR_SCL_COMM_CODE_FR RSC_DDR4_RDWR_SCL_COMM_CODE_EN +#define RSC_DDR4_RDWR_SC_COMM_CODE_FR RSC_DDR4_RDWR_SC_COMM_CODE_EN +#define RSC_DDR4_RDWR_SD_COMM_CODE_FR RSC_DDR4_RDWR_SD_COMM_CODE_EN +#define RSC_DDR4_RDWR_DD_COMM_CODE_FR RSC_DDR4_RDWR_DD_COMM_CODE_EN +#define RSC_DDR4_WRRD_SCL_COMM_CODE_FR RSC_DDR4_WRRD_SCL_COMM_CODE_EN +#define RSC_DDR4_WRRD_SC_COMM_CODE_FR RSC_DDR4_WRRD_SC_COMM_CODE_EN +#define RSC_DDR4_WRRD_SD_COMM_CODE_FR RSC_DDR4_WRRD_SD_COMM_CODE_EN +#define RSC_DDR4_WRRD_DD_COMM_CODE_FR RSC_DDR4_WRRD_DD_COMM_CODE_EN +#define RSC_DDR4_WRWR_SCL_COMM_CODE_FR RSC_DDR4_WRWR_SCL_COMM_CODE_EN +#define RSC_DDR4_WRWR_SC_COMM_CODE_FR RSC_DDR4_WRWR_SC_COMM_CODE_EN +#define RSC_DDR4_WRWR_SD_COMM_CODE_FR RSC_DDR4_WRWR_SD_COMM_CODE_EN +#define RSC_DDR4_WRWR_DD_COMM_CODE_FR RSC_DDR4_WRWR_DD_COMM_CODE_EN +#define RSC_DDR4_RRD_S_COMM_CODE_FR RSC_DDR4_RRD_S_COMM_CODE_EN +#define RSC_DDR4_RRD_L_COMM_CODE_FR RSC_DDR4_RRD_L_COMM_CODE_EN +#define RSC_DDR4_CPDED_COMM_CODE_FR RSC_DDR4_CPDED_COMM_CODE_EN +#define RSC_DDR4_GEAR_COMM_CODE_FR RSC_DDR4_GEAR_COMM_CODE_EN + +#define RSC_DDR4_ZEN_RC_COMM_CODE_FR RSC_DDR4_ZEN_RC_COMM_CODE_EN +#define RSC_DDR4_ZEN_WTR_S_COMM_CODE_FR RSC_DDR4_ZEN_WTR_S_COMM_CODE_EN +#define RSC_DDR4_ZEN_WTR_L_COMM_CODE_FR RSC_DDR4_ZEN_WTR_L_COMM_CODE_EN +#define RSC_DDR4_ZEN_RDRD_SCL_COMM_CODE_FR RSC_DDR4_ZEN_RDRD_SCL_COMM_CODE_EN +#define RSC_DDR4_ZEN_WRWR_SCL_COMM_CODE_FR RSC_DDR4_ZEN_WRWR_SCL_COMM_CODE_EN +#define RSC_DDR4_ZEN_RTP_COMM_CODE_FR RSC_DDR4_ZEN_RTP_COMM_CODE_EN +#define RSC_DDR4_ZEN_RDWR_COMM_CODE_FR RSC_DDR4_ZEN_RDWR_COMM_CODE_EN +#define RSC_DDR4_ZEN_WRRD_COMM_CODE_FR RSC_DDR4_ZEN_WRRD_COMM_CODE_EN +#define RSC_DDR4_ZEN_WRWR_SC_COMM_CODE_FR RSC_DDR4_ZEN_WRWR_SC_COMM_CODE_EN +#define RSC_DDR4_ZEN_WRWR_SD_COMM_CODE_FR RSC_DDR4_ZEN_WRWR_SD_COMM_CODE_EN +#define RSC_DDR4_ZEN_WRWR_DD_COMM_CODE_FR RSC_DDR4_ZEN_WRWR_DD_COMM_CODE_EN +#define RSC_DDR4_ZEN_RDRD_SC_COMM_CODE_FR RSC_DDR4_ZEN_RDRD_SC_COMM_CODE_EN +#define RSC_DDR4_ZEN_RDRD_SD_COMM_CODE_FR RSC_DDR4_ZEN_RDRD_SD_COMM_CODE_EN +#define RSC_DDR4_ZEN_RDRD_DD_COMM_CODE_FR RSC_DDR4_ZEN_RDRD_DD_COMM_CODE_EN +#define RSC_DDR4_ZEN_RTR_DLR_COMM_CODE_FR RSC_DDR4_ZEN_RTR_DLR_COMM_CODE_EN +#define RSC_DDR4_ZEN_WTW_DLR_COMM_CODE_FR RSC_DDR4_ZEN_WTW_DLR_COMM_CODE_EN +#define RSC_DDR4_ZEN_WTR_DLR_COMM_CODE_FR RSC_DDR4_ZEN_WTR_DLR_COMM_CODE_EN +#define RSC_DDR4_ZEN_RRD_DLR_COMM_CODE_FR RSC_DDR4_ZEN_RRD_DLR_COMM_CODE_EN +#define RSC_DDR4_ZEN_RFC1_COMM_CODE_FR RSC_DDR4_ZEN_RFC1_COMM_CODE_EN +#define RSC_DDR4_ZEN_RFC2_COMM_CODE_FR RSC_DDR4_ZEN_RFC2_COMM_CODE_EN +#define RSC_DDR4_ZEN_RFC4_COMM_CODE_FR RSC_DDR4_ZEN_RFC4_COMM_CODE_EN +#define RSC_DDR4_ZEN_RCPB_COMM_CODE_FR RSC_DDR4_ZEN_RCPB_COMM_CODE_EN +#define RSC_DDR4_ZEN_RPPB_COMM_CODE_FR RSC_DDR4_ZEN_RPPB_COMM_CODE_EN +#define RSC_DDR4_ZEN_BGS_COMM_CODE_FR RSC_DDR4_ZEN_BGS_COMM_CODE_EN +#define RSC_DDR4_ZEN_BGS_ALT_COMM_CODE_FR RSC_DDR4_ZEN_BGS_ALT_COMM_CODE_EN +#define RSC_DDR4_ZEN_BAN_COMM_CODE_FR RSC_DDR4_ZEN_BAN_COMM_CODE_EN +#define RSC_DDR4_ZEN_RCPAGE_COMM_CODE_FR RSC_DDR4_ZEN_RCPAGE_COMM_CODE_EN +#define RSC_DDR4_ZEN_GDM_COMM_CODE_FR RSC_DDR4_ZEN_GDM_COMM_CODE_EN +#define RSC_DDR4_ZEN_MRD_COMM_CODE_FR RSC_DDR4_ZEN_MRD_COMM_CODE_EN +#define RSC_DDR4_ZEN_MOD_COMM_CODE_FR RSC_DDR4_ZEN_MOD_COMM_CODE_EN +#define RSC_DDR4_ZEN_MRD_PDA_COMM_CODE_FR RSC_DDR4_ZEN_MRD_PDA_COMM_CODE_EN +#define RSC_DDR4_ZEN_MOD_PDA_COMM_CODE_FR RSC_DDR4_ZEN_MOD_PDA_COMM_CODE_EN +#define RSC_DDR4_ZEN_WRMPR_COMM_CODE_FR RSC_DDR4_ZEN_WRMPR_COMM_CODE_EN +#define RSC_DDR4_ZEN_STAG_COMM_CODE_FR RSC_DDR4_ZEN_STAG_COMM_CODE_EN +#define RSC_DDR4_ZEN_PDM_COMM_CODE_FR RSC_DDR4_ZEN_PDM_COMM_CODE_EN +#define RSC_DDR4_ZEN_RDDATA_COMM_CODE_FR RSC_DDR4_ZEN_RDDATA_COMM_CODE_EN +#define RSC_DDR4_ZEN_PHYWRD_COMM_CODE_FR RSC_DDR4_ZEN_PHYWRD_COMM_CODE_EN +#define RSC_DDR4_ZEN_PHYWRL_COMM_CODE_FR RSC_DDR4_ZEN_PHYWRL_COMM_CODE_EN +#define RSC_DDR4_ZEN_PHYRDL_COMM_CODE_FR RSC_DDR4_ZEN_PHYRDL_COMM_CODE_EN +#define RSC_DDR5_ZEN_RFC_SB_COMM_CODE_FR RSC_DDR5_ZEN_RFC_SB_COMM_CODE_EN + +#define RSC_TASKS_SORTBY_STATE_CODE_FR " ""\x89""tat " +#define RSC_TASKS_SORTBY_RTIME_CODE_FR " RunTime " +#define RSC_TASKS_SORTBY_UTIME_CODE_FR " UserTime " +#define RSC_TASKS_SORTBY_STIME_CODE_FR " SysTime " +#define RSC_TASKS_SORTBY_PID_CODE_FR " PID " +#define RSC_TASKS_SORTBY_COMM_CODE_FR " Commande " + +#define RSC_MENU_ITEM_MENU_CODE_FR " [F2] Menu " +#define RSC_MENU_ITEM_VIEW_CODE_FR " [F3] Vue " +#define RSC_MENU_ITEM_WINDOW_CODE_FR " [F4] Fen""\xaa""tre " +#define RSC_MENU_ITEM_SPACER_CODE_FR RSC_MENU_ITEM_SPACER_CODE_EN +#define RSC_MENU_ITEM_DATE_TIME_CODE_FR RSC_MENU_ITEM_DATE_TIME_CODE_EN +#define RSC_MENU_ITEM_FULL_TIME_CODE_FR RSC_MENU_ITEM_FULL_TIME_CODE_EN +#define RSC_MENU_ITEM_TINY_TIME_CODE_FR RSC_MENU_ITEM_TINY_TIME_CODE_EN +#define RSC_MENU_ITEM_SETTINGS_CODE_FR " R""\xa9""glages [s] " +#define RSC_MENU_ITEM_SMBIOS_CODE_FR " Infos SMBIOS [B] " +#define RSC_MENU_ITEM_KERNEL_CODE_FR " Infos Noyau [k] " +#define RSC_MENU_ITEM_HOTPLUG_CODE_FR " HotPlug CPU [#] " +#define RSC_MENU_ITEM_TOOLS_CODE_FR " Outils [O] " +#define RSC_MENU_ITEM_THEME_CODE_FR " Th""\xa8""me [E] " +#define RSC_MENU_ITEM_ABOUT_CODE_FR " ""\x80""-propos [a] " +#define RSC_MENU_ITEM_HELP_CODE_FR " Aide [h] " +#define RSC_MENU_ITEM_KEYS_CODE_FR " Raccourcis [F1] " +#define RSC_MENU_ITEM_LANG_CODE_FR " Langues [L] " +#define RSC_MENU_ITEM_QUIT_CODE_FR " Quitter [Ctrl]+[x] " +#define RSC_MENU_ITEM_DASHBOARD_CODE_FR " Tableau de bord [d] " +#define RSC_MENU_ITEM_FREQUENCY_CODE_FR " Fr""\xa9""quence [f] " +#define RSC_MENU_ITEM_INST_CYCLES_CODE_FR " Cycles Instruction [i] " +#define RSC_MENU_ITEM_CORE_CYCLES_CODE_FR " Cycles des Coeurs [c] " +#define RSC_MENU_ITEM_IDLE_STATES_CODE_FR " ""\x89""tats de sommeil [l] " +#define RSC_MENU_ITEM_PKG_CYCLES_CODE_FR " Cycles du Package [g] " +#define RSC_MENU_ITEM_TASKS_MON_CODE_FR " Suivi des t""\xa2""ches [x] " +#define RSC_MENU_ITEM_SYS_INTER_CODE_FR " Interruptions [q] " +#define RSC_MENU_ITEM_SENSORS_CODE_FR " Capteurs [C] " +#define RSC_MENU_ITEM_VOLTAGE_CODE_FR " Voltage [V] " +#define RSC_MENU_ITEM_POWER_CODE_FR " Puissance [W] " +#define RSC_MENU_ITEM_SLICE_CTRS_CODE_FR " Compteurs tranche [T] " +#define RSC_MENU_ITEM_CUSTOM_CODE_FR " Vue personnalis""\xa9""e [y] " +#define RSC_MENU_ITEM_PROCESSOR_CODE_FR " Processeur [p] " +#define RSC_MENU_ITEM_TOPOLOGY_CODE_FR " Topologie [m] " +#define RSC_MENU_ITEM_FEATURES_CODE_FR " Caract""\xa9""ristiques [e] " +#define RSC_MENU_ITEM_ISA_EXT_CODE_FR " Jeu Instructions [I] " +#define RSC_MENU_ITEM_TECH_CODE_FR " Technologies [t] " +#define RSC_MENU_ITEM_PERF_MON_CODE_FR " Gestion de Perf. [o] " +#define RSC_MENU_ITEM_PERF_CAPS_CODE_FR " Capacit""\xa9""s de Perf. [z] " +#define RSC_MENU_ITEM_POW_THERM_CODE_FR " Puissance-Therm. [w] " +#define RSC_MENU_ITEM_SYS_REGS_CODE_FR " Registres Syst""\xa8""me [R] " +#define RSC_MENU_ITEM_MEM_CTRL_CODE_FR " Contr""\xb4""leur " \ + "M""\xa9""moire [M] " + +#define RSC_MENU_ITEM_EVENTS_CODE_FR " ""\x89""v""\xa8" \ + "nements CPU [H] " + +#define RSC_SETTINGS_TITLE_CODE_FR " R""\xa9""glages " + +#define RSC_SETTINGS_DAEMON_CODE_FR " Acc""\xa8""s d""\xa9""mon" \ + " " + +#define RSC_SETTINGS_INTERVAL_CODE_FR " Intervalle(ms) < > " +#define RSC_SETTINGS_SYS_TICK_CODE_FR " Sys. Tick(ms) " +#define RSC_SETTINGS_POLL_WAIT_CODE_FR " Poll Wait(ms) " +#define RSC_SETTINGS_RING_WAIT_CODE_FR " Ring Wait(ms) " +#define RSC_SETTINGS_CHILD_WAIT_CODE_FR " Child Wait(ms) " +#define RSC_SETTINGS_SLICE_WAIT_CODE_FR " Slice Wait(ms) " +#define RSC_SETTINGS_RECORDER_CODE_FR " Dur""\xa9""e(sec) < > " +#define RSC_SETTINGS_AUTO_CLOCK_CODE_FR " Auto Clock < > " + +#define RSC_SETTINGS_EXPERIMENTAL_CODE_FR " Exp""\xa9""rimental" \ + " < > " + +#define RSC_SETTINGS_CPU_HOTPLUG_CODE_FR " Hot-Plug CPU [ ] " +#define RSC_SETTINGS_PCI_ENABLED_CODE_FR " Activation PCI [ ] " +#define RSC_SETTINGS_NMI_REGISTERED_CODE_FR " Activation NMI < > " +#define RSC_SETTINGS_CPUIDLE_REGISTERED_CODE_FR \ + " Pilote CPU-IDLE < > " + +#define RSC_SETTINGS_CPUFREQ_REGISTERED_CODE_FR \ + " Pilote CPU-FREQ < > " + +#define RSC_SETTINGS_GOVERNOR_REGISTERED_CODE_FR \ + " Gouverneur CPU-FREQ < > " + +#define RSC_SETTINGS_CS_REGISTERED_CODE_FR " Source d'Horloge < > " +#define RSC_SETTINGS_THERMAL_SCOPE_CODE_FR " Capteur thermique < > " +#define RSC_SETTINGS_VOLTAGE_SCOPE_CODE_FR " Capteur de tension < > " +#define RSC_SETTINGS_POWER_SCOPE_CODE_FR " Capteur de puissance < > " +#define RSC_SETTINGS_IDLE_ROUTE_CODE_FR " Route CPU-IDLE " + +#define RSC_SETTINGS_ROUTE_TITLE_CODE_FR "Route" + +#define RSC_HELP_TITLE_CODE_FR " Aide " +#define RSC_HELP_KEY_ESCAPE_CODE_FR " [""\x89""chap] " +#define RSC_HELP_KEY_SHIFT_TAB_CODE_FR " [Maj]+[Tab] " +#define RSC_HELP_KEY_TAB_CODE_FR " [Tab] " +#define RSC_HELP_KEY_UP_CODE_FR " [Haut] " +#define RSC_HELP_KEY_LEFT_RIGHT_CODE_FR " [Gauche] [Droite]" +#define RSC_HELP_KEY_DOWN_CODE_FR " [Bas] " +#define RSC_HELP_KEY_END_CODE_FR " [Fin] " +#define RSC_HELP_KEY_HOME_CODE_FR " [D""\xa9""but] " +#define RSC_HELP_KEY_ENTER_CODE_FR " [Entr""\xa9""e] " +#define RSC_HELP_KEY_PAGE_UP_CODE_FR " [Page-Pr""\xa9""c] " +#define RSC_HELP_KEY_PAGE_DOWN_CODE_FR " [Page-Suiv] " +#define RSC_HELP_KEY_MINUS_CODE_FR " [Moins] " +#define RSC_HELP_KEY_PLUS_CODE_FR " [Plus] " +#define RSC_HELP_KEY_MENU_CODE_FR " [F2] " +#define RSC_HELP_MENU_CODE_FR " Menu " +#define RSC_HELP_CLOSE_WINDOW_CODE_FR " Fermer fen""\xaa""tre " +#define RSC_HELP_PREV_WINDOW_CODE_FR " Fen""\xaa""tre arri""\xa8""re " +#define RSC_HELP_NEXT_WINDOW_CODE_FR " Fen""\xaa""tre suivante " +#define RSC_HELP_KEY_SHIFT_GR1_CODE_FR " [s] " +#define RSC_HELP_KEY_SHIFT_GR2_CODE_FR " [a|q] [x] [d] +" +#define RSC_HELP_MOVE_WINDOW_CODE_FR " [Maj] D""\xa9""placer " +#define RSC_HELP_KEY_ALT_GR3_CODE_FR " +" +#define RSC_HELP_SIZE_WINDOW_CODE_FR " [Alt] Retailler " +#define RSC_HELP_MOVE_SELECT_CODE_FR " D""\xa9""placer curseur " +#define RSC_HELP_LAST_CELL_CODE_FR " Derni""\xa8""re cellule " +#define RSC_HELP_FIRST_CELL_CODE_FR " Premi""\xa8""re cellule " +#define RSC_HELP_TRIGGER_SELECT_CODE_FR " Ex""\xa9""cuter cellule " +#define RSC_HELP_PREV_PAGE_CODE_FR " Page pr""\xa9""c""\xa9""dente " +#define RSC_HELP_NEXT_PAGE_CODE_FR " Page suivante " +#define RSC_HELP_SCROLL_DOWN_CODE_FR " D""\xa9""cro""\xae""tre CPU " +#define RSC_HELP_SCROLL_UP_CODE_FR " Accro""\xae""tre CPU " + +#define RSC_ADV_HELP_TITLE_CODE_FR " Raccourcis " + +#define RSC_ADV_HELP_SECT_FREQ_CODE_FR " Vue Fr""\xa9""quence:" \ + " " + +#define RSC_ADV_HELP_ITEM_AVG_CODE_FR " % Moyennes | " \ + "\x89""tats-Package " + +#define RSC_ADV_HELP_SECT_TASK_CODE_FR " Vue Suivi des t""\xa2""ches:" \ + " " + +#define RSC_ADV_HELP_ITEM_ORDER_CODE_FR " b Crit""\xa8""re de tri" \ + " des t""\xa2""ches " + +#define RSC_ADV_HELP_ITEM_RST_CODE_FR " N Effacer la t""\xa2""che " \ + "\xa0"" suivre " + +#define RSC_ADV_HELP_ITEM_SEL_CODE_FR " n Choisir la t""\xa2""che " \ + "\xa0"" suivre " + +#define RSC_ADV_HELP_ITEM_REV_CODE_FR " r Inverser le tri des " \ + "t""\xa2""ches " + +#define RSC_ADV_HELP_ITEM_HIDE_CODE_FR " v Afficher | Cacher valeurs " +#define RSC_ADV_HELP_SECT_ANY_CODE_FR " Vue quelconque: " + +#define RSC_ADV_HELP_ITEM_POWER_CODE_FR " $ ""\x89""nergie " \ + "en Joule | Watt " + +#define RSC_ADV_HELP_ITEM_TOP_CODE_FR " . Fr""\xa9""quence Top" \ + " ou Usage " + +#define RSC_ADV_HELP_ITEM_UPD_CODE_FR " * Rafra""\xae""chir " \ + "CoreFreq " + +#define RSC_ADV_HELP_ITEM_START_CODE_FR " { D""\xa9""marrer "\ + "CoreFreq " + +#define RSC_ADV_HELP_ITEM_STOP_CODE_FR " } Arr""\xaa""ter "\ + "CoreFreq " + +#define RSC_ADV_HELP_ITEM_TOOLS_CODE_FR " F10 Arr""\xaa""ter " \ + "les outils " + +#define RSC_ADV_HELP_ITEM_GO_UP_CODE_FR " Haut Prec " \ + "D""\xa9""filement " + +#define RSC_ADV_HELP_ITEM_GO_DW_CODE_FR " Bas Suiv CPU " +#define RSC_ADV_HELP_ITEM_TERMINAL_CODE_FR \ + " Terminal: " + +#define RSC_ADV_HELP_ITEM_PRT_SCR_CODE_FR \ + " [Ctrl]+[p] Screenshot " + +#define RSC_ADV_HELP_ITEM_REC_SCR_CODE_FR \ + " [Alt]+[p] Screencast " + +#define RSC_ADV_HELP_ITEM_FAHR_CELS_CODE_FR \ + " F Fahrenheit ou Celsius " + +#define RSC_ADV_HELP_ITEM_SYSGATE_CODE_FR \ + " G Basculer l'""\xa9""tat"\ + " SysGate " + +#define RSC_ADV_HELP_ITEM_PROC_EVENT_CODE_FR \ + " H G""\xa9""rer Alertes" \ + " Processeur " + +#define RSC_ADV_HELP_ITEM_SECRET_CODE_FR \ + " Y Basculer donn""\xa9""es" \ + " secr""\xa8""tes " + +#define RSC_TURBO_CLOCK_TITLE_CODE_FR " Fr""\xa9""q. Turbo %1dC " +#define RSC_RATIO_CLOCK_TITLE_CODE_FR " %s Ratio Fr""\xa9""q. " +#define RSC_UNCORE_CLOCK_TITLE_CODE_FR " %s Uncore Fr""\xa9""q. " + +#define RSC_SELECT_CPU_TITLE_CODE_FR " CPU Pkg Core Thread Planifier " + +#define RSC_SELECT_FREQ_TITLE_CODE_FR " CPU Pkg Core Thread " \ + " Fr""\xa9""quence Ratio " + +#define RSC_BOX_DISABLE_COND0_CODE_FR " D""\xa9""sactiver " \ + " " + +#define RSC_BOX_DISABLE_COND1_CODE_FR " < D""\xa9""sactiver >" \ + " " + +#define RSC_BOX_ENABLE_COND0_CODE_FR " Activer " +#define RSC_BOX_ENABLE_COND1_CODE_FR " < Activer > " + +#define RSC_BOX_INTERVAL_TITLE_CODE_FR "Intervalle" +#define RSC_BOX_AUTO_CLOCK_TITLE_CODE_FR " Auto Clock " +#define RSC_BOX_MODE_TITLE_CODE_FR " Exp""\xa9""rimental " + +#define RSC_BOX_MODE_DESC_CODE_FR " CoreFreq mode " \ + "op""\xa9""rationnel " + +#define RSC_BOX_HWP_DESC_CODE_FR " Contr""\xb4""le Mat""\xa9""riel" \ + " de la Performance" + +#define RSC_BOX_FMW_DESC_CODE_FR " Contr""\xb4""le Firmware" \ + " de la Performance" + +#define RSC_BOX_NOMINAL_MODE_COND0_CODE_FR \ + " Fonctionnement" \ + " nominal " + +#define RSC_BOX_NOMINAL_MODE_COND1_CODE_FR \ + " < Fonctionnement" \ + " nominal > " + +#define RSC_BOX_EXPERIMENT_MODE_COND0_CODE_FR \ + " Fonctionnement " \ + "exp""\xa9""rimental " + +#define RSC_BOX_EXPERIMENT_MODE_COND1_CODE_FR \ + " < Fonctionnement " \ + "exp""\xa9""rimental > " + +#define RSC_BOX_INTERRUPT_TITLE_CODE_FR " Interruptions NMI " +#define RSC_BOX_CPU_IDLE_TITLE_CODE_FR " Pilote CPU-IDLE " +#define RSC_BOX_CPU_FREQ_TITLE_CODE_FR " Pilote CPU-FREQ " +#define RSC_BOX_GOVERNOR_TITLE_CODE_FR " Gouverneur CPU-FREQ " +#define RSC_BOX_CLOCK_SOURCE_TITLE_CODE_FR " Source d'Horloge " + +#define RSC_BOX_OPS_REGISTER_COND0_CODE_FR " " \ + "Enregistrer " + +#define RSC_BOX_OPS_REGISTER_COND1_CODE_FR " < " \ + "Enregistrer > " + +#define RSC_BOX_OPS_UNREGISTER_COND0_CODE_FR " D""\xa9""s" \ + "enregistrer " + +#define RSC_BOX_OPS_UNREGISTER_COND1_CODE_FR " < D""\xa9""s" \ + "enregistrer > " + +#define RSC_BOX_EVENT_TITLE_CODE_FR RSC_BOX_EVENT_TITLE_CODE_EN + +#define RSC_BOX_EVENT_SPACE_CODE_FR " " +#define RSC_BOX_EVENT_THERMAL_SENSOR_CODE_FR " Capteur therm. " +#define RSC_BOX_EVENT_PROCHOT_STS_CODE_FR " PROCHOT " +#define RSC_BOX_EVENT_CRITICAL_TEMP_CODE_FR " Temp. critique " +#define RSC_BOX_EVENT_THOLD1_STS_CODE_FR " Seuil1 therm. " +#define RSC_BOX_EVENT_THOLD2_STS_CODE_FR " Seuil2 therm. " +#define RSC_BOX_EVENT_POWER_LIMIT_CODE_FR " Puissance max. " +#define RSC_BOX_EVENT_CURRENT_LIMIT_CODE_FR " Courant limit""\xa9"" " +#define RSC_BOX_EVENT_CROSS_DOM_LIMIT_CODE_FR " Interdomaine " +#define RSC_BOX_EVENT_RESIDENCY_CODE_FR " R""\xa9""sidence " +#define RSC_BOX_EVENT_AVG_THERMAL_CODE_FR " Moy. thermique " +#define RSC_BOX_EVENT_VR_THERMAL_CODE_FR " VR thermique " +#define RSC_BOX_EVENT_VR_TDC_CODE_FR " VR TDC " +#define RSC_BOX_EVENT_POWER_PL1_CODE_FR " PL1 du Package " +#define RSC_BOX_EVENT_POWER_PL2_CODE_FR " PL2 du Package " +#define RSC_BOX_EVENT_ELECTRICAL_CODE_FR " EDP ""\xa9""lectrique " +#define RSC_BOX_EVENT_INEFFICIENCY_CODE_FR " Inefficacit""\xa9"" " +#define RSC_BOX_EVENT_MAX_TURBO_CODE_FR " Turbo Max " +#define RSC_BOX_EVENT_TURBO_ATTEN_CODE_FR " Turbo Atten. " +#define RSC_BOX_EVENT_THERMAL_TVB_CODE_FR " TVB thermique " +#define RSC_BOX_EVENT_ALL_OF_THEM_CODE_FR "< Tout effacer >" + +#define RSC_BOX_DUTY_CYCLE_RESERVED_CODE_FR " " \ + "R""\xa9""serv""\xa9"" " + +#define RSC_BOX_POWER_POLICY_TITLE_CODE_FR " R""\xa8""gle " \ + "\xa9""nerg""\xa9""tique " + +#define RSC_BOX_POWER_POLICY_LOW_CODE_FR " 0 BAS " +#define RSC_BOX_POWER_POLICY_HIGH_CODE_FR " 15 HAUT " + +#define RSC_BOX_HWP_POLICY_MIN_CODE_FR " Minimale:0 " +#define RSC_BOX_HWP_POLICY_020_CODE_FR " 32 " +#define RSC_BOX_HWP_POLICY_040_CODE_FR " 64 " +#define RSC_BOX_HWP_POLICY_060_CODE_FR " 96 " +#define RSC_BOX_HWP_POLICY_MED_CODE_FR " Moyenne:128 " +#define RSC_BOX_HWP_POLICY_0A0_CODE_FR " 160 " +#define RSC_BOX_HWP_POLICY_PWR_CODE_FR " Puissance:192 " +#define RSC_BOX_HWP_POLICY_0E0_CODE_FR " 224 " +#define RSC_BOX_HWP_POLICY_MAX_CODE_FR " Maximale:255 " + +#define RSC_BOX_TOOLS_TITLE_CODE_FR " Outils " +#define RSC_BOX_TOOLS_STOP_BURN_CODE_FR " ARR""\x8a""TER " +#define RSC_BOX_TOOLS_ATOMIC_BURN_CODE_FR " Stress Atomic " +#define RSC_BOX_TOOLS_CRC32_BURN_CODE_FR " Calcul CRC32 " +#define RSC_BOX_TOOLS_CONIC_BURN_CODE_FR " < Calcul Conique > " +#define RSC_BOX_TOOLS_RANDOM_CPU_CODE_FR " Turbo CPU al""\xa9""atoire " +#define RSC_BOX_TOOLS_ROUND_ROBIN_CPU_CODE_FR \ + " Turbo CPU circulaire " +#define RSC_BOX_TOOLS_USER_CPU_CODE_FR " Turbo < Choisir CPU > " +#define RSC_BOX_TOOLS_MONTE_CARLO_CODE_FR " Calcul PI / Monte Carlo " + +#define RSC_BOX_CONIC_TITLE_CODE_FR " Variations Coniques " +#define RSC_BOX_CONIC_ITEM_1_CODE_FR " Ellipso""\xaf""de " + +#define RSC_BOX_CONIC_ITEM_2_CODE_FR " Hyperbolo""\xaf""de "\ + "\xa0"" une nappe " + +#define RSC_BOX_CONIC_ITEM_3_CODE_FR " Hyperbolo""\xaf""de "\ + "\xa0"" deux nappes " + +#define RSC_BOX_CONIC_ITEM_4_CODE_FR " Cylindre elliptique " +#define RSC_BOX_CONIC_ITEM_5_CODE_FR " Cylindre hyperbolique " +#define RSC_BOX_CONIC_ITEM_6_CODE_FR " Deux plans parall""\xa8""les " + +#define RSC_BOX_LANG_TITLE_CODE_FR " Langues " +#define RSC_BOX_LANG_ENGLISH_CODE_FR " Anglais " +#define RSC_BOX_LANG_FRENCH_CODE_FR " Fran""\xa7""ais " + +#define RSC_BOX_THEME_TITLE_CODE_FR " Th""\xa8""mes " + +#define RSC_BOX_SCOPE_THERMAL_TITLE_CODE_FR " Temp""\xa9""rature " +#define RSC_BOX_SCOPE_VOLTAGE_TITLE_CODE_FR " Tension " +#define RSC_BOX_SCOPE_POWER_TITLE_CODE_FR " Puissance " +#define RSC_BOX_SCOPE_NONE_CODE_FR " Sans " +#define RSC_BOX_SCOPE_THREAD_CODE_FR " Thread " +#define RSC_BOX_SCOPE_CORE_CODE_FR " Coeur " +#define RSC_BOX_SCOPE_PACKAGE_CODE_FR " Package " + +#define RSC_BOX_CFG_TDP_TITLE_CODE_FR " Config TDP " +#define RSC_BOX_CFG_TDP_DESC_CODE_FR " Limite BIOS " +#define RSC_BOX_CFG_TDP_LVL0_CODE_FR " Niveau 0 " +#define RSC_BOX_CFG_TDP_LVL1_CODE_FR " Niveau 1 " +#define RSC_BOX_CFG_TDP_LVL2_CODE_FR " Niveau 2 " + +#define RSC_BOX_TDP_PKG_TITLE_CODE_FR " TDP Package " +#define RSC_BOX_TDP_CORES_TITLE_CODE_FR " TDP Core " +#define RSC_BOX_TDP_UNCORE_TITLE_CODE_FR " TDP Uncore " +#define RSC_BOX_TDP_RAM_TITLE_CODE_FR " TDP DRAM " +#define RSC_BOX_TDP_PLATFORM_TITLE_CODE_FR " TDP Plateforme " +#define RSC_BOX_PL1_DESC_CODE_FR " Limite de puissance PL1 " +#define RSC_BOX_PL2_DESC_CODE_FR " Limite de puissance PL2 " + +#define RSC_BOX_TDC_TITLE_CODE_FR " TDC du courant " +#define RSC_BOX_TDC_DESC_CODE_FR " Limite de courant TDC " + +#define RSC_ERROR_CMD_SYNTAX_CODE_FR \ + "CoreFreq." \ + " Copyright (C) 2015-2024 CYRIL COURTIAT\n\n" \ + "Usage:\t%s [-Option ] [-Commande ]\n"\ + "\n Options de l'interface\n" \ + "\t-Oa\tFréquence absolue\n" \ + "\t-Op\tAfficher États-Package\n" \ + "\t-Ok\tUnité mémoire en kilo-octet\n" \ + "\t-Om\tUnité mémoire en méga-octet\n" \ + "\t-Og\tUnité mémoire en giga-octet\n" \ + "\t-OW\tChanger d'unité d'Énergie\n" \ + "\t-OF\tTempérature en Fahrenheit\n" \ + "\t-OJ #\tNuméro d'index de chaîne SMBIOS\n" \ + "\t-OE #\tNuméro d'index du thème de couleurs\n" \ + "\t-OY\tAfficher les données secrètes\n" \ + "\n Options de commande\n" \ + "\t-t \tAfficher Top (par défault); en option, la ue:\n"\ + "\t\t{\tfrequency, instructions, core, idle, package, tasks,\n"\ + "\t\t\tinterrupts, sensors, voltage, power, slices, custom }\n"\ + "\t-d\tAfficher le tableau de bord\n" \ + "\t-C <#>\tMoniteur des Capteurs\n" \ + "\t-V <#>\tMoniteur de Voltage\n" \ + "\t-W <#>\tMoniteur de Puissance\n" \ + "\t-g <#>\tMoniteur du Package\n" \ + "\t-c <#>\tMoniteur des Compteurs\n" \ + "\t-i <#>\tMoniteur des Instructions\n" \ + "\t-s\tImprimer les Informations du système\n" \ + "\t-j\tImprimer les Informations (format json)\n" \ + "\t-z\tImprimer les Capacités de performances\n" \ + "\t-M\tImprimer le Controlleur mémoire\n" \ + "\t-R\tImprimer les Registres du système\n" \ + "\t-m\tImprimer la Topologie\n" \ + "\t-B\tImprimer SMBIOS\n" \ + "\t-k\tImprimer le Kernel\n" \ + "\t-n\tNouvelle ligne\n" \ + "\t-h\tAfficher ce message\n" \ + "\t-v\tAfficher le numéro de version\n" \ + "\nCode d'exécution:\n" \ + "\t%u\tSUCCESS\t\tExécution réussie\n" \ + "\t%u\tCMD_SYNTAX\tErreur de syntaxe de la commande\n" \ + "\t%u\tSHM_FILE\tErreur du fichier de la mémoire partagée\n"\ + "\t%u\tSHM_MMAP\tErreur de mappage de la mémoire partagée\n"\ + "\t%u\tPERM_ERR\tExécution non autorisée\n" \ + "\t%u\tMEM_ERR\t\tErreur de fonctionnement de la mémoire\n"\ + "\t%u\tEXEC_ERR\tErreur d'exécution générale\n" \ + "\t%u\tSYS_CALL\tErreur d'appel système\n" \ + "\nSignaler toutes anomalies à labs[at]cyring.fr\n" + +#define RSC_ERROR_SHARED_MEM_CODE_FR \ + "Erreur code %d de connexion au démon.\n%s: '%s' @ ligne %d\n" + +#define RSC_ERROR_SYS_CALL_CODE_FR "Erreur Système code %d\n%s @ ligne %d\n" + +#define RSC_ERROR_UNIMPLEMENTED_CODE_FR "Fonctionnalit""\xa9" \ + " non implement""\xa9""e" + +#define RSC_ERROR_EXPERIMENTAL_CODE_FR "Le mode exp""\xa9""rimental est requis" + +#define RSC_ERROR_TURBO_PREREQ_CODE_FR "D""\xa9""sactiver Turbo Boost |" \ + " Core Performance Boost" + +#define RSC_ERROR_UNCORE_PREREQ_CODE_FR "Pr""\xa9""requis Uncore" \ + " non valid""\xa9""s" + +#define RSC_ERROR_PSTATE_NOT_FOUND_CODE_FR "Ce P-State de Fr\xa9quence " \ + "n'a pas \xa9t\xa9 trouv\xa9" + +#define RSC_ERROR_CLOCKSOURCE_CODE_FR "Source d'horloge incompatible" + +#define RSC_BOX_IDLE_LIMIT_TITLE_CODE_FR " Limite CPU-Idle " + +#define RSC_BOX_RECORDER_TITLE_CODE_FR " Dur""\xa9""e " + +#define RSC_SMBIOS_TITLE_CODE_FR " SMBIOS " + +#define RSC_MECH_CLRBHB_CODE_FR "Effacement de l'historique de branche" + +#define RSC_MECH_SSBD_CODE_FR \ + "Contournement Sp""\xa9""culatif de Magasin d""\xa9""sactiv""\xa9" + +#define RSC_MECH_SSBS_CODE_FR \ + "Contournement Sp""\xa9""culatif de Magasin Prot""\xa9""g""\xa9" + +#define RSC_CREATE_SELECT_AUTO_TURBO_CODE_FR " %3s Processeur " \ + " %s %c%4u %c " + +#define RSC_CREATE_SELECT_FREQ_TURBO_CODE_FR " %3s Processeur " \ + "%7.2f MHz %c%4u %c " + +#define RSC_CREATE_SELECT_FREQ_TGT_CODE_FR " TGT Processeur " +#define RSC_CREATE_SELECT_FREQ_HWP_TGT_CODE_FR " HWP-TGT Processeur " +#define RSC_CREATE_SELECT_FREQ_HWP_MAX_CODE_FR " HWP-MAX Processeur " +#define RSC_CREATE_SELECT_FREQ_HWP_MIN_CODE_FR " HWP-MIN Processeur " +#define RSC_CREATE_SELECT_FREQ_MAX_CODE_FR " MAX Processeur " +#define RSC_CREATE_SELECT_FREQ_MIN_CODE_FR " MIN Processeur " + +#define RSC_CREATE_SELECT_FREQ_OFFLINE_CODE_FR " %03u " \ + " Off " + +#define RSC_POPUP_DRIVER_TITLE_CODE_FR " Message du Pilote " + +#define RSC_EXIT_TITLE_CODE_FR " Sortie " + +#define RSC_EXIT_HEADER_CODE_FR " Les services suivants sont toujours " \ + "en cours d'ex""\xa9""cution " + +#define RSC_EXIT_CONFIRM_CODE_FR " < Confirmer > " \ + " " + +#define RSC_EXIT_FOOTER_CODE_FR " " \ + "[""\x89""chap] pour annuler " + +#define RSC_CREATE_SETTINGS_COND0_CODE_FR RSC_CREATE_SETTINGS_COND0_CODE_EN +#define RSC_CREATE_SETTINGS_COND1_CODE_FR RSC_CREATE_SETTINGS_COND1_CODE_EN + +#define RSC_CREATE_ADV_HELP_COND0_CODE_FR RSC_CREATE_ADV_HELP_COND0_CODE_EN +#define RSC_CREATE_ADV_HELP_COND1_CODE_FR RSC_CREATE_ADV_HELP_BLANK_CODE_EN diff --git a/aarch64/corefreq-cli-rsc-theme-dflt.h b/aarch64/corefreq-cli-rsc-theme-dflt.h new file mode 100644 index 00000000..11513cfd --- /dev/null +++ b/aarch64/corefreq-cli-rsc-theme-dflt.h @@ -0,0 +1,1944 @@ +/* + * CoreFreq + * Copyright (C) 2015-2024 CYRIL COURTIAT + * Licenses: GPL2 + */ + +#define RSC_THEME_DFLT_CODE /* 72 chars */ \ +" Default theme by CyrIng. Since 2015; updated May 2022 " + +#define RSC_UI_THM_DFLT_ATTR \ +{ \ + [UI_FUSE_RESET_LAYER] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_FUSE_PAINT_LAYER] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_MAKE_TITLE_UNFOCUS] = { \ + .fg = BLACK, .un = 0, .bg = BLUE, .bf = 1 \ + }, \ + [UI_MAKE_TITLE_FOCUS] = { \ + .fg = WHITE, .un = 0, .bg = CYAN, .bf = 1 \ + }, \ + [UI_MAKE_BORDER_UNFOCUS] = { \ + .fg = BLACK, .un = 0, .bg = BLUE, .bf = 1 \ + }, \ + [UI_MAKE_BORDER_FOCUS] = { \ + .fg = WHITE, .un = 0, .bg = BLUE, .bf = 1 \ + }, \ + [UI_MAKE_SELECT_UNFOCUS] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_MAKE_SELECT_FOCUS] = { \ + .fg = BLACK, .un = 0, .bg = CYAN, .bf = 0 \ + }, \ + [UI_MAKE_PRINT_UNFOCUS] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_MAKE_PRINT_FOCUS] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_MAKE_PRINT_DROP] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_LCD_RESET] = { \ + .fg = CYAN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_CLOCK_LOW] = { \ + .fg = GREEN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_CLOCK_MEDIUM] = { \ + .fg = YELLOW, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_CLOCK_HIGH] = { \ + .fg = RED, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_COUNTER_LOW] = { \ + .fg = RED, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_COUNTER_MEDIUM] = { \ + .fg = YELLOW, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_COUNTER_HIGH] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_LOAD_LOW] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_LOAD_MEDIUM] = { \ + .fg = YELLOW, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_LOAD_HIGH] = { \ + .fg = RED, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_IDLE_LOW] = { \ + .fg = YELLOW, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_IDLE_MEDIUM] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_IDLE_HIGH] = { \ + .fg = GREEN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_SYSTEM_LOW] = { \ + .fg = RED, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_SYSTEM_MEDIUM] = { \ + .fg = YELLOW, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_SYSTEM_HIGH] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_UBENCH] = { \ + .fg = MAGENTA, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_HEADER_PROC_BRAND] = { \ + .fg = CYAN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_HEADER_PROC_BRAND_FILL] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_HEADER_ARCHITECTURE] = { \ + .fg = CYAN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_HEADER_ARCH_FILL] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_HEADER_BCLK_FILL] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_RULER_INSTRUCTIONS] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_LAYOUT_RULER_CYCLES] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_LAYOUT_RULER_CSTATES] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_LAYOUT_RULER_INTERRUPTS] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_LAYOUT_RULER_PACKAGE] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_LAYOUT_RULER_TASKS_FILL] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_LAYOUT_RULER_TASKS_TRACKING] = { \ + .fg = CYAN, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_LAYOUT_RULER_ENERGY] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_LAYOUT_RULER_SLICE] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_LAYOUT_RULER_CUSTOM] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_LAYOUT_FOOTER_ENABLE_0] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_ENABLE_1] = { \ + .fg = GREEN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_ENABLE_2] = { \ + .fg = BLUE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_TSC_NONE] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_TSC_VAR] = { \ + .fg = BLUE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_TSC_INV] = { \ + .fg = GREEN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_TM_0] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_TM_1] = { \ + .fg = BLUE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_TM_2] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_TM_3] = { \ + .fg = GREEN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_FILL] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_GATE] = { \ + .fg = CYAN, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_LAYOUT_FOOTER_SPACE] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_LAYOUT_FOOTER_LEFT_BRACE] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_RIGHT_BRACE] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_KERNEL_VERSION] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_UNMAP_GATE] = { \ + .fg = RED, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_LAYOUT_FOOTER_DMI_STRING] = { \ + .fg = BLUE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_BCLK_TO_VIEW] = { \ + .fg = YELLOW, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_ROW_CPU_OFFLINE] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_LAYOUT_RULER_LOAD_TAB_DIM] = { \ + .fg = CYAN, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_LAYOUT_RULER_LOAD_TAB_BRIGHT] = { \ + .fg = CYAN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_ILLUMINATES_CPU_OFF] = { \ + .fg = BLUE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_ILLUMINATES_CPU_ON] = { \ + .fg = CYAN, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_ILLUMINATES_CPU_SP] = { \ + .fg = CYAN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_ILLUMINATES_CPU_SP_HYBRID] = { \ + .fg = GREEN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_DRAW_FREQUENCY_LOAD_CLEAR] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_DRAW_FREQUENCY_LOAD_LOW] = { \ + .fg = GREEN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_DRAW_FREQUENCY_LOAD_MEDIUM] = { \ + .fg = YELLOW, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_DRAW_FREQUENCY_LOAD_HIGH] = { \ + .fg = RED, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_DRAW_ALTMONITOR_TASKS_CLEAR] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_DRAW_ALTMONITOR_TASKS_SPACE] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_DRAW_MONITOR_FREQUENCY_NOMINAL] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_DRAW_MONITOR_FREQUENCY_LOW] = { \ + .fg = BLUE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_DRAW_MONITOR_FREQUENCY_HIGH] = { \ + .fg = YELLOW, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_DRAW_MONITOR_FREQUENCY_HOT] = { \ + .fg = RED, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_CARD_CORE_OFFLINE] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_CARD_RAM_2DIGITS] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_CARD_RAM_3DIGITS] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_DRAW_CARD_CORE_NOMINAL] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_DRAW_CARD_CORE_LOW] = { \ + .fg = BLUE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_DRAW_CARD_CORE_MEDIUM] = { \ + .fg = YELLOW, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_DRAW_CARD_CORE_HIGH] = { \ + .fg = RED, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_DRAW_CARD_TASK_FILL] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_WIN_MENU_UNSELECT] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_WIN_MENU_SELECT] = { \ + .fg = BLACK, .un = 0, .bg = CYAN, .bf = 0 \ + }, \ + [UI_WIN_MENU_TITLE_UNFOCUS] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_WIN_MENU_TITLE_FOCUS] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_WIN_MENU_ERASE_CELL] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_WIN_SORT_BY_FIELD_TITLE] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_WIN_TRACKING_PARENT_PROCESS] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_WIN_TRACKING_CHILD_PROCESS] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_WIN_TRACKING_THIS_PARENT] = { \ + .fg = BLUE, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_WIN_TRACKING_THIS_CHILD] = { \ + .fg = BLUE, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_WIN_TRACKING_COUNTERS] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_WIN_TRACKING_TITLE] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_WIN_HOT_PLUG_CPU_TITLE] = { \ + .fg = WHITE, .un = 0, .bg = BLUE, .bf = 1 \ + }, \ + [UI_WIN_SELECT_IDLE_RESET] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_WIN_SELECT_IDLE_POLL] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_WIN_SELECT_IDLE_CURRENT] = { \ + .fg = CYAN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_WIN_POPUP_MSG_ITEM] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_WIN_POPUP_MSG_SELECT_UNFOCUS] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_WIN_POPUP_MSG_SELECT_FOCUS] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_WIN_POPUP_MSG_BORDER_UNFOCUS] = { \ + .fg = WHITE, .un = 0, .bg = RED, .bf = 0 \ + }, \ + [UI_WIN_POPUP_MSG_BORDER_FOCUS] = { \ + .fg = WHITE, .un = 0, .bg = RED, .bf = 1 \ + }, \ + [UI_WIN_POPUP_MSG_TITLE_UNFOCUS] = { \ + .fg = WHITE, .un = 0, .bg = RED, .bf = 0 \ + }, \ + [UI_WIN_POPUP_MSG_TITLE_FOCUS] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_WIN_EXIT_ISSUE_RECORDER] = { \ + .fg = CYAN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_WIN_EXIT_ISSUE_STRESS] = { \ + .fg = CYAN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_WIN_EXIT_ISSUE_OS_CPU_IDLE] = { \ + .fg = CYAN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_WIN_EXIT_HEADER] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_WIN_EXIT_BLANK] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_WIN_EXIT_CONFIRM] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_WIN_EXIT_FOOTER] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_BOX_DISABLE_STATE] = { \ + .fg = CYAN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_BOX_ENABLE_STATE] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_BOX_BLANK] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_BOX_DESC] = { \ + .fg = CYAN, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_BOX_INTERVAL] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_BOX_EXPERIMENTAL_NOMINAL] = { \ + .fg = CYAN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_BOX_EXPERIMENTAL_WARNING] = { \ + .fg = RED, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_DROP_IDLE_ROUTE] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_BOX_TOOLS_STOP] = { \ + .fg = RED, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_WHEEL_CURRENT] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_WHEEL_SELECT] = { \ + .fg = CYAN, .un = 1, .bg = BLACK, .bf = 1 \ + }, \ + [UI_WHEEL_LIST] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + } \ +} + +#define RSC_VOID_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_RUN_STATE_COLOR_THM_DFLT_ATTR \ +{ \ + HRK,HRK,HRK,HRK,HRK,HRK,HRK,HRK, \ + HRK,HRK,HRK,HRK,HRK,HRK,HRK,HRK, \ + HRK,HRK,HRK,HRK,HRK,HRK,HRK,HRK, \ + HRK,HRK,HRK,HRK,HRK,HRK,HRK,HRK, \ + HRK,HRK,HRK,HRK,HRK,HRK,HRK,HRK \ +} + +#define RSC_UNINT_STATE_COLOR_THM_DFLT_ATTR \ +{ \ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK, \ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK, \ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK, \ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK, \ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK \ +} + +#define RSC_ZOMBIE_STATE_COLOR_THM_DFLT_ATTR \ +{ \ + LRW,LRW,LRW,LRW,LRW,LRW,LRW,LRW, \ + LRW,LRW,LRW,LRW,LRW,LRW,LRW,LRW, \ + LRW,LRW,LRW,LRW,LRW,LRW,LRW,LRW, \ + LRW,LRW,LRW,LRW,LRW,LRW,LRW,LRW, \ + LRW,LRW,LRW,LRW,LRW,LRW,LRW,LRW \ +} + +#define RSC_SLEEP_STATE_COLOR_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_WAIT_STATE_COLOR_THM_DFLT_ATTR \ +{ \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK \ +} + +#define RSC_OTHER_STATE_COLOR_THM_DFLT_ATTR \ +{ \ + LGK,LGK,LGK,LGK,LGK,LGK,LGK,LGK, \ + LGK,LGK,LGK,LGK,LGK,LGK,LGK,LGK, \ + LGK,LGK,LGK,LGK,LGK,LGK,LGK,LGK, \ + LGK,LGK,LGK,LGK,LGK,LGK,LGK,LGK, \ + LGK,LGK,LGK,LGK,LGK,LGK,LGK,LGK \ +} + +#define RSC_TRACKER_STATE_COLOR_THM_DFLT_ATTR \ +{ \ + LKC,LKC,LKC,LKC,LKC,LKC,LKC,LKC, \ + LKC,LKC,LKC,LKC,LKC,LKC,LKC,LKC, \ + LKC,LKC,LKC,LKC,LKC,LKC,LKC,LKC, \ + LKC,LKC,LKC,LKC,LKC,LKC,LKC,LKC, \ + LKC,LKC,LKC,LKC,LKC,LKC,LKC,LKC \ +} + +#define RSC_LAYOUT_HEADER_PROC_THM_DFLT_ATTR \ +{ \ + HRK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK \ +} + +#define RSC_LAYOUT_HEADER_CPU_THM_DFLT_ATTR \ +{ \ + HDK,HWK,HWK,HWK,HWK,HDK,HWK,HWK,HWK,HWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_HEADER_ARCH_THM_DFLT_ATTR \ +{ \ + HCK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK \ +} + +#define RSC_LAYOUT_HEADER_CACHE_L1_THM_DFLT_ATTR \ +{ \ + HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,HWK,HWK,HWK, \ + LWK,LWK,LWK,LWK,HDK,HWK,HWK,HWK,LWK,LWK \ +} + +#define RSC_LAYOUT_HEADER_BCLK_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + HYK,HYK,HYK,HYK,HYK,HDK,HYK,HYK,HYK,HDK,HYK,HYK,HYK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_HEADER_CACHES_THM_DFLT_ATTR \ +{ \ + LWK,LWK,HDK,HWK,HWK,HWK,HWK,HWK,LWK,LWK, \ + LWK,LWK,HDK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_LOAD_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,_HCK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_VAR_LOAD_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_REL_LOAD_THM_DFLT_ATTR \ + RSC_LAYOUT_RULER_VAR_LOAD_THM_DFLT_ATTR + +#define RSC_LAYOUT_RULER_ABS_LOAD_THM_DFLT_ATTR \ + RSC_LAYOUT_RULER_VAR_LOAD_THM_DFLT_ATTR + +#define RSC_LAYOUT_MONITOR_FREQUENCY_THM_DFLT_ATTR \ +{ \ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HDK,HDK,HWK,HWK,HWK,HWK,HWK,HDK,\ + HDK,HWK,HWK,HWK,HWK,HWK,HWK,HDK,HDK,HWK,HWK,HWK,HWK,HWK,HWK,HDK,\ + HDK,HWK,HWK,HWK,HWK,HWK,HWK,HDK,HDK,HWK,HWK,HWK,HWK,HWK,HWK,HDK,\ + HDK,HWK,HWK,HWK,HWK,HWK,HWK,HDK,HDK,HWK,HWK,HWK,HWK,HWK,HWK,HDK,\ + HDK,HDK,HBK,HBK,HBK,HDK,LWK,LWK,LWK,HDK,LYK,LYK,LYK \ +} + +#define RSC_LAYOUT_MONITOR_INST_THM_DFLT_ATTR \ +{ \ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HDK,LWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HDK,LWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HDK,LWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK \ +} + +#define RSC_LAYOUT_MONITOR_COMMON_THM_DFLT_ATTR \ +{ \ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK \ +} + +#define RSC_LAYOUT_MONITOR_TASKS_THM_DFLT_ATTR \ +{ \ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_MONITOR_SLICE_THM_DFLT_ATTR \ +{ \ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HRK,HRK,HRK,\ + HRK,HRK,HRK,HRK,HRK,HRK,HRK,HRK,HRK,HRK,HRK,HRK,HRK,HRK,HRK \ +} + +#define RSC_LAYOUT_CUSTOM_FIELD_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK, \ + HWK,HWK,HWK,LWK, \ + LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK, \ + HWK,HWK,HWK,HWK,HWK,HWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK, \ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK, \ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_FREQUENCY_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_FREQUENCY_AVG_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,_HCK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_FREQUENCY_PKG_THM_DFLT_ATTR \ +{ \ + _HCK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,HDK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_INST_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_CYCLES_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_CSTATES_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_INTERRUPTS_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_PACKAGE_THM_DFLT_ATTR RSC_VOID_THM_DFLT_ATTR + +#define RSC_LAYOUT_PACKAGE_PC_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,HDK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HDK,HDK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK \ +} + +#define RSC_LAYOUT_PACKAGE_PC02_THM_DFLT_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_DFLT_ATTR + +#define RSC_LAYOUT_PACKAGE_PC03_THM_DFLT_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_DFLT_ATTR + +#define RSC_LAYOUT_PACKAGE_PC04_THM_DFLT_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_DFLT_ATTR + +#define RSC_LAYOUT_PACKAGE_PC06_THM_DFLT_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_DFLT_ATTR + +#define RSC_LAYOUT_PACKAGE_PC07_THM_DFLT_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_DFLT_ATTR + +#define RSC_LAYOUT_PACKAGE_PC08_THM_DFLT_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_DFLT_ATTR + +#define RSC_LAYOUT_PACKAGE_PC09_THM_DFLT_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_DFLT_ATTR + +#define RSC_LAYOUT_PACKAGE_PC10_THM_DFLT_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_DFLT_ATTR + +#define RSC_LAYOUT_PACKAGE_MC06_THM_DFLT_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_DFLT_ATTR + +#define RSC_LAYOUT_PACKAGE_CTR0_THM_DFLT_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_DFLT_ATTR + +#define RSC_LAYOUT_PACKAGE_CTR1_THM_DFLT_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_DFLT_ATTR + +#define RSC_LAYOUT_PACKAGE_CTR2_THM_DFLT_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_DFLT_ATTR + +#define RSC_LAYOUT_PACKAGE_CTR3_THM_DFLT_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_DFLT_ATTR + +#define RSC_LAYOUT_PACKAGE_CTR4_THM_DFLT_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_DFLT_ATTR + +#define RSC_LAYOUT_PACKAGE_CTR5_THM_DFLT_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_DFLT_ATTR + +#define RSC_LAYOUT_PACKAGE_CTR6_THM_DFLT_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_DFLT_ATTR + +#define RSC_LAYOUT_PACKAGE_CTR7_THM_DFLT_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_DFLT_ATTR + +#define RSC_LAYOUT_PACKAGE_UNCORE_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,HDK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_PACKAGE_FABRIC_THM_DFLT_ATTR \ + RSC_LAYOUT_PACKAGE_UNCORE_THM_DFLT_ATTR + +#define RSC_LAYOUT_RULER_TASKS_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LDK,LDK,LDK,LDK,LDK,LDK,LDK,LDK,LDK,\ + LDK,LDK,LDK,LDK,LDK,LDK,LDK,LDK,LDK,LDK,LDK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_TASKS_STATE_SORTED_THM_DFLT_ATTR \ +{ \ + HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,_HCK,LWK, \ + LWK,LCK,LCK,LCK,LCK,LCK,HDK,LWK, LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_TASKS_RUNTIME_SORTED_THM_DFLT_ATTR \ +{ \ + HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,_HCK,LWK, \ + LWK,LCK,LCK,LCK,LCK,LCK,LCK,LCK, HDK,LWK,LWK \ +} + +#define RSC_LAYOUT_TASKS_USRTIME_SORTED_THM_DFLT_ATTR \ +{ \ + HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,_HCK,LWK, \ + LWK,LCK,LCK,LCK,LCK,LCK,LCK,LCK, LCK,HDK,LWK \ +} + +#define RSC_LAYOUT_TASKS_SYSTIME_SORTED_THM_DFLT_ATTR \ +{ \ + HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,_HCK,LWK, \ + LWK,LCK,LCK,LCK,LCK,LCK,LCK,LCK, HDK,LWK,LWK \ +} + +#define RSC_LAYOUT_TASKS_PROCESS_SORTED_THM_DFLT_ATTR \ +{ \ + HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,_HCK,LWK, \ + LWK,LCK,LCK,LCK,HDK,LWK,LWK,LWK, LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_TASKS_COMMAND_SORTED_THM_DFLT_ATTR \ +{ \ + HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,_HCK,LWK, \ + LWK,LCK,LCK,LCK,LCK,LCK,LCK,LCK, HDK,LWK,LWK \ +} + +#define RSC_LAYOUT_TASKS_REVERSE_SORT_OFF_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,_HCK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,HDK,LWK \ +} + +#define RSC_LAYOUT_TASKS_REVERSE_SORT_ON_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,_HCK,LWK,LWK,LWK,HDK,LCK,LCK,LCK,HDK,LWK \ +} + +#define RSC_LAYOUT_TASKS_VALUE_SWITCH_THM_DFLT_ATTR \ +{ \ + LWK,_HCK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,HDK,LWK \ +} + +#define RSC_LAYOUT_TASKS_VALUE_OFF_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_TASKS_VALUE_ON_THM_DFLT_ATTR \ +{ \ + LCK,LCK,LCK \ +} + +#define RSC_LAYOUT_TASKS_TRACKING_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,_HCK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK \ +} + +#define RSC_LAYOUT_RULER_SENSORS_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,\ + LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,HDK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,HDK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_PWR_DOMAIN_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,HDK,HWK,HWK,HWK,LWK,HWK,HWK,HWK,HWK,HDK,LWK,HDK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,HWK,HWK,HWK,LWK,HWK,HWK,\ + HWK,HWK,HDK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,\ + HWK,HWK,HWK,LWK,HWK,HWK,HWK,HWK,HDK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,HDK,HWK,HWK,HWK,LWK,HWK,HWK,HWK,HWK,HDK,LWK,HDK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_PWR_UNCORE_THM_DFLT_ATTR \ + RSC_LAYOUT_RULER_PWR_DOMAIN_THM_DFLT_ATTR + +#define RSC_LAYOUT_RULER_PWR_PLATFORM_THM_DFLT_ATTR \ + RSC_LAYOUT_RULER_PWR_DOMAIN_THM_DFLT_ATTR + +#define RSC_LAYOUT_RULER_PWR_SOC_THM_DFLT_ATTR \ + RSC_LAYOUT_RULER_PWR_DOMAIN_THM_DFLT_ATTR + +#define RSC_LAYOUT_RULER_VOLTAGE_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,HDK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,HDK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_VPKG_SOC_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HDK,LWK,HDK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,HDK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_VPKG_SAV_THM_DFLT_ATTR \ + RSC_LAYOUT_RULER_VPKG_SOC_THM_DFLT_ATTR + +#define RSC_LAYOUT_RULER_ENERGY_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_POWER_THM_DFLT_ATTR \ + RSC_LAYOUT_RULER_ENERGY_THM_DFLT_ATTR + +#define RSC_LAYOUT_RULER_SLICE_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_CUSTOM_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_FOOTER_TECH_TSC_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,LWK \ +} + +#define RSC_LAYOUT_FOOTER_VOLT_TEMP_THM_DFLT_ATTR \ +{ \ + LWK,HDK,HWK,HWK,HWK,HWK,HDK,HDK,LWK,HDK,HDK,HDK,HDK,LWK,HDK \ +} + +#define RSC_LAYOUT_FOOTER_SYSTEM_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,HDK,HWK,HWK,HWK,HWK,HWK,HWK,HDK, \ + LWK,LWK,LWK,LWK,LWK,HDK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK, \ + HWK,HDK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK,HDK \ +} + +#define RSC_LAYOUT_CARD_CORE_ONLINE_THM_DFLT_ATTR \ +{ \ + HDK,HDK,LCK,LCK,LCK,HDK,HDK,HDK,HDK,HDK,HDK,HDK \ +} + +#define RSC_LAYOUT_CARD_CORE_ONLINE_COND0_THM_DFLT_ATTR \ + RSC_LAYOUT_CARD_CORE_ONLINE_THM_DFLT_ATTR + +#define RSC_LAYOUT_CARD_CORE_ONLINE_COND1_THM_DFLT_ATTR \ + RSC_LAYOUT_CARD_CORE_ONLINE_THM_DFLT_ATTR + +#define RSC_LAYOUT_CARD_CORE_OFFLINE_THM_DFLT_ATTR \ +{ \ + HDK,HDK,LBK,LBK,LBK,HDK,HDK,LWK,LWK,LWK,HDK,HDK \ +} + +#define RSC_LAYOUT_CARD_CLK_THM_DFLT_ATTR \ +{ \ + HDK,HDK,HWK,HWK,HWK,LWK,HWK,HDK,HDK,HDK,HDK,HDK \ +} + +#define RSC_LAYOUT_CARD_UNCORE_THM_DFLT_ATTR \ +{ \ + HDK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,HDK,LCK,LCK,HDK \ +} + +#define RSC_LAYOUT_CARD_BUS_THM_DFLT_ATTR \ +{ \ + HDK,LWK,LWK,LWK,HWK,HWK,HWK,HWK,HWK,HDK,HDK,HDK \ +} + +#define RSC_LAYOUT_CARD_MC_THM_DFLT_ATTR \ +{ \ + HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK \ +} + +#define RSC_LAYOUT_CARD_LOAD_THM_DFLT_ATTR \ +{ \ + HDK,HDK,HDK,HDK,LWK,LWK,LWK,LWK,LWK,HDK,HDK,HDK \ +} + +#define RSC_LAYOUT_CARD_IDLE_THM_DFLT_ATTR \ +{ \ + HDK,HDK,HDK,HDK,LWK,LWK,LWK,LWK,LWK,HDK,HDK,HDK \ +} + +#define RSC_LAYOUT_CARD_RAM_THM_DFLT_ATTR \ +{ \ + HDK,HWK,HWK,HWK,HWK,HWK,LWK,HDK,HWK,HWK,LDK,HDK \ +} + +#define RSC_LAYOUT_CARD_TASK_THM_DFLT_ATTR \ +{ \ + HDK,LWK,LWK,LWK,LWK,LWK,HWK,HWK,HWK,HWK,HWK,HDK \ +} + +#define RSC_SYSINFO_CPUID_COND0_THM_DFLT_ATTR \ +{ \ + HWK,HWK,HWK,LWK,HDK,LCK,LCK,LCK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_SYSINFO_CPUID_COND1_THM_DFLT_ATTR \ +{ \ + HBK,HBK,HBK,HBK,HBK,LBK,LBK,LBK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_SYSINFO_CPUID_COND2_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_SYSINFO_CPUID_COND3_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,\ + LWK,LWK,LWK,LWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,\ + LWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,LWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_SYSTEM_REGISTERS_COND0_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK \ +} + +#define RSC_SYSTEM_REGISTERS_COND1_THM_DFLT_ATTR \ +{ \ + HBK,HBK,HBK,HBK \ +} + +#define RSC_SYSTEM_REGISTERS_COND2_THM_DFLT_ATTR \ +{ \ + HWK,HWK,HWK,HWK \ +} + +#define RSC_SYSTEM_REGISTERS_COND3_THM_DFLT_ATTR \ +{ \ + HDK,LCK,LCK,LCK \ +} + +#define RSC_SYSTEM_REGISTERS_COND4_THM_DFLT_ATTR \ +{ \ + HDK,LBK,LBK,LBK \ +} + +#define RSC_SYSINFO_PROC_COND0_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_SYSINFO_PROC_COND1_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,HGK,HGK,HGK,HGK,HGK,HGK,HGK,LWK,LWK \ +} + +#define RSC_SYSINFO_PROC_COND2_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK \ +} + +#define RSC_SYSINFO_PROC_COND3_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK \ +} + +#define RSC_SYSINFO_ISA_COND_0_0_THM_DFLT_ATTR \ +{ /* [N] & [N/N] 2*(0|0)+(0<<0) */ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} +#define RSC_SYSINFO_ISA_COND_0_1_THM_DFLT_ATTR \ +{ /* [Y] */ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,HGK,LWK \ +} +#define RSC_SYSINFO_ISA_COND_0_2_THM_DFLT_ATTR \ +{ /* [N/Y] 2*(0|1)+(0<<1) */ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,HGK,LWK \ +} +#define RSC_SYSINFO_ISA_COND_0_3_THM_DFLT_ATTR \ +{ /* [Y/N] 2*(1|0)+(1<<0) */ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,HGK,LWK,LWK,LWK \ +} +#define RSC_SYSINFO_ISA_COND_0_4_THM_DFLT_ATTR \ +{ /* [Y/Y] 2*(1|1)+(1<<1) */ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,HGK,LWK,HGK,LWK \ +} + +#define RSC_SYSINFO_ISA_COND_1_0_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} +#define RSC_SYSINFO_ISA_COND_1_1_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,HGK,LWK,LWK \ +} +#define RSC_SYSINFO_ISA_COND_1_2_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,HGK,LWK,LWK \ +} +#define RSC_SYSINFO_ISA_COND_1_3_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,HGK,LWK,LWK,LWK,LWK \ +} +#define RSC_SYSINFO_ISA_COND_1_4_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,HGK,LWK,HGK,LWK,LWK \ +} + +#define RSC_SYSINFO_FEATURES_COND0_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK \ +} + +#define RSC_SYSINFO_FEATURES_COND1_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,HBK,HBK,HBK,HBK,HBK,HBK,HBK, \ + LWK,LWK \ +} + +#define RSC_SYSINFO_FEATURES_COND2_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LCK,LCK,LCK,LCK,LCK,LCK,LCK, \ + LWK,LWK \ +} + +#define RSC_SYSINFO_FEATURES_COND3_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,HGK,HGK,HGK,HGK,HGK,HGK,HGK, \ + LWK,LWK \ +} + +#define RSC_SYSINFO_FEATURES_COND4_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,HGK,HGK,HGK,HGK,HGK,HGK,HGK,HGK,HGK, \ + LWK,LWK \ +} + +#define RSC_SYSINFO_TECH_COND0_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_SYSINFO_TECH_COND1_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,HGK,HGK,HGK,LWK,LWK \ +} + +#define RSC_SYSINFO_PERFMON_COND0_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK \ +} + +#define RSC_SYSINFO_PERFMON_COND1_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HGK, \ + HGK,HGK,LWK,LWK \ +} + +#define RSC_SYSINFO_PERFMON_COND2_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,HBK,HBK,HBK,HBK,HBK, \ + HBK,HBK,LWK,LWK \ +} + +#define RSC_SYSINFO_PERFMON_COND3_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,HGK,HGK,HGK,HGK,HGK, \ + HGK,HGK,LWK,LWK \ +} + +#define RSC_SYSINFO_PERFMON_COND4_THM_DFLT_ATTR \ +{ \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK \ +} + +#define RSC_SYSINFO_PERFMON_HWP_CAP_COND0_THM_DFLT_ATTR \ +{ \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,\ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,\ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,\ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,\ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK \ +} + +#define RSC_SYSINFO_PERFMON_HWP_CAP_COND1_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LCK,LCK,LCK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,HDK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,HDK,LWK,LWK,LWK,HDK,LWK,LWK,LWK \ +} + +#define RSC_SYSINFO_PWR_THERMAL_COND0_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_SYSINFO_PWR_THERMAL_COND1_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,LWK,LWK \ +} + +#define RSC_SYSINFO_PWR_THERMAL_COND2_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LGK,LGK,LGK,LGK,LGK,LGK,LGK,LWK,LWK \ +} + +#define RSC_SYSINFO_PWR_THERMAL_COND3_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,HGK,HGK,HGK,HGK,HGK,HGK,HGK,LWK,LWK \ +} + +#define RSC_SYSINFO_PWR_THERMAL_COND4_THM_DFLT_ATTR \ +{ \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK \ +} + +#define RSC_SYSINFO_PWR_THERMAL_COND5_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_SYSINFO_PWR_THERMAL_COND6_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HWK, \ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK \ +} + +#define RSC_SYSINFO_KERNEL_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_TOPOLOGY_COND0_THM_DFLT_ATTR \ +{ \ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK \ +} + +#define RSC_TOPOLOGY_COND1_THM_DFLT_ATTR \ +{ \ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK \ +} + +#define RSC_TOPOLOGY_COND2_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_TOPOLOGY_COND3_THM_DFLT_ATTR \ +{ \ + LCK,LCK,LCK,HDK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK \ +} + +#define RSC_TOPOLOGY_COND4_THM_DFLT_ATTR \ +{ \ + LBK,LBK,LBK,HDK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK \ +} + +#define RSC_MEMORY_CONTROLLER_COND0_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_MEMORY_CONTROLLER_COND1_THM_DFLT_ATTR \ +{ \ + HWK,HWK,HWK,HWK,HWK \ +} + +#define RSC_CREATE_MENU_DISABLE_THM_DFLT_ATTR \ +{ \ + HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW, \ + HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW \ +} + +#define RSC_MENU_ITEM_MENU_THM_DFLT_ATTR \ +{ \ + LKW,LKW,LKW,LKW,LKW,HKW,_LKW,_LKW,HKW,LKW,LKW,LKW, \ + LKW,LKW,LKW,LKW,LKW,LKW, LKW, LKW,LKW,LKW,LKW,LKW \ +} + +#define RSC_MENU_ITEM_VIEW_THM_DFLT_ATTR \ +{ \ + LKW,LKW,LKW,LKW,LKW,HKW,_LKW,_LKW,HKW,LKW,LKW,LKW, \ + LKW,LKW,LKW,LKW,LKW,LKW, LKW, LKW,LKW,LKW,LKW,LKW \ +} + +#define RSC_MENU_ITEM_WINDOW_THM_DFLT_ATTR \ +{ \ + LKW,LKW,LKW,LKW,HKW,_LKW,_LKW,HKW,LKW,LKW,LKW,LKW, \ + LKW,LKW,LKW,LKW,LKW, LKW, LKW,LKW,LKW,LKW,LKW,LKW \ +} + +#define RSC_CREATE_MENU_FN_KEY_THM_DFLT_ATTR \ +{ \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW, LKW,LKW,LKW,LKW, \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,_LKW,_LKW,HKW,LKW \ +} + +#define RSC_CREATE_MENU_SHORTKEY_THM_DFLT_ATTR \ +{ \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW, LKW,LKW,LKW, \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,_LKW,HKW,LKW \ +} + +#define RSC_CREATE_MENU_CTRL_KEY_THM_DFLT_ATTR \ +{ \ + LKW,LKW, LKW, LKW, LKW, LKW,LKW,LKW,LKW, LKW,LKW,LKW, \ + LKW,HKW,_LKW,_LKW,_LKW,_LKW,HKW,HKW,HKW,_LKW,HKW,LKW \ +} + +#define RSC_CREATE_SETTINGS_COND0_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,HDK,LWK \ +} + +#define RSC_CREATE_SETTINGS_COND1_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,HGK,HGK,HGK,HDK,LWK \ +} + +#define RSC_CREATE_ADV_HELP_COND0_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_ADV_HELP_COND1_THM_DFLT_ATTR \ +{ \ + LWK,HCK,HCK,HCK,HCK,HCK,HCK,HCK,HCK,HCK, \ + HCK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_HOTPLUG_CPU_ENABLE_THM_DFLT_ATTR \ +{ \ + LWK,LGK,LGK,LGK,LGK,LGK,LGK,LGK,LGK,LGK,LGK,LWK,LDK,LDK,LDK \ +} + +#define RSC_CREATE_HOTPLUG_CPU_DISABLE_THM_DFLT_ATTR \ +{ \ + LWK,LCK,LCK,LCK,LCK,LCK,LCK,LCK,LCK,LCK,LCK,LWK,LDK,LDK,LDK \ +} + +#define RSC_CREATE_HOTPLUG_CPU_ONLINE_THM_DFLT_ATTR \ +{ \ + LCK,LCK,LCK,LCK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_HOTPLUG_CPU_OFFLINE_THM_DFLT_ATTR \ +{ \ + LBK,LBK,LBK,LBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK \ +} + +#define RSC_CREATE_RATIO_CLOCK_COND0_THM_DFLT_ATTR \ +{ \ + LWK,HWK,HWK,HWK,HWK,LWK,HWK,HWK,LWK,HDK,HDK,HDK,LWK,LWK, \ + LWK,LWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_RATIO_CLOCK_COND1_THM_DFLT_ATTR \ +{ \ + LWK,HBK,HBK,HBK,HBK,LBK,HBK,HBK,LWK,HDK,HDK,HDK,LWK,LWK, \ + LWK,LWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_RATIO_CLOCK_COND2_THM_DFLT_ATTR \ +{ \ + LWK,HRK,HRK,HRK,HRK,LRK,HRK,HRK,LWK,HDK,HDK,HDK,LWK,LWK, \ + LWK,LWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_RATIO_CLOCK_COND3_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,HCK,HCK,HCK,HCK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_RATIO_CLOCK_COND4_THM_DFLT_ATTR \ +{ \ + LWK,HWK,HWK,HWK,HWK,LWK,HWK,HWK,LWK,HDK,HDK,HDK,LWK,LWK, \ + LWK,LWK,HCK,HCK,HCK,HCK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_RATIO_CLOCK_COND5_THM_DFLT_ATTR \ +{ \ + LWK,HBK,HBK,HBK,HBK,LBK,HBK,HBK,LWK,HDK,HDK,HDK,LWK,LWK, \ + LWK,LWK,HCK,HCK,HCK,HCK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_RATIO_CLOCK_COND6_THM_DFLT_ATTR \ +{ \ + LWK,HRK,HRK,HRK,HRK,LRK,HRK,HRK,LWK,HDK,HDK,HDK,LWK,LWK, \ + LWK,LWK,HCK,HCK,HCK,HCK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_SELECT_CPU_COND0_THM_DFLT_ATTR \ +{ \ + LBK,LBK,LBK,LBK,LBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK, \ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK, \ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK \ +} + +#define RSC_CREATE_SELECT_CPU_COND1_THM_DFLT_ATTR \ +{ \ + LCK,LCK,LCK,LCK,LCK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LCK,LCK,LCK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_SELECT_CPU_COND2_THM_DFLT_ATTR \ +{ \ + LCK,LCK,LCK,LCK,LCK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,HRK,HRK,HRK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_HOT_EVENT_COND0_THM_DFLT_ATTR \ +{ \ + HDK,HDK,HDK \ +} + +#define RSC_HOT_EVENT_COND1_THM_DFLT_ATTR \ +{ \ + HRK,HRK,HRK \ +} + +#define RSC_HOT_EVENT_COND2_THM_DFLT_ATTR \ +{ \ + {.fg=CYAN,.bg=BLACK,.bf=1,.un=1}, \ + {.fg=CYAN,.bg=BLACK,.bf=0,.un=0}, \ + {.fg=CYAN,.bg=BLACK,.bf=0,.un=0} \ +} + +#define RSC_HOT_EVENT_COND3_THM_DFLT_ATTR \ +{ \ + HWK,HWK,HWK \ +} + +#define RSC_HOT_EVENT_COND4_THM_DFLT_ATTR \ +{ \ + {.fg=CYAN,.bg=MAGENTA,.bf=0,.un=1}, \ + {.fg=CYAN,.bg=MAGENTA,.bf=0,.un=0}, \ + {.fg=CYAN,.bg=MAGENTA,.bf=0,.un=0} \ +} + +#define RSC_BOX_EVENT_COND00_THM_DFLT_ATTR \ +{ \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK \ +} + +#define RSC_BOX_EVENT_COND01_THM_DFLT_ATTR \ +{ \ + LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,HDK \ +} + +#define RSC_BOX_EVENT_COND10_THM_DFLT_ATTR \ +{ \ + LKY,LKY,LKY,LKY,LKY,LKY,LKY,LKY,LKY,LKY,LKY,LKY,LKY,LKY,LKY,LKY,HDK \ +} + +#define RSC_BOX_EVENT_COND11_THM_DFLT_ATTR \ +{ \ + LKY,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LKY,HDK \ +} + +#define RSC_BOX_EVENT_BUTTON_THM_DFLT_ATTR \ +{ \ + LWK,HCK,HCK,HCK,HCK,HCK,HCK,HCK,HCK,HCK,HCK,HCK,HCK,HCK,HCK,HCK,LWK \ +} + +#define RSC_CREATE_RECORDER_THM_DFLT_ATTR \ +{ \ + LWK,LWK,LWK,LWK,HDK,LWK,LWK,HDK,LWK,LWK,LWK,LWK \ +} + +#define RSC_SMBIOS_ITEM_THM_DFLT_ATTR \ +{ \ + HDK,LCK,LCK,HDK,HDK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_SELECT_FREQ_PKG_THM_DFLT_ATTR \ +{ \ + HYK,HYK,HYK,HYK,HYK,HYK,HYK,HYK,HYK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HYK,HYK,HYK,HYK,HYK,HYK,\ + HYK,HYK,HDK,HDK,HDK,LWK,LWK,HYK,HYK,HYK,HYK,HYK,LWK,LWK \ +} + +#define RSC_CREATE_SELECT_FREQ_COND0_THM_DFLT_ATTR \ +{ \ + LCK,LCK,LCK,LCK,LCK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,HDK,HDK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_SELECT_FREQ_COND1_THM_DFLT_ATTR \ +{ \ + LBK,LBK,LBK,LBK,LBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK, \ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK, \ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK, \ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK \ +} + +_Static_assert( __builtin_strlen(RSC_THEME_DFLT_CODE) + == __builtin_strlen(RSC_BOX_THEME_BLANK_CODE), +"Mandatory string length"); diff --git a/aarch64/corefreq-cli-rsc-theme-usr1.h b/aarch64/corefreq-cli-rsc-theme-usr1.h new file mode 100644 index 00000000..f943ccd9 --- /dev/null +++ b/aarch64/corefreq-cli-rsc-theme-usr1.h @@ -0,0 +1,1944 @@ +/* + * CoreFreq + * Copyright (C) 2015-2024 CYRIL COURTIAT + * Licenses: GPL2 + */ + +#define RSC_THEME_USR1_CODE /* 72 chars */ \ +" Strawberry theme by CyrIng. Updated by CyrIng - May 2022 " + +#define RSC_UI_THM_USR1_ATTR \ +{ \ + [UI_FUSE_RESET_LAYER] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_FUSE_PAINT_LAYER] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_MAKE_TITLE_UNFOCUS] = { \ + .fg = BLACK, .un = 0, .bg = MAGENTA, .bf = 1 \ + }, \ + [UI_MAKE_TITLE_FOCUS] = { \ + .fg = MAGENTA, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_MAKE_BORDER_UNFOCUS] = { \ + .fg = BLACK, .un = 0, .bg = MAGENTA, .bf = 1 \ + }, \ + [UI_MAKE_BORDER_FOCUS] = { \ + .fg = WHITE, .un = 0, .bg = MAGENTA, .bf = 1 \ + }, \ + [UI_MAKE_SELECT_UNFOCUS] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_MAKE_SELECT_FOCUS] = { \ + .fg = BLACK, .un = 0, .bg = MAGENTA, .bf = 0 \ + }, \ + [UI_MAKE_PRINT_UNFOCUS] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_MAKE_PRINT_FOCUS] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_MAKE_PRINT_DROP] = { \ + .fg = BLACK, .un = 0, .bg = MAGENTA, .bf = 0 \ + }, \ + [UI_LAYOUT_LCD_RESET] = { \ + .fg = MAGENTA, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_CLOCK_LOW] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_CLOCK_MEDIUM] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_LCD_CLOCK_HIGH] = { \ + .fg = MAGENTA, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_COUNTER_LOW] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_COUNTER_MEDIUM] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_COUNTER_HIGH] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_LCD_LOAD_LOW] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_LOAD_MEDIUM] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_LCD_LOAD_HIGH] = { \ + .fg = MAGENTA, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_IDLE_LOW] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_IDLE_MEDIUM] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_LCD_IDLE_HIGH] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_SYSTEM_LOW] = { \ + .fg = MAGENTA, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_SYSTEM_MEDIUM] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_LCD_SYSTEM_HIGH] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_LAYOUT_UBENCH] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_HEADER_PROC_BRAND] = { \ + .fg = MAGENTA, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_HEADER_PROC_BRAND_FILL] = { \ + .fg = MAGENTA, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_HEADER_ARCHITECTURE] = { \ + .fg = MAGENTA, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_HEADER_ARCH_FILL] = { \ + .fg = MAGENTA, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_HEADER_BCLK_FILL] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_LAYOUT_RULER_INSTRUCTIONS] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_RULER_CYCLES] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_RULER_CSTATES] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_RULER_INTERRUPTS] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_RULER_PACKAGE] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_RULER_TASKS_FILL] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_RULER_TASKS_TRACKING] = { \ + .fg = MAGENTA, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_RULER_ENERGY] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_RULER_SLICE] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_RULER_CUSTOM] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_FOOTER_ENABLE_0] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_ENABLE_1] = { \ + .fg = MAGENTA, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_FOOTER_ENABLE_2] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_FOOTER_TSC_NONE] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_TSC_VAR] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_FOOTER_TSC_INV] = { \ + .fg = MAGENTA, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_FOOTER_TM_0] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_TM_1] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_FOOTER_TM_2] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_FOOTER_TM_3] = { \ + .fg = MAGENTA, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_FOOTER_FILL] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_GATE] = { \ + .fg = MAGENTA, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_FOOTER_SPACE] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_FOOTER_LEFT_BRACE] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_RIGHT_BRACE] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_KERNEL_VERSION] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_FOOTER_UNMAP_GATE] = { \ + .fg = RED, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_FOOTER_DMI_STRING] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_LAYOUT_BCLK_TO_VIEW] = { \ + .fg = MAGENTA, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_LAYOUT_ROW_CPU_OFFLINE] = { \ + .fg = WHITE, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_RULER_LOAD_TAB_DIM] = { \ + .fg = MAGENTA, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_RULER_LOAD_TAB_BRIGHT] = { \ + .fg = MAGENTA, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_ILLUMINATES_CPU_OFF] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_ILLUMINATES_CPU_ON] = { \ + .fg = MAGENTA, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_ILLUMINATES_CPU_SP] = { \ + .fg = MAGENTA, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_ILLUMINATES_CPU_SP_HYBRID] = { \ + .fg = GREEN, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_DRAW_FREQUENCY_LOAD_CLEAR] = { \ + .fg = WHITE, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_DRAW_FREQUENCY_LOAD_LOW] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_DRAW_FREQUENCY_LOAD_MEDIUM] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_DRAW_FREQUENCY_LOAD_HIGH] = { \ + .fg = MAGENTA, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_DRAW_ALTMONITOR_TASKS_CLEAR] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_DRAW_ALTMONITOR_TASKS_SPACE] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_DRAW_MONITOR_FREQUENCY_NOMINAL] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_DRAW_MONITOR_FREQUENCY_LOW] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_DRAW_MONITOR_FREQUENCY_HIGH] = { \ + .fg = RED, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_DRAW_MONITOR_FREQUENCY_HOT] = { \ + .fg = MAGENTA, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_LAYOUT_CARD_CORE_OFFLINE] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_LAYOUT_CARD_RAM_2DIGITS] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_LAYOUT_CARD_RAM_3DIGITS] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_DRAW_CARD_CORE_NOMINAL] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_DRAW_CARD_CORE_LOW] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_DRAW_CARD_CORE_MEDIUM] = { \ + .fg = RED, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_DRAW_CARD_CORE_HIGH] = { \ + .fg = RED, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_DRAW_CARD_TASK_FILL] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_WIN_MENU_UNSELECT] = { \ + .fg = BLACK, .un = 0, .bg = MAGENTA, .bf = 1 \ + }, \ + [UI_WIN_MENU_SELECT] = { \ + .fg = MAGENTA, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_WIN_MENU_TITLE_UNFOCUS] = { \ + .fg = BLACK, .un = 0, .bg = MAGENTA, .bf = 0 \ + }, \ + [UI_WIN_MENU_TITLE_FOCUS] = { \ + .fg = BLACK, .un = 0, .bg = MAGENTA, .bf = 1 \ + }, \ + [UI_WIN_MENU_ERASE_CELL] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_WIN_SORT_BY_FIELD_TITLE] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_WIN_TRACKING_PARENT_PROCESS] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_WIN_TRACKING_CHILD_PROCESS] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_WIN_TRACKING_THIS_PARENT] = { \ + .fg = MAGENTA, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_WIN_TRACKING_THIS_CHILD] = { \ + .fg = MAGENTA, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_WIN_TRACKING_COUNTERS] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_WIN_TRACKING_TITLE] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_WIN_HOT_PLUG_CPU_TITLE] = { \ + .fg = WHITE, .un = 0, .bg = MAGENTA, .bf = 1 \ + }, \ + [UI_WIN_SELECT_IDLE_RESET] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_WIN_SELECT_IDLE_POLL] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_WIN_SELECT_IDLE_CURRENT] = { \ + .fg = MAGENTA, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_WIN_POPUP_MSG_ITEM] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_WIN_POPUP_MSG_SELECT_UNFOCUS] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_WIN_POPUP_MSG_SELECT_FOCUS] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_WIN_POPUP_MSG_BORDER_UNFOCUS] = { \ + .fg = WHITE, .un = 0, .bg = RED, .bf = 0 \ + }, \ + [UI_WIN_POPUP_MSG_BORDER_FOCUS] = { \ + .fg = WHITE, .un = 0, .bg = RED, .bf = 1 \ + }, \ + [UI_WIN_POPUP_MSG_TITLE_UNFOCUS] = { \ + .fg = WHITE, .un = 0, .bg = RED, .bf = 0 \ + }, \ + [UI_WIN_POPUP_MSG_TITLE_FOCUS] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_WIN_EXIT_ISSUE_RECORDER] = { \ + .fg = MAGENTA, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_WIN_EXIT_ISSUE_STRESS] = { \ + .fg = MAGENTA, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_WIN_EXIT_ISSUE_OS_CPU_IDLE] = { \ + .fg = MAGENTA, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_WIN_EXIT_HEADER] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_WIN_EXIT_BLANK] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_WIN_EXIT_CONFIRM] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_WIN_EXIT_FOOTER] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_BOX_DISABLE_STATE] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_BOX_ENABLE_STATE] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_BOX_BLANK] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_BOX_DESC] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_BOX_INTERVAL] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_BOX_EXPERIMENTAL_NOMINAL] = { \ + .fg = MAGENTA, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_BOX_EXPERIMENTAL_WARNING] = { \ + .fg = RED, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_DROP_IDLE_ROUTE] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_BOX_TOOLS_STOP] = { \ + .fg = RED, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_WHEEL_CURRENT] = { \ + .fg = MAGENTA, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_WHEEL_SELECT] = { \ + .fg = BLACK, .un = 0, .bg = MAGENTA, .bf = 0 \ + }, \ + [UI_WHEEL_LIST] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + } \ +} + +#define RSC_VOID_THM_USR1_ATTR \ +{ \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW \ +} + +#define RSC_RUN_STATE_COLOR_THM_USR1_ATTR \ +{ \ + HRW,HRW,HRW,HRW,HRW,HRW,HRW,HRW, \ + HRW,HRW,HRW,HRW,HRW,HRW,HRW,HRW, \ + HRW,HRW,HRW,HRW,HRW,HRW,HRW,HRW, \ + HRW,HRW,HRW,HRW,HRW,HRW,HRW,HRW, \ + HRW,HRW,HRW,HRW,HRW,HRW,HRW,HRW \ +} + +#define RSC_UNINT_STATE_COLOR_THM_USR1_ATTR \ +{ \ + HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW, \ + HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW, \ + HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW, \ + HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW, \ + HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW \ +} + +#define RSC_ZOMBIE_STATE_COLOR_THM_USR1_ATTR \ +{ \ + LRW,LRW,LRW,LRW,LRW,LRW,LRW,LRW, \ + LRW,LRW,LRW,LRW,LRW,LRW,LRW,LRW, \ + LRW,LRW,LRW,LRW,LRW,LRW,LRW,LRW, \ + LRW,LRW,LRW,LRW,LRW,LRW,LRW,LRW, \ + LRW,LRW,LRW,LRW,LRW,LRW,LRW,LRW \ +} + +#define RSC_SLEEP_STATE_COLOR_THM_USR1_ATTR \ +{ \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW, \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW, \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW, \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW, \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW \ +} + +#define RSC_WAIT_STATE_COLOR_THM_USR1_ATTR \ +{ \ + HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW, \ + HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW, \ + HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW, \ + HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW, \ + HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW \ +} + +#define RSC_OTHER_STATE_COLOR_THM_USR1_ATTR \ +{ \ + LGW,LGW,LGW,LGW,LGW,LGW,LGW,LGW, \ + LGW,LGW,LGW,LGW,LGW,LGW,LGW,LGW, \ + LGW,LGW,LGW,LGW,LGW,LGW,LGW,LGW, \ + LGW,LGW,LGW,LGW,LGW,LGW,LGW,LGW, \ + LGW,LGW,LGW,LGW,LGW,LGW,LGW,LGW \ +} + +#define RSC_TRACKER_STATE_COLOR_THM_USR1_ATTR \ +{ \ + LKM,LKM,LKM,LKM,LKM,LKM,LKM,LKM, \ + LKM,LKM,LKM,LKM,LKM,LKM,LKM,LKM, \ + LKM,LKM,LKM,LKM,LKM,LKM,LKM,LKM, \ + LKM,LKM,LKM,LKM,LKM,LKM,LKM,LKM, \ + LKM,LKM,LKM,LKM,LKM,LKM,LKM,LKM \ +} + +#define RSC_LAYOUT_HEADER_PROC_THM_USR1_ATTR \ +{ \ + HRW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW \ +} + +#define RSC_LAYOUT_HEADER_CPU_THM_USR1_ATTR \ +{ \ + HKW,LMW,LMW,LMW,LMW,HKW,LMW,LMW,LMW,LMW,HKW,HKW,HKW \ +} + +#define RSC_LAYOUT_HEADER_ARCH_THM_USR1_ATTR \ +{ \ + HCW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW \ +} + +#define RSC_LAYOUT_HEADER_CACHE_L1_THM_USR1_ATTR \ +{ \ + HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW, \ + HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,LMW,LMW,LMW, \ + HKW,HKW,HKW,HKW,HKW,LMW,LMW,LMW,HKW,HKW \ +} + +#define RSC_LAYOUT_HEADER_BCLK_THM_USR1_ATTR \ +{ \ + HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW, \ + HMW,HMW,LMW,LMW,LMW,HKW,LMW,LMW,LMW,HKW,LMW,LMW,LMW,HKW,HKW,HKW \ +} + +#define RSC_LAYOUT_HEADER_CACHES_THM_USR1_ATTR \ +{ \ + HKW,HKW,HKW,LMW,LMW,LMW,LMW,LMW,HKW,HKW, \ + HKW,HKW,HKW,LMW,LMW,LMW,LMW,LMW,LMW,HKW,HKW \ +} + +#define RSC_LAYOUT_RULER_LOAD_THM_USR1_ATTR \ +{ \ + LKW,LKW,LKW,LKW,_HCW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW \ +} + +#define RSC_LAYOUT_RULER_VAR_LOAD_THM_USR1_ATTR \ +{ \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW \ +} + +#define RSC_LAYOUT_RULER_REL_LOAD_THM_USR1_ATTR \ + RSC_LAYOUT_RULER_VAR_LOAD_THM_USR1_ATTR + +#define RSC_LAYOUT_RULER_ABS_LOAD_THM_USR1_ATTR \ + RSC_LAYOUT_RULER_VAR_LOAD_THM_USR1_ATTR + +#define RSC_LAYOUT_MONITOR_FREQUENCY_THM_USR1_ATTR \ +{ \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,HKW,LKW,LKW,LKW,LKW,LKW,HKW,\ + HKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,HKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,\ + HKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,HKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,\ + HKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,HKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,\ + HKW,HKW,HKW,HKW,HKW,HKW,LKW,LKW,LKW,HKW,HKW,HKW,HKW \ +} + +#define RSC_LAYOUT_MONITOR_INST_THM_USR1_ATTR \ +{ \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,HKW,HKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,HKW,HKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,HKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW \ +} + +#define RSC_LAYOUT_MONITOR_COMMON_THM_USR1_ATTR \ +{ \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW \ +} + +#define RSC_LAYOUT_MONITOR_TASKS_THM_USR1_ATTR \ +{ \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW \ +} + +#define RSC_LAYOUT_MONITOR_SLICE_THM_USR1_ATTR \ +{ \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HRW,HRW,HRW,\ + HRW,HRW,HRW,HRW,HRW,HRW,HRW,HRW,HRW,HRW,HRW,HRW,HRW,HRW,HRW \ +} + +#define RSC_LAYOUT_CUSTOM_FIELD_THM_USR1_ATTR \ +{ \ + HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW, \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW, \ + HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW, \ + HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW, \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW, \ + HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW, \ + HKW,HKW,HKW,HKW, \ + LKW,LKW,LKW,HKW, \ + HKW,HKW,HKW,HKW, \ + HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW, \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW, \ + HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW, \ + HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW, \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW, \ + HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW, \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW, \ + LKW,LKW,LKW,LKW,LKW,LKW,HKW, \ + HKW,HKW,HKW,HKW,HKW,HKW,HKW, \ + HKW,HKW,HKW,HKW,HKW,HKW,HKW, \ + HKW,HKW,HKW,HKW,HKW,HKW,HKW, \ + HKW,HKW,HKW,HKW,HKW,HKW,HKW, \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW, \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW, \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW, \ + HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,\ + HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,\ + HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,\ + HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,\ + HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,\ + HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,\ + HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,\ + HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW \ +} + +#define RSC_LAYOUT_RULER_FREQUENCY_THM_USR1_ATTR \ +{ \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW \ +} + +#define RSC_LAYOUT_RULER_FREQUENCY_AVG_THM_USR1_ATTR \ +{ \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,_HCW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,HKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,HKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,HKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,HKW,HKW,HKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW \ +} + +#define RSC_LAYOUT_RULER_FREQUENCY_PKG_THM_USR1_ATTR \ +{ \ + _HCW,LKW,LKW,LKW,LKW,LKW,HKW,LKW,LKW,HKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,HKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,LKW,LKW,HKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW \ +} + +#define RSC_LAYOUT_RULER_INST_THM_USR1_ATTR \ +{ \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW \ +} + +#define RSC_LAYOUT_RULER_CYCLES_THM_USR1_ATTR \ +{ \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,HKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,HKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW \ +} + +#define RSC_LAYOUT_RULER_CSTATES_THM_USR1_ATTR \ +{ \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,HKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW \ +} + +#define RSC_LAYOUT_RULER_INTERRUPTS_THM_USR1_ATTR \ +{ \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW \ +} + +#define RSC_LAYOUT_RULER_PACKAGE_THM_USR1_ATTR RSC_VOID_THM_USR1_ATTR + +#define RSC_LAYOUT_PACKAGE_PC_THM_USR1_ATTR \ +{ \ + LKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,HKW,\ + HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,\ + HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,\ + HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,\ + HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,\ + HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,\ + HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,\ + HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,\ + HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,\ + HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,\ + HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,\ + HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,\ + HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,\ + HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,\ + HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,\ + HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,\ + HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,\ + HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,\ + HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW,HBW \ +} + +#define RSC_LAYOUT_PACKAGE_PC02_THM_USR1_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR1_ATTR + +#define RSC_LAYOUT_PACKAGE_PC03_THM_USR1_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR1_ATTR + +#define RSC_LAYOUT_PACKAGE_PC04_THM_USR1_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR1_ATTR + +#define RSC_LAYOUT_PACKAGE_PC06_THM_USR1_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR1_ATTR + +#define RSC_LAYOUT_PACKAGE_PC07_THM_USR1_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR1_ATTR + +#define RSC_LAYOUT_PACKAGE_PC08_THM_USR1_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR1_ATTR + +#define RSC_LAYOUT_PACKAGE_PC09_THM_USR1_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR1_ATTR + +#define RSC_LAYOUT_PACKAGE_PC10_THM_USR1_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR1_ATTR + +#define RSC_LAYOUT_PACKAGE_MC06_THM_USR1_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR1_ATTR + +#define RSC_LAYOUT_PACKAGE_CTR0_THM_USR1_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR1_ATTR + +#define RSC_LAYOUT_PACKAGE_CTR1_THM_USR1_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR1_ATTR + +#define RSC_LAYOUT_PACKAGE_CTR2_THM_USR1_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR1_ATTR + +#define RSC_LAYOUT_PACKAGE_CTR3_THM_USR1_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR1_ATTR + +#define RSC_LAYOUT_PACKAGE_CTR4_THM_USR1_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR1_ATTR + +#define RSC_LAYOUT_PACKAGE_CTR5_THM_USR1_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR1_ATTR + +#define RSC_LAYOUT_PACKAGE_CTR6_THM_USR1_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR1_ATTR + +#define RSC_LAYOUT_PACKAGE_CTR7_THM_USR1_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR1_ATTR + +#define RSC_LAYOUT_PACKAGE_UNCORE_THM_USR1_ATTR \ +{ \ + LKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW \ +} + +#define RSC_LAYOUT_PACKAGE_FABRIC_THM_USR1_ATTR \ + RSC_LAYOUT_PACKAGE_UNCORE_THM_USR1_ATTR + +#define RSC_LAYOUT_RULER_TASKS_THM_USR1_ATTR \ +{ \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,\ + HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW \ +} + +#define RSC_LAYOUT_TASKS_STATE_SORTED_THM_USR1_ATTR \ +{ \ + HKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,_HCW,LKW, \ + LKW,LMW,LMW,LMW,LMW,LMW,HKW,LKW, LKW,LKW,LKW \ +} + +#define RSC_LAYOUT_TASKS_RUNTIME_SORTED_THM_USR1_ATTR \ +{ \ + HKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,_HCW,LKW, \ + LKW,LMW,LMW,LMW,LMW,LMW,LMW,LMW, HKW,LKW,LKW \ +} + +#define RSC_LAYOUT_TASKS_USRTIME_SORTED_THM_USR1_ATTR \ +{ \ + HKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,_HCW,LKW, \ + LKW,LMW,LMW,LMW,LMW,LMW,LMW,LMW, LMW,HKW,LKW \ +} + +#define RSC_LAYOUT_TASKS_SYSTIME_SORTED_THM_USR1_ATTR \ +{ \ + HKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,_HCW,LKW, \ + LKW,LMW,LMW,LMW,LMW,LMW,LMW,LMW, HKW,LKW,LKW \ +} + +#define RSC_LAYOUT_TASKS_PROCESS_SORTED_THM_USR1_ATTR \ +{ \ + HKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,_HCW,LKW, \ + LKW,LMW,LMW,LMW,HKW,LKW,LKW,LKW, LKW,LKW,LKW \ +} + +#define RSC_LAYOUT_TASKS_COMMAND_SORTED_THM_USR1_ATTR \ +{ \ + HKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,_HCW,LKW, \ + LKW,LMW,LMW,LMW,LMW,LMW,LMW,LMW, HKW,LKW,LKW \ +} + +#define RSC_LAYOUT_TASKS_REVERSE_SORT_OFF_THM_USR1_ATTR \ +{ \ + LKW,LKW,LKW,LKW,LKW,_HCW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,HKW,LKW \ +} + +#define RSC_LAYOUT_TASKS_REVERSE_SORT_ON_THM_USR1_ATTR \ +{ \ + LKW,LKW,LKW,LKW,LKW,_HCW,LKW,LKW,LKW,HKW,LMW,LMW,LMW,HKW,LKW \ +} + +#define RSC_LAYOUT_TASKS_VALUE_SWITCH_THM_USR1_ATTR \ +{ \ + LKW,_HCW,LKW,LKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,HKW,LKW \ +} + +#define RSC_LAYOUT_TASKS_VALUE_OFF_THM_USR1_ATTR \ +{ \ + LKW,LKW,LKW \ +} + +#define RSC_LAYOUT_TASKS_VALUE_ON_THM_USR1_ATTR \ +{ \ + LMW,LMW,LMW \ +} + +#define RSC_LAYOUT_TASKS_TRACKING_THM_USR1_ATTR \ +{ \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,_HCW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,HKW,LKW \ +} + +#define RSC_LAYOUT_RULER_SENSORS_THM_USR1_ATTR \ +{ \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,\ + LKW,HKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,LKW,HKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,LKW,HKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW \ +} + +#define RSC_LAYOUT_RULER_PWR_DOMAIN_THM_USR1_ATTR \ +{ \ + LKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,LKW,HKW,LKW,HKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,HKW,LKW,LKW,\ + LKW,LKW,HKW,LKW,HKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,\ + LKW,LKW,LKW,HKW,LKW,LKW,LKW,LKW,HKW,LKW,HKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,HKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,LKW,HKW,LKW,HKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW \ +} + +#define RSC_LAYOUT_RULER_PWR_UNCORE_THM_USR1_ATTR \ + RSC_LAYOUT_RULER_PWR_DOMAIN_THM_USR1_ATTR + +#define RSC_LAYOUT_RULER_PWR_PLATFORM_THM_USR1_ATTR \ + RSC_LAYOUT_RULER_PWR_DOMAIN_THM_USR1_ATTR + +#define RSC_LAYOUT_RULER_PWR_SOC_THM_USR1_ATTR \ + RSC_LAYOUT_RULER_PWR_DOMAIN_THM_USR1_ATTR + +#define RSC_LAYOUT_RULER_VOLTAGE_THM_USR1_ATTR \ +{ \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,LKW,HKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,LKW,HKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW \ +} + +#define RSC_LAYOUT_RULER_VPKG_SOC_THM_USR1_ATTR \ +{ \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + HKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,HKW,LKW,HKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW \ +} + +#define RSC_LAYOUT_RULER_VPKG_SAV_THM_USR1_ATTR \ + RSC_LAYOUT_RULER_VPKG_SOC_THM_USR1_ATTR + +#define RSC_LAYOUT_RULER_ENERGY_THM_USR1_ATTR \ +{ \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,LKW,HKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW \ +} + +#define RSC_LAYOUT_RULER_POWER_THM_USR1_ATTR \ + RSC_LAYOUT_RULER_ENERGY_THM_USR1_ATTR + +#define RSC_LAYOUT_RULER_SLICE_THM_USR1_ATTR \ +{ \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW \ +} + +#define RSC_LAYOUT_RULER_CUSTOM_THM_USR1_ATTR \ +{ \ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\ + LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW \ +} + +#define RSC_LAYOUT_FOOTER_TECH_TSC_THM_USR1_ATTR \ +{ \ + HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW \ +} + +#define RSC_LAYOUT_FOOTER_VOLT_TEMP_THM_USR1_ATTR \ +{ \ + LKW,HKW,LKW,LKW,LKW,LKW,HKW,HKW,LKW,HKW,HKW,HKW,HKW,LKW,HKW \ +} + +#define RSC_LAYOUT_FOOTER_SYSTEM_THM_USR1_ATTR \ +{ \ + HKW,HKW,HKW,HKW,HKW,HKW,HKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW, \ + HKW,HKW,HKW,HKW,HKW,HKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW, \ + LKW,HKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW \ +} + +#define RSC_LAYOUT_CARD_CORE_ONLINE_THM_USR1_ATTR \ +{ \ + HKW,HKW,LMW,LMW,LMW,HKW,HKW,HKW,HKW,HKW,HKW,HKW \ +} + +#define RSC_LAYOUT_CARD_CORE_ONLINE_COND0_THM_USR1_ATTR \ + RSC_LAYOUT_CARD_CORE_ONLINE_THM_USR1_ATTR + +#define RSC_LAYOUT_CARD_CORE_ONLINE_COND1_THM_USR1_ATTR \ + RSC_LAYOUT_CARD_CORE_ONLINE_THM_USR1_ATTR + +#define RSC_LAYOUT_CARD_CORE_OFFLINE_THM_USR1_ATTR \ +{ \ + HKW,HKW,LKW,LKW,LKW,HKW,HKW,LKW,LKW,LKW,HKW,HKW \ +} + +#define RSC_LAYOUT_CARD_CLK_THM_USR1_ATTR \ +{ \ + HKW,HKW,LMW,LMW,LMW,HKW,LMW,HKW,HKW,HKW,HKW,HKW \ +} + +#define RSC_LAYOUT_CARD_UNCORE_THM_USR1_ATTR \ +{ \ + HKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,HKW,LMW,LMW,HKW \ +} + +#define RSC_LAYOUT_CARD_BUS_THM_USR1_ATTR \ +{ \ + HKW,LKW,LKW,LKW,LMW,LMW,LMW,LMW,LMW,HKW,HKW,HKW \ +} + +#define RSC_LAYOUT_CARD_MC_THM_USR1_ATTR \ +{ \ + HKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW \ +} + +#define RSC_LAYOUT_CARD_LOAD_THM_USR1_ATTR \ +{ \ + HKW,HKW,HKW,HKW,LKW,LKW,LKW,LKW,LKW,HKW,HKW,HKW \ +} + +#define RSC_LAYOUT_CARD_IDLE_THM_USR1_ATTR \ +{ \ + HKW,HKW,HKW,HKW,LKW,LKW,LKW,LKW,LKW,HKW,HKW,HKW \ +} + +#define RSC_LAYOUT_CARD_RAM_THM_USR1_ATTR \ +{ \ + HKW,LMW,LMW,LMW,LMW,LMW,LKW,HKW,LMW,LMW,LKW,HKW \ +} + +#define RSC_LAYOUT_CARD_TASK_THM_USR1_ATTR \ +{ \ + HKW,LKW,LKW,LKW,LKW,LKW,LMW,LMW,LMW,LMW,LMW,HKW \ +} + +#define RSC_SYSINFO_CPUID_COND0_THM_USR1_ATTR \ +{ \ + HWK,HWK,HWK,LWK,HDK,LMK,LMK,LMK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_SYSINFO_CPUID_COND1_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,HDK,HDK,HDK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_SYSINFO_CPUID_COND2_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_SYSINFO_CPUID_COND3_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,\ + LWK,LWK,LWK,LWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,\ + LWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,LWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_SYSTEM_REGISTERS_COND0_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK \ +} + +#define RSC_SYSTEM_REGISTERS_COND1_THM_USR1_ATTR \ +{ \ + HDK,HDK,HDK,HDK \ +} + +#define RSC_SYSTEM_REGISTERS_COND2_THM_USR1_ATTR \ +{ \ + HWK,HWK,HWK,HWK \ +} + +#define RSC_SYSTEM_REGISTERS_COND3_THM_USR1_ATTR \ +{ \ + HDK,LMK,LMK,LMK \ +} + +#define RSC_SYSTEM_REGISTERS_COND4_THM_USR1_ATTR \ +{ \ + HDK,HDK,HDK,HDK \ +} + +#define RSC_SYSINFO_PROC_COND0_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_SYSINFO_PROC_COND1_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,HMK,HMK,HMK,HMK,HMK,HMK,HMK,LWK,LWK \ +} + +#define RSC_SYSINFO_PROC_COND2_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK \ +} + +#define RSC_SYSINFO_PROC_COND3_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK \ +} + +#define RSC_SYSINFO_ISA_COND_0_0_THM_USR1_ATTR \ +{ /* [N] & [N/N] 2*(0|0)+(0<<0) */ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} +#define RSC_SYSINFO_ISA_COND_0_1_THM_USR1_ATTR \ +{ /* [Y] */ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,HMK,LWK \ +} +#define RSC_SYSINFO_ISA_COND_0_2_THM_USR1_ATTR \ +{ /* [N/Y] 2*(0|1)+(0<<1) */ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,HMK,LWK \ +} +#define RSC_SYSINFO_ISA_COND_0_3_THM_USR1_ATTR \ +{ /* [Y/N] 2*(1|0)+(1<<0) */ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,HMK,LWK,LWK,LWK \ +} +#define RSC_SYSINFO_ISA_COND_0_4_THM_USR1_ATTR \ +{ /* [Y/Y] 2*(1|1)+(1<<1) */ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,HMK,LWK,HMK,LWK \ +} + +#define RSC_SYSINFO_ISA_COND_1_0_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} +#define RSC_SYSINFO_ISA_COND_1_1_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,HMK,LWK,LWK \ +} +#define RSC_SYSINFO_ISA_COND_1_2_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,HMK,LWK,LWK \ +} +#define RSC_SYSINFO_ISA_COND_1_3_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,HMK,LWK,LWK,LWK,LWK \ +} +#define RSC_SYSINFO_ISA_COND_1_4_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,HMK,LWK,HMK,LWK,LWK \ +} + +#define RSC_SYSINFO_FEATURES_COND0_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK \ +} + +#define RSC_SYSINFO_FEATURES_COND1_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK, \ + LWK,LWK \ +} + +#define RSC_SYSINFO_FEATURES_COND2_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LMK,LMK,LMK,LMK,LMK,LMK,LMK, \ + LWK,LWK \ +} + +#define RSC_SYSINFO_FEATURES_COND3_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,HMK,HMK,HMK,HMK,HMK,HMK,HMK, \ + LWK,LWK \ +} + +#define RSC_SYSINFO_FEATURES_COND4_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,HMK,HMK,HMK,HMK,HMK,HMK,HMK,HMK,HMK, \ + LWK,LWK \ +} + +#define RSC_SYSINFO_TECH_COND0_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_SYSINFO_TECH_COND1_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,HMK,HMK,HMK,LWK,LWK \ +} + +#define RSC_SYSINFO_PERFMON_COND0_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK \ +} + +#define RSC_SYSINFO_PERFMON_COND1_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HMK, \ + HMK,HMK,LWK,LWK \ +} + +#define RSC_SYSINFO_PERFMON_COND2_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,HWK,HWK,HWK,HWK,HWK, \ + HWK,HWK,LWK,LWK \ +} + +#define RSC_SYSINFO_PERFMON_COND3_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,HMK,HMK,HMK,HMK,HMK, \ + HMK,HMK,LWK,LWK \ +} + +#define RSC_SYSINFO_PERFMON_COND4_THM_USR1_ATTR \ +{ \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK \ +} + +#define RSC_SYSINFO_PERFMON_HWP_CAP_COND0_THM_USR1_ATTR \ +{ \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,\ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,\ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,\ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,\ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK \ +} + +#define RSC_SYSINFO_PERFMON_HWP_CAP_COND1_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LMK,LMK,LMK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,HDK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,HDK,LWK,LWK,LWK,HDK,LWK,LWK,LWK \ +} + +#define RSC_SYSINFO_PWR_THERMAL_COND0_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_SYSINFO_PWR_THERMAL_COND1_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK \ +} + +#define RSC_SYSINFO_PWR_THERMAL_COND2_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LGK,LGK,LGK,LGK,LGK,LGK,LGK,LWK,LWK \ +} + +#define RSC_SYSINFO_PWR_THERMAL_COND3_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,HMK,HMK,HMK,HMK,HMK,HMK,HMK,LWK,LWK \ +} + +#define RSC_SYSINFO_PWR_THERMAL_COND4_THM_USR1_ATTR \ +{ \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK \ +} + +#define RSC_SYSINFO_PWR_THERMAL_COND5_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_SYSINFO_PWR_THERMAL_COND6_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HWK, \ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK \ +} + +#define RSC_SYSINFO_KERNEL_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_TOPOLOGY_COND0_THM_USR1_ATTR \ +{ \ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK \ +} + +#define RSC_TOPOLOGY_COND1_THM_USR1_ATTR \ +{ \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK \ +} + +#define RSC_TOPOLOGY_COND2_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_TOPOLOGY_COND3_THM_USR1_ATTR \ +{ \ + LMK,LMK,LMK,HDK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK \ +} + +#define RSC_TOPOLOGY_COND4_THM_USR1_ATTR \ +{ \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK \ +} + +#define RSC_MEMORY_CONTROLLER_COND0_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_MEMORY_CONTROLLER_COND1_THM_USR1_ATTR \ +{ \ + HWK,HWK,HWK,HWK,HWK \ +} + +#define RSC_CREATE_MENU_DISABLE_THM_USR1_ATTR \ +{ \ + HKM,HKM,HKM,HKM,HKM,HKM,HKM,HKM,HKM,HKM,HKM,HKM, \ + HKM,HKM,HKM,HKM,HKM,HKM,HKM,HKM,HKM,HKM,HKM,HKM \ +} + +#define RSC_MENU_ITEM_MENU_THM_USR1_ATTR \ +{ \ + LKM,LKM,LKM,LKM,LKM,HKM,_LKM,_LKM,HKM,LKM,LKM,LKM, \ + LKM,LKM,LKM,LKM,LKM,LKM, LKM, LKM,LKM,LKM,LKM,LKM \ +} + +#define RSC_MENU_ITEM_VIEW_THM_USR1_ATTR \ +{ \ + LKM,LKM,LKM,LKM,LKM,HKM,_LKM,_LKM,HKM,LKM,LKM,LKM, \ + LKM,LKM,LKM,LKM,LKM,LKM, LKM, LKM,LKM,LKM,LKM,LKM \ +} + +#define RSC_MENU_ITEM_WINDOW_THM_USR1_ATTR \ +{ \ + LKM,LKM,LKM,LKM,HKM,_LKM,_LKM,HKM,LKM,LKM,LKM,LKM, \ + LKM,LKM,LKM,LKM,LKM, LKM, LKM,LKM,LKM,LKM,LKM,LKM \ +} + +#define RSC_CREATE_MENU_FN_KEY_THM_USR1_ATTR \ +{ \ + LKM,LKM,LKM,LKM,LKM,LKM,LKM,LKM, LKM,LKM,LKM,LKM, \ + LKM,LKM,LKM,LKM,LKM,LKM,LKM,HKM,_LKM,_LKM,HKM,LKM \ +} + +#define RSC_CREATE_MENU_SHORTKEY_THM_USR1_ATTR \ +{ \ + LKM,LKM,LKM,LKM,LKM,LKM,LKM,LKM,LKM, LKM,LKM,LKM, \ + LKM,LKM,LKM,LKM,LKM,LKM,LKM,LKM,HKM,_LKM,HKM,LKM \ +} + +#define RSC_CREATE_MENU_CTRL_KEY_THM_USR1_ATTR \ +{ \ + LKM,LKM, LKM, LKM, LKM, LKM,LKM,LKM,LKM, LKM,LKM,LKM, \ + LKM,HKM,_LKM,_LKM,_LKM,_LKM,HKM,HKM,HKM,_LKM,HKM,LKM \ +} + +#define RSC_CREATE_SETTINGS_COND0_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,HDK,LWK \ +} + +#define RSC_CREATE_SETTINGS_COND1_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,HMK,HMK,HMK,HDK,LWK \ +} + +#define RSC_CREATE_ADV_HELP_COND0_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_ADV_HELP_COND1_THM_USR1_ATTR \ +{ \ + LWK,HCK,HCK,HCK,HCK,HCK,HCK,HCK,HCK,HCK, \ + HCK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_HOTPLUG_CPU_ENABLE_THM_USR1_ATTR \ +{ \ + LWK,HMK,HMK,HMK,HMK,HMK,HMK,HMK,HMK,HMK,HMK,LWK,LDK,LDK,LDK \ +} + +#define RSC_CREATE_HOTPLUG_CPU_DISABLE_THM_USR1_ATTR \ +{ \ + LWK,LMK,LMK,LMK,LMK,LMK,LMK,LMK,LMK,LMK,LMK,LWK,LDK,LDK,LDK \ +} + +#define RSC_CREATE_HOTPLUG_CPU_ONLINE_THM_USR1_ATTR \ +{ \ + LMK,LMK,LMK,LMK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK \ +} + +#define RSC_CREATE_HOTPLUG_CPU_OFFLINE_THM_USR1_ATTR \ +{ \ + HDK,HDK,HDK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_RATIO_CLOCK_COND0_THM_USR1_ATTR \ +{ \ + LWK,HWK,HWK,HWK,HWK,LWK,HWK,HWK,LWK,HDK,HDK,HDK,LWK,LWK, \ + LWK,LWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_RATIO_CLOCK_COND1_THM_USR1_ATTR \ +{ \ + LWK,HBK,HBK,HBK,HBK,LBK,HBK,HBK,LWK,HDK,HDK,HDK,LWK,LWK, \ + LWK,LWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_RATIO_CLOCK_COND2_THM_USR1_ATTR \ +{ \ + LWK,HRK,HRK,HRK,HRK,LRK,HRK,HRK,LWK,HDK,HDK,HDK,LWK,LWK, \ + LWK,LWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_RATIO_CLOCK_COND3_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,HMK,HMK,HMK,HMK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_RATIO_CLOCK_COND4_THM_USR1_ATTR \ +{ \ + LWK,HWK,HWK,HWK,HWK,LWK,HWK,HWK,LWK,HDK,HDK,HDK,LWK,LWK, \ + LWK,LWK,HMK,HMK,HMK,HMK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_RATIO_CLOCK_COND5_THM_USR1_ATTR \ +{ \ + LWK,HBK,HBK,HBK,HBK,LBK,HBK,HBK,LWK,HDK,HDK,HDK,LWK,LWK, \ + LWK,LWK,HMK,HMK,HMK,HMK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_RATIO_CLOCK_COND6_THM_USR1_ATTR \ +{ \ + LWK,HRK,HRK,HRK,HRK,LRK,HRK,HRK,LWK,HDK,HDK,HDK,LWK,LWK, \ + LWK,LWK,HMK,HMK,HMK,HMK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_SELECT_CPU_COND0_THM_USR1_ATTR \ +{ \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,LWK,HDK,HDK,HDK,LWK,HDK,HDK,HDK,HDK \ +} + +#define RSC_CREATE_SELECT_CPU_COND1_THM_USR1_ATTR \ +{ \ + LMK,LMK,LMK,LMK,LMK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_SELECT_CPU_COND2_THM_USR1_ATTR \ +{ \ + LMK,LMK,LMK,LMK,LMK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,HRK,HRK,HRK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_HOT_EVENT_COND0_THM_USR1_ATTR \ +{ \ + HKW,HKW,HKW \ +} + +#define RSC_HOT_EVENT_COND1_THM_USR1_ATTR \ +{ \ + HRW,HRW,HRW \ +} + +#define RSC_HOT_EVENT_COND2_THM_USR1_ATTR \ +{ \ + {.fg=CYAN,.bg=WHITE,.bf=1,.un=1}, \ + {.fg=CYAN,.bg=WHITE,.bf=0,.un=0}, \ + {.fg=CYAN,.bg=WHITE,.bf=0,.un=0} \ +} + +#define RSC_HOT_EVENT_COND3_THM_USR1_ATTR \ +{ \ + LKW,LKW,LKW \ +} + +#define RSC_HOT_EVENT_COND4_THM_USR1_ATTR \ +{ \ + {.fg=CYAN,.bg=MAGENTA,.bf=0,.un=1}, \ + {.fg=CYAN,.bg=MAGENTA,.bf=0,.un=0}, \ + {.fg=CYAN,.bg=MAGENTA,.bf=0,.un=0} \ +} + +#define RSC_BOX_EVENT_COND00_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK \ +} + +#define RSC_BOX_EVENT_COND01_THM_USR1_ATTR \ +{ \ + LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,HDK \ +} + +#define RSC_BOX_EVENT_COND10_THM_USR1_ATTR \ +{ \ + LKY,LKY,LKY,LKY,LKY,LKY,LKY,LKY,LKY,LKY,LKY,LKY,LKY,LKY,LKY,LKY,HDK \ +} + +#define RSC_BOX_EVENT_COND11_THM_USR1_ATTR \ +{ \ + LKY,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LKY,HDK \ +} + +#define RSC_BOX_EVENT_BUTTON_THM_USR1_ATTR \ +{ \ + LWK,HMK,HMK,HMK,HMK,HMK,HMK,HMK,HMK,HMK,HMK,HMK,HMK,HMK,HMK,HMK,LWK \ +} + +#define RSC_CREATE_RECORDER_THM_USR1_ATTR \ +{ \ + LWK,LWK,LWK,LWK,HDK,LWK,LWK,HDK,LWK,LWK,LWK,LWK \ +} + +#define RSC_SMBIOS_ITEM_THM_USR1_ATTR \ +{ \ + HDK,LMK,LMK,HDK,HDK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_SELECT_FREQ_PKG_THM_USR1_ATTR \ +{ \ + HMK,HMK,HMK,HMK,HMK,HMK,HMK,HMK,HMK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HMK,HMK,HMK,HMK,HMK,HMK,\ + HMK,HMK,HDK,HDK,HDK,LWK,LWK,HMK,HMK,HMK,HMK,HMK,LWK,LWK \ +} + +#define RSC_CREATE_SELECT_FREQ_COND0_THM_USR1_ATTR \ +{ \ + LMK,LMK,LMK,LMK,LMK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,HDK,HDK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_SELECT_FREQ_COND1_THM_USR1_ATTR \ +{ \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK \ +} + +_Static_assert( __builtin_strlen(RSC_THEME_USR1_CODE) + == __builtin_strlen(RSC_BOX_THEME_BLANK_CODE), +"Mandatory string length"); diff --git a/aarch64/corefreq-cli-rsc-theme-usr2.h b/aarch64/corefreq-cli-rsc-theme-usr2.h new file mode 100644 index 00000000..215d7de9 --- /dev/null +++ b/aarch64/corefreq-cli-rsc-theme-usr2.h @@ -0,0 +1,1944 @@ +/* + * CoreFreq + * Copyright (C) 2015-2024 CYRIL COURTIAT + * Licenses: GPL2 + */ + +#define RSC_THEME_USR2_CODE /* 72 chars */ \ +" Transparent theme by leaty. Updated by CyrIng - May 2022 " + +#define RSC_UI_THM_USR2_ATTR \ +{ \ + [UI_FUSE_RESET_LAYER] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_FUSE_PAINT_LAYER] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_MAKE_TITLE_UNFOCUS] = { \ + .fg = BLACK, .un = 0, .bg = BLUE, .bf = 1 \ + }, \ + [UI_MAKE_TITLE_FOCUS] = { \ + .fg = WHITE, .un = 0, .bg = CYAN, .bf = 1 \ + }, \ + [UI_MAKE_BORDER_UNFOCUS] = { \ + .fg = BLACK, .un = 0, .bg = BLUE, .bf = 1 \ + }, \ + [UI_MAKE_BORDER_FOCUS] = { \ + .fg = WHITE, .un = 0, .bg = BLUE, .bf = 1 \ + }, \ + [UI_MAKE_SELECT_UNFOCUS] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_MAKE_SELECT_FOCUS] = { \ + .fg = MAGENTA, .un = 1, .bg = BLACK, .bf = 0 \ + }, \ + [UI_MAKE_PRINT_UNFOCUS] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_MAKE_PRINT_FOCUS] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_MAKE_PRINT_DROP] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_LAYOUT_LCD_RESET] = { \ + .fg = CYAN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_CLOCK_LOW] = { \ + .fg = GREEN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_CLOCK_MEDIUM] = { \ + .fg = YELLOW, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_CLOCK_HIGH] = { \ + .fg = RED, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_COUNTER_LOW] = { \ + .fg = RED, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_COUNTER_MEDIUM] = { \ + .fg = YELLOW, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_COUNTER_HIGH] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_LOAD_LOW] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_LOAD_MEDIUM] = { \ + .fg = YELLOW, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_LOAD_HIGH] = { \ + .fg = RED, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_IDLE_LOW] = { \ + .fg = YELLOW, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_IDLE_MEDIUM] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_IDLE_HIGH] = { \ + .fg = GREEN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_SYSTEM_LOW] = { \ + .fg = RED, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_SYSTEM_MEDIUM] = { \ + .fg = YELLOW, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_LCD_SYSTEM_HIGH] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_UBENCH] = { \ + .fg = MAGENTA, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_HEADER_PROC_BRAND] = { \ + .fg = CYAN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_HEADER_PROC_BRAND_FILL] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_HEADER_ARCHITECTURE] = { \ + .fg = CYAN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_HEADER_ARCH_FILL] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_HEADER_BCLK_FILL] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_RULER_INSTRUCTIONS] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_LAYOUT_RULER_CYCLES] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_LAYOUT_RULER_CSTATES] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_LAYOUT_RULER_INTERRUPTS] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_LAYOUT_RULER_PACKAGE] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_LAYOUT_RULER_TASKS_FILL] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_LAYOUT_RULER_TASKS_TRACKING] = { \ + .fg = CYAN, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_LAYOUT_RULER_ENERGY] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_LAYOUT_RULER_SLICE] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_LAYOUT_RULER_CUSTOM] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_LAYOUT_FOOTER_ENABLE_0] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_ENABLE_1] = { \ + .fg = GREEN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_ENABLE_2] = { \ + .fg = BLUE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_TSC_NONE] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_TSC_VAR] = { \ + .fg = BLUE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_TSC_INV] = { \ + .fg = GREEN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_TM_0] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_TM_1] = { \ + .fg = BLUE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_TM_2] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_TM_3] = { \ + .fg = GREEN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_FILL] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_GATE] = { \ + .fg = CYAN, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_LAYOUT_FOOTER_SPACE] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_LAYOUT_FOOTER_LEFT_BRACE] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_RIGHT_BRACE] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_KERNEL_VERSION] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_FOOTER_UNMAP_GATE] = { \ + .fg = RED, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_LAYOUT_FOOTER_DMI_STRING] = { \ + .fg = BLUE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_BCLK_TO_VIEW] = { \ + .fg = YELLOW, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_ROW_CPU_OFFLINE] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_LAYOUT_RULER_LOAD_TAB_DIM] = { \ + .fg = CYAN, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_LAYOUT_RULER_LOAD_TAB_BRIGHT] = { \ + .fg = CYAN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_ILLUMINATES_CPU_OFF] = { \ + .fg = BLUE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_ILLUMINATES_CPU_ON] = { \ + .fg = CYAN, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_ILLUMINATES_CPU_SP] = { \ + .fg = CYAN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_ILLUMINATES_CPU_SP_HYBRID] = { \ + .fg = GREEN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_DRAW_FREQUENCY_LOAD_CLEAR] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_DRAW_FREQUENCY_LOAD_LOW] = { \ + .fg = GREEN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_DRAW_FREQUENCY_LOAD_MEDIUM] = { \ + .fg = YELLOW, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_DRAW_FREQUENCY_LOAD_HIGH] = { \ + .fg = RED, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_DRAW_ALTMONITOR_TASKS_CLEAR] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_DRAW_ALTMONITOR_TASKS_SPACE] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_DRAW_MONITOR_FREQUENCY_NOMINAL] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_DRAW_MONITOR_FREQUENCY_LOW] = { \ + .fg = BLUE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_DRAW_MONITOR_FREQUENCY_HIGH] = { \ + .fg = YELLOW, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_DRAW_MONITOR_FREQUENCY_HOT] = { \ + .fg = RED, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_CARD_CORE_OFFLINE] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_CARD_RAM_2DIGITS] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_LAYOUT_CARD_RAM_3DIGITS] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_DRAW_CARD_CORE_NOMINAL] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_DRAW_CARD_CORE_LOW] = { \ + .fg = BLUE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_DRAW_CARD_CORE_MEDIUM] = { \ + .fg = YELLOW, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_DRAW_CARD_CORE_HIGH] = { \ + .fg = RED, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_DRAW_CARD_TASK_FILL] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_WIN_MENU_UNSELECT] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_WIN_MENU_SELECT] = { \ + .fg = MAGENTA, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_WIN_MENU_TITLE_UNFOCUS] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_WIN_MENU_TITLE_FOCUS] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_WIN_MENU_ERASE_CELL] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_WIN_SORT_BY_FIELD_TITLE] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_WIN_TRACKING_PARENT_PROCESS] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_WIN_TRACKING_CHILD_PROCESS] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_WIN_TRACKING_THIS_PARENT] = { \ + .fg = BLUE, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_WIN_TRACKING_THIS_CHILD] = { \ + .fg = BLUE, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_WIN_TRACKING_COUNTERS] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_WIN_TRACKING_TITLE] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_WIN_HOT_PLUG_CPU_TITLE] = { \ + .fg = WHITE, .un = 0, .bg = BLUE, .bf = 1 \ + }, \ + [UI_WIN_SELECT_IDLE_RESET] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_WIN_SELECT_IDLE_POLL] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_WIN_SELECT_IDLE_CURRENT] = { \ + .fg = CYAN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_WIN_POPUP_MSG_ITEM] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_WIN_POPUP_MSG_SELECT_UNFOCUS] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_WIN_POPUP_MSG_SELECT_FOCUS] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_WIN_POPUP_MSG_BORDER_UNFOCUS] = { \ + .fg = WHITE, .un = 0, .bg = RED, .bf = 0 \ + }, \ + [UI_WIN_POPUP_MSG_BORDER_FOCUS] = { \ + .fg = WHITE, .un = 0, .bg = RED, .bf = 1 \ + }, \ + [UI_WIN_POPUP_MSG_TITLE_UNFOCUS] = { \ + .fg = WHITE, .un = 0, .bg = RED, .bf = 0 \ + }, \ + [UI_WIN_POPUP_MSG_TITLE_FOCUS] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 0 \ + }, \ + [UI_WIN_EXIT_ISSUE_RECORDER] = { \ + .fg = CYAN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_WIN_EXIT_ISSUE_STRESS] = { \ + .fg = CYAN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_WIN_EXIT_ISSUE_OS_CPU_IDLE] = { \ + .fg = CYAN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_WIN_EXIT_HEADER] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_WIN_EXIT_BLANK] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_WIN_EXIT_CONFIRM] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_WIN_EXIT_FOOTER] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_BOX_DISABLE_STATE] = { \ + .fg = CYAN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_BOX_ENABLE_STATE] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_BOX_BLANK] = { \ + .fg = BLACK, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_BOX_DESC] = { \ + .fg = CYAN, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_BOX_INTERVAL] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + }, \ + [UI_BOX_EXPERIMENTAL_NOMINAL] = { \ + .fg = CYAN, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_BOX_EXPERIMENTAL_WARNING] = { \ + .fg = RED, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_DROP_IDLE_ROUTE] = { \ + .fg = BLACK, .un = 0, .bg = WHITE, .bf = 1 \ + }, \ + [UI_BOX_TOOLS_STOP] = { \ + .fg = RED, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_WHEEL_CURRENT] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 1 \ + }, \ + [UI_WHEEL_SELECT] = { \ + .fg = CYAN, .un = 1, .bg = BLACK, .bf = 1 \ + }, \ + [UI_WHEEL_LIST] = { \ + .fg = WHITE, .un = 0, .bg = BLACK, .bf = 0 \ + } \ +} + +#define RSC_VOID_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_RUN_STATE_COLOR_THM_USR2_ATTR \ +{ \ + HRK,HRK,HRK,HRK,HRK,HRK,HRK,HRK, \ + HRK,HRK,HRK,HRK,HRK,HRK,HRK,HRK, \ + HRK,HRK,HRK,HRK,HRK,HRK,HRK,HRK, \ + HRK,HRK,HRK,HRK,HRK,HRK,HRK,HRK, \ + HRK,HRK,HRK,HRK,HRK,HRK,HRK,HRK \ +} + +#define RSC_UNINT_STATE_COLOR_THM_USR2_ATTR \ +{ \ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK, \ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK, \ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK, \ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK, \ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK \ +} + +#define RSC_ZOMBIE_STATE_COLOR_THM_USR2_ATTR \ +{ \ + LRW,LRW,LRW,LRW,LRW,LRW,LRW,LRW, \ + LRW,LRW,LRW,LRW,LRW,LRW,LRW,LRW, \ + LRW,LRW,LRW,LRW,LRW,LRW,LRW,LRW, \ + LRW,LRW,LRW,LRW,LRW,LRW,LRW,LRW, \ + LRW,LRW,LRW,LRW,LRW,LRW,LRW,LRW \ +} + +#define RSC_SLEEP_STATE_COLOR_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_WAIT_STATE_COLOR_THM_USR2_ATTR \ +{ \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK \ +} + +#define RSC_OTHER_STATE_COLOR_THM_USR2_ATTR \ +{ \ + LGK,LGK,LGK,LGK,LGK,LGK,LGK,LGK, \ + LGK,LGK,LGK,LGK,LGK,LGK,LGK,LGK, \ + LGK,LGK,LGK,LGK,LGK,LGK,LGK,LGK, \ + LGK,LGK,LGK,LGK,LGK,LGK,LGK,LGK, \ + LGK,LGK,LGK,LGK,LGK,LGK,LGK,LGK \ +} + +#define RSC_TRACKER_STATE_COLOR_THM_USR2_ATTR \ +{ \ + LKC,LKC,LKC,LKC,LKC,LKC,LKC,LKC, \ + LKC,LKC,LKC,LKC,LKC,LKC,LKC,LKC, \ + LKC,LKC,LKC,LKC,LKC,LKC,LKC,LKC, \ + LKC,LKC,LKC,LKC,LKC,LKC,LKC,LKC, \ + LKC,LKC,LKC,LKC,LKC,LKC,LKC,LKC \ +} + +#define RSC_LAYOUT_HEADER_PROC_THM_USR2_ATTR \ +{ \ + HRK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK \ +} + +#define RSC_LAYOUT_HEADER_CPU_THM_USR2_ATTR \ +{ \ + HDK,HWK,HWK,HWK,HWK,HDK,HWK,HWK,HWK,HWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_HEADER_ARCH_THM_USR2_ATTR \ +{ \ + HCK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK \ +} + +#define RSC_LAYOUT_HEADER_CACHE_L1_THM_USR2_ATTR \ +{ \ + HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,HWK,HWK,HWK, \ + LWK,LWK,LWK,LWK,HDK,HWK,HWK,HWK,LWK,LWK \ +} + +#define RSC_LAYOUT_HEADER_BCLK_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + HYK,HYK,HYK,HYK,HYK,HDK,HYK,HYK,HYK,HDK,HYK,HYK,HYK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_HEADER_CACHES_THM_USR2_ATTR \ +{ \ + LWK,LWK,HDK,HWK,HWK,HWK,HWK,HWK,LWK,LWK, \ + LWK,LWK,HDK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_LOAD_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,_HCK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_VAR_LOAD_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_REL_LOAD_THM_USR2_ATTR \ + RSC_LAYOUT_RULER_VAR_LOAD_THM_USR2_ATTR + +#define RSC_LAYOUT_RULER_ABS_LOAD_THM_USR2_ATTR \ + RSC_LAYOUT_RULER_VAR_LOAD_THM_USR2_ATTR + +#define RSC_LAYOUT_MONITOR_FREQUENCY_THM_USR2_ATTR \ +{ \ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HDK,HDK,HWK,HWK,HWK,HWK,HWK,HDK,\ + HDK,HWK,HWK,HWK,HWK,HWK,HWK,HDK,HDK,HWK,HWK,HWK,HWK,HWK,HWK,HDK,\ + HDK,HWK,HWK,HWK,HWK,HWK,HWK,HDK,HDK,HWK,HWK,HWK,HWK,HWK,HWK,HDK,\ + HDK,HWK,HWK,HWK,HWK,HWK,HWK,HDK,HDK,HWK,HWK,HWK,HWK,HWK,HWK,HDK,\ + HDK,HDK,HBK,HBK,HBK,HDK,LWK,LWK,LWK,HDK,LYK,LYK,LYK \ +} + +#define RSC_LAYOUT_MONITOR_INST_THM_USR2_ATTR \ +{ \ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HDK,LWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HDK,LWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HDK,LWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK \ +} + +#define RSC_LAYOUT_MONITOR_COMMON_THM_USR2_ATTR \ +{ \ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK \ +} + +#define RSC_LAYOUT_MONITOR_TASKS_THM_USR2_ATTR \ +{ \ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_MONITOR_SLICE_THM_USR2_ATTR \ +{ \ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HRK,HRK,HRK,\ + HRK,HRK,HRK,HRK,HRK,HRK,HRK,HRK,HRK,HRK,HRK,HRK,HRK,HRK,HRK \ +} + +#define RSC_LAYOUT_CUSTOM_FIELD_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK, \ + HWK,HWK,HWK,LWK, \ + LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK, \ + HWK,HWK,HWK,HWK,HWK,HWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK, \ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK, \ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_FREQUENCY_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_FREQUENCY_AVG_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,_HCK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_FREQUENCY_PKG_THM_USR2_ATTR \ +{ \ + _HCK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,HDK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_INST_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_CYCLES_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_CSTATES_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_INTERRUPTS_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_PACKAGE_THM_USR2_ATTR RSC_VOID_THM_USR2_ATTR + +#define RSC_LAYOUT_PACKAGE_PC_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,HDK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HDK,HDK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,\ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK \ +} + +#define RSC_LAYOUT_PACKAGE_PC02_THM_USR2_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR2_ATTR + +#define RSC_LAYOUT_PACKAGE_PC03_THM_USR2_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR2_ATTR + +#define RSC_LAYOUT_PACKAGE_PC04_THM_USR2_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR2_ATTR + +#define RSC_LAYOUT_PACKAGE_PC06_THM_USR2_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR2_ATTR + +#define RSC_LAYOUT_PACKAGE_PC07_THM_USR2_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR2_ATTR + +#define RSC_LAYOUT_PACKAGE_PC08_THM_USR2_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR2_ATTR + +#define RSC_LAYOUT_PACKAGE_PC09_THM_USR2_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR2_ATTR + +#define RSC_LAYOUT_PACKAGE_PC10_THM_USR2_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR2_ATTR + +#define RSC_LAYOUT_PACKAGE_MC06_THM_USR2_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR2_ATTR + +#define RSC_LAYOUT_PACKAGE_CTR0_THM_USR2_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR2_ATTR + +#define RSC_LAYOUT_PACKAGE_CTR1_THM_USR2_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR2_ATTR + +#define RSC_LAYOUT_PACKAGE_CTR2_THM_USR2_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR2_ATTR + +#define RSC_LAYOUT_PACKAGE_CTR3_THM_USR2_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR2_ATTR + +#define RSC_LAYOUT_PACKAGE_CTR4_THM_USR2_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR2_ATTR + +#define RSC_LAYOUT_PACKAGE_CTR5_THM_USR2_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR2_ATTR + +#define RSC_LAYOUT_PACKAGE_CTR6_THM_USR2_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR2_ATTR + +#define RSC_LAYOUT_PACKAGE_CTR7_THM_USR2_ATTR \ + RSC_LAYOUT_PACKAGE_PC_THM_USR2_ATTR + +#define RSC_LAYOUT_PACKAGE_UNCORE_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,HDK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_PACKAGE_FABRIC_THM_USR2_ATTR \ + RSC_LAYOUT_PACKAGE_UNCORE_THM_USR2_ATTR + +#define RSC_LAYOUT_RULER_TASKS_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LDK,LDK,LDK,LDK,LDK,LDK,LDK,LDK,LDK,\ + LDK,LDK,LDK,LDK,LDK,LDK,LDK,LDK,LDK,LDK,LDK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_TASKS_STATE_SORTED_THM_USR2_ATTR \ +{ \ + HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,_HCK,LWK, \ + LWK,LCK,LCK,LCK,LCK,LCK,HDK,LWK, LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_TASKS_RUNTIME_SORTED_THM_USR2_ATTR \ +{ \ + HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,_HCK,LWK, \ + LWK,LCK,LCK,LCK,LCK,LCK,LCK,LCK, HDK,LWK,LWK \ +} + +#define RSC_LAYOUT_TASKS_USRTIME_SORTED_THM_USR2_ATTR \ +{ \ + HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,_HCK,LWK, \ + LWK,LCK,LCK,LCK,LCK,LCK,LCK,LCK, LCK,HDK,LWK \ +} + +#define RSC_LAYOUT_TASKS_SYSTIME_SORTED_THM_USR2_ATTR \ +{ \ + HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,_HCK,LWK, \ + LWK,LCK,LCK,LCK,LCK,LCK,LCK,LCK, HDK,LWK,LWK \ +} + +#define RSC_LAYOUT_TASKS_PROCESS_SORTED_THM_USR2_ATTR \ +{ \ + HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,_HCK,LWK, \ + LWK,LCK,LCK,LCK,HDK,LWK,LWK,LWK, LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_TASKS_COMMAND_SORTED_THM_USR2_ATTR \ +{ \ + HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,_HCK,LWK, \ + LWK,LCK,LCK,LCK,LCK,LCK,LCK,LCK, HDK,LWK,LWK \ +} + +#define RSC_LAYOUT_TASKS_REVERSE_SORT_OFF_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,_HCK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,HDK,LWK \ +} + +#define RSC_LAYOUT_TASKS_REVERSE_SORT_ON_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,_HCK,LWK,LWK,LWK,HDK,LCK,LCK,LCK,HDK,LWK \ +} + +#define RSC_LAYOUT_TASKS_VALUE_SWITCH_THM_USR2_ATTR \ +{ \ + LWK,_HCK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,HDK,LWK \ +} + +#define RSC_LAYOUT_TASKS_VALUE_OFF_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_TASKS_VALUE_ON_THM_USR2_ATTR \ +{ \ + LCK,LCK,LCK \ +} + +#define RSC_LAYOUT_TASKS_TRACKING_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,_HCK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK \ +} + +#define RSC_LAYOUT_RULER_SENSORS_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,\ + LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,HDK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,HDK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_PWR_DOMAIN_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,HDK,HWK,HWK,HWK,LWK,HWK,HWK,HWK,HWK,HDK,LWK,HDK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,HWK,HWK,HWK,LWK,HWK,HWK,\ + HWK,HWK,HDK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,\ + HWK,HWK,HWK,LWK,HWK,HWK,HWK,HWK,HDK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,HDK,HWK,HWK,HWK,LWK,HWK,HWK,HWK,HWK,HDK,LWK,HDK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_PWR_UNCORE_THM_USR2_ATTR \ + RSC_LAYOUT_RULER_PWR_DOMAIN_THM_USR2_ATTR + +#define RSC_LAYOUT_RULER_PWR_PLATFORM_THM_USR2_ATTR \ + RSC_LAYOUT_RULER_PWR_DOMAIN_THM_USR2_ATTR + +#define RSC_LAYOUT_RULER_PWR_SOC_THM_USR2_ATTR \ + RSC_LAYOUT_RULER_PWR_DOMAIN_THM_USR2_ATTR + +#define RSC_LAYOUT_RULER_VOLTAGE_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,HDK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,HDK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_VPKG_SOC_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\ + HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HDK,LWK,HDK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,HDK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_VPKG_SAV_THM_USR2_ATTR \ + RSC_LAYOUT_RULER_VPKG_SOC_THM_USR2_ATTR + +#define RSC_LAYOUT_RULER_ENERGY_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_POWER_THM_USR2_ATTR \ + RSC_LAYOUT_RULER_ENERGY_THM_USR2_ATTR + +#define RSC_LAYOUT_RULER_SLICE_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_RULER_CUSTOM_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_LAYOUT_FOOTER_TECH_TSC_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,LWK \ +} + +#define RSC_LAYOUT_FOOTER_VOLT_TEMP_THM_USR2_ATTR \ +{ \ + LWK,HDK,HWK,HWK,HWK,HWK,HDK,HDK,LWK,HDK,HDK,HDK,HDK,LWK,HDK \ +} + +#define RSC_LAYOUT_FOOTER_SYSTEM_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,HDK,HWK,HWK,HWK,HWK,HWK,HWK,HDK, \ + LWK,LWK,LWK,LWK,LWK,HDK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK, \ + HWK,HDK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK,HDK \ +} + +#define RSC_LAYOUT_CARD_CORE_ONLINE_THM_USR2_ATTR \ +{ \ + HDK,HDK,LCK,LCK,LCK,HDK,HDK,HDK,HDK,HDK,HDK,HDK \ +} + +#define RSC_LAYOUT_CARD_CORE_ONLINE_COND0_THM_USR2_ATTR \ + RSC_LAYOUT_CARD_CORE_ONLINE_THM_USR2_ATTR + +#define RSC_LAYOUT_CARD_CORE_ONLINE_COND1_THM_USR2_ATTR \ + RSC_LAYOUT_CARD_CORE_ONLINE_THM_USR2_ATTR + +#define RSC_LAYOUT_CARD_CORE_OFFLINE_THM_USR2_ATTR \ +{ \ + HDK,HDK,LBK,LBK,LBK,HDK,HDK,LWK,LWK,LWK,HDK,HDK \ +} + +#define RSC_LAYOUT_CARD_CLK_THM_USR2_ATTR \ +{ \ + HDK,HDK,HWK,HWK,HWK,LWK,HWK,HDK,HDK,HDK,HDK,HDK \ +} + +#define RSC_LAYOUT_CARD_UNCORE_THM_USR2_ATTR \ +{ \ + HDK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,HDK,LCK,LCK,HDK \ +} + +#define RSC_LAYOUT_CARD_BUS_THM_USR2_ATTR \ +{ \ + HDK,LWK,LWK,LWK,HWK,HWK,HWK,HWK,HWK,HDK,HDK,HDK \ +} + +#define RSC_LAYOUT_CARD_MC_THM_USR2_ATTR \ +{ \ + HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK \ +} + +#define RSC_LAYOUT_CARD_LOAD_THM_USR2_ATTR \ +{ \ + HDK,HDK,HDK,HDK,LWK,LWK,LWK,LWK,LWK,HDK,HDK,HDK \ +} + +#define RSC_LAYOUT_CARD_IDLE_THM_USR2_ATTR \ +{ \ + HDK,HDK,HDK,HDK,LWK,LWK,LWK,LWK,LWK,HDK,HDK,HDK \ +} + +#define RSC_LAYOUT_CARD_RAM_THM_USR2_ATTR \ +{ \ + HDK,HWK,HWK,HWK,HWK,HWK,LWK,HDK,HWK,HWK,LDK,HDK \ +} + +#define RSC_LAYOUT_CARD_TASK_THM_USR2_ATTR \ +{ \ + HDK,LWK,LWK,LWK,LWK,LWK,HWK,HWK,HWK,HWK,HWK,HDK \ +} + +#define RSC_SYSINFO_CPUID_COND0_THM_USR2_ATTR \ +{ \ + HWK,HWK,HWK,LWK,HDK,LCK,LCK,LCK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_SYSINFO_CPUID_COND1_THM_USR2_ATTR \ +{ \ + HBK,HBK,HBK,HBK,HBK,LBK,LBK,LBK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_SYSINFO_CPUID_COND2_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,HWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_SYSINFO_CPUID_COND3_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,\ + LWK,LWK,LWK,LWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,\ + LWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,LWK,HWK,HWK,\ + HWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_SYSTEM_REGISTERS_COND0_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK \ +} + +#define RSC_SYSTEM_REGISTERS_COND1_THM_USR2_ATTR \ +{ \ + HBK,HBK,HBK,HBK \ +} + +#define RSC_SYSTEM_REGISTERS_COND2_THM_USR2_ATTR \ +{ \ + HWK,HWK,HWK,HWK \ +} + +#define RSC_SYSTEM_REGISTERS_COND3_THM_USR2_ATTR \ +{ \ + HDK,LCK,LCK,LCK \ +} + +#define RSC_SYSTEM_REGISTERS_COND4_THM_USR2_ATTR \ +{ \ + HDK,LBK,LBK,LBK \ +} + +#define RSC_SYSINFO_PROC_COND0_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_SYSINFO_PROC_COND1_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,HGK,HGK,HGK,HGK,HGK,HGK,HGK,LWK,LWK \ +} + +#define RSC_SYSINFO_PROC_COND2_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK \ +} + +#define RSC_SYSINFO_PROC_COND3_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK \ +} + +#define RSC_SYSINFO_ISA_COND_0_0_THM_USR2_ATTR \ +{ /* [N] & [N/N] 2*(0|0)+(0<<0) */ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} +#define RSC_SYSINFO_ISA_COND_0_1_THM_USR2_ATTR \ +{ /* [Y] */ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,HGK,LWK \ +} +#define RSC_SYSINFO_ISA_COND_0_2_THM_USR2_ATTR \ +{ /* [N/Y] 2*(0|1)+(0<<1) */ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,HGK,LWK \ +} +#define RSC_SYSINFO_ISA_COND_0_3_THM_USR2_ATTR \ +{ /* [Y/N] 2*(1|0)+(1<<0) */ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,HGK,LWK,LWK,LWK \ +} +#define RSC_SYSINFO_ISA_COND_0_4_THM_USR2_ATTR \ +{ /* [Y/Y] 2*(1|1)+(1<<1) */ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,HGK,LWK,HGK,LWK \ +} + +#define RSC_SYSINFO_ISA_COND_1_0_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} +#define RSC_SYSINFO_ISA_COND_1_1_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,HGK,LWK,LWK \ +} +#define RSC_SYSINFO_ISA_COND_1_2_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,HGK,LWK,LWK \ +} +#define RSC_SYSINFO_ISA_COND_1_3_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,HGK,LWK,LWK,LWK,LWK \ +} +#define RSC_SYSINFO_ISA_COND_1_4_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,HGK,LWK,HGK,LWK,LWK \ +} + +#define RSC_SYSINFO_FEATURES_COND0_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK \ +} + +#define RSC_SYSINFO_FEATURES_COND1_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,HBK,HBK,HBK,HBK,HBK,HBK,HBK, \ + LWK,LWK \ +} + +#define RSC_SYSINFO_FEATURES_COND2_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LCK,LCK,LCK,LCK,LCK,LCK,LCK, \ + LWK,LWK \ +} + +#define RSC_SYSINFO_FEATURES_COND3_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,HGK,HGK,HGK,HGK,HGK,HGK,HGK, \ + LWK,LWK \ +} + +#define RSC_SYSINFO_FEATURES_COND4_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,HGK,HGK,HGK,HGK,HGK,HGK,HGK,HGK,HGK, \ + LWK,LWK \ +} + +#define RSC_SYSINFO_TECH_COND0_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_SYSINFO_TECH_COND1_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,HGK,HGK,HGK,LWK,LWK \ +} + +#define RSC_SYSINFO_PERFMON_COND0_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK \ +} + +#define RSC_SYSINFO_PERFMON_COND1_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HGK, \ + HGK,HGK,LWK,LWK \ +} + +#define RSC_SYSINFO_PERFMON_COND2_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,HBK,HBK,HBK,HBK,HBK, \ + HBK,HBK,LWK,LWK \ +} + +#define RSC_SYSINFO_PERFMON_COND3_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,HGK,HGK,HGK,HGK,HGK, \ + HGK,HGK,LWK,LWK \ +} + +#define RSC_SYSINFO_PERFMON_COND4_THM_USR2_ATTR \ +{ \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK \ +} + +#define RSC_SYSINFO_PERFMON_HWP_CAP_COND0_THM_USR2_ATTR \ +{ \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,\ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,\ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,\ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,\ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK \ +} + +#define RSC_SYSINFO_PERFMON_HWP_CAP_COND1_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LCK,LCK,LCK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,HDK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,HDK,LWK,LWK,LWK,HDK,LWK,LWK,LWK \ +} + +#define RSC_SYSINFO_PWR_THERMAL_COND0_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_SYSINFO_PWR_THERMAL_COND1_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,LWK,LWK \ +} + +#define RSC_SYSINFO_PWR_THERMAL_COND2_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LGK,LGK,LGK,LGK,LGK,LGK,LGK,LWK,LWK \ +} + +#define RSC_SYSINFO_PWR_THERMAL_COND3_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,HGK,HGK,HGK,HGK,HGK,HGK,HGK,LWK,LWK \ +} + +#define RSC_SYSINFO_PWR_THERMAL_COND4_THM_USR2_ATTR \ +{ \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK, \ + HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK \ +} + +#define RSC_SYSINFO_PWR_THERMAL_COND5_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_SYSINFO_PWR_THERMAL_COND6_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HWK, \ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK \ +} + +#define RSC_SYSINFO_KERNEL_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_TOPOLOGY_COND0_THM_USR2_ATTR \ +{ \ + HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK \ +} + +#define RSC_TOPOLOGY_COND1_THM_USR2_ATTR \ +{ \ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK \ +} + +#define RSC_TOPOLOGY_COND2_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_TOPOLOGY_COND3_THM_USR2_ATTR \ +{ \ + LCK,LCK,LCK,HDK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK \ +} + +#define RSC_TOPOLOGY_COND4_THM_USR2_ATTR \ +{ \ + LBK,LBK,LBK,HDK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK \ +} + +#define RSC_MEMORY_CONTROLLER_COND0_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_MEMORY_CONTROLLER_COND1_THM_USR2_ATTR \ +{ \ + HWK,HWK,HWK,HWK,HWK \ +} + +#define RSC_CREATE_MENU_DISABLE_THM_USR2_ATTR \ +{ \ + HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW, \ + HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW,HKW \ +} + +#define RSC_MENU_ITEM_MENU_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,HKW,_LWK,_LWK,HKW,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK, LWK, LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_MENU_ITEM_VIEW_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,HKW,_LWK,_LWK,HKW,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK, LWK, LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_MENU_ITEM_WINDOW_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,HKW,_LWK,_LWK,HKW,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK, LWK, LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_MENU_FN_KEY_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,HKW,_LWK,_LWK,HKW,LWK \ +} + +#define RSC_CREATE_MENU_SHORTKEY_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HKW,_LWK,HKW,LWK \ +} + +#define RSC_CREATE_MENU_CTRL_KEY_THM_USR2_ATTR \ +{ \ + LWK,LWK, LWK, LWK, LWK, LWK,LWK,LWK,LWK, LWK,LWK,LWK, \ + LWK,HKW,_LWK,_LWK,_LWK,_LWK,HKW,HKW,HKW,_LWK,HKW,LWK \ +} + +#define RSC_CREATE_SETTINGS_COND0_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,HDK,LWK \ +} + +#define RSC_CREATE_SETTINGS_COND1_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,HGK,HGK,HGK,HDK,LWK \ +} + +#define RSC_CREATE_ADV_HELP_COND0_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_ADV_HELP_COND1_THM_USR2_ATTR \ +{ \ + LWK,HCK,HCK,HCK,HCK,HCK,HCK,HCK,HCK,HCK, \ + HCK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_HOTPLUG_CPU_ENABLE_THM_USR2_ATTR \ +{ \ + LWK,LGK,LGK,LGK,LGK,LGK,LGK,LGK,LGK,LGK,LGK,LWK,LDK,LDK,LDK \ +} + +#define RSC_CREATE_HOTPLUG_CPU_DISABLE_THM_USR2_ATTR \ +{ \ + LWK,LCK,LCK,LCK,LCK,LCK,LCK,LCK,LCK,LCK,LCK,LWK,LDK,LDK,LDK \ +} + +#define RSC_CREATE_HOTPLUG_CPU_ONLINE_THM_USR2_ATTR \ +{ \ + LCK,LCK,LCK,LCK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_HOTPLUG_CPU_OFFLINE_THM_USR2_ATTR \ +{ \ + LBK,LBK,LBK,LBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK \ +} + +#define RSC_CREATE_RATIO_CLOCK_COND0_THM_USR2_ATTR \ +{ \ + LWK,HWK,HWK,HWK,HWK,LWK,HWK,HWK,LWK,HDK,HDK,HDK,LWK,LWK, \ + LWK,LWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_RATIO_CLOCK_COND1_THM_USR2_ATTR \ +{ \ + LWK,HBK,HBK,HBK,HBK,LBK,HBK,HBK,LWK,HDK,HDK,HDK,LWK,LWK, \ + LWK,LWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_RATIO_CLOCK_COND2_THM_USR2_ATTR \ +{ \ + LWK,HRK,HRK,HRK,HRK,LRK,HRK,HRK,LWK,HDK,HDK,HDK,LWK,LWK, \ + LWK,LWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_RATIO_CLOCK_COND3_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,HCK,HCK,HCK,HCK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_RATIO_CLOCK_COND4_THM_USR2_ATTR \ +{ \ + LWK,HWK,HWK,HWK,HWK,LWK,HWK,HWK,LWK,HDK,HDK,HDK,LWK,LWK, \ + LWK,LWK,HCK,HCK,HCK,HCK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_RATIO_CLOCK_COND5_THM_USR2_ATTR \ +{ \ + LWK,HBK,HBK,HBK,HBK,LBK,HBK,HBK,LWK,HDK,HDK,HDK,LWK,LWK, \ + LWK,LWK,HCK,HCK,HCK,HCK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_RATIO_CLOCK_COND6_THM_USR2_ATTR \ +{ \ + LWK,HRK,HRK,HRK,HRK,LRK,HRK,HRK,LWK,HDK,HDK,HDK,LWK,LWK, \ + LWK,LWK,HCK,HCK,HCK,HCK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_SELECT_CPU_COND0_THM_USR2_ATTR \ +{ \ + LBK,LBK,LBK,LBK,LBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK, \ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK, \ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK \ +} + +#define RSC_CREATE_SELECT_CPU_COND1_THM_USR2_ATTR \ +{ \ + LCK,LCK,LCK,LCK,LCK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LCK,LCK,LCK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_SELECT_CPU_COND2_THM_USR2_ATTR \ +{ \ + LCK,LCK,LCK,LCK,LCK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,HRK,HRK,HRK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_HOT_EVENT_COND0_THM_USR2_ATTR \ +{ \ + HDK,HDK,HDK \ +} + +#define RSC_HOT_EVENT_COND1_THM_USR2_ATTR \ +{ \ + HRK,HRK,HRK \ +} + +#define RSC_HOT_EVENT_COND2_THM_USR2_ATTR \ +{ \ + {.fg=CYAN,.bg=BLACK,.bf=1,.un=1}, \ + {.fg=CYAN,.bg=BLACK,.bf=0,.un=0}, \ + {.fg=CYAN,.bg=BLACK,.bf=0,.un=0} \ +} + +#define RSC_HOT_EVENT_COND3_THM_USR2_ATTR \ +{ \ + HWK,HWK,HWK \ +} + +#define RSC_HOT_EVENT_COND4_THM_USR2_ATTR \ +{ \ + {.fg=CYAN,.bg=MAGENTA,.bf=0,.un=1}, \ + {.fg=CYAN,.bg=MAGENTA,.bf=0,.un=0}, \ + {.fg=CYAN,.bg=MAGENTA,.bf=0,.un=0} \ +} + +#define RSC_BOX_EVENT_COND00_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK \ +} + +#define RSC_BOX_EVENT_COND01_THM_USR2_ATTR \ +{ \ + LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,HDK \ +} + +#define RSC_BOX_EVENT_COND10_THM_USR2_ATTR \ +{ \ + LKY,LKY,LKY,LKY,LKY,LKY,LKY,LKY,LKY,LKY,LKY,LKY,LKY,LKY,LKY,LKY,HDK \ +} + +#define RSC_BOX_EVENT_COND11_THM_USR2_ATTR \ +{ \ + LKY,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LWM,LKY,HDK \ +} + +#define RSC_BOX_EVENT_BUTTON_THM_USR2_ATTR \ +{ \ + LWK,HCK,HCK,HCK,HCK,HCK,HCK,HCK,HCK,HCK,HCK,HCK,HCK,HCK,HCK,HCK,LWK \ +} + +#define RSC_CREATE_RECORDER_THM_USR2_ATTR \ +{ \ + LWK,LWK,LWK,LWK,HDK,LWK,LWK,HDK,LWK,LWK,LWK,LWK \ +} + +#define RSC_SMBIOS_ITEM_THM_USR2_ATTR \ +{ \ + HDK,LCK,LCK,HDK,HDK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_SELECT_FREQ_PKG_THM_USR2_ATTR \ +{ \ + HYK,HYK,HYK,HYK,HYK,HYK,HYK,HYK,HYK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HYK,HYK,HYK,HYK,HYK,HYK,\ + HYK,HYK,HDK,HDK,HDK,LWK,LWK,HYK,HYK,HYK,HYK,HYK,LWK,LWK \ +} + +#define RSC_CREATE_SELECT_FREQ_COND0_THM_USR2_ATTR \ +{ \ + LCK,LCK,LCK,LCK,LCK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,HDK,HDK, \ + LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \ +} + +#define RSC_CREATE_SELECT_FREQ_COND1_THM_USR2_ATTR \ +{ \ + LBK,LBK,LBK,LBK,LBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK, \ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK, \ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK, \ + HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK,HBK \ +} + +_Static_assert( __builtin_strlen(RSC_THEME_USR2_CODE) + == __builtin_strlen(RSC_BOX_THEME_BLANK_CODE), +"Mandatory string length"); diff --git a/aarch64/corefreq-cli-rsc.c b/aarch64/corefreq-cli-rsc.c new file mode 100644 index 00000000..4ed423ad --- /dev/null +++ b/aarch64/corefreq-cli-rsc.c @@ -0,0 +1,1615 @@ +/* + * CoreFreq + * Copyright (C) 2015-2024 CYRIL COURTIAT + * Licenses: GPL2 + */ + +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include + +#include "bitasm.h" +#include "corefreq-ui.h" +#include "corefreq-cli-rsc.h" +#include "corefreq-cli-rsc-en.h" +#include "corefreq-cli-rsc-fr.h" +#include "corefreq-cli-rsc-theme-dflt.h" +#include "corefreq-cli-rsc-theme-usr1.h" +#include "corefreq-cli-rsc-theme-usr2.h" + +#define DEF_LDA(_rsc) \ +ATTRIBUTE _rsc##_##ATTR_ARRAY \ + [THM_CNT] \ + [(sizeof((ATTRIBUTE[]) _rsc##_##THM_DFLT_ATTR) / sizeof(ATTRIBUTE))] = \ +{ \ + [THM_DFLT] = _rsc##_##THM_DFLT_ATTR, \ + [THM_USR1] = _rsc##_##THM_USR1_ATTR, \ + [THM_USR2] = _rsc##_##THM_USR2_ATTR \ +}; \ +ASCII _rsc##_##CODE_EN_ARRAY[] = _rsc##_##CODE_EN, \ + _rsc##_##CODE_FR_ARRAY[] = _rsc##_##CODE_FR + +#define DEF_LDB(_rsc) \ +ATTRIBUTE _rsc##_##ATTR_ARRAY \ + [THM_CNT] \ + [(sizeof((ATTRIBUTE[]) _rsc##_##THM_DFLT_ATTR) / sizeof(ATTRIBUTE))] = \ +{ \ + [THM_DFLT] = _rsc##_##THM_DFLT_ATTR, \ + [THM_USR1] = _rsc##_##THM_USR1_ATTR, \ + [THM_USR2] = _rsc##_##THM_USR2_ATTR \ +} + +#define LDV(attr_var, en_var, fr_var) \ + .Attr = { \ + [THM_DFLT] = attr_var[THM_DFLT], \ + [THM_USR1] = attr_var[THM_USR1], \ + [THM_USR2] = attr_var[THM_USR2] \ + }, \ + .Code = { \ + [LOC_EN] = (ASCII*) en_var, \ + [LOC_FR] = (ASCII*) fr_var \ + } + +#define LDA(_rsc) \ +[_rsc] = { \ + LDV(_rsc##_ATTR_ARRAY, _rsc##_CODE_EN_ARRAY, _rsc##_CODE_FR_ARRAY),\ + .Size = { \ + [LOC_EN] = sizeof(_rsc##_CODE_EN_ARRAY), \ + [LOC_FR] = sizeof(_rsc##_CODE_FR_ARRAY) \ + } \ +} + +#define LDB(_rsc) \ +[_rsc] = { \ + LDV(_rsc##_ATTR_ARRAY, hSpace, hSpace) , \ + .Size = { \ + [LOC_EN] = sizeof(HSPACE), \ + [LOC_FR] = sizeof(HSPACE) \ + } \ +} + +#define LDS(_rsc) \ +[_rsc] = { \ + LDV(_rsc##_ATTR_ARRAY, _rsc##_CODE_EN, _rsc##_CODE_FR) , \ + .Size = { \ + [LOC_EN] = __builtin_strlen(_rsc##_CODE_EN), \ + [LOC_FR] = __builtin_strlen(_rsc##_CODE_FR) \ + } \ +} + +#define LDT(_rsc) \ +[_rsc] = { \ + LDV(RSC_VOID_ATTR_ARRAY, _rsc##_CODE_EN, _rsc##_CODE_FR), \ + .Size = { \ + [LOC_EN] = __builtin_strlen(_rsc##_CODE_EN), \ + [LOC_FR] = __builtin_strlen(_rsc##_CODE_FR) \ + } \ +} + +#define LDC(_rsc, _ref) \ +[_rsc] = { \ + LDV(_ref##_ATTR_ARRAY, _rsc##_CODE_EN, _rsc##_CODE_FR) , \ + .Size = { \ + [LOC_EN] = __builtin_strlen(_rsc##_CODE_EN), \ + [LOC_FR] = __builtin_strlen(_rsc##_CODE_FR) \ + } \ +} + +#define LDQ(_rsc) \ +[_rsc] = { \ + LDV(RSC_VOID_ATTR_ARRAY, _rsc##_CODE, _rsc##_CODE), \ + .Size = { \ + [LOC_EN] = __builtin_strlen(_rsc##_CODE), \ + [LOC_FR] = __builtin_strlen(_rsc##_CODE) \ + } \ +} + +DEF_LDB(RSC_UI); +DEF_LDB(RSC_VOID); + +#ifndef NO_HEADER +DEF_LDA(RSC_LAYOUT_HEADER_PROC); +DEF_LDA(RSC_LAYOUT_HEADER_CPU); +DEF_LDA(RSC_LAYOUT_HEADER_ARCH); +DEF_LDA(RSC_LAYOUT_HEADER_CACHE_L1); +DEF_LDA(RSC_LAYOUT_HEADER_BCLK); +DEF_LDA(RSC_LAYOUT_HEADER_CACHES); +#endif /* NO_HEADER */ + +#ifndef NO_UPPER +DEF_LDA(RSC_LAYOUT_RULER_LOAD); +DEF_LDA(RSC_LAYOUT_RULER_REL_LOAD); +DEF_LDA(RSC_LAYOUT_RULER_ABS_LOAD); +#endif /* NO_UPPER */ + +#ifndef NO_LOWER +DEF_LDA(RSC_LAYOUT_MONITOR_FREQUENCY); +DEF_LDA(RSC_LAYOUT_MONITOR_INST); +DEF_LDA(RSC_LAYOUT_MONITOR_COMMON); +DEF_LDA(RSC_LAYOUT_MONITOR_TASKS); +DEF_LDA(RSC_LAYOUT_MONITOR_SLICE); +DEF_LDA(RSC_LAYOUT_CUSTOM_FIELD); +DEF_LDA(RSC_LAYOUT_RULER_FREQUENCY); +DEF_LDA(RSC_LAYOUT_RULER_FREQUENCY_AVG); +DEF_LDA(RSC_LAYOUT_RULER_FREQUENCY_PKG); +DEF_LDA(RSC_LAYOUT_RULER_INST); +DEF_LDA(RSC_LAYOUT_RULER_CYCLES); +DEF_LDA(RSC_LAYOUT_RULER_CSTATES); +DEF_LDA(RSC_LAYOUT_RULER_INTERRUPTS); +DEF_LDA(RSC_LAYOUT_RULER_PACKAGE); +DEF_LDA(RSC_LAYOUT_PACKAGE_PC); +DEF_LDA(RSC_LAYOUT_PACKAGE_PC02); +DEF_LDA(RSC_LAYOUT_PACKAGE_PC03); +DEF_LDA(RSC_LAYOUT_PACKAGE_PC04); +DEF_LDA(RSC_LAYOUT_PACKAGE_PC06); +DEF_LDA(RSC_LAYOUT_PACKAGE_PC07); +DEF_LDA(RSC_LAYOUT_PACKAGE_PC08); +DEF_LDA(RSC_LAYOUT_PACKAGE_PC09); +DEF_LDA(RSC_LAYOUT_PACKAGE_PC10); +DEF_LDA(RSC_LAYOUT_PACKAGE_MC06); +DEF_LDA(RSC_LAYOUT_PACKAGE_UNCORE); +DEF_LDA(RSC_LAYOUT_RULER_TASKS); +DEF_LDA(RSC_LAYOUT_TASKS_TRACKING); +DEF_LDA(RSC_LAYOUT_TASKS_STATE_SORTED); +DEF_LDA(RSC_LAYOUT_TASKS_RUNTIME_SORTED); +DEF_LDA(RSC_LAYOUT_TASKS_USRTIME_SORTED); +DEF_LDA(RSC_LAYOUT_TASKS_SYSTIME_SORTED); +DEF_LDA(RSC_LAYOUT_TASKS_PROCESS_SORTED); +DEF_LDA(RSC_LAYOUT_TASKS_COMMAND_SORTED); +DEF_LDA(RSC_LAYOUT_TASKS_REVERSE_SORT_OFF); +DEF_LDA(RSC_LAYOUT_TASKS_REVERSE_SORT_ON); +DEF_LDA(RSC_LAYOUT_TASKS_VALUE_SWITCH); +DEF_LDA(RSC_LAYOUT_TASKS_VALUE_OFF); +DEF_LDA(RSC_LAYOUT_TASKS_VALUE_ON); +DEF_LDA(RSC_LAYOUT_RULER_SENSORS); +DEF_LDA(RSC_LAYOUT_RULER_PWR_SOC); +DEF_LDA(RSC_LAYOUT_RULER_VOLTAGE); +DEF_LDA(RSC_LAYOUT_RULER_VPKG_SOC); +DEF_LDA(RSC_LAYOUT_RULER_ENERGY); +DEF_LDA(RSC_LAYOUT_RULER_POWER); +DEF_LDA(RSC_LAYOUT_RULER_SLICE); +DEF_LDA(RSC_LAYOUT_RULER_CUSTOM); +#endif /* NO_LOWER */ + +#ifndef NO_FOOTER +DEF_LDA(RSC_LAYOUT_FOOTER_TECH_TSC); +DEF_LDA(RSC_LAYOUT_FOOTER_VOLT_TEMP); +DEF_LDA(RSC_LAYOUT_FOOTER_SYSTEM); +#endif /* NO_FOOTER */ + +DEF_LDA(RSC_LAYOUT_CARD_CORE_ONLINE_COND0); +DEF_LDA(RSC_LAYOUT_CARD_CORE_ONLINE_COND1); +DEF_LDA(RSC_LAYOUT_CARD_CORE_OFFLINE); +DEF_LDA(RSC_LAYOUT_CARD_CLK); +DEF_LDA(RSC_LAYOUT_CARD_UNCORE); +DEF_LDA(RSC_LAYOUT_CARD_BUS); +DEF_LDA(RSC_LAYOUT_CARD_MC); +DEF_LDA(RSC_LAYOUT_CARD_LOAD); +DEF_LDA(RSC_LAYOUT_CARD_IDLE); +DEF_LDA(RSC_LAYOUT_CARD_RAM); +DEF_LDA(RSC_LAYOUT_CARD_TASK); + +DEF_LDB(RSC_RUN_STATE_COLOR); +DEF_LDB(RSC_UNINT_STATE_COLOR); +DEF_LDB(RSC_ZOMBIE_STATE_COLOR); +DEF_LDB(RSC_SLEEP_STATE_COLOR); +DEF_LDB(RSC_WAIT_STATE_COLOR); +DEF_LDB(RSC_OTHER_STATE_COLOR); +DEF_LDB(RSC_TRACKER_STATE_COLOR); + +DEF_LDB(RSC_SYSTEM_REGISTERS_COND0); +DEF_LDB(RSC_SYSTEM_REGISTERS_COND1); +DEF_LDB(RSC_SYSTEM_REGISTERS_COND2); +DEF_LDB(RSC_SYSTEM_REGISTERS_COND3); +DEF_LDB(RSC_SYSTEM_REGISTERS_COND4); + +DEF_LDB(RSC_SYSINFO_PROC_COND0); +DEF_LDB(RSC_SYSINFO_PROC_COND1); +DEF_LDB(RSC_SYSINFO_PROC_COND2); +DEF_LDB(RSC_SYSINFO_PROC_COND3); + +DEF_LDB(RSC_SYSINFO_ISA_COND_0_0); +DEF_LDB(RSC_SYSINFO_ISA_COND_0_1); +DEF_LDB(RSC_SYSINFO_ISA_COND_0_2); +DEF_LDB(RSC_SYSINFO_ISA_COND_0_3); +DEF_LDB(RSC_SYSINFO_ISA_COND_0_4); + +DEF_LDB(RSC_SYSINFO_ISA_COND_1_0); +DEF_LDB(RSC_SYSINFO_ISA_COND_1_1); +DEF_LDB(RSC_SYSINFO_ISA_COND_1_2); +DEF_LDB(RSC_SYSINFO_ISA_COND_1_3); +DEF_LDB(RSC_SYSINFO_ISA_COND_1_4); + +DEF_LDB(RSC_SYSINFO_FEATURES_COND0); +DEF_LDB(RSC_SYSINFO_FEATURES_COND1); +DEF_LDB(RSC_SYSINFO_FEATURES_COND2); +DEF_LDB(RSC_SYSINFO_FEATURES_COND3); +DEF_LDB(RSC_SYSINFO_FEATURES_COND4); + +DEF_LDB(RSC_SYSINFO_TECH_COND0); +DEF_LDB(RSC_SYSINFO_TECH_COND1); + +DEF_LDB(RSC_SYSINFO_PERFMON_COND0); +DEF_LDB(RSC_SYSINFO_PERFMON_COND1); +DEF_LDB(RSC_SYSINFO_PERFMON_COND2); +DEF_LDB(RSC_SYSINFO_PERFMON_COND3); +DEF_LDB(RSC_SYSINFO_PERFMON_COND4); + +DEF_LDB(RSC_SYSINFO_PERFMON_HWP_CAP_COND0); +DEF_LDB(RSC_SYSINFO_PERFMON_HWP_CAP_COND1); + +DEF_LDB(RSC_SYSINFO_PWR_THERMAL_COND0); +DEF_LDB(RSC_SYSINFO_PWR_THERMAL_COND1); +DEF_LDB(RSC_SYSINFO_PWR_THERMAL_COND2); +DEF_LDB(RSC_SYSINFO_PWR_THERMAL_COND3); +DEF_LDB(RSC_SYSINFO_PWR_THERMAL_COND4); +DEF_LDB(RSC_SYSINFO_PWR_THERMAL_COND5); +DEF_LDB(RSC_SYSINFO_PWR_THERMAL_COND6); + +DEF_LDB(RSC_SYSINFO_KERNEL); + +DEF_LDB(RSC_TOPOLOGY_COND0); +DEF_LDB(RSC_TOPOLOGY_COND1); +DEF_LDB(RSC_TOPOLOGY_COND2); +DEF_LDB(RSC_TOPOLOGY_COND3); +DEF_LDB(RSC_TOPOLOGY_COND4); + +DEF_LDB(RSC_MEMORY_CONTROLLER_COND0); +DEF_LDB(RSC_MEMORY_CONTROLLER_COND1); + +DEF_LDB(RSC_CREATE_MENU_DISABLE); +DEF_LDB(RSC_MENU_ITEM_MENU); +DEF_LDB(RSC_MENU_ITEM_VIEW); +DEF_LDB(RSC_MENU_ITEM_WINDOW); +DEF_LDB(RSC_CREATE_MENU_FN_KEY); +DEF_LDB(RSC_CREATE_MENU_SHORTKEY); +DEF_LDB(RSC_CREATE_MENU_CTRL_KEY); + +DEF_LDB(RSC_CREATE_SETTINGS_COND0); +DEF_LDB(RSC_CREATE_SETTINGS_COND1); + +DEF_LDB(RSC_CREATE_ADV_HELP_COND0); +DEF_LDB(RSC_CREATE_ADV_HELP_COND1); + +DEF_LDB(RSC_CREATE_HOTPLUG_CPU_ENABLE); +DEF_LDB(RSC_CREATE_HOTPLUG_CPU_DISABLE); +DEF_LDB(RSC_CREATE_HOTPLUG_CPU_ONLINE); +DEF_LDB(RSC_CREATE_HOTPLUG_CPU_OFFLINE); + +DEF_LDB(RSC_CREATE_RATIO_CLOCK_COND0); +DEF_LDB(RSC_CREATE_RATIO_CLOCK_COND1); +DEF_LDB(RSC_CREATE_RATIO_CLOCK_COND2); +DEF_LDB(RSC_CREATE_RATIO_CLOCK_COND3); +DEF_LDB(RSC_CREATE_RATIO_CLOCK_COND4); +DEF_LDB(RSC_CREATE_RATIO_CLOCK_COND5); +DEF_LDB(RSC_CREATE_RATIO_CLOCK_COND6); + +DEF_LDB(RSC_CREATE_SELECT_CPU_COND0); +DEF_LDB(RSC_CREATE_SELECT_CPU_COND1); +DEF_LDB(RSC_CREATE_SELECT_CPU_COND2); + +#ifndef NO_FOOTER +DEF_LDB(RSC_HOT_EVENT_COND0); +DEF_LDB(RSC_HOT_EVENT_COND1); +DEF_LDB(RSC_HOT_EVENT_COND2); +DEF_LDB(RSC_HOT_EVENT_COND3); +DEF_LDB(RSC_HOT_EVENT_COND4); +#endif + +DEF_LDB(RSC_BOX_EVENT_COND00); +DEF_LDB(RSC_BOX_EVENT_COND01); +DEF_LDB(RSC_BOX_EVENT_COND10); +DEF_LDB(RSC_BOX_EVENT_COND11); +DEF_LDB(RSC_BOX_EVENT_BUTTON); + +DEF_LDB(RSC_CREATE_RECORDER); +DEF_LDB(RSC_SMBIOS_ITEM); + +DEF_LDB(RSC_CREATE_SELECT_FREQ_PKG); +DEF_LDB(RSC_CREATE_SELECT_FREQ_COND0); +DEF_LDB(RSC_CREATE_SELECT_FREQ_COND1); + +RESOURCE_ST Resource[] = { + LDB(RSC_UI), + LDB(RSC_VOID), + LDQ(RSC_THEME_DFLT), + LDQ(RSC_THEME_USR1), + LDQ(RSC_THEME_USR2), + LDQ(RSC_LAYOUT_LCD_RESET), +#ifndef NO_HEADER + LDA(RSC_LAYOUT_HEADER_PROC), + LDA(RSC_LAYOUT_HEADER_CPU), + LDA(RSC_LAYOUT_HEADER_ARCH), + LDA(RSC_LAYOUT_HEADER_CACHE_L1), + LDA(RSC_LAYOUT_HEADER_BCLK), + LDA(RSC_LAYOUT_HEADER_CACHES), +#endif /* NO_HEADER */ +#ifndef NO_UPPER + LDA(RSC_LAYOUT_RULER_LOAD), + LDA(RSC_LAYOUT_RULER_REL_LOAD), + LDA(RSC_LAYOUT_RULER_ABS_LOAD), +#endif /* NO_UPPER */ +#ifndef NO_LOWER + LDA(RSC_LAYOUT_MONITOR_FREQUENCY), + LDA(RSC_LAYOUT_MONITOR_INST), + LDA(RSC_LAYOUT_MONITOR_COMMON), + LDA(RSC_LAYOUT_MONITOR_TASKS), + LDA(RSC_LAYOUT_MONITOR_SLICE), + LDA(RSC_LAYOUT_CUSTOM_FIELD), + LDA(RSC_LAYOUT_RULER_FREQUENCY), + LDA(RSC_LAYOUT_RULER_FREQUENCY_AVG), + LDA(RSC_LAYOUT_RULER_FREQUENCY_PKG), + LDA(RSC_LAYOUT_RULER_INST), + LDA(RSC_LAYOUT_RULER_CYCLES), + LDA(RSC_LAYOUT_RULER_CSTATES), + LDA(RSC_LAYOUT_RULER_INTERRUPTS), + LDA(RSC_LAYOUT_RULER_PACKAGE), + LDA(RSC_LAYOUT_PACKAGE_PC), + LDA(RSC_LAYOUT_PACKAGE_PC02), + LDA(RSC_LAYOUT_PACKAGE_PC03), + LDA(RSC_LAYOUT_PACKAGE_PC04), + LDA(RSC_LAYOUT_PACKAGE_PC06), + LDA(RSC_LAYOUT_PACKAGE_PC07), + LDA(RSC_LAYOUT_PACKAGE_PC08), + LDA(RSC_LAYOUT_PACKAGE_PC09), + LDA(RSC_LAYOUT_PACKAGE_PC10), + LDA(RSC_LAYOUT_PACKAGE_MC06), + LDA(RSC_LAYOUT_PACKAGE_UNCORE), + LDA(RSC_LAYOUT_RULER_TASKS), + LDA(RSC_LAYOUT_TASKS_TRACKING), + LDA(RSC_LAYOUT_TASKS_STATE_SORTED), + LDA(RSC_LAYOUT_TASKS_RUNTIME_SORTED), + LDA(RSC_LAYOUT_TASKS_USRTIME_SORTED), + LDA(RSC_LAYOUT_TASKS_SYSTIME_SORTED), + LDA(RSC_LAYOUT_TASKS_PROCESS_SORTED), + LDA(RSC_LAYOUT_TASKS_COMMAND_SORTED), + LDA(RSC_LAYOUT_TASKS_REVERSE_SORT_OFF), + LDA(RSC_LAYOUT_TASKS_REVERSE_SORT_ON), + LDA(RSC_LAYOUT_TASKS_VALUE_SWITCH), + LDA(RSC_LAYOUT_TASKS_VALUE_OFF), + LDA(RSC_LAYOUT_TASKS_VALUE_ON), + LDA(RSC_LAYOUT_RULER_SENSORS), + LDA(RSC_LAYOUT_RULER_PWR_SOC), + LDA(RSC_LAYOUT_RULER_VOLTAGE), + LDA(RSC_LAYOUT_RULER_VPKG_SOC), + LDA(RSC_LAYOUT_RULER_ENERGY), + LDA(RSC_LAYOUT_RULER_POWER), + LDA(RSC_LAYOUT_RULER_SLICE), + LDA(RSC_LAYOUT_RULER_CUSTOM), +#endif /* NO_LOWER */ +#ifndef NO_FOOTER + LDA(RSC_LAYOUT_FOOTER_TECH_TSC), + LDA(RSC_LAYOUT_FOOTER_VOLT_TEMP), + LDA(RSC_LAYOUT_FOOTER_SYSTEM), + LDQ(RSC_LAYOUT_FOOTER_TSC_NONE), + LDQ(RSC_LAYOUT_FOOTER_TSC_VAR), + LDQ(RSC_LAYOUT_FOOTER_TSC_INV), +#endif /* NO_FOOTER */ + LDA(RSC_LAYOUT_CARD_CORE_ONLINE_COND0), + LDA(RSC_LAYOUT_CARD_CORE_ONLINE_COND1), + LDA(RSC_LAYOUT_CARD_CORE_OFFLINE), + LDA(RSC_LAYOUT_CARD_CLK), + LDA(RSC_LAYOUT_CARD_UNCORE), + LDA(RSC_LAYOUT_CARD_BUS), + LDA(RSC_LAYOUT_CARD_MC), + LDA(RSC_LAYOUT_CARD_LOAD), + LDA(RSC_LAYOUT_CARD_IDLE), + LDA(RSC_LAYOUT_CARD_RAM), + LDA(RSC_LAYOUT_CARD_TASK), +/* ATTRIBUTE */ + LDB(RSC_RUN_STATE_COLOR), + LDB(RSC_UNINT_STATE_COLOR), + LDB(RSC_ZOMBIE_STATE_COLOR), + LDB(RSC_SLEEP_STATE_COLOR), + LDB(RSC_WAIT_STATE_COLOR), + LDB(RSC_OTHER_STATE_COLOR), +#ifndef NO_LOWER + LDB(RSC_TRACKER_STATE_COLOR), +#endif + LDB(RSC_SYSTEM_REGISTERS_COND0), + LDB(RSC_SYSTEM_REGISTERS_COND1), + LDB(RSC_SYSTEM_REGISTERS_COND2), + LDB(RSC_SYSTEM_REGISTERS_COND3), + LDB(RSC_SYSTEM_REGISTERS_COND4), + LDB(RSC_SYSINFO_PROC_COND0), + LDB(RSC_SYSINFO_PROC_COND1), + LDB(RSC_SYSINFO_PROC_COND2), + LDB(RSC_SYSINFO_PROC_COND3), + LDB(RSC_SYSINFO_ISA_COND_0_0), + LDB(RSC_SYSINFO_ISA_COND_0_1), + LDB(RSC_SYSINFO_ISA_COND_0_2), + LDB(RSC_SYSINFO_ISA_COND_0_3), + LDB(RSC_SYSINFO_ISA_COND_0_4), + LDB(RSC_SYSINFO_ISA_COND_1_0), + LDB(RSC_SYSINFO_ISA_COND_1_1), + LDB(RSC_SYSINFO_ISA_COND_1_2), + LDB(RSC_SYSINFO_ISA_COND_1_3), + LDB(RSC_SYSINFO_ISA_COND_1_4), + LDB(RSC_SYSINFO_FEATURES_COND0), + LDB(RSC_SYSINFO_FEATURES_COND1), + LDB(RSC_SYSINFO_FEATURES_COND2), + LDB(RSC_SYSINFO_FEATURES_COND3), + LDB(RSC_SYSINFO_FEATURES_COND4), + LDB(RSC_SYSINFO_TECH_COND0), + LDB(RSC_SYSINFO_TECH_COND1), + LDB(RSC_SYSINFO_PERFMON_COND0), + LDB(RSC_SYSINFO_PERFMON_COND1), + LDB(RSC_SYSINFO_PERFMON_COND2), + LDB(RSC_SYSINFO_PERFMON_COND3), + LDB(RSC_SYSINFO_PERFMON_COND4), + LDB(RSC_SYSINFO_PERFMON_HWP_CAP_COND0), + LDB(RSC_SYSINFO_PERFMON_HWP_CAP_COND1), + LDB(RSC_SYSINFO_PWR_THERMAL_COND0), + LDB(RSC_SYSINFO_PWR_THERMAL_COND1), + LDB(RSC_SYSINFO_PWR_THERMAL_COND2), + LDB(RSC_SYSINFO_PWR_THERMAL_COND3), + LDB(RSC_SYSINFO_PWR_THERMAL_COND4), + LDB(RSC_SYSINFO_PWR_THERMAL_COND5), + LDB(RSC_SYSINFO_PWR_THERMAL_COND6), + LDB(RSC_SYSINFO_KERNEL), + LDB(RSC_TOPOLOGY_COND0), + LDB(RSC_TOPOLOGY_COND1), + LDB(RSC_TOPOLOGY_COND2), + LDB(RSC_TOPOLOGY_COND3), + LDB(RSC_TOPOLOGY_COND4), + LDB(RSC_MEMORY_CONTROLLER_COND0), + LDB(RSC_MEMORY_CONTROLLER_COND1), + LDB(RSC_CREATE_MENU_DISABLE), + LDB(RSC_CREATE_MENU_FN_KEY), + LDB(RSC_CREATE_MENU_SHORTKEY), + LDB(RSC_CREATE_MENU_CTRL_KEY), + LDS(RSC_CREATE_SETTINGS_COND0), + LDS(RSC_CREATE_SETTINGS_COND1), + LDS(RSC_CREATE_ADV_HELP_COND0), + LDS(RSC_CREATE_ADV_HELP_COND1), + LDQ(RSC_CREATE_HOTPLUG_CPU_TITLE), + LDS(RSC_CREATE_HOTPLUG_CPU_ENABLE), + LDS(RSC_CREATE_HOTPLUG_CPU_DISABLE), + LDS(RSC_CREATE_HOTPLUG_CPU_ONLINE), + LDS(RSC_CREATE_HOTPLUG_CPU_OFFLINE), + LDB(RSC_CREATE_RATIO_CLOCK_COND0), + LDB(RSC_CREATE_RATIO_CLOCK_COND1), + LDB(RSC_CREATE_RATIO_CLOCK_COND2), + LDB(RSC_CREATE_RATIO_CLOCK_COND3), + LDB(RSC_CREATE_RATIO_CLOCK_COND4), + LDB(RSC_CREATE_RATIO_CLOCK_COND5), + LDB(RSC_CREATE_RATIO_CLOCK_COND6), + LDB(RSC_CREATE_SELECT_CPU_COND0), + LDB(RSC_CREATE_SELECT_CPU_COND1), + LDB(RSC_CREATE_SELECT_CPU_COND2), +#ifndef NO_FOOTER + LDB(RSC_HOT_EVENT_COND0), + LDB(RSC_HOT_EVENT_COND1), + LDB(RSC_HOT_EVENT_COND2), + LDB(RSC_HOT_EVENT_COND3), + LDB(RSC_HOT_EVENT_COND4), +#endif + LDB(RSC_BOX_EVENT_COND00), + LDB(RSC_BOX_EVENT_COND01), + LDB(RSC_BOX_EVENT_COND10), + LDB(RSC_BOX_EVENT_COND11), + LDB(RSC_BOX_EVENT_BUTTON), + LDB(RSC_CREATE_RECORDER), + LDB(RSC_SMBIOS_ITEM), + LDB(RSC_CREATE_SELECT_FREQ_PKG), + LDB(RSC_CREATE_SELECT_FREQ_COND0), + LDB(RSC_CREATE_SELECT_FREQ_COND1), +/* ASCII */ + LDQ(RSC_COREFREQ_TITLE), + LDT(RSC_PROCESSOR_TITLE), + LDT(RSC_PROCESSOR), + LDT(RSC_ARCHITECTURE), + LDT(RSC_VENDOR_ID), + LDQ(RSC_HYBRID), + LDT(RSC_REVISION), + LDT(RSC_SIGNATURE), + LDT(RSC_STEPPING), + LDT(RSC_ONLINE_CPU), + LDT(RSC_BASE_CLOCK), + LDT(RSC_FREQUENCY), + LDT(RSC_RATIO), + LDT(RSC_FACTORY), + LDT(RSC_PERFORMANCE), + LDT(RSC_TARGET), + LDT(RSC_UNLOCK), + LDT(RSC_LOCK), + LDT(RSC_ENABLE), + LDT(RSC_DISABLE), + LDT(RSC_CAPABILITIES), + LDT(RSC_LOWEST), + LDT(RSC_EFFICIENT), + LDT(RSC_GUARANTEED), + LDT(RSC_HIGHEST), + LDT(RSC_RECORDER), + LDT(RSC_STRESS), + LDQ(RSC_SYSGATE), + LDQ(RSC_FREQ_UNIT_MHZ), + LDQ(RSC_PPIN), + LDQ(RSC_OPP), + LDQ(RSC_UNCORE), + LDQ(RSC_TURBO), + LDQ(RSC_CPPC), + LDQ(RSC_MAX), + LDQ(RSC_MIN), + LDQ(RSC_TGT), + LDQ(RSC_TBH), + LDQ(RSC_TBO), + LDQ(RSC_ACT), + LDT(RSC_SCOPE_NONE), + LDT(RSC_SCOPE_THREAD), + LDT(RSC_SCOPE_CORE), + LDT(RSC_SCOPE_PACKAGE), + LDT(RSC_SYS_REGS_TITLE), + LDQ(RSC_SYS_REGS_SPACE), + LDQ(RSC_SYS_REGS_NA), + LDQ(RSC_SYS_REGS_HDR_CPU), + LDQ(RSC_SYS_REG_HDR_FLAGS), + LDT(RSC_SYS_REG_PSTATE), + LDT(RSC_SYS_REG_FLAG_N), + LDT(RSC_SYS_REG_FLAG_Z), + LDT(RSC_SYS_REG_FLAG_C), + LDT(RSC_SYS_REG_FLAG_V), + LDT(RSC_SYS_REG_FLAG_D), + LDT(RSC_SYS_REG_FLAG_A), + LDT(RSC_SYS_REG_FLAG_I), + LDT(RSC_SYS_REG_FLAG_F), + LDT(RSC_SYS_REG_FLAG_EL), + LDT(RSC_SYS_REG_FLAG_SM), + LDT(RSC_SYS_REG_FLAG_SSBS), + LDT(RSC_SYS_REG_FLAG_NMI), + LDT(RSC_SYS_REG_FLAG_PAN), + LDT(RSC_SYS_REG_FLAG_UAO), + LDT(RSC_SYS_REG_FLAG_DIT), + LDT(RSC_SYS_REG_FLAG_TCO), + LDT(RSC_SYS_REG_FLAG_PM), + LDQ(RSC_SYS_REG_HDR11_SCTL), + LDQ(RSC_SYS_REG_HDR12_SCTL), + LDQ(RSC_SYS_REG_HDR21_SCTL), + LDQ(RSC_SYS_REG_HDR22_SCTL), + LDQ(RSC_SYS_REG_HDR31_SCTL), + LDQ(RSC_SYS_REG_HDR41_SCTL), + LDT(RSC_SYS_REG_SCTL), + LDT(RSC_SYS_REG_TIDCP), + LDT(RSC_SYS_REG_SPINT), + LDT(RSC_SYS_REG_NMI), + LDT(RSC_SYS_REG_EnTP2), + LDT(RSC_SYS_REG_TCSO), + LDT(RSC_SYS_REG_TCSO1), + LDT(RSC_SYS_REG_TCSO0), + LDT(RSC_SYS_REG_EPAN), + LDT(RSC_SYS_REG_EnALS), + LDT(RSC_SYS_REG_EnAS0), + LDT(RSC_SYS_REG_EnASR), + LDT(RSC_SYS_REG_TME), + LDT(RSC_SYS_REG_TME1), + LDT(RSC_SYS_REG_TME0), + LDT(RSC_SYS_REG_TMT), + LDT(RSC_SYS_REG_TMT1), + LDT(RSC_SYS_REG_TMT0), + LDT(RSC_SYS_REG_TWE_D), + LDT(RSC_SYS_REG_TWE_C), + LDT(RSC_SYS_REG_TWE_E), + LDT(RSC_SYS_REG_DSSBS), + LDT(RSC_SYS_REG_ATA), + LDT(RSC_SYS_REG_ATA1), + LDT(RSC_SYS_REG_ATA0), + LDT(RSC_SYS_REG_TCF), + LDT(RSC_SYS_REG_TCF1), + LDT(RSC_SYS_REG_TCF0), + LDT(RSC_SYS_REG_ITFSB), + LDT(RSC_SYS_REG_BT), + LDT(RSC_SYS_REG_BT1), + LDT(RSC_SYS_REG_BT0), + LDT(RSC_SYS_REG_EnFPM), + LDT(RSC_SYS_REG_MSCEn), + LDT(RSC_SYS_REG_CMOW), + LDT(RSC_SYS_REG_EnIA), + LDT(RSC_SYS_REG_EnIB), + LDT(RSC_SYS_REG_LSM), + LDT(RSC_SYS_REG_LSMA), + LDT(RSC_SYS_REG_LSMD), + LDT(RSC_SYS_REG_EnDA), + LDT(RSC_SYS_REG_UCI), + LDT(RSC_SYS_REG_EE), + LDT(RSC_SYS_REG_E0E), + LDT(RSC_SYS_REG_SPAN), + LDT(RSC_SYS_REG_EIS), + LDT(RSC_SYS_REG_IESB), + LDT(RSC_SYS_REG_TSCXT), + LDT(RSC_SYS_REG_WXN), + LDT(RSC_SYS_REG_nTWE), + LDT(RSC_SYS_REG_nTWI), + LDT(RSC_SYS_REG_UCT), + LDT(RSC_SYS_REG_DZE), + LDT(RSC_SYS_REG_EnDB), + LDT(RSC_SYS_REG_I), + LDT(RSC_SYS_REG_EOS), + LDT(RSC_SYS_REG_RCTX), + LDT(RSC_SYS_REG_UMA), + LDT(RSC_SYS_REG_SED), + LDT(RSC_SYS_REG_ITD), + LDT(RSC_SYS_REG_nAA), + LDT(RSC_SYS_REG_CP15B), + LDT(RSC_SYS_REG_SA0), + LDT(RSC_SYS_REG_SA1), + LDT(RSC_SYS_REG_C), + LDT(RSC_SYS_REG_A), + LDT(RSC_SYS_REG_M), + LDQ(RSC_SYS_REG_HDR11_SCTL2), + LDQ(RSC_SYS_REG_HDR12_SCTL2), + LDT(RSC_SYS_REG_SCTL2), + LDT(RSC_SYS_REG_CPTM), + LDT(RSC_SYS_REG_CPTM0), + LDT(RSC_SYS_REG_CPTM1), + LDT(RSC_SYS_REG_CPTA), + LDT(RSC_SYS_REG_CPTA0), + LDT(RSC_SYS_REG_CPTA1), + LDT(RSC_SYS_REG_PACM), + LDT(RSC_SYS_REG_PACM0), + LDT(RSC_SYS_REG_PACM1), + LDT(RSC_SYS_REG_128SR), + LDT(RSC_SYS_REG_EASE), + LDT(RSC_SYS_REG_ANERR), + LDT(RSC_SYS_REG_ADERR), + LDT(RSC_SYS_REG_NMEA), + LDQ(RSC_SYS_REG_HDR_FPSR), + LDT(RSC_SYS_REG_FPSR), + LDT(RSC_SYS_REG_FPSR_QC), + LDT(RSC_SYS_REG_FPSR_IDC), + LDT(RSC_SYS_REG_FPSR_IXC), + LDT(RSC_SYS_REG_FPSR_UFC), + LDT(RSC_SYS_REG_FPSR_OFC), + LDT(RSC_SYS_REG_FPSR_DZC), + LDT(RSC_SYS_REG_FPSR_IOC), + LDQ(RSC_SYS_REG_HDR11_EL), + LDQ(RSC_SYS_REG_HDR12_EL), + LDT(RSC_SYS_REG_EL), + LDT(RSC_SYS_REG_EL_EXEC), + LDT(RSC_SYS_REG_EL_SEC), + LDT(RSC_ISA_TITLE), + LDQ(RSC_ISA_AES), + LDT(RSC_ISA_AES_COMM), + LDQ(RSC_ISA_PMULL), + LDQ(RSC_ISA_LSE), + LDT(RSC_ISA_LSE_COMM), + LDQ(RSC_ISA_LSE128), + LDQ(RSC_ISA_CRC32), + LDT(RSC_ISA_CRC32_COMM), + LDQ(RSC_ISA_DP), + LDT(RSC_ISA_DP_COMM), + LDQ(RSC_ISA_EPAC), + LDT(RSC_ISA_EPAC_COMM), + LDQ(RSC_ISA_FCMA), + LDT(RSC_ISA_FCMA_COMM), + LDQ(RSC_ISA_FHM), + LDT(RSC_ISA_FHM_COMM), + LDQ(RSC_ISA_FP), + LDT(RSC_ISA_FP_COMM), + LDQ(RSC_ISA_FPAC), + LDT(RSC_ISA_FPAC_COMM), + LDQ(RSC_ISA_FPACCOMBINE), + LDT(RSC_ISA_FPACCOMBINE_COMM), + LDQ(RSC_ISA_JSCVT), + LDT(RSC_ISA_JSCVT_COMM), + LDQ(RSC_ISA_LRCPC), + LDQ(RSC_ISA_LRCPC2), + LDQ(RSC_ISA_LRCPC3), + LDT(RSC_ISA_LRCPC_COMM), + LDQ(RSC_ISA_LUT), + LDT(RSC_ISA_LUT_COMM), + LDQ(RSC_ISA_MOPS), + LDT(RSC_ISA_MOPS_COMM), + LDQ(RSC_ISA_PACGA), + LDT(RSC_ISA_PACIMP_COMM), + LDQ(RSC_ISA_PACQARMA3), + LDT(RSC_ISA_PACQARMA3_COMM), + LDQ(RSC_ISA_PACQARMA5), + LDT(RSC_ISA_PACQARMA5_COMM), + LDQ(RSC_ISA_PAUTH), + LDT(RSC_ISA_PAUTH_COMM), + LDQ(RSC_ISA_PAUTH2), + LDT(RSC_ISA_PAUTH2_COMM), + LDQ(RSC_ISA_PAUTH_LR), + LDT(RSC_ISA_PAUTH_LR_COMM), + LDQ(RSC_ISA_PRFMSLC), + LDT(RSC_ISA_PRFMSLC_COMM), + LDQ(RSC_ISA_FRINTTS), + LDT(RSC_ISA_FRINTTS_COMM), + LDQ(RSC_ISA_SPECRES), + LDT(RSC_ISA_SPECRES_COMM), + LDQ(RSC_ISA_SPECRES2), + LDQ(RSC_ISA_ATS1A), + LDT(RSC_ISA_ATS1A_COMM), + LDQ(RSC_ISA_BF16), + LDT(RSC_ISA_BF16_COMM), + LDQ(RSC_ISA_EBF16), + LDT(RSC_ISA_EBF16_COMM), + LDQ(RSC_ISA_CONSTPACFLD), + LDT(RSC_ISA_CONSTPACFLD_COMM), + LDQ(RSC_ISA_CSSC), + LDT(RSC_ISA_CSSC_COMM), + LDQ(RSC_ISA_HBC), + LDT(RSC_ISA_HBC_COMM), + LDQ(RSC_ISA_I8MM), + LDT(RSC_ISA_I8MM_COMM), + LDQ(RSC_ISA_RPRES), + LDT(RSC_ISA_RPRES_COMM), + LDQ(RSC_ISA_SB), + LDT(RSC_ISA_SB_COMM), + LDQ(RSC_ISA_SYSREG128), + LDT(RSC_ISA_SYSREG128_COMM), + LDQ(RSC_ISA_SYSINSTR128), + LDT(RSC_ISA_SYSINSTR128_COMM), + LDQ(RSC_ISA_WFxT), + LDT(RSC_ISA_WFxT_COMM), + LDQ(RSC_ISA_XS), + LDT(RSC_ISA_XS_COMM), + LDQ(RSC_ISA_LS64), + LDT(RSC_ISA_LS64_COMM), + LDQ(RSC_ISA_LS64_V), + LDQ(RSC_ISA_LS64_ACCDATA), + LDQ(RSC_ISA_DGH), + LDT(RSC_ISA_DGH_COMM), + LDQ(RSC_ISA_DPB), + LDT(RSC_ISA_DPB_COMM), + LDQ(RSC_ISA_DPB2), + LDQ(RSC_ISA_RAND), + LDT(RSC_ISA_RAND_COMM), + LDQ(RSC_ISA_RDMA), + LDT(RSC_ISA_RDMA_COMM), + LDQ(RSC_ISA_RNG_TRAP), + LDT(RSC_ISA_RNG_TRAP_COMM), + LDQ(RSC_ISA_RPRFM), + LDT(RSC_ISA_RPRFM_COMM), + LDQ(RSC_ISA_SHA1), + LDQ(RSC_ISA_SHA256), + LDQ(RSC_ISA_SHA512), + LDQ(RSC_ISA_SHA3), + LDT(RSC_ISA_SHA_COMM), + LDQ(RSC_ISA_SM3), + LDQ(RSC_ISA_SM4), + LDT(RSC_ISA_SM_COMM), + LDQ(RSC_ISA_SIMD), + LDT(RSC_ISA_SIMD_COMM), + LDQ(RSC_ISA_SME), + LDT(RSC_ISA_SME_COMM), + LDQ(RSC_ISA_SVE), + LDT(RSC_ISA_SVE_COMM), + LDQ(RSC_ISA_SVE_F64MM), + LDQ(RSC_ISA_SVE_F32MM), + LDQ(RSC_ISA_SVE_I8MM), + LDQ(RSC_ISA_SVE_SM4), + LDQ(RSC_ISA_SVE_SHA3), + LDQ(RSC_ISA_SVE_BF16), + LDQ(RSC_ISA_SVE_EBF16), + LDQ(RSC_ISA_SVE_BitPerm), + LDQ(RSC_ISA_SVE_AES), + LDQ(RSC_ISA_SVE_PMULL128), + LDQ(RSC_ISA_SVE2), + LDQ(RSC_ISA_SME2), + LDQ(RSC_ISA_SME2p1), + LDQ(RSC_ISA_SME_FA64), + LDQ(RSC_ISA_SME_LUTv2), + LDQ(RSC_ISA_SME_I16I64), + LDQ(RSC_ISA_SME_F64F64), + LDQ(RSC_ISA_SME_I16I32), + LDQ(RSC_ISA_SME_B16B16), + LDQ(RSC_ISA_SME_F16F16), + LDQ(RSC_ISA_SME_F8F16), + LDQ(RSC_ISA_SME_F8F32), + LDQ(RSC_ISA_SME_I8I32), + LDQ(RSC_ISA_SME_F16F32), + LDQ(RSC_ISA_SME_B16F32), + LDQ(RSC_ISA_SME_BI32I32), + LDQ(RSC_ISA_SME_F32F32), + LDQ(RSC_ISA_SME_SF8FMA), + LDQ(RSC_ISA_SME_SF8DP4), + LDQ(RSC_ISA_SME_SF8DP2), + LDQ(RSC_ISA_FlagM), + LDT(RSC_ISA_FlagM_COMM), + LDQ(RSC_ISA_FlagM2), + LDT(RSC_FEATURES_TITLE), + LDT(RSC_ON), + LDT(RSC_OFF), + LDT(RSC_FMW), + LDT(RSC_NOT_AVAILABLE), + LDT(RSC_AUTOMATIC), + LDT(RSC_UNABLE), + LDT(RSC_MISSING), + LDT(RSC_PRESENT), + LDT(RSC_VARIANT), + LDT(RSC_INVARIANT), + LDT(RSC_FEATURES_ACPI), + LDT(RSC_FEATURES_AMU), + LDT(RSC_FEATURES_BIG_END), + LDT(RSC_FEATURES_BTI), + LDT(RSC_FEATURES_EBEP), + LDT(RSC_FEATURES_ECBHB), + LDT(RSC_FEATURES_ECV), + LDT(RSC_FEATURES_DF2), + LDT(RSC_FEATURES_DIT), + LDT(RSC_FEATURES_EXS), + LDT(RSC_FEATURES_FGT), + LDT(RSC_FEATURES_PFAR), + LDT(RSC_FEATURES_GCS), + LDT(RSC_FEATURES_GIC), + LDT(RSC_FEATURES_MPAM), + LDT(RSC_FEATURES_MTE), + LDT(RSC_FEATURES_NMI), + LDT(RSC_FEATURES_PA), + LDT(RSC_FEATURES_PAN), + LDT(RSC_FEATURES_RAS), + LDT(RSC_FEATURES_RME), + LDT(RSC_FEATURES_SEL2), + LDT(RSC_FEATURES_THE), + LDT(RSC_FEATURES_TLB), + LDT(RSC_FEATURES_TME), + LDT(RSC_FEATURES_TSC), + LDT(RSC_FEATURES_UAO), + LDT(RSC_FEATURES_VA), + LDT(RSC_FEATURES_VHE), + LDT(RSC_FEAT_SECTION_MECH), + LDT(RSC_FEAT_SECTION_SEC), + LDT(RSC_TECHNOLOGIES_TITLE), + LDT(RSC_TECHNOLOGIES_DCU), + LDT(RSC_TECHNOLOGIES_ICU), + LDT(RSC_TECHNOLOGIES_VM), + LDT(RSC_TECHNOLOGIES_VM_COMM), + LDT(RSC_TECHNOLOGIES_IOMMU), + LDT(RSC_TECHNOLOGIES_IOMMU_COMM), + LDT(RSC_TECHNOLOGIES_SMT), + LDT(RSC_TECHNOLOGIES_HYBRID), + LDT(RSC_TECHNOLOGIES_HYPERV), + LDQ(RSC_TECH_HYPERV_NONE), + LDQ(RSC_TECH_BARE_METAL), + LDQ(RSC_TECH_HYPERV_XEN), + LDQ(RSC_TECH_HYPERV_KVM), + LDQ(RSC_TECH_HYPERV_VBOX), + LDQ(RSC_TECH_HYPERV_KBOX), + LDQ(RSC_TECH_HYPERV_VMWARE), + LDQ(RSC_TECH_HYPERV_HYPERV), + LDT(RSC_PERF_MON_TITLE), + LDT(RSC_PERF_CAPS_TITLE), + LDT(RSC_VERSION), + LDT(RSC_COUNTERS), + LDT(RSC_GENERAL_CTRS), + LDT(RSC_FIXED_CTRS), + LDT(RSC_PERF_MON_UNIT_BIT), + LDT(RSC_PERF_MON_CPPC), + LDT(RSC_PERF_MON_PCT), + LDT(RSC_PERF_MON_PSS), + LDT(RSC_PERF_MON_PPC), + LDT(RSC_PERF_MON_CPC), + LDT(RSC_PERF_MON_CST), + LDT(RSC_PERF_MON_HWP), + LDT(RSC_PERF_MON_CORE_CSTATE), + LDT(RSC_PERF_MON_CSTATE_BAR), + LDT(RSC_PERF_MON_MONITOR_MWAIT), + LDT(RSC_PERF_MON_MWAIT_IDX_CSTATE), + LDT(RSC_PERF_MON_MWAIT_SUB_CSTATE), + LDT(RSC_PERF_MON_CORE_CYCLE), + LDT(RSC_PERF_MON_INST_RET), + LDT(RSC_PERF_MON_PMC_COMM), + LDT(RSC_PERF_MON_CPPC_COMM), + LDQ(RSC_PERF_LABEL_VER), + LDQ(RSC_PERF_LABEL_HWCF), + LDQ(RSC_PERF_LABEL_CPPC), + LDQ(RSC_PERF_LABEL_PCT), + LDQ(RSC_PERF_LABEL_PSS), + LDQ(RSC_PERF_LABEL_PPC), + LDQ(RSC_PERF_LABEL_CPC), + LDQ(RSC_PERF_LABEL_CST), + LDQ(RSC_PERF_LABEL_HWP), + LDQ(RSC_PERF_LABEL_CST_BAR), + LDQ(RSC_PERF_LABEL_MWAIT_IDX), + LDQ(RSC_PERF_ENCODING_C0), + LDQ(RSC_PERF_ENCODING_C1), + LDQ(RSC_PERF_ENCODING_C2), + LDQ(RSC_PERF_ENCODING_C3), + LDQ(RSC_PERF_ENCODING_C4), + LDQ(RSC_PERF_ENCODING_C6), + LDQ(RSC_PERF_ENCODING_C6R), + LDQ(RSC_PERF_ENCODING_C7), + LDQ(RSC_PERF_ENCODING_C7S), + LDQ(RSC_PERF_ENCODING_C8), + LDQ(RSC_PERF_ENCODING_C9), + LDQ(RSC_PERF_ENCODING_C10), + LDQ(RSC_PERF_ENCODING_UNS), + LDT(RSC_POWER_THERMAL_TITLE), + LDT(RSC_POWER_THERMAL_CPPC), + LDT(RSC_POWER_THERMAL_TJMAX), + LDT(RSC_POWER_THERMAL_DTS), + LDT(RSC_POWER_THERMAL_PLN), + LDT(RSC_POWER_THERMAL_PTM), + LDT(RSC_POWER_THERMAL_UNITS), + LDT(RSC_POWER_THERMAL_POWER), + LDT(RSC_POWER_THERMAL_ENERGY), + LDT(RSC_POWER_THERMAL_WINDOW), + LDT(RSC_POWER_THERMAL_WATT), + LDT(RSC_POWER_THERMAL_JOULE), + LDT(RSC_POWER_THERMAL_SECOND), + LDT(RSC_POWER_THERMAL_TDP), + LDT(RSC_POWER_THERMAL_MIN), + LDT(RSC_POWER_THERMAL_MAX), + LDT(RSC_POWER_THERMAL_TPL), + LDT(RSC_POWER_THERMAL_TW), + LDT(RSC_POWER_THERMAL_EDC), + LDT(RSC_POWER_THERMAL_TDC), + LDT(RSC_POWER_THERMAL_POINT), + LDT(RSC_THERMAL_POINT_THRESHOLD), + LDT(RSC_THERMAL_POINT_LIMIT), + LDT(RSC_THERMAL_POINT_THRESHOLD_1), + LDT(RSC_THERMAL_POINT_THRESHOLD_2), + LDT(RSC_THERMAL_POINT_TRIP_LIMIT), + LDT(RSC_THERMAL_POINT_HTC_LIMIT), + LDT(RSC_THERMAL_POINT_HTC_HYST), + LDT(RSC_THERMAL_OFFSET_TITLE), + LDQ(RSC_POWER_LABEL_CPPC), + LDQ(RSC_POWER_LABEL_TJ), + LDQ(RSC_POWER_LABEL_DTS), + LDQ(RSC_POWER_LABEL_PLN), + LDQ(RSC_POWER_LABEL_PTM), + LDQ(RSC_POWER_LABEL_TDP), + LDQ(RSC_POWER_LABEL_MIN), + LDQ(RSC_POWER_LABEL_MAX), + LDQ(RSC_POWER_LABEL_PL1), + LDQ(RSC_POWER_LABEL_PL2), + LDQ(RSC_POWER_LABEL_TW1), + LDQ(RSC_POWER_LABEL_TW2), + LDQ(RSC_POWER_LABEL_EDC), + LDQ(RSC_POWER_LABEL_TDC), + LDQ(RSC_POWER_LABEL_PKG), + LDQ(RSC_POWER_LABEL_CORE), + LDQ(RSC_POWER_LABEL_UNCORE), + LDQ(RSC_POWER_LABEL_DRAM), + LDQ(RSC_POWER_LABEL_PLATFORM), + LDT(RSC_KERNEL_TITLE), + LDC(RSC_KERNEL_TOTAL_RAM, RSC_SYSINFO_KERNEL), + LDC(RSC_KERNEL_SHARED_RAM, RSC_SYSINFO_KERNEL), + LDC(RSC_KERNEL_FREE_RAM, RSC_SYSINFO_KERNEL), + LDC(RSC_KERNEL_BUFFER_RAM, RSC_SYSINFO_KERNEL), + LDC(RSC_KERNEL_TOTAL_HIGH, RSC_SYSINFO_KERNEL), + LDC(RSC_KERNEL_FREE_HIGH, RSC_SYSINFO_KERNEL), + LDC(RSC_KERNEL_GOVERNOR, RSC_SYSINFO_KERNEL), + LDC(RSC_KERNEL_FREQ_DRIVER, RSC_SYSINFO_KERNEL), + LDC(RSC_KERNEL_IDLE_DRIVER, RSC_SYSINFO_KERNEL), + LDC(RSC_KERNEL_CLOCK_SOURCE, RSC_SYSINFO_KERNEL), + LDC(RSC_KERNEL_RELEASE, RSC_SYSINFO_KERNEL), + LDC(RSC_KERNEL_VERSION, RSC_SYSINFO_KERNEL), + LDC(RSC_KERNEL_MACHINE, RSC_SYSINFO_KERNEL), + LDC(RSC_KERNEL_MEMORY, RSC_SYSINFO_KERNEL), + LDC(RSC_KERNEL_STATE, RSC_SYSINFO_KERNEL), + LDC(RSC_KERNEL_POWER, RSC_SYSINFO_KERNEL), + LDC(RSC_KERNEL_LATENCY, RSC_SYSINFO_KERNEL), + LDC(RSC_KERNEL_RESIDENCY, RSC_SYSINFO_KERNEL), + LDC(RSC_KERNEL_LIMIT, RSC_SYSINFO_KERNEL), + LDT(RSC_TOPOLOGY_TITLE), + LDQ(RSC_TOPOLOGY_FMT0), + LDQ(RSC_TOPOLOGY_FMT1), + LDQ(RSC_TOPOLOGY_OFF_0), + LDQ(RSC_TOPOLOGY_OFF_1), + LDQ(RSC_TOPOLOGY_OFF_2), + LDQ(RSC_TOPOLOGY_OFF_3), + LDQ(RSC_TOPOLOGY_HDR_PKG), + LDQ(RSC_TOPOLOGY_HDR_SMT), + LDQ(RSC_TOPOLOGY_HDR_CACHE), + LDQ(RSC_TOPOLOGY_HDR_WRBAK), + LDQ(RSC_TOPOLOGY_HDR_INCL), + LDQ(RSC_TOPOLOGY_HDR_EMPTY), + LDQ(RSC_TOPOLOGY_SUB_ITEM1), + LDQ(RSC_TOPOLOGY_SUB_ITEM3), + LDQ(RSC_TOPOLOGY_SUB_ITEM4), + LDQ(RSC_TOPOLOGY_SUB_ITEM5), + LDQ(RSC_TOPOLOGY_SUB_ITEM6), + LDQ(RSC_TOPOLOGY_ALT_ITEM1), + LDQ(RSC_TOPOLOGY_ALT_ITEM2), + LDQ(RSC_TOPOLOGY_ALT_ITEM3), + LDQ(RSC_TOPOLOGY_ALT_ITEM4), + LDQ(RSC_TOPOLOGY_BSP_COMM), + LDT(RSC_MEM_CTRL_TITLE), + LDQ(RSC_MEM_CTRL_UNIT_MHZ), + LDQ(RSC_MEM_CTRL_UNIT_MTS), + LDQ(RSC_MEM_CTRL_UNIT_MBS), + LDQ(RSC_MEM_CTRL_MTY_CELL), + LDQ(RSC_MEM_CTRL_CHANNEL), + LDT(RSC_MEM_CTRL_SUBSECT1_0), + LDT(RSC_MEM_CTRL_SUBSECT1_1), + LDT(RSC_MEM_CTRL_SUBSECT1_2), + LDT(RSC_MEM_CTRL_SINGLE_CHA_0), + LDT(RSC_MEM_CTRL_SINGLE_CHA_1), + LDT(RSC_MEM_CTRL_SINGLE_CHA_2), + LDT(RSC_MEM_CTRL_DUAL_CHA_0), + LDT(RSC_MEM_CTRL_DUAL_CHA_1), + LDT(RSC_MEM_CTRL_DUAL_CHA_2), + LDT(RSC_MEM_CTRL_TRIPLE_CHA_0), + LDT(RSC_MEM_CTRL_TRIPLE_CHA_1), + LDT(RSC_MEM_CTRL_TRIPLE_CHA_2), + LDT(RSC_MEM_CTRL_QUAD_CHA_0), + LDT(RSC_MEM_CTRL_QUAD_CHA_1), + LDT(RSC_MEM_CTRL_QUAD_CHA_2), + LDT(RSC_MEM_CTRL_SIX_CHA_0), + LDT(RSC_MEM_CTRL_SIX_CHA_1), + LDT(RSC_MEM_CTRL_SIX_CHA_2), + LDT(RSC_MEM_CTRL_EIGHT_CHA_0), + LDT(RSC_MEM_CTRL_EIGHT_CHA_1), + LDT(RSC_MEM_CTRL_EIGHT_CHA_2), + LDT(RSC_MEM_CTRL_DISABLED_0), + LDT(RSC_MEM_CTRL_DISABLED_1), + LDT(RSC_MEM_CTRL_DISABLED_2), + LDT(RSC_MEM_CTRL_BUS_RATE_0), + LDT(RSC_MEM_CTRL_BUS_RATE_1), + LDT(RSC_MEM_CTRL_BUS_SPEED_0), + LDT(RSC_MEM_CTRL_BUS_SPEED_1), + LDT(RSC_MEM_CTRL_RAM_STD_0), + LDT(RSC_MEM_CTRL_RAM_STD_1), + LDT(RSC_MEM_CTRL_RAM_STD_2), + LDT(RSC_MEM_CTRL_RAM_STD_3), + LDT(RSC_MEM_CTRL_DRAM_DDR2_0), + LDT(RSC_MEM_CTRL_DRAM_DDR3_0), + LDT(RSC_MEM_CTRL_DRAM_DDR4_0), + LDT(RSC_MEM_CTRL_DRAM_DDR5_0), + LDT(RSC_MEM_CTRL_DRAM_SPEED_0), + LDT(RSC_MEM_CTRL_DRAM_SPEED_1), + LDT(RSC_MEM_CTRL_SUBSECT2_0), + LDT(RSC_MEM_CTRL_SUBSECT2_1), + LDT(RSC_MEM_CTRL_SUBSECT2_2), + LDT(RSC_MEM_CTRL_SUBSECT2_3), + LDT(RSC_MEM_CTRL_SUBSECT2_4), + LDT(RSC_MEM_CTRL_SUBSECT2_5), + LDT(RSC_MEM_CTRL_DIMM_SLOT), + LDT(RSC_MEM_CTRL_DIMM_BANK), + LDT(RSC_MEM_CTRL_DIMM_RANK), + LDT(RSC_MEM_CTRL_DIMM_ROW), + LDT(RSC_MEM_CTRL_DIMM_COLUMN0), + LDT(RSC_MEM_CTRL_DIMM_COLUMN1), + LDT(RSC_MEM_CTRL_DIMM_SIZE_0), + LDT(RSC_MEM_CTRL_DIMM_SIZE_1), + LDT(RSC_MEM_CTRL_DIMM_SIZE_2), + LDT(RSC_MEM_CTRL_DIMM_SIZE_3), + LDQ(RSC_DDR3_CL), + LDQ(RSC_DDR3_RCD), + LDQ(RSC_DDR3_RP), + LDQ(RSC_DDR3_RAS), + LDQ(RSC_DDR3_RRD), + LDQ(RSC_DDR3_RFC), + LDQ(RSC_DDR3_WR), + LDQ(RSC_DDR3_RTP), + LDQ(RSC_DDR3_WTP), + LDQ(RSC_DDR3_FAW), + LDQ(RSC_DDR3_B2B), + LDQ(RSC_DDR3_CWL), + LDQ(RSC_DDR3_CMD), + LDQ(RSC_DDR3_REFI), + LDQ(RSC_DDR3_DDWRTRD), + LDQ(RSC_DDR3_DRWRTRD), + LDQ(RSC_DDR3_SRWRTRD), + LDQ(RSC_DDR3_DDRDTWR), + LDQ(RSC_DDR3_DRRDTWR), + LDQ(RSC_DDR3_SRRDTWR), + LDQ(RSC_DDR3_DDRDTRD), + LDQ(RSC_DDR3_DRRDTRD), + LDQ(RSC_DDR3_SRRDTRD), + LDQ(RSC_DDR3_DDWRTWR), + LDQ(RSC_DDR3_DRWRTWR), + LDQ(RSC_DDR3_SRWRTWR), + LDQ(RSC_DDR3_XS), + LDQ(RSC_DDR3_XP), + LDQ(RSC_DDR3_CKE), + LDQ(RSC_DDR3_ECC), + LDQ(RSC_DDR4_CL), + LDQ(RSC_DDR4_RCD_R), + LDQ(RSC_DDR4_RCD_W), + LDQ(RSC_DDR4_RP), + LDQ(RSC_DDR4_RAS), + LDQ(RSC_DDR4_RRD), + LDQ(RSC_DDR4_RFC), + LDQ(RSC_DDR4_WR), + LDQ(RSC_DDR4_RTP), + LDQ(RSC_DDR4_WTP), + LDQ(RSC_DDR4_FAW), + LDQ(RSC_DDR4_GEAR), + LDQ(RSC_DDR4_CWL), + LDQ(RSC_DDR4_CMD), + LDQ(RSC_DDR4_REFI), + LDQ(RSC_DDR4_RDRD_SCL), + LDQ(RSC_DDR4_RDRD_SC), + LDQ(RSC_DDR4_RDRD_SD), + LDQ(RSC_DDR4_RDRD_DD), + LDQ(RSC_DDR4_RDWR_SCL), + LDQ(RSC_DDR4_RDWR_SC), + LDQ(RSC_DDR4_RDWR_SD), + LDQ(RSC_DDR4_RDWR_DD), + LDQ(RSC_DDR4_WRRD_SCL), + LDQ(RSC_DDR4_WRRD_SC), + LDQ(RSC_DDR4_WRRD_SD), + LDQ(RSC_DDR4_WRRD_DD), + LDQ(RSC_DDR4_WRWR_SCL), + LDQ(RSC_DDR4_WRWR_SC), + LDQ(RSC_DDR4_WRWR_SD), + LDQ(RSC_DDR4_WRWR_DD), + LDQ(RSC_DDR4_RRD_S), + LDQ(RSC_DDR4_RRD_L), + LDQ(RSC_DDR4_CKE), + LDQ(RSC_DDR4_CPDED), + LDQ(RSC_DDR4_ECC), + LDQ(RSC_DDR4_ZEN_CL), + LDQ(RSC_DDR4_ZEN_RP), + LDQ(RSC_DDR4_ZEN_RAS), + LDQ(RSC_DDR4_ZEN_RC), + LDQ(RSC_DDR4_ZEN_FAW), + LDQ(RSC_DDR4_ZEN_WTR_S), + LDQ(RSC_DDR4_ZEN_WTR_L), + LDQ(RSC_DDR4_ZEN_WR), + LDQ(RSC_DDR4_ZEN_RDRD_SCL), + LDQ(RSC_DDR4_ZEN_WRWR_SCL), + LDQ(RSC_DDR4_ZEN_CWL), + LDQ(RSC_DDR4_ZEN_RTP), + LDQ(RSC_DDR4_ZEN_RDWR), + LDQ(RSC_DDR4_ZEN_WRRD), + LDQ(RSC_DDR4_ZEN_WRWR_SC), + LDQ(RSC_DDR4_ZEN_WRWR_SD), + LDQ(RSC_DDR4_ZEN_WRWR_DD), + LDQ(RSC_DDR4_ZEN_RDRD_SC), + LDQ(RSC_DDR4_ZEN_RDRD_SD), + LDQ(RSC_DDR4_ZEN_RDRD_DD), + LDQ(RSC_DDR4_ZEN_RTR_DLR), + LDQ(RSC_DDR4_ZEN_WTW_DLR), + LDQ(RSC_DDR4_ZEN_WTR_DLR), + LDQ(RSC_DDR4_ZEN_RRD_DLR), + LDQ(RSC_DDR4_ZEN_REFI), + LDQ(RSC_DDR4_ZEN_RFC1), + LDQ(RSC_DDR4_ZEN_RFC2), + LDQ(RSC_DDR4_ZEN_RFC4), + LDQ(RSC_DDR4_ZEN_RCPB), + LDQ(RSC_DDR4_ZEN_RPPB), + LDQ(RSC_DDR4_ZEN_BGS), + LDQ(RSC_DDR4_ZEN_BGS_ALT), + LDQ(RSC_DDR4_ZEN_BAN), + LDQ(RSC_DDR4_ZEN_RCPAGE), + LDQ(RSC_DDR4_ZEN_GDM), + LDQ(RSC_DDR4_ZEN_ECC), + LDQ(RSC_DDR4_ZEN_MRD), + LDQ(RSC_DDR4_ZEN_MOD), + LDQ(RSC_DDR4_ZEN_MRD_PDA), + LDQ(RSC_DDR4_ZEN_MOD_PDA), + LDQ(RSC_DDR4_ZEN_WRMPR), + LDQ(RSC_DDR4_ZEN_STAG), + LDQ(RSC_DDR4_ZEN_PDM), + LDQ(RSC_DDR4_ZEN_RDDATA), + LDQ(RSC_DDR4_ZEN_PHYWRD), + LDQ(RSC_DDR4_ZEN_PHYWRL), + LDQ(RSC_DDR4_ZEN_PHYRDL), + LDQ(RSC_DDR5_ZEN_RFC_SB), + LDQ(RSC_DDR5_ZEN_RCPB), + LDQ(RSC_DDR5_ZEN_RPPB), + LDQ(RSC_DDR5_ZEN_BGS), + LDT(RSC_DDR3_CL_COMM), + LDT(RSC_DDR3_RCD_COMM), + LDT(RSC_DDR3_RP_COMM), + LDT(RSC_DDR3_RAS_COMM), + LDT(RSC_DDR3_RRD_COMM), + LDT(RSC_DDR3_RFC_COMM), + LDT(RSC_DDR3_WR_COMM), + LDT(RSC_DDR3_RTP_COMM), + LDT(RSC_DDR3_WTP_COMM), + LDT(RSC_DDR3_FAW_COMM), + LDT(RSC_DDR3_B2B_COMM), + LDT(RSC_DDR3_CWL_COMM), + LDT(RSC_DDR3_CMD_COMM), + LDT(RSC_DDR3_REFI_COMM), + LDT(RSC_DDR3_DDWRTRD_COMM), + LDT(RSC_DDR3_DRWRTRD_COMM), + LDT(RSC_DDR3_SRWRTRD_COMM), + LDT(RSC_DDR3_DDRDTWR_COMM), + LDT(RSC_DDR3_DRRDTWR_COMM), + LDT(RSC_DDR3_SRRDTWR_COMM), + LDT(RSC_DDR3_DDRDTRD_COMM), + LDT(RSC_DDR3_DRRDTRD_COMM), + LDT(RSC_DDR3_SRRDTRD_COMM), + LDT(RSC_DDR3_DDWRTWR_COMM), + LDT(RSC_DDR3_DRWRTWR_COMM), + LDT(RSC_DDR3_SRWRTWR_COMM), + LDT(RSC_DDR3_XS_COMM), + LDT(RSC_DDR3_XP_COMM), + LDT(RSC_DDR3_CKE_COMM), + LDT(RSC_DDR3_ECC_COMM), + LDT(RSC_DDR4_RCD_R_COMM), + LDT(RSC_DDR4_RCD_W_COMM), + LDT(RSC_DDR4_RDRD_SCL_COMM), + LDT(RSC_DDR4_RDRD_SC_COMM), + LDT(RSC_DDR4_RDRD_SD_COMM), + LDT(RSC_DDR4_RDRD_DD_COMM), + LDT(RSC_DDR4_RDWR_SCL_COMM), + LDT(RSC_DDR4_RDWR_SC_COMM), + LDT(RSC_DDR4_RDWR_SD_COMM), + LDT(RSC_DDR4_RDWR_DD_COMM), + LDT(RSC_DDR4_WRRD_SCL_COMM), + LDT(RSC_DDR4_WRRD_SC_COMM), + LDT(RSC_DDR4_WRRD_SD_COMM), + LDT(RSC_DDR4_WRRD_DD_COMM), + LDT(RSC_DDR4_WRWR_SCL_COMM), + LDT(RSC_DDR4_WRWR_SC_COMM), + LDT(RSC_DDR4_WRWR_SD_COMM), + LDT(RSC_DDR4_WRWR_DD_COMM), + LDT(RSC_DDR4_RRD_S_COMM), + LDT(RSC_DDR4_RRD_L_COMM), + LDT(RSC_DDR4_CPDED_COMM), + LDT(RSC_DDR4_GEAR_COMM), + LDT(RSC_DDR4_ZEN_RC_COMM), + LDT(RSC_DDR4_ZEN_WTR_S_COMM), + LDT(RSC_DDR4_ZEN_WTR_L_COMM), + LDT(RSC_DDR4_ZEN_RDRD_SCL_COMM), + LDT(RSC_DDR4_ZEN_WRWR_SCL_COMM), + LDT(RSC_DDR4_ZEN_RTP_COMM), + LDT(RSC_DDR4_ZEN_RDWR_COMM), + LDT(RSC_DDR4_ZEN_WRRD_COMM), + LDT(RSC_DDR4_ZEN_WRWR_SC_COMM), + LDT(RSC_DDR4_ZEN_WRWR_SD_COMM), + LDT(RSC_DDR4_ZEN_WRWR_DD_COMM), + LDT(RSC_DDR4_ZEN_RDRD_SC_COMM), + LDT(RSC_DDR4_ZEN_RDRD_SD_COMM), + LDT(RSC_DDR4_ZEN_RDRD_DD_COMM), + LDT(RSC_DDR4_ZEN_RTR_DLR_COMM), + LDT(RSC_DDR4_ZEN_WTW_DLR_COMM), + LDT(RSC_DDR4_ZEN_WTR_DLR_COMM), + LDT(RSC_DDR4_ZEN_RRD_DLR_COMM), + LDT(RSC_DDR4_ZEN_RFC1_COMM), + LDT(RSC_DDR4_ZEN_RFC2_COMM), + LDT(RSC_DDR4_ZEN_RFC4_COMM), + LDT(RSC_DDR4_ZEN_RCPB_COMM), + LDT(RSC_DDR4_ZEN_RPPB_COMM), + LDT(RSC_DDR4_ZEN_BGS_COMM), + LDT(RSC_DDR4_ZEN_BGS_ALT_COMM), + LDT(RSC_DDR4_ZEN_BAN_COMM), + LDT(RSC_DDR4_ZEN_RCPAGE_COMM), + LDT(RSC_DDR4_ZEN_GDM_COMM), + LDT(RSC_DDR4_ZEN_MRD_COMM), + LDT(RSC_DDR4_ZEN_MOD_COMM), + LDT(RSC_DDR4_ZEN_MRD_PDA_COMM), + LDT(RSC_DDR4_ZEN_MOD_PDA_COMM), + LDT(RSC_DDR4_ZEN_WRMPR_COMM), + LDT(RSC_DDR4_ZEN_STAG_COMM), + LDT(RSC_DDR4_ZEN_PDM_COMM), + LDT(RSC_DDR4_ZEN_PHYWRD_COMM), + LDT(RSC_DDR4_ZEN_PHYWRL_COMM), + LDT(RSC_DDR4_ZEN_PHYRDL_COMM), + LDT(RSC_DDR4_ZEN_RDDATA_COMM), + LDT(RSC_DDR5_ZEN_RFC_SB_COMM), + LDT(RSC_TASKS_SORTBY_STATE), + LDT(RSC_TASKS_SORTBY_RTIME), + LDT(RSC_TASKS_SORTBY_UTIME), + LDT(RSC_TASKS_SORTBY_STIME), + LDT(RSC_TASKS_SORTBY_PID), + LDT(RSC_TASKS_SORTBY_COMM), + LDS(RSC_MENU_ITEM_MENU), + LDS(RSC_MENU_ITEM_VIEW), + LDS(RSC_MENU_ITEM_WINDOW), + LDT(RSC_MENU_ITEM_SPACER), + LDT(RSC_MENU_ITEM_DATE_TIME), + LDT(RSC_MENU_ITEM_FULL_TIME), + LDT(RSC_MENU_ITEM_TINY_TIME), + LDT(RSC_MENU_ITEM_SETTINGS), + LDT(RSC_MENU_ITEM_SMBIOS), + LDT(RSC_MENU_ITEM_KERNEL), + LDT(RSC_MENU_ITEM_HOTPLUG), + LDT(RSC_MENU_ITEM_TOOLS), + LDT(RSC_MENU_ITEM_THEME), + LDT(RSC_MENU_ITEM_ABOUT), + LDT(RSC_MENU_ITEM_HELP), + LDT(RSC_MENU_ITEM_KEYS), + LDT(RSC_MENU_ITEM_LANG), + LDT(RSC_MENU_ITEM_QUIT), + LDT(RSC_MENU_ITEM_DASHBOARD), + LDT(RSC_MENU_ITEM_FREQUENCY), + LDT(RSC_MENU_ITEM_INST_CYCLES), + LDT(RSC_MENU_ITEM_CORE_CYCLES), + LDT(RSC_MENU_ITEM_IDLE_STATES), + LDT(RSC_MENU_ITEM_PKG_CYCLES), + LDT(RSC_MENU_ITEM_TASKS_MON), + LDT(RSC_MENU_ITEM_SYS_INTER), + LDT(RSC_MENU_ITEM_SENSORS), + LDT(RSC_MENU_ITEM_VOLTAGE), + LDT(RSC_MENU_ITEM_POWER), + LDT(RSC_MENU_ITEM_SLICE_CTRS), + LDT(RSC_MENU_ITEM_CUSTOM), + LDT(RSC_MENU_ITEM_PROCESSOR), + LDT(RSC_MENU_ITEM_TOPOLOGY), + LDT(RSC_MENU_ITEM_FEATURES), + LDT(RSC_MENU_ITEM_ISA_EXT), + LDT(RSC_MENU_ITEM_TECH), + LDT(RSC_MENU_ITEM_PERF_MON), + LDT(RSC_MENU_ITEM_PERF_CAPS), + LDT(RSC_MENU_ITEM_POW_THERM), + LDT(RSC_MENU_ITEM_SYS_REGS), + LDT(RSC_MENU_ITEM_MEM_CTRL), + LDT(RSC_MENU_ITEM_EVENTS), + LDT(RSC_SETTINGS_TITLE), + LDT(RSC_SETTINGS_DAEMON), + LDT(RSC_SETTINGS_INTERVAL), + LDT(RSC_SETTINGS_SYS_TICK), + LDT(RSC_SETTINGS_POLL_WAIT), + LDT(RSC_SETTINGS_RING_WAIT), + LDT(RSC_SETTINGS_CHILD_WAIT), + LDT(RSC_SETTINGS_SLICE_WAIT), + LDT(RSC_SETTINGS_RECORDER), + LDT(RSC_SETTINGS_AUTO_CLOCK), + LDT(RSC_SETTINGS_EXPERIMENTAL), + LDT(RSC_SETTINGS_CPU_HOTPLUG), + LDT(RSC_SETTINGS_PCI_ENABLED), + LDT(RSC_SETTINGS_NMI_REGISTERED), + LDT(RSC_SETTINGS_CPUIDLE_REGISTERED), + LDT(RSC_SETTINGS_CPUFREQ_REGISTERED), + LDT(RSC_SETTINGS_GOVERNOR_REGISTERED), + LDT(RSC_SETTINGS_CS_REGISTERED), + LDT(RSC_SETTINGS_THERMAL_SCOPE), + LDT(RSC_SETTINGS_VOLTAGE_SCOPE), + LDT(RSC_SETTINGS_POWER_SCOPE), + LDT(RSC_SETTINGS_IDLE_ROUTE), + LDT(RSC_SETTINGS_ROUTE_TITLE), + LDQ(RSC_SETTINGS_ROUTE_DFLT), + LDQ(RSC_SETTINGS_ROUTE_IO), + LDQ(RSC_SETTINGS_ROUTE_HALT), + LDQ(RSC_SETTINGS_ROUTE_MWAIT), + LDT(RSC_HELP_TITLE), + LDT(RSC_HELP_KEY_ESCAPE), + LDT(RSC_HELP_KEY_SHIFT_TAB), + LDT(RSC_HELP_KEY_TAB), + LDT(RSC_HELP_KEY_UP), + LDT(RSC_HELP_KEY_LEFT_RIGHT), + LDT(RSC_HELP_KEY_DOWN), + LDT(RSC_HELP_KEY_END), + LDT(RSC_HELP_KEY_HOME), + LDT(RSC_HELP_KEY_ENTER), + LDT(RSC_HELP_KEY_PAGE_UP), + LDT(RSC_HELP_KEY_PAGE_DOWN), + LDT(RSC_HELP_KEY_MINUS), + LDT(RSC_HELP_KEY_PLUS), + LDQ(RSC_HELP_BLANK), + LDT(RSC_HELP_KEY_MENU), + LDT(RSC_HELP_MENU), + LDT(RSC_HELP_CLOSE_WINDOW), + LDT(RSC_HELP_PREV_WINDOW), + LDT(RSC_HELP_NEXT_WINDOW), + LDT(RSC_HELP_KEY_SHIFT_GR1), + LDT(RSC_HELP_KEY_SHIFT_GR2), + LDT(RSC_HELP_MOVE_WINDOW), + LDT(RSC_HELP_KEY_ALT_GR3), + LDT(RSC_HELP_SIZE_WINDOW), + LDT(RSC_HELP_MOVE_SELECT), + LDT(RSC_HELP_LAST_CELL), + LDT(RSC_HELP_FIRST_CELL), + LDT(RSC_HELP_TRIGGER_SELECT), + LDT(RSC_HELP_PREV_PAGE), + LDT(RSC_HELP_NEXT_PAGE), + LDT(RSC_HELP_SCROLL_DOWN), + LDT(RSC_HELP_SCROLL_UP), + LDT(RSC_ADV_HELP_TITLE), + LDT(RSC_ADV_HELP_SECT_FREQ), + LDT(RSC_ADV_HELP_ITEM_AVG), + LDT(RSC_ADV_HELP_SECT_TASK), + LDT(RSC_ADV_HELP_ITEM_ORDER), + LDT(RSC_ADV_HELP_ITEM_RST), + LDT(RSC_ADV_HELP_ITEM_SEL), + LDT(RSC_ADV_HELP_ITEM_REV), + LDT(RSC_ADV_HELP_ITEM_HIDE), + LDT(RSC_ADV_HELP_SECT_ANY), + LDT(RSC_ADV_HELP_ITEM_POWER), + LDT(RSC_ADV_HELP_ITEM_TOP), + LDT(RSC_ADV_HELP_ITEM_UPD), + LDT(RSC_ADV_HELP_ITEM_START), + LDT(RSC_ADV_HELP_ITEM_STOP), + LDT(RSC_ADV_HELP_ITEM_TOOLS), + LDT(RSC_ADV_HELP_ITEM_GO_UP), + LDT(RSC_ADV_HELP_ITEM_GO_DW), + LDT(RSC_ADV_HELP_ITEM_TERMINAL), + LDT(RSC_ADV_HELP_ITEM_PRT_SCR), + LDT(RSC_ADV_HELP_ITEM_REC_SCR), + LDT(RSC_ADV_HELP_ITEM_FAHR_CELS), + LDT(RSC_ADV_HELP_ITEM_SYSGATE), + LDT(RSC_ADV_HELP_ITEM_PROC_EVENT), + LDT(RSC_ADV_HELP_ITEM_SECRET), + LDT(RSC_TURBO_CLOCK_TITLE), + LDT(RSC_RATIO_CLOCK_TITLE), + LDT(RSC_UNCORE_CLOCK_TITLE), + LDT(RSC_SELECT_CPU_TITLE), + LDT(RSC_SELECT_FREQ_TITLE), + LDT(RSC_BOX_DISABLE_COND0), + LDT(RSC_BOX_DISABLE_COND1), + LDT(RSC_BOX_ENABLE_COND0), + LDT(RSC_BOX_ENABLE_COND1), + LDT(RSC_BOX_INTERVAL_TITLE), + LDQ(RSC_BOX_INTERVAL_STEP1), + LDQ(RSC_BOX_INTERVAL_STEP2), + LDQ(RSC_BOX_INTERVAL_STEP3), + LDQ(RSC_BOX_INTERVAL_STEP4), + LDQ(RSC_BOX_INTERVAL_STEP5), + LDQ(RSC_BOX_INTERVAL_STEP6), + LDQ(RSC_BOX_INTERVAL_STEP7), + LDQ(RSC_BOX_INTERVAL_STEP8), + LDQ(RSC_BOX_INTERVAL_STEP9), + LDQ(RSC_BOX_INTERVAL_STEP10), + LDT(RSC_BOX_AUTO_CLOCK_TITLE), + LDT(RSC_BOX_MODE_TITLE), + LDT(RSC_BOX_MODE_DESC), + LDQ(RSC_BOX_CPPC_TITLE), + LDQ(RSC_BOX_HWP_TITLE), + LDT(RSC_BOX_HWP_DESC), + LDT(RSC_BOX_FMW_DESC), + LDQ(RSC_BOX_BLANK_DESC), + LDT(RSC_BOX_NOMINAL_MODE_COND0), + LDT(RSC_BOX_NOMINAL_MODE_COND1), + LDT(RSC_BOX_EXPERIMENT_MODE_COND0), + LDT(RSC_BOX_EXPERIMENT_MODE_COND1), + LDT(RSC_BOX_INTERRUPT_TITLE), + LDT(RSC_BOX_CPU_IDLE_TITLE), + LDT(RSC_BOX_CPU_FREQ_TITLE), + LDT(RSC_BOX_GOVERNOR_TITLE), + LDT(RSC_BOX_CLOCK_SOURCE_TITLE), + LDT(RSC_BOX_OPS_REGISTER_COND0), + LDT(RSC_BOX_OPS_REGISTER_COND1), + LDT(RSC_BOX_OPS_UNREGISTER_COND0), + LDT(RSC_BOX_OPS_UNREGISTER_COND1), + LDT(RSC_BOX_EVENT_TITLE), + LDT(RSC_BOX_EVENT_SPACE), + LDT(RSC_BOX_EVENT_THERMAL_SENSOR), + LDT(RSC_BOX_EVENT_PROCHOT_STS), + LDT(RSC_BOX_EVENT_CRITICAL_TEMP), + LDT(RSC_BOX_EVENT_THOLD1_STS), + LDT(RSC_BOX_EVENT_THOLD2_STS), + LDT(RSC_BOX_EVENT_POWER_LIMIT), + LDT(RSC_BOX_EVENT_CURRENT_LIMIT), + LDT(RSC_BOX_EVENT_CROSS_DOM_LIMIT), + LDT(RSC_BOX_EVENT_RESIDENCY), + LDT(RSC_BOX_EVENT_AVG_THERMAL), + LDT(RSC_BOX_EVENT_VR_THERMAL), + LDT(RSC_BOX_EVENT_VR_TDC), + LDT(RSC_BOX_EVENT_POWER_PL1), + LDT(RSC_BOX_EVENT_POWER_PL2), + LDT(RSC_BOX_EVENT_ELECTRICAL), + LDT(RSC_BOX_EVENT_INEFFICIENCY), + LDT(RSC_BOX_EVENT_MAX_TURBO), + LDT(RSC_BOX_EVENT_TURBO_ATTEN), + LDT(RSC_BOX_EVENT_THERMAL_TVB), + LDT(RSC_BOX_EVENT_ALL_OF_THEM), + LDT(RSC_BOX_POWER_POLICY_TITLE), + LDT(RSC_BOX_POWER_POLICY_LOW), + LDT(RSC_BOX_POWER_POLICY_HIGH), + LDT(RSC_BOX_HWP_POLICY_MIN), + LDT(RSC_BOX_HWP_POLICY_020), + LDT(RSC_BOX_HWP_POLICY_040), + LDT(RSC_BOX_HWP_POLICY_060), + LDT(RSC_BOX_HWP_POLICY_MED), + LDT(RSC_BOX_HWP_POLICY_0A0), + LDT(RSC_BOX_HWP_POLICY_PWR), + LDT(RSC_BOX_HWP_POLICY_0E0), + LDT(RSC_BOX_HWP_POLICY_MAX), + LDT(RSC_BOX_CFG_TDP_TITLE), + LDT(RSC_BOX_CFG_TDP_DESC), + LDQ(RSC_BOX_CFG_TDP_BLANK), + LDT(RSC_BOX_CFG_TDP_LVL0), + LDT(RSC_BOX_CFG_TDP_LVL1), + LDT(RSC_BOX_CFG_TDP_LVL2), + LDT(RSC_BOX_TDP_PKG_TITLE), + LDT(RSC_BOX_TDP_CORES_TITLE), + LDT(RSC_BOX_TDP_UNCORE_TITLE), + LDT(RSC_BOX_TDP_RAM_TITLE), + LDT(RSC_BOX_TDP_PLATFORM_TITLE), + LDT(RSC_BOX_PL1_DESC), + LDT(RSC_BOX_PL2_DESC), + LDQ(RSC_BOX_PWR_OFFSET_00), + LDQ(RSC_BOX_PWR_OFFSET_01), + LDQ(RSC_BOX_PWR_OFFSET_02), + LDQ(RSC_BOX_PWR_OFFSET_03), + LDQ(RSC_BOX_PWR_OFFSET_04), + LDQ(RSC_BOX_PWR_OFFSET_05), + LDQ(RSC_BOX_PWR_OFFSET_06), + LDQ(RSC_BOX_PWR_OFFSET_07), + LDQ(RSC_BOX_PWR_OFFSET_08), + LDQ(RSC_BOX_PWR_OFFSET_09), + LDQ(RSC_BOX_PWR_OFFSET_10), + LDQ(RSC_BOX_PWR_OFFSET_11), + LDQ(RSC_BOX_PWR_OFFSET_12), + LDQ(RSC_BOX_PWR_OFFSET_13), + LDQ(RSC_BOX_CLAMPING_OFF_COND0), + LDQ(RSC_BOX_CLAMPING_OFF_COND1), + LDQ(RSC_BOX_CLAMPING_ON_COND0), + LDQ(RSC_BOX_CLAMPING_ON_COND1), + LDT(RSC_BOX_TDC_TITLE), + LDT(RSC_BOX_TDC_DESC), + LDQ(RSC_BOX_AMP_OFFSET_00), + LDQ(RSC_BOX_AMP_OFFSET_01), + LDQ(RSC_BOX_AMP_OFFSET_02), + LDQ(RSC_BOX_AMP_OFFSET_03), + LDQ(RSC_BOX_AMP_OFFSET_04), + LDQ(RSC_BOX_AMP_OFFSET_05), + LDQ(RSC_BOX_AMP_OFFSET_06), + LDQ(RSC_BOX_AMP_OFFSET_07), + LDQ(RSC_BOX_AMP_OFFSET_08), + LDQ(RSC_BOX_AMP_OFFSET_09), + LDQ(RSC_BOX_AMP_OFFSET_10), + LDQ(RSC_BOX_AMP_OFFSET_11), + LDQ(RSC_BOX_AMP_OFFSET_12), + LDQ(RSC_BOX_AMP_OFFSET_13), + LDT(RSC_BOX_TOOLS_TITLE), + LDT(RSC_BOX_TOOLS_STOP_BURN), + LDT(RSC_BOX_TOOLS_ATOMIC_BURN), + LDT(RSC_BOX_TOOLS_CRC32_BURN), + LDT(RSC_BOX_TOOLS_CONIC_BURN), + LDT(RSC_BOX_TOOLS_RANDOM_CPU), + LDT(RSC_BOX_TOOLS_ROUND_ROBIN_CPU), + LDT(RSC_BOX_TOOLS_USER_CPU), + LDT(RSC_BOX_TOOLS_MONTE_CARLO), + LDT(RSC_BOX_CONIC_TITLE), + LDT(RSC_BOX_CONIC_ITEM_1), + LDT(RSC_BOX_CONIC_ITEM_2), + LDT(RSC_BOX_CONIC_ITEM_3), + LDT(RSC_BOX_CONIC_ITEM_4), + LDT(RSC_BOX_CONIC_ITEM_5), + LDT(RSC_BOX_CONIC_ITEM_6), + LDT(RSC_BOX_LANG_TITLE), + LDT(RSC_BOX_LANG_ENGLISH), + LDT(RSC_BOX_LANG_FRENCH), + LDQ(RSC_BOX_LANG_BLANK), + LDT(RSC_BOX_THEME_TITLE), + LDQ(RSC_BOX_THEME_BLANK), + LDT(RSC_BOX_SCOPE_THERMAL_TITLE), + LDT(RSC_BOX_SCOPE_VOLTAGE_TITLE), + LDT(RSC_BOX_SCOPE_POWER_TITLE), + LDT(RSC_BOX_SCOPE_NONE), + LDT(RSC_BOX_SCOPE_THREAD), + LDT(RSC_BOX_SCOPE_CORE), + LDT(RSC_BOX_SCOPE_PACKAGE), + LDT(RSC_ERROR_CMD_SYNTAX), + LDT(RSC_ERROR_SHARED_MEM), + LDT(RSC_ERROR_SYS_CALL), + LDT(RSC_ERROR_UNIMPLEMENTED), + LDT(RSC_ERROR_EXPERIMENTAL), + LDT(RSC_ERROR_TURBO_PREREQ), + LDT(RSC_ERROR_UNCORE_PREREQ), + LDT(RSC_ERROR_PSTATE_NOT_FOUND), + LDT(RSC_ERROR_CLOCKSOURCE), + LDT(RSC_BOX_IDLE_LIMIT_TITLE), + LDQ(RSC_BOX_IDLE_LIMIT_RESET), + LDT(RSC_BOX_RECORDER_TITLE), + LDT(RSC_SMBIOS_TITLE), + LDT(RSC_MECH_CLRBHB), + LDT(RSC_MECH_SSBD), + LDT(RSC_MECH_SSBS), + LDQ(RSC_CF0), + LDQ(RSC_CF1), + LDQ(RSC_CF2), + LDQ(RSC_CF3), + LDQ(RSC_CF4), + LDQ(RSC_CF5), + LDT(RSC_COPY0), + LDT(RSC_COPY1), + LDT(RSC_COPY2), + LDT(RSC_CREATE_SELECT_AUTO_TURBO), + LDT(RSC_CREATE_SELECT_FREQ_TURBO), + LDT(RSC_CREATE_SELECT_FREQ_TGT), + LDT(RSC_CREATE_SELECT_FREQ_HWP_TGT), + LDT(RSC_CREATE_SELECT_FREQ_HWP_MAX), + LDT(RSC_CREATE_SELECT_FREQ_HWP_MIN), + LDT(RSC_CREATE_SELECT_FREQ_MAX), + LDT(RSC_CREATE_SELECT_FREQ_MIN), + LDT(RSC_CREATE_SELECT_FREQ_OFFLINE), + LDT(RSC_POPUP_DRIVER_TITLE), + LDT(RSC_EXIT_TITLE), + LDT(RSC_EXIT_HEADER), + LDT(RSC_EXIT_CONFIRM), + LDT(RSC_EXIT_FOOTER) +}; + +#undef LDV +#undef LDA +#undef LDB +#undef LDS +#undef LDT +#undef LDC +#undef LDQ +#undef DEF_LDA +#undef DEF_LDB diff --git a/aarch64/corefreq-cli-rsc.h b/aarch64/corefreq-cli-rsc.h new file mode 100644 index 00000000..718398d9 --- /dev/null +++ b/aarch64/corefreq-cli-rsc.h @@ -0,0 +1,1444 @@ +/* + * CoreFreq + * Copyright (C) 2015-2024 CYRIL COURTIAT + * Licenses: GPL2 + */ + +enum UI_THEME { + UI_FUSE_RESET_LAYER, + UI_FUSE_PAINT_LAYER, + UI_MAKE_TITLE_UNFOCUS, + UI_MAKE_TITLE_FOCUS, + UI_MAKE_BORDER_UNFOCUS, + UI_MAKE_BORDER_FOCUS, + UI_MAKE_SELECT_UNFOCUS, + UI_MAKE_SELECT_FOCUS, + UI_MAKE_PRINT_UNFOCUS, + UI_MAKE_PRINT_FOCUS, + UI_MAKE_PRINT_DROP, + UI_LAYOUT_LCD_RESET, + UI_LAYOUT_LCD_CLOCK_LOW, + UI_LAYOUT_LCD_CLOCK_MEDIUM, + UI_LAYOUT_LCD_CLOCK_HIGH, + UI_LAYOUT_LCD_COUNTER_LOW, + UI_LAYOUT_LCD_COUNTER_MEDIUM, + UI_LAYOUT_LCD_COUNTER_HIGH, + UI_LAYOUT_LCD_LOAD_LOW, + UI_LAYOUT_LCD_LOAD_MEDIUM, + UI_LAYOUT_LCD_LOAD_HIGH, + UI_LAYOUT_LCD_IDLE_LOW, + UI_LAYOUT_LCD_IDLE_MEDIUM, + UI_LAYOUT_LCD_IDLE_HIGH, + UI_LAYOUT_LCD_SYSTEM_LOW, + UI_LAYOUT_LCD_SYSTEM_MEDIUM, + UI_LAYOUT_LCD_SYSTEM_HIGH, + UI_LAYOUT_UBENCH, + UI_LAYOUT_HEADER_PROC_BRAND, + UI_LAYOUT_HEADER_PROC_BRAND_FILL, + UI_LAYOUT_HEADER_ARCHITECTURE, + UI_LAYOUT_HEADER_ARCH_FILL, + UI_LAYOUT_HEADER_BCLK_FILL, + UI_LAYOUT_RULER_INSTRUCTIONS, + UI_LAYOUT_RULER_CYCLES, + UI_LAYOUT_RULER_CSTATES, + UI_LAYOUT_RULER_INTERRUPTS, + UI_LAYOUT_RULER_PACKAGE, + UI_LAYOUT_RULER_TASKS_FILL, + UI_LAYOUT_RULER_TASKS_TRACKING, + UI_LAYOUT_RULER_ENERGY, + UI_LAYOUT_RULER_SLICE, + UI_LAYOUT_RULER_CUSTOM, + UI_LAYOUT_FOOTER_ENABLE_0, + UI_LAYOUT_FOOTER_ENABLE_1, + UI_LAYOUT_FOOTER_ENABLE_2, + UI_LAYOUT_FOOTER_TSC_NONE, + UI_LAYOUT_FOOTER_TSC_VAR, + UI_LAYOUT_FOOTER_TSC_INV, + UI_LAYOUT_FOOTER_TM_0, + UI_LAYOUT_FOOTER_TM_1, + UI_LAYOUT_FOOTER_TM_2, + UI_LAYOUT_FOOTER_TM_3, + UI_LAYOUT_FOOTER_FILL, + UI_LAYOUT_FOOTER_GATE, + UI_LAYOUT_FOOTER_SPACE, + UI_LAYOUT_FOOTER_LEFT_BRACE, + UI_LAYOUT_FOOTER_RIGHT_BRACE, + UI_LAYOUT_FOOTER_KERNEL_VERSION, + UI_LAYOUT_FOOTER_UNMAP_GATE, + UI_LAYOUT_FOOTER_DMI_STRING, + UI_LAYOUT_BCLK_TO_VIEW, + UI_LAYOUT_ROW_CPU_OFFLINE, + UI_LAYOUT_RULER_LOAD_TAB_DIM, + UI_LAYOUT_RULER_LOAD_TAB_BRIGHT, + UI_ILLUMINATES_CPU_OFF, + UI_ILLUMINATES_CPU_ON, + UI_ILLUMINATES_CPU_SP, + UI_ILLUMINATES_CPU_SP_HYBRID, + UI_DRAW_FREQUENCY_LOAD_CLEAR, + UI_DRAW_FREQUENCY_LOAD_LOW, + UI_DRAW_FREQUENCY_LOAD_MEDIUM, + UI_DRAW_FREQUENCY_LOAD_HIGH, + UI_DRAW_ALTMONITOR_TASKS_CLEAR, + UI_DRAW_ALTMONITOR_TASKS_SPACE, + UI_DRAW_MONITOR_FREQUENCY_NOMINAL, + UI_DRAW_MONITOR_FREQUENCY_LOW, + UI_DRAW_MONITOR_FREQUENCY_HIGH, + UI_DRAW_MONITOR_FREQUENCY_HOT, + UI_LAYOUT_CARD_CORE_OFFLINE, + UI_LAYOUT_CARD_RAM_2DIGITS, + UI_LAYOUT_CARD_RAM_3DIGITS, + UI_DRAW_CARD_CORE_NOMINAL, + UI_DRAW_CARD_CORE_LOW, + UI_DRAW_CARD_CORE_MEDIUM, + UI_DRAW_CARD_CORE_HIGH, + UI_DRAW_CARD_TASK_FILL, + UI_WIN_MENU_UNSELECT, + UI_WIN_MENU_SELECT, + UI_WIN_MENU_TITLE_UNFOCUS, + UI_WIN_MENU_TITLE_FOCUS, + UI_WIN_MENU_ERASE_CELL, + UI_WIN_SORT_BY_FIELD_TITLE, + UI_WIN_TRACKING_PARENT_PROCESS, + UI_WIN_TRACKING_CHILD_PROCESS, + UI_WIN_TRACKING_THIS_PARENT, + UI_WIN_TRACKING_THIS_CHILD, + UI_WIN_TRACKING_COUNTERS, + UI_WIN_TRACKING_TITLE, + UI_WIN_HOT_PLUG_CPU_TITLE, + UI_WIN_SELECT_IDLE_RESET, + UI_WIN_SELECT_IDLE_POLL, + UI_WIN_SELECT_IDLE_CURRENT, + UI_WIN_POPUP_MSG_ITEM, + UI_WIN_POPUP_MSG_SELECT_UNFOCUS, + UI_WIN_POPUP_MSG_SELECT_FOCUS, + UI_WIN_POPUP_MSG_BORDER_UNFOCUS, + UI_WIN_POPUP_MSG_BORDER_FOCUS, + UI_WIN_POPUP_MSG_TITLE_UNFOCUS, + UI_WIN_POPUP_MSG_TITLE_FOCUS, + UI_WIN_EXIT_ISSUE_RECORDER, + UI_WIN_EXIT_ISSUE_STRESS, + UI_WIN_EXIT_ISSUE_OS_CPU_IDLE, + UI_WIN_EXIT_HEADER, + UI_WIN_EXIT_BLANK, + UI_WIN_EXIT_CONFIRM, + UI_WIN_EXIT_FOOTER, + UI_BOX_DISABLE_STATE, + UI_BOX_ENABLE_STATE, + UI_BOX_BLANK, + UI_BOX_DESC, + UI_BOX_INTERVAL, + UI_BOX_EXPERIMENTAL_NOMINAL, + UI_BOX_EXPERIMENTAL_WARNING, + UI_DROP_IDLE_ROUTE, + UI_BOX_TOOLS_STOP, + UI_WHEEL_CURRENT, + UI_WHEEL_SELECT, + UI_WHEEL_LIST +}; + +enum { + RSC_UI, + RSC_VOID, + RSC_THEME_DFLT, + RSC_THEME_USR1, + RSC_THEME_USR2, + RSC_LAYOUT_LCD_RESET, +#ifndef NO_HEADER + RSC_LAYOUT_HEADER_PROC, + RSC_LAYOUT_HEADER_CPU, + RSC_LAYOUT_HEADER_ARCH, + RSC_LAYOUT_HEADER_CACHE_L1, + RSC_LAYOUT_HEADER_BCLK, + RSC_LAYOUT_HEADER_CACHES, +#endif +#ifndef NO_UPPER + RSC_LAYOUT_RULER_LOAD, + RSC_LAYOUT_RULER_REL_LOAD, + RSC_LAYOUT_RULER_ABS_LOAD, +#endif +#ifndef NO_LOWER + RSC_LAYOUT_MONITOR_FREQUENCY, + RSC_LAYOUT_MONITOR_INST, + RSC_LAYOUT_MONITOR_COMMON, + RSC_LAYOUT_MONITOR_TASKS, + RSC_LAYOUT_MONITOR_SLICE, + RSC_LAYOUT_CUSTOM_FIELD, + RSC_LAYOUT_RULER_FREQUENCY, + RSC_LAYOUT_RULER_FREQUENCY_AVG, + RSC_LAYOUT_RULER_FREQUENCY_PKG, + RSC_LAYOUT_RULER_INST, + RSC_LAYOUT_RULER_CYCLES, + RSC_LAYOUT_RULER_CSTATES, + RSC_LAYOUT_RULER_INTERRUPTS, + RSC_LAYOUT_RULER_PACKAGE, + RSC_LAYOUT_PACKAGE_PC, + RSC_LAYOUT_PACKAGE_PC02, + RSC_LAYOUT_PACKAGE_PC03, + RSC_LAYOUT_PACKAGE_PC04, + RSC_LAYOUT_PACKAGE_PC06, + RSC_LAYOUT_PACKAGE_PC07, + RSC_LAYOUT_PACKAGE_PC08, + RSC_LAYOUT_PACKAGE_PC09, + RSC_LAYOUT_PACKAGE_PC10, + RSC_LAYOUT_PACKAGE_MC06, + RSC_LAYOUT_PACKAGE_UNCORE, + RSC_LAYOUT_RULER_TASKS, + RSC_LAYOUT_TASKS_TRACKING, + RSC_LAYOUT_TASKS_STATE_SORTED, + RSC_LAYOUT_TASKS_RUNTIME_SORTED, + RSC_LAYOUT_TASKS_USRTIME_SORTED, + RSC_LAYOUT_TASKS_SYSTIME_SORTED, + RSC_LAYOUT_TASKS_PROCESS_SORTED, + RSC_LAYOUT_TASKS_COMMAND_SORTED, + RSC_LAYOUT_TASKS_REVERSE_SORT_OFF, + RSC_LAYOUT_TASKS_REVERSE_SORT_ON, + RSC_LAYOUT_TASKS_VALUE_SWITCH, + RSC_LAYOUT_TASKS_VALUE_OFF, + RSC_LAYOUT_TASKS_VALUE_ON, + RSC_LAYOUT_RULER_SENSORS, + RSC_LAYOUT_RULER_PWR_SOC, + RSC_LAYOUT_RULER_VOLTAGE, + RSC_LAYOUT_RULER_VPKG_SOC, + RSC_LAYOUT_RULER_ENERGY, + RSC_LAYOUT_RULER_POWER, + RSC_LAYOUT_RULER_SLICE, + RSC_LAYOUT_RULER_CUSTOM, +#endif /* NO_LOWER */ +#ifndef NO_FOOTER + RSC_LAYOUT_FOOTER_TECH_TSC, + RSC_LAYOUT_FOOTER_VOLT_TEMP, + RSC_LAYOUT_FOOTER_SYSTEM, + RSC_LAYOUT_FOOTER_TSC_NONE, + RSC_LAYOUT_FOOTER_TSC_VAR, + RSC_LAYOUT_FOOTER_TSC_INV, +#endif + RSC_LAYOUT_CARD_CORE_ONLINE_COND0, + RSC_LAYOUT_CARD_CORE_ONLINE_COND1, + RSC_LAYOUT_CARD_CORE_OFFLINE, + RSC_LAYOUT_CARD_CLK, + RSC_LAYOUT_CARD_UNCORE, + RSC_LAYOUT_CARD_BUS, + RSC_LAYOUT_CARD_MC, + RSC_LAYOUT_CARD_LOAD, + RSC_LAYOUT_CARD_IDLE, + RSC_LAYOUT_CARD_RAM, + RSC_LAYOUT_CARD_TASK, +/* ATTRIBUTE */ + RSC_RUN_STATE_COLOR, + RSC_UNINT_STATE_COLOR, + RSC_ZOMBIE_STATE_COLOR, + RSC_SLEEP_STATE_COLOR, + RSC_WAIT_STATE_COLOR, + RSC_OTHER_STATE_COLOR, +#ifndef NO_LOWER + RSC_TRACKER_STATE_COLOR, +#endif + RSC_SYSTEM_REGISTERS_COND0, + RSC_SYSTEM_REGISTERS_COND1, + RSC_SYSTEM_REGISTERS_COND2, + RSC_SYSTEM_REGISTERS_COND3, + RSC_SYSTEM_REGISTERS_COND4, + RSC_SYSINFO_PROC_COND0, + RSC_SYSINFO_PROC_COND1, + RSC_SYSINFO_PROC_COND2, + RSC_SYSINFO_PROC_COND3, + RSC_SYSINFO_ISA_COND_0_0, + RSC_SYSINFO_ISA_COND_0_1, + RSC_SYSINFO_ISA_COND_0_2, + RSC_SYSINFO_ISA_COND_0_3, + RSC_SYSINFO_ISA_COND_0_4, + RSC_SYSINFO_ISA_COND_1_0, + RSC_SYSINFO_ISA_COND_1_1, + RSC_SYSINFO_ISA_COND_1_2, + RSC_SYSINFO_ISA_COND_1_3, + RSC_SYSINFO_ISA_COND_1_4, + RSC_SYSINFO_FEATURES_COND0, + RSC_SYSINFO_FEATURES_COND1, + RSC_SYSINFO_FEATURES_COND2, + RSC_SYSINFO_FEATURES_COND3, + RSC_SYSINFO_FEATURES_COND4, + RSC_SYSINFO_TECH_COND0, + RSC_SYSINFO_TECH_COND1, + RSC_SYSINFO_PERFMON_COND0, + RSC_SYSINFO_PERFMON_COND1, + RSC_SYSINFO_PERFMON_COND2, + RSC_SYSINFO_PERFMON_COND3, + RSC_SYSINFO_PERFMON_COND4, + RSC_SYSINFO_PERFMON_HWP_CAP_COND0, + RSC_SYSINFO_PERFMON_HWP_CAP_COND1, + RSC_SYSINFO_PWR_THERMAL_COND0, + RSC_SYSINFO_PWR_THERMAL_COND1, + RSC_SYSINFO_PWR_THERMAL_COND2, + RSC_SYSINFO_PWR_THERMAL_COND3, + RSC_SYSINFO_PWR_THERMAL_COND4, + RSC_SYSINFO_PWR_THERMAL_COND5, + RSC_SYSINFO_PWR_THERMAL_COND6, + RSC_SYSINFO_KERNEL, + RSC_TOPOLOGY_COND0, + RSC_TOPOLOGY_COND1, + RSC_TOPOLOGY_COND2, + RSC_TOPOLOGY_COND3, + RSC_TOPOLOGY_COND4, + RSC_MEMORY_CONTROLLER_COND0, + RSC_MEMORY_CONTROLLER_COND1, + RSC_CREATE_MENU_DISABLE, + RSC_CREATE_MENU_FN_KEY, + RSC_CREATE_MENU_SHORTKEY, + RSC_CREATE_MENU_CTRL_KEY, + RSC_CREATE_SETTINGS_COND0, + RSC_CREATE_SETTINGS_COND1, + RSC_CREATE_ADV_HELP_COND0, + RSC_CREATE_ADV_HELP_COND1, + RSC_CREATE_HOTPLUG_CPU_TITLE, + RSC_CREATE_HOTPLUG_CPU_ENABLE, + RSC_CREATE_HOTPLUG_CPU_DISABLE, + RSC_CREATE_HOTPLUG_CPU_ONLINE, + RSC_CREATE_HOTPLUG_CPU_OFFLINE, + RSC_CREATE_RATIO_CLOCK_COND0, + RSC_CREATE_RATIO_CLOCK_COND1, + RSC_CREATE_RATIO_CLOCK_COND2, + RSC_CREATE_RATIO_CLOCK_COND3, + RSC_CREATE_RATIO_CLOCK_COND4, + RSC_CREATE_RATIO_CLOCK_COND5, + RSC_CREATE_RATIO_CLOCK_COND6, + RSC_CREATE_SELECT_CPU_COND0, + RSC_CREATE_SELECT_CPU_COND1, + RSC_CREATE_SELECT_CPU_COND2, +#ifndef NO_FOOTER + RSC_HOT_EVENT_COND0, + RSC_HOT_EVENT_COND1, + RSC_HOT_EVENT_COND2, + RSC_HOT_EVENT_COND3, + RSC_HOT_EVENT_COND4, +#endif + RSC_BOX_EVENT_COND00, + RSC_BOX_EVENT_COND01, + RSC_BOX_EVENT_COND10, + RSC_BOX_EVENT_COND11, + RSC_BOX_EVENT_BUTTON, + RSC_CREATE_RECORDER, + RSC_SMBIOS_ITEM, + RSC_CREATE_SELECT_FREQ_PKG, + RSC_CREATE_SELECT_FREQ_COND0, + RSC_CREATE_SELECT_FREQ_COND1, +/* ASCII */ + RSC_COREFREQ_TITLE, + RSC_PROCESSOR_TITLE, + RSC_PROCESSOR, + RSC_ARCHITECTURE, + RSC_VENDOR_ID, + RSC_HYBRID, + RSC_REVISION, + RSC_SIGNATURE, + RSC_STEPPING, + RSC_ONLINE_CPU, + RSC_BASE_CLOCK, + RSC_FREQUENCY, + RSC_RATIO, + RSC_FACTORY, + RSC_PERFORMANCE, + RSC_TARGET, + RSC_UNLOCK, + RSC_LOCK, + RSC_ENABLE, + RSC_DISABLE, + RSC_CAPABILITIES, + RSC_LOWEST, + RSC_EFFICIENT, + RSC_GUARANTEED, + RSC_HIGHEST, + RSC_RECORDER, + RSC_STRESS, + RSC_SYSGATE, + RSC_FREQ_UNIT_MHZ, + RSC_PPIN, + RSC_OPP, + RSC_UNCORE, + RSC_TURBO, + RSC_CPPC, + RSC_MAX, + RSC_MIN, + RSC_TGT, + RSC_TBH, + RSC_TBO, + RSC_ACT, + RSC_SCOPE_NONE, + RSC_SCOPE_THREAD, + RSC_SCOPE_CORE, + RSC_SCOPE_PACKAGE, + RSC_SYS_REGS_TITLE, + RSC_SYS_REGS_SPACE, + RSC_SYS_REGS_NA, + RSC_SYS_REGS_HDR_CPU, + RSC_SYS_REG_HDR_FLAGS, + RSC_SYS_REG_PSTATE, + RSC_SYS_REG_FLAG_N, + RSC_SYS_REG_FLAG_Z, + RSC_SYS_REG_FLAG_C, + RSC_SYS_REG_FLAG_V, + RSC_SYS_REG_FLAG_D, + RSC_SYS_REG_FLAG_A, + RSC_SYS_REG_FLAG_I, + RSC_SYS_REG_FLAG_F, + RSC_SYS_REG_FLAG_EL, + RSC_SYS_REG_FLAG_SM, + RSC_SYS_REG_FLAG_SSBS, + RSC_SYS_REG_FLAG_NMI, + RSC_SYS_REG_FLAG_PAN, + RSC_SYS_REG_FLAG_UAO, + RSC_SYS_REG_FLAG_DIT, + RSC_SYS_REG_FLAG_TCO, + RSC_SYS_REG_FLAG_PM, + RSC_SYS_REG_HDR11_SCTL, + RSC_SYS_REG_HDR12_SCTL, + RSC_SYS_REG_HDR21_SCTL, + RSC_SYS_REG_HDR22_SCTL, + RSC_SYS_REG_HDR31_SCTL, + RSC_SYS_REG_HDR41_SCTL, + RSC_SYS_REG_SCTL, + RSC_SYS_REG_TIDCP, + RSC_SYS_REG_SPINT, + RSC_SYS_REG_NMI, + RSC_SYS_REG_EnTP2, + RSC_SYS_REG_TCSO, + RSC_SYS_REG_TCSO1, + RSC_SYS_REG_TCSO0, + RSC_SYS_REG_EPAN, + RSC_SYS_REG_EnALS, + RSC_SYS_REG_EnAS0, + RSC_SYS_REG_EnASR, + RSC_SYS_REG_TME, + RSC_SYS_REG_TME1, + RSC_SYS_REG_TME0, + RSC_SYS_REG_TMT, + RSC_SYS_REG_TMT1, + RSC_SYS_REG_TMT0, + RSC_SYS_REG_TWE_D, + RSC_SYS_REG_TWE_C, + RSC_SYS_REG_TWE_E, + RSC_SYS_REG_DSSBS, + RSC_SYS_REG_ATA, + RSC_SYS_REG_ATA1, + RSC_SYS_REG_ATA0, + RSC_SYS_REG_TCF, + RSC_SYS_REG_TCF1, + RSC_SYS_REG_TCF0, + RSC_SYS_REG_ITFSB, + RSC_SYS_REG_BT, + RSC_SYS_REG_BT1, + RSC_SYS_REG_BT0, + RSC_SYS_REG_EnFPM, + RSC_SYS_REG_MSCEn, + RSC_SYS_REG_CMOW, + RSC_SYS_REG_EnIA, + RSC_SYS_REG_EnIB, + RSC_SYS_REG_LSM, + RSC_SYS_REG_LSMA, + RSC_SYS_REG_LSMD, + RSC_SYS_REG_EnDA, + RSC_SYS_REG_UCI, + RSC_SYS_REG_EE, + RSC_SYS_REG_E0E, + RSC_SYS_REG_SPAN, + RSC_SYS_REG_EIS, + RSC_SYS_REG_IESB, + RSC_SYS_REG_TSCXT, + RSC_SYS_REG_WXN, + RSC_SYS_REG_nTWE, + RSC_SYS_REG_nTWI, + RSC_SYS_REG_UCT, + RSC_SYS_REG_DZE, + RSC_SYS_REG_EnDB, + RSC_SYS_REG_I, + RSC_SYS_REG_EOS, + RSC_SYS_REG_RCTX, + RSC_SYS_REG_UMA, + RSC_SYS_REG_SED, + RSC_SYS_REG_ITD, + RSC_SYS_REG_nAA, + RSC_SYS_REG_CP15B, + RSC_SYS_REG_SA0, + RSC_SYS_REG_SA1, + RSC_SYS_REG_C, + RSC_SYS_REG_A, + RSC_SYS_REG_M, + RSC_SYS_REG_HDR11_SCTL2, + RSC_SYS_REG_HDR12_SCTL2, + RSC_SYS_REG_SCTL2, + RSC_SYS_REG_CPTM, + RSC_SYS_REG_CPTM0, + RSC_SYS_REG_CPTM1, + RSC_SYS_REG_CPTA, + RSC_SYS_REG_CPTA0, + RSC_SYS_REG_CPTA1, + RSC_SYS_REG_PACM, + RSC_SYS_REG_PACM0, + RSC_SYS_REG_PACM1, + RSC_SYS_REG_128SR, + RSC_SYS_REG_EASE, + RSC_SYS_REG_ANERR, + RSC_SYS_REG_ADERR, + RSC_SYS_REG_NMEA, + RSC_SYS_REG_HDR_FPSR, + RSC_SYS_REG_FPSR, + RSC_SYS_REG_FPSR_QC, + RSC_SYS_REG_FPSR_IDC, + RSC_SYS_REG_FPSR_IXC, + RSC_SYS_REG_FPSR_UFC, + RSC_SYS_REG_FPSR_OFC, + RSC_SYS_REG_FPSR_DZC, + RSC_SYS_REG_FPSR_IOC, + RSC_SYS_REG_HDR11_EL, + RSC_SYS_REG_HDR12_EL, + RSC_SYS_REG_EL, + RSC_SYS_REG_EL_EXEC, + RSC_SYS_REG_EL_SEC, + RSC_ISA_TITLE, + RSC_ISA_AES, + RSC_ISA_AES_COMM, + RSC_ISA_PMULL, + RSC_ISA_LSE, + RSC_ISA_LSE_COMM, + RSC_ISA_LSE128, + RSC_ISA_CRC32, + RSC_ISA_CRC32_COMM, + RSC_ISA_DP, + RSC_ISA_DP_COMM, + RSC_ISA_EPAC, + RSC_ISA_EPAC_COMM, + RSC_ISA_FCMA, + RSC_ISA_FCMA_COMM, + RSC_ISA_FHM, + RSC_ISA_FHM_COMM, + RSC_ISA_FP, + RSC_ISA_FP_COMM, + RSC_ISA_FPAC, + RSC_ISA_FPAC_COMM, + RSC_ISA_FPACCOMBINE, + RSC_ISA_FPACCOMBINE_COMM, + RSC_ISA_JSCVT, + RSC_ISA_JSCVT_COMM, + RSC_ISA_LRCPC, + RSC_ISA_LRCPC2, + RSC_ISA_LRCPC3, + RSC_ISA_LRCPC_COMM, + RSC_ISA_LUT, + RSC_ISA_LUT_COMM, + RSC_ISA_MOPS, + RSC_ISA_MOPS_COMM, + RSC_ISA_PACGA, + RSC_ISA_PACIMP_COMM, + RSC_ISA_PACQARMA3, + RSC_ISA_PACQARMA3_COMM, + RSC_ISA_PACQARMA5, + RSC_ISA_PACQARMA5_COMM, + RSC_ISA_PAUTH, + RSC_ISA_PAUTH_COMM, + RSC_ISA_PAUTH2, + RSC_ISA_PAUTH2_COMM, + RSC_ISA_PAUTH_LR, + RSC_ISA_PAUTH_LR_COMM, + RSC_ISA_PRFMSLC, + RSC_ISA_PRFMSLC_COMM, + RSC_ISA_FRINTTS, + RSC_ISA_FRINTTS_COMM, + RSC_ISA_SPECRES, + RSC_ISA_SPECRES_COMM, + RSC_ISA_SPECRES2, + RSC_ISA_ATS1A, + RSC_ISA_ATS1A_COMM, + RSC_ISA_BF16, + RSC_ISA_BF16_COMM, + RSC_ISA_EBF16, + RSC_ISA_EBF16_COMM, + RSC_ISA_CONSTPACFLD, + RSC_ISA_CONSTPACFLD_COMM, + RSC_ISA_CSSC, + RSC_ISA_CSSC_COMM, + RSC_ISA_HBC, + RSC_ISA_HBC_COMM, + RSC_ISA_I8MM, + RSC_ISA_I8MM_COMM, + RSC_ISA_RPRES, + RSC_ISA_RPRES_COMM, + RSC_ISA_SB, + RSC_ISA_SB_COMM, + RSC_ISA_SYSREG128, + RSC_ISA_SYSREG128_COMM, + RSC_ISA_SYSINSTR128, + RSC_ISA_SYSINSTR128_COMM, + RSC_ISA_WFxT, + RSC_ISA_WFxT_COMM, + RSC_ISA_XS, + RSC_ISA_XS_COMM, + RSC_ISA_LS64, + RSC_ISA_LS64_COMM, + RSC_ISA_LS64_V, + RSC_ISA_LS64_ACCDATA, + RSC_ISA_DGH, + RSC_ISA_DGH_COMM, + RSC_ISA_DPB, + RSC_ISA_DPB_COMM, + RSC_ISA_DPB2, + RSC_ISA_RAND, + RSC_ISA_RAND_COMM, + RSC_ISA_RDMA, + RSC_ISA_RDMA_COMM, + RSC_ISA_RNG_TRAP, + RSC_ISA_RNG_TRAP_COMM, + RSC_ISA_RPRFM, + RSC_ISA_RPRFM_COMM, + RSC_ISA_SHA1, + RSC_ISA_SHA256, + RSC_ISA_SHA512, + RSC_ISA_SHA3, + RSC_ISA_SHA_COMM, + RSC_ISA_SM3, + RSC_ISA_SM4, + RSC_ISA_SM_COMM, + RSC_ISA_SIMD, + RSC_ISA_SIMD_COMM, + RSC_ISA_SME, + RSC_ISA_SME_COMM, + RSC_ISA_SVE, + RSC_ISA_SVE_COMM, + RSC_ISA_SVE_F64MM, + RSC_ISA_SVE_F32MM, + RSC_ISA_SVE_I8MM, + RSC_ISA_SVE_SM4, + RSC_ISA_SVE_SHA3, + RSC_ISA_SVE_BF16, + RSC_ISA_SVE_EBF16, + RSC_ISA_SVE_BitPerm, + RSC_ISA_SVE_AES, + RSC_ISA_SVE_PMULL128, + RSC_ISA_SVE2, + RSC_ISA_SME2, + RSC_ISA_SME2p1, + RSC_ISA_SME_FA64, + RSC_ISA_SME_LUTv2, + RSC_ISA_SME_I16I64, + RSC_ISA_SME_F64F64, + RSC_ISA_SME_I16I32, + RSC_ISA_SME_B16B16, + RSC_ISA_SME_F16F16, + RSC_ISA_SME_F8F16, + RSC_ISA_SME_F8F32, + RSC_ISA_SME_I8I32, + RSC_ISA_SME_F16F32, + RSC_ISA_SME_B16F32, + RSC_ISA_SME_BI32I32, + RSC_ISA_SME_F32F32, + RSC_ISA_SME_SF8FMA, + RSC_ISA_SME_SF8DP4, + RSC_ISA_SME_SF8DP2, + RSC_ISA_FlagM, + RSC_ISA_FlagM_COMM, + RSC_ISA_FlagM2, + RSC_FEATURES_TITLE, + RSC_ON, + RSC_OFF, + RSC_FMW, + RSC_NOT_AVAILABLE, + RSC_AUTOMATIC, + RSC_UNABLE, + RSC_MISSING, + RSC_PRESENT, + RSC_VARIANT, + RSC_INVARIANT, + RSC_FEATURES_ACPI, + RSC_FEATURES_AMU, + RSC_FEATURES_BIG_END, + RSC_FEATURES_BTI, + RSC_FEATURES_EBEP, + RSC_FEATURES_ECBHB, + RSC_FEATURES_ECV, + RSC_FEATURES_DF2, + RSC_FEATURES_DIT, + RSC_FEATURES_EXS, + RSC_FEATURES_FGT, + RSC_FEATURES_PFAR, + RSC_FEATURES_GCS, + RSC_FEATURES_GIC, + RSC_FEATURES_MPAM, + RSC_FEATURES_MTE, + RSC_FEATURES_NMI, + RSC_FEATURES_PA, + RSC_FEATURES_PAN, + RSC_FEATURES_RAS, + RSC_FEATURES_RME, + RSC_FEATURES_SEL2, + RSC_FEATURES_THE, + RSC_FEATURES_TLB, + RSC_FEATURES_TME, + RSC_FEATURES_TSC, + RSC_FEATURES_UAO, + RSC_FEATURES_VA, + RSC_FEATURES_VHE, + RSC_FEAT_SECTION_MECH, + RSC_FEAT_SECTION_SEC, + RSC_TECHNOLOGIES_TITLE, + RSC_TECHNOLOGIES_DCU, + RSC_TECHNOLOGIES_ICU, + RSC_TECHNOLOGIES_VM, + RSC_TECHNOLOGIES_VM_COMM, + RSC_TECHNOLOGIES_IOMMU, + RSC_TECHNOLOGIES_IOMMU_COMM, + RSC_TECHNOLOGIES_SMT, + RSC_TECHNOLOGIES_HYBRID, + RSC_TECHNOLOGIES_HYPERV, + RSC_TECH_HYPERV_NONE, + RSC_TECH_BARE_METAL, + RSC_TECH_HYPERV_XEN, + RSC_TECH_HYPERV_KVM, + RSC_TECH_HYPERV_VBOX, + RSC_TECH_HYPERV_KBOX, + RSC_TECH_HYPERV_VMWARE, + RSC_TECH_HYPERV_HYPERV, + RSC_PERF_MON_TITLE, + RSC_PERF_CAPS_TITLE, + RSC_VERSION, + RSC_COUNTERS, + RSC_GENERAL_CTRS, + RSC_FIXED_CTRS, + RSC_PERF_MON_UNIT_BIT, + RSC_PERF_MON_CPPC, + RSC_PERF_MON_PCT, + RSC_PERF_MON_PSS, + RSC_PERF_MON_PPC, + RSC_PERF_MON_CPC, + RSC_PERF_MON_CST, + RSC_PERF_MON_HWP, + RSC_PERF_MON_CORE_CSTATE, + RSC_PERF_MON_CSTATE_BAR, + RSC_PERF_MON_MONITOR_MWAIT, + RSC_PERF_MON_MWAIT_IDX_CSTATE, + RSC_PERF_MON_MWAIT_SUB_CSTATE, + RSC_PERF_MON_CORE_CYCLE, + RSC_PERF_MON_INST_RET, + RSC_PERF_MON_PMC_COMM, + RSC_PERF_MON_CPPC_COMM, + RSC_PERF_LABEL_VER, + RSC_PERF_LABEL_HWCF, + RSC_PERF_LABEL_CPPC, + RSC_PERF_LABEL_PCT, + RSC_PERF_LABEL_PSS, + RSC_PERF_LABEL_PPC, + RSC_PERF_LABEL_CPC, + RSC_PERF_LABEL_CST, + RSC_PERF_LABEL_HWP, + RSC_PERF_LABEL_CST_BAR, + RSC_PERF_LABEL_MWAIT_IDX, + RSC_PERF_ENCODING_C0, + RSC_PERF_ENCODING_C1, + RSC_PERF_ENCODING_C2, + RSC_PERF_ENCODING_C3, + RSC_PERF_ENCODING_C4, + RSC_PERF_ENCODING_C6, + RSC_PERF_ENCODING_C6R, + RSC_PERF_ENCODING_C7, + RSC_PERF_ENCODING_C7S, + RSC_PERF_ENCODING_C8, + RSC_PERF_ENCODING_C9, + RSC_PERF_ENCODING_C10, + RSC_PERF_ENCODING_UNS, + RSC_POWER_THERMAL_TITLE, + RSC_POWER_THERMAL_CPPC, + RSC_POWER_THERMAL_TJMAX, + RSC_POWER_THERMAL_DTS, + RSC_POWER_THERMAL_PLN, + RSC_POWER_THERMAL_PTM, + RSC_POWER_THERMAL_UNITS, + RSC_POWER_THERMAL_POWER, + RSC_POWER_THERMAL_ENERGY, + RSC_POWER_THERMAL_WINDOW, + RSC_POWER_THERMAL_WATT, + RSC_POWER_THERMAL_JOULE, + RSC_POWER_THERMAL_SECOND, + RSC_POWER_THERMAL_TDP, + RSC_POWER_THERMAL_MIN, + RSC_POWER_THERMAL_MAX, + RSC_POWER_THERMAL_TPL, + RSC_POWER_THERMAL_TW, + RSC_POWER_THERMAL_EDC, + RSC_POWER_THERMAL_TDC, + RSC_POWER_THERMAL_POINT, + RSC_THERMAL_POINT_THRESHOLD, + RSC_THERMAL_POINT_LIMIT, + RSC_THERMAL_POINT_THRESHOLD_1, + RSC_THERMAL_POINT_THRESHOLD_2, + RSC_THERMAL_POINT_TRIP_LIMIT, + RSC_THERMAL_POINT_HTC_LIMIT, + RSC_THERMAL_POINT_HTC_HYST, + RSC_THERMAL_OFFSET_TITLE, + RSC_POWER_LABEL_CPPC, + RSC_POWER_LABEL_TJ, + RSC_POWER_LABEL_DTS, + RSC_POWER_LABEL_PLN, + RSC_POWER_LABEL_PTM, + RSC_POWER_LABEL_TDP, + RSC_POWER_LABEL_MIN, + RSC_POWER_LABEL_MAX, + RSC_POWER_LABEL_PL1, + RSC_POWER_LABEL_PL2, + RSC_POWER_LABEL_TW1, + RSC_POWER_LABEL_TW2, + RSC_POWER_LABEL_EDC, + RSC_POWER_LABEL_TDC, + RSC_POWER_LABEL_PKG, + RSC_POWER_LABEL_CORE, + RSC_POWER_LABEL_UNCORE, + RSC_POWER_LABEL_DRAM, + RSC_POWER_LABEL_PLATFORM, + RSC_KERNEL_TITLE, + RSC_KERNEL_TOTAL_RAM, + RSC_KERNEL_SHARED_RAM, + RSC_KERNEL_FREE_RAM, + RSC_KERNEL_BUFFER_RAM, + RSC_KERNEL_TOTAL_HIGH, + RSC_KERNEL_FREE_HIGH, + RSC_KERNEL_GOVERNOR, + RSC_KERNEL_FREQ_DRIVER, + RSC_KERNEL_IDLE_DRIVER, + RSC_KERNEL_CLOCK_SOURCE, + RSC_KERNEL_RELEASE, + RSC_KERNEL_VERSION, + RSC_KERNEL_MACHINE, + RSC_KERNEL_MEMORY, + RSC_KERNEL_STATE, + RSC_KERNEL_POWER, + RSC_KERNEL_LATENCY, + RSC_KERNEL_RESIDENCY, + RSC_KERNEL_LIMIT, + RSC_TOPOLOGY_TITLE, + RSC_TOPOLOGY_FMT0, + RSC_TOPOLOGY_FMT1, + RSC_TOPOLOGY_OFF_0, + RSC_TOPOLOGY_OFF_1, + RSC_TOPOLOGY_OFF_2, + RSC_TOPOLOGY_OFF_3, + RSC_TOPOLOGY_HDR_PKG, + RSC_TOPOLOGY_HDR_SMT, + RSC_TOPOLOGY_HDR_CACHE, + RSC_TOPOLOGY_HDR_WRBAK, + RSC_TOPOLOGY_HDR_INCL, + RSC_TOPOLOGY_HDR_EMPTY, + RSC_TOPOLOGY_SUB_ITEM1, + RSC_TOPOLOGY_SUB_ITEM3, + RSC_TOPOLOGY_SUB_ITEM4, + RSC_TOPOLOGY_SUB_ITEM5, + RSC_TOPOLOGY_SUB_ITEM6, + RSC_TOPOLOGY_ALT_ITEM1, + RSC_TOPOLOGY_ALT_ITEM2, + RSC_TOPOLOGY_ALT_ITEM3, + RSC_TOPOLOGY_ALT_ITEM4, + RSC_TOPOLOGY_BSP_COMM, + RSC_MEM_CTRL_TITLE, + RSC_MEM_CTRL_UNIT_MHZ, + RSC_MEM_CTRL_UNIT_MTS, + RSC_MEM_CTRL_UNIT_MBS, + RSC_MEM_CTRL_MTY_CELL, + RSC_MEM_CTRL_CHANNEL, + RSC_MEM_CTRL_SUBSECT1_0, + RSC_MEM_CTRL_SUBSECT1_1, + RSC_MEM_CTRL_SUBSECT1_2, + RSC_MEM_CTRL_SINGLE_CHA_0, + RSC_MEM_CTRL_SINGLE_CHA_1, + RSC_MEM_CTRL_SINGLE_CHA_2, + RSC_MEM_CTRL_DUAL_CHA_0, + RSC_MEM_CTRL_DUAL_CHA_1, + RSC_MEM_CTRL_DUAL_CHA_2, + RSC_MEM_CTRL_TRIPLE_CHA_0, + RSC_MEM_CTRL_TRIPLE_CHA_1, + RSC_MEM_CTRL_TRIPLE_CHA_2, + RSC_MEM_CTRL_QUAD_CHA_0, + RSC_MEM_CTRL_QUAD_CHA_1, + RSC_MEM_CTRL_QUAD_CHA_2, + RSC_MEM_CTRL_SIX_CHA_0, + RSC_MEM_CTRL_SIX_CHA_1, + RSC_MEM_CTRL_SIX_CHA_2, + RSC_MEM_CTRL_EIGHT_CHA_0, + RSC_MEM_CTRL_EIGHT_CHA_1, + RSC_MEM_CTRL_EIGHT_CHA_2, + RSC_MEM_CTRL_DISABLED_0, + RSC_MEM_CTRL_DISABLED_1, + RSC_MEM_CTRL_DISABLED_2, + RSC_MEM_CTRL_BUS_RATE_0, + RSC_MEM_CTRL_BUS_RATE_1, + RSC_MEM_CTRL_BUS_SPEED_0, + RSC_MEM_CTRL_BUS_SPEED_1, + RSC_MEM_CTRL_RAM_STD_0, + RSC_MEM_CTRL_RAM_STD_1, + RSC_MEM_CTRL_RAM_STD_2, + RSC_MEM_CTRL_RAM_STD_3, + RSC_MEM_CTRL_DRAM_DDR2_0, + RSC_MEM_CTRL_DRAM_DDR3_0, + RSC_MEM_CTRL_DRAM_DDR4_0, + RSC_MEM_CTRL_DRAM_DDR5_0, + RSC_MEM_CTRL_DRAM_SPEED_0, + RSC_MEM_CTRL_DRAM_SPEED_1, + RSC_MEM_CTRL_SUBSECT2_0, + RSC_MEM_CTRL_SUBSECT2_1, + RSC_MEM_CTRL_SUBSECT2_2, + RSC_MEM_CTRL_SUBSECT2_3, + RSC_MEM_CTRL_SUBSECT2_4, + RSC_MEM_CTRL_SUBSECT2_5, + RSC_MEM_CTRL_DIMM_SLOT, + RSC_MEM_CTRL_DIMM_BANK, + RSC_MEM_CTRL_DIMM_RANK, + RSC_MEM_CTRL_DIMM_ROW, + RSC_MEM_CTRL_DIMM_COLUMN0, + RSC_MEM_CTRL_DIMM_COLUMN1, + RSC_MEM_CTRL_DIMM_SIZE_0, + RSC_MEM_CTRL_DIMM_SIZE_1, + RSC_MEM_CTRL_DIMM_SIZE_2, + RSC_MEM_CTRL_DIMM_SIZE_3, + RSC_DDR3_CL, + RSC_DDR3_RCD, + RSC_DDR3_RP, + RSC_DDR3_RAS, + RSC_DDR3_RRD, + RSC_DDR3_RFC, + RSC_DDR3_WR, + RSC_DDR3_RTP, + RSC_DDR3_WTP, + RSC_DDR3_FAW, + RSC_DDR3_B2B, + RSC_DDR3_CWL, + RSC_DDR3_CMD, + RSC_DDR3_REFI, + RSC_DDR3_DDWRTRD, + RSC_DDR3_DRWRTRD, + RSC_DDR3_SRWRTRD, + RSC_DDR3_DDRDTWR, + RSC_DDR3_DRRDTWR, + RSC_DDR3_SRRDTWR, + RSC_DDR3_DDRDTRD, + RSC_DDR3_DRRDTRD, + RSC_DDR3_SRRDTRD, + RSC_DDR3_DDWRTWR, + RSC_DDR3_DRWRTWR, + RSC_DDR3_SRWRTWR, + RSC_DDR3_XS, + RSC_DDR3_XP, + RSC_DDR3_CKE, + RSC_DDR3_ECC, + RSC_DDR4_CL, + RSC_DDR4_RCD_R, + RSC_DDR4_RCD_W, + RSC_DDR4_RP, + RSC_DDR4_RAS, + RSC_DDR4_RRD, + RSC_DDR4_RFC, + RSC_DDR4_WR, + RSC_DDR4_RTP, + RSC_DDR4_WTP, + RSC_DDR4_FAW, + RSC_DDR4_GEAR, + RSC_DDR4_CWL, + RSC_DDR4_CMD, + RSC_DDR4_REFI, + RSC_DDR4_RDRD_SCL, + RSC_DDR4_RDRD_SC, + RSC_DDR4_RDRD_SD, + RSC_DDR4_RDRD_DD, + RSC_DDR4_RDWR_SCL, + RSC_DDR4_RDWR_SC, + RSC_DDR4_RDWR_SD, + RSC_DDR4_RDWR_DD, + RSC_DDR4_WRRD_SCL, + RSC_DDR4_WRRD_SC, + RSC_DDR4_WRRD_SD, + RSC_DDR4_WRRD_DD, + RSC_DDR4_WRWR_SCL, + RSC_DDR4_WRWR_SC, + RSC_DDR4_WRWR_SD, + RSC_DDR4_WRWR_DD, + RSC_DDR4_RRD_S, + RSC_DDR4_RRD_L, + RSC_DDR4_CKE, + RSC_DDR4_CPDED, + RSC_DDR4_ECC, + RSC_DDR4_ZEN_CL, + RSC_DDR4_ZEN_RP, + RSC_DDR4_ZEN_RAS, + RSC_DDR4_ZEN_RC, + RSC_DDR4_ZEN_FAW, + RSC_DDR4_ZEN_WTR_S, + RSC_DDR4_ZEN_WTR_L, + RSC_DDR4_ZEN_WR, + RSC_DDR4_ZEN_RDRD_SCL, + RSC_DDR4_ZEN_WRWR_SCL, + RSC_DDR4_ZEN_CWL, + RSC_DDR4_ZEN_RTP, + RSC_DDR4_ZEN_RDWR, + RSC_DDR4_ZEN_WRRD, + RSC_DDR4_ZEN_WRWR_SC, + RSC_DDR4_ZEN_WRWR_SD, + RSC_DDR4_ZEN_WRWR_DD, + RSC_DDR4_ZEN_RDRD_SC, + RSC_DDR4_ZEN_RDRD_SD, + RSC_DDR4_ZEN_RDRD_DD, + RSC_DDR4_ZEN_RTR_DLR, + RSC_DDR4_ZEN_WTW_DLR, + RSC_DDR4_ZEN_WTR_DLR, + RSC_DDR4_ZEN_RRD_DLR, + RSC_DDR4_ZEN_REFI, + RSC_DDR4_ZEN_RFC1, + RSC_DDR4_ZEN_RFC2, + RSC_DDR4_ZEN_RFC4, + RSC_DDR4_ZEN_RCPB, + RSC_DDR4_ZEN_RPPB, + RSC_DDR4_ZEN_BGS, + RSC_DDR4_ZEN_BGS_ALT, + RSC_DDR4_ZEN_BAN, + RSC_DDR4_ZEN_RCPAGE, + RSC_DDR4_ZEN_GDM, + RSC_DDR4_ZEN_ECC, + RSC_DDR4_ZEN_MRD, + RSC_DDR4_ZEN_MOD, + RSC_DDR4_ZEN_MRD_PDA, + RSC_DDR4_ZEN_MOD_PDA, + RSC_DDR4_ZEN_WRMPR, + RSC_DDR4_ZEN_STAG, + RSC_DDR4_ZEN_PDM, + RSC_DDR4_ZEN_RDDATA, + RSC_DDR4_ZEN_PHYWRD, + RSC_DDR4_ZEN_PHYWRL, + RSC_DDR4_ZEN_PHYRDL, + RSC_DDR5_ZEN_RFC_SB, + RSC_DDR5_ZEN_RCPB, + RSC_DDR5_ZEN_RPPB, + RSC_DDR5_ZEN_BGS, + RSC_DDR3_CL_COMM, + RSC_DDR3_RCD_COMM, + RSC_DDR3_RP_COMM, + RSC_DDR3_RAS_COMM, + RSC_DDR3_RRD_COMM, + RSC_DDR3_RFC_COMM, + RSC_DDR3_WR_COMM, + RSC_DDR3_RTP_COMM, + RSC_DDR3_WTP_COMM, + RSC_DDR3_FAW_COMM, + RSC_DDR3_B2B_COMM, + RSC_DDR3_CWL_COMM, + RSC_DDR3_CMD_COMM, + RSC_DDR3_REFI_COMM, + RSC_DDR3_DDWRTRD_COMM, + RSC_DDR3_DRWRTRD_COMM, + RSC_DDR3_SRWRTRD_COMM, + RSC_DDR3_DDRDTWR_COMM, + RSC_DDR3_DRRDTWR_COMM, + RSC_DDR3_SRRDTWR_COMM, + RSC_DDR3_DDRDTRD_COMM, + RSC_DDR3_DRRDTRD_COMM, + RSC_DDR3_SRRDTRD_COMM, + RSC_DDR3_DDWRTWR_COMM, + RSC_DDR3_DRWRTWR_COMM, + RSC_DDR3_SRWRTWR_COMM, + RSC_DDR3_XS_COMM, + RSC_DDR3_XP_COMM, + RSC_DDR3_CKE_COMM, + RSC_DDR3_ECC_COMM, + RSC_DDR4_RCD_R_COMM, + RSC_DDR4_RCD_W_COMM, + RSC_DDR4_RDRD_SCL_COMM, + RSC_DDR4_RDRD_SC_COMM, + RSC_DDR4_RDRD_SD_COMM, + RSC_DDR4_RDRD_DD_COMM, + RSC_DDR4_RDWR_SCL_COMM, + RSC_DDR4_RDWR_SC_COMM, + RSC_DDR4_RDWR_SD_COMM, + RSC_DDR4_RDWR_DD_COMM, + RSC_DDR4_WRRD_SCL_COMM, + RSC_DDR4_WRRD_SC_COMM, + RSC_DDR4_WRRD_SD_COMM, + RSC_DDR4_WRRD_DD_COMM, + RSC_DDR4_WRWR_SCL_COMM, + RSC_DDR4_WRWR_SC_COMM, + RSC_DDR4_WRWR_SD_COMM, + RSC_DDR4_WRWR_DD_COMM, + RSC_DDR4_RRD_S_COMM, + RSC_DDR4_RRD_L_COMM, + RSC_DDR4_CPDED_COMM, + RSC_DDR4_GEAR_COMM, + RSC_DDR4_ZEN_RC_COMM, + RSC_DDR4_ZEN_WTR_S_COMM, + RSC_DDR4_ZEN_WTR_L_COMM, + RSC_DDR4_ZEN_RDRD_SCL_COMM, + RSC_DDR4_ZEN_WRWR_SCL_COMM, + RSC_DDR4_ZEN_RTP_COMM, + RSC_DDR4_ZEN_RDWR_COMM, + RSC_DDR4_ZEN_WRRD_COMM, + RSC_DDR4_ZEN_WRWR_SC_COMM, + RSC_DDR4_ZEN_WRWR_SD_COMM, + RSC_DDR4_ZEN_WRWR_DD_COMM, + RSC_DDR4_ZEN_RDRD_SC_COMM, + RSC_DDR4_ZEN_RDRD_SD_COMM, + RSC_DDR4_ZEN_RDRD_DD_COMM, + RSC_DDR4_ZEN_RTR_DLR_COMM, + RSC_DDR4_ZEN_WTW_DLR_COMM, + RSC_DDR4_ZEN_WTR_DLR_COMM, + RSC_DDR4_ZEN_RRD_DLR_COMM, + RSC_DDR4_ZEN_RFC1_COMM, + RSC_DDR4_ZEN_RFC2_COMM, + RSC_DDR4_ZEN_RFC4_COMM, + RSC_DDR4_ZEN_RCPB_COMM, + RSC_DDR4_ZEN_RPPB_COMM, + RSC_DDR4_ZEN_BGS_COMM, + RSC_DDR4_ZEN_BGS_ALT_COMM, + RSC_DDR4_ZEN_BAN_COMM, + RSC_DDR4_ZEN_RCPAGE_COMM, + RSC_DDR4_ZEN_GDM_COMM, + RSC_DDR4_ZEN_MRD_COMM, + RSC_DDR4_ZEN_MOD_COMM, + RSC_DDR4_ZEN_MRD_PDA_COMM, + RSC_DDR4_ZEN_MOD_PDA_COMM, + RSC_DDR4_ZEN_WRMPR_COMM, + RSC_DDR4_ZEN_STAG_COMM, + RSC_DDR4_ZEN_PDM_COMM, + RSC_DDR4_ZEN_RDDATA_COMM, + RSC_DDR4_ZEN_PHYWRD_COMM, + RSC_DDR4_ZEN_PHYWRL_COMM, + RSC_DDR4_ZEN_PHYRDL_COMM, + RSC_DDR5_ZEN_RFC_SB_COMM, + RSC_TASKS_SORTBY_STATE, + RSC_TASKS_SORTBY_RTIME, + RSC_TASKS_SORTBY_UTIME, + RSC_TASKS_SORTBY_STIME, + RSC_TASKS_SORTBY_PID, + RSC_TASKS_SORTBY_COMM, + RSC_MENU_ITEM_MENU, + RSC_MENU_ITEM_VIEW, + RSC_MENU_ITEM_WINDOW, + RSC_MENU_ITEM_SPACER, + RSC_MENU_ITEM_DATE_TIME, + RSC_MENU_ITEM_FULL_TIME, + RSC_MENU_ITEM_TINY_TIME, + RSC_MENU_ITEM_SETTINGS, + RSC_MENU_ITEM_SMBIOS, + RSC_MENU_ITEM_KERNEL, + RSC_MENU_ITEM_HOTPLUG, + RSC_MENU_ITEM_TOOLS, + RSC_MENU_ITEM_THEME, + RSC_MENU_ITEM_ABOUT, + RSC_MENU_ITEM_HELP, + RSC_MENU_ITEM_KEYS, + RSC_MENU_ITEM_LANG, + RSC_MENU_ITEM_QUIT, + RSC_MENU_ITEM_DASHBOARD, + RSC_MENU_ITEM_FREQUENCY, + RSC_MENU_ITEM_INST_CYCLES, + RSC_MENU_ITEM_CORE_CYCLES, + RSC_MENU_ITEM_IDLE_STATES, + RSC_MENU_ITEM_PKG_CYCLES, + RSC_MENU_ITEM_TASKS_MON, + RSC_MENU_ITEM_SYS_INTER, + RSC_MENU_ITEM_SENSORS, + RSC_MENU_ITEM_VOLTAGE, + RSC_MENU_ITEM_POWER, + RSC_MENU_ITEM_SLICE_CTRS, + RSC_MENU_ITEM_CUSTOM, + RSC_MENU_ITEM_PROCESSOR, + RSC_MENU_ITEM_TOPOLOGY, + RSC_MENU_ITEM_FEATURES, + RSC_MENU_ITEM_ISA_EXT, + RSC_MENU_ITEM_TECH, + RSC_MENU_ITEM_PERF_MON, + RSC_MENU_ITEM_PERF_CAPS, + RSC_MENU_ITEM_POW_THERM, + RSC_MENU_ITEM_SYS_REGS, + RSC_MENU_ITEM_MEM_CTRL, + RSC_MENU_ITEM_EVENTS, + RSC_SETTINGS_TITLE, + RSC_SETTINGS_DAEMON, + RSC_SETTINGS_INTERVAL, + RSC_SETTINGS_SYS_TICK, + RSC_SETTINGS_POLL_WAIT, + RSC_SETTINGS_RING_WAIT, + RSC_SETTINGS_CHILD_WAIT, + RSC_SETTINGS_SLICE_WAIT, + RSC_SETTINGS_RECORDER, + RSC_SETTINGS_AUTO_CLOCK, + RSC_SETTINGS_EXPERIMENTAL, + RSC_SETTINGS_CPU_HOTPLUG, + RSC_SETTINGS_PCI_ENABLED, + RSC_SETTINGS_NMI_REGISTERED, + RSC_SETTINGS_CPUIDLE_REGISTERED, + RSC_SETTINGS_CPUFREQ_REGISTERED, + RSC_SETTINGS_GOVERNOR_REGISTERED, + RSC_SETTINGS_CS_REGISTERED, + RSC_SETTINGS_THERMAL_SCOPE, + RSC_SETTINGS_VOLTAGE_SCOPE, + RSC_SETTINGS_POWER_SCOPE, + RSC_SETTINGS_IDLE_ROUTE, + RSC_SETTINGS_ROUTE_TITLE, + RSC_SETTINGS_ROUTE_DFLT, + RSC_SETTINGS_ROUTE_IO, + RSC_SETTINGS_ROUTE_HALT, + RSC_SETTINGS_ROUTE_MWAIT, + RSC_HELP_TITLE, + RSC_HELP_KEY_ESCAPE, + RSC_HELP_KEY_SHIFT_TAB, + RSC_HELP_KEY_TAB, + RSC_HELP_KEY_UP, + RSC_HELP_KEY_LEFT_RIGHT, + RSC_HELP_KEY_DOWN, + RSC_HELP_KEY_END, + RSC_HELP_KEY_HOME, + RSC_HELP_KEY_ENTER, + RSC_HELP_KEY_PAGE_UP, + RSC_HELP_KEY_PAGE_DOWN, + RSC_HELP_KEY_MINUS, + RSC_HELP_KEY_PLUS, + RSC_HELP_BLANK, + RSC_HELP_KEY_MENU, + RSC_HELP_MENU, + RSC_HELP_CLOSE_WINDOW, + RSC_HELP_PREV_WINDOW, + RSC_HELP_NEXT_WINDOW, + RSC_HELP_KEY_SHIFT_GR1, + RSC_HELP_KEY_SHIFT_GR2, + RSC_HELP_MOVE_WINDOW, + RSC_HELP_KEY_ALT_GR3, + RSC_HELP_SIZE_WINDOW, + RSC_HELP_MOVE_SELECT, + RSC_HELP_LAST_CELL, + RSC_HELP_FIRST_CELL, + RSC_HELP_TRIGGER_SELECT, + RSC_HELP_PREV_PAGE, + RSC_HELP_NEXT_PAGE, + RSC_HELP_SCROLL_DOWN, + RSC_HELP_SCROLL_UP, + RSC_ADV_HELP_TITLE, + RSC_ADV_HELP_SECT_FREQ, + RSC_ADV_HELP_ITEM_AVG, + RSC_ADV_HELP_SECT_TASK, + RSC_ADV_HELP_ITEM_ORDER, + RSC_ADV_HELP_ITEM_RST, + RSC_ADV_HELP_ITEM_SEL, + RSC_ADV_HELP_ITEM_REV, + RSC_ADV_HELP_ITEM_HIDE, + RSC_ADV_HELP_SECT_ANY, + RSC_ADV_HELP_ITEM_POWER, + RSC_ADV_HELP_ITEM_TOP, + RSC_ADV_HELP_ITEM_UPD, + RSC_ADV_HELP_ITEM_START, + RSC_ADV_HELP_ITEM_STOP, + RSC_ADV_HELP_ITEM_TOOLS, + RSC_ADV_HELP_ITEM_GO_UP, + RSC_ADV_HELP_ITEM_GO_DW, + RSC_ADV_HELP_ITEM_TERMINAL, + RSC_ADV_HELP_ITEM_PRT_SCR, + RSC_ADV_HELP_ITEM_REC_SCR, + RSC_ADV_HELP_ITEM_FAHR_CELS, + RSC_ADV_HELP_ITEM_SYSGATE, + RSC_ADV_HELP_ITEM_PROC_EVENT, + RSC_ADV_HELP_ITEM_SECRET, + RSC_TURBO_CLOCK_TITLE, + RSC_RATIO_CLOCK_TITLE, + RSC_UNCORE_CLOCK_TITLE, + RSC_SELECT_CPU_TITLE, + RSC_SELECT_FREQ_TITLE, + RSC_BOX_DISABLE_COND0, + RSC_BOX_DISABLE_COND1, + RSC_BOX_ENABLE_COND0, + RSC_BOX_ENABLE_COND1, + RSC_BOX_INTERVAL_TITLE, + RSC_BOX_INTERVAL_STEP1, + RSC_BOX_INTERVAL_STEP2, + RSC_BOX_INTERVAL_STEP3, + RSC_BOX_INTERVAL_STEP4, + RSC_BOX_INTERVAL_STEP5, + RSC_BOX_INTERVAL_STEP6, + RSC_BOX_INTERVAL_STEP7, + RSC_BOX_INTERVAL_STEP8, + RSC_BOX_INTERVAL_STEP9, + RSC_BOX_INTERVAL_STEP10, + RSC_BOX_AUTO_CLOCK_TITLE, + RSC_BOX_MODE_TITLE, + RSC_BOX_MODE_DESC, + RSC_BOX_CPPC_TITLE, + RSC_BOX_HWP_TITLE, + RSC_BOX_HWP_DESC, + RSC_BOX_FMW_DESC, + RSC_BOX_BLANK_DESC, + RSC_BOX_NOMINAL_MODE_COND0, + RSC_BOX_NOMINAL_MODE_COND1, + RSC_BOX_EXPERIMENT_MODE_COND0, + RSC_BOX_EXPERIMENT_MODE_COND1, + RSC_BOX_INTERRUPT_TITLE, + RSC_BOX_CPU_IDLE_TITLE, + RSC_BOX_CPU_FREQ_TITLE, + RSC_BOX_GOVERNOR_TITLE, + RSC_BOX_CLOCK_SOURCE_TITLE, + RSC_BOX_OPS_REGISTER_COND0, + RSC_BOX_OPS_REGISTER_COND1, + RSC_BOX_OPS_UNREGISTER_COND0, + RSC_BOX_OPS_UNREGISTER_COND1, + RSC_BOX_EVENT_TITLE, + RSC_BOX_EVENT_SPACE, + RSC_BOX_EVENT_THERMAL_SENSOR, + RSC_BOX_EVENT_PROCHOT_STS, + RSC_BOX_EVENT_CRITICAL_TEMP, + RSC_BOX_EVENT_THOLD1_STS, + RSC_BOX_EVENT_THOLD2_STS, + RSC_BOX_EVENT_POWER_LIMIT, + RSC_BOX_EVENT_CURRENT_LIMIT, + RSC_BOX_EVENT_CROSS_DOM_LIMIT, + RSC_BOX_EVENT_RESIDENCY, + RSC_BOX_EVENT_AVG_THERMAL, + RSC_BOX_EVENT_VR_THERMAL, + RSC_BOX_EVENT_VR_TDC, + RSC_BOX_EVENT_POWER_PL1, + RSC_BOX_EVENT_POWER_PL2, + RSC_BOX_EVENT_ELECTRICAL, + RSC_BOX_EVENT_INEFFICIENCY, + RSC_BOX_EVENT_MAX_TURBO, + RSC_BOX_EVENT_TURBO_ATTEN, + RSC_BOX_EVENT_THERMAL_TVB, + RSC_BOX_EVENT_ALL_OF_THEM, + RSC_BOX_POWER_POLICY_TITLE, + RSC_BOX_POWER_POLICY_LOW, + RSC_BOX_POWER_POLICY_HIGH, + RSC_BOX_HWP_POLICY_MIN, + RSC_BOX_HWP_POLICY_020, + RSC_BOX_HWP_POLICY_040, + RSC_BOX_HWP_POLICY_060, + RSC_BOX_HWP_POLICY_MED, + RSC_BOX_HWP_POLICY_0A0, + RSC_BOX_HWP_POLICY_PWR, + RSC_BOX_HWP_POLICY_0E0, + RSC_BOX_HWP_POLICY_MAX, + RSC_BOX_CFG_TDP_TITLE, + RSC_BOX_CFG_TDP_DESC, + RSC_BOX_CFG_TDP_BLANK, + RSC_BOX_CFG_TDP_LVL0, + RSC_BOX_CFG_TDP_LVL1, + RSC_BOX_CFG_TDP_LVL2, + RSC_BOX_TDP_PKG_TITLE, + RSC_BOX_TDP_CORES_TITLE, + RSC_BOX_TDP_UNCORE_TITLE, + RSC_BOX_TDP_RAM_TITLE, + RSC_BOX_TDP_PLATFORM_TITLE, + RSC_BOX_PL1_DESC, + RSC_BOX_PL2_DESC, + RSC_BOX_PWR_OFFSET_00, + RSC_BOX_PWR_OFFSET_01, + RSC_BOX_PWR_OFFSET_02, + RSC_BOX_PWR_OFFSET_03, + RSC_BOX_PWR_OFFSET_04, + RSC_BOX_PWR_OFFSET_05, + RSC_BOX_PWR_OFFSET_06, + RSC_BOX_PWR_OFFSET_07, + RSC_BOX_PWR_OFFSET_08, + RSC_BOX_PWR_OFFSET_09, + RSC_BOX_PWR_OFFSET_10, + RSC_BOX_PWR_OFFSET_11, + RSC_BOX_PWR_OFFSET_12, + RSC_BOX_PWR_OFFSET_13, + RSC_BOX_CLAMPING_OFF_COND0, + RSC_BOX_CLAMPING_OFF_COND1, + RSC_BOX_CLAMPING_ON_COND0, + RSC_BOX_CLAMPING_ON_COND1, + RSC_BOX_TDC_TITLE, + RSC_BOX_TDC_DESC, + RSC_BOX_AMP_OFFSET_00, + RSC_BOX_AMP_OFFSET_01, + RSC_BOX_AMP_OFFSET_02, + RSC_BOX_AMP_OFFSET_03, + RSC_BOX_AMP_OFFSET_04, + RSC_BOX_AMP_OFFSET_05, + RSC_BOX_AMP_OFFSET_06, + RSC_BOX_AMP_OFFSET_07, + RSC_BOX_AMP_OFFSET_08, + RSC_BOX_AMP_OFFSET_09, + RSC_BOX_AMP_OFFSET_10, + RSC_BOX_AMP_OFFSET_11, + RSC_BOX_AMP_OFFSET_12, + RSC_BOX_AMP_OFFSET_13, + RSC_BOX_TOOLS_TITLE, + RSC_BOX_TOOLS_STOP_BURN, + RSC_BOX_TOOLS_ATOMIC_BURN, + RSC_BOX_TOOLS_CRC32_BURN, + RSC_BOX_TOOLS_CONIC_BURN, + RSC_BOX_TOOLS_RANDOM_CPU, + RSC_BOX_TOOLS_ROUND_ROBIN_CPU, + RSC_BOX_TOOLS_USER_CPU, + RSC_BOX_TOOLS_MONTE_CARLO, + RSC_BOX_CONIC_TITLE, + RSC_BOX_CONIC_ITEM_1, + RSC_BOX_CONIC_ITEM_2, + RSC_BOX_CONIC_ITEM_3, + RSC_BOX_CONIC_ITEM_4, + RSC_BOX_CONIC_ITEM_5, + RSC_BOX_CONIC_ITEM_6, + RSC_BOX_LANG_TITLE, + RSC_BOX_LANG_ENGLISH, + RSC_BOX_LANG_FRENCH, + RSC_BOX_LANG_BLANK, + RSC_BOX_THEME_TITLE, + RSC_BOX_THEME_BLANK, + RSC_BOX_SCOPE_THERMAL_TITLE, + RSC_BOX_SCOPE_VOLTAGE_TITLE, + RSC_BOX_SCOPE_POWER_TITLE, + RSC_BOX_SCOPE_NONE, + RSC_BOX_SCOPE_THREAD, + RSC_BOX_SCOPE_CORE, + RSC_BOX_SCOPE_PACKAGE, + RSC_ERROR_CMD_SYNTAX, + RSC_ERROR_SHARED_MEM, + RSC_ERROR_SYS_CALL, + RSC_ERROR_UNIMPLEMENTED, + RSC_ERROR_EXPERIMENTAL, + RSC_ERROR_TURBO_PREREQ, + RSC_ERROR_UNCORE_PREREQ, + RSC_ERROR_PSTATE_NOT_FOUND, + RSC_ERROR_CLOCKSOURCE, + RSC_BOX_IDLE_LIMIT_TITLE, + RSC_BOX_IDLE_LIMIT_RESET, + RSC_BOX_RECORDER_TITLE, + RSC_SMBIOS_TITLE, + RSC_MECH_CLRBHB, + RSC_MECH_SSBD, + RSC_MECH_SSBS, + RSC_CF0, + RSC_CF1, + RSC_CF2, + RSC_CF3, + RSC_CF4, + RSC_CF5, + RSC_COPY0, + RSC_COPY1, + RSC_COPY2, + RSC_CREATE_SELECT_AUTO_TURBO, + RSC_CREATE_SELECT_FREQ_TURBO, + RSC_CREATE_SELECT_FREQ_TGT, + RSC_CREATE_SELECT_FREQ_HWP_TGT, + RSC_CREATE_SELECT_FREQ_HWP_MAX, + RSC_CREATE_SELECT_FREQ_HWP_MIN, + RSC_CREATE_SELECT_FREQ_MAX, + RSC_CREATE_SELECT_FREQ_MIN, + RSC_CREATE_SELECT_FREQ_OFFLINE, + RSC_POPUP_DRIVER_TITLE, + RSC_EXIT_TITLE, + RSC_EXIT_HEADER, + RSC_EXIT_CONFIRM, + RSC_EXIT_FOOTER +}; + +typedef struct { + ATTRIBUTE *Attr[THM_CNT]; + ASCII *Code[LOC_CNT]; + const int Size[LOC_CNT]; +} RESOURCE_ST; + +extern RESOURCE_ST Resource[]; + +#define ATTR() Attr[GET_THEME()] + +#define CODE() Code[GET_LOCALE()] + +#define RSC(_ID) (Resource[RSC_##_ID]) + +#define RSZ(_ID) (RSC(_ID).Size[GET_LOCALE()]) diff --git a/aarch64/corefreq-cli.c b/aarch64/corefreq-cli.c new file mode 100644 index 00000000..89ffda33 --- /dev/null +++ b/aarch64/corefreq-cli.c @@ -0,0 +1,17640 @@ +/* + * CoreFreq + * Copyright (C) 2015-2024 CYRIL COURTIAT + * Licenses: GPL2 + */ + +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "bitasm.h" +#include "coretypes.h" +#include "corefreq.h" +#include "corefreq-ui.h" +#include "corefreq-cli-rsc.h" +#include "corefreq-cli.h" +#include "corefreq-cli-json.h" +#include "corefreq-cli-extra.h" + +RO(SHM_STRUCT) *RO(Shm) = NULL; +RW(SHM_STRUCT) *RW(Shm) = NULL; + +static Bit64 Shutdown __attribute__ ((aligned (8))) = 0x0; + +SERVICE_PROC localService = RESET_SERVICE; + +UBENCH_DECLARE() + +struct SETTING_ST Setting = { + .fahrCels = 0, + .jouleWatt= 1, + .secret = 1, + ._padding = 0 +}; + +char ConfigFQN[1+4095] = {[0] = 0}; + +char *BuildConfigFQN(char *dirPath) +{ + if (ConfigFQN[0] == 0) + { + char *homePath, *dotted; + if ((homePath = secure_getenv("XDG_CONFIG_HOME")) == NULL) + { + struct stat cfgStat; + + if ((homePath = secure_getenv("HOME")) == NULL) { + struct passwd *pwd = getpwuid(getuid()); + if (pwd != NULL) { + homePath = pwd->pw_dir; + } else { + homePath = "."; + } + } + StrFormat(&ConfigFQN[1], 4095, "%s/.config", homePath); + + if ((stat(&ConfigFQN[1], &cfgStat) == 0) + && (cfgStat.st_mode & S_IFDIR)) + { + dotted = "/.config/"; + } else { + dotted = "/."; + } + } else { + dotted = "/"; + } + StrFormat(&ConfigFQN[1], 4095, "%s%s%s/corefreq.cfg", + homePath, dotted, dirPath); + + ConfigFQN[0] = 1; + } + return &ConfigFQN[1]; +} + +int ClientFollowService(SERVICE_PROC *pSlave, SERVICE_PROC *pMaster, pid_t pid) +{ + if (pSlave->Proc != pMaster->Proc) { + pSlave->Proc = pMaster->Proc; + + cpu_set_t cpuset; + CPU_ZERO(&cpuset); + CPU_SET(pSlave->Core, &cpuset); + if (pSlave->Thread != -1) { + const signed int cpu = pSlave->Thread; + CPU_SET(cpu , &cpuset); + } + return sched_setaffinity(pid, sizeof(cpu_set_t), &cpuset); + } + return 0; +} + +struct RULER_ST Ruler = { + .Count = 0 +}; + +#define GetTopOfRuler() (RO(Shm)->Cpu[Ruler.TopOf.Top].Boost[Ruler.TopOf.Boost]) + +#define SetTopOfRuler(_cpu, _boost) \ +( \ + Ruler.TopOf = (struct TOPOF) { .Top = _cpu , .Boost = _boost} \ +) + +void SetTopOftheTop( unsigned int cpu, enum RATIO_BOOST rb, + unsigned int *lowest, unsigned int *highest ) +{ + switch (rb) { + case BOOST(HWP_MIN): + case BOOST(MIN): + if(RO(Shm)->Cpu[cpu].Boost[rb] < RO(Shm)->Cpu[ Ruler.Top[rb] ].Boost[rb]) + { + Ruler.Top[rb] = cpu; + } + if (RO(Shm)->Cpu[cpu].Boost[rb] < (*lowest)) + { + (*lowest) = RO(Shm)->Cpu[cpu].Boost[rb]; + SetTopOfRuler(Ruler.Top[rb], rb); + } + break; + default: + if(RO(Shm)->Cpu[cpu].Boost[rb] > RO(Shm)->Cpu[ Ruler.Top[rb] ].Boost[rb]) + { + Ruler.Top[rb] = cpu; + } + if (RO(Shm)->Cpu[cpu].Boost[rb] > (*highest)) + { + (*highest) = RO(Shm)->Cpu[cpu].Boost[rb]; + SetTopOfRuler(Ruler.Top[rb], rb); + } + break; + } +} + +void InsertionSortRuler(unsigned int base[], + unsigned int cnt, + enum RATIO_BOOST start) +{ + __typeof__(start) lt = start + 1, rt; + while (lt < cnt) + { + rt = lt; + while ((rt > start) && (base[rt - 1] > base[rt])) + { + __typeof__(base[0]) swap = base[rt - 1]; + base[rt - 1] = base[rt]; + base[rt] = swap; + rt = rt - 1; + } + lt = lt + 1; + } +} + +void AggregateRatio(void) +{ + const size_t dimension = sizeof(Ruler.Uniq) / sizeof(Ruler.Uniq[0]); + const unsigned int highestFactory = MAXCLOCK_TO_RATIO( + unsigned int, RO(Shm)->Proc.Features.Factory.Clock.Hz + ); + enum RATIO_BOOST lt, rt, min_boost = BOOST(MIN); + if ((RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Boost[BOOST(HWP_MIN)] > 0) + && (RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Boost[BOOST(HWP_MIN)] + < RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Boost[BOOST(MIN)])) + { + min_boost = BOOST(HWP_MIN); + } + unsigned int cpu, + lowest = RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Boost[BOOST(MAX)], + highest = RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Boost[min_boost]; + + Ruler.Count = 0; + SetTopOfRuler(RO(Shm)->Proc.Service.Core, BOOST(MIN)); + + lt = BOOST(MIN); + while (lt < BOOST(SIZE)) + { + Ruler.Top[lt] = RO(Shm)->Proc.Service.Core; + + for (cpu = 0; + !BITVAL(RO(Shm)->Cpu[cpu].OffLine, OS) + && (cpu < RO(Shm)->Proc.CPU.Count) + && (Ruler.Count < dimension); + cpu++) + { + if ((RO(Shm)->Cpu[cpu].Boost[lt] > 0) + && (RO(Shm)->Cpu[cpu].Boost[lt] <= highestFactory) ) + { + SetTopOftheTop(cpu, lt, &lowest, &highest); + + for (rt = BOOST(MIN); rt < Ruler.Count; rt++) + { + if (Ruler.Uniq[rt] == RO(Shm)->Cpu[cpu].Boost[lt]) + { + break; + } + } + if (rt == Ruler.Count) { + Ruler.Uniq[Ruler.Count] = RO(Shm)->Cpu[cpu].Boost[lt]; + Ruler.Count++; + } + } + } + lt = lt + 1; + } + InsertionSortRuler(Ruler.Uniq, Ruler.Count, BOOST(MIN)); + + Ruler.Minimum = (double) lowest; + Ruler.Maximum = (double) highest; + Ruler.Median = (double) RO(Shm)->Cpu[ + Ruler.Top[BOOST(ACT)] + ].Boost[BOOST(ACT)]; + + if (Ruler.Median == 0.0) { + Ruler.Median = (Ruler.Minimum + Ruler.Maximum) / 2.0; + } +} + +#undef InsertionSort + +ATTRIBUTE *StateToSymbol(short int state, char stateStr[]) +{ + ATTRIBUTE *symbAttr[16] = { + /* R */ RSC(RUN_STATE_COLOR).ATTR(), + /* S */ RSC(SLEEP_STATE_COLOR).ATTR(), + /* D */ RSC(UNINT_STATE_COLOR).ATTR(), + /* T */ RSC(WAIT_STATE_COLOR).ATTR(), + /* t */ RSC(WAIT_STATE_COLOR).ATTR(), + /* X */ RSC(WAIT_STATE_COLOR).ATTR(), + /* Z */ RSC(ZOMBIE_STATE_COLOR).ATTR(), + /* P */ RSC(WAIT_STATE_COLOR).ATTR(), + /* I */ RSC(WAIT_STATE_COLOR).ATTR(), + /* K */ RSC(SLEEP_STATE_COLOR).ATTR(), + /* W */ RSC(RUN_STATE_COLOR).ATTR(), + /* i */ RSC(WAIT_STATE_COLOR).ATTR(), + /* N */ RSC(RUN_STATE_COLOR).ATTR(), + /* m */ RSC(OTHER_STATE_COLOR).ATTR(), /* Linux 5.15 */ + /* F */ RSC(UNINT_STATE_COLOR).ATTR(), /* Linux 6.1 */ + /* f */ RSC(UNINT_STATE_COLOR).ATTR() + }, *stateAttr = RSC(OTHER_STATE_COLOR).ATTR(); + const char symbol[16] = "RSDTtXZPIKWiNmFf"; + register unsigned short idx, jdx = 0; + + if (BITBSR(state, idx) == 1) { + stateStr[jdx++] = symbol[0]; + stateAttr = symbAttr[0]; + } else + do { + BITCLR(LOCKLESS, state, (unsigned int) idx); + if (idx < 15) { + const unsigned short bdx = 1 + idx; + stateStr[jdx++] = symbol[bdx]; + stateAttr = symbAttr[bdx]; + } else { + stateStr[jdx++] = '?'; + } + } while ((BITBSR(state, idx) == 0) && (jdx < TASK_COMM_LEN)); + stateStr[jdx] = '\0'; + return stateAttr; +} + +#define Dec2Digit(decimal, thisDigit) \ +({ \ + register __typeof__(decimal) dec = decimal; \ + register size_t j = sizeof(thisDigit) / sizeof(thisDigit[0]); \ + \ + while (j > 0 && dec > 0) { \ + thisDigit[--j] = dec % 10; \ + dec /= 10; \ + } \ + while (j > 0) { \ + thisDigit[--j] = 0; \ + } \ +}) + +#define Cels2Fahr(cels) (((cels * 117965) >> 16) + 32) + +const char *Indent[2][4] = { + {"", "|", "|- ", " |- "}, + {"", " ", " ", " "} +}; + +TGrid *Print_v1(CELL_FUNC OutFunc, + Window *win, + unsigned long long key, + unsigned int *cellPadding, + ATTRIBUTE *attrib, + CUINT width, + int tab, + char *fmt, ...) +{ + TGrid *pGrid = NULL; + char *line = malloc(width + 1); + if (line != NULL) + { + va_list ap; + va_start(ap, fmt); + if (vsnprintf(line, width + 1, fmt, ap) < 0) { + goto EXIT_v1; + } + if (OutFunc == NULL) { + printf("%s%s%.*s\n", Indent[0][tab], line, + (int)(width - strlen(line) - strlen(Indent[0][tab])), hSpace); + } else { + ASCII *item = malloc(width + 1); + if (item != NULL) { + if (0 < StrFormat(item, width + 1, "%s%s%.*s", Indent[1][tab], line, + (int)(width - strlen(line) - strlen(Indent[1][tab])), hSpace)) + { + pGrid = OutFunc(win, key, attrib, item, cellPadding); + } + free(item); + } + } +EXIT_v1: + va_end(ap); + free(line); + } + return pGrid; +} + +TGrid *Print_v2(CELL_FUNC OutFunc, + Window *win, + CUINT *nl, + unsigned int *cellPadding, + ATTRIBUTE *attrib, ...) +{ + TGrid *pGrid = NULL; + ASCII *item = malloc(MIN_WIDTH); + if (item != NULL) + { + char *fmt; + va_list ap; + va_start(ap, attrib); + if ((fmt = va_arg(ap, char*)) != NULL) + { + if (vsnprintf((char*) item, MIN_WIDTH, fmt, ap) < 0) { + goto EXIT_v2; + } + if (OutFunc == NULL) { + (*nl)--; + if ((*nl) == 0) { + (*nl) = win->matrix.size.wth; + printf("%s\n", item); + } else + printf("%s", item); + } else { + pGrid = OutFunc(win, SCANKEY_NULL, attrib, item, cellPadding); + } + } +EXIT_v2: + va_end(ap); + free(item); + } + return pGrid; +} + +TGrid *Print_v3(CELL_FUNC OutFunc, + Window *win, + CUINT *nl, + unsigned int *cellPadding, + ATTRIBUTE *attrib, ...) +{ + TGrid *pGrid = NULL; + ASCII *item = malloc(MIN_WIDTH); + if (item != NULL) + { + char *fmt; + va_list ap; + va_start(ap, attrib); + if ((fmt = va_arg(ap, char*)) != NULL) + { + if (!(vsnprintf((char*) item, MIN_WIDTH, fmt, ap) < 0)) + { + if (OutFunc == NULL) { + (*nl)--; + if ((*nl) == (win->matrix.size.wth - 1)) { + printf("|-%s", item); + } else if ((*nl) == 0) { + (*nl) = win->matrix.size.wth; + printf("%s\n", item); + } else { + printf("%s", item); + } + } else { + pGrid = OutFunc(win, SCANKEY_NULL, attrib, item, cellPadding); + } + } + } + va_end(ap); + free(item); + } + return pGrid; +} + +#define PUT(key, attrib, width, tab, fmt, ...) \ + Print_v1(OutFunc, win, key, cellPadding, attrib, width, tab, fmt, __VA_ARGS__) + +#define Print_REG Print_v2 +#define Print_MAP Print_v2 +#define Print_IMC Print_v2 +#define Print_ISA Print_v3 + +#define PRT(FUN, attrib, ...) \ + Print_##FUN(OutFunc, win, nl, cellPadding, attrib, __VA_ARGS__) + +REASON_CODE SystemRegisters( Window *win, + CELL_FUNC OutFunc, + unsigned int *cellPadding ) +{ + REASON_INIT(reason); + ATTRIBUTE *attrib[5] = { + RSC(SYSTEM_REGISTERS_COND0).ATTR(), + RSC(SYSTEM_REGISTERS_COND1).ATTR(), + RSC(SYSTEM_REGISTERS_COND2).ATTR(), + RSC(SYSTEM_REGISTERS_COND3).ATTR(), + RSC(SYSTEM_REGISTERS_COND4).ATTR() + }; + enum AUTOMAT { + DO_END, DO_SPC, DO_CPU, DO_FLAG, + DO_SCTLR, DO_SCTLR2, DO_EL, DO_FPSR + }; + const struct SR_ST { + struct SR_HDR { + const ASCII *flag, + *comm; + } *header; + struct SR_BIT { + enum AUTOMAT automat; + unsigned int capable; + enum SYS_REG pos; + unsigned int len; + } *flag; + } SR[] = \ + { + { + .header = (struct SR_HDR[]) { + [ 0]={&RSC(SYS_REG_HDR_FLAGS).CODE()[ 0],RSC(SYS_REG_PSTATE).CODE()}, + [ 1]={&RSC(SYS_REG_HDR_FLAGS).CODE()[ 5],RSC(SYS_REG_FLAG_PM).CODE()}, + [ 2]={&RSC(SYS_REG_HDR_FLAGS).CODE()[10],RSC(SYS_REG_FLAG_N).CODE()}, + [ 3]={&RSC(SYS_REG_HDR_FLAGS).CODE()[15],RSC(SYS_REG_FLAG_Z).CODE()}, + [ 4]={&RSC(SYS_REG_HDR_FLAGS).CODE()[20],RSC(SYS_REG_FLAG_C).CODE()}, + [ 5]={&RSC(SYS_REG_HDR_FLAGS).CODE()[25],RSC(SYS_REG_FLAG_V).CODE()}, + [ 6]={&RSC(SYS_REG_HDR_FLAGS).CODE()[30],RSC(SYS_REG_FLAG_TCO).CODE()}, + [ 7]={&RSC(SYS_REG_HDR_FLAGS).CODE()[35],RSC(SYS_REG_FLAG_DIT).CODE()}, + [ 8]={&RSC(SYS_REG_HDR_FLAGS).CODE()[40],RSC(SYS_REG_FLAG_UAO).CODE()}, + [ 9]={&RSC(SYS_REG_HDR_FLAGS).CODE()[45],RSC(SYS_REG_FLAG_PAN).CODE()}, + [10]={&RSC(SYS_REG_HDR_FLAGS).CODE()[50],RSC(SYS_REG_FLAG_NMI).CODE()}, + [11]={&RSC(SYS_REG_HDR_FLAGS).CODE()[55],RSC(SYS_REG_FLAG_SSBS).CODE()}, + [12]={&RSC(SYS_REG_HDR_FLAGS).CODE()[60],RSC(SYS_REG_FLAG_D).CODE()}, + [13]={&RSC(SYS_REG_HDR_FLAGS).CODE()[65],RSC(SYS_REG_FLAG_A).CODE()}, + [14]={&RSC(SYS_REG_HDR_FLAGS).CODE()[70],RSC(SYS_REG_FLAG_I).CODE()}, + [15]={&RSC(SYS_REG_HDR_FLAGS).CODE()[75],RSC(SYS_REG_FLAG_F).CODE()}, + [16]={&RSC(SYS_REG_HDR_FLAGS).CODE()[80],RSC(SYS_REG_FLAG_EL).CODE()}, + {NULL, NULL} + }, + .flag = (struct SR_BIT[]) { + [ 0] = {DO_CPU , 1 , UNDEF_CR , 0 }, + [ 1] = {DO_FLAG, RO(Shm)->Proc.Features.EBEP, FLAG_PM, 1}, + [ 2] = {DO_FLAG, 1 , FLAG_N , 1 }, + [ 3] = {DO_FLAG, 1 , FLAG_Z , 1 }, + [ 4] = {DO_FLAG, 1 , FLAG_C , 1 }, + [ 5] = {DO_FLAG, 1 , FLAG_V , 1 }, + [ 6] = {DO_FLAG, RO(Shm)->Proc.Features.MTE, FLAG_TCO, 1}, + [ 7] = {DO_FLAG, RO(Shm)->Proc.Features.DIT, FLAG_DIT, 1}, + [ 8] = {DO_FLAG, RO(Shm)->Proc.Features.UAO, FLAG_UAO, 1}, + [ 9] = {DO_FLAG, RO(Shm)->Proc.Features.PAN, FLAG_PAN, 1}, + [10] = {DO_FLAG, RO(Shm)->Proc.Features.NMI, FLAG_NMI, 1}, + [11] = {DO_FLAG, RO(Shm)->Proc.Features.SSBS == 0b0010, FLAG_SSBS, 1}, + [12] = {DO_FLAG, 1 , FLAG_D , 1 }, + [13] = {DO_FLAG, 1 , FLAG_A , 1 }, + [14] = {DO_FLAG, 1 , FLAG_I , 1 }, + [15] = {DO_FLAG, 1 , FLAG_F , 1 }, + [16] = {DO_FLAG, 1 , FLAG_EL , 2 }, + {DO_END , 1 , UNDEF_CR , 0 } + } + }, + { + .header = (struct SR_HDR[]) { + [ 0] = {&RSC(SYS_REG_HDR11_SCTL).CODE()[ 0], NULL}, + [ 1] = {&RSC(SYS_REG_HDR11_SCTL).CODE()[ 5], RSC(SYS_REG_TIDCP).CODE()}, + [ 2] = {&RSC(SYS_REG_HDR11_SCTL).CODE()[10], RSC(SYS_REG_SPINT).CODE()}, + [ 3] = {&RSC(SYS_REG_HDR11_SCTL).CODE()[15], RSC(SYS_REG_NMI).CODE()}, + [ 4] = {&RSC(SYS_REG_HDR11_SCTL).CODE()[20], RSC(SYS_REG_EnTP2).CODE()}, + [ 5] = {&RSC(SYS_REG_HDR11_SCTL).CODE()[25], RSC(SYS_REG_TCSO).CODE()}, + [ 6] = {&RSC(SYS_REG_HDR11_SCTL).CODE()[30], RSC(SYS_REG_TCSO).CODE()}, + [ 7] = {&RSC(SYS_REG_HDR11_SCTL).CODE()[35], RSC(SYS_REG_EPAN).CODE()}, + [ 8] = {&RSC(SYS_REG_HDR11_SCTL).CODE()[40], RSC(SYS_REG_EnALS).CODE()}, + [ 9] = {&RSC(SYS_REG_HDR11_SCTL).CODE()[45], RSC(SYS_REG_EnAS0).CODE()}, + [10] = {&RSC(SYS_REG_HDR11_SCTL).CODE()[50], RSC(SYS_REG_EnASR).CODE()}, + [11] = {&RSC(SYS_REG_HDR11_SCTL).CODE()[55], RSC(SYS_REG_TME).CODE()}, + [12] = {&RSC(SYS_REG_HDR11_SCTL).CODE()[60], RSC(SYS_REG_TME).CODE()}, + [13] = {&RSC(SYS_REG_HDR11_SCTL).CODE()[65], RSC(SYS_REG_TMT).CODE()}, + [14] = {&RSC(SYS_REG_HDR11_SCTL).CODE()[70], RSC(SYS_REG_TMT).CODE()}, + [15] = {&RSC(SYS_REG_HDR11_SCTL).CODE()[75], RSC(SYS_REG_TWE_D).CODE()}, + [16] = {&RSC(SYS_REG_HDR11_SCTL).CODE()[80], RSC(SYS_REG_TWE_D).CODE()}, + + [17] = {&RSC(SYS_REG_HDR12_SCTL).CODE()[ 0], RSC(SYS_REG_SCTL).CODE()}, + [18] = {&RSC(SYS_REG_HDR12_SCTL).CODE()[ 5], RSC(SYS_REG_TIDCP).CODE()}, + [19] = {&RSC(SYS_REG_HDR12_SCTL).CODE()[10], RSC(SYS_REG_SPINT).CODE()}, + [20] = {&RSC(SYS_REG_HDR12_SCTL).CODE()[15], RSC(SYS_REG_NMI).CODE()}, + [21] = {&RSC(SYS_REG_HDR12_SCTL).CODE()[20], RSC(SYS_REG_EnTP2).CODE()}, + [22] = {&RSC(SYS_REG_HDR12_SCTL).CODE()[25], RSC(SYS_REG_TCSO1).CODE()}, + [23] = {&RSC(SYS_REG_HDR12_SCTL).CODE()[30], RSC(SYS_REG_TCSO0).CODE()}, + [24] = {&RSC(SYS_REG_HDR12_SCTL).CODE()[35], RSC(SYS_REG_EPAN).CODE()}, + [25] = {&RSC(SYS_REG_HDR12_SCTL).CODE()[40], RSC(SYS_REG_EnALS).CODE()}, + [26] = {&RSC(SYS_REG_HDR12_SCTL).CODE()[45], RSC(SYS_REG_EnAS0).CODE()}, + [27] = {&RSC(SYS_REG_HDR12_SCTL).CODE()[50], RSC(SYS_REG_EnASR).CODE()}, + [28] = {&RSC(SYS_REG_HDR12_SCTL).CODE()[55], RSC(SYS_REG_TME1).CODE()}, + [29] = {&RSC(SYS_REG_HDR12_SCTL).CODE()[60], RSC(SYS_REG_TME0).CODE()}, + [30] = {&RSC(SYS_REG_HDR12_SCTL).CODE()[65], RSC(SYS_REG_TMT1).CODE()}, + [31] = {&RSC(SYS_REG_HDR12_SCTL).CODE()[70], RSC(SYS_REG_TMT0).CODE()}, + [32] = {&RSC(SYS_REG_HDR12_SCTL).CODE()[75], RSC(SYS_REG_TWE_C).CODE()}, + [33] = {&RSC(SYS_REG_HDR12_SCTL).CODE()[80], RSC(SYS_REG_TWE_E).CODE()}, + {NULL, NULL} + }, + .flag = (struct SR_BIT[]) { + [ 0] = {DO_CPU , 1 , UNDEF_CR , 0 }, + [ 1] = {DO_SCTLR,1 , SCTLR_TIDCP , 1 }, + [ 2] = {DO_SCTLR,1 , SCTLR_SPINT , 1 }, + [ 3] = {DO_SCTLR,1 , SCTLR_NMI , 1 }, + [ 4] = {DO_SCTLR,1 , SCTLR_EnTP2 , 1 }, + [ 5] = {DO_SCTLR,1 , SCTLR_TCSO1 , 1 }, + [ 6] = {DO_SCTLR,1 , SCTLR_TCSO0 , 1 }, + [ 7] = {DO_SCTLR,1 , SCTLR_EPAN , 1 }, + [ 8] = {DO_SCTLR,1 , SCTLR_EnALS , 1 }, + [ 9] = {DO_SCTLR,1 , SCTLR_EnAS0 , 1 }, + [10] = {DO_SCTLR,1 , SCTLR_EnASR , 1 }, + [11] = {DO_SCTLR,1 , SCTLR_TME1 , 1 }, + [12] = {DO_SCTLR,1 , SCTLR_TME0 , 1 }, + [13] = {DO_SCTLR,1 , SCTLR_TMT1 , 1 }, + [14] = {DO_SCTLR,1 , SCTLR_TMT0 , 1 }, + [15] = {DO_SCTLR,1 , SCTLR_TWEDEL , 4 }, + [16] = {DO_SCTLR,1 , SCTLR_TWEDEn , 1 }, + {DO_END , 1 , UNDEF_CR , 0 } + } + }, + { + .header = (struct SR_HDR[]) { + [ 0] = {&RSC(SYS_REG_HDR21_SCTL).CODE()[ 0], NULL}, + [ 1] = {&RSC(SYS_REG_HDR21_SCTL).CODE()[ 5], RSC(SYS_REG_DSSBS).CODE()}, + [ 2] = {&RSC(SYS_REG_HDR21_SCTL).CODE()[10], RSC(SYS_REG_ATA).CODE()}, + [ 3] = {&RSC(SYS_REG_HDR21_SCTL).CODE()[15], RSC(SYS_REG_ATA).CODE()}, + [ 4] = {&RSC(SYS_REG_HDR21_SCTL).CODE()[20], RSC(SYS_REG_TCF).CODE()}, + [ 5] = {&RSC(SYS_REG_HDR21_SCTL).CODE()[25], RSC(SYS_REG_TCF).CODE()}, + [ 6] = {&RSC(SYS_REG_HDR21_SCTL).CODE()[30], RSC(SYS_REG_ITFSB).CODE()}, + [ 7] = {&RSC(SYS_REG_HDR21_SCTL).CODE()[35], RSC(SYS_REG_BT).CODE()}, + [ 8] = {&RSC(SYS_REG_HDR21_SCTL).CODE()[40], RSC(SYS_REG_BT).CODE()}, + [ 9] = {&RSC(SYS_REG_HDR21_SCTL).CODE()[45], RSC(SYS_REG_EnFPM).CODE()}, + [10] = {&RSC(SYS_REG_HDR21_SCTL).CODE()[50], RSC(SYS_REG_MSCEn).CODE()}, + [11] = {&RSC(SYS_REG_HDR21_SCTL).CODE()[55], RSC(SYS_REG_CMOW).CODE()}, + [12] = {&RSC(SYS_REG_HDR21_SCTL).CODE()[60], RSC(SYS_REG_EnIA).CODE()}, + [13] = {&RSC(SYS_REG_HDR21_SCTL).CODE()[65], RSC(SYS_REG_EnIB).CODE()}, + [14] = {&RSC(SYS_REG_HDR21_SCTL).CODE()[70], RSC(SYS_REG_LSM).CODE()}, + [15] = {&RSC(SYS_REG_HDR21_SCTL).CODE()[75], RSC(SYS_REG_LSM).CODE()}, + [16] = {&RSC(SYS_REG_HDR21_SCTL).CODE()[80], RSC(SYS_REG_EnDA).CODE()}, + + [17] = {&RSC(SYS_REG_HDR22_SCTL).CODE()[ 0], RSC(SYS_REG_SCTL).CODE()}, + [18] = {&RSC(SYS_REG_HDR22_SCTL).CODE()[ 5], RSC(SYS_REG_DSSBS).CODE()}, + [19] = {&RSC(SYS_REG_HDR22_SCTL).CODE()[10], RSC(SYS_REG_ATA1).CODE()}, + [20] = {&RSC(SYS_REG_HDR22_SCTL).CODE()[15], RSC(SYS_REG_ATA0).CODE()}, + [21] = {&RSC(SYS_REG_HDR22_SCTL).CODE()[20], RSC(SYS_REG_TCF1).CODE()}, + [22] = {&RSC(SYS_REG_HDR22_SCTL).CODE()[25], RSC(SYS_REG_TCF0).CODE()}, + [23] = {&RSC(SYS_REG_HDR22_SCTL).CODE()[30], RSC(SYS_REG_ITFSB).CODE()}, + [24] = {&RSC(SYS_REG_HDR22_SCTL).CODE()[35], RSC(SYS_REG_BT1).CODE()}, + [25] = {&RSC(SYS_REG_HDR22_SCTL).CODE()[40], RSC(SYS_REG_BT0).CODE()}, + [26] = {&RSC(SYS_REG_HDR22_SCTL).CODE()[45], RSC(SYS_REG_EnFPM).CODE()}, + [27] = {&RSC(SYS_REG_HDR22_SCTL).CODE()[50], RSC(SYS_REG_MSCEn).CODE()}, + [28] = {&RSC(SYS_REG_HDR22_SCTL).CODE()[55], RSC(SYS_REG_CMOW).CODE()}, + [29] = {&RSC(SYS_REG_HDR22_SCTL).CODE()[60], RSC(SYS_REG_EnIA).CODE()}, + [30] = {&RSC(SYS_REG_HDR22_SCTL).CODE()[65], RSC(SYS_REG_EnIB).CODE()}, + [31] = {&RSC(SYS_REG_HDR22_SCTL).CODE()[70], RSC(SYS_REG_LSMA).CODE()}, + [32] = {&RSC(SYS_REG_HDR22_SCTL).CODE()[75], RSC(SYS_REG_LSMD).CODE()}, + [33] = {&RSC(SYS_REG_HDR22_SCTL).CODE()[80], RSC(SYS_REG_EnDA).CODE()}, + {NULL, NULL} + }, + .flag = (struct SR_BIT[]) { + [ 0] = {DO_CPU , 1 , UNDEF_CR , 0 }, + [ 1] = {DO_SCTLR,1 , SCTLR_DSSBS , 1 }, + [ 2] = {DO_SCTLR,1 , SCTLR_ATA1 , 1 }, + [ 3] = {DO_SCTLR,1 , SCTLR_ATA0 , 1 }, + [ 4] = {DO_SCTLR,1 , SCTLR_TCF1 , 2 }, + [ 5] = {DO_SCTLR,1 , SCTLR_TCF0 , 2 }, + [ 6] = {DO_SCTLR,1 , SCTLR_ITFSB , 1 }, + [ 7] = {DO_SCTLR,1 , SCTLR_BT1 , 1 }, + [ 8] = {DO_SCTLR,1 , SCTLR_BT0 , 1 }, + [ 9] = {DO_SCTLR,1 , SCTLR_EnFPM , 1 }, + [10] = {DO_SCTLR,1 , SCTLR_MSCEn , 1 }, + [11] = {DO_SCTLR,1 , SCTLR_CMOW , 1 }, + [12] = {DO_SCTLR,1 , SCTLR_EnIA , 1 }, + [13] = {DO_SCTLR,1 , SCTLR_EnIB , 1 }, + [14] = {DO_SCTLR,1 , SCTLR_LSMAOE , 1 }, + [15] = {DO_SCTLR,1 , SCTLR_nTLSMD , 1 }, + [16] = {DO_SCTLR,1 , SCTLR_EnDA , 1 }, + {DO_END , 1 , UNDEF_CR , 0 } + } + }, + { + .header = (struct SR_HDR[]) { + [ 0] = {&RSC(SYS_REG_HDR31_SCTL).CODE()[ 0], RSC(SYS_REG_SCTL).CODE()}, + [ 1] = {&RSC(SYS_REG_HDR31_SCTL).CODE()[ 5], RSC(SYS_REG_UCI).CODE()}, + [ 2] = {&RSC(SYS_REG_HDR31_SCTL).CODE()[10], RSC(SYS_REG_EE).CODE()}, + [ 3] = {&RSC(SYS_REG_HDR31_SCTL).CODE()[15], RSC(SYS_REG_E0E).CODE()}, + [ 4] = {&RSC(SYS_REG_HDR31_SCTL).CODE()[20], RSC(SYS_REG_SPAN).CODE()}, + [ 5] = {&RSC(SYS_REG_HDR31_SCTL).CODE()[25], RSC(SYS_REG_EIS).CODE()}, + [ 6] = {&RSC(SYS_REG_HDR31_SCTL).CODE()[30], RSC(SYS_REG_IESB).CODE()}, + [ 7] = {&RSC(SYS_REG_HDR31_SCTL).CODE()[35], RSC(SYS_REG_TSCXT).CODE()}, + [ 8] = {&RSC(SYS_REG_HDR31_SCTL).CODE()[40], RSC(SYS_REG_WXN).CODE()}, + [ 9] = {&RSC(SYS_REG_HDR31_SCTL).CODE()[45], RSC(SYS_REG_nTWE).CODE()}, + [10] = {&RSC(SYS_REG_HDR31_SCTL).CODE()[50], RSC(SYS_REG_nTWI).CODE()}, + [11] = {&RSC(SYS_REG_HDR31_SCTL).CODE()[55], RSC(SYS_REG_UCT).CODE()}, + [12] = {&RSC(SYS_REG_HDR31_SCTL).CODE()[60], RSC(SYS_REG_DZE).CODE()}, + [13] = {&RSC(SYS_REG_HDR31_SCTL).CODE()[65], RSC(SYS_REG_EnDB).CODE()}, + [14] = {&RSC(SYS_REG_HDR31_SCTL).CODE()[70], RSC(SYS_REG_I).CODE()}, + [15] = {&RSC(SYS_REG_HDR31_SCTL).CODE()[75], RSC(SYS_REG_EOS).CODE()}, + [16] = {&RSC(SYS_REG_HDR31_SCTL).CODE()[80], RSC(SYS_REG_RCTX).CODE()}, + {NULL, NULL} + }, + .flag = (struct SR_BIT[]) { + [ 0] = {DO_CPU , 1 , UNDEF_CR , 0 }, + [ 1] = {DO_SCTLR,1 , SCTLR_UCI , 1 }, + [ 2] = {DO_SCTLR,1 , SCTLR_EE , 1 }, + [ 3] = {DO_SCTLR,1 , SCTLR_E0E , 1 }, + [ 4] = {DO_SCTLR,1 , SCTLR_SPAN , 1 }, + [ 5] = {DO_SCTLR,1 , SCTLR_EIS , 1 }, + [ 6] = {DO_SCTLR,1 , SCTLR_IESB , 1 }, + [ 7] = {DO_SCTLR,1 , SCTLR_TSCXT , 1 }, + [ 8] = {DO_SCTLR,1 , SCTLR_WXN , 1 }, + [ 9] = {DO_SCTLR,1 , SCTLR_nTWE , 1 }, + [10] = {DO_SCTLR,1 , SCTLR_nTWI , 1 }, + [11] = {DO_SCTLR,1 , SCTLR_UCT , 1 }, + [12] = {DO_SCTLR,1 , SCTLR_DZE , 1 }, + [13] = {DO_SCTLR,1 , SCTLR_EnDB , 1 }, + [14] = {DO_SCTLR,1 , SCTLR_I , 1 }, + [15] = {DO_SCTLR,1 , SCTLR_EOS , 1 }, + [16] = {DO_SCTLR,1 , SCTLR_EnRCTX , 1 }, + {DO_END , 1 , UNDEF_CR , 0 } + } + }, + { + .header = (struct SR_HDR[]) { + [ 0] = {&RSC(SYS_REG_HDR41_SCTL).CODE()[ 0], RSC(SYS_REG_SCTL).CODE()}, + [ 1] = {&RSC(SYS_REG_HDR41_SCTL).CODE()[ 5], RSC(SYS_REG_UMA).CODE()}, + [ 2] = {&RSC(SYS_REG_HDR41_SCTL).CODE()[10], RSC(SYS_REG_SED).CODE()}, + [ 3] = {&RSC(SYS_REG_HDR41_SCTL).CODE()[15], RSC(SYS_REG_ITD).CODE()}, + [ 4] = {&RSC(SYS_REG_HDR41_SCTL).CODE()[20], RSC(SYS_REG_nAA).CODE()}, + [ 5] = {&RSC(SYS_REG_HDR41_SCTL).CODE()[25], RSC(SYS_REG_CP15B).CODE()}, + [ 6] = {&RSC(SYS_REG_HDR41_SCTL).CODE()[30], RSC(SYS_REG_SA0).CODE()}, + [ 7] = {&RSC(SYS_REG_HDR41_SCTL).CODE()[35], RSC(SYS_REG_SA1).CODE()}, + [ 8] = {&RSC(SYS_REG_HDR41_SCTL).CODE()[40], RSC(SYS_REG_C).CODE()}, + [ 9] = {&RSC(SYS_REG_HDR41_SCTL).CODE()[45], RSC(SYS_REG_A).CODE()}, + [10] = {&RSC(SYS_REG_HDR41_SCTL).CODE()[50], RSC(SYS_REG_M).CODE()}, + [11] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + [12] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + [13] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + [14] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + [15] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + [16] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + {NULL, NULL} + }, + .flag = (struct SR_BIT[]) { + [ 0] = {DO_CPU , 1 , UNDEF_CR , 0 }, + [ 1] = {DO_SCTLR,1 , SCTLR_UMA , 1 }, + [ 2] = {DO_SCTLR,1 , SCTLR_SED , 1 }, + [ 3] = {DO_SCTLR,1 , SCTLR_ITD , 1 }, + [ 4] = {DO_SCTLR,1 , SCTLR_nAA , 1 }, + [ 5] = {DO_SCTLR,1 , SCTLR_CP15B , 1 }, + [ 6] = {DO_SCTLR,1 , SCTLR_SA0 , 1 }, + [ 7] = {DO_SCTLR,1 , SCTLR_SA1 , 1 }, + [ 8] = {DO_SCTLR,1 , SCTLR_C , 1 }, + [ 9] = {DO_SCTLR,1 , SCTLR_A , 1 }, + [10] = {DO_SCTLR,1 , SCTLR_M , 1 }, + [11] = {DO_SPC , 1 , UNDEF_CR , 0 }, + [12] = {DO_SPC , 1 , UNDEF_CR , 0 }, + [13] = {DO_SPC , 1 , UNDEF_CR , 0 }, + [14] = {DO_SPC , 1 , UNDEF_CR , 0 }, + [15] = {DO_SPC , 1 , UNDEF_CR , 0 }, + [16] = {DO_SPC , 1 , UNDEF_CR , 0 }, + {DO_END , 1 , UNDEF_CR , 0 } + } + }, + { + .header = (struct SR_HDR[]) { + [ 0] = {&RSC(SYS_REG_HDR11_SCTL2).CODE()[ 0],NULL}, + [ 1] = {&RSC(SYS_REG_HDR11_SCTL2).CODE()[ 5],RSC(SYS_REG_CPTM).CODE()}, + [ 2] = {&RSC(SYS_REG_HDR11_SCTL2).CODE()[10],RSC(SYS_REG_CPTM).CODE()}, + [ 3] = {&RSC(SYS_REG_HDR11_SCTL2).CODE()[15],RSC(SYS_REG_CPTA).CODE()}, + [ 4] = {&RSC(SYS_REG_HDR11_SCTL2).CODE()[20],RSC(SYS_REG_CPTA).CODE()}, + [ 5] = {&RSC(SYS_REG_HDR11_SCTL2).CODE()[25],RSC(SYS_REG_PACM).CODE()}, + [ 6] = {&RSC(SYS_REG_HDR11_SCTL2).CODE()[30],RSC(SYS_REG_PACM).CODE()}, + [ 7] = {&RSC(SYS_REG_HDR11_SCTL2).CODE()[35],RSC(SYS_REG_128SR).CODE()}, + [ 8] = {&RSC(SYS_REG_HDR11_SCTL2).CODE()[40],RSC(SYS_REG_EASE).CODE()}, + [ 9] = {&RSC(SYS_REG_HDR11_SCTL2).CODE()[45],RSC(SYS_REG_ANERR).CODE()}, + [10] = {&RSC(SYS_REG_HDR11_SCTL2).CODE()[50],RSC(SYS_REG_ADERR).CODE()}, + [11] = {&RSC(SYS_REG_HDR11_SCTL2).CODE()[55],RSC(SYS_REG_NMEA).CODE()}, + [12] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + [13] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + [14] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + [15] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + [16] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + + [17] = {&RSC(SYS_REG_HDR12_SCTL2).CODE()[ 0],RSC(SYS_REG_SCTL2).CODE()}, + [18] = {&RSC(SYS_REG_HDR12_SCTL2).CODE()[ 5],RSC(SYS_REG_CPTM0).CODE()}, + [19] = {&RSC(SYS_REG_HDR12_SCTL2).CODE()[10],RSC(SYS_REG_CPTM1).CODE()}, + [20] = {&RSC(SYS_REG_HDR12_SCTL2).CODE()[15],RSC(SYS_REG_CPTA0).CODE()}, + [21] = {&RSC(SYS_REG_HDR12_SCTL2).CODE()[20],RSC(SYS_REG_CPTA1).CODE()}, + [22] = {&RSC(SYS_REG_HDR12_SCTL2).CODE()[25],RSC(SYS_REG_PACM0).CODE()}, + [23] = {&RSC(SYS_REG_HDR12_SCTL2).CODE()[30],RSC(SYS_REG_PACM1).CODE()}, + [24] = {&RSC(SYS_REG_HDR12_SCTL2).CODE()[35],RSC(SYS_REG_128SR).CODE()}, + [25] = {&RSC(SYS_REG_HDR12_SCTL2).CODE()[40],RSC(SYS_REG_EASE).CODE()}, + [26] = {&RSC(SYS_REG_HDR12_SCTL2).CODE()[45],RSC(SYS_REG_ANERR).CODE()}, + [27] = {&RSC(SYS_REG_HDR12_SCTL2).CODE()[50],RSC(SYS_REG_ADERR).CODE()}, + [28] = {&RSC(SYS_REG_HDR12_SCTL2).CODE()[55],RSC(SYS_REG_NMEA).CODE()}, + [29] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + [30] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + [31] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + [32] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + [33] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + {NULL, NULL} + }, + .flag = (struct SR_BIT[]) { + [ 0] = {DO_CPU , 1 , UNDEF_CR , 0 }, + [ 1] = {DO_SCTLR2,1 , SCTLR2_CPTM0 , 1 }, + [ 2] = {DO_SCTLR2,1 , SCTLR2_CPTM1 , 1 }, + [ 3] = {DO_SCTLR2,1 , SCTLR2_CPTA0 , 1 }, + [ 4] = {DO_SCTLR2,1 , SCTLR2_CPTA1 , 1 }, + [ 5] = {DO_SCTLR2,1 , SCTLR2_EnPACM0, 1 }, + [ 6] = {DO_SCTLR2,1 , SCTLR2_EnPACM1, 1 }, + [ 7] = {DO_SCTLR2,1 , SCTLR2_IDCP128, 1 }, + [ 8] = {DO_SCTLR2,1 , SCTLR2_EASE , 1 }, + [ 9] = {DO_SCTLR2,1 , SCTLR2_EnANERR, 1 }, + [10] = {DO_SCTLR2,1 , SCTLR2_EnADERR, 1 }, + [11] = {DO_SCTLR2,1 , SCTLR2_NMEA , 1 }, + [12] = {DO_SPC , 1 , UNDEF_CR , 0 }, + [13] = {DO_SPC , 1 , UNDEF_CR , 0 }, + [14] = {DO_SPC , 1 , UNDEF_CR , 0 }, + [15] = {DO_SPC , 1 , UNDEF_CR , 0 }, + [16] = {DO_SPC , 1 , UNDEF_CR , 0 }, + {DO_END , 1 , UNDEF_CR , 0 } + } + }, + { + .header = (struct SR_HDR[]) { + [ 0] = {&RSC(SYS_REG_HDR11_EL).CODE()[ 0], RSC(SYS_REG_EL).CODE()}, + [ 1] = {&RSC(SYS_REG_HDR11_EL).CODE()[ 5], NULL}, + [ 2] = {&RSC(SYS_REG_HDR11_EL).CODE()[10], NULL}, + [ 3] = {&RSC(SYS_REG_HDR11_EL).CODE()[15], NULL}, + [ 4] = {&RSC(SYS_REG_HDR11_EL).CODE()[20], NULL}, + [ 5] = {&RSC(SYS_REG_HDR11_EL).CODE()[25], NULL}, + [ 6] = {&RSC(SYS_REG_HDR11_EL).CODE()[30], NULL}, + [ 7] = {&RSC(SYS_REG_HDR11_EL).CODE()[35], NULL}, + [ 8] = {&RSC(SYS_REG_HDR11_EL).CODE()[40], NULL}, + [ 9] = {&RSC(SYS_REG_HDR11_EL).CODE()[45], NULL}, + [10] = {&RSC(SYS_REG_HDR11_EL).CODE()[50], NULL}, + [11] = {&RSC(SYS_REG_HDR11_EL).CODE()[55], NULL}, + [12] = {&RSC(SYS_REG_HDR11_EL).CODE()[60], NULL}, + [13] = {&RSC(SYS_REG_HDR11_EL).CODE()[65], NULL}, + [14] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + [15] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + [16] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + + [17] = {&RSC(SYS_REG_HDR12_EL).CODE()[ 0], RSC(SYS_REG_EL_EXEC).CODE()}, + [18] = {&RSC(SYS_REG_HDR12_EL).CODE()[ 5], NULL}, + [19] = {&RSC(SYS_REG_HDR12_EL).CODE()[10], NULL}, + [20] = {&RSC(SYS_REG_HDR12_EL).CODE()[15], NULL}, + [21] = {&RSC(SYS_REG_HDR12_EL).CODE()[20], NULL}, + [22] = {&RSC(SYS_REG_HDR12_EL).CODE()[25], NULL}, + [23] = {&RSC(SYS_REG_HDR12_EL).CODE()[30], NULL}, + [24] = {&RSC(SYS_REG_HDR12_EL).CODE()[35], NULL}, + [25] = {&RSC(SYS_REG_HDR12_EL).CODE()[40], NULL}, + [26] = {&RSC(SYS_REG_HDR12_EL).CODE()[45], NULL}, + [27] = {&RSC(SYS_REG_HDR12_EL).CODE()[50], RSC(SYS_REG_EL_SEC).CODE()}, + [28] = {&RSC(SYS_REG_HDR12_EL).CODE()[55], NULL}, + [29] = {&RSC(SYS_REG_HDR12_EL).CODE()[60], NULL}, + [30] = {&RSC(SYS_REG_HDR12_EL).CODE()[65], NULL}, + [31] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + [32] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + [33] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + {NULL, NULL} + }, + .flag = (struct SR_BIT[]) { + [ 0] = {DO_CPU , 1 , UNDEF_CR , 0 }, + [ 1] = {DO_SPC , 1 , UNDEF_CR , 0 }, + [ 2] = {DO_EL , 1 , EL0_64 , 1 }, + [ 3] = {DO_EL , 1 , EL0_32 , 1 }, + [ 4] = {DO_SPC , 1 , UNDEF_CR , 0 }, + [ 5] = {DO_EL , 1 , EL1_64 , 1 }, + [ 6] = {DO_EL , 1 , EL1_32 , 1 }, + [ 7] = {DO_SPC , 1 , UNDEF_CR , 0 }, + [ 8] = {DO_EL , 1 , EL2_64 , 1 }, + [ 9] = {DO_EL , 1 , EL2_32 , 1 }, + [10] = {DO_EL , 1 , EL2_SEC , 1 }, + [11] = {DO_SPC , 1 , UNDEF_CR , 0 }, + [12] = {DO_EL , 1 , EL3_64 , 1 }, + [13] = {DO_EL , 1 , EL3_32 , 1 }, + [14] = {DO_SPC , 1 , UNDEF_CR , 0 }, + [15] = {DO_SPC , 1 , UNDEF_CR , 0 }, + [16] = {DO_SPC , 1 , UNDEF_CR , 0 }, + {DO_END , 1 , UNDEF_CR , 0 } + } + }, + { + .header = (struct SR_HDR[]) { + [ 0] = {&RSC(SYS_REG_HDR_FPSR).CODE()[ 0],RSC(SYS_REG_FPSR).CODE()}, + [ 1] = {&RSC(SYS_REG_HDR_FPSR).CODE()[ 5],RSC(SYS_REG_FLAG_N).CODE()}, + [ 2] = {&RSC(SYS_REG_HDR_FPSR).CODE()[10],RSC(SYS_REG_FLAG_Z).CODE()}, + [ 3] = {&RSC(SYS_REG_HDR_FPSR).CODE()[15],RSC(SYS_REG_FLAG_C).CODE()}, + [ 4] = {&RSC(SYS_REG_HDR_FPSR).CODE()[20],RSC(SYS_REG_FLAG_V).CODE()}, + [ 5] = {&RSC(SYS_REG_HDR_FPSR).CODE()[25],RSC(SYS_REG_FPSR_QC).CODE()}, + [ 6] = {&RSC(SYS_REG_HDR_FPSR).CODE()[30],RSC(SYS_REG_FPSR_IDC).CODE()}, + [ 7] = {&RSC(SYS_REG_HDR_FPSR).CODE()[35],RSC(SYS_REG_FPSR_IXC).CODE()}, + [ 8] = {&RSC(SYS_REG_HDR_FPSR).CODE()[40],RSC(SYS_REG_FPSR_UFC).CODE()}, + [ 9] = {&RSC(SYS_REG_HDR_FPSR).CODE()[45],RSC(SYS_REG_FPSR_OFC).CODE()}, + [10] = {&RSC(SYS_REG_HDR_FPSR).CODE()[50],RSC(SYS_REG_FPSR_DZC).CODE()}, + [11] = {&RSC(SYS_REG_HDR_FPSR).CODE()[55],RSC(SYS_REG_FPSR_IOC).CODE()}, + [12] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + [13] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + [14] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + [15] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + [16] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + {NULL, NULL} + }, + .flag = (struct SR_BIT[]) { + [ 0] = {DO_CPU , 1 , UNDEF_CR , 0 }, + [ 1] = {DO_FPSR, 1 , FPSR_N , 1 }, + [ 2] = {DO_FPSR, 1 , FPSR_Z , 1 }, + [ 3] = {DO_FPSR, 1 , FPSR_C , 1 }, + [ 4] = {DO_FPSR, 1 , FPSR_V , 1 }, + [ 5] = {DO_FPSR, 1 , FPSR_QC , 1 }, + [ 6] = {DO_FPSR, 1 , FPSR_IDC , 1 }, + [ 7] = {DO_FPSR, 1 , FPSR_IXC , 1 }, + [ 8] = {DO_FPSR, 1 , FPSR_UFC , 1 }, + [ 9] = {DO_FPSR, 1 , FPSR_OFC , 1 }, + [10] = {DO_FPSR, 1 , FPSR_DZC , 1 }, + [11] = {DO_FPSR, 1 , FPSR_IOC , 1 }, + [12] = {DO_SPC , 1 , UNDEF_CR , 0 }, + [13] = {DO_SPC , 1 , UNDEF_CR , 0 }, + [14] = {DO_SPC , 1 , UNDEF_CR , 0 }, + [15] = {DO_SPC , 1 , UNDEF_CR , 0 }, + [16] = {DO_SPC , 1 , UNDEF_CR , 0 }, + {DO_END , 1 , UNDEF_CR , 0 } + } + } + }; + CUINT cells_per_line = win->matrix.size.wth, *nl = &cells_per_line; + + size_t idx; + for (idx = 0; idx < sizeof(SR) / sizeof(struct SR_ST); idx++) + { + struct SR_HDR *pHdr; + for (pHdr = SR[idx].header; pHdr->flag != NULL; pHdr++) + { + GridHover( PRT(REG, attrib[0], "%s", pHdr->flag), + (char *) pHdr->comm ); + } + unsigned int cpu; + for (cpu = 0; cpu < RO(Shm)->Proc.CPU.Count; cpu++) + { + struct SR_BIT *pFlag; + for (pFlag = SR[idx].flag; pFlag->automat != DO_END; pFlag++) + { + switch (pFlag->automat) { + case DO_END: + case DO_SPC: + PRT(REG, attrib[0], RSC(SYS_REGS_SPACE).CODE()); + break; + case DO_CPU: + PRT(REG,attrib[BITVAL(RO(Shm)->Cpu[cpu].OffLine,OS) ? 4:3], + "#%-2u ", cpu); + break; + default: + { + if (pFlag->capable && !BITVAL(RO(Shm)->Cpu[cpu].OffLine, OS)) + { + switch (pFlag->automat) { + case DO_FLAG: + PRT(REG, attrib[2], "%3llx ", + BITEXTRZ(RO(Shm)->Cpu[cpu].SystemRegister.FLAGS, + pFlag->pos, pFlag->len)); + break; + case DO_SCTLR: + PRT(REG, attrib[2], "%3llx ", + BITEXTRZ(RO(Shm)->Cpu[cpu].SystemRegister.SCTLR, + pFlag->pos, pFlag->len)); + break; + case DO_SCTLR2: + if (RO(Shm)->Cpu[cpu].Query.SCTLRX) + { + PRT(REG, attrib[2], "%3llx ", + BITEXTRZ(RO(Shm)->Cpu[cpu].SystemRegister.SCTLR2, + pFlag->pos, pFlag->len)); + } else { + PRT(REG, attrib[1], RSC(SYS_REGS_NA).CODE()); + } + break; + case DO_EL: + PRT(REG, attrib[2], "%3llx ", + BITEXTRZ(RO(Shm)->Cpu[cpu].SystemRegister.EL, + pFlag->pos, pFlag->len)); + break; + case DO_FPSR: + PRT(REG, attrib[2], "%3llx ", + BITEXTRZ(RO(Shm)->Cpu[cpu].SystemRegister.FPSR, + pFlag->pos, pFlag->len)); + break; + default: + PRT(REG, attrib[1], RSC(SYS_REGS_NA).CODE()); + break; + } + } else { + PRT(REG, attrib[1], RSC(SYS_REGS_NA).CODE()); + } + } + break; + } + } + } + } + return reason; +} + +char SymbUnlock[2][2] = {{'[', ']'}, {'<', '>'}}; + +TGrid *PrintRatioFreq( Window *win, + struct FLIP_FLOP *CFlop, + unsigned int zerobase, + char *pfx, + unsigned int *pRatio, + int syc, + unsigned long long _key, + CUINT width, + CELL_FUNC OutFunc, + unsigned int *cellPadding, + ATTRIBUTE attrib[] ) +{ + TGrid *pGrid = NULL; + + if ((( (*pRatio) > 0) && !zerobase) || (zerobase)) + { + double Freq_MHz = ABS_FREQ_MHz(double, (*pRatio), CFlop->Clock); + + if ((Freq_MHz > 0.0) && (Freq_MHz < CLOCK_MHz(double, UNIT_GHz(10.0)))) + { + pGrid = PUT(_key, attrib, width, 0, + "%.*s""%s""%.*s""%7.2f""%.*s""%c%4d %c", + (int) (20 - strlen(pfx)), hSpace, pfx, 3, hSpace, + Freq_MHz, + 20, hSpace, + SymbUnlock[syc][0], + (*pRatio), + SymbUnlock[syc][1]); + } else { + pGrid = PUT(_key, attrib, width, 0, + "%.*s""%s""%.*s""%7s""%.*s""%c%4d %c", + (int) (20 - strlen(pfx)), hSpace, pfx, 3, hSpace, + RSC(AUTOMATIC).CODE(), + 20, hSpace, + SymbUnlock[syc][0], + (*pRatio), + SymbUnlock[syc][1]); + } + } + return pGrid; +} + +void RefreshBaseClock(TGrid *grid, DATA_TYPE data[]) +{ + struct FLIP_FLOP *CFlop = \ + &RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].FlipFlop[ + !RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Toggle + ]; + char item[8+1]; + UNUSED(data); + + StrFormat(item, 8+1, "%7.3f", CLOCK_MHz(double, CFlop->Clock.Hz)); + + memcpy(&grid->cell.item[grid->cell.length - 9], item, 7); +} + +void RefreshFactoryClock(TGrid *grid, DATA_TYPE data[]) +{ + char item[8+1]; + UNUSED(data); + + StrFormat(item, 8+1, "%7.3f", + CLOCK_MHz(double, RO(Shm)->Proc.Features.Factory.Clock.Hz)); + + memcpy(&grid->cell.item[grid->cell.length - 9], item, 7); +} + +void RefreshFactoryFreq(TGrid *grid, DATA_TYPE data[]) +{ + char item[11+11+1]; + UNUSED(data); + + StrFormat(item, 11+11+1, "%5u" "%4u", + RO(Shm)->Proc.Features.Factory.Freq, + RO(Shm)->Proc.Features.Factory.Ratio); + + memcpy(&grid->cell.item[22], &item[0], 5); + memcpy(&grid->cell.item[51], &item[5], 4); +} + +void RefreshItemFreq(TGrid *grid, unsigned int ratio, double Freq_MHz) +{ + char item[11+8+1]; + + if ((Freq_MHz > 0.0) && (Freq_MHz < CLOCK_MHz(double, UNIT_GHz(10.0)))) { + StrFormat(item,11+8+1, "%4u%7.2f", ratio, Freq_MHz); + } else { + StrFormat(item,11+7+1, "%4u%7s", ratio, RSC(AUTOMATIC).CODE()); + } + memcpy(&grid->cell.item[23], &item[4], 7); + memcpy(&grid->cell.item[51], &item[0], 4); +} + +void RefreshRatioFreq(TGrid *grid, DATA_TYPE data[]) +{ + struct FLIP_FLOP *CFlop = \ + &RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].FlipFlop[ + !RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Toggle + ]; + RefreshItemFreq(grid, + (*data[0].puint), + ABS_FREQ_MHz(double, (*data[0].puint), CFlop->Clock)); +} + +void RefreshTopFreq(TGrid *grid, DATA_TYPE data[]) +{ + enum RATIO_BOOST boost = data[0].uint[0]; + unsigned int top = Ruler.Top[boost]; + unsigned int ratio = RO(Shm)->Cpu[top].Boost[boost]; + + struct FLIP_FLOP *CFlop = &RO(Shm)->Cpu[top].FlipFlop[ + !RO(Shm)->Cpu[top].Toggle + ]; + RefreshItemFreq(grid, ratio, ABS_FREQ_MHz(double, ratio, CFlop->Clock)); +} + +void RefreshPrimaryFreq(TGrid *grid, DATA_TYPE data[]) +{ + enum RATIO_BOOST boost = data[0].uint[0]; + unsigned int ratio = RO(Shm)->Cpu[ + RO(Shm)->Proc.Service.Core + ].Boost[boost]; + + struct FLIP_FLOP *CFlop = &RO(Shm)->Cpu[ + RO(Shm)->Proc.Service.Core + ].FlipFlop[ + !RO(Shm)->Cpu[ + RO(Shm)->Proc.Service.Core + ].Toggle + ]; + RefreshItemFreq(grid, ratio, ABS_FREQ_MHz(double, ratio, CFlop->Clock)); +} + +void RefreshHybridFreq(TGrid *grid, DATA_TYPE data[]) +{ + enum RATIO_BOOST boost = data[0].uint[0]; + unsigned int ratio = RO(Shm)->Cpu[ + RO(Shm)->Proc.Service.Hybrid + ].Boost[boost]; + + struct FLIP_FLOP *CFlop = &RO(Shm)->Cpu[ + RO(Shm)->Proc.Service.Hybrid + ].FlipFlop[ + !RO(Shm)->Cpu[ + RO(Shm)->Proc.Service.Hybrid + ].Toggle + ]; + RefreshItemFreq(grid, ratio, ABS_FREQ_MHz(double, ratio, CFlop->Clock)); +} + +void RefreshConfigTDP(TGrid *grid, DATA_TYPE data[]) +{ + char item[11+11+1]; + UNUSED(data); + + StrFormat(item, 11+11+1, "%3d:%-3d", + RO(Shm)->Proc.Features.TDP_Cfg_Level, + RO(Shm)->Proc.Features.TDP_Levels); + + memcpy(&grid->cell.item[grid->cell.length - 9], item, 7); +} + +REASON_CODE SysInfoProc(Window *win, + CUINT width, + CELL_FUNC OutFunc, + unsigned int *cellPadding) +{ + REASON_INIT(reason); + ATTRIBUTE *attrib[4] = { + RSC(SYSINFO_PROC_COND0).ATTR(), + RSC(SYSINFO_PROC_COND1).ATTR(), + RSC(SYSINFO_PROC_COND2).ATTR(), + RSC(SYSINFO_PROC_COND3).ATTR() + }; + struct FLIP_FLOP *CFlop; + CLOCK_ARG coreClock = {.NC = 0, .Offset = 0}; + unsigned int activeCores; + enum RATIO_BOOST boost = 0; + + PUT( SCANKEY_NULL, attrib[0], width, 0, + "%s""%.*s[%s]", RSC(PROCESSOR).CODE(), + width - 2 - RSZ(PROCESSOR) - (int) strlen(RO(Shm)->Proc.Brand), + hSpace, RO(Shm)->Proc.Brand ); + + if (RO(Shm)->Proc.Features.Factory.PPIN > 0) + { + PUT( SCANKEY_NULL, attrib[0], width, 2, + "%s""%.*s[%16llx]", RSC(PPIN).CODE(), + width - 21 - RSZ(PPIN), + hSpace, RO(Shm)->Proc.Features.Factory.PPIN ); + } + PUT( SCANKEY_NULL, attrib[0], width, 2, + "%s""%.*s[%s]", RSC(ARCHITECTURE).CODE(), + width - 5 - RSZ(ARCHITECTURE) + - (int) strlen(RO(Shm)->Proc.Architecture), + hSpace, RO(Shm)->Proc.Architecture ); + + PUT( SCANKEY_NULL, attrib[0], width, 2, + "%s""%.*s[%s]", RSC(VENDOR_ID).CODE(), + width - 5 - RSZ(VENDOR_ID) + - (int) strlen(RO(Shm)->Proc.Features.Info.Vendor.ID), + hSpace, RO(Shm)->Proc.Features.Info.Vendor.ID ); + + PUT( SCANKEY_NULL, attrib[0], width, 2, + "%s""%.*s[0x%08x]", RSC(REVISION).CODE(), + width - 15 - RSZ(REVISION), hSpace, + RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Query.Revision ); + + PUT( SCANKEY_NULL, attrib[2], width, 2, + "%s""%.*s[%3X%1X_%1X%1X]", RSC(SIGNATURE).CODE(), + width - 12 - RSZ(SIGNATURE), hSpace, + RO(Shm)->Proc.Features.Info.Signature.ExtFamily, + RO(Shm)->Proc.Features.Info.Signature.Family, + RO(Shm)->Proc.Features.Info.Signature.ExtModel, + RO(Shm)->Proc.Features.Info.Signature.Model ); + + PUT( SCANKEY_NULL, attrib[2], width, 2, + "%s""%.*s[ r%xp%-x]", RSC(STEPPING).CODE(), + width - 12 - RSZ(STEPPING), hSpace, + (RO(Shm)->Proc.Features.Info.Signature.Stepping >> 4) & 0xf, + RO(Shm)->Proc.Features.Info.Signature.Stepping & 0xf); + + PUT( SCANKEY_NULL, attrib[2], width, 2, + "%s""%.*s[%3u/%3u]", RSC(ONLINE_CPU).CODE(), + width - 12 - RSZ(ONLINE_CPU), hSpace, + RO(Shm)->Proc.CPU.OnLine, RO(Shm)->Proc.CPU.Count ); + + CFlop = &RO(Shm)->Cpu[ + RO(Shm)->Proc.Service.Core + ].FlipFlop[ + !RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Toggle + ]; + + GridCall( PUT( SCANKEY_NULL, attrib[2], width, 2, + "%s""%.*s[%7.3f]", RSC(BASE_CLOCK).CODE(), + width - 12 - RSZ(BASE_CLOCK), hSpace, + CLOCK_MHz(double, CFlop->Clock.Hz) ), + RefreshBaseClock ); + + PUT( SCANKEY_NULL, attrib[0], width, 2, + "%s""%.*s%s%.*s""%s", RSC(FREQUENCY).CODE(), + 21 - RSZ(FREQUENCY), hSpace, + RSC(FREQ_UNIT_MHZ).CODE(), + 23 - (OutFunc == NULL), hSpace, + RSC(RATIO).CODE() ); + + coreClock.NC = BOXKEY_RATIO_CLOCK_OR | CLOCK_MOD_MIN; + + CFlop = &RO(Shm)->Cpu[ + Ruler.Top[ BOOST(MIN) ] + ].FlipFlop[ + !RO(Shm)->Cpu[ Ruler.Top[ BOOST(MIN) ] ].Toggle + ]; + + GridCall( PrintRatioFreq(win, CFlop, + 0, (char*) RSC(MIN).CODE(), + &RO(Shm)->Cpu[ + Ruler.Top[ BOOST(MIN) ] + ].Boost[ BOOST(MIN) ], + 1, coreClock.ullong, + width, OutFunc, cellPadding, attrib[3] ), + RefreshTopFreq, BOOST(MIN) ); + + coreClock = (CLOCK_ARG) {.NC = 0, .Offset = 0}; + + coreClock.NC = BOXKEY_RATIO_CLOCK_OR | CLOCK_MOD_MAX; + + CFlop = &RO(Shm)->Cpu[ + Ruler.Top[ BOOST(MAX) ] + ].FlipFlop[ + !RO(Shm)->Cpu[ Ruler.Top[ BOOST(MAX) ] ].Toggle + ]; + + GridCall( PrintRatioFreq(win, CFlop, + 0, (char*) RSC(MAX).CODE(), + &RO(Shm)->Cpu[ + Ruler.Top[ BOOST(MAX) ] + ].Boost[ BOOST(MAX) ], + 1, coreClock.ullong, + width, OutFunc, cellPadding, attrib[3] ), + RefreshTopFreq, BOOST(MAX) ); + + GridCall( PUT( SCANKEY_NULL, attrib[0], width, 2, + "%s""%.*s[%7.3f]", RSC(FACTORY).CODE(), + (OutFunc == NULL ? 68 : 64) - RSZ(FACTORY), hSpace, + CLOCK_MHz(double,RO(Shm)->Proc.Features.Factory.Clock.Hz) ), + RefreshFactoryClock ); + + GridCall( PUT( SCANKEY_NULL, attrib[3], width, 0, + "%.*s""%5u""%.*s""[%4d ]", + 22, hSpace, RO(Shm)->Proc.Features.Factory.Freq, + 23, hSpace, RO(Shm)->Proc.Features.Factory.Ratio ), + RefreshFactoryFreq ); + + PUT(SCANKEY_NULL, attrib[0], width, 2, "%s", RSC(PERFORMANCE).CODE()); + + coreClock = (CLOCK_ARG) {.NC = 0, .Offset = 0}; + + coreClock.NC = BOXKEY_RATIO_CLOCK_OR | CLOCK_MOD_TGT; + + CFlop = &RO(Shm)->Cpu[ + Ruler.Top[ BOOST(TGT) ] + ].FlipFlop[ + !RO(Shm)->Cpu[ Ruler.Top[ BOOST(TGT) ] ].Toggle + ]; + + GridCall( PrintRatioFreq(win, CFlop, + 1, (char*) RSC(TGT).CODE(), + &RO(Shm)->Cpu[ + Ruler.Top[ BOOST(TGT) ] + ].Boost[ BOOST(TGT) ], + 1, coreClock.ullong, + width, OutFunc, cellPadding, attrib[3] ), + RefreshTopFreq, BOOST(TGT) ); +/* Section Mark */ + if ((RO(Shm)->Proc.Features.HWP_Enable == 1) + || (RO(Shm)->Proc.Features.ACPI_CPPC == 1)) + { + coreClock = (CLOCK_ARG) {.NC = 0, .Offset = 0}; + + PUT(SCANKEY_NULL, attrib[0], width, 3, "%s", RSC(CPPC).CODE()); + + coreClock.NC = BOXKEY_RATIO_CLOCK_OR | CLOCK_MOD_HWP_MIN; + + CFlop = &RO(Shm)->Cpu[ + Ruler.Top[ BOOST(HWP_MIN) ] + ].FlipFlop[ + !RO(Shm)->Cpu[ Ruler.Top[ BOOST(HWP_MIN) ] ].Toggle + ]; + + GridCall( PrintRatioFreq(win, CFlop, + 1, (char*) RSC(MIN).CODE(), + &RO(Shm)->Cpu[ + Ruler.Top[ BOOST(HWP_MIN) ] + ].Boost[ BOOST(HWP_MIN) ], + 1, coreClock.ullong, + width, OutFunc, cellPadding, attrib[3] ), + RefreshTopFreq, BOOST(HWP_MIN) ); + + coreClock.NC = BOXKEY_RATIO_CLOCK_OR | CLOCK_MOD_HWP_MAX; + + CFlop = &RO(Shm)->Cpu[ + Ruler.Top[ BOOST(HWP_MAX) ] + ].FlipFlop[ + !RO(Shm)->Cpu[Ruler.Top[ BOOST(HWP_MAX) ] ].Toggle + ]; + + GridCall( PrintRatioFreq(win, CFlop, + 1, (char*) RSC(MAX).CODE(), + &RO(Shm)->Cpu[ + Ruler.Top[ BOOST(HWP_MAX) ] + ].Boost[ BOOST(HWP_MAX) ], + 1, coreClock.ullong, + width, OutFunc, cellPadding, attrib[3] ), + RefreshTopFreq, BOOST(HWP_MAX) ); + + coreClock.NC = BOXKEY_RATIO_CLOCK_OR | CLOCK_MOD_HWP_TGT; + + CFlop = &RO(Shm)->Cpu[ + Ruler.Top[ BOOST(HWP_TGT) ] + ].FlipFlop[ + !RO(Shm)->Cpu[ Ruler.Top[ BOOST(HWP_TGT) ] ].Toggle + ]; + + GridCall( PrintRatioFreq(win, CFlop, + 1, (char*) RSC(TGT).CODE(), + &RO(Shm)->Cpu[ + Ruler.Top[ BOOST(HWP_TGT) ] + ].Boost[ BOOST(HWP_TGT) ], + 1, coreClock.ullong, + width, OutFunc, cellPadding, attrib[3] ), + RefreshTopFreq, BOOST(HWP_TGT) ); + } +/* Section Mark */ + if (RO(Shm)->Proc.Features.Turbo_OPP == 1) + { + PUT( SCANKEY_NULL, attrib[RO(Shm)->Proc.Features.Turbo_Unlock], + width, 2, "%s%.*s[%7.*s]", RSC(TURBO).CODE(), + width - 12 - RSZ(TURBO), hSpace, 6, + RO(Shm)->Proc.Features.Turbo_Unlock ? + RSC(UNLOCK).CODE() : RSC(LOCK).CODE() ); + + CFlop = &RO(Shm)->Cpu[ + Ruler.Top[ BOOST(TBH) ] + ].FlipFlop[ + !RO(Shm)->Cpu[ Ruler.Top[ BOOST(TBH) ] ].Toggle + ]; + + GridCall( PrintRatioFreq(win, CFlop, + 0, (char*) RSC(TBH).CODE(), + &RO(Shm)->Cpu[ + Ruler.Top[ BOOST(TBH) ] + ].Boost[ BOOST(TBH) ], + 0, SCANKEY_NULL, + width, OutFunc, cellPadding, attrib[3] ), + RefreshTopFreq, BOOST(TBH) ); + + CFlop = &RO(Shm)->Cpu[ + Ruler.Top[ BOOST(TBO) ] + ].FlipFlop[ + !RO(Shm)->Cpu[ Ruler.Top[ BOOST(TBO) ] ].Toggle + ]; + + GridCall( PrintRatioFreq(win, CFlop, + 0, (char*) RSC(TBO).CODE(), + &RO(Shm)->Cpu[ + Ruler.Top[ BOOST(TBO) ] + ].Boost[BOOST(TBO)], + 0, SCANKEY_NULL, + width, OutFunc, cellPadding, attrib[3] ), + RefreshTopFreq, BOOST(TBO) ); + } +/* Section Mark */ + PUT(SCANKEY_NULL, attrib[0], width, 2, "%s", RSC(OPP).CODE()); + + for(boost = BOOST(1C), activeCores = 1; + boost > BOOST(1C)-(enum RATIO_BOOST)RO(Shm)->Proc.Features.SpecTurboRatio; + boost--, activeCores++) + { + CLOCK_ARG clockMod={.NC=BOXKEY_TURBO_CLOCK_NC | activeCores,.Offset=0}; + const unsigned int primary = RO(Shm)->Proc.Features.Hybrid == 1 ? + RO(Shm)->Proc.Service.Core : Ruler.Top[boost]; + + char pfx[10+1+1]; + StrFormat(pfx, 10+1+1, "%2uC", activeCores); + + CFlop = &RO(Shm)->Cpu[primary].FlipFlop[!RO(Shm)->Cpu[primary].Toggle]; + + GridCall( PrintRatioFreq(win, CFlop, + 0, pfx, &RO(Shm)->Cpu[ + primary + ].Boost[boost], + 1, clockMod.ullong, + width, OutFunc, cellPadding, attrib[3] ), + RO(Shm)->Proc.Features.Hybrid == 1 ? + RefreshPrimaryFreq : RefreshTopFreq, boost ); + } + if (RO(Shm)->Proc.Features.Hybrid == 1) + { + PUT( SCANKEY_NULL, attrib[RO(Shm)->Proc.Features.Turbo_Unlock], + width, 2, "%s%.*s[%7.*s]", RSC(HYBRID).CODE(), + width - 12 - RSZ(HYBRID), hSpace, 6, + RO(Shm)->Proc.Features.Turbo_Unlock ? + RSC(UNLOCK).CODE() : RSC(LOCK).CODE() ); + + for(boost = BOOST(1C), activeCores = 1; + boost > BOOST(1C)-(enum RATIO_BOOST)RO(Shm)->Proc.Features.SpecTurboRatio; + boost--, activeCores++) + { + CLOCK_ARG clockMod={.NC=BOXKEY_TURBO_CLOCK_NC | activeCores,.Offset=0}; + char pfx[10+1+1]; + StrFormat(pfx, 10+1+1, "%2uC", activeCores); + + CFlop = &RO(Shm)->Cpu[ + RO(Shm)->Proc.Service.Hybrid + ].FlipFlop[ + !RO(Shm)->Cpu[RO(Shm)->Proc.Service.Hybrid].Toggle + ]; + + GridCall( PrintRatioFreq(win, CFlop, + 0, pfx, &RO(Shm)->Cpu[ + RO(Shm)->Proc.Service.Hybrid + ].Boost[boost], + 1, clockMod.ullong, + width, OutFunc, cellPadding, attrib[3] ), + RefreshHybridFreq, boost ); + } + } +/* Section Mark */ + PUT( SCANKEY_NULL, attrib[RO(Shm)->Proc.Features.Uncore_Unlock], + width, 2, "%s%.*s[%7.*s]", RSC(UNCORE).CODE(), + width - 18, hSpace, 6, + RO(Shm)->Proc.Features.Uncore_Unlock ? + RSC(UNLOCK).CODE() : RSC(LOCK).CODE() ); + + ASCII *uncoreLabel[2]; + + uncoreLabel[0] = RSC(MIN).CODE(); + uncoreLabel[1] = RSC(MAX).CODE(); + + if (RO(Shm)->Proc.Features.Uncore_Unlock) { + CLOCK_ARG uncoreClock = {.NC = 0, .Offset = 0}; + + uncoreClock.NC = BOXKEY_UNCORE_CLOCK_OR | CLOCK_MOD_MIN; + GridCall( PrintRatioFreq(win, CFlop, + 0, (char*) uncoreLabel[0], + &RO(Shm)->Uncore.Boost[UNCORE_BOOST(MIN)], + 1, uncoreClock.ullong, + width, OutFunc, cellPadding, attrib[3] ), + RefreshRatioFreq, &RO(Shm)->Uncore.Boost[UNCORE_BOOST(MIN)] ); + + uncoreClock.NC = BOXKEY_UNCORE_CLOCK_OR | CLOCK_MOD_MAX; + GridCall( PrintRatioFreq(win, CFlop, + 0, (char*) uncoreLabel[1], + &RO(Shm)->Uncore.Boost[UNCORE_BOOST(MAX)], + 1, uncoreClock.ullong, + width, OutFunc, cellPadding, attrib[3]), + RefreshRatioFreq, &RO(Shm)->Uncore.Boost[UNCORE_BOOST(MAX)] ); + } else { + GridCall( PrintRatioFreq(win, CFlop, + 0, (char*) uncoreLabel[0], + &RO(Shm)->Uncore.Boost[UNCORE_BOOST(MIN)], + 0, SCANKEY_NULL, + width, OutFunc, cellPadding, attrib[3]), + RefreshRatioFreq, &RO(Shm)->Uncore.Boost[UNCORE_BOOST(MIN)] ); + + GridCall( PrintRatioFreq(win, CFlop, + 0, (char*) uncoreLabel[1], + &RO(Shm)->Uncore.Boost[UNCORE_BOOST(MAX)], + 0, SCANKEY_NULL, + width, OutFunc, cellPadding, attrib[3]), + RefreshRatioFreq, &RO(Shm)->Uncore.Boost[UNCORE_BOOST(MAX)] ); + } + return reason; +} + +REASON_CODE SysInfoISA( Window *win, + CELL_FUNC OutFunc, + unsigned int *cellPadding ) +{ + REASON_INIT(reason); + ATTRIBUTE *attrib[2][5] = { + { + /* [N],[N/N]*/ RSC(SYSINFO_ISA_COND_0_0).ATTR(), + /* [Y] */ RSC(SYSINFO_ISA_COND_0_1).ATTR(), + /* [N/Y] */ RSC(SYSINFO_ISA_COND_0_2).ATTR(), + /* [Y/N] */ RSC(SYSINFO_ISA_COND_0_3).ATTR(), + /* [Y/Y] */ RSC(SYSINFO_ISA_COND_0_4).ATTR() + }, { + RSC(SYSINFO_ISA_COND_1_0).ATTR(), + RSC(SYSINFO_ISA_COND_1_1).ATTR(), + RSC(SYSINFO_ISA_COND_1_2).ATTR(), + RSC(SYSINFO_ISA_COND_1_3).ATTR(), + RSC(SYSINFO_ISA_COND_1_4).ATTR() + } + }; + const struct ISA_ST { + unsigned int *CRC; + const ASCII *item, *comm; + unsigned short thm[2]; + unsigned short *cond; + } ISA[] = \ + { +/* Row Mark */ + { + NULL, + RSC(ISA_AES).CODE(), RSC(ISA_AES_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.AES }, + (unsigned short[]) + { RO(Shm)->Proc.Features.AES }, + }, + { + NULL, + RSC(ISA_SIMD).CODE(), RSC(ISA_SIMD_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.SIMD }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SIMD }, + }, + { + NULL, + RSC(ISA_ATS1A).CODE(), RSC(ISA_ATS1A_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.ATS1A }, + (unsigned short[]) + { RO(Shm)->Proc.Features.ATS1A }, + }, + { + NULL, + RSC(ISA_BF16).CODE(), RSC(ISA_BF16_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.BF16 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.BF16 }, + }, +/* Row Mark */ + { + NULL, + RSC(ISA_CONSTPACFLD).CODE(), RSC(ISA_CONSTPACFLD_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.CONSTPACFIELD }, + (unsigned short[]) + { RO(Shm)->Proc.Features.CONSTPACFIELD }, + }, + { + NULL, + RSC(ISA_CRC32).CODE(), RSC(ISA_CRC32_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.CRC32 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.CRC32 }, + }, + { + NULL, + RSC(ISA_CSSC).CODE(), RSC(ISA_CSSC_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.CSSC }, + (unsigned short[]) + { RO(Shm)->Proc.Features.CSSC }, + }, + { + NULL, + RSC(ISA_DGH).CODE(), RSC(ISA_DGH_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.DGH }, + (unsigned short[]) + { RO(Shm)->Proc.Features.DGH }, + }, +/* Row Mark */ + { + NULL, + RSC(ISA_DP).CODE(), RSC(ISA_DP_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.DP }, + (unsigned short[]) + { RO(Shm)->Proc.Features.DP }, + }, + { + NULL, + RSC(ISA_DPB).CODE(), RSC(ISA_DPB_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.DPB }, + (unsigned short[]) + { RO(Shm)->Proc.Features.DPB }, + }, + { + NULL, + RSC(ISA_DPB2).CODE(), RSC(ISA_DPB_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.DPB2 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.DPB2 }, + }, + { + NULL, + RSC(ISA_EBF16).CODE(), RSC(ISA_EBF16_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.EBF16 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.EBF16 }, + }, +/* Row Mark */ + { + NULL, + RSC(ISA_EPAC).CODE(), RSC(ISA_EPAC_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.EPAC }, + (unsigned short[]) + { RO(Shm)->Proc.Features.EPAC }, + }, + { + NULL, + RSC(ISA_FCMA).CODE(), RSC(ISA_FCMA_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.FCMA }, + (unsigned short[]) + { RO(Shm)->Proc.Features.FCMA }, + }, + { + NULL, + RSC(ISA_FHM).CODE(), RSC(ISA_FHM_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.FHM }, + (unsigned short[]) + { RO(Shm)->Proc.Features.FHM }, + }, + { + NULL, + RSC(ISA_FlagM).CODE(), RSC(ISA_FlagM_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.FlagM }, + (unsigned short[]) + { RO(Shm)->Proc.Features.FlagM }, + }, +/* Row Mark */ + { + NULL, + RSC(ISA_FlagM2).CODE(), RSC(ISA_FlagM_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.FlagM2 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.FlagM2 }, + }, + { + NULL, + RSC(ISA_FP).CODE(), RSC(ISA_FP_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.FP }, + (unsigned short[]) + { RO(Shm)->Proc.Features.FP }, + }, + { + NULL, + RSC(ISA_FPAC).CODE(), RSC(ISA_FPAC_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.FPAC }, + (unsigned short[]) + { RO(Shm)->Proc.Features.FPAC }, + }, + { + NULL, + RSC(ISA_FPACCOMBINE).CODE(), RSC(ISA_FPACCOMBINE_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.FPACCOMBINE }, + (unsigned short[]) + { RO(Shm)->Proc.Features.FPACCOMBINE }, + }, +/* Row Mark */ + { + NULL, + RSC(ISA_FRINTTS).CODE(), RSC(ISA_FRINTTS_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.FRINTTS }, + (unsigned short[]) + { RO(Shm)->Proc.Features.FRINTTS }, + }, + { + NULL, + RSC(ISA_HBC).CODE(), RSC(ISA_HBC_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.HBC }, + (unsigned short[]) + { RO(Shm)->Proc.Features.HBC }, + }, + { + NULL, + RSC(ISA_I8MM).CODE(), RSC(ISA_I8MM_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.I8MM }, + (unsigned short[]) + { RO(Shm)->Proc.Features.I8MM }, + }, + { + NULL, + RSC(ISA_JSCVT).CODE(), RSC(ISA_JSCVT_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.JSCVT }, + (unsigned short[]) + { RO(Shm)->Proc.Features.JSCVT }, + }, +/* Row Mark */ + { + NULL, + RSC(ISA_LRCPC).CODE(), RSC(ISA_LRCPC_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.LRCPC }, + (unsigned short[]) + { RO(Shm)->Proc.Features.LRCPC }, + }, + { + NULL, + RSC(ISA_LRCPC2).CODE(), RSC(ISA_LRCPC_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.LRCPC2 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.LRCPC2 }, + }, + { + NULL, + RSC(ISA_LRCPC3).CODE(), RSC(ISA_LRCPC_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.LRCPC3 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.LRCPC3 }, + }, + { + NULL, + RSC(ISA_LS64).CODE(), RSC(ISA_LS64_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.LS64 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.LS64 }, + }, +/* Row Mark */ + { + NULL, + RSC(ISA_LS64_V).CODE(), RSC(ISA_LS64_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.LS64_V }, + (unsigned short[]) + { RO(Shm)->Proc.Features.LS64_V }, + }, + { + NULL, + RSC(ISA_LS64_ACCDATA).CODE(), RSC(ISA_LS64_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.LS64_ACCDATA }, + (unsigned short[]) + { RO(Shm)->Proc.Features.LS64_ACCDATA }, + }, + { + NULL, + RSC(ISA_LSE).CODE(), RSC(ISA_LSE_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.LSE }, + (unsigned short[]) + { RO(Shm)->Proc.Features.LSE }, + }, + { + NULL, + RSC(ISA_LSE128).CODE(), RSC(ISA_LSE_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.LSE128 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.LSE128 }, + }, +/* Row Mark */ + { + NULL, + RSC(ISA_LUT).CODE(), RSC(ISA_LUT_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.LUT }, + (unsigned short[]) + { RO(Shm)->Proc.Features.LUT }, + }, + { + NULL, + RSC(ISA_MOPS).CODE(), RSC(ISA_MOPS_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.MOPS }, + (unsigned short[]) + { RO(Shm)->Proc.Features.MOPS }, + }, + { + NULL, + RSC(ISA_PACGA).CODE(), RSC(ISA_PACIMP_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.PACIMP }, + (unsigned short[]) + { RO(Shm)->Proc.Features.PACIMP }, + }, + { + NULL, + RSC(ISA_PACQARMA3).CODE(), RSC(ISA_PACQARMA3_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.PACQARMA3 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.PACQARMA3 }, + }, +/* Row Mark */ + { + NULL, + RSC(ISA_PACQARMA5).CODE(), RSC(ISA_PACQARMA5_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.PACQARMA5 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.PACQARMA5 }, + }, + { + NULL, + RSC(ISA_PAUTH).CODE(), RSC(ISA_PAUTH_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.PAuth }, + (unsigned short[]) + { RO(Shm)->Proc.Features.PAuth }, + }, + { + NULL, + RSC(ISA_PAUTH2).CODE(), RSC(ISA_PAUTH2_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.PAuth2 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.PAuth2 }, + }, + { + NULL, + RSC(ISA_PAUTH_LR).CODE(), RSC(ISA_PAUTH_LR_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.PAuth_LR }, + (unsigned short[]) + { RO(Shm)->Proc.Features.PAuth_LR }, + }, +/* Row Mark */ + { + NULL, + RSC(ISA_PRFMSLC).CODE(), RSC(ISA_PRFMSLC_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.PRFMSLC }, + (unsigned short[]) + { RO(Shm)->Proc.Features.PRFMSLC }, + }, + { + NULL, + RSC(ISA_PMULL).CODE(), RSC(ISA_AES_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.PMULL }, + (unsigned short[]) + { RO(Shm)->Proc.Features.PMULL }, + }, + { + NULL, + RSC(ISA_RAND).CODE(), RSC(ISA_RAND_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.RAND }, + (unsigned short[]) + { RO(Shm)->Proc.Features.RAND }, + }, + { + NULL, + RSC(ISA_RDMA).CODE(), RSC(ISA_RDMA_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.RDMA }, + (unsigned short[]) + { RO(Shm)->Proc.Features.RDMA }, + }, +/* Row Mark */ + { + NULL, + RSC(ISA_RNG_TRAP).CODE(), RSC(ISA_RNG_TRAP_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.RNG_TRAP }, + (unsigned short[]) + { RO(Shm)->Proc.Features.RNG_TRAP }, + }, + { + NULL, + RSC(ISA_RPRES).CODE(), RSC(ISA_RPRES_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.RPRES }, + (unsigned short[]) + { RO(Shm)->Proc.Features.RPRES }, + }, + { + NULL, + RSC(ISA_RPRFM).CODE(), RSC(ISA_RPRFM_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.RPRFM }, + (unsigned short[]) + { RO(Shm)->Proc.Features.RPRFM }, + }, + { + NULL, + RSC(ISA_SB).CODE(), RSC(ISA_SB_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.SB }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SB }, + }, +/* Row Mark */ + { + NULL, + RSC(ISA_SHA1).CODE(), RSC(ISA_SHA_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.SHA1 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SHA1 }, + }, + { + NULL, + RSC(ISA_SHA256).CODE(), RSC(ISA_SHA_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.SHA256 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SHA256 }, + }, + { + NULL, + RSC(ISA_SHA512).CODE(), RSC(ISA_SHA_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.SHA512 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SHA512 }, + }, + { + NULL, + RSC(ISA_SHA3).CODE(), RSC(ISA_SHA_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.SHA3 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SHA3 }, + }, +/* Row Mark */ + { + NULL, + RSC(ISA_SM3).CODE(), RSC(ISA_SM_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.SM3 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SM3 }, + }, + { + NULL, + RSC(ISA_SM4).CODE(), RSC(ISA_SM_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.SM4 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SM4 }, + }, + { + NULL, + RSC(ISA_SME).CODE(), RSC(ISA_SME_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.SME }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME }, + }, + { + NULL, + RSC(ISA_SME2).CODE(), RSC(ISA_SME_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.SME2 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME2 }, + }, +/* Row Mark */ + { + NULL, + RSC(ISA_SME2p1).CODE(), RSC(ISA_SME_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.SME2p1 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME2p1 }, + }, + { + NULL, + RSC(ISA_SME_FA64).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_FA64 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_FA64 }, + }, + { + NULL, + RSC(ISA_SME_LUTv2).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_LUTv2 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_LUTv2 }, + }, + { + NULL, + RSC(ISA_SME_I16I64).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_I16I64 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_I16I64 }, + }, +/* Row Mark */ + { + NULL, + RSC(ISA_SME_F64F64).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_F64F64 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_F64F64 }, + }, + { + NULL, + RSC(ISA_SME_I16I32).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_I16I32 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_I16I32 }, + }, + { + NULL, + RSC(ISA_SME_B16B16).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_B16B16 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_B16B16 }, + }, + { + NULL, + RSC(ISA_SME_F16F16).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_F16F16 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_F16F16 }, + }, +/* Row Mark */ + { + NULL, + RSC(ISA_SME_F8F16).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_F8F16 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_F8F16 }, + }, + { + NULL, + RSC(ISA_SME_F8F32).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_F8F32 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_F8F32 }, + }, + { + NULL, + RSC(ISA_SME_I8I32).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_I8I32 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_I8I32 }, + }, + { + NULL, + RSC(ISA_SME_F16F32).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_F16F32 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_F16F32 }, + }, +/* Row Mark */ + { + NULL, + RSC(ISA_SME_B16F32).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_B16F32 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_B16F32 }, + }, + { + NULL, + RSC(ISA_SME_BI32I32).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_BI32I32 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_BI32I32 }, + }, + { + NULL, + RSC(ISA_SME_F32F32).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_F32F32 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_F32F32 }, + }, + { + NULL, + RSC(ISA_SME_SF8FMA).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_SF8FMA }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_SF8FMA }, + }, +/* Row Mark */ + { + NULL, + RSC(ISA_SME_SF8DP4).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_SF8DP4 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_SF8DP4 }, + }, + { + NULL, + RSC(ISA_SME_SF8DP2).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SME_SF8DP2 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SME_SF8DP2 }, + }, + { + NULL, + RSC(ISA_SPECRES).CODE(), RSC(ISA_SPECRES_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.SPECRES }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SPECRES }, + }, + { + NULL, + RSC(ISA_SPECRES2).CODE(), RSC(ISA_SPECRES_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.SPECRES2 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SPECRES2 }, + }, +/* Row Mark */ + { + NULL, + RSC(ISA_SVE).CODE(), RSC(ISA_SVE_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.SVE }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SVE }, + }, + { + NULL, + RSC(ISA_SVE2).CODE(), RSC(ISA_SVE_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.SVE2 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SVE2 }, + }, + { + NULL, + RSC(ISA_SVE_F64MM).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SVE_F64MM }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SVE_F64MM }, + }, + { + NULL, + RSC(ISA_SVE_F32MM).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SVE_F32MM }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SVE_F32MM }, + }, +/* Row Mark */ + { + NULL, + RSC(ISA_SVE_I8MM).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SVE_I8MM }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SVE_I8MM }, + }, + { + NULL, + RSC(ISA_SVE_SM4).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SVE_SM4 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SVE_SM4 }, + }, + { + NULL, + RSC(ISA_SVE_SHA3).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SVE_SHA3 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SVE_SHA3 }, + }, + { + NULL, + RSC(ISA_SVE_BF16).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SVE_BF16 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SVE_BF16 }, + }, +/* Row Mark */ + { + NULL, + RSC(ISA_SVE_EBF16).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SVE_EBF16 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SVE_EBF16 }, + }, + { + NULL, + RSC(ISA_SVE_BitPerm).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SVE_BitPerm }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SVE_BitPerm }, + }, + { + NULL, + RSC(ISA_SVE_AES).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SVE_AES }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SVE_AES }, + }, + { + NULL, + RSC(ISA_SVE_PMULL128).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.SVE_PMULL128 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SVE_PMULL128 }, + }, +/* Row Mark */ + { + NULL, + RSC(ISA_SYSREG128).CODE(), RSC(ISA_SYSREG128_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.SYSREG128 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SYSREG128 }, + }, + { + NULL, + RSC(ISA_SYSINSTR128).CODE(), RSC(ISA_SYSINSTR128_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.SYSINSTR128 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.SYSINSTR128 }, + }, + { + NULL, + RSC(ISA_WFxT).CODE(), RSC(ISA_WFxT_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.WFxT }, + (unsigned short[]) + { RO(Shm)->Proc.Features.WFxT }, + }, + { + NULL, + RSC(ISA_XS).CODE(), RSC(ISA_XS_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.XS }, + (unsigned short[]) + { RO(Shm)->Proc.Features.XS }, + }, + }; + CUINT cells_per_line = win->matrix.size.wth, *nl = &cells_per_line; + + size_t idx; + for (idx = 0; idx < sizeof(ISA) / sizeof(struct ISA_ST); idx++) + { + unsigned short capable = 0; + if (ISA[idx].CRC == NULL) { + capable = 1; + } else { + unsigned int *CRC; + for (CRC = ISA[idx].CRC; (*CRC) != 0 && capable == 0; CRC++) + { + if ( (*CRC) == RO(Shm)->Proc.Features.Info.Vendor.CRC ) { + capable = 1; + } + } + } + if (capable) { + GridHover(PRT(ISA, attrib[ ISA[idx].thm[0] ][ ISA[idx].thm[1] ], + ISA[idx].item, + ISA[idx].cond[0] ? 'Y' : 'N', + ISA[idx].cond[1] ? 'Y' : 'N' ), + (char *)ISA[idx].comm ); + } + } + return reason; +} + +REASON_CODE SysInfoFeatures( Window *win, + CUINT width, + CELL_FUNC OutFunc, + unsigned int *cellPadding ) +{ + REASON_INIT(reason); + ATTRIBUTE *attr_Feat[4] = { + RSC(SYSINFO_FEATURES_COND0).ATTR(), + RSC(SYSINFO_FEATURES_COND1).ATTR(), + RSC(SYSINFO_FEATURES_COND2).ATTR(), + RSC(SYSINFO_FEATURES_COND3).ATTR() + }; + ATTRIBUTE *attr_TSC[3] = { + RSC(SYSINFO_FEATURES_COND0).ATTR(), + RSC(SYSINFO_FEATURES_COND1).ATTR(), + RSC(SYSINFO_FEATURES_COND4).ATTR() + }; + const ASCII *powered[] = { + RSC(MISSING).CODE(), + RSC(PRESENT).CODE() + }; + const ASCII *code_TSC[] = { + RSC(MISSING).CODE(), + RSC(VARIANT).CODE(), + RSC(INVARIANT).CODE() + }; + const ASCII *MECH[] = { + RSC(UNABLE).CODE(), + RSC(PRESENT).CODE(), + RSC(DISABLE).CODE(), + RSC(ENABLE).CODE() + }; + const struct FEAT_ST { + unsigned int *CRC; + const unsigned short cond; + ATTRIBUTE **attrib; + const int tab; + char *item; + const ASCII *code; + const CUINT spaces; + const ASCII **state; + } FEAT[] = \ + { +/* Section Mark */ + { + NULL, + RO(Shm)->Proc.Features.ACPI == 1, + attr_Feat, + 2, "%s%.*sACPI [%7s]", RSC(FEATURES_ACPI).CODE(), + width - 19 - RSZ(FEATURES_ACPI), + NULL + }, + { + NULL, + ( RO(Shm)->Proc.Features.AMU_vers + + RO(Shm)->Proc.Features.AMU_frac ) > 0, + attr_Feat, + 2, RO(Shm)->Proc.Features.AMU_vers ? + RO(Shm)->Proc.Features.AMU_frac ? + "%s v1p1%.*sAMU [%7s]" : "%s v1p0%.*sAMU [%7s]" + : RO(Shm)->Proc.Features.AMU_frac ? + "%s v0p1%.*sAMU [%7s]" : "%s %.*sAMU [%7s]", + RSC(FEATURES_AMU).CODE(), width - 23 - RSZ(FEATURES_AMU), + NULL + }, + { + NULL, + RO(Shm)->Proc.Features.BigEnd_EL0 == 1, + attr_Feat, + 2, "%s EL0%.*sBigEnd [%7s]", RSC(FEATURES_BIG_END).CODE(), + width - 25 - RSZ(FEATURES_BIG_END), + NULL + }, + { + NULL, + RO(Shm)->Proc.Features.BigEnd_EE == 1, + attr_Feat, + 2, "%s EE|E0E%.*sBigEnd [%7s]", RSC(FEATURES_BIG_END).CODE(), + width - 28 - RSZ(FEATURES_BIG_END), + NULL + }, + { + NULL, + RO(Shm)->Proc.Features.EBEP == 1, + attr_Feat, + 2, "%s%.*sEBEP [%7s]", RSC(FEATURES_EBEP).CODE(), + width - 19 - RSZ(FEATURES_EBEP), + NULL + }, + { + NULL, + RO(Shm)->Proc.Features.ECV == 1, + attr_Feat, + 2, "%s%.*sECV [%7s]", RSC(FEATURES_ECV).CODE(), + width - 18 - RSZ(FEATURES_ECV), + NULL + }, + { + NULL, + RO(Shm)->Proc.Features.DF2 == 1, + attr_Feat, + 2, "%s%.*sDF2 [%7s]", RSC(FEATURES_DF2).CODE(), + width - 18 - RSZ(FEATURES_DF2), + NULL + }, + { + NULL, + RO(Shm)->Proc.Features.DIT == 1, + attr_Feat, + 2, "%s%.*sDIT [%7s]", RSC(FEATURES_DIT).CODE(), + width - 18 - RSZ(FEATURES_DIT), + NULL + }, + { + NULL, + RO(Shm)->Proc.Features.ExS == 1, + attr_Feat, + 2, "%s%.*sExS [%7s]", RSC(FEATURES_EXS).CODE(), + width - 18 - RSZ(FEATURES_EXS), + NULL + }, + { + NULL, + RO(Shm)->Proc.Features.FGT == 1, + attr_Feat, + 2, "%s%.*sFGT [%7s]", RSC(FEATURES_FGT).CODE(), + width - 18 - RSZ(FEATURES_FGT), + NULL + }, + { + NULL, + RO(Shm)->Proc.Features.FGT2 == 1, + attr_Feat, + 2, "%s%.*sFGT2 [%7s]", RSC(FEATURES_FGT).CODE(), + width - 19 - RSZ(FEATURES_FGT), + NULL + }, + { + NULL, + RO(Shm)->Proc.Features.PFAR == 1, + attr_Feat, + 2, "%s%.*sPFAR [%7s]", RSC(FEATURES_PFAR).CODE(), + width - 19 - RSZ(FEATURES_PFAR), + NULL + }, + { + NULL, + ( RO(Shm)->Proc.Features.GIC_vers + + RO(Shm)->Proc.Features.GIC_frac ) > 0, + attr_Feat, + 2, RO(Shm)->Proc.Features.GIC_vers ? + RO(Shm)->Proc.Features.GIC_frac ? + "%s v4.1%.*sGIC [%7s]" : "%s v3.0%.*sGIC [%7s]" + : RO(Shm)->Proc.Features.GIC_frac ? + "%s %.*sGIC [%7s]" : "%s %.*sGIC [%7s]", + RSC(FEATURES_GIC).CODE(), width - 23 - RSZ(FEATURES_GIC), + NULL + }, + { + NULL, + ( RO(Shm)->Proc.Features.MPAM_vers + + RO(Shm)->Proc.Features.MPAM_frac ) > 0, + attr_Feat, + 2, RO(Shm)->Proc.Features.MPAM_vers ? + RO(Shm)->Proc.Features.MPAM_frac ? + "%s v1p1%.*sMPAM [%7s]" : "%s v1p0%.*sMPAM [%7s]" + : RO(Shm)->Proc.Features.MPAM_frac ? + "%s v0p1%.*sMPAM [%7s]" : "%s %.*sMPAM [%7s]", + RSC(FEATURES_MPAM).CODE(), width - 24 - RSZ(FEATURES_MPAM), + NULL + }, + { + NULL, + RO(Shm)->Proc.Features.MTE > 0, + attr_Feat, + 2, RO(Shm)->Proc.Features.MTE == 4 ? + "%s v4%.*sMTE [%7s]" + : RO(Shm)->Proc.Features.MTE == 3 ? + "%s v3%.*sMTE [%7s]" + : RO(Shm)->Proc.Features.MTE == 2 ? + "%s v2%.*sMTE [%7s]" + : RO(Shm)->Proc.Features.MTE == 1 ? + "%s v1%.*sMTE [%7s]" : "%s %.*sMTE [%7s]", + RSC(FEATURES_MTE).CODE(), width - 21 - RSZ(FEATURES_MTE), + NULL + }, + { + NULL, + RO(Shm)->Proc.Features.NMI == 1, + attr_Feat, + 2, "%s%.*sNMI [%7s]", RSC(FEATURES_NMI).CODE(), + width - 18 - RSZ(FEATURES_NMI), + NULL + }, + { + NULL, + RO(Shm)->Proc.Features.PARange <= 0b0111, + attr_Feat, + 2, RO(Shm)->Proc.Features.PARange == 0b0000 ? + "%s 32 bits, 4GB %.*sPA [%7s]" + : RO(Shm)->Proc.Features.PARange == 0b0001 ? + "%s 36 bits, 64GB %.*sPA [%7s]" + : RO(Shm)->Proc.Features.PARange == 0b0010 ? + "%s 40 bits, 1TB %.*sPA [%7s]" + : RO(Shm)->Proc.Features.PARange == 0b0011 ? + "%s 42 bits, 4TB %.*sPA [%7s]" + : RO(Shm)->Proc.Features.PARange == 0b0100 ? + "%s 44 bits, 16TB %.*sPA [%7s]" + : RO(Shm)->Proc.Features.PARange == 0b0101 ? + "%s 48 bits, 256TB%.*sPA [%7s]" + : RO(Shm)->Proc.Features.PARange == 0b0110 ? + "%s 52 bits, 4PB %.*sPA [%7s]" + : RO(Shm)->Proc.Features.PARange == 0b0111 ? + "%s 56 bits, 64PB %.*sPA [%7s]" + : "%s %.*sPA [%7s]", + RSC(FEATURES_PA).CODE(), width - 32 - RSZ(FEATURES_PA), + NULL + }, + { + NULL, + RO(Shm)->Proc.Features.PAN == 1, + attr_Feat, + 2, "%s%.*sPAN [%7s]", RSC(FEATURES_PAN).CODE(), + width - 18 - RSZ(FEATURES_PAN), + NULL + }, + { + NULL, + ( RO(Shm)->Proc.Features.RAS + + RO(Shm)->Proc.Features.RAS_frac ) > 0, + attr_Feat, + 2, RO(Shm)->Proc.Features.RAS ? + RO(Shm)->Proc.Features.RAS_frac ? + "%s v1p1%.*sRAS [%7s]" : "%s v1p0%.*sRAS [%7s]" + : RO(Shm)->Proc.Features.RAS_frac ? + "%s v0p1%.*sRAS [%7s]" : "%s %.*sRAS [%7s]", + RSC(FEATURES_RAS).CODE(), width - 23 - RSZ(FEATURES_RAS), + NULL + }, + { + NULL, + RO(Shm)->Proc.Features.TLBIOS == 1, + attr_Feat, + 2, "%s%.*sTLBIOS [%7s]", RSC(FEATURES_TLB).CODE(), + width - 21 - RSZ(FEATURES_TLB), + NULL + }, + { + NULL, + RO(Shm)->Proc.Features.TLBIRANGE == 1, + attr_Feat, + 2, "%s%.*sTLBIRANGE [%7s]", RSC(FEATURES_TLB).CODE(), + width - 24 - RSZ(FEATURES_TLB), + NULL + }, + { + NULL, + RO(Shm)->Proc.Features.TME == 1, + attr_Feat, + 2, "%s%.*sTME [%7s]", RSC(FEATURES_TME).CODE(), + width - 18 - RSZ(FEATURES_TME), + NULL + }, + { + NULL, + RO(Shm)->Proc.Features.InvariantTSC, + attr_TSC, + 2, "%s%.*sTSC [%9s]", RSC(FEATURES_TSC).CODE(), + width - 18 - RSZ(FEATURES_TSC), + code_TSC + }, + { + NULL, + RO(Shm)->Proc.Features.UAO == 1, + attr_Feat, + 2, "%s%.*sUAO [%7s]", RSC(FEATURES_UAO).CODE(), + width - 18 - RSZ(FEATURES_UAO), + NULL + }, + { + NULL, + RO(Shm)->Proc.Features.VARange <= 0b10, + attr_Feat, + 2, RO(Shm)->Proc.Features.VARange == 0b00 ? + "%s 48 bits%.*sVA [%7s]" + : RO(Shm)->Proc.Features.VARange == 0b01 ? + "%s 52 bits%.*sVA [%7s]" + : RO(Shm)->Proc.Features.VARange == 0b10 ? + "%s 56 bits%.*sVA [%7s]" + : "%s *RSVD* %.*sVA [%7s]", + RSC(FEATURES_VA).CODE(), width - 25 - RSZ(FEATURES_VA), + NULL + }, + { + NULL, + RO(Shm)->Proc.Features.VHE == 1, + attr_Feat, + 2, "%s%.*sVHE [%7s]", RSC(FEATURES_VHE).CODE(), + width - 18 - RSZ(FEATURES_VHE), + NULL + }, +/* Section Mark */ + { + NULL, + 0, + attr_Feat, + 0, "%s", RSC(FEAT_SECTION_MECH).CODE(), + 0, + NULL + }, + { + NULL, + RO(Shm)->Proc.Mechanisms.CLRBHB, + attr_Feat, + 2, "%s%.*sCLRBHB [%7s]", RSC(MECH_CLRBHB).CODE(), + width - 21 - RSZ(MECH_CLRBHB), + MECH + }, + { + NULL, + RO(Shm)->Proc.Mechanisms.CSV2 == CSV_NONE ? 0b00 + : RO(Shm)->Proc.Mechanisms.CSV2 == CSV2_1p0 ? 0b11 + : RO(Shm)->Proc.Mechanisms.CSV2 == CSV2_1p1 ? 0b11 + : RO(Shm)->Proc.Mechanisms.CSV2 == CSV2_1p2 ? 0b11 + : RO(Shm)->Proc.Mechanisms.CSV2 == CSV2_2p0 ? 0b11 + : RO(Shm)->Proc.Mechanisms.CSV2 == CSV2_3p0 ? 0b11 : 0b10, + attr_Feat, + 2, RO(Shm)->Proc.Mechanisms.CSV2 == CSV_NONE ? + "%s%.*s NONE [%7s]" + : RO(Shm)->Proc.Mechanisms.CSV2 == CSV2_1p0 ? + "%s%.*sCSV2_1p0 [%7s]" + : RO(Shm)->Proc.Mechanisms.CSV2 == CSV2_1p1 ? + "%s%.*sCSV2_1p1 [%7s]" + : RO(Shm)->Proc.Mechanisms.CSV2 == CSV2_1p2 ? + "%s%.*sCSV2_1p2 [%7s]" + : RO(Shm)->Proc.Mechanisms.CSV2 == CSV2_2p0 ? + "%s%.*sCSV2_2p0 [%7s]" + : RO(Shm)->Proc.Mechanisms.CSV2 == CSV2_3p0 ? + "%s%.*sCSV2_3p0 [%7s]" + /* default: */ + : "%s%.*s UNKNOWN [%7s]", + RSC(MECH_SSBD).CODE(), width - 23 - RSZ(MECH_SSBD), + MECH + }, + { + NULL, + RO(Shm)->Proc.Mechanisms.CSV3, + attr_Feat, + 2, "%s%.*sCSV3 [%7s]", RSC(MECH_SSBD).CODE(), + width - 19 - RSZ(MECH_SSBD), + MECH + }, + { + NULL, + RO(Shm)->Proc.Features.ECBHB == 1, + attr_Feat, + 2, "%s%.*sECBHB [%7s]", RSC(FEATURES_ECBHB).CODE(), + width - 20 - RSZ(FEATURES_ECBHB), + MECH + }, + { + NULL, + RO(Shm)->Proc.Mechanisms.SSBS, + attr_Feat, + 2, "%s%.*sSSBS [%7s]", RSC(MECH_SSBS).CODE(), + width - 19 - RSZ(MECH_SSBS), + MECH + }, +/* Section Mark */ + { + NULL, + 0, + attr_Feat, + 0, "%s", RSC(FEAT_SECTION_SEC).CODE(), + 0, + NULL + }, + { + NULL, + RO(Shm)->Proc.Features.BTI == 1, + attr_Feat, + 2, "%s%.*sBTI [%7s]", RSC(FEATURES_BTI).CODE(), + width - 18 - RSZ(FEATURES_BTI), + NULL + }, + { + NULL, + RO(Shm)->Proc.Features.GCS == 1, + attr_Feat, + 2, "%s%.*sGCS [%7s]", RSC(FEATURES_GCS).CODE(), + width - 18 - RSZ(FEATURES_GCS), + NULL + }, + { + NULL, + RO(Shm)->Proc.Features.RME == 1, + attr_Feat, + 2, "%s%.*sRME [%7s]", RSC(FEATURES_RME).CODE(), + width - 18 - RSZ(FEATURES_RME), + NULL + }, + { + NULL, + RO(Shm)->Proc.Features.SEL2 == 1, + attr_Feat, + 2, "%s%.*sSEL2 [%7s]", RSC(FEATURES_SEL2).CODE(), + width - 19 - RSZ(FEATURES_SEL2), + NULL + }, + { + NULL, + RO(Shm)->Proc.Features.THE == 1, + attr_Feat, + 2, "%s%.*sTHE [%7s]", RSC(FEATURES_THE).CODE(), + width - 18 - RSZ(FEATURES_THE), + NULL + }, + }; + size_t idx; + for (idx = 0; idx < sizeof(FEAT) / sizeof(struct FEAT_ST); idx++) + { + unsigned short capable = 0; + if (FEAT[idx].CRC == NULL) { + capable = 1; + } else { + unsigned int *CRC; + for (CRC = FEAT[idx].CRC; (*CRC) != 0 && capable == 0; CRC++) + { + if ( (*CRC) == RO(Shm)->Proc.Features.Info.Vendor.CRC ) { + capable = 1; + } + } + } + if (capable) + { + PUT( SCANKEY_NULL, + FEAT[idx].attrib[ FEAT[idx].cond ], + width, FEAT[idx].tab, + FEAT[idx].item, FEAT[idx].code, + FEAT[idx].spaces, hSpace, + (FEAT[idx].state == NULL) ? powered[ FEAT[idx].cond ] + : FEAT[idx].state[ FEAT[idx].cond ] ); + } + } + return reason; +} + +void TechUpdate(TGrid *grid, const int unsigned bix, const signed int pos, + const size_t len, const char *item) +{ + ATTRIBUTE *attrib[2] = { + RSC(SYSINFO_TECH_COND0).ATTR(), + RSC(SYSINFO_TECH_COND1).ATTR() + }; + memcpy(&grid->cell.attr[pos], &attrib[bix][pos], len); + memcpy(&grid->cell.item[pos], item, len); +} + +REASON_CODE SysInfoTech(Window *win, + CUINT width, + CELL_FUNC OutFunc, + unsigned int *cellPadding) +{ + REASON_INIT(reason); + char IOMMU_Version_String[10+1+10+1+1]; + const ASCII *Hypervisor[HYPERVISORS] = { + [HYPERV_NONE] = RSC(TECH_HYPERV_NONE).CODE(), + [BARE_METAL] = RSC(TECH_BARE_METAL).CODE(), + [HYPERV_XEN] = RSC(TECH_HYPERV_XEN).CODE(), + [HYPERV_KVM] = RSC(TECH_HYPERV_KVM).CODE(), + [HYPERV_VBOX] = RSC(TECH_HYPERV_VBOX).CODE(), + [HYPERV_KBOX] = RSC(TECH_HYPERV_KBOX).CODE(), + [HYPERV_VMWARE] = RSC(TECH_HYPERV_VMWARE).CODE(), + [HYPERV_HYPERV] = RSC(TECH_HYPERV_HYPERV).CODE() + }; + ATTRIBUTE *attrib[2] = { + RSC(SYSINFO_TECH_COND0).ATTR(), + RSC(SYSINFO_TECH_COND1).ATTR() + }; + const struct TECH_ST { + unsigned int *CRC; + const unsigned short cond; + const int tab; + char *item; + const ASCII *code, *comm; + const CUINT spaces; + const char *context; + const unsigned long long shortkey; + void (*Update)(struct _Grid*, DATA_TYPE[]); + } TECH[] = \ + { + { + NULL, + 0, + 2, "%s%.*s", + RSC(TECHNOLOGIES_ICU).CODE(), NULL, + width - 3 - RSZ(TECHNOLOGIES_ICU), + NULL, + SCANKEY_NULL, + NULL + }, + { + NULL, + 0, + 2, "%s%.*s", + RSC(TECHNOLOGIES_DCU).CODE(), NULL, + width - 3 - RSZ(TECHNOLOGIES_DCU), + NULL, + SCANKEY_NULL, + NULL + }, + { + NULL, + RO(Shm)->Proc.Features.HyperThreading == 1, + 2, "%s%.*sSMT [%3s]", + RSC(TECHNOLOGIES_SMT).CODE(), NULL, + width - 14 - RSZ(TECHNOLOGIES_SMT), + NULL, + SCANKEY_NULL, + NULL + }, + { + NULL, + RO(Shm)->Proc.Features.Hybrid == 1, + 2, "%s%.*sHYBRID [%3s]", + RSC(TECHNOLOGIES_HYBRID).CODE(), NULL, + width - 17 - RSZ(TECHNOLOGIES_HYBRID), + NULL, + SCANKEY_NULL, + NULL + }, + { + NULL, + RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Query.CStateBaseAddr != 0, + 2, "%s%.*sCCx [%3s]", + RSC(PERF_MON_CORE_CSTATE).CODE(), NULL, + width - 14 - RSZ(PERF_MON_CORE_CSTATE), + NULL, + SCANKEY_NULL, + NULL + }, + { + NULL, + RO(Shm)->Proc.Technology.VM == 1, + 2, "%s%.*sVHE [%3s]", + RSC(TECHNOLOGIES_VM).CODE(), RSC(TECHNOLOGIES_VM_COMM).CODE(), + width - 14 - RSZ(TECHNOLOGIES_VM), + NULL, + SCANKEY_NULL, + NULL + }, + { + NULL, + RO(Shm)->Proc.Technology.IOMMU == 1, + 3, "%s%.*sIOMMU [%3s]", + RSC(TECHNOLOGIES_IOMMU).CODE(), + RSC(TECHNOLOGIES_IOMMU_COMM).CODE(), + width - (OutFunc? 17 : 19) - RSZ(TECHNOLOGIES_IOMMU), + NULL, + SCANKEY_NULL, + NULL + }, + { + NULL, + (StrFormat(IOMMU_Version_String, 10+1+10+1+1, "%d.%d", + RO(Shm)->Proc.Technology.IOMMU_Ver_Major, + RO(Shm)->Proc.Technology.IOMMU_Ver_Minor) > 0) & 0x0, + 3, "%s%.*s"" [%12s]", + RSC(VERSION).CODE(), NULL, + width - (OutFunc? 21 : 23) - RSZ(VERSION), + (RO(Shm)->Proc.Technology.IOMMU_Ver_Major > 0 + || RO(Shm)->Proc.Technology.IOMMU_Ver_Minor > 0) ? + IOMMU_Version_String : (char*) RSC(NOT_AVAILABLE).CODE(), + SCANKEY_NULL, + NULL + }, + { + NULL, + RO(Shm)->Proc.Features.Hyperv == 1, + 3, "%s%.*s""%10s [%3s]", + RSC(TECHNOLOGIES_HYPERV).CODE(), NULL, + width - (OutFunc? 22 : 24) - RSZ(TECHNOLOGIES_HYPERV), + (char*) Hypervisor[RO(Shm)->Proc.HypervisorID], + SCANKEY_NULL, + NULL + }, + { + NULL, + 0, + 3, "%s%.*s"" [%12s]", + RSC(VENDOR_ID).CODE(), NULL, + width - (OutFunc? 21 : 23) - RSZ(VENDOR_ID), + strlen(RO(Shm)->Proc.Features.Info.Hypervisor.ID) > 0 ? + RO(Shm)->Proc.Features.Info.Hypervisor.ID + : (char*) RSC(NOT_AVAILABLE).CODE(), + SCANKEY_NULL, + NULL + } + }; + size_t idx; + for (idx = 0; idx < sizeof(TECH) / sizeof(struct TECH_ST); idx++) + { + unsigned short capable = 0; + if (TECH[idx].CRC == NULL) { + capable = 1; + } else { + unsigned int *CRC; + for (CRC = TECH[idx].CRC; (*CRC) != 0 && capable == 0; CRC++) + { + if ( (*CRC) == RO(Shm)->Proc.Features.Info.Vendor.CRC ) { + capable = 1; + } + } + } + if (capable) + { + TGrid *grid = \ + GridHover(PUT( (TECH[idx].shortkey == SCANKEY_NULL) ? SCANKEY_NULL + : TECH[idx].shortkey, + attrib[ TECH[idx].cond ], + width, TECH[idx].tab, + TECH[idx].item, TECH[idx].code, + TECH[idx].spaces, hSpace, + (TECH[idx].context == NULL) ? ENABLED(TECH[idx].cond) + : TECH[idx].context, + ENABLED(TECH[idx].cond) ), (char *)TECH[idx].comm); + + if (TECH[idx].Update != NULL) + { + GridCall(grid, TECH[idx].Update); + } + } + } + return reason; +} + +void PerfMonUpdate(TGrid *grid, const unsigned int bix, const signed int pos, + const size_t len, const char *item) +{ + ATTRIBUTE *attrib[4] = { + RSC(SYSINFO_PERFMON_COND0).ATTR(), + RSC(SYSINFO_PERFMON_COND1).ATTR(), + RSC(SYSINFO_PERFMON_COND2).ATTR(), + RSC(SYSINFO_PERFMON_COND3).ATTR() + }; + memcpy(&grid->cell.attr[pos], &attrib[bix][pos], len); + memcpy(&grid->cell.item[pos], item, len); +} + +void HWP_Update(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int bix = RO(Shm)->Proc.Features.HWP_Enable == 1; + const signed int pos = grid->cell.length - 5; + UNUSED(data); + + PerfMonUpdate(grid, bix, pos, 3, ENABLED(bix)); +} + +void Refresh_HWP_Cap_Freq(TGrid *grid, DATA_TYPE data[]) +{ + char *item; + ATTRIBUTE *HWP_Cap_Attr[2] = { + RSC(SYSINFO_PERFMON_HWP_CAP_COND0).ATTR(), + RSC(SYSINFO_PERFMON_HWP_CAP_COND1).ATTR() + }; + size_t length; + const unsigned int cpu = data[0].uint[0]; + if (!BITVAL(RO(Shm)->Cpu[cpu].OffLine, OS)) + { + const unsigned int bix = (RO(Shm)->Proc.Features.HWP_Enable == 1) + | (RO(Shm)->Proc.Features.ACPI_CPPC == 1); + + memcpy(grid->cell.attr, HWP_Cap_Attr[bix], grid->cell.length); + + if ((item = malloc(grid->cell.length + 1)) != NULL) + { + CPU_STRUCT *SProc = &RO(Shm)->Cpu[cpu]; + struct FLIP_FLOP *CFlop = &SProc->FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + + double Lowest_MHz = ABS_FREQ_MHz(double, + SProc->PowerThermal.HWP.Capabilities.Lowest, + CFlop->Clock + ), + Efficient_MHz = ABS_FREQ_MHz(double, + SProc->PowerThermal.HWP.Capabilities.Most_Efficient, + CFlop->Clock + ), + Guaranteed_MHz = ABS_FREQ_MHz(double, + SProc->PowerThermal.HWP.Capabilities.Guaranteed, + CFlop->Clock + ), + Highest_MHz = ABS_FREQ_MHz(double, + SProc->PowerThermal.HWP.Capabilities.Highest, + CFlop->Clock + ); + + const unsigned int maxRatio = MAXCLOCK_TO_RATIO(unsigned int, + CFlop->Clock.Hz); + + if (StrLenFormat(length, item, grid->cell.length + 1, + "CPU #%-3u %7.2f (%3u) %7.2f (%3u) %7.2f (%3u) %7.2f (%3u)", + cpu, + SProc->PowerThermal.HWP.Capabilities.Lowest <= maxRatio ? + Lowest_MHz : 0, + SProc->PowerThermal.HWP.Capabilities.Lowest, + SProc->PowerThermal.HWP.Capabilities.Most_Efficient <= maxRatio? + Efficient_MHz : 0, + SProc->PowerThermal.HWP.Capabilities.Most_Efficient, + SProc->PowerThermal.HWP.Capabilities.Guaranteed <= maxRatio ? + Guaranteed_MHz : 0, + SProc->PowerThermal.HWP.Capabilities.Guaranteed, + SProc->PowerThermal.HWP.Capabilities.Highest <= maxRatio ? + Highest_MHz : 0, + SProc->PowerThermal.HWP.Capabilities.Highest) > 0) + { + memcpy(&grid->cell.item[3], item, length); + } + free(item); + } + } else { + memcpy(grid->cell.attr, HWP_Cap_Attr[0], grid->cell.length); + + if ((item = malloc(grid->cell.length + 1)) != NULL) + { + if (StrLenFormat(length, item, grid->cell.length + 1, + "CPU #%-3u%.*s-%.*s-%.*s-%.*s- ", cpu, + 13, hSpace, 14, hSpace, 14, hSpace, 14, hSpace) > 0) + { + memcpy(&grid->cell.item[3], item, length); + } + free(item); + } + } +} + +REASON_CODE SysInfoPerfMon( Window *win, + CUINT width, + CELL_FUNC OutFunc, + unsigned int *cellPadding ) +{ + REASON_INIT(reason); + ATTRIBUTE *attrib[5] = { + RSC(SYSINFO_PERFMON_COND0).ATTR(), + RSC(SYSINFO_PERFMON_COND1).ATTR(), + RSC(SYSINFO_PERFMON_COND2).ATTR(), + RSC(SYSINFO_PERFMON_COND3).ATTR(), + RSC(SYSINFO_PERFMON_COND4).ATTR() + }; + unsigned int bix; +/* Section Mark */ + if (RO(Shm)->Proc.PM_version > 0) + { + PUT( SCANKEY_NULL, attrib[0], width, 2, + "%s%.*s%s [%1u.%1x]", RSC(VERSION).CODE(), + width - 17 - RSZ(VERSION), hSpace, RSC(PERF_LABEL_VER).CODE(), + RO(Shm)->Proc.PM_ext.v, RO(Shm)->Proc.PM_ext.p ); + } else { + PUT( SCANKEY_NULL, attrib[0], width, 2, + "%s%.*s%s [%3s]", RSC(VERSION).CODE(), + width - 17 - RSZ(VERSION), hSpace, + RSC(PERF_LABEL_VER).CODE(), RSC(NOT_AVAILABLE).CODE() ); + } + PUT( SCANKEY_NULL, attrib[0], width, 2, "%s:%.*s%s%.*s%s", + RSC(COUNTERS).CODE(), + 8 + (10 - RSZ(COUNTERS)), hSpace, + RSC(GENERAL_CTRS).CODE(), + width - (54 + RSZ(GENERAL_CTRS)), hSpace, + RSC(FIXED_CTRS).CODE() ); + + if (OutFunc == NULL) { + PUT( SCANKEY_NULL, attrib[0], width, 1, + "%.*s{%3u,%3u,%3u } x%3u %s%.*s%3u x%3u %s", + 11, hSpace, RO(Shm)->Proc.Features.PerfMon.MonCtrs, + RO(Shm)->Proc.Features.AMU.CG0NC, + RO(Shm)->Proc.Features.AMU.CG1NC, + RO(Shm)->Proc.Features.PerfMon.MonWidth, + RSC(PERF_MON_UNIT_BIT).CODE(), + 10, hSpace, RO(Shm)->Proc.Features.PerfMon.FixCtrs, + RO(Shm)->Proc.Features.PerfMon.FixWidth, + RSC(PERF_MON_UNIT_BIT).CODE() ); + } else { + GridHover( PUT( SCANKEY_NULL, attrib[0], width, 0, + "%.*s{%3u,%3u,%3u } x%3u %s%.*s%3u x%3u %s", + 11, hSpace, RO(Shm)->Proc.Features.PerfMon.MonCtrs, + RO(Shm)->Proc.Features.AMU.CG0NC, + RO(Shm)->Proc.Features.AMU.CG1NC, + RO(Shm)->Proc.Features.PerfMon.MonWidth, + RSC(PERF_MON_UNIT_BIT).CODE(), + 4, hSpace, RO(Shm)->Proc.Features.PerfMon.FixCtrs, + RO(Shm)->Proc.Features.PerfMon.FixWidth, + RSC(PERF_MON_UNIT_BIT).CODE() ), + (char *) RSC(PERF_MON_PMC_COMM).CODE() ); + } +/* Section Mark */ + PUT( SCANKEY_NULL, attrib[0], width, 2, + "%s", RSC(PERF_MON_CORE_CSTATE).CODE() ); + + PUT( SCANKEY_NULL, + attrib[ !RO(Shm)->Cpu[ + RO(Shm)->Proc.Service.Core + ].Query.CStateBaseAddr ? 0 : 3 ], + width, 3, + "%s%.*s%s [ 0x%-4X]", RSC(PERF_MON_CSTATE_BAR).CODE(), + width - (OutFunc == NULL ? 21 : 19) + - RSZ(PERF_MON_CSTATE_BAR), hSpace, + RSC(PERF_LABEL_CST_BAR).CODE(), + RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Query.CStateBaseAddr ); +/* Section Mark */ + if (RO(Shm)->Proc.Features.ACPI_CST_CAP) { + PUT( SCANKEY_NULL, attrib[RO(Shm)->Proc.Features.ACPI_CST ? 3 : 0], + width, 2, + "%s%.*s%s [%7u]", RSC(PERF_MON_CST).CODE(), + width - 19 - RSZ(PERF_MON_CST), hSpace, + RSC(PERF_LABEL_CST).CODE(), + RO(Shm)->Proc.Features.ACPI_CST ); + } else { + PUT( SCANKEY_NULL, attrib[0], width, 2, + "%s%.*s%s [%7s]", RSC(PERF_MON_CST).CODE(), + width - 19 - RSZ(PERF_MON_CST), hSpace, + RSC(PERF_LABEL_CST).CODE(), RSC(MISSING).CODE() ); + } +/* Section Mark */ + PUT( SCANKEY_NULL, attrib[0], width, 2, + "%s", RSC(PERF_MON_MONITOR_MWAIT).CODE() ); + + PUT( SCANKEY_NULL, attrib[0], width, 3, "%s:%.*s%s", + RSC(PERF_MON_MWAIT_IDX_CSTATE).CODE(), 04, hSpace, + RSC(PERF_LABEL_MWAIT_IDX).CODE() ); + + PUT( SCANKEY_NULL, attrib[0], width, 3, + "%s:%.*s%2d %2d %2d %2d %2d %2d %2d %2d", + RSC(PERF_MON_MWAIT_SUB_CSTATE).CODE(), + 15 - RSZ(PERF_MON_MWAIT_SUB_CSTATE), hSpace, + RO(Shm)->Proc.Features.MWait.SubCstate_MWAIT0, + RO(Shm)->Proc.Features.MWait.SubCstate_MWAIT1, + RO(Shm)->Proc.Features.MWait.SubCstate_MWAIT2, + RO(Shm)->Proc.Features.MWait.SubCstate_MWAIT3, + RO(Shm)->Proc.Features.MWait.SubCstate_MWAIT4, + RO(Shm)->Proc.Features.MWait.SubCstate_MWAIT5, + RO(Shm)->Proc.Features.MWait.SubCstate_MWAIT6, + RO(Shm)->Proc.Features.MWait.SubCstate_MWAIT7 ); +/* Section Mark */ + bix = RO(Shm)->Proc.Features.PerfMon.CoreCycles == 1 ? 2 : 0; + + PUT( SCANKEY_NULL, attrib[bix], width, 2, + "%s%.*s[%7s]", RSC(PERF_MON_CORE_CYCLE).CODE(), + width - 12 - RSZ(PERF_MON_CORE_CYCLE), hSpace, POWERED(bix) ); + + bix = RO(Shm)->Proc.Features.PerfMon.InstrRetired == 1 ? 2 : 0; + + PUT( SCANKEY_NULL, attrib[bix], width, 2, + "%s%.*s[%7s]", RSC(PERF_MON_INST_RET).CODE(), + width - 12 - RSZ(PERF_MON_INST_RET), hSpace, POWERED(bix) ); +/* Section Mark */ + PUT( SCANKEY_NULL, attrib[RO(Shm)->Proc.Features.ACPI_PCT_CAP ? 3:0], + width, 2, + "%s%.*s%s [%7s]", RSC(PERF_MON_PCT).CODE(), + width - 19 - RSZ(PERF_MON_PCT), hSpace, + RSC(PERF_LABEL_PCT).CODE(), + RO(Shm)->Proc.Features.ACPI_PCT_CAP ? + RO(Shm)->Proc.Features.ACPI_PCT ? RSC(ENABLE).CODE() + : RSC(DISABLE).CODE() + : RSC(MISSING).CODE() ); + + if (RO(Shm)->Proc.Features.ACPI_PSS_CAP) { + PUT( SCANKEY_NULL, attrib[RO(Shm)->Proc.Features.ACPI_PSS ? 3 : 0], + width, 2, + "%s%.*s%s [%7u]", RSC(PERF_MON_PSS).CODE(), + width - 19 - RSZ(PERF_MON_PSS), hSpace, + RSC(PERF_LABEL_PSS).CODE(), + RO(Shm)->Proc.Features.ACPI_PSS ); + } else { + PUT( SCANKEY_NULL, attrib[0], width, 2, + "%s%.*s%s [%7s]", RSC(PERF_MON_PSS).CODE(), + width - 19 - RSZ(PERF_MON_PSS), hSpace, + RSC(PERF_LABEL_PSS).CODE(), RSC(MISSING).CODE() ); + } + if (RO(Shm)->Proc.Features.ACPI_PPC_CAP) { + PUT( SCANKEY_NULL, attrib[3], width, 2, + "%s%.*s%s [%7u]", RSC(PERF_MON_PPC).CODE(), + width - 19 - RSZ(PERF_MON_PPC), hSpace, + RSC(PERF_LABEL_PPC).CODE(), + RO(Shm)->Proc.Features.ACPI_PPC ); + } else { + PUT( SCANKEY_NULL, attrib[0], width, 2, + "%s%.*s%s [%7s]", RSC(PERF_MON_PPC).CODE(), + width - 19 - RSZ(PERF_MON_PPC), hSpace, + RSC(PERF_LABEL_PPC).CODE(), RSC(MISSING).CODE() ); + } + PUT( SCANKEY_NULL, attrib[RO(Shm)->Proc.Features.OSPM_CPC ? 3 : 0], + width, 2, + "%s%.*s%s [%7s]", RSC(PERF_MON_CPC).CODE(), + width - 19 - RSZ(PERF_MON_CPC), hSpace, + RSC(PERF_LABEL_CPC).CODE(), + RO(Shm)->Proc.Features.OSPM_CPC ? RSC(ENABLE).CODE() + : RSC(MISSING).CODE() ); + return reason; +} + +REASON_CODE SysInfoPerfCaps( Window *win, + CUINT width, + CELL_FUNC OutFunc, + unsigned int *cellPadding ) +{ + REASON_INIT(reason); + ATTRIBUTE *attrib[5] = { + RSC(SYSINFO_PERFMON_COND0).ATTR(), + RSC(SYSINFO_PERFMON_COND1).ATTR(), + RSC(SYSINFO_PERFMON_COND2).ATTR(), + RSC(SYSINFO_PERFMON_COND3).ATTR(), + RSC(SYSINFO_PERFMON_COND4).ATTR() + }; + unsigned int bix; + bix = (RO(Shm)->Proc.Features.Power.HWP_Reg == 1) + || (RO(Shm)->Proc.Features.ACPI_CPPC == 1); + if (bix) + { + ATTRIBUTE *HWP_Cap_Attr[2] = { + RSC(SYSINFO_PERFMON_HWP_CAP_COND0).ATTR(), + RSC(SYSINFO_PERFMON_HWP_CAP_COND1).ATTR() + }; + unsigned int cpu; + + bix = RO(Shm)->Proc.Features.HWP_Enable == 1; + if (RO(Shm)->Proc.Features.Power.HWP_Reg == 0) + { + if (RO(Shm)->Proc.Features.ACPI_CPPC == 1) + { + GridHover( PUT( BOXKEY_FMW_CPPC, + attrib[RO(Shm)->Proc.Features.ACPI_CPPC], width, 2, + "%s%.*s%s <%3s>", RSC(PERF_MON_CPPC).CODE(), + width - 19 - RSZ(PERF_MON_CPPC), hSpace, + RSC(PERF_LABEL_CPPC).CODE(), RSC(FMW).CODE() ), + (char *) RSC(PERF_MON_CPPC_COMM).CODE() ); + } + else + { + GridCall( PUT( BOXKEY_HWP, attrib[bix], width, 2, + "%s%.*s%s <%3s>", RSC(PERF_MON_CPPC).CODE(), + width - 19 - RSZ(PERF_MON_CPPC), hSpace, + RSC(PERF_LABEL_CPPC).CODE(), ENABLED(bix) ), + HWP_Update); + } + } else { + GridCall( PUT( BOXKEY_HWP, attrib[bix], width, 2, + "%s%.*s%s <%3s>", RSC(PERF_MON_HWP).CODE(), + width - 18 - RSZ(PERF_MON_HWP), hSpace, + RSC(PERF_LABEL_HWP).CODE(), ENABLED(bix) ), + HWP_Update); + } + PUT( SCANKEY_NULL, attrib[0], width, 3, + "%s %s %s %s %s", + RSC(CAPABILITIES).CODE(), + RSC(LOWEST).CODE(), RSC(EFFICIENT).CODE(), + RSC(GUARANTEED).CODE(), RSC(HIGHEST).CODE()); + + for (cpu = 0; cpu < RO(Shm)->Proc.CPU.Count; cpu++) + if (!BITVAL(RO(Shm)->Cpu[cpu].OffLine, OS)) + { + CPU_STRUCT *SProc = &RO(Shm)->Cpu[cpu]; + struct FLIP_FLOP *CFlop = &SProc->FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + + double Lowest_MHz = ABS_FREQ_MHz(double, + SProc->PowerThermal.HWP.Capabilities.Lowest, + CFlop->Clock + ), + Efficient_MHz = ABS_FREQ_MHz(double, + SProc->PowerThermal.HWP.Capabilities.Most_Efficient, + CFlop->Clock + ), + Guaranteed_MHz = ABS_FREQ_MHz(double, + SProc->PowerThermal.HWP.Capabilities.Guaranteed, + CFlop->Clock + ), + Highest_MHz = ABS_FREQ_MHz(double, + SProc->PowerThermal.HWP.Capabilities.Highest, + CFlop->Clock + ); + + const unsigned int maxRatio = MAXCLOCK_TO_RATIO(unsigned int, + CFlop->Clock.Hz); + + GridCall( + PUT(SCANKEY_NULL, HWP_Cap_Attr[bix], width, 3, + "CPU #%-3u %7.2f (%3u) %7.2f (%3u) %7.2f (%3u) %7.2f (%3u)", + cpu, + SProc->PowerThermal.HWP.Capabilities.Lowest <= maxRatio ? + Lowest_MHz : 0, + SProc->PowerThermal.HWP.Capabilities.Lowest, + SProc->PowerThermal.HWP.Capabilities.Most_Efficient <= maxRatio? + Efficient_MHz : 0, + SProc->PowerThermal.HWP.Capabilities.Most_Efficient, + SProc->PowerThermal.HWP.Capabilities.Guaranteed <= maxRatio ? + Guaranteed_MHz : 0, + SProc->PowerThermal.HWP.Capabilities.Guaranteed, + SProc->PowerThermal.HWP.Capabilities.Highest <= maxRatio ? + Highest_MHz : 0, + SProc->PowerThermal.HWP.Capabilities.Highest), + Refresh_HWP_Cap_Freq, cpu); + } else { + GridCall( + PUT(SCANKEY_NULL, HWP_Cap_Attr[0], width, 3, + "CPU #%-3u%.*s-%.*s-%.*s-%.*s-", cpu, + 13, hSpace, 14, hSpace, 14, hSpace, 14, hSpace), + Refresh_HWP_Cap_Freq, cpu); + } + } + const unsigned int cix = ((RO(Shm)->Proc.Features.HWP_Enable == 1) + || (RO(Shm)->Proc.Features.ACPI_CPPC == 1)); + + PUT( SCANKEY_NULL, attrib[bix], width, 2, + "%s%.*s%s [%3s]", RSC(PERF_MON_HWP).CODE(), + width - 18 - RSZ(PERF_MON_HWP), hSpace, + RSC(PERF_LABEL_HWP).CODE(), ENABLED(cix) ); + + return reason; +} + +void PwrThermalUpdate(TGrid *grid, const unsigned int bix,const signed int pos, + const size_t len, const char *item) +{ + ATTRIBUTE *attrib[7] = { + RSC(SYSINFO_PWR_THERMAL_COND0).ATTR(), + RSC(SYSINFO_PWR_THERMAL_COND1).ATTR(), + RSC(SYSINFO_PWR_THERMAL_COND2).ATTR(), + RSC(SYSINFO_PWR_THERMAL_COND3).ATTR(), + RSC(SYSINFO_PWR_THERMAL_COND4).ATTR(), + RSC(SYSINFO_PWR_THERMAL_COND5).ATTR(), + RSC(SYSINFO_PWR_THERMAL_COND6).ATTR() + }; + memcpy(&grid->cell.attr[pos], &attrib[bix][pos], len); + memcpy(&grid->cell.item[pos], item, len); +} + +void Hint_Update(TGrid *grid, DATA_TYPE data[]) +{ + const signed int pos = grid->cell.length - 9; + char item[10+1]; + + StrFormat(item, 10+1, "%7u", (*data[0].puint)); + memcpy(&grid->cell.item[pos], item, 7); +} + +void TjMax_Update(TGrid *grid, DATA_TYPE data[]) +{ + struct FLIP_FLOP *SFlop = &RO(Shm)->Cpu[ + RO(Shm)->Proc.Service.Core + ].FlipFlop[ + !RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Toggle + ]; + const signed int pos = grid->cell.length - 11; + char item[11+1+11+2+1]; + UNUSED(data); + + if (Setting.fahrCels) { + StrFormat(item, 11+1+11+2+1, "%3d:%3d F", + Cels2Fahr(SFlop->Thermal.Param.Offset[THERMAL_OFFSET_P1]), + Cels2Fahr(SFlop->Thermal.Param.Offset[THERMAL_TARGET])); + } else { + StrFormat(item, 10+1+10+2+1, "%3hu:%3hu C", + SFlop->Thermal.Param.Offset[THERMAL_OFFSET_P1], + SFlop->Thermal.Param.Offset[THERMAL_TARGET]); + } + memcpy(&grid->cell.item[pos], item, 9); +} + +void TDP_State(TGrid *grid, DATA_TYPE data[]) +{ + const enum PWR_DOMAIN pw = (enum PWR_DOMAIN) data[0].sint[0]; + const unsigned int bix = \ + RO(Shm)->Proc.Power.Domain[pw].Feature[PL1].Enable + | RO(Shm)->Proc.Power.Domain[pw].Feature[PL2].Enable; + const signed int pos = grid->cell.length - 9; + + PwrThermalUpdate( grid, bix ? 3 : 1, pos, 7, + (char *)(bix ? RSC(ENABLE).CODE() : RSC(DISABLE).CODE()) ); +} + +void PCT_Update(TGrid *grid, const char *item, const unsigned int cix) +{ + ATTRIBUTE *attrib[7] = { + RSC(SYSINFO_PWR_THERMAL_COND0).ATTR(), + RSC(SYSINFO_PWR_THERMAL_COND1).ATTR(), + RSC(SYSINFO_PWR_THERMAL_COND2).ATTR(), + RSC(SYSINFO_PWR_THERMAL_COND3).ATTR(), + RSC(SYSINFO_PWR_THERMAL_COND4).ATTR(), + RSC(SYSINFO_PWR_THERMAL_COND5).ATTR(), + RSC(SYSINFO_PWR_THERMAL_COND6).ATTR() + }; + const signed int pos = grid->cell.length - 9; + + memcpy(&grid->cell.attr[pos], &attrib[cix][pos], 7); + memcpy(&grid->cell.item[pos], item, 7); +} + +void TDP_Update(TGrid *grid, DATA_TYPE data[]) +{ + char item[7+1]; + UNUSED(data); + + StrFormat(item, 7+1, "%5u W", RO(Shm)->Proc.Power.TDP); + + PCT_Update(grid, item, RO(Shm)->Proc.Power.TDP > 0 ? 5 : 0); +} + +void PWL_Update(TGrid *grid, DATA_TYPE data[]) +{ + const enum PWR_DOMAIN pw = (enum PWR_DOMAIN) data[0].sint[0]; + const enum PWR_LIMIT pl = (enum PWR_LIMIT) data[1].uint[0]; + char item[7+1]; + StrFormat(item, 7+1, "%5u W", RO(Shm)->Proc.Power.Domain[pw].PWL[pl]); + + PCT_Update( grid, item, RO(Shm)->Proc.Power.Domain[pw].PWL[pl] > 0 ? + RO(Shm)->Proc.Power.Domain[pw].Feature[pl].Enable ? + 3 : 5 : 0 ); +} + +char *FormatTime(const size_t fsz, char *str, const double fTime) +{ + if (fTime >= 1.0) { + unsigned long long iTime, rTime; + if (fTime >= 36000.0) { + iTime = fTime / 86400LLU; + rTime = fTime - (iTime * 86400LLU); + rTime = (100LLU * rTime) / 86400LLU; + StrFormat(str, fsz, "%2llu.%02llu d", iTime, rTime); + } else if (fTime >= 60.0) { + unsigned long long hTW = fTime / 3600LLU, mTime; + iTime = fTime / 60LLU; + rTime = fTime - (iTime * 60LLU); + mTime = (fTime - (hTW * 3600LLU)) / 60LLU; + if (hTW) { + StrFormat(str, fsz, "%1lluh%02llum%02llu", hTW, mTime, rTime); + } else if (rTime) { + StrFormat(str, fsz, " %2llum%02llus", mTime, rTime); + } else { + StrFormat(str, fsz, " %2llu m", mTime); + } + } else { + iTime = fTime; + rTime = (100LLU * fTime) - (100LLU * iTime); + if (rTime) { + StrFormat(str, fsz, "%2llu.%02llu s", iTime, rTime); + } else { + StrFormat(str, fsz, " %2llu s", iTime); + } + } + } else { + unsigned long long iTime; + char unit; + if (fTime < 0.000001) { + iTime = 1000LLU * 1000LLU * 1000LLU * fTime; + unit = 'n'; + } else if (fTime < 0.001) { + iTime = 1000LLU * 1000LLU * fTime; + unit = 'u'; + } else { + iTime = 1000LLU * fTime; + unit = 'm'; + } + StrFormat(str, fsz, "%4llu %cs", iTime, unit); + } + return str; +} + +void TAU_Update(TGrid *grid, DATA_TYPE data[]) +{ + const enum PWR_DOMAIN pw = (enum PWR_DOMAIN) data[0].sint[0]; + const enum PWR_LIMIT pl = (enum PWR_LIMIT) data[1].uint[0]; + + char *item = malloc(64); + if (item != NULL) { + PCT_Update(grid, + FormatTime(64, item, RO(Shm)->Proc.Power.Domain[pw].TAU[pl]), + RO(Shm)->Proc.Power.Domain[pw].TAU[pl] > 0 ? + RO(Shm)->Proc.Power.Domain[pw].Feature[pl].Enable ? 3 : 5 : 0); + + free(item); + } +} + +void TDC_Update(TGrid *grid, DATA_TYPE data[]) +{ + char item[7+1]; + UNUSED(data); + + StrFormat(item, 7+1, "%5u A", RO(Shm)->Proc.Power.TDC); + + PCT_Update(grid, item, RO(Shm)->Proc.Power.TDC > 0 ? + RO(Shm)->Proc.Power.Feature.TDC ? 3 : 5 : 0); +} + +REASON_CODE SysInfoPwrThermal( Window *win, + CUINT width, + CELL_FUNC OutFunc, + unsigned int *cellPadding ) +{ + REASON_INIT(reason); + ATTRIBUTE *attrib[7] = { + RSC(SYSINFO_PWR_THERMAL_COND0).ATTR(), + RSC(SYSINFO_PWR_THERMAL_COND1).ATTR(), + RSC(SYSINFO_PWR_THERMAL_COND2).ATTR(), + RSC(SYSINFO_PWR_THERMAL_COND3).ATTR(), + RSC(SYSINFO_PWR_THERMAL_COND4).ATTR(), + RSC(SYSINFO_PWR_THERMAL_COND5).ATTR(), + RSC(SYSINFO_PWR_THERMAL_COND6).ATTR() + }; + struct FLIP_FLOP *SFlop = &RO(Shm)->Cpu[ + RO(Shm)->Proc.Service.Core + ].FlipFlop[ + !RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Toggle + ]; + unsigned int bix; +/* Section Mark */ + GridCall( PUT( BOXKEY_THM, + attrib[6], width, 2, + "%s%.*s%s %c%3u:%3u %c%c", + RSC(POWER_THERMAL_TJMAX).CODE(), + width - 20 - RSZ(POWER_THERMAL_TJMAX), hSpace, + RSC(POWER_LABEL_TJ).CODE(), + '<', + Setting.fahrCels ? Cels2Fahr( + SFlop->Thermal.Param.Offset[THERMAL_OFFSET_P1] + ) : SFlop->Thermal.Param.Offset[THERMAL_OFFSET_P1], + Setting.fahrCels ? Cels2Fahr( + SFlop->Thermal.Param.Offset[THERMAL_TARGET] + ) : SFlop->Thermal.Param.Offset[THERMAL_TARGET], + Setting.fahrCels ? 'F' : 'C', + '>'), + TjMax_Update ); +/* Section Mark */ +/* Row Mark */ + bix = (RO(Shm)->Proc.Features.HWP_Enable == 1) + || (RO(Shm)->Proc.Features.OSPM_EPP == 1); + if (bix) { + GridCall( PUT( BOXKEY_HWP_EPP, attrib[0], width, 2, + "%s%.*s%s <%7u>", RSC(POWER_THERMAL_CPPC).CODE(), + width - 18 - RSZ(POWER_THERMAL_CPPC), hSpace, + RSC(POWER_LABEL_CPPC).CODE(), + RO(Shm)->Cpu[ + RO(Shm)->Proc.Service.Core + ].PowerThermal.HWP.Request.Energy_Pref ), + Hint_Update, + &RO(Shm)->Cpu[ + RO(Shm)->Proc.Service.Core + ].PowerThermal.HWP.Request.Energy_Pref ); + } +/* Row Mark */ + bix = RO(Shm)->Proc.Features.Power.DTS == 1; + + PUT( SCANKEY_NULL, attrib[bix], width, 2, + "%s%.*s%s [%7s]", RSC(POWER_THERMAL_DTS).CODE(), + width - 18 - RSZ(POWER_THERMAL_DTS), hSpace, + RSC(POWER_LABEL_DTS).CODE(), POWERED(bix) ); +/* Row Mark */ + bix = RO(Shm)->Proc.Features.Power.PLN == 1; + + PUT( SCANKEY_NULL, attrib[bix], width, 2, + "%s%.*s%s [%7s]", RSC(POWER_THERMAL_PLN).CODE(), + width - 18 - RSZ(POWER_THERMAL_PLN), hSpace, + RSC(POWER_LABEL_PLN).CODE(), POWERED(bix) ); +/* Row Mark */ + bix = RO(Shm)->Proc.Features.Power.PTM == 1; + + PUT( SCANKEY_NULL, attrib[bix], width, 2, + "%s%.*s%s [%7s]", RSC(POWER_THERMAL_PTM).CODE(), + width - 18 - RSZ(POWER_THERMAL_PTM), hSpace, + RSC(POWER_LABEL_PTM).CODE(), POWERED(bix) ); +/* Section Mark */ + if (RO(Shm)->Proc.Power.TDP > 0) { + GridCall( PUT( SCANKEY_NULL, attrib[5], width, 2, + "%s%.*s%s [%5u W]", RSC(POWER_THERMAL_TDP).CODE(), + width - 18 - RSZ(POWER_THERMAL_TDP), hSpace, + RSC(POWER_LABEL_TDP).CODE(), RO(Shm)->Proc.Power.TDP ), + TDP_Update ); + } else { + PUT( SCANKEY_NULL, attrib[0], width, 2, + "%s%.*s%s [%7s]", RSC(POWER_THERMAL_TDP).CODE(), + width - 18 - RSZ(POWER_THERMAL_TDP), hSpace, + RSC(POWER_LABEL_TDP).CODE(), POWERED(0) ); + } +/* Section Mark */ + if (RO(Shm)->Proc.Power.Min > 0) { + PUT( SCANKEY_NULL, attrib[5], width, 3, + "%s%.*s%s [%5u W]", RSC(POWER_THERMAL_MIN).CODE(), + width - (OutFunc == NULL ? 21 : 19) + - RSZ(POWER_THERMAL_MIN), hSpace, + RSC(POWER_LABEL_MIN).CODE(), RO(Shm)->Proc.Power.Min ); + } else { + PUT( SCANKEY_NULL, attrib[0], width, 3, + "%s%.*s%s [%7s]", RSC(POWER_THERMAL_MIN).CODE(), + width - (OutFunc == NULL ? 21 : 19) + - RSZ(POWER_THERMAL_MIN), hSpace, + RSC(POWER_LABEL_MIN).CODE(), POWERED(0) ); + } +/* Section Mark */ + if (RO(Shm)->Proc.Power.Max > 0) { + PUT( SCANKEY_NULL, attrib[5], width, 3, + "%s%.*s%s [%5u W]", RSC(POWER_THERMAL_MAX).CODE(), + width - (OutFunc == NULL ? 21 : 19) + - RSZ(POWER_THERMAL_MAX), hSpace, + RSC(POWER_LABEL_MAX).CODE(), RO(Shm)->Proc.Power.Max ); + } else { + PUT( SCANKEY_NULL, attrib[0], width, 3, + "%s%.*s%s [%7s]", RSC(POWER_THERMAL_MAX).CODE(), + width - (OutFunc == NULL ? 21 : 19) + - RSZ(POWER_THERMAL_MAX), hSpace, + RSC(POWER_LABEL_MAX).CODE(), POWERED(0) ); + } +/* Section Mark */ + struct { + const ASCII *code; + const int size; + } label[] = { + {RSC(POWER_LABEL_PKG).CODE() , RSZ(POWER_LABEL_PKG)}, + {RSC(POWER_LABEL_CORE).CODE() , RSZ(POWER_LABEL_CORE)}, + {RSC(POWER_LABEL_UNCORE).CODE() , RSZ(POWER_LABEL_UNCORE)}, + {RSC(POWER_LABEL_DRAM).CODE() , RSZ(POWER_LABEL_DRAM)}, + {RSC(POWER_LABEL_PLATFORM).CODE(),RSZ(POWER_LABEL_PLATFORM)} + }; + enum PWR_DOMAIN pw; + for (pw = PWR_DOMAIN(PKG); pw < PWR_DOMAIN(SIZE); pw++) + { + char item[7+1]; + unsigned int cix; + + GridCall( + PUT(RO(Shm)->Proc.Power.Domain[pw].Feature[PL1].Unlock ? + (BOXKEY_TDP_OR | (pw << 5) | PL1) : SCANKEY_NULL, + attrib[ + RO(Shm)->Proc.Power.Domain[pw].Feature[PL1].Enable ? 3:1 + ], + width, 2, + "%s%.*s%s %c%7s%c", + RSC(POWER_THERMAL_TDP).CODE(), + width - 15 - RSZ(POWER_THERMAL_TDP) - label[pw].size, + hSpace, + label[pw].code, + RO(Shm)->Proc.Power.Domain[pw].Feature[PL1].Unlock ? '<' : '[', + RO(Shm)->Proc.Power.Domain[pw].Feature[PL1].Enable ? + RSC(ENABLE).CODE() : RSC(DISABLE).CODE(), + RO(Shm)->Proc.Power.Domain[pw].Feature[PL1].Unlock ? '>' : ']'), + TDP_State, pw ); + + cix = RO(Shm)->Proc.Power.Domain[pw].PWL[PL1] > 0 ? + RO(Shm)->Proc.Power.Domain[pw].Feature[PL1].Enable ? 3 : 5 : 0; + + GridCall( + PUT(RO(Shm)->Proc.Power.Domain[pw].Feature[PL1].Unlock ? + (BOXKEY_TDP_OR | (pw << 5) | PL1) : SCANKEY_NULL, + attrib[cix], + width, 3, + "%s%.*s%s %c%5u W%c", + RSC(POWER_THERMAL_TPL).CODE(), + width - (OutFunc == NULL ? 21 : 19) - RSZ(POWER_THERMAL_TPL), + hSpace, + RSC(POWER_LABEL_PL1).CODE(), + RO(Shm)->Proc.Power.Domain[pw].Feature[PL1].Unlock ? '<' : '[', + RO(Shm)->Proc.Power.Domain[pw].PWL[PL1], + RO(Shm)->Proc.Power.Domain[pw].Feature[PL1].Unlock ? '>' : ']'), + PWL_Update, pw, PL1 ); + + cix = RO(Shm)->Proc.Power.Domain[pw].TAU[PL1] > 0 ? + RO(Shm)->Proc.Power.Domain[pw].Feature[PL1].Enable ? 3 : 5 : 0; + + GridCall( + PUT(RO(Shm)->Proc.Power.Domain[pw].Feature[PL1].Unlock ? + (BOXKEY_TW_OR | (pw << 5) | PL1) : SCANKEY_NULL, + attrib[cix], + width, 3, + "%s%.*s%s %c%s%c", + RSC(POWER_THERMAL_TW).CODE(), + width - (OutFunc == NULL ? 21 : 19) - RSZ(POWER_THERMAL_TW), + hSpace, + RSC(POWER_LABEL_TW1).CODE(), + RO(Shm)->Proc.Power.Domain[pw].Feature[PL1].Unlock ? '<' : '[', + FormatTime(7+1, item, RO(Shm)->Proc.Power.Domain[pw].TAU[PL1]), + RO(Shm)->Proc.Power.Domain[pw].Feature[PL1].Unlock ? '>' : ']'), + TAU_Update, pw, PL1 ); + + if (pw == PWR_DOMAIN(PKG) || pw == PWR_DOMAIN(PLATFORM)) + { + cix = RO(Shm)->Proc.Power.Domain[pw].PWL[PL2] > 0 ? + RO(Shm)->Proc.Power.Domain[pw].Feature[PL2].Enable ? 3 : 5 : 0; + + GridCall( + PUT(RO(Shm)->Proc.Power.Domain[pw].Feature[PL2].Unlock ? + (BOXKEY_TDP_OR | (pw << 5) | PL2) : SCANKEY_NULL, + attrib[cix], + width, 3, + "%s%.*s%s %c%5u W%c", + RSC(POWER_THERMAL_TPL).CODE(), + width - (OutFunc == NULL ? 21 : 19) - RSZ(POWER_THERMAL_TPL), + hSpace, + RSC(POWER_LABEL_PL2).CODE(), + RO(Shm)->Proc.Power.Domain[pw].Feature[PL2].Unlock ? '<' : '[', + RO(Shm)->Proc.Power.Domain[pw].PWL[PL2], + RO(Shm)->Proc.Power.Domain[pw].Feature[PL2].Unlock ? '>' : ']'), + PWL_Update, pw, PL2 ); + + cix = RO(Shm)->Proc.Power.Domain[pw].TAU[PL2] > 0 ? + RO(Shm)->Proc.Power.Domain[pw].Feature[PL2].Enable ? 3 : 5 : 0; + + GridCall( + PUT(RO(Shm)->Proc.Power.Domain[pw].Feature[PL2].Unlock ? + (BOXKEY_TW_OR | (pw << 5) | PL2) : SCANKEY_NULL, + attrib[cix], + width, 3, + "%s%.*s%s %c%s%c", + RSC(POWER_THERMAL_TW).CODE(), + width - (OutFunc == NULL ? 21 : 19) - RSZ(POWER_THERMAL_TW), + hSpace, + RSC(POWER_LABEL_TW2).CODE(), + RO(Shm)->Proc.Power.Domain[pw].Feature[PL2].Unlock ? '<' : '[', + FormatTime(7+1, item, RO(Shm)->Proc.Power.Domain[pw].TAU[PL2]), + RO(Shm)->Proc.Power.Domain[pw].Feature[PL2].Unlock ? '>' : ']'), + TAU_Update, pw, PL2 ); + } + } +/* Section Mark */ +/* Row Mark */ + if (RO(Shm)->Proc.Power.EDC > 0) { + PUT( SCANKEY_NULL, attrib[5], width, 2, + "%s%.*s%s [%5u A]", RSC(POWER_THERMAL_EDC).CODE(), + width - 18 - RSZ(POWER_THERMAL_EDC), hSpace, + RSC(POWER_LABEL_EDC).CODE(), RO(Shm)->Proc.Power.EDC ); + } else { + PUT( SCANKEY_NULL, attrib[0], width, 2, + "%s%.*s%s [%7s]", RSC(POWER_THERMAL_EDC).CODE(), + width - 18 - RSZ(POWER_THERMAL_EDC), hSpace, + RSC(POWER_LABEL_EDC).CODE(), POWERED(0) ); + } +/* Row Mark */ + if (RO(Shm)->Proc.Power.TDC > 0) { + bix = RO(Shm)->Proc.Features.TDP_Unlock; + + GridCall( PUT( bix ? BOXKEY_TDC : SCANKEY_NULL, + attrib[ RO(Shm)->Proc.Power.Feature.TDC ? 3 : 5 ], + width, 2, + "%s%.*s%s %c%5u A%c", RSC(POWER_THERMAL_TDC).CODE(), + width - 18 - RSZ(POWER_THERMAL_TDC), hSpace, + RSC(POWER_LABEL_TDC).CODE(), + bix ? '<' : '[', + RO(Shm)->Proc.Power.TDC, + bix ? '>' : ']' ), + TDC_Update ); + } else { + PUT( SCANKEY_NULL, attrib[0], width, 2, + "%s%.*s%s [%7s]", RSC(POWER_THERMAL_TDC).CODE(), + width - 18 - RSZ(POWER_THERMAL_TDC), hSpace, + RSC(POWER_LABEL_TDC).CODE(), POWERED(0) ); + } +/* Section Mark */ + struct { + const ASCII *code; + const int size; + } thmPt[THM_POINTS_DIM] = { + [THM_THRESHOLD_1] = { + RSC(THERMAL_POINT_THRESHOLD_1).CODE(), + RSZ(THERMAL_POINT_THRESHOLD_1) + }, + [THM_THRESHOLD_2] = { + RSC(THERMAL_POINT_THRESHOLD_2).CODE(), + RSZ(THERMAL_POINT_THRESHOLD_2) + }, + [THM_TRIP_LIMIT] = { + RSC(THERMAL_POINT_TRIP_LIMIT).CODE(), + RSZ(THERMAL_POINT_TRIP_LIMIT) + }, + [THM_HTC_LIMIT] = { + RSC(THERMAL_POINT_HTC_LIMIT).CODE(), + RSZ(THERMAL_POINT_HTC_LIMIT) + }, + [THM_HTC_HYST] = { + RSC(THERMAL_POINT_HTC_HYST).CODE(), + RSZ(THERMAL_POINT_HTC_HYST) + }, + }; + + PUT( SCANKEY_NULL, attrib[0], width, 2, "%s %s", + RSC(POWER_LABEL_CORE).CODE(), RSC(POWER_THERMAL_POINT).CODE() ); + + enum THM_POINTS tp; + for (tp = THM_THRESHOLD_1; tp < THM_POINTS_DIM; tp++) + { + if (BITVAL(RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].ThermalPoint.Mask, tp)) + { + ASCII *code; + int size; + if (BITVAL(RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].ThermalPoint.Kind, tp)) + { + code = RSC(THERMAL_POINT_LIMIT).CODE(); + size = RSZ(THERMAL_POINT_LIMIT); + } else { + code = RSC(THERMAL_POINT_THRESHOLD).CODE(); + size = RSZ(THERMAL_POINT_THRESHOLD); + } + if (BITVAL(RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].ThermalPoint.State, tp)) + { + PUT( SCANKEY_NULL, attrib[5], width, 3, + "%s%.*s%s [%5u %c]", + thmPt[tp].code, + width - (OutFunc == NULL ? 18 : 16) - thmPt[tp].size - size, + hSpace, code, + Setting.fahrCels ? Cels2Fahr(RO(Shm)->Cpu[ + RO(Shm)->Proc.Service.Core + ].ThermalPoint.Value[tp]) + : RO(Shm)->Cpu[ + RO(Shm)->Proc.Service.Core + ].ThermalPoint.Value[tp], + Setting.fahrCels ? 'F' : 'C'); + } else { + PUT( SCANKEY_NULL, attrib[0], width, 3, + "%s%.*s%s [%7s]", + thmPt[tp].code, + width - (OutFunc == NULL ? 18 : 16) - thmPt[tp].size - size, + hSpace, code, POWERED(0) ); + } + } + } +/* Section Mark */ + PUT( SCANKEY_NULL, attrib[0], width, 2, "%s %s", + RSC(POWER_LABEL_PKG).CODE(), RSC(POWER_THERMAL_POINT).CODE() ); + + for (tp = THM_THRESHOLD_1; tp < THM_POINTS_DIM; tp++) + { + if (BITVAL(RO(Shm)->Proc.ThermalPoint.Mask, tp)) + { + ASCII *code; + int size; + if (BITVAL(RO(Shm)->Proc.ThermalPoint.Kind, tp)) { + code = RSC(THERMAL_POINT_LIMIT).CODE(); + size = RSZ(THERMAL_POINT_LIMIT); + } else { + code = RSC(THERMAL_POINT_THRESHOLD).CODE(); + size = RSZ(THERMAL_POINT_THRESHOLD); + } + if (BITVAL(RO(Shm)->Proc.ThermalPoint.State, tp)) + { + PUT( SCANKEY_NULL, attrib[5], width, 3, + "%s%.*s%s [%5u %c]", + thmPt[tp].code, + width - (OutFunc == NULL ? 18 : 16) - thmPt[tp].size - size, + hSpace, code, + Setting.fahrCels ? + Cels2Fahr(RO(Shm)->Proc.ThermalPoint.Value[tp]) + : RO(Shm)->Proc.ThermalPoint.Value[tp], + Setting.fahrCels ? 'F' : 'C'); + } else { + PUT( SCANKEY_NULL, attrib[0], width, 3, + "%s%.*s%s [%7s]", + thmPt[tp].code, + width - (OutFunc == NULL ? 18 : 16) - thmPt[tp].size - size, + hSpace, code, POWERED(0) ); + } + } + } +/* Section Mark */ + PUT( SCANKEY_NULL, attrib[0], width, 2, + (char*) RSC(POWER_THERMAL_UNITS).CODE(), NULL ); + + if (RO(Shm)->Proc.Power.Unit.Watts > 0.0) { + PUT( SCANKEY_NULL, attrib[0], width, 3, + "%s%.*s%s [%13.9f]", + RSC(POWER_THERMAL_POWER).CODE(), + width - (OutFunc == NULL ? 24 : 22) + - RSZ(POWER_THERMAL_POWER) - RSZ(POWER_THERMAL_WATT), hSpace, + RSC(POWER_THERMAL_WATT).CODE(), + RO(Shm)->Proc.Power.Unit.Watts ); + } else { + PUT( SCANKEY_NULL, attrib[0], width, 3, + "%s%.*s%s [%13s]", + RSC(POWER_THERMAL_POWER).CODE(), + width - (OutFunc == NULL ? 24 : 22) + - RSZ(POWER_THERMAL_POWER) - RSZ(POWER_THERMAL_WATT), hSpace, + RSC(POWER_THERMAL_WATT).CODE(), POWERED(0) ); + } +/* Row Mark */ + if (RO(Shm)->Proc.Power.Unit.Joules > 0.0) { + PUT( SCANKEY_NULL, attrib[0], width, 3, + "%s%.*s%s [%13.9f]", RSC(POWER_THERMAL_ENERGY).CODE(), + width - (OutFunc == NULL ? 24 : 22) + - RSZ(POWER_THERMAL_ENERGY) - RSZ(POWER_THERMAL_JOULE), hSpace, + RSC(POWER_THERMAL_JOULE).CODE(), + RO(Shm)->Proc.Power.Unit.Joules ); + } else { + PUT( SCANKEY_NULL, attrib[0], width, 3, + "%s%.*s%s [%13s]", RSC(POWER_THERMAL_ENERGY).CODE(), + width - (OutFunc == NULL ? 24 : 22) + - RSZ(POWER_THERMAL_ENERGY) - RSZ(POWER_THERMAL_JOULE), hSpace, + RSC(POWER_THERMAL_JOULE).CODE(), POWERED(0) ); + } +/* Row Mark */ + if (RO(Shm)->Proc.Power.Unit.Times > 0.0) { + PUT( SCANKEY_NULL, attrib[0], width, 3, + "%s%.*s%s [%13.9f]", RSC(POWER_THERMAL_WINDOW).CODE(), + width - (OutFunc == NULL ? 24 : 22) + - RSZ(POWER_THERMAL_WINDOW) - RSZ(POWER_THERMAL_SECOND), hSpace, + RSC(POWER_THERMAL_SECOND).CODE(), + RO(Shm)->Proc.Power.Unit.Times ); + } else { + PUT( SCANKEY_NULL, attrib[0], width, 3, + "%s%.*s%s [%13s]", RSC(POWER_THERMAL_WINDOW).CODE(), + width - (OutFunc == NULL ? 24 : 22) + - RSZ(POWER_THERMAL_WINDOW) - RSZ(POWER_THERMAL_SECOND), hSpace, + RSC(POWER_THERMAL_SECOND).CODE(), POWERED(0) ); + } + return reason; +} + +void Kernel_RAM_Update(TGrid *grid, DATA_TYPE data[]) +{ + char item[20+3+1]; + size_t len; + + StrLenFormat(len, item, 20+3+1, "%18lu KB", (*data[0].pulong)); + + memcpy(&grid->cell.item[grid->cell.length - len - 1], item, len); +} + +void Kernel_ClockSource_Update(TGrid *grid, DATA_TYPE data[]) +{ + char item[CPUFREQ_NAME_LEN+1]; + size_t fmtLen; + const signed int len = KMIN(strlen(RO(Shm)->CS.array),CPUFREQ_NAME_LEN); + UNUSED(data); + + if (len > 0) { + StrLenFormat( fmtLen, item, CPUFREQ_NAME_LEN+1, "%.*s""%-.*s", + CPUFREQ_NAME_LEN - len, hSpace, + len, RO(Shm)->CS.array ); + } else { + StrLenFormat( fmtLen, item, CPUFREQ_NAME_LEN+1, "%.*s""%-.*s", + CPUFREQ_NAME_LEN - RSZ(MISSING), hSpace, + CPUFREQ_NAME_LEN, RSC(MISSING).CODE() ); + } + memcpy(&grid->cell.item[grid->cell.length - fmtLen - 2], item, fmtLen); +} + +void Kernel_CPU_Freq_Update(TGrid *grid, DATA_TYPE data[]) +{ + char item[CPUFREQ_NAME_LEN+1]; + size_t fmtLen; + const signed int len = \ + KMIN(strlen(RO(Shm)->SysGate.OS.FreqDriver.Name), CPUFREQ_NAME_LEN); + UNUSED(data); + + if (len > 0) { + StrLenFormat( fmtLen, item, CPUFREQ_NAME_LEN+1, "%.*s""%-.*s", + CPUFREQ_NAME_LEN - len, hSpace, + len, RO(Shm)->SysGate.OS.FreqDriver.Name ); + } else { + StrLenFormat( fmtLen, item, CPUFREQ_NAME_LEN+1, "%.*s""%-.*s", + CPUFREQ_NAME_LEN - RSZ(MISSING), hSpace, + CPUFREQ_NAME_LEN, RSC(MISSING).CODE() ); + } + memcpy(&grid->cell.item[grid->cell.length - fmtLen - 2], item, fmtLen); +} + +void Kernel_Governor_Update(TGrid *grid, DATA_TYPE data[]) +{ + char item[CPUFREQ_NAME_LEN+1]; + size_t fmtLen; + const signed int len = \ + KMIN(strlen(RO(Shm)->SysGate.OS.FreqDriver.Governor), CPUFREQ_NAME_LEN); + UNUSED(data); + + if (len > 0) { + StrLenFormat( fmtLen, item, CPUFREQ_NAME_LEN+1, "%.*s""%-.*s", + CPUFREQ_NAME_LEN - len, hSpace, + len, RO(Shm)->SysGate.OS.FreqDriver.Governor ); + } else { + StrLenFormat( fmtLen, item, CPUFREQ_NAME_LEN+1, "%.*s""%-.*s", + CPUFREQ_NAME_LEN - RSZ(MISSING), hSpace, + CPUFREQ_NAME_LEN, RSC(MISSING).CODE() ); + } + memcpy(&grid->cell.item[grid->cell.length - fmtLen - 2], item, fmtLen); +} + +void Kernel_CPU_Idle_Update(TGrid *grid, DATA_TYPE data[]) +{ + char item[CPUIDLE_NAME_LEN+1]; + size_t fmtLen; + signed int len = \ + KMIN(strlen(RO(Shm)->SysGate.OS.IdleDriver.Name), CPUIDLE_NAME_LEN); + UNUSED(data); + + if (len > 0) { + StrLenFormat( fmtLen, item, CPUIDLE_NAME_LEN+1, "%.*s""%-.*s", + CPUIDLE_NAME_LEN - len, hSpace, + len, RO(Shm)->SysGate.OS.IdleDriver.Name ); + } else { + StrLenFormat( fmtLen, item, CPUIDLE_NAME_LEN+1, "%.*s""%-.*s", + CPUIDLE_NAME_LEN - RSZ(MISSING), hSpace, + CPUIDLE_NAME_LEN, RSC(MISSING).CODE() ); + } + memcpy(&grid->cell.item[grid->cell.length - fmtLen - 2], item, fmtLen); +} + +void Kernel_IdleLimit_Update(TGrid *grid, DATA_TYPE data[]) +{ + char item[CPUIDLE_NAME_LEN+1]; + size_t len; + signed int idx = (*data[0].psint) - 1; + + if (RO(Shm)->SysGate.OS.IdleDriver.stateCount > 0) + { + StrLenFormat(len, item, CPUIDLE_NAME_LEN + 1, + COREFREQ_FORMAT_STR(CPUIDLE_NAME_LEN), + RO(Shm)->SysGate.OS.IdleDriver.State[idx].Name); + } + else + { + StrLenFormat(len, item, CPUIDLE_NAME_LEN + 1, + COREFREQ_FORMAT_STR(CPUIDLE_NAME_LEN), + RSC(NOT_AVAILABLE).CODE()); + } + memcpy(&grid->cell.item[grid->cell.length - len - 2], item, len); + + grid->cell.item[grid->cell.length - 2] = \ + RO(Shm)->Registration.Driver.CPUidle & REGISTRATION_ENABLE ? + '>' : ']'; + + grid->cell.item[grid->cell.length - 3 - CPUIDLE_NAME_LEN] = \ + RO(Shm)->Registration.Driver.CPUidle & REGISTRATION_ENABLE ? + '<' : '['; + + grid->cell.quick.key = \ + RO(Shm)->Registration.Driver.CPUidle & REGISTRATION_ENABLE ? + BOXKEY_LIMIT_IDLE_STATE : SCANKEY_NULL; +} + +REASON_CODE SysInfoKernel(Window *win, + CUINT width, + CELL_FUNC OutFunc, + unsigned int *cellPadding) +{ + REASON_INIT(reason); + char *item[5], str[CPUFREQ_NAME_LEN+4+1]; + signed int idx, len = (1 + width) * 5; + for (idx = 0; idx < 5; idx++) { + if ((item[idx] = malloc((size_t) len)) != NULL) { + continue; + } else { + do { + free(item[idx]); + } while (idx-- != 0); + + REASON_SET(reason, RC_MEM_ERR); + return reason; + } + } +/* Section Mark */ + PUT( SCANKEY_NULL, RSC(SYSINFO_KERNEL).ATTR(), width, 0, + "%s:", BITWISEAND(LOCKLESS, RO(Shm)->SysGate.Operation, 0x1) ? + RO(Shm)->SysGate.sysname : (char*) RSC(SYSGATE).CODE() ); + + PUT( SCANKEY_NULL, RSC(KERNEL_RELEASE).ATTR(), width, 2, + "%s%.*s[%s]", RSC(KERNEL_RELEASE).CODE(), + width - 5 - RSZ(KERNEL_RELEASE) + - (int) strlen(RO(Shm)->SysGate.release), + hSpace, RO(Shm)->SysGate.release ); + + PUT( SCANKEY_NULL, RSC(KERNEL_VERSION).ATTR(), width, 2, + "%s%.*s[%s]", RSC(KERNEL_VERSION).CODE(), + width - 5 - RSZ(KERNEL_VERSION) + - (int) strlen(RO(Shm)->SysGate.version), + hSpace, RO(Shm)->SysGate.version ); + + PUT( SCANKEY_NULL, RSC(KERNEL_MACHINE).ATTR(), width, 2, + "%s%.*s[%s]", RSC(KERNEL_MACHINE).CODE(), + width - 5 - RSZ(KERNEL_MACHINE) + - (int) strlen(RO(Shm)->SysGate.machine), + hSpace, RO(Shm)->SysGate.machine ); +/* Section Mark */ + PUT( SCANKEY_NULL, RSC(KERNEL_MEMORY).ATTR(), width, 0, + "%s:%.*s", RSC(KERNEL_MEMORY).CODE(), + width - RSZ(KERNEL_MEMORY), hSpace ); + + StrLenFormat(len, str, CPUFREQ_NAME_LEN+4+1, "%lu", + RO(Shm)->SysGate.memInfo.totalram); + + PUT( SCANKEY_NULL, RSC(KERNEL_TOTAL_RAM).ATTR(), width, 2, + "%s%.*s" "%s KB", RSC(KERNEL_TOTAL_RAM).CODE(), + width - 6 - RSZ(KERNEL_TOTAL_RAM) - len, hSpace, str ); + + StrLenFormat(len, str, CPUFREQ_NAME_LEN+4+1, "%lu", + RO(Shm)->SysGate.memInfo.sharedram); + + GridCall( PUT( SCANKEY_NULL, RSC(KERNEL_SHARED_RAM).ATTR(), width, 2, + "%s%.*s" "%s KB", RSC(KERNEL_SHARED_RAM).CODE(), + width - 6 - RSZ(KERNEL_SHARED_RAM) - len, hSpace, str ), + Kernel_RAM_Update, &RO(Shm)->SysGate.memInfo.sharedram ); + + StrLenFormat(len, str, CPUFREQ_NAME_LEN+4+1, + "%lu", RO(Shm)->SysGate.memInfo.freeram); + + GridCall( PUT( SCANKEY_NULL, RSC(KERNEL_FREE_RAM).ATTR(), width, 2, + "%s%.*s" "%s KB", RSC(KERNEL_FREE_RAM).CODE(), + width - 6 - RSZ(KERNEL_FREE_RAM) - len, hSpace, str ), + Kernel_RAM_Update, &RO(Shm)->SysGate.memInfo.freeram ); + + StrLenFormat(len, str, CPUFREQ_NAME_LEN+4+1, + "%lu", RO(Shm)->SysGate.memInfo.bufferram); + + GridCall( PUT( SCANKEY_NULL, RSC(KERNEL_BUFFER_RAM).ATTR(), width, 2, + "%s%.*s" "%s KB", RSC(KERNEL_BUFFER_RAM).CODE(), + width - 6 - RSZ(KERNEL_BUFFER_RAM) - len, hSpace, str ), + Kernel_RAM_Update, &RO(Shm)->SysGate.memInfo.bufferram ); + + StrLenFormat(len, str, CPUFREQ_NAME_LEN+4+1, + "%lu", RO(Shm)->SysGate.memInfo.totalhigh); + + GridCall( PUT( SCANKEY_NULL, RSC(KERNEL_TOTAL_HIGH).ATTR(), width, 2, + "%s%.*s" "%s KB", RSC(KERNEL_TOTAL_HIGH).CODE(), + width - 6 - RSZ(KERNEL_TOTAL_HIGH) - len, hSpace, str ), + Kernel_RAM_Update, &RO(Shm)->SysGate.memInfo.totalhigh ); + + StrLenFormat(len, str, CPUFREQ_NAME_LEN+4+1, + "%lu", RO(Shm)->SysGate.memInfo.freehigh); + + GridCall( PUT( SCANKEY_NULL, RSC(KERNEL_FREE_HIGH).ATTR(), width, 2, + "%s%.*s" "%s KB", RSC(KERNEL_FREE_HIGH).CODE(), + width - 6 - RSZ(KERNEL_FREE_HIGH) - len, hSpace, str ), + Kernel_RAM_Update, &RO(Shm)->SysGate.memInfo.freehigh ); +/* Section Mark */ + StrFormat(item[0], 2+4+1+6+1+1, "%%s%%.*s<%%%d.*s>", CPUFREQ_NAME_LEN); + + len = KMIN(strlen(RO(Shm)->CS.array), CPUFREQ_NAME_LEN); + if (len > 0) + { + GridCall( PUT( OPS_CLOCK_SOURCE_SEL, RSC(KERNEL_CLOCK_SOURCE).ATTR(), + width, 0, item[0], RSC(KERNEL_CLOCK_SOURCE).CODE(), + width - (OutFunc == NULL ? 2 : 3) + - RSZ(KERNEL_CLOCK_SOURCE) - CPUFREQ_NAME_LEN, hSpace, + len, RO(Shm)->CS.array ), + Kernel_ClockSource_Update ); + } else { + GridCall( PUT( OPS_CLOCK_SOURCE_SEL, RSC(KERNEL_CLOCK_SOURCE).ATTR(), + width, 0, item[0], RSC(KERNEL_CLOCK_SOURCE).CODE(), + width - (OutFunc == NULL ? 2 : 3) + - RSZ(KERNEL_CLOCK_SOURCE) - CPUFREQ_NAME_LEN, hSpace, + CPUFREQ_NAME_LEN, RSC(MISSING).CODE() ), + Kernel_ClockSource_Update ); + } +/* Section Mark */ + StrFormat(item[0], 2+4+1+6+1+1, "%%s%%.*s[%%%d.*s]", CPUFREQ_NAME_LEN); + + len = KMIN(strlen(RO(Shm)->SysGate.OS.FreqDriver.Name), CPUFREQ_NAME_LEN); + if (len > 0) + { + GridCall( PUT( SCANKEY_NULL, RSC(KERNEL_FREQ_DRIVER).ATTR(), width, 0, + item[0], RSC(KERNEL_FREQ_DRIVER).CODE(), + width - (OutFunc == NULL ? 2 : 3) + - RSZ(KERNEL_FREQ_DRIVER) - CPUFREQ_NAME_LEN, hSpace, + len, RO(Shm)->SysGate.OS.FreqDriver.Name ), + Kernel_CPU_Freq_Update ); + } else { + GridCall( PUT( SCANKEY_NULL, RSC(KERNEL_FREQ_DRIVER).ATTR(), width, 0, + item[0], RSC(KERNEL_FREQ_DRIVER).CODE(), + width - (OutFunc == NULL ? 2 : 3) + - RSZ(KERNEL_FREQ_DRIVER) - CPUFREQ_NAME_LEN, hSpace, + CPUFREQ_NAME_LEN, RSC(MISSING).CODE() ), + Kernel_CPU_Freq_Update ); + } +/* Row Mark */ + len=KMIN(strlen(RO(Shm)->SysGate.OS.FreqDriver.Governor), CPUFREQ_NAME_LEN); + if (len > 0) + { + GridCall( PUT( SCANKEY_NULL, RSC(KERNEL_GOVERNOR).ATTR(), width, 0, + item[0], RSC(KERNEL_GOVERNOR).CODE(), + width - (OutFunc == NULL ? 2 : 3) - RSZ(KERNEL_GOVERNOR) + - CPUFREQ_NAME_LEN, hSpace, + len, RO(Shm)->SysGate.OS.FreqDriver.Governor ), + Kernel_Governor_Update ); + } else { + GridCall( PUT( SCANKEY_NULL, RSC(KERNEL_GOVERNOR).ATTR(), width, 0, + item[0], RSC(KERNEL_GOVERNOR).CODE(), + width - (OutFunc == NULL ? 2 : 3) - RSZ(KERNEL_GOVERNOR) + - CPUFREQ_NAME_LEN, hSpace, + CPUFREQ_NAME_LEN, RSC(MISSING).CODE() ), + Kernel_Governor_Update ); + } +/* Row Mark */ + StrFormat(item[0], 2+4+1+6+1+1, "%%s%%.*s[%%%d.*s]", CPUIDLE_NAME_LEN); + + len = KMIN(strlen(RO(Shm)->SysGate.OS.IdleDriver.Name), CPUIDLE_NAME_LEN); + if (len > 0) + { + GridCall( PUT( SCANKEY_NULL, RSC(KERNEL_IDLE_DRIVER).ATTR(), width, 0, + item[0], RSC(KERNEL_IDLE_DRIVER).CODE(), + width - (OutFunc == NULL ? 2 : 3) + - RSZ(KERNEL_IDLE_DRIVER) - CPUIDLE_NAME_LEN, hSpace, + len, RO(Shm)->SysGate.OS.IdleDriver.Name ), + Kernel_CPU_Idle_Update ); + } else { + GridCall( PUT( SCANKEY_NULL, RSC(KERNEL_IDLE_DRIVER).ATTR(), width, 0, + item[0], RSC(KERNEL_IDLE_DRIVER).CODE(), + width - (OutFunc == NULL ? 2 : 3) + - RSZ(KERNEL_IDLE_DRIVER) - CPUIDLE_NAME_LEN, hSpace, + CPUIDLE_NAME_LEN, RSC(MISSING).CODE() ), + Kernel_CPU_Idle_Update ); + } +/* Section Mark */ + StrFormat(item[0], 2+4+1+4+1+1, + "%%s%%.*s%c%%%ds%c", + RO(Shm)->Registration.Driver.CPUidle & REGISTRATION_ENABLE ? '<' : '[', + CPUIDLE_NAME_LEN, + RO(Shm)->Registration.Driver.CPUidle & REGISTRATION_ENABLE ? '>' : ']'); + + if (RO(Shm)->SysGate.OS.IdleDriver.stateCount > 0) + { + idx = RO(Shm)->SysGate.OS.IdleDriver.stateLimit - 1; + GridCall( + PUT(RO(Shm)->Registration.Driver.CPUidle & REGISTRATION_ENABLE ? + BOXKEY_LIMIT_IDLE_STATE : SCANKEY_NULL, + RSC(KERNEL_LIMIT).ATTR(), width, 2, + item[0], RSC(KERNEL_LIMIT).CODE(), + width - RSZ(KERNEL_LIMIT) - CPUIDLE_NAME_LEN-5, hSpace, + RO(Shm)->SysGate.OS.IdleDriver.State[idx].Name ), + Kernel_IdleLimit_Update, + &RO(Shm)->SysGate.OS.IdleDriver.stateLimit ); + } else { + GridCall( PUT( SCANKEY_NULL, RSC(KERNEL_LIMIT).ATTR(), width, 2, + item[0], RSC(KERNEL_LIMIT).CODE(), + width - RSZ(KERNEL_LIMIT) - CPUIDLE_NAME_LEN-5, hSpace, + RSC(NOT_AVAILABLE).CODE() ), + Kernel_IdleLimit_Update, + &RO(Shm)->SysGate.OS.IdleDriver.stateLimit ); + } +/* Row Mark */ + if (RO(Shm)->SysGate.OS.IdleDriver.stateCount > 0) + { + StrFormat(item[0], 10+1, "%s%.*s", + RSC(KERNEL_STATE).CODE(), 10 - RSZ(KERNEL_STATE), hSpace); + + StrFormat(item[1], 10+1, "%.*s", 10, hSpace); + + StrFormat(item[2], 10+1, "%s%.*s", + RSC(KERNEL_POWER).CODE(), 10 - RSZ(KERNEL_POWER), hSpace); + + StrFormat(item[3], 10+1, "%s%.*s", + RSC(KERNEL_LATENCY).CODE(), 10 - RSZ(KERNEL_LATENCY), hSpace); + + StrFormat(item[4], 10+1, "%s%.*s", + RSC(KERNEL_RESIDENCY).CODE(), 10-RSZ(KERNEL_RESIDENCY), hSpace); + + for (idx = 0; idx < CPUIDLE_STATE_MAX; idx++) + { + if (idx < RO(Shm)->SysGate.OS.IdleDriver.stateCount) + { + ssize_t cat; + signed int n; + + len = KMIN(strlen(RO(Shm)->SysGate.OS.IdleDriver.State[idx].Name), 7); + StrLenFormat(cat, str, 7+1, "%7.*s", (int) len, + RO(Shm)->SysGate.OS.IdleDriver.State[idx].Name); + + len = strlen(item[0]); + for (n = 0; n < cat; n++) { + item[0][len + n] = str[n]; + } + item[0][len + n] = '\0'; + + len = KMIN(strlen(RO(Shm)->SysGate.OS.IdleDriver.State[idx].Desc), 7); + StrLenFormat(cat, str, 7+1, "%7.*s", (int) len, + RO(Shm)->SysGate.OS.IdleDriver.State[idx].Desc); + + len = strlen(item[1]); + for (n = 0; n < cat; n++) { + item[1][len + n] = str[n]; + } + item[1][len + n] = '\0'; + + StrLenFormat(cat, str, 10+1, "%7d", + RO(Shm)->SysGate.OS.IdleDriver.State[idx].powerUsage); + + len = strlen(item[2]); + for (n = 0; n < cat; n++) { + item[2][len + n] = str[n]; + } + item[2][len + n] = '\0'; + + StrLenFormat(cat, str, 10+1, "%7u", + RO(Shm)->SysGate.OS.IdleDriver.State[idx].exitLatency); + + len = strlen(item[3]); + for (n = 0; n < cat; n++) { + item[3][len + n] = str[n]; + } + item[3][len + n] = '\0'; + + StrLenFormat(cat, str, 10+1, "%7u", + RO(Shm)->SysGate.OS.IdleDriver.State[idx].targetResidency); + + len = strlen(item[4]); + for (n = 0; n < cat; n++) { + item[4][len + n] = str[n]; + } + item[4][len + n] = '\0'; + } else { + int d; + for (d = 0; d < 5; d++) { + len = strlen(item[d]); + item[d][len ] = \ + item[d][len + 1] = \ + item[d][len + 2] = \ + item[d][len + 3] = '\x20'; + item[d][len + 4] = '\0'; + } + } + if (idx < (CPUIDLE_STATE_MAX - 1)) { + int d; + for (d = 0; d < 5; d++) { + len = strlen(item[d]); + item[d][len ] = '\x20'; + item[d][len + 1] = '\0'; + } + } + } + PUT( SCANKEY_NULL, RSC(KERNEL_STATE).ATTR(), width, 3, + "%.*s", width - (OutFunc == NULL ? 6 : 3), item[0] ); + + PUT( SCANKEY_NULL, RSC(KERNEL_STATE).ATTR(), width, 3, + "%.*s", width - (OutFunc == NULL ? 6 : 3), item[1] ); + + PUT( SCANKEY_NULL, RSC(KERNEL_POWER).ATTR(), width, 3, + "%.*s", width - (OutFunc == NULL ? 6 : 3), item[2] ); + + PUT( SCANKEY_NULL, RSC(KERNEL_LATENCY).ATTR(), width, 3, + "%.*s", width - (OutFunc == NULL ? 6 : 3), item[3] ); + + PUT( SCANKEY_NULL, RSC(KERNEL_RESIDENCY).ATTR(), width, 3, + "%.*s", width - (OutFunc == NULL ? 6 : 3), item[4] ); + } +/* Section Mark */ + for (idx = 0; idx < 5; idx++) { + free(item[idx]); + } + return reason; +} + +char *ScrambleSMBIOS(enum SMB_STRING idx, const size_t mod, const char thing) +{ + struct { + char *pString; + unsigned short secret; + } smb[SMB_STRING_COUNT] = { + {.pString = RO(Shm)->SMB.BIOS.Vendor , .secret = 0}, + {.pString = RO(Shm)->SMB.BIOS.Version , .secret = 0}, + {.pString = RO(Shm)->SMB.BIOS.Release , .secret = 0}, + {.pString = RO(Shm)->SMB.System.Vendor , .secret = 0}, + {.pString = RO(Shm)->SMB.Product.Name , .secret = 0}, + {.pString = RO(Shm)->SMB.Product.Version, .secret = 0}, + {.pString = RO(Shm)->SMB.Product.Serial, .secret = 1}, + {.pString = RO(Shm)->SMB.Product.SKU , .secret = 0}, + {.pString = RO(Shm)->SMB.Product.Family , .secret = 0}, + {.pString = RO(Shm)->SMB.Board.Vendor , .secret = 0}, + {.pString = RO(Shm)->SMB.Board.Name , .secret = 0}, + {.pString = RO(Shm)->SMB.Board.Version , .secret = 0}, + {.pString = RO(Shm)->SMB.Board.Serial , .secret = 1}, + {.pString = RO(Shm)->SMB.Phys.Memory.Array , .secret = 0}, + {.pString = RO(Shm)->SMB.Memory.Locator[0], .secret = 0}, + {.pString = RO(Shm)->SMB.Memory.Locator[1], .secret = 0}, + {.pString = RO(Shm)->SMB.Memory.Locator[2], .secret = 0}, + {.pString = RO(Shm)->SMB.Memory.Locator[3], .secret = 0}, + {.pString = RO(Shm)->SMB.Memory.Manufacturer[0],.secret = 0}, + {.pString = RO(Shm)->SMB.Memory.Manufacturer[1],.secret = 0}, + {.pString = RO(Shm)->SMB.Memory.Manufacturer[2],.secret = 0}, + {.pString = RO(Shm)->SMB.Memory.Manufacturer[3],.secret = 0}, + {.pString = RO(Shm)->SMB.Memory.PartNumber[0], .secret = 0}, + {.pString = RO(Shm)->SMB.Memory.PartNumber[1], .secret = 0}, + {.pString = RO(Shm)->SMB.Memory.PartNumber[2], .secret = 0}, + {.pString = RO(Shm)->SMB.Memory.PartNumber[3], .secret = 0} + }; + if (smb[idx].secret && Setting.secret) { + static char outStr[MAX_UTS_LEN]; + size_t len = strlen(smb[idx].pString), dst; + for (dst = 0; dst < len; dst++) { + outStr[dst] = (dst % mod) ? thing : smb[idx].pString[dst]; + } + outStr[dst] = '\0'; + return outStr; + } else { + return smb[idx].pString; + } +} + +const char *SMB_Comment[SMB_STRING_COUNT] = { + " " COREFREQ_STRINGIFY(SMB_BIOS_VENDOR) " ", + " " COREFREQ_STRINGIFY(SMB_BIOS_VERSION) " ", + " " COREFREQ_STRINGIFY(SMB_BIOS_RELEASE) " ", + " " COREFREQ_STRINGIFY(SMB_SYSTEM_VENDOR) " ", + " " COREFREQ_STRINGIFY(SMB_PRODUCT_NAME) " ", + " " COREFREQ_STRINGIFY(SMB_PRODUCT_VERSION) " ", + " " COREFREQ_STRINGIFY(SMB_PRODUCT_SERIAL) " ", + " " COREFREQ_STRINGIFY(SMB_PRODUCT_SKU) " ", + " " COREFREQ_STRINGIFY(SMB_PRODUCT_FAMILY) " ", + " " COREFREQ_STRINGIFY(SMB_BOARD_VENDOR) " ", + " " COREFREQ_STRINGIFY(SMB_BOARD_NAME) " ", + " " COREFREQ_STRINGIFY(SMB_BOARD_VERSION) " ", + " " COREFREQ_STRINGIFY(SMB_BOARD_SERIAL) " ", + " " COREFREQ_STRINGIFY(SMB_PHYS_MEM_ARRAY) " ", + " " COREFREQ_STRINGIFY(SMB_MEM_0_LOCATOR) " ", + " " COREFREQ_STRINGIFY(SMB_MEM_1_LOCATOR) " ", + " " COREFREQ_STRINGIFY(SMB_MEM_2_LOCATOR) " ", + " " COREFREQ_STRINGIFY(SMB_MEM_3_LOCATOR) " ", + " " COREFREQ_STRINGIFY(SMB_MEM_0_MANUFACTURER) " ", + " " COREFREQ_STRINGIFY(SMB_MEM_1_MANUFACTURER) " ", + " " COREFREQ_STRINGIFY(SMB_MEM_2_MANUFACTURER) " ", + " " COREFREQ_STRINGIFY(SMB_MEM_3_MANUFACTURER) " ", + " " COREFREQ_STRINGIFY(SMB_MEM_0_PARTNUMBER) " ", + " " COREFREQ_STRINGIFY(SMB_MEM_1_PARTNUMBER) " ", + " " COREFREQ_STRINGIFY(SMB_MEM_2_PARTNUMBER) " ", + " " COREFREQ_STRINGIFY(SMB_MEM_3_PARTNUMBER) " " +}; + +REASON_CODE SysInfoSMBIOS(Window *win, + CUINT width, + CELL_FUNC OutFunc, + unsigned int *cellPadding) +{ + enum SMB_STRING idx; + + REASON_INIT(reason); + + for (idx = 0; idx < SMB_STRING_COUNT; idx ++) + { + const unsigned long long key = SMBIOS_STRING_INDEX + | (unsigned long long) idx; + + GridHover( PUT( key, RSC(SMBIOS_ITEM).ATTR(), width, 0, + "[%2d] %s", idx, ScrambleSMBIOS(idx, 4, '-')), + SMB_Comment[idx] ); + } + return reason; +} + +void Package(unsigned int iter) +{ + char *out = malloc(8 + (RO(Shm)->Proc.CPU.Count + 10) * MIN_WIDTH); + if (out != NULL) + { + int idx, rdx; + const int sdx = sprintf(out, "\t\t" "Cycles" "\t\t" "State(%%)" "\n"); + + while (!BITVAL(Shutdown, SYNC) && (iter-- > 0) && (sdx > 0)) + { + while (!BITCLR(LOCKLESS, RW(Shm)->Proc.Sync, SYNC0) + && !BITVAL(Shutdown, SYNC)) { + nanosleep(&RO(Shm)->Sleep.pollingWait, NULL); + } + if (BITCLR(LOCKLESS, RW(Shm)->Proc.Sync, NTFY0)) { + ClientFollowService(&localService, &RO(Shm)->Proc.Service, 0); + } + struct PKG_FLIP_FLOP *PFlop = \ + &RO(Shm)->Proc.FlipFlop[!RO(Shm)->Proc.Toggle]; + + idx = sdx; + if ((rdx = sprintf(&out[idx], + "PC02" "\t" "%18llu" "\t" "%7.2f" "\n" \ + "PC03" "\t" "%18llu" "\t" "%7.2f" "\n" \ + "PC04" "\t" "%18llu" "\t" "%7.2f" "\n" \ + "PC06" "\t" "%18llu" "\t" "%7.2f" "\n" \ + "PC07" "\t" "%18llu" "\t" "%7.2f" "\n" \ + "PC08" "\t" "%18llu" "\t" "%7.2f" "\n" \ + "PC09" "\t" "%18llu" "\t" "%7.2f" "\n" \ + "PC10" "\t" "%18llu" "\t" "%7.2f" "\n" \ + "MC6" "\t" "%18llu" "\t" "%7.2f" "\n" \ + "PTSC" "\t" "%18llu" "\n" \ + "UNCORE" "\t" "%18llu" "\n\n", + PFlop->Delta.PC02, 100.f * RO(Shm)->Proc.State.PC02, + PFlop->Delta.PC03, 100.f * RO(Shm)->Proc.State.PC03, + PFlop->Delta.PC04, 100.f * RO(Shm)->Proc.State.PC04, + PFlop->Delta.PC06, 100.f * RO(Shm)->Proc.State.PC06, + PFlop->Delta.PC07, 100.f * RO(Shm)->Proc.State.PC07, + PFlop->Delta.PC08, 100.f * RO(Shm)->Proc.State.PC08, + PFlop->Delta.PC09, 100.f * RO(Shm)->Proc.State.PC09, + PFlop->Delta.PC10, 100.f * RO(Shm)->Proc.State.PC10, + PFlop->Delta.MC6, 100.f * RO(Shm)->Proc.State.MC6, + PFlop->Delta.PCLK, + PFlop->Uncore.FC0)) > 0) + { + idx += rdx; + } + fwrite(out, (size_t) idx, 1, stdout); + } + free(out); + } +} + +signed int Core_Celsius(char *out, struct FLIP_FLOP *CFlop, unsigned int cpu) +{ + return sprintf(out, + "%03u %7.2f (%5.2f)" \ + " %6.2f %6.2f %6.2f %6.2f %6.2f %6.2f" \ + " %-3u/%3u:%-3u/%3u\n", + cpu, + CFlop->Relative.Freq, + CFlop->Relative.Ratio, + 100.f * CFlop->State.Turbo, + 100.f * CFlop->State.C0, + 100.f * CFlop->State.C1, + 100.f * CFlop->State.C3, + 100.f * CFlop->State.C6, + 100.f * CFlop->State.C7, + RO(Shm)->Cpu[cpu].PowerThermal.Limit[SENSOR_LOWEST], + CFlop->Thermal.Temp, + CFlop->Thermal.Sensor, + RO(Shm)->Cpu[cpu].PowerThermal.Limit[SENSOR_HIGHEST]); +} + +signed int Core_Fahrenheit(char *out,struct FLIP_FLOP *CFlop,unsigned int cpu) +{ + return sprintf(out, + "%03u %7.2f (%5.2f)" \ + " %6.2f %6.2f %6.2f %6.2f %6.2f %6.2f" \ + " %-3u/%3u:%-3u/%3u\n", + cpu, + CFlop->Relative.Freq, + CFlop->Relative.Ratio, + 100.f * CFlop->State.Turbo, + 100.f * CFlop->State.C0, + 100.f * CFlop->State.C1, + 100.f * CFlop->State.C3, + 100.f * CFlop->State.C6, + 100.f * CFlop->State.C7, + Cels2Fahr(RO(Shm)->Cpu[cpu].PowerThermal.Limit[SENSOR_LOWEST]), + Cels2Fahr(CFlop->Thermal.Temp), + Cels2Fahr(CFlop->Thermal.Sensor), + Cels2Fahr(RO(Shm)->Cpu[cpu].PowerThermal.Limit[SENSOR_HIGHEST]) + ); +} + +signed int Pkg_Celsius(char *out, struct PKG_FLIP_FLOP *PFlop) +{ + struct FLIP_FLOP *SFlop = &RO(Shm)->Cpu[ + RO(Shm)->Proc.Service.Core + ].FlipFlop[ + !RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Toggle + ]; + + return sprintf(out, "\n" \ + "%.*s" "Averages:" \ + "%.*s" "Turbo C0(%%) C1(%%) C3(%%) C6(%%) C7(%%)" \ + "%.*s" "TjMax:" "%.*s" "Pkg:\n" \ + "%.*s" "%6.2f %6.2f %6.2f %6.2f %6.2f %6.2f" \ + "%.*s" "%3u C" "%.*s" "%3u C\n\n", + 4, hSpace, + 8, hSpace, + 4, hSpace, + 4, hSpace, + 20, hSpace, + 100.f * RO(Shm)->Proc.Avg.Turbo, + 100.f * RO(Shm)->Proc.Avg.C0, + 100.f * RO(Shm)->Proc.Avg.C1, + 100.f * RO(Shm)->Proc.Avg.C3, + 100.f * RO(Shm)->Proc.Avg.C6, + 100.f * RO(Shm)->Proc.Avg.C7, + 5, hSpace, + SFlop->Thermal.Param.Offset[THERMAL_TARGET], + 3, hSpace, + PFlop->Thermal.Temp); +} + +signed int Pkg_Fahrenheit(char *out, struct PKG_FLIP_FLOP *PFlop) +{ + struct FLIP_FLOP *SFlop = &RO(Shm)->Cpu[ + RO(Shm)->Proc.Service.Core + ].FlipFlop[ + !RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Toggle + ]; + + return sprintf(out, "\n" \ + "%.*s" "Averages:" \ + "%.*s" "Turbo C0(%%) C1(%%) C3(%%) C6(%%) C7(%%)" \ + "%.*s" "TjMax:" "%.*s" "Pkg:\n" \ + "%.*s" "%6.2f %6.2f %6.2f %6.2f %6.2f %6.2f" \ + "%.*s" "%3u C" "%.*s" "%3u C\n\n", + 4, hSpace, + 8, hSpace, + 4, hSpace, + 4, hSpace, + 20, hSpace, + 100.f * RO(Shm)->Proc.Avg.Turbo, + 100.f * RO(Shm)->Proc.Avg.C0, + 100.f * RO(Shm)->Proc.Avg.C1, + 100.f * RO(Shm)->Proc.Avg.C3, + 100.f * RO(Shm)->Proc.Avg.C6, + 100.f * RO(Shm)->Proc.Avg.C7, + 5, hSpace, + SFlop->Thermal.Param.Offset[THERMAL_TARGET], + 3, hSpace, + Cels2Fahr(PFlop->Thermal.Temp)); +} + +void Counters(unsigned int iter) +{ + signed int (*Core_Temp)(char *, struct FLIP_FLOP *, unsigned int) = \ + Setting.fahrCels ? Core_Fahrenheit : Core_Celsius; + + signed int (*Pkg_Temp)(char *, struct PKG_FLIP_FLOP *) = \ + Setting.fahrCels ? Pkg_Fahrenheit : Pkg_Celsius; + + char *out = malloc(8 + (RO(Shm)->Proc.CPU.Count + 3) * MIN_WIDTH); + if (out != NULL) + { + unsigned int cpu; + signed int idx, rdx; + const int sdx = \ + sprintf( out, "CPU Freq(MHz) Ratio Turbo" \ + " C0(%%) C1(%%) C3(%%) C6(%%) C7(%%)" \ + " Min TMP:TS Max\n" ); + + while (!BITVAL(Shutdown, SYNC) && (iter-- > 0) && (sdx > 0)) + { + while (!BITCLR(LOCKLESS, RW(Shm)->Proc.Sync, SYNC0) + && !BITVAL(Shutdown, SYNC)) { + nanosleep(&RO(Shm)->Sleep.pollingWait, NULL); + } + if (BITCLR(LOCKLESS, RW(Shm)->Proc.Sync, NTFY0)) { + ClientFollowService(&localService, &RO(Shm)->Proc.Service, 0); + } + idx = sdx; + for (cpu = 0; + (cpu < RO(Shm)->Proc.CPU.Count) && !BITVAL(Shutdown, SYNC); + cpu++) + { + if (!BITVAL(RO(Shm)->Cpu[cpu].OffLine, HW)) { + struct FLIP_FLOP *CFlop = \ + &RO(Shm)->Cpu[cpu].FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + + if (!BITVAL(RO(Shm)->Cpu[cpu].OffLine, OS)) { + rdx = Core_Temp(&out[idx], CFlop, cpu); + } else { + rdx = sprintf(&out[idx], "%03u OFF\n", cpu); + } + if (rdx > 0) { + idx += rdx; + } + } + } + struct PKG_FLIP_FLOP *PFlop = \ + &RO(Shm)->Proc.FlipFlop[!RO(Shm)->Proc.Toggle]; + + if ((rdx = Pkg_Temp(&out[idx], PFlop)) > 0) { + idx += rdx; + } + fwrite(out, (size_t) idx, 1, stdout); + } + free(out); + } +} + +void Sensors(unsigned int iter) +{ + char *out = malloc(8 + (RO(Shm)->Proc.CPU.Count + 4) * MIN_WIDTH); + char *row = malloc(MIN_WIDTH + 16); + if (out && row) + { + enum PWR_DOMAIN pw; + unsigned int cpu; + signed int idx, rdx; + const int sdx = \ + sprintf( out, "CPU Freq(MHz) VID Vcore TMP(%c)" \ + " Accumulator Energy(J) Power(W)\n", + Setting.fahrCels ? 'F' : 'C' ); + + const int ldx = \ + sprintf( row, "\n" "%.*sPackage[%c]%.*sCores%.*sUncore%.*sMemory" \ + "%.*sPlatform" "\n" "Energy(J):", + 13, hSpace, + '0'+RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Topology.PackageID, + 4, hSpace, 9, hSpace, 8, hSpace, 8, hSpace); + + while (!BITVAL(Shutdown, SYNC) && (iter-- > 0) && (sdx > 0) && (ldx > 0)) + { + while (!BITCLR(LOCKLESS, RW(Shm)->Proc.Sync, SYNC0) + && !BITVAL(Shutdown, SYNC)) { + nanosleep(&RO(Shm)->Sleep.pollingWait, NULL); + } + if (BITCLR(LOCKLESS, RW(Shm)->Proc.Sync, NTFY0)) { + ClientFollowService(&localService, &RO(Shm)->Proc.Service, 0); + } + idx = sdx; + for (cpu = 0; + (cpu < RO(Shm)->Proc.CPU.Count) && !BITVAL(Shutdown, SYNC); + cpu++) + { + if (!BITVAL(RO(Shm)->Cpu[cpu].OffLine, HW)) + { + struct FLIP_FLOP *CFlop = \ + &RO(Shm)->Cpu[cpu].FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + + if (!BITVAL(RO(Shm)->Cpu[cpu].OffLine, OS)) { + rdx = sprintf(&out[idx],"%03u %7.2f %5d %5.4f %3u" \ + " %018llu %13.9f %13.9f\n", + cpu, + CFlop->Relative.Freq, + CFlop->Voltage.VID, + CFlop->Voltage.Vcore, + Setting.fahrCels ? Cels2Fahr(CFlop->Thermal.Temp) + : CFlop->Thermal.Temp, + CFlop->Delta.Power.ACCU, + CFlop->State.Energy, + CFlop->State.Power); + } else { + rdx = sprintf(&out[idx], "%03u OFF\n", cpu); + } + if (rdx > 0) { + idx += rdx; + } + } + } + memcpy(&out[idx], row, (size_t) ldx); + idx += ldx; + + for (pw = PWR_DOMAIN(PKG); pw < PWR_DOMAIN(SIZE); pw++) { + rdx = sprintf(&out[idx], "%.*s" "%13.9f", 1, hSpace, + RO(Shm)->Proc.State.Energy[pw].Current); + if (rdx > 0) { + idx += rdx; + } + } + memcpy(&out[idx], "\n" "Power(W) :", 11); + idx += 11; + for (pw = PWR_DOMAIN(PKG); pw < PWR_DOMAIN(SIZE); pw++) { + rdx = sprintf(&out[idx], "%.*s" "%13.9f", 1, hSpace, + RO(Shm)->Proc.State.Power[pw].Current); + if (rdx > 0) { + idx += rdx; + } + } + out[idx++] = '\n'; out[idx++] = '\n'; + + fwrite(out, (size_t) idx, 1, stdout); + } + } + if (out != NULL) { + free(out); + } + if (row != NULL) { + free(row); + } +} + +void Voltage(unsigned int iter) +{ + char *out = malloc(8 + (RO(Shm)->Proc.CPU.Count + 1) * MIN_WIDTH); + if (out != NULL) + { + unsigned int cpu; + signed int idx, rdx; + const int sdx=sprintf(out, "CPU Freq(MHz) VID Min Vcore Max\n"); + + while (!BITVAL(Shutdown, SYNC) && (iter-- > 0) && (sdx > 0)) + { + while (!BITCLR(LOCKLESS, RW(Shm)->Proc.Sync, SYNC0) + && !BITVAL(Shutdown, SYNC)) { + nanosleep(&RO(Shm)->Sleep.pollingWait, NULL); + } + if (BITCLR(LOCKLESS, RW(Shm)->Proc.Sync, NTFY0)) { + ClientFollowService(&localService, &RO(Shm)->Proc.Service, 0); + } + idx = sdx; + for (cpu = 0; + (cpu < RO(Shm)->Proc.CPU.Count) && !BITVAL(Shutdown, SYNC); + cpu++) + { + if (!BITVAL(RO(Shm)->Cpu[cpu].OffLine, HW)) + { + struct FLIP_FLOP *CFlop = \ + &RO(Shm)->Cpu[cpu].FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + + if (!BITVAL(RO(Shm)->Cpu[cpu].OffLine, OS)) { + rdx = sprintf(&out[idx], + "%03u %7.2f %5d %5.4f %5.4f %5.4f\n", + cpu, + CFlop->Relative.Freq, + CFlop->Voltage.VID, + RO(Shm)->Cpu[cpu].Sensors.Voltage.Limit[SENSOR_LOWEST], + CFlop->Voltage.Vcore, + RO(Shm)->Cpu[cpu].Sensors.Voltage.Limit[SENSOR_HIGHEST] + ); + } else { + rdx = sprintf(&out[idx], "%03u OFF\n", cpu); + } + if (rdx > 0) { + idx += rdx; + } + } + } + out[idx++] = '\n'; + + fwrite(out, (size_t) idx, 1, stdout); + } + free(out); + } +} + +void Power(unsigned int iter) +{ + char *out = malloc(8 + (RO(Shm)->Proc.CPU.Count + 5) * MIN_WIDTH); + char *row = malloc(MIN_WIDTH + 8); + if (out && row) + { + enum PWR_DOMAIN pw; + unsigned int cpu; + signed int idx, rdx; + const int sdx = \ + sprintf( out, "CPU Freq(MHz)" \ + " Accumulator Min Energy(J) Max" \ + " Min Power(W) Max\n" ); + const int ldx = \ + sprintf( row, "\nEnergy(J) Package[%c]%.*sCores%.*sUncore%.*sMemory\n", + '0'+RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Topology.PackageID, + 9, hSpace, 15, hSpace, 14, hSpace ); + + while (!BITVAL(Shutdown, SYNC) && (iter-- > 0) && (sdx > 0) && (ldx > 0)) + { + while (!BITCLR(LOCKLESS, RW(Shm)->Proc.Sync, SYNC0) + && !BITVAL(Shutdown, SYNC)) { + nanosleep(&RO(Shm)->Sleep.pollingWait, NULL); + } + if (BITCLR(LOCKLESS, RW(Shm)->Proc.Sync, NTFY0)) { + ClientFollowService(&localService, &RO(Shm)->Proc.Service, 0); + } + idx = sdx; + for (cpu = 0; + (cpu < RO(Shm)->Proc.CPU.Count) && !BITVAL(Shutdown, SYNC); + cpu++) + { + if (!BITVAL(RO(Shm)->Cpu[cpu].OffLine, HW)) + { + struct FLIP_FLOP *CFlop = \ + &RO(Shm)->Cpu[cpu].FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + + if (!BITVAL(RO(Shm)->Cpu[cpu].OffLine, OS)) { + rdx = sprintf(&out[idx], + "%03u %7.2f" \ + " %018llu %6.2f %6.2f %6.2f %6.2f %6.2f %6.2f\n", + cpu, + CFlop->Relative.Freq, + CFlop->Delta.Power.ACCU, + RO(Shm)->Cpu[cpu].Sensors.Energy.Limit[SENSOR_LOWEST], + CFlop->State.Energy, + RO(Shm)->Cpu[cpu].Sensors.Energy.Limit[SENSOR_HIGHEST], + RO(Shm)->Cpu[cpu].Sensors.Power.Limit[SENSOR_LOWEST], + CFlop->State.Power, + RO(Shm)->Cpu[cpu].Sensors.Power.Limit[SENSOR_HIGHEST]); + } else { + rdx = sprintf(&out[idx], "%03u OFF\n", cpu); + } + if (rdx > 0) { + idx += rdx; + } + } + } + memcpy(&out[idx], row, (size_t) ldx); + idx += ldx; + + for (pw = PWR_DOMAIN(PKG); pw < PWR_DOMAIN(PLATFORM); pw++) { + rdx = sprintf(&out[idx], "%.*s" "%6.2f %5.1f %6.2f", + pw == PWR_DOMAIN(PKG) ? 0 : 1, hSpace, + RO(Shm)->Proc.State.Energy[pw].Limit[SENSOR_LOWEST], + RO(Shm)->Proc.State.Energy[pw].Current, + RO(Shm)->Proc.State.Energy[pw].Limit[SENSOR_HIGHEST]); + if (rdx > 0) { + idx += rdx; + } + } + memcpy(&out[idx], "\n" "Power(W)\n", 10); + idx += 10; + + for (pw = PWR_DOMAIN(PKG); pw < PWR_DOMAIN(PLATFORM); pw++) { + rdx = sprintf(&out[idx], "%.*s" "%6.2f %5.1f %6.2f", + pw == PWR_DOMAIN(PKG) ? 0 : 1, hSpace, + RO(Shm)->Proc.State.Power[pw].Limit[SENSOR_LOWEST], + RO(Shm)->Proc.State.Power[pw].Current, + RO(Shm)->Proc.State.Power[pw].Limit[SENSOR_HIGHEST]); + if (rdx > 0) { + idx += rdx; + } + } + out[idx++] = '\n'; out[idx++] = '\n'; + + fwrite(out, (size_t) idx, 1, stdout); + } + } + if (out != NULL) { + free(out); + } + if (row != NULL) { + free(row); + } +} + +void Instructions(unsigned int iter) +{ + char *out = malloc(8 + (RO(Shm)->Proc.CPU.Count + 1) * MIN_WIDTH); + if (out != NULL) + { + unsigned int cpu; + signed int idx, rdx; + const int sdx = \ + sprintf(out, "CPU IPS IPC CPI\n"); + + while (!BITVAL(Shutdown, SYNC) && (iter-- > 0) && (sdx > 0)) + { + while (!BITCLR(LOCKLESS, RW(Shm)->Proc.Sync, SYNC0) + && !BITVAL(Shutdown, SYNC)) { + nanosleep(&RO(Shm)->Sleep.pollingWait, NULL); + } + if (BITCLR(LOCKLESS, RW(Shm)->Proc.Sync, NTFY0)) { + ClientFollowService(&localService, &RO(Shm)->Proc.Service, 0); + } + idx = sdx; + for (cpu = 0; + (cpu < RO(Shm)->Proc.CPU.Count) && !BITVAL(Shutdown, SYNC); + cpu++) + { + if (!BITVAL(RO(Shm)->Cpu[cpu].OffLine, HW)) { + struct FLIP_FLOP *CFlop = \ + &RO(Shm)->Cpu[cpu].FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + + if (!BITVAL(RO(Shm)->Cpu[cpu].OffLine, OS)) { + rdx = sprintf(&out[idx], + "%03u %12.6f/s %12.6f/c %12.6f/i\n", + cpu, + CFlop->State.IPS, + CFlop->State.IPC, + CFlop->State.CPI); + } else { + rdx = sprintf(&out[idx], "%03u OFF\n", cpu); + } + if (rdx > 0) { + idx += rdx; + } + } + } + out[idx++] = '\n'; + + fwrite(out, (size_t) idx, 1, stdout); + } + free(out); + } +} + +#define TOPO_MATX 13 +#define TOPO_MATY 6 + +ASCII* Topology_Std(char *pStr, unsigned int cpu) +{ + if (RO(Shm)->Cpu[cpu].Topology.BSP) { + StrFormat(&pStr[ 0], 4+(2*11)+1, "%03u:BSP%5X\x20", + cpu, + RO(Shm)->Cpu[cpu].Topology.MPID); + return RSC(TOPOLOGY_BSP_COMM).CODE(); + } else { + StrFormat(&pStr[ 0], 1+(3*11)+1, "%03u:%3d%5X\x20", + cpu, + RO(Shm)->Cpu[cpu].Topology.PackageID, + RO(Shm)->Cpu[cpu].Topology.MPID); + return NULL; + } +} + +ASCII* Topology_SMT(char *pStr, unsigned int cpu) +{ + StrFormat(pStr, 1+1+1+(2*11)+1, "%5d\x20\x20%5d\x20", + RO(Shm)->Cpu[cpu].Topology.CoreID, + RO(Shm)->Cpu[cpu].Topology.ThreadID); + return NULL; +} + +ASCII* Topology_CMP(char *pStr, unsigned int cpu) +{ + StrFormat(pStr, (3*11)+1, "%3u%4d%6d", + RO(Shm)->Cpu[cpu].Topology.Cluster.CMP, + RO(Shm)->Cpu[cpu].Topology.CoreID, + RO(Shm)->Cpu[cpu].Topology.ThreadID); + return NULL; +} + +ASCII* Topology_CCD(char *pStr, unsigned int cpu) +{ + StrFormat(pStr, (4*11)+1, "%3u%3u%4d%3d", + RO(Shm)->Cpu[cpu].Topology.Cluster.CCD, + RO(Shm)->Cpu[cpu].Topology.Cluster.CCX, + RO(Shm)->Cpu[cpu].Topology.CoreID, + RO(Shm)->Cpu[cpu].Topology.ThreadID); + return NULL; +} + +ASCII* Topology_Hybrid(char *pStr, unsigned int cpu) +{ + StrFormat(pStr, 3+(3*11)+1, "\x20%c%4X%4d%3d", + RO(Shm)->Cpu[cpu].Topology.Cluster.Hybrid_ID==Hybrid_Secondary ? + 'E' : RO(Shm)->Cpu[cpu].Topology.Cluster.Hybrid_ID==Hybrid_Primary ? + 'P' : '?', + RO(Shm)->Cpu[cpu].Topology.PN, + RO(Shm)->Cpu[cpu].Topology.CoreID, + RO(Shm)->Cpu[cpu].Topology.ThreadID); + return NULL; +} + +void Topology_Std_Update(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int cpu = data[0].ullong & CPU_MASK; + char item[1+(3*11)+1]; + + if (!BITVAL(RO(Shm)->Cpu[cpu].OffLine, OS)) { + if ((data[0].ullong & CPU_STATE_MASK) == CPU_OFFLINE) + { + memcpy(grid->cell.attr, RSC(TOPOLOGY_COND3).ATTR(), grid->cell.length); + + Topology_Std(item, cpu); + memcpy(grid->cell.item, item, grid->cell.length); + + grid->data[0].ullong = (unsigned long long) (CPU_ONLINE | cpu); + } + } else { + if ((data[0].ullong & CPU_STATE_MASK) == CPU_ONLINE) + { + size_t length; + + memcpy(grid->cell.attr, RSC(TOPOLOGY_COND4).ATTR(), grid->cell.length); + + StrLenFormat(length, item, (3*11)+1, RSC(TOPOLOGY_FMT0).CODE(), cpu); + memcpy(grid->cell.item, item, length); + + grid->data[0].ullong = (unsigned long long) (CPU_OFFLINE | cpu); + } + } +} + +void Topology_SMT_Update(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int cpu = data[0].ullong & CPU_MASK; + char item[1+1+1+(2*11)+1]; + + if (!BITVAL(RO(Shm)->Cpu[cpu].OffLine, OS)) { + if ((data[0].ullong & CPU_STATE_MASK) == CPU_OFFLINE) + { + memcpy(grid->cell.attr, RSC(TOPOLOGY_COND0).ATTR(), grid->cell.length); + + Topology_SMT(item, cpu); + memcpy(grid->cell.item, item, grid->cell.length); + + grid->data[0].ullong = (unsigned long long) (CPU_ONLINE | cpu); + } + } else { + if ((data[0].ullong & CPU_STATE_MASK) == CPU_ONLINE) + { + memcpy(grid->cell.attr, RSC(TOPOLOGY_COND1).ATTR(), grid->cell.length); + memcpy(grid->cell.item, RSC(TOPOLOGY_OFF_0).CODE(), grid->cell.length); + + grid->data[0].ullong = (unsigned long long) (CPU_OFFLINE | cpu); + } + } +} + +void Topology_CMP_Update(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int cpu = data[0].ullong & CPU_MASK; + char item[(3*11)+1]; + + if (!BITVAL(RO(Shm)->Cpu[cpu].OffLine, OS)) { + if ((data[0].ullong & CPU_STATE_MASK) == CPU_OFFLINE) + { + memcpy(grid->cell.attr, RSC(TOPOLOGY_COND0).ATTR(), grid->cell.length); + + Topology_CMP(item, cpu); + memcpy(grid->cell.item, item, grid->cell.length); + + grid->data[0].ullong = (unsigned long long) (CPU_ONLINE | cpu); + } + } else { + if ((data[0].ullong & CPU_STATE_MASK) == CPU_ONLINE) + { + memcpy(grid->cell.attr, RSC(TOPOLOGY_COND1).ATTR(), grid->cell.length); + memcpy(grid->cell.item, RSC(TOPOLOGY_OFF_1).CODE(), grid->cell.length); + + grid->data[0].ullong = (unsigned long long) (CPU_OFFLINE | cpu); + } + } +} + +void Topology_CCD_Update(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int cpu = data[0].ullong & CPU_MASK; + char item[(4*11)+1]; + + if (!BITVAL(RO(Shm)->Cpu[cpu].OffLine, OS)) { + if ((data[0].ullong & CPU_STATE_MASK) == CPU_OFFLINE) + { + memcpy(grid->cell.attr, RSC(TOPOLOGY_COND0).ATTR(), grid->cell.length); + + Topology_CCD(item, cpu); + memcpy(grid->cell.item, item, grid->cell.length); + + grid->data[0].ullong = (unsigned long long) (CPU_ONLINE | cpu); + } + } else { + if ((data[0].ullong & CPU_STATE_MASK) == CPU_ONLINE) + { + memcpy(grid->cell.attr, RSC(TOPOLOGY_COND1).ATTR(), grid->cell.length); + memcpy(grid->cell.item, RSC(TOPOLOGY_OFF_2).CODE(), grid->cell.length); + + grid->data[0].ullong = (unsigned long long) (CPU_OFFLINE | cpu); + } + } +} + +void Topology_Hybrid_Update(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int cpu = data[0].ullong & CPU_MASK; + char item[3+(3*11)+1]; + + if (!BITVAL(RO(Shm)->Cpu[cpu].OffLine, OS)) { + if ((data[0].ullong & CPU_STATE_MASK) == CPU_OFFLINE) + { + memcpy(grid->cell.attr, RSC(TOPOLOGY_COND0).ATTR(), grid->cell.length); + + Topology_Hybrid(item, cpu); + memcpy(grid->cell.item, item, grid->cell.length); + + grid->data[0].ullong = (unsigned long long) (CPU_ONLINE | cpu); + } + } else { + if ((data[0].ullong & CPU_STATE_MASK) == CPU_ONLINE) + { + memcpy(grid->cell.attr, RSC(TOPOLOGY_COND1).ATTR(), grid->cell.length); + memcpy(grid->cell.item, RSC(TOPOLOGY_OFF_3).CODE(), grid->cell.length); + + grid->data[0].ullong = (unsigned long long) (CPU_OFFLINE | cpu); + } + } +} + +void TopologyCache_Update(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int cpu = data[0].ullong & CPU_MASK, + level = data[1].uint[0]; + char item[(2*11)+1+1+1]; + + if (!BITVAL(RO(Shm)->Cpu[cpu].OffLine, OS)) { + if ((data[0].ullong & CPU_STATE_MASK) == CPU_OFFLINE) + { + size_t length; + + memcpy(grid->cell.attr, RSC(TOPOLOGY_COND0).ATTR(), grid->cell.length); + + StrLenFormat(length, item, (2*11)+1+1+1, "%8u%3u%c%c", + RO(Shm)->Cpu[cpu].Topology.Cache[level].Size, + RO(Shm)->Cpu[cpu].Topology.Cache[level].Way, + RO(Shm)->Cpu[cpu].Topology.Cache[level].Feature.WriteBack ? + 'w' : 0x20, + RO(Shm)->Cpu[cpu].Topology.Cache[level].Feature.Inclusive ? + 'i' : 0x20); + + memcpy(grid->cell.item, item, length); + + grid->data[0].ullong = (unsigned long long) (CPU_ONLINE | cpu); + } + } else { + if ((data[0].ullong & CPU_STATE_MASK) == CPU_ONLINE) + { + memcpy(grid->cell.attr, RSC(TOPOLOGY_COND1).ATTR(), grid->cell.length); + memcpy(grid->cell.item, RSC(TOPOLOGY_FMT1).CODE(), RSZ(TOPOLOGY_FMT1)); + + grid->data[0].ullong = (unsigned long long) (CPU_OFFLINE | cpu); + } + } +} + +void Topology(Window *win, CELL_FUNC OutFunc, unsigned int *cellPadding) +{ + ASCII *TopologyHeader[TOPO_MATY] = { + RSC(TOPOLOGY_HDR_PKG).CODE(), + RSC(TOPOLOGY_HDR_SMT).CODE(), + RSC(TOPOLOGY_HDR_CACHE).CODE(), + RSC(TOPOLOGY_HDR_WRBAK).CODE(), + RSC(TOPOLOGY_HDR_INCL).CODE(), + RSC(TOPOLOGY_HDR_EMPTY).CODE() + }; + ASCII *TopologySubHeader[TOPO_MATY] = { + RSC(TOPOLOGY_SUB_ITEM1).CODE(), + NULL, + RSC(TOPOLOGY_SUB_ITEM3).CODE(), + RSC(TOPOLOGY_SUB_ITEM4).CODE(), + RSC(TOPOLOGY_SUB_ITEM5).CODE(), + RSC(TOPOLOGY_SUB_ITEM6).CODE() + }; + ASCII *TopologyAltSubHeader[] = { + RSC(TOPOLOGY_ALT_ITEM1).CODE(), + RSC(TOPOLOGY_ALT_ITEM2).CODE(), + RSC(TOPOLOGY_ALT_ITEM3).CODE(), + RSC(TOPOLOGY_ALT_ITEM4).CODE() + }; + ATTRIBUTE *TopologyAttr[5] = { + RSC(TOPOLOGY_COND0).ATTR(), + RSC(TOPOLOGY_COND1).ATTR(), + RSC(TOPOLOGY_COND2).ATTR(), + RSC(TOPOLOGY_COND3).ATTR(), + RSC(TOPOLOGY_COND4).ATTR() + }; + char *strID = malloc(2 * ((4*11) + 1)); + ASCII *OffLineItem = RSC(TOPOLOGY_OFF_0).CODE(); + unsigned int cpu, level; + CUINT cells_per_line = win->matrix.size.wth, *nl = &cells_per_line; + + if (strID != NULL) + { + ASCII* (*TopologyFunc)(char*, unsigned int) = Topology_SMT; + + void (*TopologyUpdate)(struct _Grid *grid, DATA_TYPE data[]) = \ + Topology_SMT_Update; +/* Row Mark */ + PRT(MAP, TopologyAttr[2], TopologyHeader[0]); + PRT(MAP, TopologyAttr[2], TopologyHeader[1]); + PRT(MAP, TopologyAttr[2], TopologyHeader[2]); + PRT(MAP, TopologyAttr[2], TopologyHeader[3]); + PRT(MAP, TopologyAttr[2], TopologyHeader[4]); + PRT(MAP, TopologyAttr[2], TopologyHeader[5]); +/* Row Mark */ + PRT(MAP, TopologyAttr[2], TopologySubHeader[0]); + + if (RO(Shm)->Proc.Features.Hybrid) { + TopologyFunc = Topology_Hybrid; + OffLineItem = RSC(TOPOLOGY_OFF_3).CODE(); + TopologySubHeader[1] = TopologyAltSubHeader[3]; + TopologyUpdate = Topology_Hybrid_Update; + } else { + TopologyFunc = Topology_CMP; + OffLineItem = RSC(TOPOLOGY_OFF_1).CODE(); + TopologySubHeader[1] = TopologyAltSubHeader[1]; + TopologyUpdate = Topology_CMP_Update; + } + PRT(MAP, TopologyAttr[2], TopologySubHeader[1]); + PRT(MAP, TopologyAttr[2], TopologySubHeader[2]); + PRT(MAP, TopologyAttr[2], TopologySubHeader[3]); + PRT(MAP, TopologyAttr[2], TopologySubHeader[4]); + PRT(MAP, TopologyAttr[2], TopologySubHeader[5]); +/* Row Mark */ + for (cpu = 0; cpu < RO(Shm)->Proc.CPU.Count; cpu++) + { + if (!BITVAL(RO(Shm)->Cpu[cpu].OffLine, OS)) + { + ASCII *comment = Topology_Std(strID, cpu); + + GridCall(GridHover(PRT(MAP, TopologyAttr[3], strID), (char*) comment), + Topology_Std_Update, (unsigned long long) (CPU_ONLINE | cpu)); + + TopologyFunc(&strID[TOPO_MATX+1], cpu); + + GridCall(PRT(MAP, TopologyAttr[0], &strID[TOPO_MATX+1]), + TopologyUpdate, (unsigned long long) (CPU_ONLINE | cpu)); + + for (level = 0; level < CACHE_MAX_LEVEL; level++) + { + GridCall( + PRT(MAP, TopologyAttr[0], "%8u%3u%c%c", + RO(Shm)->Cpu[cpu].Topology.Cache[level].Size, + RO(Shm)->Cpu[cpu].Topology.Cache[level].Way, + RO(Shm)->Cpu[cpu].Topology.Cache[level].Feature.WriteBack ? + 'w' : 0x20, + RO(Shm)->Cpu[cpu].Topology.Cache[level].Feature.Inclusive ? + 'i' : 0x20), + TopologyCache_Update, + (unsigned long long) (CPU_ONLINE | cpu), level); + } + } else { + GridCall(PRT(MAP, TopologyAttr[4], RSC(TOPOLOGY_FMT0).CODE(), cpu), + Topology_Std_Update, (unsigned long long) (CPU_OFFLINE | cpu)); + + GridCall(PRT(MAP, TopologyAttr[1], OffLineItem), + TopologyUpdate, (unsigned long long) (CPU_OFFLINE | cpu)); + + for (level = 0; level < CACHE_MAX_LEVEL; level++) { + GridCall(PRT(MAP, TopologyAttr[1], RSC(TOPOLOGY_FMT1).CODE()), + TopologyCache_Update, + (unsigned long long) (CPU_OFFLINE | cpu), level); + } + } + } + free(strID); + } +} + +#define MC_MATX 15 /* Must be equal to or greater than 14 */ +#define MC_MATY 5 /* Must be strictly equal to 5 */ + +#define TIMING(_mc, _cha) RO(Shm)->Uncore.MC[_mc].Channel[_cha].Timing + +const char *MEM_CTRL_FMT = "%*.s"; + +void iSplit(unsigned int sInt, char hInt[]) { + char fInt[11+1]; + StrFormat(fInt, 11+1, "%10u", sInt); + memcpy((hInt + 0), (fInt + 0), 5); *(hInt + 0 + 5) = '\0'; + memcpy((hInt + 8), (fInt + 5), 5); *(hInt + 8 + 5) = '\0'; +} + +typedef void (*TIMING_FUNC)( Window*, \ + CELL_FUNC, \ + CUINT*, \ + unsigned int*, \ + unsigned short ); + +void Timing_DDR3(Window *win, + CELL_FUNC OutFunc, + CUINT *nl, + unsigned int *cellPadding, + unsigned short mc) +{ + const ASCII *Header_DDR3[2][MC_MATX] = { + { + RSC(MEM_CTRL_CHANNEL).CODE(), + RSC(DDR3_CL).CODE(), + RSC(DDR3_RCD).CODE(), + RSC(DDR3_RP).CODE(), + RSC(DDR3_RAS).CODE(), + RSC(DDR3_RRD).CODE(), + RSC(DDR3_RFC).CODE(), + RSC(DDR3_WR).CODE(), + RSC(DDR3_RTP).CODE(), + RSC(DDR3_WTP).CODE(), + RSC(DDR3_FAW).CODE(), + RSC(DDR3_B2B).CODE(), + RSC(DDR3_CWL).CODE(), + RSC(DDR3_CMD).CODE(), + RSC(DDR3_REFI).CODE() + }, + { + RSC(MEM_CTRL_MTY_CELL).CODE(), + RSC(DDR3_DDWRTRD).CODE(), + RSC(DDR3_DRWRTRD).CODE(), + RSC(DDR3_SRWRTRD).CODE(), + RSC(DDR3_DDRDTWR).CODE(), + RSC(DDR3_DRRDTWR).CODE(), + RSC(DDR3_SRRDTWR).CODE(), + RSC(DDR3_DDRDTRD).CODE(), + RSC(DDR3_DRRDTRD).CODE(), + RSC(DDR3_SRRDTRD).CODE(), + RSC(DDR3_DDWRTWR).CODE(), + RSC(DDR3_DRWRTWR).CODE(), + RSC(DDR3_SRWRTWR).CODE(), + RSC(DDR3_CKE).CODE(), + RSC(DDR3_ECC).CODE() + } + }; + const ASCII *Footer_DDR3[2][MC_MATX] = { + { + NULL, + RSC(DDR3_CL_COMM).CODE(), + RSC(DDR3_RCD_COMM).CODE(), + RSC(DDR3_RP_COMM).CODE(), + RSC(DDR3_RAS_COMM).CODE(), + RSC(DDR3_RRD_COMM).CODE(), + RSC(DDR3_RFC_COMM).CODE(), + RSC(DDR3_WR_COMM).CODE(), + RSC(DDR3_RTP_COMM).CODE(), + RSC(DDR3_WTP_COMM).CODE(), + RSC(DDR3_FAW_COMM).CODE(), + RSC(DDR3_B2B_COMM).CODE(), + RSC(DDR3_CWL_COMM).CODE(), + RSC(DDR3_CMD_COMM).CODE(), + RSC(DDR3_REFI_COMM).CODE() + }, + { + NULL, + RSC(DDR3_DDWRTRD_COMM).CODE(), + RSC(DDR3_DRWRTRD_COMM).CODE(), + RSC(DDR3_SRWRTRD_COMM).CODE(), + RSC(DDR3_DDRDTWR_COMM).CODE(), + RSC(DDR3_DRRDTWR_COMM).CODE(), + RSC(DDR3_SRRDTWR_COMM).CODE(), + RSC(DDR3_DDRDTRD_COMM).CODE(), + RSC(DDR3_DRRDTRD_COMM).CODE(), + RSC(DDR3_SRRDTRD_COMM).CODE(), + RSC(DDR3_DDWRTWR_COMM).CODE(), + RSC(DDR3_DRWRTWR_COMM).CODE(), + RSC(DDR3_SRWRTWR_COMM).CODE(), + RSC(DDR3_CKE_COMM).CODE(), + RSC(DDR3_ECC_COMM).CODE() + } + }; + ATTRIBUTE *attrib[2] = { + RSC(MEMORY_CONTROLLER_COND0).ATTR(), + RSC(MEMORY_CONTROLLER_COND1).ATTR() + }; + CUINT nc; + unsigned short cha; + + for (nc = 0; nc < MC_MATX; nc++) { + GridHover( PRT(IMC, attrib[0], Header_DDR3[0][nc]), + (char*) Footer_DDR3[0][nc] ); + } + for (cha = 0; cha < RO(Shm)->Uncore.MC[mc].ChannelCount; cha++) + { + PRT(IMC, attrib[0], "\x20\x20#%-2u", cha); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tCL); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRCD); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRP); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRAS); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRRD); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRFC); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tWR); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRTPr); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tWTPr); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tFAW); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).B2B); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tCWL); + PRT(IMC, attrib[1], "%3uT\x20", TIMING(mc, cha).CMD_Rate); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tREFI); + } + for (nc = 0; nc < MC_MATX; nc++) { + GridHover( PRT(IMC, attrib[0], Header_DDR3[1][nc]), + (char*) Footer_DDR3[1][nc] ); + } + for (cha = 0; cha < RO(Shm)->Uncore.MC[mc].ChannelCount; cha++) + { + PRT(IMC, attrib[0], "\x20\x20#%-2u", cha); + + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tddWrTRd); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tdrWrTRd); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tsrWrTRd); + + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tddRdTWr); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tdrRdTWr); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tsrRdTWr); + + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tddRdTRd); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tdrRdTRd); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tsrRdTRd); + + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tddWrTWr); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tdrWrTWr); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tsrWrTWr); + + PRT(IMC, attrib[1], "%4u\x20", TIMING(mc, cha).tCKE); + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).ECC); + } +} + +void Timing_DDR4(Window *win, + CELL_FUNC OutFunc, + CUINT *nl, + unsigned int *cellPadding, + unsigned short mc) +{ + const ASCII *Header_DDR4[3][MC_MATX] = { + { + RSC(MEM_CTRL_CHANNEL).CODE(), + RSC(DDR4_CL).CODE(), + RSC(DDR4_RCD_R).CODE(), + RSC(DDR4_RCD_W).CODE(), + RSC(DDR4_RP).CODE(), + RSC(DDR4_RAS).CODE(), + RSC(DDR4_RRD_S).CODE(), + RSC(DDR4_RRD_L).CODE(), + RSC(DDR4_FAW).CODE(), + RSC(DDR4_WR).CODE(), + RSC(DDR4_RTP).CODE(), + RSC(DDR4_WTP).CODE(), + RSC(DDR4_CWL).CODE(), + RSC(DDR4_CKE).CODE(), + RSC(DDR4_CMD).CODE() + }, + { + RSC(MEM_CTRL_MTY_CELL).CODE(), + RSC(DDR4_RDRD_SCL).CODE(), + RSC(DDR4_RDRD_SC).CODE(), + RSC(DDR4_RDRD_SD).CODE(), + RSC(DDR4_RDRD_DD).CODE(), + RSC(MEM_CTRL_MTY_CELL).CODE(), + RSC(DDR4_RDWR_SCL).CODE(), + RSC(DDR4_RDWR_SC).CODE(), + RSC(DDR4_RDWR_SD).CODE(), + RSC(DDR4_RDWR_DD).CODE(), + RSC(MEM_CTRL_MTY_CELL).CODE(), + RSC(DDR4_WRRD_SCL).CODE(), + RSC(DDR4_WRRD_SC).CODE(), + RSC(DDR4_WRRD_SD).CODE(), + RSC(DDR4_WRRD_DD).CODE() + }, + { + RSC(MEM_CTRL_MTY_CELL).CODE(), + RSC(DDR4_WRWR_SCL).CODE(), + RSC(DDR4_WRWR_SC).CODE(), + RSC(DDR4_WRWR_SD).CODE(), + RSC(DDR4_WRWR_DD).CODE(), + RSC(MEM_CTRL_MTY_CELL).CODE(), + RSC(MEM_CTRL_MTY_CELL).CODE(), + RSC(MEM_CTRL_MTY_CELL).CODE(), + RSC(DDR4_REFI).CODE(), + RSC(DDR4_RFC).CODE(), + RSC(DDR3_XS).CODE(), + RSC(DDR3_XP).CODE(), + RSC(DDR4_CPDED).CODE(), + RSC(DDR4_GEAR).CODE(), + RSC(DDR4_ECC).CODE() + } + }; + const ASCII *Footer_DDR4[3][MC_MATX] = { + { + NULL, + RSC(DDR3_CL_COMM).CODE(), + RSC(DDR4_RCD_R_COMM).CODE(), + RSC(DDR4_RCD_W_COMM).CODE(), + RSC(DDR3_RP_COMM).CODE(), + RSC(DDR3_RAS_COMM).CODE(), + RSC(DDR4_RRD_S_COMM).CODE(), + RSC(DDR4_RRD_L_COMM).CODE(), + RSC(DDR3_FAW_COMM).CODE(), + RSC(DDR3_WR_COMM).CODE(), + RSC(DDR3_RTP_COMM).CODE(), + RSC(DDR3_WTP_COMM).CODE(), + RSC(DDR3_CWL_COMM).CODE(), + RSC(DDR3_CKE_COMM).CODE(), + RSC(DDR3_CMD_COMM).CODE() + }, + { + NULL, + RSC(DDR4_RDRD_SCL_COMM).CODE(), + RSC(DDR4_RDRD_SC_COMM).CODE(), + RSC(DDR4_RDRD_SD_COMM).CODE(), + RSC(DDR4_RDRD_DD_COMM).CODE(), + NULL, + RSC(DDR4_RDWR_SCL_COMM).CODE(), + RSC(DDR4_RDWR_SC_COMM).CODE(), + RSC(DDR4_RDWR_SD_COMM).CODE(), + RSC(DDR4_RDWR_DD_COMM).CODE(), + NULL, + RSC(DDR4_WRRD_SCL_COMM).CODE(), + RSC(DDR4_WRRD_SC_COMM).CODE(), + RSC(DDR4_WRRD_SD_COMM).CODE(), + RSC(DDR4_WRRD_DD_COMM).CODE() + }, + { + NULL, + RSC(DDR4_WRWR_SCL_COMM).CODE(), + RSC(DDR4_WRWR_SC_COMM).CODE(), + RSC(DDR4_WRWR_SD_COMM).CODE(), + RSC(DDR4_WRWR_DD_COMM).CODE(), + NULL, + NULL, + NULL, + RSC(DDR3_REFI_COMM).CODE(), + RSC(DDR3_RFC_COMM).CODE(), + RSC(DDR3_XS_COMM).CODE(), + RSC(DDR3_XP_COMM).CODE(), + RSC(DDR4_CPDED_COMM).CODE(), + RSC(DDR4_GEAR_COMM).CODE(), + RSC(DDR3_ECC_COMM).CODE() + } + }; + ATTRIBUTE *attrib[2] = { + RSC(MEMORY_CONTROLLER_COND0).ATTR(), + RSC(MEMORY_CONTROLLER_COND1).ATTR() + }; + CUINT nc; + unsigned short cha; + + for (nc = 0; nc < MC_MATX; nc++) { + GridHover( PRT(IMC, attrib[0], Header_DDR4[0][nc]), + (char*) Footer_DDR4[0][nc] ); + } + for (cha = 0; cha < RO(Shm)->Uncore.MC[mc].ChannelCount; cha++) + { + PRT(IMC, attrib[0], "\x20\x20#%-2u", cha); + + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tCL); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRCD_RD); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRCD_WR); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRP); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRAS); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRRDS); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRRDL); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tFAW); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tWR); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRTPr); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tWTPr); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tCWL); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tCKE); + PRT(IMC, attrib[1], "\x20%3uT", TIMING(mc, cha).CMD_Rate); + } + for (nc = 0; nc < MC_MATX; nc++) { + GridHover( PRT(IMC, attrib[0], Header_DDR4[1][nc]), + (char*) Footer_DDR4[1][nc] ); + } + for (cha = 0; cha < RO(Shm)->Uncore.MC[mc].ChannelCount; cha++) + { + PRT(IMC, attrib[0], "\x20\x20#%-2u", cha); + + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRDRD_SG); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRDRD_DG); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRDRD_DR); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRDRD_DD); + + PRT(IMC, attrib[0], MEM_CTRL_FMT, MC_MATY, HSPACE); + + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRDWR_SG); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRDWR_DG); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRDWR_DR); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRDWR_DD); + + PRT(IMC, attrib[0], MEM_CTRL_FMT, MC_MATY, HSPACE); + + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tWRRD_SG); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tWRRD_DG); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tWRRD_DR); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tWRRD_DD); + } + for (nc = 0; nc < MC_MATX; nc++) { + GridHover( PRT(IMC, attrib[0], Header_DDR4[2][nc]), + (char*) Footer_DDR4[2][nc] ); + } + for (cha = 0; cha < RO(Shm)->Uncore.MC[mc].ChannelCount; cha++) + { + char str[16]; + + PRT(IMC, attrib[0], "\x20\x20#%-2u", cha); + + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tWRWR_SG); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tWRWR_DG); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tWRWR_DR); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tWRWR_DD); + + for (nc = 0; nc < (MC_MATX - 13); nc++) { + PRT(IMC, attrib[0], MEM_CTRL_FMT, MC_MATY, HSPACE); + } + + iSplit(TIMING(mc, cha).tREFI, str); + PRT(IMC, attrib[1], "%5s", &str[0]); + PRT(IMC, attrib[1], "%5s", &str[8]); + + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRFC); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tXS); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tXP); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tCPDED); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).GEAR); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).ECC); + } +} + +void Timing_DRAM_Zen( Window *win, + CELL_FUNC OutFunc, + CUINT *nl, + unsigned int *cellPadding, + unsigned short mc ) +{ + const ASCII *Header_DDR4_Zen[4][MC_MATX] = { + { + RSC(MEM_CTRL_CHANNEL).CODE(), + RSC(DDR4_ZEN_CL).CODE(), + RSC(DDR4_RCD_R).CODE(), + RSC(DDR4_RCD_W).CODE(), + RSC(DDR4_ZEN_RP).CODE(), + RSC(DDR4_ZEN_RAS).CODE(), + RSC(DDR4_ZEN_RC).CODE(), + RSC(DDR4_RRD_S).CODE(), + RSC(DDR4_RRD_L).CODE(), + RSC(DDR4_ZEN_FAW).CODE(), + RSC(DDR4_ZEN_WTR_S).CODE(), + RSC(DDR4_ZEN_WTR_L).CODE(), + RSC(DDR4_ZEN_WR).CODE(), + RSC(DDR4_ZEN_RDRD_SCL).CODE(), + RSC(DDR4_ZEN_WRWR_SCL).CODE() + }, + { + RSC(MEM_CTRL_MTY_CELL).CODE(), + RSC(DDR4_ZEN_CWL).CODE(), + RSC(DDR4_ZEN_RTP).CODE(), + RSC(DDR4_ZEN_RDWR).CODE(), + RSC(DDR4_ZEN_WRRD).CODE(), + RSC(DDR4_ZEN_WRWR_SC).CODE(), + RSC(DDR4_ZEN_WRWR_SD).CODE(), + RSC(DDR4_ZEN_WRWR_DD).CODE(), + RSC(DDR4_ZEN_RDRD_SC).CODE(), + RSC(DDR4_ZEN_RDRD_SD).CODE(), + RSC(DDR4_ZEN_RDRD_DD).CODE(), + RSC(DDR4_ZEN_RTR_DLR).CODE(), + RSC(DDR4_ZEN_WTW_DLR).CODE(), + RSC(DDR4_ZEN_WTR_DLR).CODE(), + RSC(DDR4_ZEN_RRD_DLR).CODE() + }, + { + RSC(MEM_CTRL_MTY_CELL).CODE(), + RSC(DDR4_ZEN_REFI).CODE(), + RSC(DDR4_ZEN_RFC1).CODE(), + RSC(DDR4_ZEN_RFC2).CODE(), + RO(Shm)->Uncore.Unit.DDR_Ver < 5 ? + RSC(DDR4_ZEN_RFC4).CODE() + : RSC(DDR5_ZEN_RFC_SB).CODE(), + RO(Shm)->Uncore.Unit.DDR_Ver < 5 ? + RSC(DDR4_ZEN_RCPB).CODE() + : RSC(DDR5_ZEN_RCPB).CODE(), + RO(Shm)->Uncore.Unit.DDR_Ver < 5 ? + RSC(DDR4_ZEN_RPPB).CODE() + : RSC(DDR5_ZEN_RPPB).CODE(), + RO(Shm)->Uncore.Unit.DDR_Ver < 5 ? + RSC(DDR4_ZEN_BGS).CODE() + : RSC(DDR5_ZEN_BGS).CODE(), + RSC(DDR4_ZEN_BGS_ALT).CODE(), + RSC(DDR4_ZEN_BAN).CODE(), + RSC(DDR4_ZEN_RCPAGE).CODE(), + RSC(DDR4_CKE).CODE(), + RSC(DDR4_CMD).CODE(), + RSC(DDR4_ZEN_GDM).CODE(), + RSC(DDR4_ZEN_ECC).CODE() + }, + { + RSC(MEM_CTRL_MTY_CELL).CODE(), + RSC(DDR4_ZEN_MRD).CODE(), + RSC(DDR4_ZEN_MRD_PDA).CODE(), + RSC(DDR4_ZEN_MOD).CODE(), + RSC(DDR4_ZEN_MOD_PDA).CODE(), + RSC(DDR4_ZEN_WRMPR).CODE(), + RSC(DDR4_ZEN_STAG).CODE(), + RSC(DDR4_ZEN_PDM).CODE(), + RSC(DDR4_ZEN_RDDATA).CODE(), + RSC(DDR4_ZEN_PHYWRD).CODE(), + RSC(DDR4_ZEN_PHYWRL).CODE(), + RSC(DDR4_ZEN_PHYRDL).CODE(), + RSC(DDR3_XS).CODE(), + RSC(DDR3_XP).CODE(), + RSC(DDR4_CPDED).CODE() + } + }; + const ASCII *Footer_DDR4_Zen[4][MC_MATX] = { + { + NULL, + RSC(DDR3_CL_COMM).CODE(), + RSC(DDR4_RCD_R_COMM).CODE(), + RSC(DDR4_RCD_W_COMM).CODE(), + RSC(DDR3_RP_COMM).CODE(), + RSC(DDR3_RAS_COMM).CODE(), + RSC(DDR4_ZEN_RC_COMM).CODE(), + RSC(DDR4_RRD_S_COMM).CODE(), + RSC(DDR4_RRD_L_COMM).CODE(), + RSC(DDR3_FAW_COMM).CODE(), + RSC(DDR4_ZEN_WTR_S_COMM).CODE(), + RSC(DDR4_ZEN_WTR_L_COMM).CODE(), + RSC(DDR3_WR_COMM).CODE(), + RSC(DDR4_ZEN_RDRD_SCL_COMM).CODE(), + RSC(DDR4_ZEN_WRWR_SCL_COMM).CODE() + }, + { + NULL, + RSC(DDR3_CWL_COMM).CODE(), + RSC(DDR4_ZEN_RTP_COMM).CODE(), + RSC(DDR4_ZEN_RDWR_COMM).CODE(), + RSC(DDR4_ZEN_WRRD_COMM).CODE(), + RSC(DDR4_ZEN_WRWR_SC_COMM).CODE(), + RSC(DDR4_ZEN_WRWR_SD_COMM).CODE(), + RSC(DDR4_ZEN_WRWR_DD_COMM).CODE(), + RSC(DDR4_ZEN_RDRD_SC_COMM).CODE(), + RSC(DDR4_ZEN_RDRD_SD_COMM).CODE(), + RSC(DDR4_ZEN_RDRD_DD_COMM).CODE(), + RSC(DDR4_ZEN_RTR_DLR_COMM).CODE(), + RSC(DDR4_ZEN_WTW_DLR_COMM).CODE(), + RSC(DDR4_ZEN_WTR_DLR_COMM).CODE(), + RSC(DDR4_ZEN_RRD_DLR_COMM).CODE() + }, + { + NULL, + RSC(DDR3_REFI_COMM).CODE(), + RSC(DDR4_ZEN_RFC1_COMM).CODE(), + RSC(DDR4_ZEN_RFC2_COMM).CODE(), + RO(Shm)->Uncore.Unit.DDR_Ver < 5 ? + RSC(DDR4_ZEN_RFC4_COMM).CODE() + : RSC(DDR5_ZEN_RFC_SB_COMM).CODE(), + RSC(DDR4_ZEN_RCPB_COMM).CODE(), + RSC(DDR4_ZEN_RPPB_COMM).CODE(), + RSC(DDR4_ZEN_BGS_COMM).CODE(), + RSC(DDR4_ZEN_BGS_ALT_COMM).CODE(), + RSC(DDR4_ZEN_BAN_COMM).CODE(), + RSC(DDR4_ZEN_RCPAGE_COMM).CODE(), + RSC(DDR3_CKE_COMM).CODE(), + RSC(DDR3_CMD_COMM).CODE(), + RSC(DDR4_ZEN_GDM_COMM).CODE(), + RSC(DDR3_ECC_COMM).CODE() + }, + { + NULL, + RSC(DDR4_ZEN_MRD_COMM).CODE(), + RSC(DDR4_ZEN_MRD_PDA_COMM).CODE(), + RSC(DDR4_ZEN_MOD_COMM).CODE(), + RSC(DDR4_ZEN_MOD_PDA_COMM).CODE(), + RSC(DDR4_ZEN_WRMPR_COMM).CODE(), + RSC(DDR4_ZEN_STAG_COMM).CODE(), + RSC(DDR4_ZEN_PDM_COMM).CODE(), + RSC(DDR4_ZEN_RDDATA_COMM).CODE(), + RSC(DDR4_ZEN_PHYWRD_COMM).CODE(), + RSC(DDR4_ZEN_PHYWRL_COMM).CODE(), + RSC(DDR4_ZEN_PHYRDL_COMM).CODE(), + RSC(DDR3_XS_COMM).CODE(), + RSC(DDR3_XP_COMM).CODE(), + RSC(DDR4_CPDED_COMM).CODE() + } + }; + ATTRIBUTE *attrib[2] = { + RSC(MEMORY_CONTROLLER_COND0).ATTR(), + RSC(MEMORY_CONTROLLER_COND1).ATTR() + }; + CUINT nc; + unsigned short cha; + + for (nc = 0; nc < MC_MATX; nc++) { + GridHover( PRT(IMC,attrib[0], Header_DDR4_Zen[0][nc]), + (char*) Footer_DDR4_Zen[0][nc] ); + } + for (cha = 0; cha < RO(Shm)->Uncore.MC[mc].ChannelCount; cha++) + { + PRT(IMC, attrib[0], "\x20\x20#%-2u", cha); + + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).tCL); + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).tRCD_RD); + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).tRCD_WR); + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).tRP); + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).tRAS); + + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).tRC); + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).tRRDS); + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).tRRDL); + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).tFAW); + + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).tWTRS); + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).tWTRL); + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).tWR); + + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).Zen.tRdRdScl); + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).Zen.tWrWrScl); + } + for (nc = 0; nc < MC_MATX; nc++) { + GridHover( PRT(IMC,attrib[0], Header_DDR4_Zen[1][nc]), + (char*) Footer_DDR4_Zen[1][nc] ); + } + for (cha = 0; cha < RO(Shm)->Uncore.MC[mc].ChannelCount; cha++) + { + PRT(IMC, attrib[0], "\x20\x20#%-2u", cha); + + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).tCWL); + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).tRTP); + + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).Zen.tddRdTWr); + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).Zen.tddWrTRd); + + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).Zen.tscWrTWr); + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).Zen.tsdWrTWr); + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).Zen.tddWrTWr); + + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).Zen.tscRdTRd); + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).Zen.tsdRdTRd); + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).Zen.tddRdTRd); + + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).Zen.tRdRdScDLR); + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).Zen.tWrWrScDLR); + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).Zen.tWrRdScDLR); + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).Zen.tRRDDLR); + } + for (nc = 0; nc < MC_MATX; nc++) { + GridHover( PRT(IMC,attrib[0], Header_DDR4_Zen[2][nc]), + (char*) Footer_DDR4_Zen[2][nc] ); + } + for (cha = 0; cha < RO(Shm)->Uncore.MC[mc].ChannelCount; cha++) + { + PRT(IMC, attrib[0], "\x20\x20#%-2u", cha); + + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tREFI); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRFC1); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRFC2); + PRT(IMC, attrib[1], "%5u", RO(Shm)->Uncore.Unit.DDR_Ver < 5 ? + TIMING(mc, cha).tRFC4 : TIMING(mc, cha).tRFCsb); + + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).tRCPB); + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).tRPPB); + + PRT(IMC, attrib[1], " %3s", ENABLED(TIMING(mc, cha).BGS)); + PRT(IMC, attrib[1], " %3s ", ENABLED(TIMING(mc, cha).BGS_ALT)); + + PRT(IMC, attrib[1], " R%1uW%1u", TIMING(mc,cha).Zen.tRdRdBan, + TIMING(mc, cha).Zen.tWrWrBan); + + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).tRCPage); + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).tCKE); + PRT(IMC, attrib[1], "%3uT ", TIMING(mc, cha).CMD_Rate); + PRT(IMC, attrib[1], " %3s", ENABLED(TIMING(mc,cha).GDM)); + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).ECC); + } + for (nc = 0; nc < MC_MATX; nc++) { + GridHover( PRT(IMC,attrib[0], Header_DDR4_Zen[3][nc]), + (char*) Footer_DDR4_Zen[3][nc] ); + } + for (cha = 0; cha < RO(Shm)->Uncore.MC[mc].ChannelCount; cha++) + { + PRT(IMC, attrib[0], "\x20\x20#%-2u", cha); + + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).tMRD); + PRT(IMC, attrib[1], " %-4u", TIMING(mc, cha).tMRD_PDA); + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).tMOD); + PRT(IMC, attrib[1], " %-4u", TIMING(mc, cha).tMOD_PDA); + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).tWRMPR); + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).tSTAG); + PRT(IMC, attrib[1],"%1u:%c:%1u",TIMING(mc, cha).PDM_AGGR, + TIMING(mc, cha).PDM_MODE ? + 'P' : 'F', + TIMING(mc, cha).PDM_EN); + PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRDDATA); + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).tPHYWRD); + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).tPHYWRL); + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).tPHYRDL); + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).tXS); + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).tXP); + PRT(IMC, attrib[1], "%4u ", TIMING(mc, cha).tCPDED); + } +} + +#undef TIMING + +void MemoryController( Window *win, + CELL_FUNC OutFunc, + unsigned int *cellPadding, + TIMING_FUNC TimingFunc ) +{ + ATTRIBUTE *attrib[2] = { + RSC(MEMORY_CONTROLLER_COND0).ATTR(), + RSC(MEMORY_CONTROLLER_COND1).ATTR() + }; + const ASCII *MC_Unit[4] = { + [MC_MHZ] = RSC(MEM_CTRL_UNIT_MHZ).CODE(), + [MC_MTS] = RSC(MEM_CTRL_UNIT_MTS).CODE(), + [MC_MBS] = RSC(MEM_CTRL_UNIT_MBS).CODE(), + [MC_NIL] = (ASCII*) MEM_CTRL_FMT + }; + char item[MC_MATY + 1], *str = malloc(CODENAME_LEN + 4 + 10), + *chipStr = malloc((MC_MATX * MC_MATY) + 1); + if ((str != NULL) && (chipStr != NULL)) + { + CUINT cells_per_line = win->matrix.size.wth, *nl = &cells_per_line, + ni, nc, li; + + unsigned short mc, cha, slot; + + StrLenFormat(li, str, CODENAME_LEN + 4 + 10, + "%s [%4hX]", + RO(Shm)->Uncore.Chipset.CodeName, + RO(Shm)->Uncore.ChipID); + + nc = (MC_MATX * MC_MATY) - li; + ni = nc >> 1; + nc = ni + (nc & 0x1); + + StrLenFormat(li, chipStr, (MC_MATX * MC_MATY) + 1, + "%.*s" "%s" "%.*s", + nc % ((MC_MATX * MC_MATY) / 2), HSPACE, + str, + ni % ((MC_MATX * MC_MATY) / 2), HSPACE); + + for (nc = 0; nc < MC_MATX; nc++) { + memcpy(item, &chipStr[nc * MC_MATY], MC_MATY); + item[MC_MATY] = '\0'; + PRT(IMC, attrib[1], item); + } + for (mc = 0; mc < RO(Shm)->Uncore.CtrlCount; mc++) + { + PRT(IMC, attrib[0], RSC(MEM_CTRL_SUBSECT1_0).CODE()); + PRT(IMC, attrib[0], RSC(MEM_CTRL_SUBSECT1_1).CODE()); + PRT(IMC, attrib[1], RSC(MEM_CTRL_SUBSECT1_2).CODE(), mc); + + for (nc = 0; nc < (MC_MATX - 6); nc++) { + PRT(IMC, attrib[0], MEM_CTRL_FMT, MC_MATY, HSPACE); + } + + switch (RO(Shm)->Uncore.MC[mc].ChannelCount) { + case 1: + PRT(IMC, attrib[1], RSC(MEM_CTRL_SINGLE_CHA_0).CODE()); + PRT(IMC, attrib[1], RSC(MEM_CTRL_SINGLE_CHA_1).CODE()); + PRT(IMC, attrib[1], RSC(MEM_CTRL_SINGLE_CHA_2).CODE()); + break; + case 2: + PRT(IMC, attrib[1], RSC(MEM_CTRL_DUAL_CHA_0).CODE()); + PRT(IMC, attrib[1], RSC(MEM_CTRL_DUAL_CHA_1).CODE()); + PRT(IMC, attrib[1], RSC(MEM_CTRL_DUAL_CHA_2).CODE()); + break; + case 3: + PRT(IMC, attrib[1], RSC(MEM_CTRL_TRIPLE_CHA_0).CODE()); + PRT(IMC, attrib[1], RSC(MEM_CTRL_TRIPLE_CHA_1).CODE()); + PRT(IMC, attrib[1], RSC(MEM_CTRL_TRIPLE_CHA_2).CODE()); + break; + case 4: + PRT(IMC, attrib[1], RSC(MEM_CTRL_QUAD_CHA_0).CODE()); + PRT(IMC, attrib[1], RSC(MEM_CTRL_QUAD_CHA_1).CODE()); + PRT(IMC, attrib[1], RSC(MEM_CTRL_QUAD_CHA_2).CODE()); + break; + case 6: + PRT(IMC, attrib[1], RSC(MEM_CTRL_SIX_CHA_0).CODE()); + PRT(IMC, attrib[1], RSC(MEM_CTRL_SIX_CHA_1).CODE()); + PRT(IMC, attrib[1], RSC(MEM_CTRL_SIX_CHA_2).CODE()); + break; + case 8: + PRT(IMC, attrib[1], RSC(MEM_CTRL_EIGHT_CHA_0).CODE()); + PRT(IMC, attrib[1], RSC(MEM_CTRL_EIGHT_CHA_1).CODE()); + PRT(IMC, attrib[1], RSC(MEM_CTRL_EIGHT_CHA_2).CODE()); + break; + default: + PRT(IMC, attrib[0], RSC(MEM_CTRL_DISABLED_0).CODE()); + PRT(IMC, attrib[0], RSC(MEM_CTRL_DISABLED_1).CODE()); + PRT(IMC, attrib[0], RSC(MEM_CTRL_DISABLED_2).CODE()); + break; + } + if (RO(Shm)->Uncore.MC[mc].ChannelCount > 0) + { + PRT(IMC, attrib[0], RSC(MEM_CTRL_BUS_RATE_0).CODE()); + PRT(IMC, attrib[0], RSC(MEM_CTRL_BUS_RATE_1).CODE()); + PRT(IMC, attrib[1], "%5llu", RO(Shm)->Uncore.Bus.Rate); + + PRT(IMC, attrib[0], MC_Unit[ + RO(Shm)->Uncore.Unit.Bus_Rate + ], MC_MATY,HSPACE); + + PRT(IMC, attrib[0], MEM_CTRL_FMT, MC_MATY, HSPACE); + + PRT(IMC, attrib[0], RSC(MEM_CTRL_BUS_SPEED_0).CODE()); + PRT(IMC, attrib[0], RSC(MEM_CTRL_BUS_SPEED_1).CODE()); + PRT(IMC, attrib[1], "%5llu", RO(Shm)->Uncore.Bus.Speed); + + PRT(IMC, attrib[0], MC_Unit[ + RO(Shm)->Uncore.Unit.BusSpeed + ], MC_MATY,HSPACE); + + for (nc = 0; nc < (MC_MATX - 14); nc++) { + PRT(IMC, attrib[0], MEM_CTRL_FMT, MC_MATY, HSPACE); + } + + switch (RO(Shm)->Uncore.Unit.DDR_Std) { + case RAM_STD_UNSPEC: + PRT(IMC, attrib[0], RSC(MEM_CTRL_RAM_STD_0).CODE()); + break; + case RAM_STD_SDRAM: + PRT(IMC, attrib[0], RSC(MEM_CTRL_RAM_STD_1).CODE()); + break; + case RAM_STD_LPDDR: + PRT(IMC, attrib[0], RSC(MEM_CTRL_RAM_STD_2).CODE()); + break; + case RAM_STD_RDIMM: + PRT(IMC, attrib[0], RSC(MEM_CTRL_RAM_STD_3).CODE()); + break; + } + switch (RO(Shm)->Uncore.Unit.DDR_Ver) { + case 2: + PRT(IMC, attrib[0], RSC(MEM_CTRL_DRAM_DDR2_0).CODE()); + break; + case 3: + PRT(IMC, attrib[0], RSC(MEM_CTRL_DRAM_DDR3_0).CODE()); + break; + case 4: + PRT(IMC, attrib[0], RSC(MEM_CTRL_DRAM_DDR4_0).CODE()); + break; + case 5: + PRT(IMC, attrib[0], RSC(MEM_CTRL_DRAM_DDR5_0).CODE()); + break; + default: + PRT(IMC, attrib[0], RSC(MEM_CTRL_DRAM_SPEED_0).CODE()); + break; + } + PRT(IMC, attrib[0], RSC(MEM_CTRL_DRAM_SPEED_1).CODE()); + PRT(IMC, attrib[1], "%5llu", RO(Shm)->Uncore.CtrlSpeed); + + PRT(IMC, attrib[0], MC_Unit[ + RO(Shm)->Uncore.Unit.DDRSpeed + ], MC_MATY,HSPACE); + + for (nc = 0; nc < MC_MATX; nc++) { + PRT(IMC, attrib[0], MEM_CTRL_FMT, MC_MATY, HSPACE); + } + + TimingFunc(win, OutFunc, nl, cellPadding, mc); + + for (nc = 0; nc < MC_MATX; nc++) { + PRT(IMC, attrib[0], MEM_CTRL_FMT, MC_MATY, HSPACE); + } + + for (cha = 0; cha < RO(Shm)->Uncore.MC[mc].ChannelCount; cha++) + { + PRT(IMC, attrib[0], RSC(MEM_CTRL_SUBSECT2_0).CODE()); + PRT(IMC, attrib[0], RSC(MEM_CTRL_SUBSECT2_1).CODE()); + PRT(IMC, attrib[0], RSC(MEM_CTRL_SUBSECT2_2).CODE()); + PRT(IMC, attrib[0], RSC(MEM_CTRL_SUBSECT2_3).CODE()); + PRT(IMC, attrib[0], RSC(MEM_CTRL_SUBSECT2_4).CODE()); + PRT(IMC, attrib[0], RSC(MEM_CTRL_SUBSECT2_5).CODE(), cha); + for (nc = 0; nc < (MC_MATX - 6); nc++) { + PRT(IMC, attrib[0], MEM_CTRL_FMT, MC_MATY, HSPACE); + } + + PRT(IMC, attrib[0], MEM_CTRL_FMT, MC_MATY, HSPACE); + PRT(IMC, attrib[0], RSC(MEM_CTRL_DIMM_SLOT).CODE()); + PRT(IMC, attrib[0], RSC(MEM_CTRL_DIMM_BANK).CODE()); + PRT(IMC, attrib[0], RSC(MEM_CTRL_DIMM_RANK).CODE()); + PRT(IMC, attrib[0], MEM_CTRL_FMT, MC_MATY, HSPACE); + PRT(IMC, attrib[0], RSC(MEM_CTRL_DIMM_ROW).CODE()); + PRT(IMC, attrib[0], RSC(MEM_CTRL_DIMM_COLUMN0).CODE()); + PRT(IMC, attrib[0], RSC(MEM_CTRL_DIMM_COLUMN1).CODE()); + PRT(IMC, attrib[0], RSC(MEM_CTRL_DIMM_SIZE_0).CODE()); + PRT(IMC, attrib[0], RSC(MEM_CTRL_DIMM_SIZE_1).CODE()); + PRT(IMC, attrib[0], RSC(MEM_CTRL_DIMM_SIZE_2).CODE()); + PRT(IMC, attrib[0], RSC(MEM_CTRL_DIMM_SIZE_3).CODE()); + for (nc = 0; nc < (MC_MATX - 12); nc++) { + PRT(IMC, attrib[0], MEM_CTRL_FMT, MC_MATY, HSPACE); + } + + for (slot = 0; slot < RO(Shm)->Uncore.MC[mc].SlotCount; slot++) + { + PRT(IMC, attrib[0], MEM_CTRL_FMT, MC_MATY, HSPACE); + PRT(IMC, attrib[0], "\x20\x20#%-2u", slot); + + if (RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Size > 0) + { + PRT(IMC, attrib[1], "%5u", + RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks); + PRT(IMC, attrib[1], "%5u", + RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks); + + iSplit(RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows,str); + PRT(IMC, attrib[1], "%5s", &str[0]); + PRT(IMC, attrib[1], "%5s", &str[8]); + + iSplit(RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols,str); + PRT(IMC, attrib[1], "%5s", &str[0]); + PRT(IMC, attrib[1], "%5s", &str[8]); + PRT(IMC, attrib[0], MEM_CTRL_FMT, MC_MATY, HSPACE); + + iSplit(RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Size,str); + PRT(IMC, attrib[1], "%5s", &str[0]); + PRT(IMC, attrib[1], "%5s", &str[8]); + + if ((li = strlen(RO(Shm)->SMB.Memory.PartNumber[slot])) > 0) + { + if (li >= (4 * MC_MATY)) { + li = (4 * MC_MATY) - 1; + } + StrFormat(str, CODENAME_LEN + 4 + 10, + "%%%d.*s", (MC_MATX - 11) * MC_MATY); + + StrFormat(chipStr, (MC_MATX * MC_MATY) + 1, + str, li, RO(Shm)->SMB.Memory.PartNumber[slot]); + + for (nc = 0; nc < (MC_MATX - 11); nc++) { + memcpy(item, &chipStr[nc * MC_MATY], MC_MATY); + item[MC_MATY] = '\0'; + PRT(IMC, attrib[1], "%5s", item); + } + } else for (nc = 0; nc < (MC_MATX - 11); nc++) { + PRT(IMC, attrib[0], MEM_CTRL_FMT, MC_MATY, HSPACE); + } + } + else for (nc = 0; nc < (MC_MATX - 2); nc++) { + PRT(IMC, attrib[0], MEM_CTRL_FMT, MC_MATY, HSPACE); + } + } + } + } + if (mc < (RO(Shm)->Uncore.CtrlCount - 1)) { + for (nc = 0; nc < MC_MATX; nc++) { + PRT(IMC, attrib[0], MEM_CTRL_FMT, MC_MATY, HSPACE); + } + } + } + } + if (str != NULL) { + free(str); + } + if (chipStr != NULL) { + free(chipStr); + } +} + +/* >>> GLOBALS >>> */ +static char *Buffer = NULL; /* Memory allocation for a mono-thread context */ + +Coordinate *cTask = NULL; + +CardList cardList = {.head = NULL, .tail = NULL}; + +struct DRAW_ST Draw = { + .Cache = { + #ifndef NO_HEADER + .TopAvg = 0.0, + #endif + #ifndef NO_FOOTER + .FreeRAM= 0, + .procCount = 0 + #endif + }, + .Flag = { + .layout = 0, + .clear = 0, + .height = 0, + .width = 0, + .daemon = 0, + .taskVal= 0, + .avgOrPC= 0, + .clkOrLd= 0, + #if defined(UBENCH) && UBENCH == 1 + .uBench = 0, + #endif + ._padding=0 + }, + .View = V_FREQ, + .Disposal = D_MAINVIEW, + .Size = { .width = 0, .height = 0 }, + .Area = { + .MinHeight = 0, .MaxRows = 0, .LoadWidth = 0, + #ifndef NO_FOOTER + .Footer = { + .VoltTemp = { + .Hot = { + [0] = MIN_WIDTH - 13, + [1] = MIN_WIDTH - 20 + }, + }, + .TaskMem = { + .Total = MIN_WIDTH - 35, + .Free = MIN_WIDTH - 22, + .Count = MIN_WIDTH - 12 + }, + }, + #endif + }, + .iClock = 0, + .cpuScroll = 0, + .Load = 0, + .Unit = { .Memory = 0 }, + .SmbIndex = SMB_BOARD_NAME, + .Theme = THM_DFLT, + #ifndef NO_UPPER + .garbage = InitCC(0) + #endif +}; + +struct RECORDER_ST Recorder = { + .Reset = 0, + .Select = 1, + .Ratios = {0, 1, 2, 10, 20, 60, 90, 120, 240, 0} +}; +/* <<< GLOBALS <<< */ + +int ByteReDim(unsigned long ival, int constraint, unsigned long *oval) +{ + if (ival > 0) + { + int base = 1 + (int) log10(ival); + + (*oval) = ival; + if (base > constraint) { + (*oval) = (*oval) >> 10; + return 1 + ByteReDim((*oval), constraint, oval); + } else { + return 0; + } + } else { + (*oval) = 0; + return 0; + } +} + +#define Threshold(value, threshold1, threshold2, _low, _medium, _high) \ +({ \ + ATTRIBUTE _retAttr; \ + if (value > threshold2) { \ + _retAttr = _high; \ + } else if (value > threshold1) { \ + _retAttr = _medium; \ + } else { \ + _retAttr = _low; \ + } \ + _retAttr; \ +}) + +#define frtostr(r, d, pStr) \ +({ \ + if (r > 0) { \ + int p = d - ((int) log10(r)) - 2 ; \ + StrFormat(pStr, d+1, "%*.*f", d, p, r) ; \ + } else { \ + StrFormat(pStr, d+1, "%.*s", d, HSPACE); \ + } \ + pStr; \ +}) + +#define Clock2LCD(layer, col, row, value1, value2) \ +({ \ + StrFormat(Buffer, 4+1, "%04.0f", value1); \ + PrintLCD(layer, col, row, 4, Buffer, \ + Threshold(value2, Ruler.Minimum, Ruler.Median, \ + RSC(UI).ATTR()[UI_LAYOUT_LCD_CLOCK_LOW], \ + RSC(UI).ATTR()[UI_LAYOUT_LCD_CLOCK_MEDIUM], \ + RSC(UI).ATTR()[UI_LAYOUT_LCD_CLOCK_HIGH])); \ +}) + +#define Counter2LCD(layer, col, row, value) \ +({ \ + StrFormat(Buffer, 4+1, "%04.0f" , value); \ + PrintLCD(layer, col, row, 4, Buffer, \ + Threshold(value, 0.f, 1.f, \ + RSC(UI).ATTR()[UI_LAYOUT_LCD_COUNTER_LOW], \ + RSC(UI).ATTR()[UI_LAYOUT_LCD_COUNTER_MEDIUM], \ + RSC(UI).ATTR()[UI_LAYOUT_LCD_COUNTER_HIGH])); \ +}) + +#define Load2LCD(layer, col, row, value) \ + PrintLCD(layer, col, row, 4, frtostr(value, 4, Buffer) , \ + Threshold(value, 100.f/3.f, 100.f/1.5f , \ + RSC(UI).ATTR()[UI_LAYOUT_LCD_LOAD_LOW] , \ + RSC(UI).ATTR()[UI_LAYOUT_LCD_LOAD_MEDIUM], \ + RSC(UI).ATTR()[UI_LAYOUT_LCD_LOAD_HIGH])) + +#define Idle2LCD(layer, col, row, value) \ + PrintLCD(layer, col, row, 4, frtostr(value, 4, Buffer) , \ + Threshold(value, 100.f/3.f, 100.f/1.5f , \ + RSC(UI).ATTR()[UI_LAYOUT_LCD_IDLE_LOW] , \ + RSC(UI).ATTR()[UI_LAYOUT_LCD_IDLE_MEDIUM], \ + RSC(UI).ATTR()[UI_LAYOUT_LCD_IDLE_HIGH])) + +#define Sys2LCD(layer, col, row, value) \ + PrintLCD(layer, col, row, 4, frtostr(value, 4, Buffer) , \ + Threshold(value, 100.f/6.6f, 50.0, \ + RSC(UI).ATTR()[UI_LAYOUT_LCD_SYSTEM_LOW], \ + RSC(UI).ATTR()[UI_LAYOUT_LCD_SYSTEM_MEDIUM], \ + RSC(UI).ATTR()[UI_LAYOUT_LCD_SYSTEM_HIGH])) + +void ForEachCellPrint_Menu(Window *win, void *plist) +{ + WinList *list = (WinList *) plist; + TGrid *spacer; + CUINT col, row; + + if (win->lazyComp.rowLen == 0) { + for (col = 0; col < win->matrix.size.wth; col++) { + win->lazyComp.rowLen += TCellAt(win, col, 0).length; + } + } + for (col = 0; col < win->matrix.size.wth; col++) { + PrintContent(win, list, col, 0); + } + for (row = 1; row < win->matrix.size.hth - 1; row++) { + if (TCellAt(win, + (win->matrix.scroll.horz + win->matrix.select.col), + (win->matrix.scroll.vert + row)).quick.key != SCANKEY_VOID) { + PrintContent(win, list, win->matrix.select.col, row); + } + } + if ((spacer = &win->grid[col * row]) != NULL) + { + const int len = Draw.Size.width + - (int) win->lazyComp.rowLen + - (int) win->matrix.origin.col; + + LayerFillAt( win->layer, + 0, win->matrix.origin.row, + spacer->cell.length, spacer->cell.item, + win->hook.color[0].title ); + spacer++; + spacer++; + + if (len > 0) { + LayerFillAt( win->layer, + (win->matrix.origin.col + win->lazyComp.rowLen), + win->matrix.origin.row, + len, spacer->cell.item, + win->hook.color[0].title); + } + } +} + +#define MENU_LEFT_LENGTH ( RSZ(MENU_ITEM_SPACER) \ + + RSZ(MENU_ITEM_MENU) \ + + RSZ(MENU_ITEM_VIEW) \ + + RSZ(MENU_ITEM_WINDOW) ) + +#define MENU_RIGHT_MARGIN (MIN_WIDTH - MENU_LEFT_LENGTH) + +#define ALLOC_DATE_TIME_FMT 24 +#define RESP_FULL_TIME_FMT 14 +#define RESP_TINY_TIME_FMT 2 + +void TOD_Refresh(TGrid *grid, DATA_TYPE data[]) +{ + size_t timeLength; + char timeString[ALLOC_DATE_TIME_FMT], *timeFormat; + struct tm *brokTime, localTime; + int pos = Draw.Size.width > MIN_WIDTH ? Draw.Size.width - MIN_WIDTH : 0; + UNUSED(data); + + time_t currTime = time(NULL); + brokTime = localtime_r(&currTime, &localTime); + + if (pos > RESP_FULL_TIME_FMT) { + timeFormat = (char*) RSC(MENU_ITEM_DATE_TIME).CODE(); + } else if (pos > RESP_TINY_TIME_FMT) { + timeFormat = (char*) RSC(MENU_ITEM_FULL_TIME).CODE(); + } else { + timeFormat = (char*) RSC(MENU_ITEM_TINY_TIME).CODE(); + } + timeLength = strftime( timeString, ALLOC_DATE_TIME_FMT, + timeFormat, brokTime ); + + pos = pos - (int) timeLength + MENU_RIGHT_MARGIN; + if (pos >= 0) { + if (pos != data[0].sint[0]) { + data[0].sint[0] = pos; + /* Clear garbage left by resizing */ + memcpy(grid->cell.item, hSpace, grid->cell.length); + } + memcpy(&grid->cell.item[pos], timeString, timeLength); + } +} + +#undef RESP_TINY_TIME_FMT +#undef RESP_FULL_TIME_FMT +#undef ALLOC_DATE_TIME_FMT +#undef MENU_RIGHT_MARGIN +#undef MENU_LEFT_LENGTH + +Window *CreateMenu(unsigned long long id, CUINT matrixSelectCol) +{ + Window *wMenu = CreateWindow( wLayer, id, + 3, 15, 3, 0, + WINFLAG_NO_STOCK + | WINFLAG_NO_SCALE + | WINFLAG_NO_BORDER ); + if (wMenu != NULL) + { +/* Top Menu */ + StoreTCell(wMenu, SCANKEY_NULL, RSC(MENU_ITEM_MENU).CODE(), + RSC(MENU_ITEM_MENU).ATTR()); + + StoreTCell(wMenu, SCANKEY_NULL, RSC(MENU_ITEM_VIEW).CODE(), + RSC(MENU_ITEM_VIEW).ATTR()); + + StoreTCell(wMenu, SCANKEY_NULL, RSC(MENU_ITEM_WINDOW).CODE(), + RSC(MENU_ITEM_WINDOW).ATTR()); +/* Row 1 */ + StoreTCell(wMenu, SCANKEY_F1, RSC(MENU_ITEM_KEYS).CODE(), + RSC(CREATE_MENU_FN_KEY).ATTR()); + + StoreTCell(wMenu, SCANKEY_d, RSC(MENU_ITEM_DASHBOARD).CODE(), + RSC(CREATE_MENU_SHORTKEY).ATTR()); + + StoreTCell(wMenu, SCANKEY_p, RSC(MENU_ITEM_PROCESSOR).CODE(), + RSC(CREATE_MENU_SHORTKEY).ATTR()); +/* Row 2 */ + StoreTCell(wMenu, SCANKEY_SHIFT_l, RSC(MENU_ITEM_LANG).CODE(), + RSC(CREATE_MENU_SHORTKEY).ATTR()); + + StoreTCell(wMenu, SCANKEY_f, RSC(MENU_ITEM_FREQUENCY).CODE(), + RSC(CREATE_MENU_SHORTKEY).ATTR()); + + StoreTCell(wMenu, SCANKEY_m, RSC(MENU_ITEM_TOPOLOGY).CODE(), + RSC(CREATE_MENU_SHORTKEY).ATTR()); +/* Row 3 */ + StoreTCell(wMenu, SCANKEY_s, RSC(MENU_ITEM_SETTINGS).CODE(), + RSC(CREATE_MENU_SHORTKEY).ATTR()); + +#ifndef NO_LOWER + StoreTCell(wMenu, SCANKEY_i, RSC(MENU_ITEM_INST_CYCLES).CODE(), + RSC(CREATE_MENU_SHORTKEY).ATTR()); +#else + StoreTCell(wMenu, SCANKEY_i, RSC(MENU_ITEM_INST_CYCLES).CODE(), + RSC(CREATE_MENU_DISABLE).ATTR()); +#endif + + StoreTCell(wMenu, SCANKEY_e, RSC(MENU_ITEM_FEATURES).CODE(), + RSC(CREATE_MENU_SHORTKEY).ATTR()); +/* Row 4 */ + StoreTCell(wMenu, SCANKEY_SHIFT_b, RSC(MENU_ITEM_SMBIOS).CODE(), + RSC(CREATE_MENU_SHORTKEY).ATTR()); + +#ifndef NO_LOWER + StoreTCell(wMenu, SCANKEY_c, RSC(MENU_ITEM_CORE_CYCLES).CODE(), + RSC(CREATE_MENU_SHORTKEY).ATTR()); +#else + StoreTCell(wMenu, SCANKEY_c, RSC(MENU_ITEM_CORE_CYCLES).CODE(), + RSC(CREATE_MENU_DISABLE).ATTR()); +#endif + + StoreTCell(wMenu, SCANKEY_SHIFT_i, RSC(MENU_ITEM_ISA_EXT).CODE(), + RSC(CREATE_MENU_SHORTKEY).ATTR()); +/* Row 5 */ + StoreTCell(wMenu, SCANKEY_k, RSC(MENU_ITEM_KERNEL).CODE(), + RSC(CREATE_MENU_SHORTKEY).ATTR()); + +#ifndef NO_LOWER + StoreTCell(wMenu, SCANKEY_l, RSC(MENU_ITEM_IDLE_STATES).CODE(), + RSC(CREATE_MENU_SHORTKEY).ATTR()); +#else + StoreTCell(wMenu, SCANKEY_l, RSC(MENU_ITEM_IDLE_STATES).CODE(), + RSC(CREATE_MENU_DISABLE).ATTR()); +#endif + + StoreTCell(wMenu, SCANKEY_t, RSC(MENU_ITEM_TECH).CODE(), + RSC(CREATE_MENU_SHORTKEY).ATTR()); +/* Row 6 */ + StoreTCell(wMenu, SCANKEY_HASH, RSC(MENU_ITEM_HOTPLUG).CODE(), + RSC(CREATE_MENU_SHORTKEY).ATTR()); + +#ifndef NO_LOWER + StoreTCell(wMenu, SCANKEY_g, RSC(MENU_ITEM_PKG_CYCLES).CODE(), + RSC(CREATE_MENU_SHORTKEY).ATTR()); +#else + StoreTCell(wMenu, SCANKEY_g, RSC(MENU_ITEM_PKG_CYCLES).CODE(), + RSC(CREATE_MENU_DISABLE).ATTR()); +#endif + + StoreTCell(wMenu, SCANKEY_o, RSC(MENU_ITEM_PERF_MON).CODE(), + RSC(CREATE_MENU_SHORTKEY).ATTR()); +/* Row 7 */ + StoreTCell(wMenu, SCANKEY_SHIFT_o, RSC(MENU_ITEM_TOOLS).CODE(), + RO(Shm)->Registration.Experimental ? + RSC(CREATE_MENU_SHORTKEY).ATTR() + : RSC(CREATE_MENU_DISABLE).ATTR()); + +#ifndef NO_LOWER + StoreTCell(wMenu, SCANKEY_x, RSC(MENU_ITEM_TASKS_MON).CODE(), + BITWISEAND(LOCKLESS, RO(Shm)->SysGate.Operation, 0x1) ? + RSC(CREATE_MENU_SHORTKEY).ATTR() + : RSC(CREATE_MENU_DISABLE).ATTR()); +#else + StoreTCell(wMenu, SCANKEY_x, RSC(MENU_ITEM_TASKS_MON).CODE(), + RSC(CREATE_MENU_DISABLE).ATTR()); +#endif + + StoreTCell(wMenu, SCANKEY_z, RSC(MENU_ITEM_PERF_CAPS).CODE(), + RSC(CREATE_MENU_SHORTKEY).ATTR()); +/* Row 8 */ + StoreTCell(wMenu, SCANKEY_SHIFT_e, RSC(MENU_ITEM_THEME).CODE(), + RSC(CREATE_MENU_SHORTKEY).ATTR()); + +#ifndef NO_LOWER + StoreTCell(wMenu, SCANKEY_q, RSC(MENU_ITEM_SYS_INTER).CODE(), + RSC(CREATE_MENU_SHORTKEY).ATTR()); +#else + StoreTCell(wMenu, SCANKEY_q, RSC(MENU_ITEM_SYS_INTER).CODE(), + RSC(CREATE_MENU_DISABLE).ATTR()); +#endif + + StoreTCell(wMenu, SCANKEY_w, RSC(MENU_ITEM_POW_THERM).CODE(), + RSC(CREATE_MENU_SHORTKEY).ATTR()); +/* Row 9 */ + StoreTCell(wMenu, SCANKEY_a, RSC(MENU_ITEM_ABOUT).CODE(), + RSC(CREATE_MENU_SHORTKEY).ATTR()); + +#ifndef NO_LOWER + StoreTCell(wMenu, SCANKEY_SHIFT_c, RSC(MENU_ITEM_SENSORS).CODE(), + RSC(CREATE_MENU_SHORTKEY).ATTR()); +#else + StoreTCell(wMenu, SCANKEY_SHIFT_c, RSC(MENU_ITEM_SENSORS).CODE(), + RSC(CREATE_MENU_DISABLE).ATTR()); +#endif + + StoreTCell(wMenu, SCANKEY_SHIFT_r, RSC(MENU_ITEM_SYS_REGS).CODE(), + RSC(CREATE_MENU_SHORTKEY).ATTR()); + +/* Row 10 */ + StoreTCell(wMenu, SCANKEY_h, RSC(MENU_ITEM_HELP).CODE(), + RSC(CREATE_MENU_SHORTKEY).ATTR()); + +#ifndef NO_LOWER + StoreTCell(wMenu, SCANKEY_SHIFT_v, RSC(MENU_ITEM_VOLTAGE).CODE(), + RSC(CREATE_MENU_SHORTKEY).ATTR()); +#else + StoreTCell(wMenu, SCANKEY_SHIFT_v, RSC(MENU_ITEM_VOLTAGE).CODE(), + RSC(CREATE_MENU_DISABLE).ATTR()); +#endif + + StoreTCell(wMenu, SCANKEY_SHIFT_m, RSC(MENU_ITEM_MEM_CTRL).CODE(), + RO(Shm)->Uncore.CtrlCount > 0 ? + RSC(CREATE_MENU_SHORTKEY).ATTR() + : RSC(CREATE_MENU_DISABLE).ATTR()); +/* Row 11 */ + StoreTCell(wMenu, SCANKEY_CTRL_x, RSC(MENU_ITEM_QUIT).CODE(), + RSC(CREATE_MENU_CTRL_KEY).ATTR()); + +#ifndef NO_LOWER + StoreTCell(wMenu, SCANKEY_SHIFT_w, RSC(MENU_ITEM_POWER).CODE(), + RSC(CREATE_MENU_SHORTKEY).ATTR()); +#else + StoreTCell(wMenu, SCANKEY_SHIFT_w, RSC(MENU_ITEM_POWER).CODE(), + RSC(CREATE_MENU_DISABLE).ATTR()); +#endif + + StoreTCell(wMenu, SCANKEY_SHIFT_h, RSC(MENU_ITEM_EVENTS).CODE(), + RSC(CREATE_MENU_SHORTKEY).ATTR()); +/* Row 12 */ + StoreTCell(wMenu, SCANKEY_VOID, "", RSC(VOID).ATTR()); + +#ifndef NO_LOWER + StoreTCell(wMenu, SCANKEY_SHIFT_t, RSC(MENU_ITEM_SLICE_CTRS).CODE(), + RSC(CREATE_MENU_SHORTKEY).ATTR()); +#else + StoreTCell(wMenu, SCANKEY_SHIFT_t, RSC(MENU_ITEM_SLICE_CTRS).CODE(), + RSC(CREATE_MENU_DISABLE).ATTR()); +#endif + + StoreTCell(wMenu, SCANKEY_VOID, "", RSC(VOID).ATTR()); +/* Row 13 */ + StoreTCell(wMenu, SCANKEY_VOID, "", RSC(VOID).ATTR()); + +#ifndef NO_LOWER + StoreTCell(wMenu, SCANKEY_y, RSC(MENU_ITEM_CUSTOM).CODE(), + RSC(CREATE_MENU_SHORTKEY).ATTR()); +#else + StoreTCell(wMenu, SCANKEY_y, RSC(MENU_ITEM_CUSTOM).CODE(), + RSC(CREATE_MENU_DISABLE).ATTR()); +#endif + + StoreTCell(wMenu, SCANKEY_VOID, "", RSC(VOID).ATTR()); +/* Menu Spacers */ + StoreTCell(wMenu, SCANKEY_VOID, RSC(MENU_ITEM_SPACER).CODE(), + RSC(UI).ATTR()[UI_WIN_MENU_TITLE_UNFOCUS]); + + StoreTCell(wMenu, SCANKEY_VOID, "", RSC(VOID).ATTR()); + + GridCall( + StoreTCell(wMenu, SCANKEY_VOID, hSpace, + RSC(UI).ATTR()[UI_WIN_MENU_TITLE_UNFOCUS]), + TOD_Refresh, 0); +/* Bottom Menu */ + StoreWindow(wMenu, .color[0].select, + RSC(UI).ATTR()[UI_WIN_MENU_UNSELECT]); + + StoreWindow(wMenu, .color[1].select, + RSC(UI).ATTR()[UI_WIN_MENU_SELECT]); + + StoreWindow(wMenu, .color[0].title, + RSC(UI).ATTR()[UI_WIN_MENU_TITLE_UNFOCUS]); + + StoreWindow(wMenu, .color[1].title, + RSC(UI).ATTR()[UI_WIN_MENU_TITLE_FOCUS]); + + wMenu->matrix.select.col = matrixSelectCol; + + StoreWindow(wMenu, .Print , ForEachCellPrint_Menu); + StoreWindow(wMenu, .key.Enter, MotionEnter_Cell); + StoreWindow(wMenu, .key.Left, MotionLeft_Menu); + StoreWindow(wMenu, .key.Right, MotionRight_Menu); + StoreWindow(wMenu, .key.Down, MotionDown_Menu); + StoreWindow(wMenu, .key.Up, MotionUp_Menu); + StoreWindow(wMenu, .key.Home, MotionHome_Menu); + StoreWindow(wMenu, .key.End, MotionEnd_Menu); + } + return wMenu; +} + +void IntervalUpdate(TGrid *grid, DATA_TYPE data[]) +{ + UNUSED(data); + StrFormat(Buffer, 10+1, "%4u", RO(Shm)->Sleep.Interval); + memcpy(&grid->cell.item[grid->cell.length - 6], Buffer, 4); +} + +void SysTickUpdate(TGrid *grid, DATA_TYPE data[]) +{ + UNUSED(data); + StrFormat(Buffer, 10+1, "%4u", + RO(Shm)->Sleep.Interval*RO(Shm)->SysGate.tickReset); + + memcpy(&grid->cell.item[grid->cell.length - 6], Buffer, 4); +} + +void SvrWaitUpdate(TGrid *grid, DATA_TYPE data[]) +{ + StrFormat(Buffer, 21+1, "%4ld", (*data[0].pslong) / 1000000L); + memcpy(&grid->cell.item[grid->cell.length - 6], Buffer, 4); +} + +void RecorderUpdate(TGrid *grid, DATA_TYPE data[]) +{ + unsigned int duration = RECORDER_SECONDS((*data[0].puint), + RO(Shm)->Sleep.Interval); + if (duration <= 9999) { + StrFormat(Buffer, 11+1, "%4u", duration); + memcpy(&grid->cell.item[grid->cell.length - 6], Buffer, 4); + } +} + +void SettingUpdate(TGrid *grid, const unsigned int bix, const int pos, + const size_t len, const char *item) +{ + ATTRIBUTE *attrib[2] = { + RSC(CREATE_SETTINGS_COND0).ATTR(), + RSC(CREATE_SETTINGS_COND1).ATTR() + }; + memcpy(&grid->cell.attr[pos], &attrib[bix][pos], len); + memcpy(&grid->cell.item[pos], item, len); +} + +void AutoClockUpdate(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int bix = (RO(Shm)->Registration.AutoClock & 0b10) != 0; + const signed int pos = grid->cell.length - 5; + UNUSED(data); + + SettingUpdate(grid, bix, pos, 3, ENABLED(bix)); +} + +void ExperimentalUpdate(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int bix = RO(Shm)->Registration.Experimental != 0; + const signed int pos = grid->cell.length - 5; + UNUSED(data); + + SettingUpdate(grid, bix, pos, 3, ENABLED(bix)); +} + +void HotPlug_Update(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int bix = !(RO(Shm)->Registration.HotPlug < 0); + const signed int pos = grid->cell.length - 5; + UNUSED(data); + + SettingUpdate(grid, bix, pos, 3, ENABLED(bix)); +} + +void PCI_Probe_Update(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int bix = RO(Shm)->Registration.PCI == 1; + const signed int pos = grid->cell.length - 5; + UNUSED(data); + + SettingUpdate(grid, bix, pos, 3, ENABLED(bix)); +} + +void IdleRoute_Update(TGrid *grid, DATA_TYPE data[]) +{ + const ASCII *instructions[ROUTE_SIZE] = { + [ROUTE_DEFAULT] = RSC(SETTINGS_ROUTE_DFLT).CODE(), + [ROUTE_IO] = RSC(SETTINGS_ROUTE_IO).CODE(), + [ROUTE_HALT] = RSC(SETTINGS_ROUTE_HALT).CODE(), + [ROUTE_MWAIT] = RSC(SETTINGS_ROUTE_MWAIT).CODE() + }; + const unsigned int bix = RO(Shm)->Registration.Driver.CPUidle + & REGISTRATION_ENABLE; + const size_t size = (size_t) RSZ(SETTINGS_ROUTE_DFLT); + UNUSED(data); + + memcpy(&grid->cell.item[grid->cell.length - size - 2], + instructions[RO(Shm)->Registration.Driver.Route], size); + + grid->cell.item[grid->cell.length - 2] = bix ? '>' : ']'; + grid->cell.item[grid->cell.length - 10] = bix ? '<' : '['; + grid->cell.quick.key = bix ? OPS_IDLE_ROUTE : SCANKEY_NULL; +} + +void NMI_Registration_Update(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int bix = BITWISEAND( LOCKLESS, + RO(Shm)->Registration.NMI, + BIT_NMI_MASK ) != 0; + const signed int pos = grid->cell.length - 5; + UNUSED(data); + + SettingUpdate(grid, bix, pos, 3, ENABLED(bix)); +} + +void CPU_Idle_Update(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int bix = RO(Shm)->Registration.Driver.CPUidle + & REGISTRATION_ENABLE; + + const signed int pos = grid->cell.length - 5; + UNUSED(data); + + SettingUpdate(grid, bix, pos, 3, ENABLED(bix)); +} + +void CPU_Freq_Update(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int bix = RO(Shm)->Registration.Driver.CPUfreq + & REGISTRATION_ENABLE; + + const signed int pos = grid->cell.length - 5; + UNUSED(data); + + SettingUpdate(grid, bix, pos, 3, ENABLED(bix)); +} + +void Governor_Update(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int bix = RO(Shm)->Registration.Driver.Governor + & REGISTRATION_ENABLE; + + const signed int pos = grid->cell.length - 5; + UNUSED(data); + + SettingUpdate(grid, bix, pos, 3, ENABLED(bix)); +} + +void ClockSource_Update(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int bix = RO(Shm)->Registration.Driver.CS + & REGISTRATION_ENABLE; + + const signed int pos = grid->cell.length - 5; + UNUSED(data); + + SettingUpdate(grid, bix, pos, 3, ENABLED(bix)); +} + +void ScopeUpdate(TGrid *grid, DATA_TYPE data[]) +{ + ASCII *code[] = { + RSC(SCOPE_NONE).CODE(), + RSC(SCOPE_THREAD).CODE(), + RSC(SCOPE_CORE).CODE(), + RSC(SCOPE_PACKAGE).CODE() + }; + const enum FORMULA_SCOPE scope = SCOPE_OF_FORMULA(*data[0].psint); + const size_t size = (size_t) RSZ(SCOPE_NONE); + memcpy(&grid->cell.item[grid->cell.length - size-2], code[scope], size); +} + +Window *CreateSettings(unsigned long long id) +{ + const CUINT height = 25; + Window *wSet = CreateWindow(wLayer, id, 1, height, 8, TOP_HEADER_ROW+2); + if (wSet != NULL) + { + ATTRIBUTE *attrib[2] = { + RSC(CREATE_SETTINGS_COND0).ATTR(), + RSC(CREATE_SETTINGS_COND1).ATTR() + }; + TGrid *grid; + unsigned int bix; + + StoreTCell(wSet, SCANKEY_NULL, RSC(CREATE_SETTINGS_COND0).CODE(), + MAKE_PRINT_UNFOCUS); + + grid = StoreTCell(wSet, SCANKEY_NULL, RSC(SETTINGS_DAEMON).CODE(), + MAKE_PRINT_UNFOCUS); + if (grid != NULL) { + const size_t length = strlen(RO(Shm)->ShmName); + memcpy(&grid->cell.item[grid->cell.length - length - 1], + RO(Shm)->ShmName, length); + } + GridCall( StoreTCell( wSet, OPS_INTERVAL, + RSC(SETTINGS_INTERVAL).CODE(), + MAKE_PRINT_UNFOCUS ), + IntervalUpdate ); + + GridCall( StoreTCell( wSet, SCANKEY_NULL, + RSC(SETTINGS_SYS_TICK).CODE(), + MAKE_PRINT_UNFOCUS ), + SysTickUpdate ); + + GridCall( StoreTCell( wSet, SCANKEY_NULL, + RSC(SETTINGS_POLL_WAIT).CODE(), + MAKE_PRINT_UNFOCUS ), + SvrWaitUpdate, &RO(Shm)->Sleep.pollingWait.tv_nsec ); + + GridCall( StoreTCell( wSet, SCANKEY_NULL, + RSC(SETTINGS_RING_WAIT).CODE(), + MAKE_PRINT_UNFOCUS ), + SvrWaitUpdate, &RO(Shm)->Sleep.ringWaiting.tv_nsec ); + + GridCall( StoreTCell( wSet, SCANKEY_NULL, + RSC(SETTINGS_CHILD_WAIT).CODE(), + MAKE_PRINT_UNFOCUS ), + SvrWaitUpdate, &RO(Shm)->Sleep.childWaiting.tv_nsec ); + + GridCall( StoreTCell( wSet, SCANKEY_NULL, + RSC(SETTINGS_SLICE_WAIT).CODE(), + MAKE_PRINT_UNFOCUS ), + SvrWaitUpdate, &RO(Shm)->Sleep.sliceWaiting.tv_nsec ); + + GridCall( StoreTCell( wSet, OPS_RECORDER, + RSC(SETTINGS_RECORDER).CODE(), + MAKE_PRINT_UNFOCUS ), + RecorderUpdate, &Recorder.Reset ); + + StoreTCell(wSet, SCANKEY_NULL, RSC(CREATE_SETTINGS_COND0).CODE(), + MAKE_PRINT_UNFOCUS); + + bix = ((RO(Shm)->Registration.AutoClock & 0b10) != 0); + GridCall( StoreTCell( wSet, OPS_AUTOCLOCK, + RSC(SETTINGS_AUTO_CLOCK).CODE(), + attrib[bix] ), + AutoClockUpdate ); + + bix = (RO(Shm)->Registration.Experimental != 0); + GridCall( StoreTCell( wSet, OPS_EXPERIMENTAL, + RSC(SETTINGS_EXPERIMENTAL).CODE(), + attrib[bix] ), + ExperimentalUpdate ); + + bix = !(RO(Shm)->Registration.HotPlug < 0); + GridCall( StoreTCell( wSet, SCANKEY_NULL, + RSC(SETTINGS_CPU_HOTPLUG).CODE(), + attrib[bix] ), + HotPlug_Update ); + + bix = (RO(Shm)->Registration.PCI == 1); + GridCall( StoreTCell( wSet, SCANKEY_NULL, + RSC(SETTINGS_PCI_ENABLED).CODE(), + attrib[bix] ), + PCI_Probe_Update ); + + bix=BITWISEAND(LOCKLESS, RO(Shm)->Registration.NMI, BIT_NMI_MASK) != 0; + GridCall( StoreTCell( wSet, OPS_INTERRUPTS, + RSC(SETTINGS_NMI_REGISTERED).CODE(), + attrib[bix] ), + NMI_Registration_Update ); + + bix = RO(Shm)->Registration.Driver.CPUidle & REGISTRATION_ENABLE; + grid = GridCall( StoreTCell( wSet, bix ? OPS_IDLE_ROUTE:SCANKEY_NULL, + RSC(SETTINGS_IDLE_ROUTE).CODE(), + MAKE_PRINT_UNFOCUS ), + IdleRoute_Update ); + if (grid != NULL) { + grid->cell.item[grid->cell.length - 2] = bix ? '>' : ']'; + grid->cell.item[grid->cell.length - 10] = bix ? '<' : '['; + } + + GridCall( StoreTCell( wSet, OPS_CPU_IDLE, + RSC(SETTINGS_CPUIDLE_REGISTERED).CODE(), + attrib[bix] ), + CPU_Idle_Update ); + + bix = RO(Shm)->Registration.Driver.CPUfreq & REGISTRATION_ENABLE; + GridCall( StoreTCell( wSet, OPS_CPU_FREQ, + RSC(SETTINGS_CPUFREQ_REGISTERED).CODE(), + attrib[bix] ), + CPU_Freq_Update ); + + bix = RO(Shm)->Registration.Driver.Governor & REGISTRATION_ENABLE; + GridCall( StoreTCell( wSet, OPS_GOVERNOR, + RSC(SETTINGS_GOVERNOR_REGISTERED).CODE(), + attrib[bix] ), + Governor_Update ); + + bix = RO(Shm)->Registration.Driver.CS & REGISTRATION_ENABLE; + GridCall( StoreTCell( wSet, OPS_CLOCK_SOURCE, + RSC(SETTINGS_CS_REGISTERED).CODE(), + attrib[bix] ), + ClockSource_Update ); + + StoreTCell(wSet, SCANKEY_NULL, RSC(CREATE_SETTINGS_COND0).CODE(), + MAKE_PRINT_UNFOCUS); + + GridCall( StoreTCell( wSet, OPS_THERMAL_SCOPE, + RSC(SETTINGS_THERMAL_SCOPE).CODE(), + MAKE_PRINT_UNFOCUS ), + ScopeUpdate, &RO(Shm)->Proc.thermalFormula ); + + GridCall( StoreTCell( wSet, OPS_VOLTAGE_SCOPE, + RSC(SETTINGS_VOLTAGE_SCOPE).CODE(), + MAKE_PRINT_UNFOCUS ), + ScopeUpdate, &RO(Shm)->Proc.voltageFormula ); + + GridCall( StoreTCell( wSet, OPS_POWER_SCOPE, + RSC(SETTINGS_POWER_SCOPE).CODE(), + MAKE_PRINT_UNFOCUS ), + ScopeUpdate, &RO(Shm)->Proc.powerFormula ); + + StoreTCell(wSet, SCANKEY_NULL, RSC(CREATE_SETTINGS_COND0).CODE(), + MAKE_PRINT_UNFOCUS); + + StoreWindow(wSet, .title, (char*) RSC(SETTINGS_TITLE).CODE()); + + StoreWindow(wSet, .key.WinLeft, MotionOriginLeft_Win); + StoreWindow(wSet, .key.WinRight, MotionOriginRight_Win); + StoreWindow(wSet, .key.WinDown, MotionOriginDown_Win); + StoreWindow(wSet, .key.WinUp, MotionOriginUp_Win); + StoreWindow(wSet, .key.Enter, Enter_StickyCell); + StoreWindow(wSet, .key.Down, MotionDown_Win); + StoreWindow(wSet, .key.Up, MotionUp_Win); + StoreWindow(wSet, .key.PgUp, MotionPgUp_Win); + StoreWindow(wSet, .key.PgDw, MotionPgDw_Win); + StoreWindow(wSet, .key.Home, MotionReset_Win); + StoreWindow(wSet, .key.End, MotionEnd_Cell); + StoreWindow(wSet, .key.Shrink, MotionShrink_Win); + StoreWindow(wSet, .key.Expand, MotionExpand_Win); + } + return wSet; +} + +Window *CreateHelp(unsigned long long id) +{ + Window *wHelp = CreateWindow(wLayer, id, 2, 19, 2, TOP_HEADER_ROW+1); + if (wHelp != NULL) + { + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_BLANK).CODE(), + MAKE_PRINT_UNFOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_BLANK).CODE(), + MAKE_PRINT_UNFOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_KEY_MENU).CODE(), + MAKE_PRINT_FOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_MENU).CODE(), + MAKE_PRINT_UNFOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_KEY_ESCAPE).CODE(), + MAKE_PRINT_FOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_CLOSE_WINDOW).CODE(), + MAKE_PRINT_UNFOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_KEY_SHIFT_TAB).CODE(), + MAKE_PRINT_FOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_PREV_WINDOW).CODE(), + MAKE_PRINT_UNFOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_KEY_TAB).CODE(), + MAKE_PRINT_FOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_NEXT_WINDOW).CODE(), + MAKE_PRINT_UNFOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_KEY_SHIFT_GR1).CODE(), + MAKE_PRINT_FOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_BLANK).CODE(), + MAKE_PRINT_UNFOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_KEY_SHIFT_GR2).CODE(), + MAKE_PRINT_FOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_MOVE_WINDOW).CODE(), + MAKE_PRINT_UNFOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_KEY_ALT_GR3).CODE(), + MAKE_PRINT_FOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_SIZE_WINDOW).CODE(), + MAKE_PRINT_UNFOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_KEY_UP).CODE(), + MAKE_PRINT_FOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_BLANK).CODE(), + MAKE_PRINT_UNFOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_KEY_LEFT_RIGHT).CODE(), + MAKE_PRINT_FOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_MOVE_SELECT).CODE(), + MAKE_PRINT_UNFOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_KEY_DOWN).CODE(), + MAKE_PRINT_FOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_BLANK).CODE(), + MAKE_PRINT_UNFOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_KEY_END).CODE(), + MAKE_PRINT_FOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_LAST_CELL).CODE(), + MAKE_PRINT_UNFOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_KEY_HOME).CODE(), + MAKE_PRINT_FOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_FIRST_CELL).CODE(), + MAKE_PRINT_UNFOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_KEY_ENTER).CODE(), + MAKE_PRINT_FOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_TRIGGER_SELECT).CODE(), + MAKE_PRINT_UNFOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_KEY_PAGE_UP).CODE(), + MAKE_PRINT_FOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_PREV_PAGE).CODE(), + MAKE_PRINT_UNFOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_KEY_PAGE_DOWN).CODE(), + MAKE_PRINT_FOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_NEXT_PAGE).CODE(), + MAKE_PRINT_UNFOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_KEY_MINUS).CODE(), + MAKE_PRINT_FOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_SCROLL_DOWN).CODE(), + MAKE_PRINT_UNFOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_KEY_PLUS).CODE(), + MAKE_PRINT_FOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_SCROLL_UP).CODE(), + MAKE_PRINT_UNFOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_BLANK).CODE(), + MAKE_PRINT_UNFOCUS); + StoreTCell(wHelp, SCANKEY_NULL, RSC(HELP_BLANK).CODE(), + MAKE_PRINT_UNFOCUS); + + StoreWindow(wHelp, .title, (char*) RSC(HELP_TITLE).CODE()); + StoreWindow(wHelp, .color[0].select, MAKE_PRINT_UNFOCUS); + StoreWindow(wHelp, .color[1].select, MAKE_PRINT_FOCUS); + + StoreWindow(wHelp, .key.WinLeft, MotionOriginLeft_Win); + StoreWindow(wHelp, .key.WinRight, MotionOriginRight_Win); + StoreWindow(wHelp, .key.WinDown, MotionOriginDown_Win); + StoreWindow(wHelp, .key.WinUp, MotionOriginUp_Win); + StoreWindow(wHelp, .key.Down, MotionDown_Win); + StoreWindow(wHelp, .key.Up, MotionUp_Win); + StoreWindow(wHelp, .key.PgUp, MotionPgUp_Win); + StoreWindow(wHelp, .key.PgDw, MotionPgDw_Win); + StoreWindow(wHelp, .key.Home, MotionReset_Win); + StoreWindow(wHelp, .key.End, MotionEnd_Cell); + StoreWindow(wHelp, .key.Shrink, MotionShrink_Win); + StoreWindow(wHelp, .key.Expand, MotionExpand_Win); + } + return wHelp; +} + +Window *CreateAdvHelp(unsigned long long id) +{ + ATTRIBUTE *attrib[2] = { + RSC(CREATE_ADV_HELP_COND0).ATTR(), + RSC(CREATE_ADV_HELP_COND1).ATTR() + }; + struct ADV_HELP_ST { + short theme; + ASCII *item; + SCANKEY quick; + } advHelp[] = { + {0, RSC(CREATE_ADV_HELP_COND0).CODE(), {SCANKEY_NULL} }, + {0, RSC(ADV_HELP_SECT_FREQ).CODE(), {SCANKEY_NULL} }, + {1, RSC(ADV_HELP_ITEM_AVG).CODE(), {SCANKEY_PERCENT}}, + {0, RSC(CREATE_ADV_HELP_COND0).CODE(), {SCANKEY_NULL} }, + {0, RSC(ADV_HELP_SECT_TASK).CODE(), {SCANKEY_NULL} }, + {1, RSC(ADV_HELP_ITEM_ORDER).CODE(), {SCANKEY_b} }, + {1, RSC(ADV_HELP_ITEM_RST).CODE(), {SCANKEY_SHIFT_n}}, + {1, RSC(ADV_HELP_ITEM_SEL).CODE(), {SCANKEY_n} }, + {1, RSC(ADV_HELP_ITEM_REV).CODE(), {SCANKEY_r} }, + {1, RSC(ADV_HELP_ITEM_HIDE).CODE(), {SCANKEY_v} }, + {0, RSC(CREATE_ADV_HELP_COND0).CODE(), {SCANKEY_NULL} }, + {0, RSC(ADV_HELP_SECT_ANY).CODE(), {SCANKEY_NULL} }, + {1, RSC(ADV_HELP_ITEM_POWER).CODE(), {SCANKEY_DOLLAR}}, + {1, RSC(ADV_HELP_ITEM_TOP).CODE(), {SCANKEY_DOT} }, + {1, RSC(ADV_HELP_ITEM_FAHR_CELS).CODE(),{SCANKEY_SHIFT_f}}, + {1, RSC(ADV_HELP_ITEM_SYSGATE).CODE(), {SCANKEY_SHIFT_g}}, + {1, RSC(ADV_HELP_ITEM_PROC_EVENT).CODE(),{SCANKEY_SHIFT_h}}, + {1, RSC(ADV_HELP_ITEM_SECRET).CODE(), {SCANKEY_SHIFT_y}}, + {1, RSC(ADV_HELP_ITEM_UPD).CODE(), {SCANKEY_AST} }, + {1, RSC(ADV_HELP_ITEM_START).CODE(), {SCANKEY_OPEN_BRACE}}, + {1, RSC(ADV_HELP_ITEM_STOP).CODE(), {SCANKEY_CLOSE_BRACE}}, + {1, RSC(ADV_HELP_ITEM_TOOLS).CODE(), {SCANKEY_F10} }, + {0, RSC(CREATE_ADV_HELP_COND0).CODE(), {SCANKEY_NULL} }, + {0, RSC(ADV_HELP_ITEM_TERMINAL).CODE(), {SCANKEY_NULL} }, + {1, RSC(ADV_HELP_ITEM_PRT_SCR).CODE(), {SCANKEY_CTRL_p}}, + {1, RSC(ADV_HELP_ITEM_REC_SCR).CODE(), {SCANKEY_ALT_p} }, + {0, RSC(CREATE_ADV_HELP_COND0).CODE(), {SCANKEY_NULL} }, + {1, RSC(ADV_HELP_ITEM_GO_UP).CODE(), {SCANKEY_NULL} }, + {1, RSC(ADV_HELP_ITEM_GO_DW).CODE(), {SCANKEY_NULL} }, + {0, RSC(CREATE_ADV_HELP_COND0).CODE(), {SCANKEY_NULL} } + }; + const size_t nmemb = sizeof(advHelp) / sizeof(struct ADV_HELP_ST); + Window *wHelp = CreateWindow(wLayer, id, 1,nmemb,41,TOP_HEADER_ROW+1); + if (wHelp != NULL) + { + unsigned int idx; + for (idx = 0; idx < nmemb; idx++) { + StoreTCell( wHelp, + advHelp[idx].quick.key, + advHelp[idx].item, + attrib[advHelp[idx].theme] ); + } + StoreWindow(wHelp, .title, (char*) RSC(ADV_HELP_TITLE).CODE()); + + StoreWindow(wHelp, .key.WinLeft, MotionOriginLeft_Win); + StoreWindow(wHelp, .key.WinRight, MotionOriginRight_Win); + StoreWindow(wHelp, .key.WinDown, MotionOriginDown_Win); + StoreWindow(wHelp, .key.WinUp, MotionOriginUp_Win); + StoreWindow(wHelp, .key.Enter, MotionEnter_Cell); + StoreWindow(wHelp, .key.Down, MotionDown_Win); + StoreWindow(wHelp, .key.Up, MotionUp_Win); + StoreWindow(wHelp, .key.PgUp, MotionPgUp_Win); + StoreWindow(wHelp, .key.PgDw, MotionPgDw_Win); + StoreWindow(wHelp, .key.Home, MotionReset_Win); + StoreWindow(wHelp, .key.End, MotionEnd_Cell); + StoreWindow(wHelp, .key.Shrink, MotionShrink_Win); + StoreWindow(wHelp, .key.Expand, MotionExpand_Win); + } + return wHelp; +} + +Window *CreateAbout(unsigned long long id) +{ + ASCII *C[] = { + RSC(CF0).CODE(), + RSC(CF1).CODE(), + RSC(CF2).CODE(), + RSC(CF3).CODE(), + RSC(CF4).CODE(), + RSC(CF5).CODE() + } , *F[] = { + RSC(COPY0).CODE(), + RSC(COPY1).CODE(), + RSC(COPY2).CODE() + }; + size_t c = sizeof(C) / sizeof(C[0]), + f = sizeof(F) / sizeof(F[0]), + v = strlen(COREFREQ_VERSION); + CUINT cHeight = c + f, + oCol = (Draw.Size.width - RSZ(CF0)) / 2, + oRow = TOP_HEADER_ROW + 4; + + if (cHeight >= (Draw.Size.height - 1)) { + cHeight = Draw.Size.height - 2; + } + if (oRow + cHeight >= Draw.Size.height) { + oRow = abs(Draw.Size.height - (1 + cHeight)); + } + Window *wAbout = CreateWindow( wLayer, id, 1, cHeight, + oCol, oRow, + WINFLAG_NO_SCALE ); + if (wAbout != NULL) + { + unsigned int i; + + for (i = 0; i < c; i++) + StoreTCell(wAbout,SCANKEY_NULL, C[i], MAKE_PRINT_FOCUS); + for (i = 0; i < f; i++) + StoreTCell(wAbout,SCANKEY_NULL, F[i], MAKE_PRINT_FOCUS); + + size_t p = TCellAt(wAbout, 1, 5).length - 3 - v; + memcpy(&TCellAt(wAbout, 1, 5).item[p], COREFREQ_VERSION, v); + + wAbout->matrix.select.row = wAbout->matrix.size.hth - 1; + + StoreWindow(wAbout, .title, (char *)RSC(COREFREQ_TITLE).CODE()); + + StoreWindow(wAbout, .color[0].select, MAKE_PRINT_UNFOCUS); + StoreWindow(wAbout, .color[1].select, MAKE_PRINT_FOCUS); + + StoreWindow(wAbout, .key.WinLeft, MotionOriginLeft_Win); + StoreWindow(wAbout, .key.WinRight, MotionOriginRight_Win); + StoreWindow(wAbout, .key.WinDown, MotionOriginDown_Win); + StoreWindow(wAbout, .key.WinUp, MotionOriginUp_Win); + } + return wAbout; +} + +TGrid *AddSysInfoCell(CELL_ARGS) +{ + (*cellPadding)++; + return StoreTCell(win, key, item, attrib); +} + +Window *CreateSysInfo(unsigned long long id) +{ + REASON_CODE (*SysInfoFunc)(Window*,CUINT,CELL_FUNC,unsigned int*)=NULL; + ASCII *title = NULL; + CoordSize matrixSize = { + .wth = 1, + .hth = 18 + }; + Coordinate winOrigin = {.col = 3, .row = TOP_HEADER_ROW + 2}; + CUINT winWidth = 74; + unsigned int cellPadding = 0, hwp_cppc = \ + (RO(Shm)->Proc.Features.Power.HWP_Reg == 1) + || (RO(Shm)->Proc.Features.ACPI_CPPC == 1) + || (RO(Shm)->Proc.Features.HWP_Enable == 1); + + switch (id) { + case SCANKEY_p: + { + winOrigin.row = TOP_HEADER_ROW + 2; + winOrigin.col = 2; + matrixSize.hth = 21; + winWidth = 76; + SysInfoFunc = SysInfoProc; + title = RSC(PROCESSOR_TITLE).CODE(); + } + break; + case SCANKEY_e: + { + winOrigin.row = TOP_HEADER_ROW + 1; + winOrigin.col = 4; + matrixSize.hth = 16; + winWidth = 72; + SysInfoFunc = SysInfoFeatures; + title = RSC(FEATURES_TITLE).CODE(); + } + break; + case SCANKEY_t: + { + winOrigin.col = 23; + matrixSize.hth = 10; + winOrigin.row = TOP_HEADER_ROW + 5; + winWidth = 60; + SysInfoFunc = SysInfoTech; + title = RSC(TECHNOLOGIES_TITLE).CODE(); + } + break; + case SCANKEY_o: + { + matrixSize.hth = 16; + winOrigin.row = TOP_HEADER_ROW + 1; + SysInfoFunc = SysInfoPerfMon; + title = RSC(PERF_MON_TITLE).CODE(); + } + break; + case SCANKEY_w: + { + winOrigin.col = 25; + matrixSize.hth = 28; + winOrigin.row = TOP_HEADER_ROW + 2; + winWidth = 60; + SysInfoFunc = SysInfoPwrThermal; + title = RSC(POWER_THERMAL_TITLE).CODE(); + } + break; + case SCANKEY_k: + { + CUINT height = 16 + + ( RO(Shm)->SysGate.OS.IdleDriver.stateCount > 0 ) * 5; + winOrigin.col = 1; + winWidth = 78; + matrixSize.hth = height; + winOrigin.row = TOP_HEADER_ROW + 1; + SysInfoFunc = SysInfoKernel; + title = RSC(KERNEL_TITLE).CODE(); + } + break; + case SCANKEY_SHIFT_b: + { + winOrigin.col = 4; + winWidth = MAX_UTS_LEN + 4 + 1; + SysInfoFunc = SysInfoSMBIOS; + title = RSC(SMBIOS_TITLE).CODE(); + } + break; + case SCANKEY_z: + { + winOrigin.col = 5; + matrixSize.hth = hwp_cppc == 0 ? + 1 : CUMIN(Draw.Size.height - 5, 2 + RO(Shm)->Proc.CPU.Count); + #if defined(NO_UPPER) || defined(NO_LOWER) + winOrigin.row = hwp_cppc == 0 ? 2 + TOP_HEADER_ROW : 2; + #else + winOrigin.row = Draw.Area.MaxRows + TOP_HEADER_ROW; + #endif + SysInfoFunc = SysInfoPerfCaps; + title = RSC(PERF_CAPS_TITLE).CODE(); + } + break; + } + + Window *wSysInfo = CreateWindow(wLayer, id, + matrixSize.wth, matrixSize.hth, + winOrigin.col, winOrigin.row); + if (wSysInfo != NULL) + { + if (SysInfoFunc != NULL) { + SysInfoFunc( wSysInfo, + winWidth, + AddSysInfoCell, + &cellPadding ); + } + /* Pad with blank rows. */ + while (cellPadding < matrixSize.hth) { + cellPadding++; + StoreTCell(wSysInfo, + SCANKEY_NULL, + &hSpace[MAX_WIDTH - winWidth], + MAKE_PRINT_FOCUS); + } + + switch (id) { + case SCANKEY_p: + case SCANKEY_t: + case SCANKEY_o: + case SCANKEY_w: + case SCANKEY_k: + case SCANKEY_z: + StoreWindow(wSysInfo, .key.Enter, Enter_StickyCell); + break; + case SCANKEY_SHIFT_b: + if (Draw.SmbIndex >= matrixSize.hth) { + wSysInfo->matrix.scroll.vert = 1 + + (Draw.SmbIndex - matrixSize.hth); + + wSysInfo->matrix.select.row = matrixSize.hth - 1; + } else { + wSysInfo->matrix.scroll.vert = 0; + wSysInfo->matrix.select.row = Draw.SmbIndex; + } + fallthrough; + default: + StoreWindow(wSysInfo, .key.Enter, MotionEnter_Cell); + break; + } + if (title != NULL) { + StoreWindow(wSysInfo, .title, (char*) title); + } + StoreWindow(wSysInfo, .key.Left, MotionLeft_Win); + StoreWindow(wSysInfo, .key.Right, MotionRight_Win); + StoreWindow(wSysInfo, .key.Down, MotionDown_Win); + StoreWindow(wSysInfo, .key.Up, MotionUp_Win); + StoreWindow(wSysInfo, .key.PgUp, MotionPgUp_Win); + StoreWindow(wSysInfo, .key.PgDw, MotionPgDw_Win); + StoreWindow(wSysInfo, .key.Home, MotionReset_Win); + StoreWindow(wSysInfo, .key.End, MotionEnd_Cell); + + StoreWindow(wSysInfo, .key.WinLeft, MotionOriginLeft_Win); + StoreWindow(wSysInfo, .key.WinRight, MotionOriginRight_Win); + StoreWindow(wSysInfo, .key.WinDown, MotionOriginDown_Win); + StoreWindow(wSysInfo, .key.WinUp, MotionOriginUp_Win); + + StoreWindow(wSysInfo, .key.Shrink, MotionShrink_Win); + StoreWindow(wSysInfo, .key.Expand, MotionExpand_Win); + } + return wSysInfo; +} + +TGrid *AddCell(CELL_ARGS) +{ + UNUSED(cellPadding); + + return StoreTCell(win, key, item, attrib); +} + +Window *CreateTopology(unsigned long long id) +{ + Window *wTopology = CreateWindow(wLayer, id, + TOPO_MATY, 2+RO(Shm)->Proc.CPU.Count, + 1, TOP_HEADER_ROW + 1); + + if (wTopology != NULL) + { + unsigned int cellPadding = 0; + + wTopology->matrix.select.row = 2; + + Topology(wTopology, AddCell, &cellPadding); + + StoreWindow(wTopology,.title,(char*)RSC(TOPOLOGY_TITLE).CODE()); + + StoreWindow(wTopology, .key.Left, MotionLeft_Win); + StoreWindow(wTopology, .key.Right, MotionRight_Win); + StoreWindow(wTopology, .key.Down, MotionDown_Win); + StoreWindow(wTopology, .key.Up, MotionUp_Win); + StoreWindow(wTopology, .key.PgUp, MotionPgUp_Win); + StoreWindow(wTopology, .key.PgDw, MotionPgDw_Win); + StoreWindow(wTopology, .key.Home, MotionReset_Win); + StoreWindow(wTopology, .key.End, MotionEnd_Cell); + + StoreWindow(wTopology, .key.WinLeft, MotionOriginLeft_Win); + StoreWindow(wTopology, .key.WinRight, MotionOriginRight_Win); + StoreWindow(wTopology, .key.WinDown, MotionOriginDown_Win); + StoreWindow(wTopology, .key.WinUp, MotionOriginUp_Win); + + StoreWindow(wTopology, .key.Shrink, MotionShrink_Win); + StoreWindow(wTopology, .key.Expand, MotionExpand_Win); + } + return wTopology; +} + +Window *CreateISA(unsigned long long id) +{ + Window *wISA = CreateWindow(wLayer, id, 4, 15, 6, TOP_HEADER_ROW + 2); + + if (wISA != NULL) + { + unsigned int cellPadding = 0; + + SysInfoISA(wISA, AddCell, &cellPadding); + + StoreWindow(wISA, .title, (char*) RSC(ISA_TITLE).CODE()); + + StoreWindow(wISA, .key.Left, MotionLeft_Win); + StoreWindow(wISA, .key.Right, MotionRight_Win); + StoreWindow(wISA, .key.Down, MotionDown_Win); + StoreWindow(wISA, .key.Up, MotionUp_Win); + StoreWindow(wISA, .key.PgUp, MotionPgUp_Win); + StoreWindow(wISA, .key.PgDw, MotionPgDw_Win); + StoreWindow(wISA, .key.Home, MotionHome_Win); + StoreWindow(wISA, .key.End, MotionEnd_Win); + + StoreWindow(wISA, .key.WinLeft, MotionOriginLeft_Win); + StoreWindow(wISA, .key.WinRight, MotionOriginRight_Win); + StoreWindow(wISA, .key.WinDown, MotionOriginDown_Win); + StoreWindow(wISA, .key.WinUp, MotionOriginUp_Win); + + StoreWindow(wISA, .key.Shrink, MotionShrink_Win); + StoreWindow(wISA, .key.Expand, MotionExpand_Win); + } + return wISA; +} + +Window *CreateSysRegs(unsigned long long id) +{ + Window *wSR = CreateWindow( wLayer, id, + 17, (2*(1+RO(Shm)->Proc.CPU.Count)), + 6, TOP_HEADER_ROW + 2 ); + if (wSR != NULL) + { + unsigned int cellPadding = 0; + + SystemRegisters(wSR, AddCell, &cellPadding); + + StoreWindow(wSR, .title, (char*) RSC(SYS_REGS_TITLE).CODE()); + + StoreWindow(wSR, .key.Left, MotionLeft_Win); + StoreWindow(wSR, .key.Right, MotionRight_Win); + StoreWindow(wSR, .key.Down, MotionDown_Win); + StoreWindow(wSR, .key.Up, MotionUp_Win); + StoreWindow(wSR, .key.PgUp, MotionPgUp_Win); + StoreWindow(wSR, .key.PgDw, MotionPgDw_Win); + StoreWindow(wSR, .key.Home, MotionHome_Win); + StoreWindow(wSR, .key.End, MotionEnd_Win); + + StoreWindow(wSR, .key.WinLeft, MotionOriginLeft_Win); + StoreWindow(wSR, .key.WinRight, MotionOriginRight_Win); + StoreWindow(wSR, .key.WinDown, MotionOriginDown_Win); + StoreWindow(wSR, .key.WinUp, MotionOriginUp_Win); + + StoreWindow(wSR, .key.Shrink, MotionShrink_Win); + StoreWindow(wSR, .key.Expand, MotionExpand_Win); + } + return wSR; +} + +Window *CreateMemCtrl(unsigned long long id) +{ + Window *wIMC; + TIMING_FUNC pTimingFunc = Timing_DDR3; + unsigned int mc, rows = 1 + (RO(Shm)->Uncore.CtrlCount > 1), + ctrlHeaders = 6, channelHeaders = 4; + + switch (RO(Shm)->Uncore.Unit.DDR_Ver) { + case 5: + case 4: + case 3: + case 2: + default: + ctrlHeaders = 6; + channelHeaders = 4; + pTimingFunc = Timing_DDR3; + break; + } + for (mc = 0; mc < RO(Shm)->Uncore.CtrlCount; mc++) { + rows += ctrlHeaders * (RO(Shm)->Uncore.MC[mc].ChannelCount > 0); + rows += channelHeaders * RO(Shm)->Uncore.MC[mc].ChannelCount; + rows += RO(Shm)->Uncore.MC[mc].SlotCount + * RO(Shm)->Uncore.MC[mc].ChannelCount; + } + wIMC = CreateWindow(wLayer, id, MC_MATX, rows, 4, TOP_HEADER_ROW + 2); + if (wIMC != NULL) + { + unsigned int cellPadding = 0; + + MemoryController(wIMC, AddCell, &cellPadding, pTimingFunc); + + wIMC->matrix.select.col = 2; + wIMC->matrix.select.row = 1; + + StoreWindow(wIMC, .title, (char*) RSC(MEM_CTRL_TITLE).CODE()); + + StoreWindow(wIMC, .key.Left, MotionLeft_Win); + StoreWindow(wIMC, .key.Right, MotionRight_Win); + StoreWindow(wIMC, .key.Down, MotionDown_Win); + StoreWindow(wIMC, .key.Up, MotionUp_Win); + StoreWindow(wIMC, .key.PgUp, MotionPgUp_Win); + StoreWindow(wIMC, .key.PgDw, MotionPgDw_Win); + StoreWindow(wIMC, .key.Home, MotionHome_Win); + StoreWindow(wIMC, .key.End, MotionEnd_Win); + + StoreWindow(wIMC, .key.WinLeft, MotionOriginLeft_Win); + StoreWindow(wIMC, .key.WinRight, MotionOriginRight_Win); + StoreWindow(wIMC, .key.WinDown, MotionOriginDown_Win); + StoreWindow(wIMC, .key.WinUp, MotionOriginUp_Win); + + StoreWindow(wIMC, .key.Shrink, MotionShrink_Win); + StoreWindow(wIMC, .key.Expand, MotionExpand_Win); + } + return wIMC; +} + +Window *CreateSortByField(unsigned long long id) +{ + const CUINT oRow = TOP_HEADER_ROW + #ifndef NO_UPPER + + Draw.Area.MaxRows + + 2; + #else + + 1; + #endif + Window *wSortBy = CreateWindow( wLayer, id, + 1, SORTBYCOUNT, + 33, oRow, + WINFLAG_NO_STOCK + | WINFLAG_NO_SCALE + | WINFLAG_NO_BORDER ); + if (wSortBy != NULL) + { + StoreTCell(wSortBy,SORTBY_STATE,RSC(TASKS_SORTBY_STATE).CODE(), + MAKE_PRINT_DROP); + StoreTCell(wSortBy,SORTBY_RTIME,RSC(TASKS_SORTBY_RTIME).CODE(), + MAKE_PRINT_DROP); + StoreTCell(wSortBy,SORTBY_UTIME,RSC(TASKS_SORTBY_UTIME).CODE(), + MAKE_PRINT_DROP); + StoreTCell(wSortBy,SORTBY_STIME,RSC(TASKS_SORTBY_STIME).CODE(), + MAKE_PRINT_DROP); + StoreTCell(wSortBy,SORTBY_PID, RSC(TASKS_SORTBY_PID).CODE(), + MAKE_PRINT_DROP); + StoreTCell(wSortBy,SORTBY_COMM, RSC(TASKS_SORTBY_COMM).CODE(), + MAKE_PRINT_DROP); + + wSortBy->matrix.select.row = RO(Shm)->SysGate.sortByField; + + StoreWindow(wSortBy, .color[0].select, MAKE_PRINT_DROP); + StoreWindow(wSortBy, .color[1].select, + RSC(UI).ATTR()[UI_WIN_MENU_SELECT]); + + StoreWindow(wSortBy, .color[0].title, MAKE_PRINT_DROP); + StoreWindow(wSortBy, .color[1].title, + RSC(UI).ATTR()[UI_WIN_SORT_BY_FIELD_TITLE]); + + StoreWindow(wSortBy, .Print, ForEachCellPrint_Drop); + + StoreWindow(wSortBy, .key.Enter, MotionEnter_Cell); + StoreWindow(wSortBy, .key.Down, MotionDown_Win); + StoreWindow(wSortBy, .key.Up, MotionUp_Win); + StoreWindow(wSortBy, .key.Home, MotionReset_Win); + StoreWindow(wSortBy, .key.End, MotionEnd_Cell); + } + return wSortBy; +} + +int SortTaskListByForest(const void *p1, const void *p2) +{ + TASK_MCB *task1 = (TASK_MCB*) p1, *task2 = (TASK_MCB*) p2; + + if (task1->ppid < task2->ppid) { + return -1; + } else if (task1->ppid > task2->ppid) { + return 1; + } else if (task1->tgid < task2->tgid) { + return -1; + } else if (task1->tgid > task2->tgid) { + return 1; + } else if (task1->pid < task2->pid) { + return -1; + } else if (task1->pid > task2->pid) { + return 1; + } else { + return 1; + } +} + +void UpdateTracker(TGrid *grid, DATA_TYPE data[]) +{ + signed int *tracked = &data[0].sint[1]; + if ((*tracked) == 1) + { + const pid_t pid = data[0].sint[0]; + signed int idx; + for (idx = 0; idx < RO(Shm)->SysGate.taskCount; idx++) + { + if (((*tracked) = (RO(Shm)->SysGate.taskList[idx].pid == pid)) == 1) + { + double runtime, usertime, systime; + /* + * Source: kernel/sched/cputime.c + * If either stime or utime are 0, assume all runtime is userspace. + */ + runtime = RO(Shm)->SysGate.taskList[idx].runtime; + systime = RO(Shm)->SysGate.taskList[idx].systime; + usertime= RO(Shm)->SysGate.taskList[idx].usertime; + + if (systime == 0.0) + { + usertime = runtime; + } + if (usertime == 0.0) + { + systime = runtime; + } + systime = (systime * runtime) / (systime + usertime); + usertime= runtime - systime; + + const double fulltime = usertime + systime; + if (fulltime > 0.0) + { + usertime= (100.0 * usertime)/ fulltime; + systime = (100.0 * systime) / fulltime; + } else { + usertime= 0.0; + systime = 0.0; + } + size_t len; + StrLenFormat(len, Buffer, 20+20+5+4+6+1, + "User:%3.0f%% Sys:%3.0f%% ", + usertime, systime); + + memcpy( &grid->cell.item[grid->cell.length - len], Buffer, len); + break; + } + } + if (!(idx < RO(Shm)->SysGate.taskCount)) { + memcpy(grid->cell.item, hSpace, grid->cell.length); + } + } +} + +Window *CreateTracking(unsigned long long id) +{ + Window *wTrack = NULL; + const size_t tc = (size_t) RO(Shm)->SysGate.taskCount; + + if (BITWISEAND(LOCKLESS, RO(Shm)->SysGate.Operation, 0x1) && (tc > 0)) + { + TASK_MCB *trackList; + trackList = malloc(tc * sizeof(TASK_MCB)); + if (trackList != NULL) + { + memcpy(trackList, RO(Shm)->SysGate.taskList, tc * sizeof(TASK_MCB)); + qsort(trackList, tc, sizeof(TASK_MCB), SortTaskListByForest); + + const CUINT margin = 12; /* "--- Freq(MHz" */ + const CUINT height = TOP_SEPARATOR + + (Draw.Area.MaxRows << (ADD_UPPER & ADD_LOWER)); + const CUINT width = (Draw.Size.width - margin) / 2; + const int padding = width - TASK_COMM_LEN - (7 + 2); + + wTrack = CreateWindow( wLayer, id, + 2, height, + margin, TOP_HEADER_ROW, + WINFLAG_NO_STOCK + | WINFLAG_NO_BORDER ); + if (wTrack != NULL) + { + size_t ti; + ssize_t si = 0; + signed int qi = 0; + pid_t previd = (pid_t) -1; + + for (ti = 0; ti < tc; ti++) + { + if (trackList[ti].ppid == previd) { + si += (si < padding - 2) ? 1 : 0; + } else if (trackList[ti].tgid != previd) { + si -= (si > 0) ? 1 : 0; + } + previd = trackList[ti].tgid; + + if (trackList[ti].pid == trackList[ti].tgid) { + qi = si + 1; + } else { + qi = si + 2; + } + StrFormat(Buffer, MAX_WIDTH-1, + "%.*s" "%-16s" "%.*s" "(%7d)", + qi, + hSpace, + trackList[ti].comm, + padding - qi, + hSpace, + trackList[ti].pid); + + StoreTCell(wTrack, + (TRACK_TASK | (unsigned long long) trackList[ti].pid), + Buffer, + (trackList[ti].pid == trackList[ti].tgid) ? + (trackList[ti].pid == RO(Shm)->SysGate.trackTask) ? + RSC(UI).ATTR()[UI_WIN_TRACKING_THIS_PARENT] + : RSC(UI).ATTR()[UI_WIN_TRACKING_PARENT_PROCESS] + : (trackList[ti].pid == RO(Shm)->SysGate.trackTask) ? + RSC(UI).ATTR()[UI_WIN_TRACKING_THIS_CHILD] + : RSC(UI).ATTR()[UI_WIN_TRACKING_CHILD_PROCESS]); + + StrFormat(Buffer, MAX_WIDTH-1, "%.*s", width, hSpace); + + DATA_TYPE data = { + .sint = { [0] = (pid_t) trackList[ti].pid, [1] = 1 } + }; + GridCall(StoreTCell(wTrack, SCANKEY_NULL, Buffer, + RSC(UI).ATTR()[UI_WIN_TRACKING_COUNTERS]), + UpdateTracker, data); + } + StoreWindow( wTrack, .color[0].select, + RSC(UI).ATTR()[UI_WIN_TRACKING_COUNTERS] ); + + StoreWindow( wTrack, .color[1].select, + RSC(UI).ATTR()[UI_MAKE_SELECT_FOCUS] ); + + StoreWindow( wTrack, .color[0].title, + MAKE_PRINT_DROP ); + + StoreWindow( wTrack, .color[1].title, + RSC(UI).ATTR()[UI_WIN_TRACKING_TITLE] ); + + StoreWindow(wTrack, .Print, ForEachCellPrint_Drop); + StoreWindow(wTrack, .key.Enter, MotionEnter_Cell); + + StoreWindow(wTrack, .key.Left, MotionLeft_Win); + StoreWindow(wTrack, .key.Right, MotionRight_Win); + StoreWindow(wTrack, .key.Down, MotionDown_Win); + StoreWindow(wTrack, .key.Up, MotionUp_Win); + + StoreWindow(wTrack, .key.PgUp, MotionPgUp_Win); + StoreWindow(wTrack, .key.PgDw, MotionPgDw_Win); + StoreWindow(wTrack, .key.Home, MotionReset_Win); + StoreWindow(wTrack, .key.End, MotionEnd_Cell); + + StoreWindow(wTrack, .key.Shrink, MotionShrink_Win); + StoreWindow(wTrack, .key.Expand, MotionExpand_Win); + } + free(trackList); + } + } + return wTrack; +} + +void UpdateHotPlugCPU(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int cpu = data[0].ullong & CPU_MASK; + + if (BITVAL(RO(Shm)->Cpu[cpu].OffLine, OS)) + { + if ((data[0].ullong & CPU_STATE_MASK) == CPU_ONLINE) + { + StrFormat(Buffer, 9+10+1, + RSC(CREATE_HOTPLUG_CPU_OFFLINE).CODE(), cpu); + + memcpy(grid->cell.item, Buffer, grid->cell.length); + memcpy(grid->cell.attr, RSC(CREATE_HOTPLUG_CPU_OFFLINE).ATTR(), + grid->cell.length); + + grid->data[0].ullong = (unsigned long long) (CPU_OFFLINE | cpu); + } + } + else + { + if ((data[0].ullong & CPU_STATE_MASK) == CPU_OFFLINE) + { + StrFormat(Buffer, 9+10+1, + RSC(CREATE_HOTPLUG_CPU_ONLINE).CODE(), cpu); + + memcpy(grid->cell.item, Buffer, grid->cell.length); + memcpy(grid->cell.attr, RSC(CREATE_HOTPLUG_CPU_ONLINE).ATTR(), + grid->cell.length); + + grid->data[0].ullong = (unsigned long long) (CPU_ONLINE | cpu); + } + } +} + +void UpdateHotPlugTrigger(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int cpu = data[0].ullong & CPU_MASK; + + if (BITVAL(RO(Shm)->Cpu[cpu].OffLine, OS)) + { + if ((data[0].ullong & CPU_STATE_MASK) == CPU_ONLINE) + { + memcpy( grid->cell.item, + RSC(CREATE_HOTPLUG_CPU_ENABLE).CODE(), + (size_t)RSZ(CREATE_HOTPLUG_CPU_ENABLE) ); + + memcpy( grid->cell.attr, + RSC(CREATE_HOTPLUG_CPU_ENABLE).ATTR(), + grid->cell.length ); + + grid->cell.quick.key = (unsigned long long) (CPU_ONLINE | cpu); + grid->data[0].ullong = (unsigned long long) (CPU_OFFLINE | cpu); + } + } + else + { + if ((data[0].ullong & CPU_STATE_MASK) == CPU_OFFLINE) + { + memcpy( grid->cell.item, + RSC(CREATE_HOTPLUG_CPU_DISABLE).CODE(), + (size_t)RSZ(CREATE_HOTPLUG_CPU_DISABLE) ); + + memcpy( grid->cell.attr, + RSC(CREATE_HOTPLUG_CPU_DISABLE).ATTR(), + grid->cell.length ); + + grid->cell.quick.key = (unsigned long long) (CPU_OFFLINE | cpu); + grid->data[0].ullong = (unsigned long long) (CPU_ONLINE | cpu); + } + } +} + +Window *CreateHotPlugCPU(unsigned long long id) +{ + Window *wCPU = CreateWindow( wLayer, id, 2, Draw.Area.MaxRows, + LOAD_LEAD + 1, TOP_HEADER_ROW + 1, + WINFLAG_NO_STOCK ); + if (wCPU != NULL) + { + unsigned int cpu; + for (cpu = 0; cpu < RO(Shm)->Proc.CPU.Count; cpu++) + { + if (BITVAL(RO(Shm)->Cpu[cpu].OffLine, OS)) + { + StrFormat(Buffer, 9+10+1, RSC(CREATE_HOTPLUG_CPU_OFFLINE).CODE(), cpu); + + GridCall( StoreTCell( wCPU, SCANKEY_NULL, Buffer, + RSC(CREATE_HOTPLUG_CPU_OFFLINE).ATTR() ), + UpdateHotPlugCPU, (unsigned long long) (CPU_OFFLINE | cpu) ); + + GridCall( StoreTCell( wCPU, (unsigned long long) (CPU_ONLINE | cpu), + RSC(CREATE_HOTPLUG_CPU_ENABLE).CODE(), + RSC(CREATE_HOTPLUG_CPU_ENABLE).ATTR() ), + UpdateHotPlugTrigger, (unsigned long long)(CPU_OFFLINE | cpu) ); + } + else + { + StrFormat(Buffer, 9+10+1, RSC(CREATE_HOTPLUG_CPU_ONLINE).CODE(), cpu); + + GridCall( StoreTCell( wCPU, SCANKEY_NULL, Buffer, + RSC(CREATE_HOTPLUG_CPU_ONLINE).ATTR() ), + UpdateHotPlugCPU, (unsigned long long) (CPU_ONLINE | cpu) ); + + GridCall( StoreTCell( wCPU, (unsigned long long) (CPU_OFFLINE | cpu), + RSC(CREATE_HOTPLUG_CPU_DISABLE).CODE(), + RSC(CREATE_HOTPLUG_CPU_DISABLE).ATTR() ), + UpdateHotPlugTrigger, (unsigned long long)(CPU_ONLINE | cpu) ); + } + } + wCPU->matrix.select.col = 1; + + StoreWindow(wCPU, .title, (char *)RSC(CREATE_HOTPLUG_CPU_TITLE).CODE()); + + StoreWindow(wCPU, .color[1].title, + RSC(UI).ATTR()[UI_WIN_HOT_PLUG_CPU_TITLE]); + + StoreWindow(wCPU, .key.Enter, Enter_StickyCell); + StoreWindow(wCPU, .key.Down, MotionDown_Win); + StoreWindow(wCPU, .key.Up, MotionUp_Win); + StoreWindow(wCPU, .key.PgUp, MotionPgUp_Win); + StoreWindow(wCPU, .key.PgDw, MotionPgDw_Win); + StoreWindow(wCPU, .key.Home, MotionTop_Win); + StoreWindow(wCPU, .key.End, MotionBottom_Win); + + StoreWindow(wCPU, .key.WinLeft, MotionOriginLeft_Win); + StoreWindow(wCPU, .key.WinRight, MotionOriginRight_Win); + StoreWindow(wCPU, .key.WinDown, MotionOriginDown_Win); + StoreWindow(wCPU, .key.WinUp, MotionOriginUp_Win); + + StoreWindow(wCPU, .key.Shrink, MotionShrink_Win); + StoreWindow(wCPU, .key.Expand, MotionExpand_Win); + } + return wCPU; +} + +void UpdateRatioClock(TGrid *grid, DATA_TYPE data[]) +{ + struct FLIP_FLOP *CFlop = \ + &RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].FlipFlop[ + !RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Toggle + ]; + if (data[0].uint[0] > MAXCLOCK_TO_RATIO(unsigned int, CFlop->Clock.Hz)) + { + StrFormat(Buffer, 1+6+1, " %-6s", RSC(NOT_AVAILABLE).CODE()); + } else { + StrFormat(Buffer, 8+1, "%7.2f", + ABS_FREQ_MHz(double, data[0].uint[0], CFlop->Clock)); + } + memcpy(&grid->cell.item[1], Buffer, 7); +} + +void TitleForTurboClock(unsigned int NC, ASCII *title) +{ + StrFormat(title, 15+11+1, RSC(TURBO_CLOCK_TITLE).CODE(), NC); +} + +void TitleForRatioClock(unsigned int NC, ASCII *title) +{ + StrFormat(title, 14+6+1, RSC(RATIO_CLOCK_TITLE).CODE(), + (NC == CLOCK_MOD_TGT) || (NC == CLOCK_MOD_HWP_TGT) ? + RSC(TARGET).CODE() : + (NC == CLOCK_MOD_MAX) || (NC == CLOCK_MOD_HWP_MAX) ? + RSC(MAX).CODE() : + (NC == CLOCK_MOD_MIN) || (NC == CLOCK_MOD_HWP_MIN) ? + RSC(MIN).CODE() : + (NC == CLOCK_MOD_ACT) ? + RSC(ACT).CODE() : (ASCII*) ""); +} + +void TitleForUncoreClock(unsigned int NC, ASCII *title) +{ + StrFormat(title, 15+3+1, RSC(UNCORE_CLOCK_TITLE).CODE(), + (NC == CLOCK_MOD_MAX) ? RSC(MAX).CODE() : + (NC == CLOCK_MOD_MIN) ? RSC(MIN).CODE() : (ASCII*) ""); +} + +void ComputeRatioShifts(unsigned int COF, + unsigned int lowestOperating, + unsigned int highestOperating, + signed int *lowestShift, + signed int *highestShift) +{ + unsigned int minRatio, maxRatio; + if (highestOperating < lowestOperating) { + minRatio = highestOperating; + maxRatio = lowestOperating; + } else { + minRatio = lowestOperating; + maxRatio = highestOperating; + } + if (COF < minRatio) { + minRatio = COF; + } + if (COF > maxRatio) { + maxRatio = COF; + } + (*lowestShift) = (int) COF - (int) minRatio; + (*highestShift) = (int) maxRatio - (int) COF; +} + +unsigned int MultiplierIsRatio(unsigned int cpu, unsigned int multiplier) +{ + enum RATIO_BOOST boost; + for (boost = BOOST(MIN); boost < BOOST(SIZE); boost++) + { + switch (boost) { + case BOOST(TBO): + case BOOST(TBH): + fallthrough; + default: + if (RO(Shm)->Cpu[cpu].Boost[boost] == multiplier) + { + return 1; + } + break; + } + } + if (RO(Shm)->Proc.Features.Factory.Ratio == multiplier) { + return 1; + } + return 0; +} + +Window *CreateRatioClock(unsigned long long id, + unsigned int COF, + signed short any, + unsigned int NC, + signed int lowestShift, + signed int highestShift, + signed int medianColdZone, + signed int startingHotZone, + unsigned long long boxKey, + CPU_ITEM_CALLBACK TitleCallback, + CUINT oCol) +{ + unsigned int cpu = (any == -1) ? Ruler.Top[NC] : (unsigned int) any; + struct FLIP_FLOP *CFlop = &RO(Shm)->Cpu[cpu].FlipFlop[ + !RO(Shm)->Cpu[cpu].Toggle + ]; + ATTRIBUTE *attrib[7] = { + RSC(CREATE_RATIO_CLOCK_COND0).ATTR(), + RSC(CREATE_RATIO_CLOCK_COND1).ATTR(), + RSC(CREATE_RATIO_CLOCK_COND2).ATTR(), + RSC(CREATE_RATIO_CLOCK_COND3).ATTR(), + RSC(CREATE_RATIO_CLOCK_COND4).ATTR(), + RSC(CREATE_RATIO_CLOCK_COND5).ATTR(), + RSC(CREATE_RATIO_CLOCK_COND6).ATTR() + }; + CLOCK_ARG clockMod = {.ullong = id}; + + const CUINT hthMax = 1 + lowestShift + highestShift; + CUINT oRow = CUMAX(1 + TOP_HEADER_ROW + TOP_FOOTER_ROW, 2); + CUINT hthWin = CUMIN(Draw.Size.height - oRow, hthMax); + if (hthWin < oRow) { + oRow = 1; + hthWin = Draw.Size.height - 2; + } + Window *wCK = CreateWindow( wLayer, id, + 1, hthWin, + oCol, + oRow, + WINFLAG_NO_STOCK ); + if (wCK != NULL) + { + signed int multiplier, offset; + for (offset = -lowestShift; offset <= highestShift; offset++) + { + ATTRIBUTE *attr = attrib[3]; + + multiplier = (int) COF + offset; + + clockMod.NC = NC | boxKey; + clockMod.cpu = any; + + if (any == -1) { + clockMod.Ratio = multiplier; + } else { + clockMod.Offset = offset; + } + + if (multiplier == 0) { + StrFormat(Buffer, RSZ(AUTOMATIC)+17+11+11+1, + " %s <%4d > %+4d ", + RSC(AUTOMATIC).CODE(), multiplier, offset); + + StoreTCell(wCK, clockMod.ullong, Buffer, attr); + } else { + if (multiplier > MAXCLOCK_TO_RATIO(signed int, CFlop->Clock.Hz)) + { + StrFormat(Buffer, 15+6+11+11+1, + " %-6s MHz <%4d > %+4d ", + RSC(NOT_AVAILABLE).CODE(), multiplier, offset); + } else { + const unsigned int _multiplier = (unsigned int)multiplier; + attr = attrib[ + multiplier < medianColdZone ? + 1 + 4 * MultiplierIsRatio(cpu, _multiplier) + : multiplier >= startingHotZone ? + 2 + 4 * MultiplierIsRatio(cpu, _multiplier) + : 0 + 4 * MultiplierIsRatio(cpu, _multiplier) + ]; + StrFormat(Buffer, 14+8+11+11+1, + " %7.2f MHz <%4d > %+4d ", + ABS_FREQ_MHz(double, _multiplier, CFlop->Clock), + multiplier, offset); + } + GridCall(StoreTCell(wCK, clockMod.ullong, Buffer, attr), + UpdateRatioClock, multiplier); + } + } + + TitleCallback(NC, (ASCII *) Buffer); + StoreWindow(wCK, .title, Buffer); + + if (lowestShift >= hthWin) { + wCK->matrix.scroll.vert = hthMax + - hthWin * (1+(highestShift / hthWin)); + wCK->matrix.select.row = lowestShift + - wCK->matrix.scroll.vert; + } else { + wCK->matrix.select.row = COF > 0 ? lowestShift : 0; + } + StoreWindow(wCK, .key.Enter, MotionEnter_Cell); + StoreWindow(wCK, .key.Down, MotionDown_Win); + StoreWindow(wCK, .key.Up, MotionUp_Win); + StoreWindow(wCK, .key.PgUp, MotionPgUp_Win); + StoreWindow(wCK, .key.PgDw, MotionPgDw_Win); + StoreWindow(wCK, .key.Home, MotionTop_Win); + StoreWindow(wCK, .key.End, MotionBottom_Win); + + StoreWindow(wCK, .key.WinLeft, MotionOriginLeft_Win); + StoreWindow(wCK, .key.WinRight, MotionOriginRight_Win); + StoreWindow(wCK, .key.WinDown, MotionOriginDown_Win); + StoreWindow(wCK, .key.WinUp, MotionOriginUp_Win); + + StoreWindow(wCK, .key.Shrink, MotionShrink_Win); + StoreWindow(wCK, .key.Expand, MotionExpand_Win); + } + return wCK; +} + +void UpdateRoomSchedule(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int cpu = data[0].ullong & CPU_MASK; + const signed int pos = grid->cell.length - 8; + + if (BITVAL(RO(Shm)->Cpu[cpu].OffLine, OS)) + { + if ((data[0].ullong & CPU_STATE_MASK) == CPU_ONLINE) + { + memcpy( grid->cell.attr, + RSC(CREATE_SELECT_CPU_COND0).ATTR(), + grid->cell.length ); + + grid->cell.quick.key = SCANKEY_NULL; + grid->data[0].ullong = (unsigned long long) (CPU_OFFLINE | cpu); + } + } + else + { + if ((data[0].ullong & CPU_STATE_MASK) == CPU_OFFLINE) + { + memcpy( grid->cell.attr, + RSC(CREATE_SELECT_CPU_COND1).ATTR(), + grid->cell.length ); + + grid->cell.quick.key = (unsigned long long) (CPU_SELECT | cpu); + grid->data[0].ullong = (unsigned long long) (CPU_ONLINE | cpu); + } + } + + const unsigned int run = BITVAL_CC(RO(Shm)->roomSched, cpu); + unsigned int sched = BITVAL(data[0].ullong, 63); + + if (run != sched) + { + memcpy( &grid->cell.item[pos], + ENABLED(run), __builtin_strlen(ENABLED(0)) ); + + if (run) { + BITSET(LOCKLESS, grid->data[0].ullong, 63); + } else { + BITCLR(LOCKLESS, grid->data[0].ullong, 63); + } + if (!BITVAL(RO(Shm)->Cpu[cpu].OffLine, OS)) + { + sched = BITVAL(grid->data[0].ullong, 63); + if (sched) { + memcpy( &grid->cell.attr[pos], + &RSC(CREATE_SELECT_CPU_COND2).ATTR()[pos], + __builtin_strlen(ENABLED(0)) ); + } else { + memcpy( &grid->cell.attr[pos], + &RSC(CREATE_SELECT_CPU_COND1).ATTR()[pos], + __builtin_strlen(ENABLED(0)) ); + } + } + } +} + +Window *CreateSelectCPU(unsigned long long id) +{ + const CUINT _height = (ADD_UPPER & ADD_LOWER) + + (Draw.Area.MaxRows << (ADD_UPPER & ADD_LOWER)); + const CUINT height = CUMIN(RO(Shm)->Proc.CPU.Count, _height); + const CUINT column = Draw.Size.width <= 35 ? 1 : Draw.Size.width - 35; + + Window *wUSR = CreateWindow( wLayer, id, + 1, height, + column, TOP_HEADER_ROW + 1, + WINFLAG_NO_STOCK ); + if (wUSR != NULL) + { + unsigned int cpu, bix; + for (cpu = 0; cpu < RO(Shm)->Proc.CPU.Count; cpu++) + { + bix = BITVAL_CC(RO(Shm)->roomSched, cpu); + StrFormat(Buffer, 17+10+11+11+11+1, + " %03u %4d%6d%6d <%3s> ", + cpu, + RO(Shm)->Cpu[cpu].Topology.PackageID, + RO(Shm)->Cpu[cpu].Topology.CoreID, + RO(Shm)->Cpu[cpu].Topology.ThreadID, + ENABLED(bix)); + + if (BITVAL(RO(Shm)->Cpu[cpu].OffLine, OS)) + { + unsigned long long + data = BITVAL_CC(RO(Shm)->roomSched, cpu); + data = data << 63; + data = data | (CPU_OFFLINE | cpu); + + GridCall( StoreTCell( wUSR, SCANKEY_NULL, Buffer, + RSC(CREATE_SELECT_CPU_COND0).ATTR() ), + UpdateRoomSchedule, data ); + } + else + { + unsigned long long + data = BITVAL_CC(RO(Shm)->roomSched, cpu); + data = data << 63; + data = data | (CPU_ONLINE | cpu); + + GridCall( StoreTCell( wUSR, CPU_SELECT | cpu, Buffer, + bix ? RSC(CREATE_SELECT_CPU_COND2).ATTR() + : RSC(CREATE_SELECT_CPU_COND1).ATTR() ), + UpdateRoomSchedule, data ); + } + } + StoreWindow(wUSR, .title, (char*) RSC(SELECT_CPU_TITLE).CODE()); + StoreWindow(wUSR, .color[1].title, wUSR->hook.color[1].border); + + StoreWindow(wUSR, .key.Enter, Enter_StickyCell); + StoreWindow(wUSR, .key.Down, MotionDown_Win); + StoreWindow(wUSR, .key.Up, MotionUp_Win); + StoreWindow(wUSR, .key.PgUp, MotionPgUp_Win); + StoreWindow(wUSR, .key.PgDw, MotionPgDw_Win); + StoreWindow(wUSR, .key.Home, MotionTop_Win); + StoreWindow(wUSR, .key.End, MotionBottom_Win); + StoreWindow(wUSR, .key.Shrink, MotionShrink_Win); + StoreWindow(wUSR, .key.Expand, MotionExpand_Win); + + StoreWindow(wUSR, .key.WinLeft, MotionOriginLeft_Win); + StoreWindow(wUSR, .key.WinRight, MotionOriginRight_Win); + StoreWindow(wUSR, .key.WinDown, MotionOriginDown_Win); + StoreWindow(wUSR, .key.WinUp, MotionOriginUp_Win); + + StoreWindow(wUSR, .key.Shrink, MotionShrink_Win); + StoreWindow(wUSR, .key.Expand, MotionExpand_Win); + } + return wUSR; +} + +void Pkg_Fmt_Turbo(ASCII *item, CLOCK *clock, unsigned int ratio, char *NC) +{ + if (ratio == 0) { + StrFormat(item, RSZ(CREATE_SELECT_FREQ_OFFLINE)+10+1, + (char *) RSC(CREATE_SELECT_AUTO_TURBO).CODE(), + NC, RSC(AUTOMATIC).CODE(), + RO(Shm)->Proc.Features.Turbo_Unlock ? '<' : '[', + ratio, + RO(Shm)->Proc.Features.Turbo_Unlock ? '>' : ']'); + } else { + StrFormat(item, RSZ(CREATE_SELECT_FREQ_OFFLINE)+9+10+1, + (char *) RSC(CREATE_SELECT_FREQ_TURBO).CODE(), + NC, ABS_FREQ_MHz(double, ratio, (*clock)), + RO(Shm)->Proc.Features.Turbo_Unlock ? '<' : '[', + ratio, + RO(Shm)->Proc.Features.Turbo_Unlock ? '>' : ']'); + } +} + +void Pkg_Fmt_Freq( ASCII *item, ASCII *code, CLOCK *clock, + unsigned int ratio, unsigned char unlock ) +{ + if (ratio == 0) { + StrFormat(item, RSZ(CREATE_SELECT_FREQ_OFFLINE)+10+1, + "%s" " %s %c%4u %c ", + code, RSC(AUTOMATIC).CODE(), + unlock ? '<' : '[', ratio, unlock ? '>' : ']'); + } else { + StrFormat(item, RSZ(CREATE_SELECT_FREQ_OFFLINE)+9+10+1, + "%s" "%7.2f MHz %c%4u %c ", + code, ABS_FREQ_MHz(double, ratio, (*clock)), + unlock ? '<' : '[', ratio, unlock ? '>' : ']'); + } +} + +void CPU_Item_Auto_Freq(unsigned int cpu, unsigned int ratio, + unsigned char unlock, ASCII *item) +{ + StrFormat(item, RSZ(CREATE_SELECT_FREQ_OFFLINE)+10+11+11+11+10+1, + " %03u %4d%6d%6d " " %s %c%4u %c ", + cpu, + RO(Shm)->Cpu[cpu].Topology.PackageID, + RO(Shm)->Cpu[cpu].Topology.CoreID, + RO(Shm)->Cpu[cpu].Topology.ThreadID, + RSC(AUTOMATIC).CODE(), + unlock ? '<' : '[', + ratio, + unlock ? '>' : ']'); +} + +#define DECLARE_Pkg_Item_Turbo(_NC) \ +void Pkg_Item_Turbo_##_NC(ASCII *item) \ +{ \ + unsigned int top = Ruler.Top[BOOST(_NC)]; \ + \ + Pkg_Fmt_Turbo( item, \ + &RO(Shm)->Cpu[top].FlipFlop[ \ + !RO(Shm)->Cpu[top].Toggle \ + ].Clock, \ + RO(Shm)->Cpu[top].Boost[BOOST(_NC)], \ + COREFREQ_STRINGIFY(_NC) ); \ +} +DECLARE_Pkg_Item_Turbo( 1C) +DECLARE_Pkg_Item_Turbo( 2C) +DECLARE_Pkg_Item_Turbo( 3C) +DECLARE_Pkg_Item_Turbo( 4C) +DECLARE_Pkg_Item_Turbo( 5C) +DECLARE_Pkg_Item_Turbo( 6C) +DECLARE_Pkg_Item_Turbo( 7C) +DECLARE_Pkg_Item_Turbo( 8C) +DECLARE_Pkg_Item_Turbo( 9C) +DECLARE_Pkg_Item_Turbo(10C) +DECLARE_Pkg_Item_Turbo(11C) +DECLARE_Pkg_Item_Turbo(12C) +DECLARE_Pkg_Item_Turbo(13C) +DECLARE_Pkg_Item_Turbo(14C) +DECLARE_Pkg_Item_Turbo(15C) +DECLARE_Pkg_Item_Turbo(16C) +DECLARE_Pkg_Item_Turbo(17C) +DECLARE_Pkg_Item_Turbo(18C) +#undef DECLARE_Pkg_Item_Turbo + +#define DECLARE_Pkg_Update_Turbo(_NC) \ +void Pkg_Update_Turbo_##_NC(TGrid *grid, DATA_TYPE data[]) \ +{ \ + ASCII item[RSZ(CREATE_SELECT_FREQ_OFFLINE)+9+10+1]; \ + unsigned int top = Ruler.Top[BOOST(_NC)]; \ + UNUSED(data); \ + \ + Pkg_Fmt_Turbo( item, \ + &RO(Shm)->Cpu[top].FlipFlop[ \ + !RO(Shm)->Cpu[top].Toggle \ + ].Clock, \ + RO(Shm)->Cpu[top].Boost[BOOST(_NC)], \ + COREFREQ_STRINGIFY(_NC) ); \ + \ + memcpy(grid->cell.item, item, grid->cell.length); \ +} + +DECLARE_Pkg_Update_Turbo( 1C) +DECLARE_Pkg_Update_Turbo( 2C) +DECLARE_Pkg_Update_Turbo( 3C) +DECLARE_Pkg_Update_Turbo( 4C) +DECLARE_Pkg_Update_Turbo( 5C) +DECLARE_Pkg_Update_Turbo( 6C) +DECLARE_Pkg_Update_Turbo( 7C) +DECLARE_Pkg_Update_Turbo( 8C) +DECLARE_Pkg_Update_Turbo( 9C) +DECLARE_Pkg_Update_Turbo(10C) +DECLARE_Pkg_Update_Turbo(11C) +DECLARE_Pkg_Update_Turbo(12C) +DECLARE_Pkg_Update_Turbo(13C) +DECLARE_Pkg_Update_Turbo(14C) +DECLARE_Pkg_Update_Turbo(15C) +DECLARE_Pkg_Update_Turbo(16C) +DECLARE_Pkg_Update_Turbo(17C) +DECLARE_Pkg_Update_Turbo(18C) +#undef DECLARE_Pkg_Update_Turbo + +#define DECLARE_CPU_Item_Turbo(_NC) \ +void CPU_Item_Turbo_##_NC(unsigned int cpu, ASCII *item) \ +{ \ + if (RO(Shm)->Cpu[cpu].Boost[BOOST(_NC)] == 0) { \ + CPU_Item_Auto_Freq(cpu, RO(Shm)->Cpu[cpu].Boost[BOOST(_NC)], \ + RO(Shm)->Proc.Features.Turbo_Unlock, item); \ + } else { \ + struct FLIP_FLOP *CFlop = &RO(Shm)->Cpu[cpu].FlipFlop[ \ + !RO(Shm)->Cpu[cpu].Toggle \ + ]; \ + StrFormat(item , \ + RSZ(CREATE_SELECT_FREQ_OFFLINE)+10+11+11+11+8+10+1, \ + " %03u %4d%6d%6d " "%7.2f MHz %c%4u %c ", \ + cpu, \ + RO(Shm)->Cpu[cpu].Topology.PackageID, \ + RO(Shm)->Cpu[cpu].Topology.CoreID, \ + RO(Shm)->Cpu[cpu].Topology.ThreadID, \ + ABS_FREQ_MHz(double, RO(Shm)->Cpu[cpu].Boost[BOOST(_NC)],\ + CFlop->Clock), \ + RO(Shm)->Proc.Features.Turbo_Unlock ? '<' : '[', \ + RO(Shm)->Cpu[cpu].Boost[BOOST(_NC)], \ + RO(Shm)->Proc.Features.Turbo_Unlock ? '>' : ']'); \ + } \ +} +DECLARE_CPU_Item_Turbo( 1C) +DECLARE_CPU_Item_Turbo( 2C) +DECLARE_CPU_Item_Turbo( 3C) +DECLARE_CPU_Item_Turbo( 4C) +DECLARE_CPU_Item_Turbo( 5C) +DECLARE_CPU_Item_Turbo( 6C) +DECLARE_CPU_Item_Turbo( 7C) +DECLARE_CPU_Item_Turbo( 8C) +DECLARE_CPU_Item_Turbo( 9C) +DECLARE_CPU_Item_Turbo(10C) +DECLARE_CPU_Item_Turbo(11C) +DECLARE_CPU_Item_Turbo(12C) +DECLARE_CPU_Item_Turbo(13C) +DECLARE_CPU_Item_Turbo(14C) +DECLARE_CPU_Item_Turbo(15C) +DECLARE_CPU_Item_Turbo(16C) +DECLARE_CPU_Item_Turbo(17C) +DECLARE_CPU_Item_Turbo(18C) +#undef DECLARE_CPU_Item_Turbo + +#define DECLARE_CPU_Update_Turbo(_NC) \ +void CPU_Update_Turbo_##_NC(TGrid *grid, DATA_TYPE data[]) \ +{ \ + const unsigned int cpu = data[0].ullong & CPU_MASK; \ + ASCII item[ RSZ(CREATE_SELECT_FREQ_OFFLINE)+10+11+11+11+8+1 ]; \ + if (BITVAL(RO(Shm)->Cpu[cpu].OffLine, OS)) \ + { \ + if ((data[0].ullong & CPU_STATE_MASK) == CPU_ONLINE) \ + { \ + StrFormat(item, RSZ(CREATE_SELECT_FREQ_OFFLINE)+10+11+11+11+1, \ + RSC(CREATE_SELECT_FREQ_OFFLINE).CODE(), cpu); \ + \ + memcpy(grid->cell.item, item, grid->cell.length); \ + \ + memcpy( grid->cell.attr, \ + RSC(CREATE_SELECT_FREQ_COND1).ATTR(), \ + grid->cell.length ); \ + \ + grid->cell.quick.key = SCANKEY_NULL; \ + grid->data[0].ullong = (unsigned long long) (CPU_OFFLINE | cpu);\ + } \ + } \ + else \ + { \ + CPU_Item_Turbo_##_NC(cpu, item); \ + memcpy(grid->cell.item, item, grid->cell.length); \ + if ((data[0].ullong & CPU_STATE_MASK) == CPU_OFFLINE) \ + { \ + memcpy( grid->cell.attr, \ + RSC(CREATE_SELECT_FREQ_COND0).ATTR(), \ + grid->cell.length ); \ + \ + grid->cell.quick.key = BOXKEY_TURBO_CLOCK_##_NC | (cpu ^ CORE_COUNT);\ + grid->data[0].ullong = (unsigned long long) (CPU_ONLINE | cpu); \ + } \ + } \ +} +DECLARE_CPU_Update_Turbo( 1C) +DECLARE_CPU_Update_Turbo( 2C) +DECLARE_CPU_Update_Turbo( 3C) +DECLARE_CPU_Update_Turbo( 4C) +DECLARE_CPU_Update_Turbo( 5C) +DECLARE_CPU_Update_Turbo( 6C) +DECLARE_CPU_Update_Turbo( 7C) +DECLARE_CPU_Update_Turbo( 8C) +DECLARE_CPU_Update_Turbo( 9C) +DECLARE_CPU_Update_Turbo(10C) +DECLARE_CPU_Update_Turbo(11C) +DECLARE_CPU_Update_Turbo(12C) +DECLARE_CPU_Update_Turbo(13C) +DECLARE_CPU_Update_Turbo(14C) +DECLARE_CPU_Update_Turbo(15C) +DECLARE_CPU_Update_Turbo(16C) +DECLARE_CPU_Update_Turbo(17C) +DECLARE_CPU_Update_Turbo(18C) +#undef DECLARE_CPU_Update_Turbo + +void Pkg_Item_Target_Freq(ASCII *item) +{ + unsigned int top = Ruler.Top[BOOST(TGT)]; + + Pkg_Fmt_Freq( item, RSC(CREATE_SELECT_FREQ_TGT).CODE(), + &RO(Shm)->Cpu[top].FlipFlop[ + !RO(Shm)->Cpu[top].Toggle + ].Clock, + RO(Shm)->Cpu[top].Boost[BOOST(TGT)], + RO(Shm)->Proc.Features.TgtRatio_Unlock ); +} + +void Pkg_Target_Freq_Update(TGrid *grid, DATA_TYPE data[]) +{ + ASCII item[RSZ(CREATE_SELECT_FREQ_OFFLINE)+9+10+1]; + unsigned int top = Ruler.Top[BOOST(TGT)]; + UNUSED(data); + + Pkg_Fmt_Freq( item, RSC(CREATE_SELECT_FREQ_TGT).CODE(), + &RO(Shm)->Cpu[top].FlipFlop[ + !RO(Shm)->Cpu[top].Toggle + ].Clock, + RO(Shm)->Cpu[top].Boost[BOOST(TGT)], + RO(Shm)->Proc.Features.TgtRatio_Unlock ); + + memcpy(grid->cell.item, item, grid->cell.length); +} + +void CPU_Item_Target_Freq(unsigned int cpu, ASCII *item) +{ + struct FLIP_FLOP *CFlop; + CFlop = &RO(Shm)->Cpu[cpu].FlipFlop[ !RO(Shm)->Cpu[cpu].Toggle ]; + + if (RO(Shm)->Cpu[cpu].Boost[BOOST(TGT)] == 0) { + CPU_Item_Auto_Freq( cpu, RO(Shm)->Cpu[cpu].Boost[BOOST(TGT)], + RO(Shm)->Proc.Features.TgtRatio_Unlock, item ); + } else { + StrFormat(item, + RSZ(CREATE_SELECT_FREQ_OFFLINE)+10+11+11+11+4+6+10+1, + " %03u %4d%6d %-3d" "[%3.0f ]%5.0f MHz %c%4u %c ", + cpu, + RO(Shm)->Cpu[cpu].Topology.PackageID, + RO(Shm)->Cpu[cpu].Topology.CoreID, + RO(Shm)->Cpu[cpu].Topology.ThreadID, + CFlop->Absolute.Ratio.Perf, + CFlop->Absolute.Freq, + RO(Shm)->Proc.Features.TgtRatio_Unlock ? '<' : '[', + RO(Shm)->Cpu[cpu].Boost[BOOST(TGT)], + RO(Shm)->Proc.Features.TgtRatio_Unlock ? '>' : ']'); + } +} + +void CPU_Target_Freq_Update(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int cpu = data[0].ullong & CPU_MASK; + ASCII item[RSZ(CREATE_SELECT_FREQ_OFFLINE)+10+11+11+11+8+1]; + + if (BITVAL(RO(Shm)->Cpu[cpu].OffLine, OS)) + { + if ((data[0].ullong & CPU_STATE_MASK) == CPU_ONLINE) + { + StrFormat(item, RSZ(CREATE_SELECT_FREQ_OFFLINE)+10+11+11+11+1, + RSC(CREATE_SELECT_FREQ_OFFLINE).CODE(), cpu); + + memcpy(grid->cell.item, item, grid->cell.length); + + memcpy( grid->cell.attr, + RSC(CREATE_SELECT_FREQ_COND1).ATTR(), + grid->cell.length ); + + grid->cell.quick.key = SCANKEY_NULL; + grid->data[0].ullong = (unsigned long long) (CPU_OFFLINE | cpu); + } + } + else + { + CPU_Item_Target_Freq(cpu, item); + + memcpy(grid->cell.item, item, grid->cell.length); + + if ((data[0].ullong & CPU_STATE_MASK) == CPU_OFFLINE) + { + memcpy( grid->cell.attr, + RSC(CREATE_SELECT_FREQ_COND0).ATTR(), + grid->cell.length ); + + grid->cell.quick.key = BOXKEY_RATIO_CLOCK_TGT | (cpu ^ CORE_COUNT); + grid->data[0].ullong = (unsigned long long) (CPU_ONLINE | cpu); + } + } +} + +void Pkg_Item_HWP_Target_Freq(ASCII *item) +{ + unsigned int top = Ruler.Top[BOOST(HWP_TGT)]; + const unsigned int isEnable = (RO(Shm)->Proc.Features.HWP_Enable == 1) + || (RO(Shm)->Proc.Features.ACPI_CPPC == 1); + + Pkg_Fmt_Freq( item, RSC(CREATE_SELECT_FREQ_HWP_TGT).CODE(), + &RO(Shm)->Cpu[top].FlipFlop[ + !RO(Shm)->Cpu[top].Toggle + ].Clock, + RO(Shm)->Cpu[top].Boost[BOOST(HWP_TGT)], + isEnable ); +} + +void Pkg_HWP_Target_Freq_Update(TGrid *grid, DATA_TYPE data[]) +{ + ASCII item[RSZ(CREATE_SELECT_FREQ_OFFLINE)+9+10+1]; + unsigned int top = Ruler.Top[BOOST(HWP_TGT)]; + const unsigned int isEnable = (RO(Shm)->Proc.Features.HWP_Enable == 1) + || (RO(Shm)->Proc.Features.ACPI_CPPC == 1); + UNUSED(data); + + Pkg_Fmt_Freq( item, RSC(CREATE_SELECT_FREQ_HWP_TGT).CODE(), + &RO(Shm)->Cpu[top].FlipFlop[ + !RO(Shm)->Cpu[top].Toggle + ].Clock, + RO(Shm)->Cpu[top].Boost[BOOST(HWP_TGT)], + isEnable ); + + memcpy(grid->cell.item, item, grid->cell.length); +} + +void CPU_Item_HWP_Target_Freq(unsigned int cpu, ASCII *item) +{ + struct FLIP_FLOP *CFlop; + CFlop = &RO(Shm)->Cpu[cpu].FlipFlop[ !RO(Shm)->Cpu[cpu].Toggle ]; + const unsigned int isEnable = (RO(Shm)->Proc.Features.HWP_Enable == 1) + || (RO(Shm)->Proc.Features.ACPI_CPPC == 1); + + if (RO(Shm)->Cpu[cpu].PowerThermal.HWP.Request.Desired_Perf == 0) { + CPU_Item_Auto_Freq( cpu, + RO(Shm)->Cpu[cpu].PowerThermal.HWP.Request.Desired_Perf, + isEnable, item ); + } else { + StrFormat(item, + RSZ(CREATE_SELECT_FREQ_OFFLINE)+10+11+11+11+8+10+1, + " %03u %4d%6d%6d " "%7.2f MHz %c%4u %c ", + cpu, + RO(Shm)->Cpu[cpu].Topology.PackageID, + RO(Shm)->Cpu[cpu].Topology.CoreID, + RO(Shm)->Cpu[cpu].Topology.ThreadID, + ABS_FREQ_MHz(double, + RO(Shm)->Cpu[cpu].PowerThermal.HWP.Request.Desired_Perf, + CFlop->Clock + ), + isEnable ? '<' : '[', + RO(Shm)->Cpu[cpu].PowerThermal.HWP.Request.Desired_Perf, + isEnable ? '>' : ']'); + } +} + +void CPU_HWP_Target_Freq_Update(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int cpu = data[0].ullong & CPU_MASK; + ASCII item[RSZ(CREATE_SELECT_FREQ_OFFLINE)+10+11+11+11+8+1]; + + if (BITVAL(RO(Shm)->Cpu[cpu].OffLine, OS)) + { + if ((data[0].ullong & CPU_STATE_MASK) == CPU_ONLINE) + { + StrFormat(item, RSZ(CREATE_SELECT_FREQ_OFFLINE)+10+11+11+11+1, + RSC(CREATE_SELECT_FREQ_OFFLINE).CODE(), cpu); + + memcpy(grid->cell.item, item, grid->cell.length); + + memcpy( grid->cell.attr, + RSC(CREATE_SELECT_FREQ_COND1).ATTR(), + grid->cell.length ); + + grid->cell.quick.key = SCANKEY_NULL; + grid->data[0].ullong = (unsigned long long) (CPU_OFFLINE | cpu); + } + } + else + { + CPU_Item_HWP_Target_Freq(cpu, item); + + memcpy(grid->cell.item, item, grid->cell.length); + + if ((data[0].ullong & CPU_STATE_MASK) == CPU_OFFLINE) + { + memcpy( grid->cell.attr, + RSC(CREATE_SELECT_FREQ_COND0).ATTR(), + grid->cell.length ); + + grid->cell.quick.key = BOXKEY_RATIO_CLOCK_HWP_TGT | (cpu ^ CORE_COUNT); + grid->data[0].ullong = (unsigned long long) (CPU_ONLINE | cpu); + } + } +} + +void Pkg_Item_HWP_Max_Freq(ASCII *item) +{ + unsigned int top = Ruler.Top[BOOST(HWP_MAX)]; + const unsigned int isEnable = (RO(Shm)->Proc.Features.HWP_Enable == 1) + || (RO(Shm)->Proc.Features.ACPI_CPPC == 1); + + Pkg_Fmt_Freq( item, RSC(CREATE_SELECT_FREQ_HWP_MAX).CODE(), + &RO(Shm)->Cpu[top].FlipFlop[ + !RO(Shm)->Cpu[top].Toggle + ].Clock, + RO(Shm)->Cpu[top].Boost[BOOST(HWP_MAX)], + isEnable ); +} + +void Pkg_HWP_Max_Freq_Update(TGrid *grid, DATA_TYPE data[]) +{ + ASCII item[RSZ(CREATE_SELECT_FREQ_OFFLINE)+9+10+1]; + unsigned int top = Ruler.Top[BOOST(HWP_MAX)]; + const unsigned int isEnable = (RO(Shm)->Proc.Features.HWP_Enable == 1) + || (RO(Shm)->Proc.Features.ACPI_CPPC == 1); + UNUSED(data); + + Pkg_Fmt_Freq( item, RSC(CREATE_SELECT_FREQ_HWP_MAX).CODE(), + &RO(Shm)->Cpu[top].FlipFlop[ + !RO(Shm)->Cpu[top].Toggle + ].Clock, + RO(Shm)->Cpu[top].Boost[BOOST(HWP_MAX)], + isEnable ); + + memcpy(grid->cell.item, item, grid->cell.length); +} + +void CPU_Item_HWP_Max_Freq(unsigned int cpu, ASCII *item) +{ + struct FLIP_FLOP *CFlop; + CFlop = &RO(Shm)->Cpu[cpu].FlipFlop[ !RO(Shm)->Cpu[cpu].Toggle ]; + const unsigned int isEnable = (RO(Shm)->Proc.Features.HWP_Enable == 1) + || (RO(Shm)->Proc.Features.ACPI_CPPC == 1); + + if (RO(Shm)->Cpu[cpu].PowerThermal.HWP.Request.Maximum_Perf == 0) { + CPU_Item_Auto_Freq( cpu, + RO(Shm)->Cpu[cpu].PowerThermal.HWP.Request.Maximum_Perf, + isEnable, item ); + } else { + StrFormat(item, + RSZ(CREATE_SELECT_FREQ_OFFLINE)+10+11+11+11+8+10+1, + " %03u %4d%6d%6d " "%7.2f MHz %c%4u %c ", + cpu, + RO(Shm)->Cpu[cpu].Topology.PackageID, + RO(Shm)->Cpu[cpu].Topology.CoreID, + RO(Shm)->Cpu[cpu].Topology.ThreadID, + ABS_FREQ_MHz(double, + RO(Shm)->Cpu[cpu].PowerThermal.HWP.Request.Maximum_Perf, + CFlop->Clock + ), + isEnable ? '<' : '[', + RO(Shm)->Cpu[cpu].PowerThermal.HWP.Request.Maximum_Perf, + isEnable ? '>' : ']'); + } +} + +void CPU_HWP_Max_Freq_Update(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int cpu = data[0].ullong & CPU_MASK; + ASCII item[RSZ(CREATE_SELECT_FREQ_OFFLINE)+10+11+11+11+8+1]; + + if (BITVAL(RO(Shm)->Cpu[cpu].OffLine, OS)) + { + if ((data[0].ullong & CPU_STATE_MASK) == CPU_ONLINE) + { + StrFormat(item, RSZ(CREATE_SELECT_FREQ_OFFLINE)+10+11+11+11+1, + RSC(CREATE_SELECT_FREQ_OFFLINE).CODE(), cpu); + + memcpy(grid->cell.item, item, grid->cell.length); + + memcpy( grid->cell.attr, + RSC(CREATE_SELECT_FREQ_COND1).ATTR(), + grid->cell.length ); + + grid->cell.quick.key = SCANKEY_NULL; + grid->data[0].ullong = (unsigned long long) (CPU_OFFLINE | cpu); + } + } + else + { + CPU_Item_HWP_Max_Freq(cpu, item); + + memcpy(grid->cell.item, item, grid->cell.length); + + if ((data[0].ullong & CPU_STATE_MASK) == CPU_OFFLINE) + { + memcpy( grid->cell.attr, + RSC(CREATE_SELECT_FREQ_COND0).ATTR(), + grid->cell.length ); + + grid->cell.quick.key = BOXKEY_RATIO_CLOCK_HWP_MAX | (cpu ^ CORE_COUNT); + grid->data[0].ullong = (unsigned long long) (CPU_ONLINE | cpu); + } + } +} + +void Pkg_Item_HWP_Min_Freq(ASCII *item) +{ + unsigned int top = Ruler.Top[BOOST(HWP_MIN)]; + const unsigned int isEnable = (RO(Shm)->Proc.Features.HWP_Enable == 1) + || (RO(Shm)->Proc.Features.ACPI_CPPC == 1); + + Pkg_Fmt_Freq( item, RSC(CREATE_SELECT_FREQ_HWP_MIN).CODE(), + &RO(Shm)->Cpu[top].FlipFlop[ + !RO(Shm)->Cpu[top].Toggle + ].Clock, + RO(Shm)->Cpu[top].Boost[BOOST(HWP_MIN)], + isEnable ); +} + +void Pkg_HWP_Min_Freq_Update(TGrid *grid, DATA_TYPE data[]) +{ + ASCII item[RSZ(CREATE_SELECT_FREQ_OFFLINE)+9+10+1]; + unsigned int top = Ruler.Top[BOOST(HWP_MIN)]; + const unsigned int isEnable = (RO(Shm)->Proc.Features.HWP_Enable == 1) + || (RO(Shm)->Proc.Features.ACPI_CPPC == 1); + UNUSED(data); + + Pkg_Fmt_Freq( item, RSC(CREATE_SELECT_FREQ_HWP_MIN).CODE(), + &RO(Shm)->Cpu[top].FlipFlop[ + !RO(Shm)->Cpu[top].Toggle + ].Clock, + RO(Shm)->Cpu[top].Boost[BOOST(HWP_MIN)], + isEnable ); + + memcpy(grid->cell.item, item, grid->cell.length); +} + +void CPU_Item_HWP_Min_Freq(unsigned int cpu, ASCII *item) +{ + struct FLIP_FLOP *CFlop; + CFlop = &RO(Shm)->Cpu[cpu].FlipFlop[ !RO(Shm)->Cpu[cpu].Toggle ]; + const unsigned int isEnable = (RO(Shm)->Proc.Features.HWP_Enable == 1) + || (RO(Shm)->Proc.Features.ACPI_CPPC == 1); + + if (RO(Shm)->Cpu[cpu].PowerThermal.HWP.Request.Minimum_Perf == 0) { + CPU_Item_Auto_Freq( cpu, + RO(Shm)->Cpu[cpu].PowerThermal.HWP.Request.Minimum_Perf, + isEnable, item ); + } else { + StrFormat(item, + RSZ(CREATE_SELECT_FREQ_OFFLINE)+10+11+11+11+8+10+1, + " %03u %4d%6d%6d " "%7.2f MHz %c%4u %c ", + cpu, + RO(Shm)->Cpu[cpu].Topology.PackageID, + RO(Shm)->Cpu[cpu].Topology.CoreID, + RO(Shm)->Cpu[cpu].Topology.ThreadID, + ABS_FREQ_MHz(double, + RO(Shm)->Cpu[cpu].PowerThermal.HWP.Request.Minimum_Perf, + CFlop->Clock + ), + isEnable ? '<' : '[', + RO(Shm)->Cpu[cpu].PowerThermal.HWP.Request.Minimum_Perf, + isEnable ? '>' : ']'); + } +} + +void CPU_HWP_Min_Freq_Update(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int cpu = data[0].ullong & CPU_MASK; + ASCII item[RSZ(CREATE_SELECT_FREQ_OFFLINE)+10+11+11+11+8+1]; + + if (BITVAL(RO(Shm)->Cpu[cpu].OffLine, OS)) + { + if ((data[0].ullong & CPU_STATE_MASK) == CPU_ONLINE) + { + StrFormat(item, RSZ(CREATE_SELECT_FREQ_OFFLINE)+10+11+11+11+1, + RSC(CREATE_SELECT_FREQ_OFFLINE).CODE(), cpu); + + memcpy(grid->cell.item, item, grid->cell.length); + + memcpy( grid->cell.attr, + RSC(CREATE_SELECT_FREQ_COND1).ATTR(), + grid->cell.length ); + + grid->cell.quick.key = SCANKEY_NULL; + grid->data[0].ullong = (unsigned long long) (CPU_OFFLINE | cpu); + } + } + else + { + CPU_Item_HWP_Min_Freq(cpu, item); + + memcpy(grid->cell.item, item, grid->cell.length); + + if ((data[0].ullong & CPU_STATE_MASK) == CPU_OFFLINE) + { + memcpy( grid->cell.attr, + RSC(CREATE_SELECT_FREQ_COND0).ATTR(), + grid->cell.length ); + + grid->cell.quick.key = BOXKEY_RATIO_CLOCK_HWP_MIN | (cpu ^ CORE_COUNT); + grid->data[0].ullong = (unsigned long long) (CPU_ONLINE | cpu); + } + } +} + +void Pkg_Item_Max_Freq(ASCII *item) +{ + unsigned int top = Ruler.Top[BOOST(MAX)]; + + Pkg_Fmt_Freq( item, RSC(CREATE_SELECT_FREQ_MAX).CODE(), + &RO(Shm)->Cpu[top].FlipFlop[ + !RO(Shm)->Cpu[top].Toggle + ].Clock, + RO(Shm)->Cpu[top].Boost[BOOST(MAX)], + (RO(Shm)->Proc.Features.ClkRatio_Unlock & 0b10) == 0b10); +} + +void Pkg_Max_Freq_Update(TGrid *grid, DATA_TYPE data[]) +{ + ASCII item[RSZ(CREATE_SELECT_FREQ_OFFLINE)+9+10+1]; + unsigned int top = Ruler.Top[BOOST(MAX)]; + UNUSED(data); + + Pkg_Fmt_Freq( item, RSC(CREATE_SELECT_FREQ_MAX).CODE(), + &RO(Shm)->Cpu[top].FlipFlop[ + !RO(Shm)->Cpu[top].Toggle + ].Clock, + RO(Shm)->Cpu[top].Boost[BOOST(MAX)], + (RO(Shm)->Proc.Features.ClkRatio_Unlock & 0b10) == 0b10); + + memcpy(grid->cell.item, item, grid->cell.length); +} + +void CPU_Item_Max_Freq(unsigned int cpu, ASCII *item) +{ + struct FLIP_FLOP *CFlop; + CFlop = &RO(Shm)->Cpu[cpu].FlipFlop[ !RO(Shm)->Cpu[cpu].Toggle ]; + + if (RO(Shm)->Cpu[cpu].Boost[BOOST(MAX)] == 0) { + CPU_Item_Auto_Freq( cpu, RO(Shm)->Cpu[cpu].Boost[BOOST(MAX)], + (RO(Shm)->Proc.Features.ClkRatio_Unlock & 0b10) == 0b10, + item ); + } else { + StrFormat(item, + RSZ(CREATE_SELECT_FREQ_OFFLINE)+10+11+11+11+8+10+1, + " %03u %4d%6d%6d " "%7.2f MHz %c%4u %c ", + cpu, + RO(Shm)->Cpu[cpu].Topology.PackageID, + RO(Shm)->Cpu[cpu].Topology.CoreID, + RO(Shm)->Cpu[cpu].Topology.ThreadID, + ABS_FREQ_MHz( double, RO(Shm)->Cpu[cpu].Boost[BOOST(MAX)], + CFlop->Clock ), + (RO(Shm)->Proc.Features.ClkRatio_Unlock & 0b10) == 0b10 ? + '<' : '[', + RO(Shm)->Cpu[cpu].Boost[BOOST(MAX)], + (RO(Shm)->Proc.Features.ClkRatio_Unlock & 0b10) == 0b10 ? + '>' : ']'); + } +} + +void CPU_Max_Freq_Update(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int cpu = data[0].ullong & CPU_MASK; + ASCII item[RSZ(CREATE_SELECT_FREQ_OFFLINE)+10+11+11+11+8+1]; + + if (BITVAL(RO(Shm)->Cpu[cpu].OffLine, OS)) + { + if ((data[0].ullong & CPU_STATE_MASK) == CPU_ONLINE) + { + StrFormat(item, RSZ(CREATE_SELECT_FREQ_OFFLINE)+10+11+11+11+1, + RSC(CREATE_SELECT_FREQ_OFFLINE).CODE(), cpu); + + memcpy(grid->cell.item, item, grid->cell.length); + + memcpy( grid->cell.attr, + RSC(CREATE_SELECT_FREQ_COND1).ATTR(), + grid->cell.length ); + + grid->cell.quick.key = SCANKEY_NULL; + grid->data[0].ullong = (unsigned long long) (CPU_OFFLINE | cpu); + } + } + else + { + CPU_Item_Max_Freq(cpu, item); + + memcpy(grid->cell.item, item, grid->cell.length); + + if ((data[0].ullong & CPU_STATE_MASK) == CPU_OFFLINE) + { + memcpy( grid->cell.attr, + RSC(CREATE_SELECT_FREQ_COND0).ATTR(), + grid->cell.length ); + + grid->cell.quick.key = BOXKEY_RATIO_CLOCK_MAX | (cpu ^ CORE_COUNT); + grid->data[0].ullong = (unsigned long long) (CPU_ONLINE | cpu); + } + } +} + +void Pkg_Item_Min_Freq(ASCII *item) +{ + unsigned int top = Ruler.Top[BOOST(MIN)]; + + Pkg_Fmt_Freq( item, RSC(CREATE_SELECT_FREQ_MIN).CODE(), + &RO(Shm)->Cpu[top].FlipFlop[ + !RO(Shm)->Cpu[top].Toggle + ].Clock, + RO(Shm)->Cpu[top].Boost[BOOST(MIN)], + (RO(Shm)->Proc.Features.ClkRatio_Unlock & 0b01) == 0b01); +} + +void Pkg_Min_Freq_Update(TGrid *grid, DATA_TYPE data[]) +{ + ASCII item[RSZ(CREATE_SELECT_FREQ_OFFLINE)+9+10+1]; + unsigned int top = Ruler.Top[BOOST(MIN)]; + UNUSED(data); + + Pkg_Fmt_Freq( item, RSC(CREATE_SELECT_FREQ_MIN).CODE(), + &RO(Shm)->Cpu[top].FlipFlop[ + !RO(Shm)->Cpu[top].Toggle + ].Clock, + RO(Shm)->Cpu[top].Boost[BOOST(MIN)], + (RO(Shm)->Proc.Features.ClkRatio_Unlock & 0b01) == 0b01); + + memcpy(grid->cell.item, item, grid->cell.length); +} + +void CPU_Item_Min_Freq(unsigned int cpu, ASCII *item) +{ + struct FLIP_FLOP *CFlop; + CFlop = &RO(Shm)->Cpu[cpu].FlipFlop[ !RO(Shm)->Cpu[cpu].Toggle ]; + + if (RO(Shm)->Cpu[cpu].Boost[BOOST(MIN)] == 0) { + CPU_Item_Auto_Freq( cpu, RO(Shm)->Cpu[cpu].Boost[BOOST(MIN)], + (RO(Shm)->Proc.Features.ClkRatio_Unlock & 0b01) == 0b01, + item ); + } else { + StrFormat(item, + RSZ(CREATE_SELECT_FREQ_OFFLINE)+10+11+11+11+8+10+1, + " %03u %4d%6d%6d " "%7.2f MHz %c%4u %c ", + cpu, + RO(Shm)->Cpu[cpu].Topology.PackageID, + RO(Shm)->Cpu[cpu].Topology.CoreID, + RO(Shm)->Cpu[cpu].Topology.ThreadID, + ABS_FREQ_MHz( double, RO(Shm)->Cpu[cpu].Boost[BOOST(MIN)], + CFlop->Clock ), + (RO(Shm)->Proc.Features.ClkRatio_Unlock & 0b01) == 0b01 ? + '<' : '[', + RO(Shm)->Cpu[cpu].Boost[BOOST(MIN)], + (RO(Shm)->Proc.Features.ClkRatio_Unlock & 0b01) == 0b01 ? + '>' : ']'); + } +} + +void CPU_Min_Freq_Update(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int cpu = data[0].ullong & CPU_MASK; + ASCII item[RSZ(CREATE_SELECT_FREQ_OFFLINE)+10+11+11+11+8+1]; + + if (BITVAL(RO(Shm)->Cpu[cpu].OffLine, OS)) + { + if ((data[0].ullong & CPU_STATE_MASK) == CPU_ONLINE) + { + StrFormat(item, RSZ(CREATE_SELECT_FREQ_OFFLINE)+10+1, + RSC(CREATE_SELECT_FREQ_OFFLINE).CODE(), cpu); + + memcpy(grid->cell.item, item, grid->cell.length); + + memcpy( grid->cell.attr, + RSC(CREATE_SELECT_FREQ_COND1).ATTR(), + grid->cell.length ); + + grid->cell.quick.key = SCANKEY_NULL; + grid->data[0].ullong = (unsigned long long) (CPU_OFFLINE | cpu); + } + } + else + { + CPU_Item_Min_Freq(cpu, item); + + memcpy(grid->cell.item, item, grid->cell.length); + + if ((data[0].ullong & CPU_STATE_MASK) == CPU_OFFLINE) + { + memcpy( grid->cell.attr, + RSC(CREATE_SELECT_FREQ_COND0).ATTR(), + grid->cell.length ); + + grid->cell.quick.key = BOXKEY_RATIO_CLOCK_MIN | (cpu ^ CORE_COUNT); + grid->data[0].ullong = (unsigned long long) (CPU_ONLINE | cpu); + } + } +} + +Window *CreateSelectFreq(unsigned long long id, + PKG_ITEM_CALLBACK Pkg_Item_Callback, + CPU_ITEM_CALLBACK CPU_Item_Callback, + UPDATE_CALLBACK Pkg_Freq_Update, + UPDATE_CALLBACK CPU_Freq_Update) +{ + const CUINT _height = (Draw.Area.MaxRows << (ADD_UPPER & ADD_LOWER)) + #ifndef NO_FOOTER + + (ADD_UPPER | ADD_LOWER) + #endif + , height = CUMIN( (RO(Shm)->Proc.CPU.Count + 1), _height ); + + Window *wFreq = CreateWindow( wLayer, id, + 1, height, + 30, (TOP_HEADER_ROW | 1) ); + if (wFreq != NULL) + { + ASCII item[RSZ(CREATE_SELECT_FREQ_OFFLINE)+10+11+11+11+8+1]; + const unsigned long long all = id | (0xffff ^ CORE_COUNT); + unsigned int cpu; + + Pkg_Item_Callback(item); + + GridCall(StoreTCell(wFreq, all, (char*) item, + RSC(CREATE_SELECT_FREQ_PKG).ATTR()), + Pkg_Freq_Update); + + for (cpu = 0; cpu < RO(Shm)->Proc.CPU.Count; cpu++) + { + if (BITVAL(RO(Shm)->Cpu[cpu].OffLine, OS)) + { + StrFormat(item, RSZ(CREATE_SELECT_FREQ_OFFLINE)+10+1, + RSC(CREATE_SELECT_FREQ_OFFLINE).CODE(), cpu); + + GridCall( StoreTCell(wFreq, SCANKEY_NULL, + item, RSC(CREATE_SELECT_FREQ_COND1).ATTR()), + CPU_Freq_Update, (unsigned long long) (CPU_OFFLINE | cpu) ); + } + else + { + CPU_Item_Callback(cpu, item); + + GridCall( StoreTCell(wFreq, id | (cpu ^ CORE_COUNT), + item, RSC(CREATE_SELECT_FREQ_COND0).ATTR()), + CPU_Freq_Update, (unsigned long long) (CPU_ONLINE | cpu) ); + } + } + StoreWindow(wFreq, .title, (char*) RSC(SELECT_FREQ_TITLE).CODE()); + StoreWindow(wFreq, .color[1].title, wFreq->hook.color[1].border); + + StoreWindow(wFreq, .key.Enter, Enter_StickyCell); + StoreWindow(wFreq, .key.Down, MotionDown_Win); + StoreWindow(wFreq, .key.Up, MotionUp_Win); + StoreWindow(wFreq, .key.PgUp, MotionPgUp_Win); + StoreWindow(wFreq, .key.PgDw, MotionPgDw_Win); + StoreWindow(wFreq, .key.Home, MotionTop_Win); + StoreWindow(wFreq, .key.End, MotionBottom_Win); + + StoreWindow(wFreq, .key.WinLeft, MotionOriginLeft_Win); + StoreWindow(wFreq, .key.WinRight, MotionOriginRight_Win); + StoreWindow(wFreq, .key.WinDown, MotionOriginDown_Win); + StoreWindow(wFreq, .key.WinUp, MotionOriginUp_Win); + } + return wFreq; +} + +Window *CreateSelectIdle(unsigned long long id) +{ + Window *wIdle = CreateWindow(wLayer, id, + 1, 1 + RO(Shm)->SysGate.OS.IdleDriver.stateCount, + (Draw.Size.width - (2 + RSZ(BOX_IDLE_LIMIT_TITLE))) / 2, + TOP_HEADER_ROW + 2, + WINFLAG_NO_STOCK); + + if (wIdle != NULL) + { + signed int idx; + + StoreTCell(wIdle, BOXKEY_LIMIT_IDLE_ST00, + RSC(BOX_IDLE_LIMIT_RESET).CODE(), + RSC(UI).ATTR()[UI_WIN_SELECT_IDLE_RESET]); + + for (idx = 0; idx < RO(Shm)->SysGate.OS.IdleDriver.stateCount; idx++) + { + StrFormat(Buffer, 12+11+10+1, + " %2d%10.*s ", 1 + idx, + 10, RO(Shm)->SysGate.OS.IdleDriver.State[idx].Name); + + StoreTCell(wIdle, (BOXKEY_LIMIT_IDLE_ST00 + | ((1 + (unsigned long long)idx) << 4)), + Buffer, + RSC(UI).ATTR()[UI_WIN_SELECT_IDLE_POLL]); + } + StoreWindow(wIdle, .title, (char*) RSC(BOX_IDLE_LIMIT_TITLE).CODE()); + + wIdle->matrix.select.row = RO(Shm)->SysGate.OS.IdleDriver.stateLimit \ + < RO(Shm)->SysGate.OS.IdleDriver.stateCount ? + RO(Shm)->SysGate.OS.IdleDriver.stateLimit : 0; + + TCellAt(wIdle, 0, wIdle->matrix.select.row).attr[ 8] = \ + TCellAt(wIdle, 0, wIdle->matrix.select.row).attr[ 9] = \ + TCellAt(wIdle, 0, wIdle->matrix.select.row).attr[10] = \ + TCellAt(wIdle, 0, wIdle->matrix.select.row).attr[11] = \ + TCellAt(wIdle, 0, wIdle->matrix.select.row).attr[12] = \ + TCellAt(wIdle, 0, wIdle->matrix.select.row).attr[13] = \ + TCellAt(wIdle, 0, wIdle->matrix.select.row).attr[14] = \ + TCellAt(wIdle, 0, wIdle->matrix.select.row).attr[15] = \ + TCellAt(wIdle, 0, wIdle->matrix.select.row).attr[16] = \ + RSC(UI).ATTR()[UI_WIN_SELECT_IDLE_CURRENT]; + TCellAt(wIdle, 0, wIdle->matrix.select.row).item[ 8] = '<'; + if (wIdle->matrix.select.row > 9) { + TCellAt(wIdle, 0, wIdle->matrix.select.row).item[15] = '>'; + } else { + TCellAt(wIdle, 0, wIdle->matrix.select.row).item[16] = '>'; + } + StoreWindow(wIdle, .key.Enter, MotionEnter_Cell); + StoreWindow(wIdle, .key.Down, MotionDown_Win); + StoreWindow(wIdle, .key.Up, MotionUp_Win); + StoreWindow(wIdle, .key.Home, MotionTop_Win); + StoreWindow(wIdle, .key.End, MotionBottom_Win); + + StoreWindow(wIdle, .key.WinLeft, MotionOriginLeft_Win); + StoreWindow(wIdle, .key.WinRight, MotionOriginRight_Win); + StoreWindow(wIdle, .key.WinDown, MotionOriginDown_Win); + StoreWindow(wIdle, .key.WinUp, MotionOriginUp_Win); + + StoreWindow(wIdle, .key.Shrink, MotionShrink_Win); + StoreWindow(wIdle, .key.Expand, MotionExpand_Win); + } + return wIdle; +} + +Window *CreateThermalOffsetWindow(unsigned long long id) +{ + Window *wTHO = CreateWindow( wLayer, id, + 1, 31, + (MIN_WIDTH - 21) >> 1, + TOP_HEADER_ROW + 1, + WINFLAG_NO_STOCK|WINFLAG_NO_VSB ); + if (wTHO != NULL) + { + char item[11+19+1]; + unsigned long long bits, key; + signed short circle, loop; + for (loop = 0; loop < 2; loop++) + for (circle = -31; circle < +32; circle++) + { + const unsigned short word = circle; + bits = ((unsigned long long) word) << 20, + key = BOXKEY_THM_OP | bits; + + if (Setting.fahrCels) { + int fahrenheit = Cels2Fahr(circle); + StrFormat(item, 11+19+1 , " %c%3d F ", + fahrenheit < 0 ? '-' : fahrenheit > 0 ? '+' : ' ', + abs(fahrenheit)); + } else { + StrFormat(item, 11+19+1 , " %c%2d C ", + circle < 0 ? '-' : circle > 0 ? '+' : ' ', + abs(circle)); + } + StoreTCell(wTHO, key, item, + circle == 0 ? RSC(UI).ATTR()[UI_WHEEL_CURRENT] + : RSC(UI).ATTR()[UI_WHEEL_LIST]); + } + wTHO->matrix.select.row = wTHO->matrix.size.hth >> 1; + wTHO->matrix.scroll.vert = 16; + + StoreWindow(wTHO, .title,(char*)RSC(THERMAL_OFFSET_TITLE).CODE()); + + StoreWindow(wTHO, .key.Enter, MotionEnter_Cell); + StoreWindow(wTHO, .key.Up, MotionUp_Wheel); + StoreWindow(wTHO, .key.Down, MotionDown_Wheel); + StoreWindow(wTHO, .key.PgUp, MotionPgUp_Wheel); + StoreWindow(wTHO, .key.PgDw, MotionPgDw_Wheel); + StoreWindow(wTHO, .key.Home, MotionHome_Wheel); + StoreWindow(wTHO, .key.End, MotionEnd_Wheel); + + StoreWindow(wTHO, .key.WinLeft, MotionOriginLeft_Win); + StoreWindow(wTHO, .key.WinRight, MotionOriginRight_Win); + StoreWindow(wTHO, .key.WinDown, MotionOriginDown_Win); + StoreWindow(wTHO, .key.WinUp, MotionOriginUp_Win); + + StoreWindow(wTHO, .color[1].select, RSC(UI).ATTR()[UI_WHEEL_SELECT]); + } + return wTHO; +} + +#define TW_START_Z 0b000 +#define TW_START_Y 0b00000 +#define TW_STOP_Z 0b011 +#define TW_STOP_Y 0b10010 +#define TW_POST_Y 0b10011 +#define TW_POST_Z 0b000 + +#define TW_CELL_COUNT(adj) ( \ + (1 + (TW_STOP_Z - TW_START_Z)) \ + * (1 + (TW_STOP_Y - TW_START_Y)) \ + + adj \ +) + +#define TW_CELL_HEIGHT (TW_CELL_COUNT(0) >> 2) +#define TW_CELL_WIDTH 18 + +struct TW_ST { + double TAU; + unsigned char TW; +}; + +void InsertionSortTW( struct TW_ST base[], + unsigned int cnt, + enum RATIO_BOOST start ) +{ + __typeof__(start) lt = start + 1, rt; + while (lt < cnt) + { + rt = lt; + while ((rt > start) && (base[rt - 1].TAU > base[rt].TAU)) + { + __typeof__(base[0]) swap; + swap.TAU = base[rt - 1].TAU; + swap.TW = base[rt - 1].TW; + + base[rt - 1].TAU = base[rt].TAU; + base[rt - 1].TW = base[rt].TW; + + base[rt].TAU = swap.TAU; + base[rt].TW = swap.TW; + + rt = rt - 1; + } + lt = lt + 1; + } +} + +Window *CreatePowerTimeWindow(unsigned long long id) +{ + Window *wPTW = NULL; + const enum PWR_DOMAIN pw = (id >> 5) & BOXKEY_TDP_MASK; + const enum PWR_LIMIT pl = id & 0b11; + + struct TW_ST *array = calloc(TW_CELL_COUNT(+1), sizeof(struct TW_ST)); + if (array != NULL) + { + signed int idx = 0, fdx = -1; + unsigned char Y, Z; + for (Y = TW_START_Y; Y <= TW_STOP_Y; Y++) + for (Z = TW_START_Z; Z <= TW_STOP_Z; Z++) + { + array[idx].TAU = COMPUTE_TAU(Y, Z, RO(Shm)->Proc.Power.Unit.Times); + array[idx].TW = COMPUTE_TW(Y, Z); + + if ((fdx == -1) + && (array[idx].TW == RO(Shm)->Proc.Power.Domain[pw].Feature[pl].TW)) { + fdx = idx; + } + idx++; + } + if (fdx == -1) { + array[idx].TAU = RO(Shm)->Proc.Power.Domain[pw].TAU[pl]; + array[idx].TW = RO(Shm)->Proc.Power.Domain[pw].Feature[pl].TW; + } else { + array[idx].TAU = COMPUTE_TAU( TW_POST_Y, TW_POST_Z, + RO(Shm)->Proc.Power.Unit.Times ); + + array[idx].TW = COMPUTE_TW(TW_POST_Y, TW_POST_Z); + } + + InsertionSortTW(array, TW_CELL_COUNT(+1), 0); + + wPTW = CreateWindow( wLayer, id, + 1, TW_CELL_HEIGHT, + (MIN_WIDTH - TW_CELL_WIDTH) >> 1, + TOP_HEADER_ROW + 1, + WINFLAG_NO_VSB ); + if (wPTW != NULL) + { + const ASCII *labelTW[PWR_LIMIT_SIZE] = { + RSC(POWER_LABEL_TW1).CODE(), + RSC(POWER_LABEL_TW2).CODE() + }; + const ASCII *labelDom[DOMAIN_SIZE] = { + RSC(POWER_LABEL_PKG).CODE(), + RSC(POWER_LABEL_CORE).CODE(), + RSC(POWER_LABEL_UNCORE).CODE(), + RSC(POWER_LABEL_DRAM).CODE(), + RSC(POWER_LABEL_PLATFORM).CODE() + }; + char item[3*20+5+1]; + + unsigned long long us, ms, ss, bits, key; + unsigned char circle; + for (circle = 0, fdx = -1; circle < 2; circle++) + for (idx = 0; idx < TW_CELL_COUNT(+1); idx++) + { + bits = ((unsigned long long) array[idx].TW) << 20, + key = (BOXKEY_TW_OP | (0x8ULL << pl)) | (pw << 5) | bits; + + us = 1000LLU * 1000LLU * array[idx].TAU; + ms = 1000LLU * array[idx].TAU; + ss = array[idx].TAU; + us = us % 1000LLU; + ms = ms % 1000LLU; + + if (us) { + StrFormat(item, 3*20+5+1, " %7llu,%03llu%-3llu ",ss, ms, us); + } else if (ms) { + StrFormat(item, 2*20+8+1, " %7llu,%-3llu ", ss, ms); + } else { + StrFormat(item, 20+11+1 , " %7llu ", ss); + } + if (array[idx].TW == RO(Shm)->Proc.Power.Domain[pw].Feature[pl].TW) { + StoreTCell(wPTW, key, item, RSC(UI).ATTR()[UI_WHEEL_CURRENT]); + fdx = idx; + } else { + StoreTCell(wPTW, key, item, RSC(UI).ATTR()[UI_WHEEL_LIST]); + } + } + + wPTW->matrix.select.row = wPTW->matrix.size.hth >> 1; + + if (fdx >= 0) { + if (fdx >= wPTW->matrix.select.row) { + wPTW->matrix.scroll.vert = fdx - wPTW->matrix.select.row; + } else { + wPTW->matrix.scroll.vert = (wPTW->dim >> 1) + - (wPTW->matrix.select.row - fdx); + } + } else { + wPTW->matrix.scroll.vert = 0; + } + + StrFormat(item, TW_CELL_WIDTH+1, " %s %s ", labelDom[pw], labelTW[pl]); + StoreWindow(wPTW, .title, item); + + StoreWindow(wPTW, .key.Enter, MotionEnter_Cell); + StoreWindow(wPTW, .key.Up, MotionUp_Wheel); + StoreWindow(wPTW, .key.Down, MotionDown_Wheel); + StoreWindow(wPTW, .key.PgUp, MotionPgUp_Wheel); + StoreWindow(wPTW, .key.PgDw, MotionPgDw_Wheel); + StoreWindow(wPTW, .key.Home, MotionHome_Wheel); + StoreWindow(wPTW, .key.End, MotionEnd_Wheel); + + StoreWindow(wPTW, .key.WinLeft, MotionOriginLeft_Win); + StoreWindow(wPTW, .key.WinRight, MotionOriginRight_Win); + StoreWindow(wPTW, .key.WinDown, MotionOriginDown_Win); + StoreWindow(wPTW, .key.WinUp, MotionOriginUp_Win); + + StoreWindow(wPTW, .color[1].select, RSC(UI).ATTR()[UI_WHEEL_SELECT]); + } + free(array); + } + return wPTW; +} + +#undef TW_CELL_WIDTH +#undef TW_CELL_HEIGHT +#undef TW_CELL_COUNT +#undef TW_POST_Y +#undef TW_POST_Z +#undef TW_STOP_Y +#undef TW_STOP_Z +#undef TW_START_Y +#undef TW_START_Z + +#define EVENT_DOMAINS 4 +#define EVENT_SECTIONS 12 + +void Update_Event(TGrid *grid, DATA_TYPE data[]) +{ + const enum THERM_PWR_EVENTS events[eDIM] = { + data[eLOG].ullong, data[eSTS].ullong + }; + const ATTRIBUTE *attrib[eDIM][eDIM] = { + {RSC(BOX_EVENT_COND00).ATTR(), RSC(BOX_EVENT_COND01).ATTR()}, + {RSC(BOX_EVENT_COND10).ATTR(), RSC(BOX_EVENT_COND11).ATTR()} + }; + const unsigned int eTheme[eDIM] = { + (events[eLOG] != EVENT_THERM_NONE) + && (RO(Shm)->ProcessorEvents[eLOG] & events[eLOG]), + + (events[eSTS] != EVENT_THERM_NONE) + && (RO(Shm)->ProcessorEvents[eSTS] & events[eSTS]) + }; + memcpy( grid->cell.attr, + attrib[eTheme[eLOG]][eTheme[eSTS]], + grid->cell.length - 1 ); +} + +Window *CreateEvents(unsigned long long id) +{ + struct EVENT_LDR_ST { + SCANKEY quick; + ASCII *item; + enum THERM_PWR_EVENTS events[eDIM]; + } eLdr[EVENT_DOMAINS][EVENT_SECTIONS] = { + { + /* Thermal Sensor */ + { {BOXKEY_CLR_THM_SENSOR} , RSC(BOX_EVENT_THERMAL_SENSOR).CODE(), + {EVENT_THERMAL_LOG , EVENT_THERMAL_STS} }, + /* PROCHOT# Agent */ + { {BOXKEY_CLR_PROCHOT_LOG}, RSC(BOX_EVENT_PROCHOT_STS).CODE(), + {EVENT_PROCHOT_LOG , EVENT_PROCHOT_STS} }, + /* Critical Temperature */ + { {BOXKEY_CLR_THM_CRIT} , RSC(BOX_EVENT_CRITICAL_TEMP).CODE(), + {EVENT_CRITIC_LOG , EVENT_CRITIC_TMP} }, + /* Thermal Threshold */ + { {BOXKEY_CLR_THM_THOLD1} , RSC(BOX_EVENT_THOLD1_STS).CODE(), + {EVENT_THOLD1_LOG , EVENT_THOLD1_STS} }, + /* Thermal Threshold */ + { {BOXKEY_CLR_THM_THOLD2} , RSC(BOX_EVENT_THOLD2_STS).CODE(), + {EVENT_THOLD2_LOG , EVENT_THOLD2_STS} }, + /* Power Limitation */ + { {BOXKEY_CLR_PWR_LIMIT} , RSC(BOX_EVENT_POWER_LIMIT).CODE(), + {EVENT_POWER_LIMIT , EVENT_THERM_NONE} }, + /* Current Limitation */ + { {BOXKEY_CLR_CUR_LIMIT} , RSC(BOX_EVENT_CURRENT_LIMIT).CODE(), + {EVENT_CURRENT_LIMIT , EVENT_THERM_NONE} }, + /* Cross Domain Limit. */ + { {BOXKEY_CLR_X_DOMAIN} , RSC(BOX_EVENT_CROSS_DOM_LIMIT).CODE(), + {EVENT_CROSS_DOMAIN , EVENT_THERM_NONE} }, + /* Blank cell */ + { {SCANKEY_NULL} , RSC(BOX_EVENT_SPACE).CODE(), + {EVENT_THERM_NONE , EVENT_THERM_NONE} }, + /* Blank cell */ + { {SCANKEY_NULL} , RSC(BOX_EVENT_SPACE).CODE(), + {EVENT_THERM_NONE , EVENT_THERM_NONE} }, + /* Blank cell */ + { {SCANKEY_NULL} , RSC(BOX_EVENT_SPACE).CODE(), + {EVENT_THERM_NONE , EVENT_THERM_NONE} }, + /* Blank cell */ + { {SCANKEY_NULL} , RSC(BOX_EVENT_SPACE).CODE(), + {EVENT_THERM_NONE , EVENT_THERM_NONE} } + }, { + /* Thermal Sensor */ + { {BOXKEY_CLR_CORE_THM} , RSC(BOX_EVENT_THERMAL_SENSOR).CODE(), + {EVENT_CORE_THM_LOG , EVENT_CORE_THM_STS} }, + /* PROCHOT# Agent */ + { {BOXKEY_CLR_CORE_HOT} , RSC(BOX_EVENT_PROCHOT_STS).CODE(), + {EVENT_CORE_HOT_LOG , EVENT_CORE_HOT_STS} }, + /* Avg Thermal */ + { {BOXKEY_CLR_CORE_AVG} , RSC(BOX_EVENT_AVG_THERMAL).CODE(), + {EVENT_CORE_AVG_LOG , EVENT_CORE_AVG_STS} }, + /* VR Thermal */ + { {BOXKEY_CLR_CORE_VRT} , RSC(BOX_EVENT_VR_THERMAL).CODE(), + {EVENT_CORE_VRT_LOG , EVENT_CORE_VRT_STS} }, + /* VR TDC */ + { {BOXKEY_CLR_CORE_TDC} , RSC(BOX_EVENT_VR_TDC).CODE(), + {EVENT_CORE_TDC_LOG , EVENT_CORE_TDC_STS} }, + /* Package PL1 */ + { {BOXKEY_CLR_CORE_PL1} , RSC(BOX_EVENT_POWER_PL1).CODE(), + {EVENT_CORE_PL1_LOG , EVENT_CORE_PL1_STS} }, + /* Package PL2 */ + { {BOXKEY_CLR_CORE_PL2} , RSC(BOX_EVENT_POWER_PL2).CODE(), + {EVENT_CORE_PL2_LOG , EVENT_CORE_PL2_STS} }, + /* Electrical EDP */ + { {BOXKEY_CLR_CORE_EDP} , RSC(BOX_EVENT_ELECTRICAL).CODE(), + {EVENT_CORE_EDP_LOG , EVENT_CORE_EDP_STS} }, + /* Residency */ + { {BOXKEY_CLR_CORE_RES} , RSC(BOX_EVENT_RESIDENCY).CODE(), + {EVENT_CORE_RES_LOG , EVENT_CORE_RES_STS} }, + /* Max Turbo Limit. */ + { {BOXKEY_CLR_CORE_BST} , RSC(BOX_EVENT_MAX_TURBO).CODE(), + {EVENT_CORE_BST_LOG , EVENT_CORE_BST_STS} }, + /* Turbo Transition Attenuation */ + { {BOXKEY_CLR_CORE_ATT} , RSC(BOX_EVENT_TURBO_ATTEN).CODE(), + {EVENT_CORE_ATT_LOG , EVENT_CORE_ATT_STS} }, + /* Thermal Velocity Boost */ + { {BOXKEY_CLR_CORE_TVB} , RSC(BOX_EVENT_THERMAL_TVB).CODE(), + {EVENT_CORE_TVB_LOG , EVENT_CORE_TVB_STS} } + }, { + /* Thermal Sensor */ + { {BOXKEY_CLR_GFX_THM} , RSC(BOX_EVENT_THERMAL_SENSOR).CODE(), + {EVENT_GFX_THM_LOG , EVENT_GFX_THM_STS} }, + /* PROCHOT# Agent */ + { {BOXKEY_CLR_GFX_HOT} , RSC(BOX_EVENT_PROCHOT_STS).CODE(), + {EVENT_GFX_HOT_LOG , EVENT_GFX_HOT_STS} }, + /* Avg Thermal */ + { {BOXKEY_CLR_GFX_AVG} , RSC(BOX_EVENT_AVG_THERMAL).CODE(), + {EVENT_GFX_AVG_LOG , EVENT_GFX_AVG_STS} }, + /* VR Thermal */ + { {BOXKEY_CLR_GFX_VRT} , RSC(BOX_EVENT_VR_THERMAL).CODE(), + {EVENT_GFX_VRT_LOG , EVENT_GFX_VRT_STS} }, + /* VR TDC */ + { {BOXKEY_CLR_GFX_TDC} , RSC(BOX_EVENT_VR_TDC).CODE(), + {EVENT_GFX_TDC_LOG , EVENT_GFX_TDC_STS} }, + /* Package PL1 */ + { {BOXKEY_CLR_GFX_PL1} , RSC(BOX_EVENT_POWER_PL1).CODE(), + {EVENT_GFX_PL1_LOG , EVENT_GFX_PL1_STS} }, + /* Package PL2 */ + { {BOXKEY_CLR_GFX_PL2} , RSC(BOX_EVENT_POWER_PL2).CODE(), + {EVENT_GFX_PL2_LOG , EVENT_GFX_PL2_STS} }, + /* Electrical EDP */ + { {BOXKEY_CLR_GFX_EDP} , RSC(BOX_EVENT_ELECTRICAL).CODE(), + {EVENT_GFX_EDP_LOG , EVENT_GFX_EDP_STS} }, + /* Inefficiency Ops */ + { {BOXKEY_CLR_GFX_EFF} , RSC(BOX_EVENT_INEFFICIENCY).CODE(), + {EVENT_GFX_EFF_LOG , EVENT_GFX_EFF_STS} }, + /* Blank cell */ + { {SCANKEY_NULL} , RSC(BOX_EVENT_SPACE).CODE(), + {EVENT_THERM_NONE , EVENT_THERM_NONE} }, + /* Blank cell */ + { {SCANKEY_NULL} , RSC(BOX_EVENT_SPACE).CODE(), + {EVENT_THERM_NONE , EVENT_THERM_NONE} }, + /* Blank cell */ + { {SCANKEY_NULL} , RSC(BOX_EVENT_SPACE).CODE(), + {EVENT_THERM_NONE , EVENT_THERM_NONE} } + }, { + /* Thermal Sensor */ + { {BOXKEY_CLR_RING_THM} , RSC(BOX_EVENT_THERMAL_SENSOR).CODE(), + {EVENT_RING_THM_LOG , EVENT_RING_THM_STS} }, + /* PROCHOT# Agent */ + { {BOXKEY_CLR_RING_HOT} , RSC(BOX_EVENT_PROCHOT_STS).CODE(), + {EVENT_RING_HOT_LOG , EVENT_RING_HOT_STS} }, + /* Avg Thermal */ + { {BOXKEY_CLR_RING_AVG} , RSC(BOX_EVENT_AVG_THERMAL).CODE(), + {EVENT_RING_AVG_LOG , EVENT_RING_AVG_STS} }, + /* VR Thermal */ + { {BOXKEY_CLR_RING_VRT} , RSC(BOX_EVENT_VR_THERMAL).CODE(), + {EVENT_RING_VRT_LOG , EVENT_RING_VRT_STS} }, + /* VR TDC */ + { {BOXKEY_CLR_RING_TDC} , RSC(BOX_EVENT_VR_TDC).CODE(), + {EVENT_RING_TDC_LOG , EVENT_RING_TDC_STS} }, + /* Package PL1 */ + { {BOXKEY_CLR_RING_PL1} , RSC(BOX_EVENT_POWER_PL1).CODE(), + {EVENT_RING_PL1_LOG , EVENT_RING_PL1_STS} }, + /* Package PL2 */ + { {BOXKEY_CLR_RING_PL2} , RSC(BOX_EVENT_POWER_PL2).CODE(), + {EVENT_RING_PL2_LOG , EVENT_RING_PL2_STS} }, + /* Electrical EDP */ + { {BOXKEY_CLR_RING_EDP} , RSC(BOX_EVENT_ELECTRICAL).CODE(), + {EVENT_RING_EDP_LOG , EVENT_RING_EDP_STS} }, + /* Blank cell */ + { {SCANKEY_NULL} , RSC(BOX_EVENT_SPACE).CODE(), + {EVENT_THERM_NONE , EVENT_THERM_NONE} }, + /* Blank cell */ + { {SCANKEY_NULL} , RSC(BOX_EVENT_SPACE).CODE(), + {EVENT_THERM_NONE , EVENT_THERM_NONE} }, + /* Blank cell */ + { {SCANKEY_NULL} , RSC(BOX_EVENT_SPACE).CODE(), + {EVENT_THERM_NONE , EVENT_THERM_NONE} }, + /* Blank cell */ + { {SCANKEY_NULL} , RSC(BOX_EVENT_SPACE).CODE(), + {EVENT_THERM_NONE , EVENT_THERM_NONE} } + } + }; + const size_t nmemb = sizeof(eLdr) / sizeof(struct EVENT_LDR_ST); + + Window *wEvent = CreateWindow( wLayer, id, + EVENT_DOMAINS, + 1 + (nmemb / EVENT_DOMAINS), + 6, TOP_HEADER_ROW + 2 ); + if (wEvent != NULL) + { + ATTRIBUTE *attrib[eDIM][eDIM] = { + {RSC(BOX_EVENT_COND00).ATTR(), RSC(BOX_EVENT_COND01).ATTR()}, + {RSC(BOX_EVENT_COND10).ATTR(), RSC(BOX_EVENT_COND11).ATTR()} + }; + CUINT col, row; + for (row = 0; row < EVENT_SECTIONS; row++) { + for (col = 0; col < EVENT_DOMAINS; col++) { + const unsigned int eTheme[eDIM] = { + (eLdr[col][row].events[eLOG] != EVENT_THERM_NONE) + && (RO(Shm)->ProcessorEvents[eLOG] & eLdr[col][row].events[eLOG]), + + (eLdr[col][row].events[eSTS] != EVENT_THERM_NONE) + && (RO(Shm)->ProcessorEvents[eSTS] & eLdr[col][row].events[eSTS]) + }; + + TGrid *grid=StoreTCell( wEvent, + eLdr[col][row].quick.key, + eLdr[col][row].item, + attrib[eTheme[eLOG]][eTheme[eSTS]] ); + + GridCall(grid, Update_Event, + eLdr[col][row].events[eLOG], eLdr[col][row].events[eSTS]); + } + } + for (col = 0; col < EVENT_DOMAINS - 1; col++) { + StoreTCell(wEvent, SCANKEY_NULL, + RSC(BOX_EVENT_SPACE).CODE(), + RSC(BOX_EVENT_COND00).ATTR()); + } + StoreTCell(wEvent, BOXKEY_CLR_ALL_EVENTS, + RSC(BOX_EVENT_ALL_OF_THEM).CODE(), + RSC(BOX_EVENT_BUTTON).ATTR()); + + wEvent->matrix.select.col = wEvent->matrix.size.wth - 1; + wEvent->matrix.select.row = wEvent->matrix.size.hth - 1; + + StoreWindow(wEvent, .title, (char*) RSC(BOX_EVENT_TITLE).CODE()); + StoreWindow(wEvent, .color[1].title, wEvent->hook.color[1].border); + + StoreWindow(wEvent, .key.Enter, Enter_StickyCell); + StoreWindow(wEvent, .key.Left, MotionLeft_Win); + StoreWindow(wEvent, .key.Right, MotionRight_Win); + StoreWindow(wEvent, .key.Down, MotionDown_Win); + StoreWindow(wEvent, .key.Up, MotionUp_Win); + StoreWindow(wEvent, .key.PgUp, MotionPgUp_Win); + StoreWindow(wEvent, .key.PgDw, MotionPgDw_Win); + StoreWindow(wEvent, .key.Home, MotionHome_Win); + StoreWindow(wEvent, .key.End, MotionEnd_Win); + + StoreWindow(wEvent, .key.WinLeft, MotionOriginLeft_Win); + StoreWindow(wEvent, .key.WinRight, MotionOriginRight_Win); + StoreWindow(wEvent, .key.WinDown, MotionOriginDown_Win); + StoreWindow(wEvent, .key.WinUp, MotionOriginUp_Win); + + StoreWindow(wEvent, .key.Shrink, MotionShrink_Win); + StoreWindow(wEvent, .key.Expand, MotionExpand_Win); + } + return wEvent; +} + +#undef EVENT_DOMAINS +#undef EVENT_SECTIONS + +Window *CreateClockSource(unsigned long long id) +{ + const unsigned int count = (unsigned int) RO(Shm)->CS.index[0]; + + Window *wCS = CreateWindow( wLayer, id, 1, count + 1, + 22, TOP_HEADER_ROW + 7, + WINFLAG_NO_STOCK ); + if (wCS != NULL) + { + const char *current = RO(Shm)->CS.array; + CUINT row = 1; + unsigned int idx; + + StoreTCell(wCS, SCANKEY_NULL, RSC(BOX_BLANK_DESC).CODE(), + RSC(UI).ATTR()[UI_BOX_ENABLE_STATE]); + + for (idx = 1; idx < count; idx++) + { + const unsigned long long key = OPS_CLOCK_SOURCE | idx; + const char *avail = &RO(Shm)->CS.array[RO(Shm)->CS.index[idx]]; + char *format; + CUINT lt, rt, li = strlen(avail); + ATTRIBUTE attrib; + + lt = RSZ(BOX_BLANK_DESC) - li; + rt = lt >> 1; + lt = rt + (lt & 0x1); + + if (!strcmp(current, avail)) { + format = "%.*s" "< %s >" "%.*s"; + attrib = RSC(UI).ATTR()[UI_BOX_DISABLE_STATE]; + row = (CUINT) (idx - 1); + lt = lt - 3; + rt = rt - 3; + } else { + format = "%.*s" "%s" "%.*s"; + attrib = RSC(UI).ATTR()[UI_BOX_ENABLE_STATE]; + } + StrLenFormat(li, Buffer, MAX_UTS_LEN, + format, lt, HSPACE, avail, rt, HSPACE); + + StoreTCell(wCS, key, Buffer, attrib); + } + StoreTCell(wCS, SCANKEY_NULL, RSC(BOX_BLANK_DESC).CODE(), + RSC(UI).ATTR()[UI_BOX_ENABLE_STATE]); + + wCS->matrix.select.row = 1 + row; + + StoreWindow(wCS, .title, (char*) RSC(BOX_CLOCK_SOURCE_TITLE).CODE()); + + StoreWindow(wCS, .key.Enter, MotionEnter_Cell); + StoreWindow(wCS, .key.Down, MotionDown_Win); + StoreWindow(wCS, .key.Up, MotionUp_Win); + StoreWindow(wCS, .key.Home, MotionReset_Win); + StoreWindow(wCS, .key.End, MotionEnd_Cell); + } + return wCS; +} + +Window *CreateRecorder(unsigned long long id) +{ + Window *wRec = CreateWindow( wLayer, id, + 1, 8, 43, TOP_HEADER_ROW+4, + WINFLAG_NO_STOCK ); + if (wRec != NULL) + { + unsigned int idx = 1; + do { + unsigned long long key = OPS_RECORDER | (idx << 4); + unsigned int duration = Recorder.Ratios[idx] * RECORDER_DEFAULT, + remainder = duration % (60 * 60), + hours = duration / (60 * 60), + minutes = remainder / 60, + seconds = remainder % 60; + + StrFormat(Buffer, 6+11+11+11+1, + "\x20\x20%02u:%02u:%02u\x20\x20", + hours, minutes, seconds); + + StoreTCell( wRec, + key, + Buffer, + RSC(CREATE_RECORDER).ATTR() ); + + } while (Recorder.Ratios[++idx] != 0); + + if (Recorder.Select > 0) { + wRec->matrix.select.row = Recorder.Select - 1; + } + StoreWindow(wRec, .title, (char*) RSC(BOX_RECORDER_TITLE).CODE()); + + StoreWindow(wRec, .key.WinLeft, MotionOriginLeft_Win); + StoreWindow(wRec, .key.WinRight, MotionOriginRight_Win); + StoreWindow(wRec, .key.WinDown, MotionOriginDown_Win); + StoreWindow(wRec, .key.WinUp, MotionOriginUp_Win); + StoreWindow(wRec, .key.Enter, MotionEnter_Cell); + StoreWindow(wRec, .key.Down, MotionDown_Win); + StoreWindow(wRec, .key.Up, MotionUp_Win); + StoreWindow(wRec, .key.Home, MotionReset_Win); + StoreWindow(wRec, .key.End, MotionEnd_Cell); + StoreWindow(wRec, .key.Shrink, MotionShrink_Win); + StoreWindow(wRec, .key.Expand, MotionExpand_Win); + } + return wRec; +} + +#define POPUP_WIDTH (MIN_WIDTH - 2) +#define POPUP_ALLOC (POPUP_WIDTH + 1) + +Window *PopUpMessage(ASCII *title, RING_CTRL *pCtrl) +{ + char *sysMsg, *item = NULL, *inStr = NULL, *outStr = NULL; + Window *wMsg = NULL; + + if (((item = malloc(POPUP_ALLOC)) != NULL) + && ((inStr = malloc(POPUP_ALLOC)) != NULL) + && ((outStr = malloc(POPUP_ALLOC)) != NULL)) + { + item[POPUP_WIDTH] = '\0'; + + wMsg = CreateWindow( wLayer, pCtrl->arg, + 1, 5, + 1, Draw.Size.height - (1 + 5), + WINFLAG_NO_STOCK ); + if (wMsg != NULL) + { + struct tm *brokTime, localTime; + time_t execTime; + size_t hdrLen, sysLen; + + execTime = RO(Shm)->StartedAt + pCtrl->tds; + brokTime = localtime_r(&execTime, &localTime); + + switch ( GET_LOCALE() ) { + case LOC_FR: /* Convert the local time in ASCII */ + hdrLen = strftime(inStr, POPUP_ALLOC, "%c", brokTime); + ISO_8859_To_Unicode((ASCII *) inStr, (ASCII *) outStr); + break; + case LOC_EN: /* Keep the default language. No conversion. */ + default: + hdrLen = strftime(outStr, POPUP_ALLOC, "%c", brokTime); + break; + } + + if (pCtrl->drc < RC_DRIVER_BASE) + { + #ifdef __GLIBC__ + sysMsg = strerror_r(pCtrl->drc, inStr, POPUP_ALLOC); + #else + sysMsg = strerror(pCtrl->drc); + #endif + switch ( GET_LOCALE() ) { + case LOC_FR: /* Convert the System message to locale */ + ISO_8859_To_Unicode((ASCII *) sysMsg, (ASCII *) inStr); + sysMsg = inStr; + break; + case LOC_EN: + default: /* No conversion required. */ + break; + } + sysLen = sysMsg != NULL ? strlen(sysMsg) : 0; + } else { + struct { + enum REASON_CLASS rc; + ASCII *code; + CUINT len; + } drvReason[] = { + { + RC_UNIMPLEMENTED, + RSC(ERROR_UNIMPLEMENTED).CODE() , RSZ(ERROR_UNIMPLEMENTED) + }, + { + RC_EXPERIMENTAL, + RSC(ERROR_EXPERIMENTAL).CODE() , RSZ(ERROR_EXPERIMENTAL) + }, + { + RC_TURBO_PREREQ, + RSC(ERROR_TURBO_PREREQ).CODE() , RSZ(ERROR_TURBO_PREREQ) + }, + { + RC_UNCORE_PREREQ, + RSC(ERROR_UNCORE_PREREQ).CODE() , RSZ(ERROR_UNCORE_PREREQ) + }, + { + RC_PSTATE_NOT_FOUND, + RSC(ERROR_PSTATE_NOT_FOUND).CODE(), RSZ(ERROR_PSTATE_NOT_FOUND) + }, + { + RC_CLOCKSOURCE, + RSC(ERROR_CLOCKSOURCE).CODE(), RSZ(ERROR_CLOCKSOURCE) + } + }; + const size_t count = sizeof(drvReason) / sizeof(drvReason[0]); + size_t idx; + for (idx = 0; idx < count; idx++) { + if (drvReason[idx].rc == pCtrl->drc) { + break; + } + } + if (idx < count) { + sysMsg = (char *) drvReason[idx].code; + sysLen = drvReason[idx].len; + } else { + sysMsg = NULL; + sysLen = 0; + } + } + memset(item, 0x20, POPUP_WIDTH); + if ((hdrLen > 0) && (hdrLen < POPUP_WIDTH)) { + memcpy(&item[POPUP_WIDTH - hdrLen], outStr, hdrLen); + } + hdrLen = (size_t) sprintf(outStr, "[%x:%llx]", pCtrl->cmd, pCtrl->arg); + if ((hdrLen > 0) && (hdrLen < POPUP_WIDTH)) { + memcpy(item, outStr, hdrLen); + } + StoreTCell(wMsg, SCANKEY_NULL, item, + RSC(UI).ATTR()[UI_WIN_POPUP_MSG_ITEM]); + + memset(item, 0x20, POPUP_WIDTH); + StoreTCell(wMsg, SCANKEY_NULL, item, + RSC(UI).ATTR()[UI_WIN_POPUP_MSG_ITEM]); + + if ((sysLen > 0) && (sysLen < POPUP_WIDTH)) { + memcpy(&item[(POPUP_WIDTH / 2) - (sysLen / 2)], sysMsg,sysLen); + } else { + memcpy(item, sysMsg, POPUP_WIDTH); + } + StoreTCell(wMsg, SCANKEY_NULL, item, + RSC(UI).ATTR()[UI_WIN_POPUP_MSG_ITEM]); + + memset(item, 0x20, POPUP_WIDTH); + StoreTCell(wMsg, SCANKEY_NULL, item, + RSC(UI).ATTR()[UI_WIN_POPUP_MSG_ITEM]); + + StoreTCell(wMsg, SCANKEY_NULL, item, + RSC(UI).ATTR()[UI_WIN_POPUP_MSG_ITEM]); + + StoreWindow(wMsg, .color[0].select, + RSC(UI).ATTR()[UI_WIN_POPUP_MSG_SELECT_UNFOCUS]); + + StoreWindow(wMsg, .color[1].select, + RSC(UI).ATTR()[UI_WIN_POPUP_MSG_SELECT_FOCUS]); + + StoreWindow(wMsg, .color[0].border, + RSC(UI).ATTR()[UI_WIN_POPUP_MSG_BORDER_UNFOCUS]); + + StoreWindow(wMsg, .color[1].border, + RSC(UI).ATTR()[UI_WIN_POPUP_MSG_BORDER_FOCUS]); + + StoreWindow(wMsg, .color[0].title, + RSC(UI).ATTR()[UI_WIN_POPUP_MSG_TITLE_UNFOCUS]); + + StoreWindow(wMsg, .color[1].title, + RSC(UI).ATTR()[UI_WIN_POPUP_MSG_TITLE_FOCUS]); + + StoreWindow(wMsg, .title, (char *) title); + } + } + if (outStr != NULL) { + free(outStr); + } + if (inStr != NULL) { + free(inStr); + } + if (item != NULL) { + free(item); + } + return wMsg; +} +#undef POPUP_ALLOC +#undef POPUP_WIDTH + +Window *_CreateBox( unsigned long long id, + Coordinate origin, + Coordinate select, + char *title, + ASCII *button, ...) +{ + struct PBOX { + int cnt; + struct SBOX { + unsigned long long key; + ASCII item[MIN_WIDTH]; + ATTRIBUTE attr; + } btn[]; + } *pBox = NULL; + int cnt = 0; + + va_list ap; + va_start(ap, button); + ASCII *item = button; + ATTRIBUTE attrib = va_arg(ap, ATTRIBUTE); + unsigned long long aKey = va_arg(ap, unsigned long long); + do { + if (item != NULL) { + size_t size; + cnt = (pBox == NULL) ? 1 : pBox->cnt + 1; + size = sizeof(struct PBOX) + + sizeof(struct SBOX) * (unsigned int) cnt; + if ((pBox = realloc(pBox, size)) != NULL) + { + size_t len = KMIN(strlen((char *) item), MIN_WIDTH); + memcpy((char*)pBox->btn[cnt - 1].item,(char *)item,len); + pBox->btn[cnt - 1].item[len] = '\0'; + pBox->btn[cnt - 1].attr = attrib; + pBox->btn[cnt - 1].key = aKey; + pBox->cnt = cnt; + } + item = va_arg(ap, ASCII*); + attrib = va_arg(ap, ATTRIBUTE); + aKey = va_arg(ap, unsigned long long); + } + } while (item != NULL) ; + va_end(ap); + + Window *wBox = NULL; + if (pBox != NULL) + { + wBox = CreateWindow( wLayer, id, + 1, pBox->cnt, origin.col, origin.row, + WINFLAG_NO_STOCK ); + if (wBox != NULL) { + wBox->matrix.select.col = select.col; + wBox->matrix.select.row = select.row; + + for (cnt = 0; cnt < pBox->cnt; cnt++) + StoreTCell( wBox, + pBox->btn[cnt].key, + pBox->btn[cnt].item, + pBox->btn[cnt].attr); + if (title != NULL) { + StoreWindow(wBox, .title, title); + } + StoreWindow(wBox, .key.Enter, MotionEnter_Cell); + StoreWindow(wBox, .key.Down, MotionDown_Win); + StoreWindow(wBox, .key.Up, MotionUp_Win); + StoreWindow(wBox, .key.Home, MotionReset_Win); + StoreWindow(wBox, .key.End, MotionEnd_Cell); + StoreWindow(wBox, .key.Shrink, MotionShrink_Win); + StoreWindow(wBox, .key.Expand, MotionExpand_Win); + } + free(pBox); + } + return wBox; +} + +#define CreateBox(id, origin, select, title, button, ...) \ + _CreateBox(id, origin, select, title, button, __VA_ARGS__,NULL) + +typedef struct { + ASCII *item; + CUINT length; + ATTRIBUTE attrib; + unsigned long long quick; +} IssueList; + +IssueList *FindIssues(CUINT *wth, CUINT *hth) +{ + struct { + IssueList issue; + unsigned short state; + } problem[] = { + { + { + RSC(RECORDER).CODE(), + RSZ(RECORDER), + RSC(UI).ATTR()[UI_WIN_EXIT_ISSUE_RECORDER], + SCANKEY_ALT_p + }, + DumpStatus() + }, + { + { + RSC(STRESS).CODE(), + RSZ(STRESS), + RSC(UI).ATTR()[UI_WIN_EXIT_ISSUE_STRESS], + BOXKEY_TOOLS_MACHINE + }, + BITVAL(RW(Shm)->Proc.Sync, BURN) + }, + { + { + RSC(KERNEL_IDLE_DRIVER).CODE(), + RSZ(KERNEL_IDLE_DRIVER), + RSC(UI).ATTR()[UI_WIN_EXIT_ISSUE_OS_CPU_IDLE], + OPS_CPU_IDLE + }, + (RO(Shm)->Registration.Driver.CPUidle == REGISTRATION_ENABLE) + } + }; + IssueList *list = NULL; + CUINT idx; + for (idx = 0, (*hth) = 0; + idx < (CUINT) (sizeof(problem) / sizeof(problem[0])); idx++) + { + if (problem[idx].state) + { + if ((list = realloc(list, (1+(*hth)) * sizeof(IssueList))) != NULL) + { + list[(*hth)].item = problem[idx].issue.item; + list[(*hth)].length = problem[idx].issue.length; + list[(*hth)].attrib = problem[idx].issue.attrib; + list[(*hth)].quick = problem[idx].issue.quick; + + (*wth) = CUMAX((*wth), list[(*hth)].length); + (*hth) = (*hth) + 1; + } + } + } + return list; +} + +Window *CreateExit(unsigned long long id, IssueList *issue, CUINT wth,CUINT hth) +{ + Window *wExit; + + wExit = CreateWindow( wLayer, id, + 1, (hth + 6), + (Draw.Size.width - wth) / 2, + (hth + 6) > Draw.Size.height ? + 1 : (Draw.Size.height - (hth + 2)) / 2, + WINFLAG_NO_STOCK ); + if (wExit != NULL) + { + CUINT idx; + + StoreTCell( wExit, SCANKEY_NULL, RSC(EXIT_HEADER).CODE(), + RSC(UI).ATTR()[UI_WIN_EXIT_HEADER] ); + + memset(Buffer, 0x20, wth); + Buffer[wth] = '\0'; + StoreTCell( wExit, SCANKEY_NULL, Buffer, + RSC(UI).ATTR()[UI_WIN_EXIT_BLANK] ); + + for (idx = 0; idx < hth; idx++) + { + const CUINT pos = (wth - issue[idx].length) / 2; + memset(Buffer, 0x20, wth); + memcpy(&Buffer[pos], issue[idx].item, issue[idx].length); + Buffer[wth] = '\0'; + + StoreTCell(wExit, issue[idx].quick, Buffer, issue[idx].attrib); + }; + memset(Buffer, 0x20, wth); + Buffer[wth] = '\0'; + StoreTCell( wExit, SCANKEY_NULL, Buffer, + RSC(UI).ATTR()[UI_WIN_EXIT_BLANK] ); + + StoreTCell( wExit, SCANKEY_CTRL_ALT_x, RSC(EXIT_CONFIRM).CODE(), + RSC(UI).ATTR()[UI_WIN_EXIT_CONFIRM] ); + + memset(Buffer, 0x20, wth); + Buffer[wth] = '\0'; + StoreTCell( wExit, SCANKEY_NULL, Buffer, + RSC(UI).ATTR()[UI_WIN_EXIT_BLANK] ); + + StoreTCell( wExit, SCANKEY_NULL, RSC(EXIT_FOOTER).CODE(), + RSC(UI).ATTR()[UI_WIN_EXIT_FOOTER] ); + + wExit->matrix.select.row = 2; + + StoreWindow(wExit, .key.Enter, MotionEnter_Cell); + StoreWindow(wExit, .key.Down, MotionDown_Win); + StoreWindow(wExit, .key.Up, MotionUp_Win); + StoreWindow(wExit, .key.Home, MotionReset_Win); + StoreWindow(wExit, .key.End, MotionEnd_Cell); + StoreWindow(wExit, .title, (char*) RSC(EXIT_TITLE).CODE()); + } + return wExit; +} + +void TrapScreenSize(int caught) +{ + if (caught == SIGWINCH) + { + SCREEN_SIZE currentSize = GetScreenSize(); + CUINT areaMaxRows = 1; + + if (currentSize.height != Draw.Size.height) + { + if (currentSize.height > MAX_HEIGHT) { + Draw.Size.height = MAX_HEIGHT; + } else { + Draw.Size.height = currentSize.height; + } + switch (Draw.Disposal) { + case D_MAINVIEW: + Draw.Area.MinHeight = (ADD_LOWER * (Draw.View == V_PACKAGE ? 10 : 0)) + + TOP_HEADER_ROW + + TOP_SEPARATOR + + TOP_FOOTER_ROW; + break; + default: + Draw.Area.MinHeight = LEADING_TOP + 2 * (MARGIN_HEIGHT + INTER_HEIGHT); + break; + } + Draw.Flag.clear = 1; + Draw.Flag.height = !(Draw.Size.height < Draw.Area.MinHeight); + } + if (currentSize.width != Draw.Size.width) { + if (currentSize.width > MAX_WIDTH) { + Draw.Size.width = MAX_WIDTH; + } else { + Draw.Size.width = currentSize.width; + } + Draw.Flag.clear = 1; + Draw.Flag.width = !(Draw.Size.width < MIN_WIDTH); + } + if ((ADD_UPPER | ADD_LOWER) && (Draw.Size.height > Draw.Area.MinHeight)) { + areaMaxRows = Draw.Size.height - Draw.Area.MinHeight; + if (Draw.View != V_PACKAGE) { + areaMaxRows = areaMaxRows >> (ADD_UPPER & ADD_LOWER); + } + if (!areaMaxRows) { + areaMaxRows = 1; + } + } + Draw.Area.MaxRows = CUMIN(RO(Shm)->Proc.CPU.Count, areaMaxRows); + Draw.Area.LoadWidth = Draw.Size.width - LOAD_LEAD; + Draw.cpuScroll = 0; + + if (Draw.Flag.clear == 1 ) { + ReScaleAllWindows(&winList); + } + } +} + +int Shortcut(SCANKEY *scan) +{ + const ATTRIBUTE stateAttr[2] = { + RSC(UI).ATTR()[UI_BOX_ENABLE_STATE], + RSC(UI).ATTR()[UI_BOX_DISABLE_STATE] + }, + blankAttr = RSC(UI).ATTR()[UI_BOX_BLANK], + descAttr = RSC(UI).ATTR()[UI_BOX_DESC]; + + const ASCII *stateStr[2][2] = { + { + RSC(BOX_DISABLE_COND0).CODE(), + RSC(BOX_DISABLE_COND1).CODE() + },{ + RSC(BOX_ENABLE_COND0).CODE(), + RSC(BOX_ENABLE_COND1).CODE() + } + }; + + switch (scan->key) { + case SCANKEY_DOWN: + if (!IsDead(&winList)) { + return -1; + } + fallthrough; + case SCANKEY_PLUS: + if ((Draw.Disposal == D_MAINVIEW) + && (Draw.cpuScroll < (RO(Shm)->Proc.CPU.Count - Draw.Area.MaxRows))) + { + Draw.cpuScroll++; + Draw.Flag.layout = 1; + } + break; + + case SCANKEY_UP: + if (!IsDead(&winList)) { + return -1; + } + fallthrough; + case SCANKEY_MINUS: + if ((Draw.Disposal == D_MAINVIEW) && (Draw.cpuScroll > 0)) { + Draw.cpuScroll--; + Draw.Flag.layout = 1; + } + break; + + case SCANKEY_HOME: + case SCANCON_HOME: + case SCANSYM_HOME: + if (!IsDead(&winList)) { + return -1; + } else if (Draw.Disposal == D_MAINVIEW) { + Draw.cpuScroll = 0; + Draw.Flag.layout = 1; + } + break; + + case SCANKEY_END: + case SCANCON_END: + case SCANSYM_END: + if (!IsDead(&winList)) { + return -1; + } else if (Draw.Disposal == D_MAINVIEW) { + Draw.cpuScroll = RO(Shm)->Proc.CPU.Count - Draw.Area.MaxRows; + Draw.Flag.layout = 1; + } + break; + + case SCANKEY_PGDW: + if (!IsDead(&winList)) { + return -1; + } else if (Draw.Disposal == D_MAINVIEW) { + if ( (Draw.cpuScroll + Draw.Area.MaxRows) < (RO(Shm)->Proc.CPU.Count + - Draw.Area.MaxRows ) ) + { + Draw.cpuScroll += Draw.Area.MaxRows; + } else { + Draw.cpuScroll = RO(Shm)->Proc.CPU.Count - Draw.Area.MaxRows; + } + Draw.Flag.layout = 1; + } + break; + + case SCANKEY_PGUP: + if (!IsDead(&winList)) { + return -1; + } else if (Draw.Disposal == D_MAINVIEW) { + if (Draw.cpuScroll >= Draw.Area.MaxRows) { + Draw.cpuScroll -= Draw.Area.MaxRows; + } else { + Draw.cpuScroll = 0; + } + Draw.Flag.layout = 1; + } + break; + + case SCANKEY_AST: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE(RW(Shm)->Ring[0], COREFREQ_IOCTL_SYSUPDT); + } + break; + + case SCANKEY_OPEN_BRACE: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_MACHINE, + COREFREQ_TOGGLE_ON, + MACHINE_CONTROLLER ); + } + break; + + case SCANKEY_CLOSE_BRACE: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_MACHINE, + COREFREQ_TOGGLE_OFF, + MACHINE_CONTROLLER ); + } + break; + + case SCANKEY_F2: + case SCANCON_F2: + case SCANSYM_F2: + { + Window *win = SearchWinListById(SCANKEY_F2, &winList); + if (win == NULL) { + AppendWindow(CreateMenu(SCANKEY_F2, 0), &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case SCANKEY_F3: + case SCANCON_F3: + case SCANSYM_F3: + { + Window *win = SearchWinListById(SCANKEY_F2, &winList); + if (win == NULL) { + AppendWindow(CreateMenu(SCANKEY_F2, 1), &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case SCANKEY_F4: + case SCANCON_F4: + case SCANSYM_F4: + { + Window *win = SearchWinListById(SCANKEY_F2, &winList); + if (win == NULL) { + AppendWindow(CreateMenu(SCANKEY_F2, 2), &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case SCANKEY_CTRL_u: + #if defined(UBENCH) && UBENCH == 1 + Draw.Flag.uBench = !Draw.Flag.uBench; + #endif + break; + + case SCANKEY_CTRL_ALT_x: + case SCANCON_CTRL_ALT_x: + BITSET(LOCKLESS, Shutdown, SYNC); + break; + + case SCANKEY_CTRL_x: + { + CUINT wth = RSZ(EXIT_HEADER), hth; + IssueList *issueList = FindIssues(&wth, &hth); + if (issueList != NULL) { + Window *win = SearchWinListById(SCANKEY_CTRL_x, &winList); + if (win == NULL) { + AppendWindow( CreateExit(SCANKEY_CTRL_x, issueList, wth, hth), + &winList ); + } else { + SetHead(&winList, win); + } + free(issueList); + } else { + BITSET(LOCKLESS, Shutdown, SYNC); + } + } + break; + + case OPS_INTERVAL: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + const Coordinate origin = { + .col = 43, + .row = TOP_HEADER_ROW + 4 + }, select = { + .col = 0, + .row = 5 + }; + AppendWindow( + CreateBox(scan->key, origin, select, + (char*) RSC(BOX_INTERVAL_TITLE).CODE(), + RSC(BOX_INTERVAL_STEP1).CODE(), + RSC(UI).ATTR()[UI_BOX_INTERVAL], OPS_INTERVAL_100, + RSC(BOX_INTERVAL_STEP2).CODE(), + RSC(UI).ATTR()[UI_BOX_INTERVAL], OPS_INTERVAL_150, + RSC(BOX_INTERVAL_STEP3).CODE(), + RSC(UI).ATTR()[UI_BOX_INTERVAL], OPS_INTERVAL_250, + RSC(BOX_INTERVAL_STEP4).CODE(), + RSC(UI).ATTR()[UI_BOX_INTERVAL], OPS_INTERVAL_500, + RSC(BOX_INTERVAL_STEP5).CODE(), + RSC(UI).ATTR()[UI_BOX_INTERVAL], OPS_INTERVAL_750, + RSC(BOX_INTERVAL_STEP6).CODE(), + RSC(UI).ATTR()[UI_BOX_INTERVAL], OPS_INTERVAL_1000, + RSC(BOX_INTERVAL_STEP7).CODE(), + RSC(UI).ATTR()[UI_BOX_INTERVAL], OPS_INTERVAL_1500, + RSC(BOX_INTERVAL_STEP8).CODE(), + RSC(UI).ATTR()[UI_BOX_INTERVAL], OPS_INTERVAL_2000, + RSC(BOX_INTERVAL_STEP9).CODE(), + RSC(UI).ATTR()[UI_BOX_INTERVAL], OPS_INTERVAL_2500, + RSC(BOX_INTERVAL_STEP10).CODE(), + RSC(UI).ATTR()[UI_BOX_INTERVAL],OPS_INTERVAL_3000), + &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case OPS_INTERVAL_100: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE(RW(Shm)->Ring[0], + COREFREQ_IOCTL_MACHINE, + 100, + MACHINE_INTERVAL ); + } + break; + + case OPS_INTERVAL_150: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_MACHINE, + 150, + MACHINE_INTERVAL ); + } + break; + + case OPS_INTERVAL_250: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_MACHINE, + 250, + MACHINE_INTERVAL ); + } + break; + + case OPS_INTERVAL_500: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_MACHINE, + 500, + MACHINE_INTERVAL ); + } + break; + + case OPS_INTERVAL_750: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_MACHINE, + 750, + MACHINE_INTERVAL ); + } + break; + + case OPS_INTERVAL_1000: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_MACHINE, + 1000, + MACHINE_INTERVAL ); + } + break; + + case OPS_INTERVAL_1500: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_MACHINE, + 1500, + MACHINE_INTERVAL ); + } + break; + + case OPS_INTERVAL_2000: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_MACHINE, + 2000, + MACHINE_INTERVAL ); + } + break; + + case OPS_INTERVAL_2500: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_MACHINE, + 2500, + MACHINE_INTERVAL ); + } + break; + + case OPS_INTERVAL_3000: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_MACHINE, + 3000, + MACHINE_INTERVAL ); + } + break; + + case OPS_AUTOCLOCK: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + const int bON = ((RO(Shm)->Registration.AutoClock & 0b10) != 0); + const Coordinate origin = { + .col = (Draw.Size.width - RSZ(BOX_BLANK_DESC)) / 2, + .row = TOP_HEADER_ROW + 4 + }, select = { + .col = 0, + .row = bON ? 2 : 1 + }; + AppendWindow( + CreateBox(scan->key, origin, select, + (char*) RSC(BOX_AUTO_CLOCK_TITLE).CODE(), + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL, + stateStr[1][bON] , stateAttr[bON] , OPS_AUTOCLOCK_ON, + stateStr[0][!bON], stateAttr[!bON], OPS_AUTOCLOCK_OFF, + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL), + &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case OPS_AUTOCLOCK_OFF: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_MACHINE, + COREFREQ_TOGGLE_OFF, + MACHINE_AUTOCLOCK ); + } + break; + + case OPS_AUTOCLOCK_ON: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_MACHINE, + COREFREQ_TOGGLE_ON, + MACHINE_AUTOCLOCK ); + } + break; + + case OPS_EXPERIMENTAL: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + ATTRIBUTE exp_Attr[2] = { + RSC(UI).ATTR()[UI_BOX_EXPERIMENTAL_WARNING], + RSC(UI).ATTR()[UI_BOX_EXPERIMENTAL_NOMINAL] + }; + ASCII *ops_Str[2][2] = { + { + RSC(BOX_NOMINAL_MODE_COND0).CODE(), + RSC(BOX_NOMINAL_MODE_COND1).CODE() + },{ + RSC(BOX_EXPERIMENT_MODE_COND0).CODE(), + RSC(BOX_EXPERIMENT_MODE_COND1).CODE() + } + }; + const Coordinate origin = { + .col = (Draw.Size.width - RSZ(BOX_BLANK_DESC)) / 2, + .row = TOP_HEADER_ROW + 3 + }, select = { + .col = 0, + .row = 3 + }; + AppendWindow( + CreateBox(scan->key, origin, select, + (char*) RSC(BOX_MODE_TITLE).CODE(), + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL, + RSC(BOX_MODE_DESC).CODE(), descAttr, SCANKEY_NULL, + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL, + ops_Str[0][RO(Shm)->Registration.Experimental == 0], + stateAttr[RO(Shm)->Registration.Experimental == 0], + OPS_EXPERIMENTAL_OFF, + ops_Str[1][RO(Shm)->Registration.Experimental != 0] , + exp_Attr[RO(Shm)->Registration.Experimental != 0], + OPS_EXPERIMENTAL_ON, + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL), + &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case OPS_EXPERIMENTAL_OFF: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_MACHINE, + COREFREQ_TOGGLE_OFF, + MACHINE_EXPERIMENTAL ); + } + break; + + case OPS_EXPERIMENTAL_ON: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_MACHINE, + COREFREQ_TOGGLE_ON, + MACHINE_EXPERIMENTAL ); + } + break; + + case OPS_IDLE_ROUTE: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + const Coordinate origin = { + .col = 43, + .row = TOP_HEADER_ROW + 17 + }, select = { + .col = 0, + .row = RO(Shm)->Registration.Driver.Route + }; + AppendWindow( + CreateBox(scan->key, origin, select, + (char *) RSC(SETTINGS_ROUTE_TITLE).CODE(), + RSC(SETTINGS_ROUTE_DFLT).CODE(), stateAttr[0], OPS_ROUTE_DFLT, + RSC(SETTINGS_ROUTE_IO).CODE(), stateAttr[0], OPS_ROUTE_IO, + RSC(SETTINGS_ROUTE_HALT).CODE(), stateAttr[0], OPS_ROUTE_HALT, + RSC(SETTINGS_ROUTE_MWAIT).CODE(),stateAttr[0], OPS_ROUTE_MWAIT), + &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case OPS_ROUTE_DFLT: + case OPS_ROUTE_IO: + case OPS_ROUTE_HALT: + case OPS_ROUTE_MWAIT: + { + enum IDLE_ROUTE idleRoute = (scan->key & BOXKEY_ROUTE_MASK) >> 4; + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_MACHINE, + idleRoute, + MACHINE_IDLE_ROUTE ); + } + } + break; + + case OPS_INTERRUPTS: + case OPS_CPU_IDLE: + case OPS_CPU_FREQ: + case OPS_GOVERNOR: + case OPS_CLOCK_SOURCE: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + ASCII *ops_Str[2][2] = { + { + RSC(BOX_OPS_REGISTER_COND0).CODE(), + RSC(BOX_OPS_REGISTER_COND1).CODE() + },{ + RSC(BOX_OPS_UNREGISTER_COND0).CODE(), + RSC(BOX_OPS_UNREGISTER_COND1).CODE() + } + }, *ops_title = NULL; + + unsigned long long ops_key_on = SCANKEY_NULL, + ops_key_off = SCANKEY_NULL; + unsigned int bix = 0; + + switch (scan->key) { + case OPS_INTERRUPTS: + ops_title = RSC(BOX_INTERRUPT_TITLE).CODE(); + ops_key_on = OPS_INTERRUPTS_ON; + ops_key_off = OPS_INTERRUPTS_OFF; + bix = BITWISEAND(LOCKLESS, + RO(Shm)->Registration.NMI,BIT_NMI_MASK) != 0; + break; + case OPS_CPU_IDLE: + ops_title = RSC(BOX_CPU_IDLE_TITLE).CODE(); + ops_key_on = OPS_CPU_IDLE_ON; + ops_key_off = OPS_CPU_IDLE_OFF; + bix = RO(Shm)->Registration.Driver.CPUidle + & REGISTRATION_ENABLE; + break; + case OPS_CPU_FREQ: + ops_title = RSC(BOX_CPU_FREQ_TITLE).CODE(); + ops_key_on = OPS_CPU_FREQ_ON; + ops_key_off = OPS_CPU_FREQ_OFF; + bix = RO(Shm)->Registration.Driver.CPUfreq + & REGISTRATION_ENABLE; + break; + case OPS_GOVERNOR: + ops_title = RSC(BOX_GOVERNOR_TITLE).CODE(); + ops_key_on = OPS_GOVERNOR_ON; + ops_key_off = OPS_GOVERNOR_OFF; + bix = RO(Shm)->Registration.Driver.Governor + & REGISTRATION_ENABLE; + break; + case OPS_CLOCK_SOURCE: + ops_title = RSC(BOX_CLOCK_SOURCE_TITLE).CODE(); + ops_key_on = OPS_CLOCK_SOURCE_ON; + ops_key_off = OPS_CLOCK_SOURCE_OFF; + bix = RO(Shm)->Registration.Driver.CS & REGISTRATION_ENABLE; + break; + } + const Coordinate origin = { + .col = (Draw.Size.width - RSZ(BOX_BLANK_DESC)) / 2, + .row = TOP_HEADER_ROW + 5 + }, select = { + .col = 0, + .row = bix == 0 ? 1 : 2 + }; + AppendWindow( + CreateBox(scan->key, origin, select, (char*) ops_title, + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL, + ops_Str[0][bix != 0], stateAttr[bix != 0], ops_key_on, + ops_Str[1][bix == 0], stateAttr[bix == 0], ops_key_off, + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL), + &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case OPS_CLOCK_SOURCE_1: + case OPS_CLOCK_SOURCE_2: + case OPS_CLOCK_SOURCE_3: + case OPS_CLOCK_SOURCE_4: + case OPS_CLOCK_SOURCE_5: + case OPS_CLOCK_SOURCE_6: + case OPS_CLOCK_SOURCE_7: + { + const unsigned short indexCS = scan->key & CLOCK_SOURCE_MASK; + + if (!RING_FULL(RW(Shm)->Ring[1])) { + RING_WRITE( RW(Shm)->Ring[1], + COREFREQ_KERNEL_MISC, + indexCS, + MACHINE_CLOCK_SOURCE ); + } + } + break; + + case OPS_CLOCK_SOURCE_SEL: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + AppendWindow(CreateClockSource(scan->key), &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case OPS_INTERRUPTS_OFF: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_MACHINE, + COREFREQ_TOGGLE_OFF, + MACHINE_INTERRUPTS ); + } + break; + + case OPS_INTERRUPTS_ON: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_MACHINE, + COREFREQ_TOGGLE_ON, + MACHINE_INTERRUPTS ); + } + break; + + case OPS_CPU_IDLE_OFF: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_MACHINE, + COREFREQ_TOGGLE_OFF, + MACHINE_CPU_IDLE ); + } + break; + + case OPS_CPU_IDLE_ON: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_MACHINE, + COREFREQ_TOGGLE_ON, + MACHINE_CPU_IDLE ); + } + break; + + case OPS_CPU_FREQ_OFF: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_MACHINE, + COREFREQ_TOGGLE_OFF, + MACHINE_CPU_FREQ ); + } + break; + + case OPS_CPU_FREQ_ON: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_MACHINE, + COREFREQ_TOGGLE_ON, + MACHINE_CPU_FREQ ); + } + break; + + case OPS_GOVERNOR_OFF: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_MACHINE, + COREFREQ_TOGGLE_OFF, + MACHINE_GOVERNOR ); + } + break; + + case OPS_GOVERNOR_ON: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_MACHINE, + COREFREQ_TOGGLE_ON, + MACHINE_GOVERNOR ); + } + break; + + case OPS_CLOCK_SOURCE_OFF: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_MACHINE, + COREFREQ_TOGGLE_OFF, + MACHINE_CLOCK_SOURCE ); + } + break; + + case OPS_CLOCK_SOURCE_ON: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_MACHINE, + COREFREQ_TOGGLE_ON, + MACHINE_CLOCK_SOURCE ); + } + break; + + case OPS_THERMAL_SCOPE: + case OPS_VOLTAGE_SCOPE: + case OPS_POWER_SCOPE: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + const ASCII *title[] = { + RSC(BOX_SCOPE_THERMAL_TITLE).CODE(), + RSC(BOX_SCOPE_VOLTAGE_TITLE).CODE(), + RSC(BOX_SCOPE_POWER_TITLE).CODE() + }; + const union { + int *pInteger; + enum THERMAL_FORMULAS *pThermal; + enum VOLTAGE_FORMULAS *pVoltage; + enum POWER_FORMULAS *pPower; + } formula[] = { + { .pThermal = &RO(Shm)->Proc.thermalFormula }, + { .pVoltage = &RO(Shm)->Proc.voltageFormula }, + { .pPower = &RO(Shm)->Proc.powerFormula } + }; + const int index = (scan->key & 0x000000000000f000) >> 12; + const Coordinate origin = { + .col = 43, + .row = TOP_HEADER_ROW + 20 + }, select = { + .col = 0, + .row = SCOPE_OF_FORMULA((*formula[index].pInteger)) + }; + AppendWindow( + CreateBox(scan->key, origin, select, + (char*) title[index], + RSC(BOX_SCOPE_NONE).CODE(), stateAttr[0], + (scan->key & 0x100000000002f000) | (7 ^ FORMULA_SCOPE_NONE), + RSC(BOX_SCOPE_THREAD).CODE(), stateAttr[0], + (scan->key & 0x100000000002f000) | (7 ^ FORMULA_SCOPE_SMT), + RSC(BOX_SCOPE_CORE).CODE(), stateAttr[0], + (scan->key & 0x100000000002f000) | (7 ^ FORMULA_SCOPE_CORE), + RSC(BOX_SCOPE_PACKAGE).CODE(), stateAttr[0], + (scan->key & 0x100000000002f000) | (7 ^ FORMULA_SCOPE_PKG)), + &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case OPS_THERMAL_SCOPE_NONE: + case OPS_THERMAL_SCOPE_SMT: + case OPS_THERMAL_SCOPE_CORE: + case OPS_THERMAL_SCOPE_PKG: + case OPS_VOLTAGE_SCOPE_NONE: + case OPS_VOLTAGE_SCOPE_SMT: + case OPS_VOLTAGE_SCOPE_CORE: + case OPS_VOLTAGE_SCOPE_PKG: + case OPS_POWER_SCOPE_NONE: + case OPS_POWER_SCOPE_SMT: + case OPS_POWER_SCOPE_CORE: + case OPS_POWER_SCOPE_PKG: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_MACHINE, + (scan->key & 0x000000000000f000) >> 12, + MACHINE_FORMULA_SCOPE, + (scan->key & 0x000000000000000f) ^ 7 ); + } + break; + + case SCANKEY_HASH: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) { + AppendWindow(CreateHotPlugCPU(scan->key), &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case SCANKEY_PERCENT: + if ((Draw.View == V_FREQ) && (Draw.Disposal == D_MAINVIEW)) { + Draw.Flag.avgOrPC = !Draw.Flag.avgOrPC; + Draw.Flag.clear = 1; + } + break; + + case SCANKEY_DOT: + if (Draw.Disposal == D_MAINVIEW) { + Draw.Flag.clkOrLd = !Draw.Flag.clkOrLd; + Draw.Flag.clear = 1; + } + break; + + case 0x000000000000007e: + { + Draw.Disposal = D_ASCIITEST; + Draw.Size.height = 0; + TrapScreenSize(SIGWINCH); + } + break; + + case SCANKEY_a: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) { + AppendWindow(CreateAbout(scan->key), &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case SCANKEY_b: + if ((Draw.View == V_TASKS) && (Draw.Disposal == D_MAINVIEW)) { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) { + AppendWindow(CreateSortByField(scan->key), &winList); + } else { + SetHead(&winList, win); + } + } + break; +#ifndef NO_LOWER + case SCANKEY_c: + { + Draw.Disposal = D_MAINVIEW; + Draw.View = V_CYCLES; + Draw.Size.height = 0; + TrapScreenSize(SIGWINCH); + } + break; +#endif + case SCANKEY_d: + { + Draw.Disposal = D_DASHBOARD; + Draw.Size.height = 0; + TrapScreenSize(SIGWINCH); + } + break; + + case SCANKEY_f: + { + Draw.Disposal = D_MAINVIEW; + Draw.View = V_FREQ; + Draw.Size.height = 0; + TrapScreenSize(SIGWINCH); + } + break; + + case SCANKEY_SHIFT_n: + if ((Draw.View == V_TASKS) && (Draw.Disposal == D_MAINVIEW)) { + RING_WRITE_SUB_CMD( TASK_TRACKING, + RW(Shm)->Ring[1], + COREFREQ_TASK_MONITORING, + (pid_t) 0 ); + } + break; + + case SCANKEY_n: + if ((Draw.View == V_TASKS) && (Draw.Disposal == D_MAINVIEW)) { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) { + AppendWindow(CreateTracking(scan->key), &winList); + } else { + SetHead(&winList, win); + } + } + break; +#ifndef NO_LOWER + case SCANKEY_g: + { + Draw.Disposal = D_MAINVIEW; + Draw.View = V_PACKAGE; + Draw.Size.height = 0; + TrapScreenSize(SIGWINCH); + } + break; +#endif + case SCANKEY_F1: + case SCANCON_F1: + case SCANSYM_F1: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) { + AppendWindow(CreateAdvHelp(scan->key), &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case SCANKEY_h: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) { + AppendWindow(CreateHelp(scan->key), &winList); + } else { + SetHead(&winList, win); + } + } + break; +#ifndef NO_LOWER + case SCANKEY_i: + { + Draw.Disposal = D_MAINVIEW; + Draw.View = V_INST; + Draw.Size.height = 0; + TrapScreenSize(SIGWINCH); + } + break; + + case SCANKEY_l: + { + Draw.Disposal = D_MAINVIEW; + Draw.View = V_CSTATES; + Draw.Size.height = 0; + TrapScreenSize(SIGWINCH); + } + break; +#endif /* NO_LOWER */ + case SCANKEY_m: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) { + AppendWindow(CreateTopology(scan->key), &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case SCANKEY_DOLLAR: + Setting.jouleWatt = !Setting.jouleWatt; + if (Draw.Disposal == D_MAINVIEW) { + Draw.Flag.layout = 1; + } + break; + + case SCANKEY_SHIFT_f: + Setting.fahrCels = !Setting.fahrCels; + Draw.Flag.layout = 1; + break; + + case SCANKEY_SHIFT_y: + Setting.secret = !Setting.secret; + Draw.Flag.layout = 1; + break; + + case SCANKEY_SHIFT_g: + if (!RING_FULL(RW(Shm)->Ring[1])) { + RING_WRITE(RW(Shm)->Ring[1], + COREFREQ_TOGGLE_SYSGATE, + !BITWISEAND(LOCKLESS, RO(Shm)->SysGate.Operation, 0x1)); + } + break; + + case SCANKEY_SHIFT_h: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) { + AppendWindow(CreateEvents(scan->key), &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case SCANKEY_SHIFT_i: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) { + AppendWindow(CreateISA(scan->key), &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case SCANKEY_SHIFT_l: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + const Coordinate origin = { + .col = 30, + .row = TOP_HEADER_ROW + 6 + }, select = { + .col = 0, + .row = 1 + ((GET_LOCALE() >= LOC_EN) + && (GET_LOCALE() < LOC_CNT) ? + GET_LOCALE() : LOC_EN) + }; + + Window *wBox = CreateBox(scan->key, origin, select, + (char*) RSC(BOX_LANG_TITLE).CODE(), + RSC(BOX_LANG_BLANK).CODE(), blankAttr , SCANKEY_NULL, + RSC(BOX_LANG_ENGLISH).CODE(),stateAttr[0], BOXKEY_LANG_ENGLISH, + RSC(BOX_LANG_FRENCH).CODE(), stateAttr[0], BOXKEY_LANG_FRENCH, + RSC(BOX_LANG_BLANK).CODE(), blankAttr , SCANKEY_NULL); + + if (wBox != NULL) { + AppendWindow(wBox, &winList); + } else { + SetHead(&winList, win); + } + } else { + SetHead(&winList, win); + } + } + break; + + case BOXKEY_LANG_ENGLISH: + { + if (GET_LOCALE() != LOC_EN) { + SET_LOCALE(LOC_EN); + Draw.Flag.layout = 1; + } + } + break; + + case BOXKEY_LANG_FRENCH: + { + if (GET_LOCALE() != LOC_FR) { + SET_LOCALE(LOC_FR); + Draw.Flag.layout = 1; + } + } + break; + + case SCANKEY_SHIFT_e: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + const Coordinate origin = { + .col = (Draw.Size.width - RSZ(BOX_THEME_BLANK)) / 2, + .row = TOP_HEADER_ROW + 11 + }, select = { + .col = 0, + .row = 1 + GET_THEME() + }; + + Window *wBox = CreateBox(scan->key, origin, select, + (char*) RSC(BOX_THEME_TITLE).CODE(), + RSC(BOX_THEME_BLANK).CODE(), blankAttr, SCANKEY_NULL, + RSC(THEME_DFLT).CODE() , stateAttr[0], BOXKEY_THEME_DFLT, + RSC(THEME_USR1).CODE() , stateAttr[0], BOXKEY_THEME_USR1, + RSC(THEME_USR2).CODE() , stateAttr[0], BOXKEY_THEME_USR2, + RSC(BOX_THEME_BLANK).CODE(), blankAttr, SCANKEY_NULL); + + if (wBox != NULL) { + AppendWindow(wBox, &winList); + } else { + SetHead(&winList, win); + } + } else { + SetHead(&winList, win); + } + } + break; + + case BOXKEY_THEME_DFLT: + SET_THEME(THM_DFLT); + Draw.Flag.clear = 1; + break; + + case BOXKEY_THEME_USR1: + SET_THEME(THM_USR1); + Draw.Flag.clear = 1; + break; + + case BOXKEY_THEME_USR2: + SET_THEME(THM_USR2); + Draw.Flag.clear = 1; + break; + + case SCANKEY_SHIFT_m: + if (RO(Shm)->Uncore.CtrlCount > 0) { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) { + AppendWindow(CreateMemCtrl(scan->key),&winList); + } else { + SetHead(&winList, win); + } + } + break; + + case SCANKEY_SHIFT_r: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) { + AppendWindow(CreateSysRegs(scan->key), &winList); + } else { + SetHead(&winList, win); + } + } + break; +#ifndef NO_LOWER + case SCANKEY_q: + { + Draw.Disposal = D_MAINVIEW; + Draw.View = V_INTR; + Draw.Size.height = 0; + TrapScreenSize(SIGWINCH); + } + break; + + case SCANKEY_SHIFT_c: + { + Draw.Disposal = D_MAINVIEW; + Draw.View = V_SENSORS; + Draw.Size.height = 0; + TrapScreenSize(SIGWINCH); + } + break; + + case SCANKEY_SHIFT_v: + { + Draw.Disposal = D_MAINVIEW; + Draw.View = V_VOLTAGE; + Draw.Size.height = 0; + TrapScreenSize(SIGWINCH); + } + break; + + case SCANKEY_SHIFT_w: + { + Draw.Disposal = D_MAINVIEW; + Draw.View = V_ENERGY; + Draw.Size.height = 0; + TrapScreenSize(SIGWINCH); + } + break; + + case SCANKEY_SHIFT_t: + { + Draw.Disposal = D_MAINVIEW; + Draw.View = V_SLICE; + Draw.Size.height = 0; + TrapScreenSize(SIGWINCH); + } + break; + + case SCANKEY_y: + { + Draw.Disposal = D_MAINVIEW; + Draw.View = V_CUSTOM; + Draw.Size.height = 0; + TrapScreenSize(SIGWINCH); + } + break; +#endif /* NO_LOWER */ + case SCANKEY_s: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) { + AppendWindow(CreateSettings(scan->key), &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case SCANKEY_r: + if ((Draw.View == V_TASKS) && (Draw.Disposal == D_MAINVIEW)) { + RING_WRITE_SUB_CMD( TASK_INVERSING, + RW(Shm)->Ring[1], + COREFREQ_TASK_MONITORING ); + } + break; + + case SCANKEY_v: + if ((Draw.View == V_TASKS) && (Draw.Disposal == D_MAINVIEW)) { + Draw.Flag.taskVal = !Draw.Flag.taskVal; + Draw.Flag.layout = 1; + } + break; +#ifndef NO_LOWER + case SCANKEY_x: + if (BITWISEAND(LOCKLESS, RO(Shm)->SysGate.Operation, 0x1)) { + Draw.Disposal = D_MAINVIEW; + Draw.View = V_TASKS; + Draw.Size.height = 0; + TrapScreenSize(SIGWINCH); + } + break; +#endif + case SCANKEY_EXCL: + if (Draw.Disposal == D_MAINVIEW) { + Draw.Load = !Draw.Load; + Draw.Flag.layout = 1; + } + break; + + case SORTBY_STATE: + { + RING_WRITE_SUB_CMD( TASK_SORTING, + RW(Shm)->Ring[1], + COREFREQ_TASK_MONITORING, + F_STATE ); + } + break; + + case SORTBY_RTIME: + { + RING_WRITE_SUB_CMD( TASK_SORTING, + RW(Shm)->Ring[1], + COREFREQ_TASK_MONITORING, + F_RTIME ); + } + break; + + case SORTBY_UTIME: + { + RING_WRITE_SUB_CMD( TASK_SORTING, + RW(Shm)->Ring[1], + COREFREQ_TASK_MONITORING, + F_UTIME ); + } + break; + + case SORTBY_STIME: + { + RING_WRITE_SUB_CMD( TASK_SORTING, + RW(Shm)->Ring[1], + COREFREQ_TASK_MONITORING, + F_STIME ); + } + break; + + case SORTBY_PID: + { + RING_WRITE_SUB_CMD( TASK_SORTING, + RW(Shm)->Ring[1], + COREFREQ_TASK_MONITORING, + F_PID ); + } + break; + + case SORTBY_COMM: + { + RING_WRITE_SUB_CMD( TASK_SORTING, + RW(Shm)->Ring[1], + COREFREQ_TASK_MONITORING, + F_COMM ); + } + break; + + case BOXKEY_HWP_EPP: + { + CPU_STRUCT *SProc = &RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core]; + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + const Coordinate origin = { + .col = (Draw.Size.width - (2 + RSZ(BOX_POWER_POLICY_LOW))) / 2, + .row = TOP_HEADER_ROW + 3 + }, select = { + .col = 0, + .row = SProc->PowerThermal.HWP.Request.Energy_Pref == 0xff ? + 8 : SProc->PowerThermal.HWP.Request.Energy_Pref >= 0xe0 ? + 7 : SProc->PowerThermal.HWP.Request.Energy_Pref >= 0xc0 ? + 6 : SProc->PowerThermal.HWP.Request.Energy_Pref >= 0xa0 ? + 5 : SProc->PowerThermal.HWP.Request.Energy_Pref >= 0x80 ? + 4 : SProc->PowerThermal.HWP.Request.Energy_Pref >= 0x60 ? + 3 : SProc->PowerThermal.HWP.Request.Energy_Pref >= 0x40 ? + 2 : SProc->PowerThermal.HWP.Request.Energy_Pref >= 0x20 ? + 1 : 0 + }; + Window *wBox = CreateBox(scan->key, origin, select, + (char*) RSC(BOX_POWER_POLICY_TITLE).CODE(), + /*00*/RSC(BOX_HWP_POLICY_MIN).CODE(), stateAttr[0], BOXKEY_HWP_EPP_MIN, + /*20*/RSC(BOX_HWP_POLICY_020).CODE(), stateAttr[0], BOXKEY_HWP_EPP_020, + /*40*/RSC(BOX_HWP_POLICY_040).CODE(), stateAttr[0], BOXKEY_HWP_EPP_040, + /*60*/RSC(BOX_HWP_POLICY_060).CODE(), stateAttr[0], BOXKEY_HWP_EPP_060, + /*80*/RSC(BOX_HWP_POLICY_MED).CODE(), stateAttr[0], BOXKEY_HWP_EPP_MED, + /*A0*/RSC(BOX_HWP_POLICY_0A0).CODE(), stateAttr[0], BOXKEY_HWP_EPP_0A0, + /*C0*/RSC(BOX_HWP_POLICY_PWR).CODE(), stateAttr[0], BOXKEY_HWP_EPP_PWR, + /*E0*/RSC(BOX_HWP_POLICY_0E0).CODE(), stateAttr[0], BOXKEY_HWP_EPP_0E0, + /*FF*/RSC(BOX_HWP_POLICY_MAX).CODE(), stateAttr[0], BOXKEY_HWP_EPP_MAX); + + if (wBox != NULL) { + TCellAt(wBox, 0, select.row).attr[ 3] = \ + TCellAt(wBox, 0, select.row).attr[ 4] = \ + TCellAt(wBox, 0, select.row).attr[ 5] = \ + TCellAt(wBox, 0, select.row).attr[ 6] = \ + TCellAt(wBox, 0, select.row).attr[ 7] = \ + TCellAt(wBox, 0, select.row).attr[ 8] = \ + TCellAt(wBox, 0, select.row).attr[ 9] = \ + TCellAt(wBox, 0, select.row).attr[10] = \ + TCellAt(wBox, 0, select.row).attr[11] = \ + TCellAt(wBox, 0, select.row).attr[12] = \ + TCellAt(wBox, 0, select.row).attr[13] = \ + TCellAt(wBox, 0, select.row).attr[14] = \ + TCellAt(wBox, 0, select.row).attr[15] = \ + TCellAt(wBox, 0, select.row).attr[16] = \ + TCellAt(wBox, 0, select.row).attr[17] = \ + TCellAt(wBox, 0, select.row).attr[18] = \ + TCellAt(wBox, 0, select.row).attr[19] = \ + TCellAt(wBox, 0, select.row).attr[20] = \ + TCellAt(wBox, 0, select.row).attr[21] = stateAttr[1]; + TCellAt(wBox, 0, select.row).item[ 3] = '<'; + TCellAt(wBox, 0, select.row).item[21] = '>'; + + AppendWindow(wBox, &winList); + } else { + SetHead(&winList, win); + } + } else { + SetHead(&winList, win); + } + } + break; + + case BOXKEY_HWP_EPP_MIN: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_TECHNOLOGY, + 0x0, + TECHNOLOGY_HWP_EPP ); + } + break; + + case BOXKEY_HWP_EPP_020: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_TECHNOLOGY, + 0x20, + TECHNOLOGY_HWP_EPP ); + } + break; + + case BOXKEY_HWP_EPP_040: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_TECHNOLOGY, + 0x40, + TECHNOLOGY_HWP_EPP ); + } + break; + + case BOXKEY_HWP_EPP_060: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_TECHNOLOGY, + 0x60, + TECHNOLOGY_HWP_EPP ); + } + break; + + case BOXKEY_HWP_EPP_MED: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_TECHNOLOGY, + 0x80, + TECHNOLOGY_HWP_EPP ); + } + break; + + case BOXKEY_HWP_EPP_0A0: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_TECHNOLOGY, + 0xa0, + TECHNOLOGY_HWP_EPP ); + } + break; + + case BOXKEY_HWP_EPP_PWR: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_TECHNOLOGY, + 0xc0, + TECHNOLOGY_HWP_EPP ); + } + break; + + case BOXKEY_HWP_EPP_0E0: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_TECHNOLOGY, + 0xe0, + TECHNOLOGY_HWP_EPP ); + } + break; + + case BOXKEY_HWP_EPP_MAX: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_TECHNOLOGY, + 0xff, + TECHNOLOGY_HWP_EPP ); + } + break; + + case BOXKEY_HWP: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + const Coordinate origin = { + .col = (Draw.Size.width - RSZ(BOX_BLANK_DESC)) / 2, + .row = TOP_HEADER_ROW + 11 + }, select = { + .col = 0, + .row = 3 + }; + AppendWindow( + CreateBox(scan->key, origin, select, + (char*) RSC(BOX_HWP_TITLE).CODE(), + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL, + RSC(BOX_HWP_DESC).CODE() , descAttr, SCANKEY_NULL, + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL, + stateStr[1][RO(Shm)->Proc.Features.HWP_Enable], + stateAttr[RO(Shm)->Proc.Features.HWP_Enable], + BOXKEY_HWP_ON, + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL), + &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case BOXKEY_HWP_ON: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_TECHNOLOGY, + COREFREQ_TOGGLE_ON, + TECHNOLOGY_HWP ); + } + break; + + case BOXKEY_FMW_CPPC: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + const Coordinate origin = { + .col = (Draw.Size.width - RSZ(BOX_BLANK_DESC)) / 2, + .row = TOP_HEADER_ROW + 14 + }, select = { + .col = 0, + .row = 2 + }; + AppendWindow( + CreateBox(scan->key, origin, select, + (char*) RSC(BOX_CPPC_TITLE).CODE(), + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL, + RSC(BOX_FMW_DESC).CODE() , descAttr, SCANKEY_NULL, + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL, + stateStr[1][0], stateAttr[0], BOXKEY_HWP_ON, + stateStr[0][0], stateAttr[0], BOXKEY_FMW_CPPC_OFF, + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL), + &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case BOXKEY_FMW_CPPC_OFF: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_TECHNOLOGY, + COREFREQ_TOGGLE_OFF, + TECHNOLOGY_HWP ); + } + break; + + case (BOXKEY_TDP_PKG | PL1): + case (BOXKEY_TDP_CORES | PL1): + case (BOXKEY_TDP_UNCORE | PL1): + case (BOXKEY_TDP_RAM | PL1): + case (BOXKEY_TDP_PLATFORM | PL1): + fallthrough; + case (BOXKEY_TDP_PKG | PL2): + case (BOXKEY_TDP_CORES | PL2): + case (BOXKEY_TDP_UNCORE | PL2): + case (BOXKEY_TDP_RAM | PL2): + case (BOXKEY_TDP_PLATFORM | PL2): + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + const enum PWR_DOMAIN pw = (scan->key >> 5) & BOXKEY_TDP_MASK; + const enum PWR_LIMIT pl = scan->key & (PL1 | PL2); + const unsigned long long key[14] = { + (BOXKEY_PLX_OP | (0x8ULL << pl)) | (pw << 5) | (+50U << 20), + (BOXKEY_PLX_OP | (0x8ULL << pl)) | (pw << 5) | (+10U << 20), + (BOXKEY_PLX_OP | (0x8ULL << pl)) | (pw << 5) | (+05U << 20), + (BOXKEY_PLX_OP | (0x8ULL << pl)) | (pw << 5) | (+04U << 20), + (BOXKEY_PLX_OP | (0x8ULL << pl)) | (pw << 5) | (+03U << 20), + (BOXKEY_PLX_OP | (0x8ULL << pl)) | (pw << 5) | (+02U << 20), + (BOXKEY_PLX_OP | (0x8ULL << pl)) | (pw << 5) | (+01U << 20), + (BOXKEY_PLX_OP | (0x8ULL << pl)) | (pw << 5) | (-01U << 20), + (BOXKEY_PLX_OP | (0x8ULL << pl)) | (pw << 5) | (-02U << 20), + (BOXKEY_PLX_OP | (0x8ULL << pl)) | (pw << 5) | (-03U << 20), + (BOXKEY_PLX_OP | (0x8ULL << pl)) | (pw << 5) | (-04U << 20), + (BOXKEY_PLX_OP | (0x8ULL << pl)) | (pw << 5) | (-05U << 20), + (BOXKEY_PLX_OP | (0x8ULL << pl)) | (pw << 5) | (-10U << 20), + (BOXKEY_PLX_OP | (0x8ULL << pl)) | (pw << 5) | (-50U << 20) + }; + const ASCII *title[] = { + RSC(BOX_TDP_PKG_TITLE).CODE(), + RSC(BOX_TDP_CORES_TITLE).CODE(), + RSC(BOX_TDP_UNCORE_TITLE).CODE(), + RSC(BOX_TDP_RAM_TITLE).CODE(), + RSC(BOX_TDP_PLATFORM_TITLE).CODE() + }; + const ASCII *descItem[PWR_LIMIT_SIZE] = { + RSC(BOX_PL1_DESC).CODE(), + RSC(BOX_PL2_DESC).CODE() + }; + const ASCII *clampItem[2][2] = { + { + RSC(BOX_CLAMPING_OFF_COND0).CODE(), + RSC(BOX_CLAMPING_OFF_COND1).CODE() + }, + { + RSC(BOX_CLAMPING_ON_COND0).CODE(), + RSC(BOX_CLAMPING_ON_COND1).CODE() + } + }; + const Coordinate origin = { + .col = (Draw.Size.width - RSZ(BOX_BLANK_DESC)) / 2, + .row = TOP_HEADER_ROW + 1 + }, select = { + .col = 0, + .row = RO(Shm)->Proc.Power.Domain[pw].Feature[pl].Enable ? 12:11 + }; + AppendWindow( + CreateBox(scan->key, origin, select, (char*) title[pw], + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL, + descItem[pl], descAttr , SCANKEY_NULL, + + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL, + RSC(BOX_PWR_OFFSET_00).CODE(), stateAttr[0], key[ 0], + RSC(BOX_PWR_OFFSET_01).CODE(), stateAttr[0], key[ 1], + RSC(BOX_PWR_OFFSET_02).CODE(), stateAttr[0], key[ 2], + RSC(BOX_PWR_OFFSET_03).CODE(), stateAttr[0], key[ 3], + RSC(BOX_PWR_OFFSET_04).CODE(), stateAttr[0], key[ 4], + RSC(BOX_PWR_OFFSET_05).CODE(), stateAttr[0], key[ 5], + RSC(BOX_PWR_OFFSET_06).CODE(), stateAttr[0], key[ 6], + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL, + + stateStr[1][RO(Shm)->Proc.Power.Domain[pw].Feature[pl].Enable], + stateAttr[RO(Shm)->Proc.Power.Domain[pw].Feature[pl].Enable], + (BOXKEY_PLX_OP | (0x8U << pl)) | ( pw << 5) | 1, + + stateStr[0][!RO(Shm)->Proc.Power.Domain[pw].Feature[pl].Enable], + stateAttr[!RO(Shm)->Proc.Power.Domain[pw].Feature[pl].Enable], + (BOXKEY_PLX_OP | (0x8U << pl)) | ( pw << 5) | 2, + + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL, + RSC(BOX_PWR_OFFSET_07).CODE(), stateAttr[0], key[ 7], + RSC(BOX_PWR_OFFSET_08).CODE(), stateAttr[0], key[ 8], + RSC(BOX_PWR_OFFSET_09).CODE(), stateAttr[0], key[ 9], + RSC(BOX_PWR_OFFSET_10).CODE(), stateAttr[0], key[10], + RSC(BOX_PWR_OFFSET_11).CODE(), stateAttr[0], key[11], + RSC(BOX_PWR_OFFSET_12).CODE(), stateAttr[0], key[12], + RSC(BOX_PWR_OFFSET_13).CODE(), stateAttr[0], key[13], + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL, + + clampItem[1][RO(Shm)->Proc.Power.Domain[pw].Feature[pl].Clamping], + stateAttr[RO(Shm)->Proc.Power.Domain[pw].Feature[pl].Clamping], + (BOXKEY_PLX_OP | (0x8U << pl)) | (pw << 5) | 5, + + clampItem[0][!RO(Shm)->Proc.Power.Domain[pw].Feature[pl].Clamping], + stateAttr[!RO(Shm)->Proc.Power.Domain[pw].Feature[pl].Clamping], + (BOXKEY_PLX_OP | (0x8U << pl)) | (pw << 5) | 6, + + RSC(BOX_BLANK_DESC).CODE(), blankAttr,SCANKEY_NULL), + &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case BOXKEY_TW1_PKG: + case BOXKEY_TW1_CORES: + case BOXKEY_TW1_UNCORE: + case BOXKEY_TW1_RAM: + case BOXKEY_TW1_PLATFORM: + fallthrough; + case BOXKEY_TW2_PKG: + case BOXKEY_TW2_CORES: + case BOXKEY_TW2_UNCORE: + case BOXKEY_TW2_RAM: + case BOXKEY_TW2_PLATFORM: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) { + AppendWindow(CreatePowerTimeWindow(scan->key), &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case BOXKEY_TDC: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + const Coordinate origin = { + .col = (Draw.Size.width - RSZ(BOX_BLANK_DESC)) / 2, + .row = TOP_HEADER_ROW + 2 + }, select = { + .col = 0, + .row = RO(Shm)->Proc.Power.Feature.TDC ? 12 : 11 + }; + const unsigned long long key[14] = { + BOXKEY_TDC_MASK | (+50U << 20), + BOXKEY_TDC_MASK | (+10U << 20), + BOXKEY_TDC_MASK | (+05U << 20), + BOXKEY_TDC_MASK | (+04U << 20), + BOXKEY_TDC_MASK | (+03U << 20), + BOXKEY_TDC_MASK | (+02U << 20), + BOXKEY_TDC_MASK | (+01U << 20), + BOXKEY_TDC_MASK | (-01U << 20), + BOXKEY_TDC_MASK | (-02U << 20), + BOXKEY_TDC_MASK | (-03U << 20), + BOXKEY_TDC_MASK | (-04U << 20), + BOXKEY_TDC_MASK | (-05U << 20), + BOXKEY_TDC_MASK | (-10U << 20), + BOXKEY_TDC_MASK | (-50U << 20) + }; + AppendWindow( + CreateBox(scan->key, origin, select, + (char*) RSC(BOX_TDC_TITLE).CODE(), + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL, + RSC(BOX_TDC_DESC).CODE(), descAttr , SCANKEY_NULL, + + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL, + RSC(BOX_AMP_OFFSET_00).CODE(), stateAttr[0], key[ 0], + RSC(BOX_AMP_OFFSET_01).CODE(), stateAttr[0], key[ 1], + RSC(BOX_AMP_OFFSET_02).CODE(), stateAttr[0], key[ 2], + RSC(BOX_AMP_OFFSET_03).CODE(), stateAttr[0], key[ 3], + RSC(BOX_AMP_OFFSET_04).CODE(), stateAttr[0], key[ 4], + RSC(BOX_AMP_OFFSET_05).CODE(), stateAttr[0], key[ 5], + RSC(BOX_AMP_OFFSET_06).CODE(), stateAttr[0], key[ 6], + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL, + + stateStr[1][RO(Shm)->Proc.Power.Feature.TDC], + stateAttr[RO(Shm)->Proc.Power.Feature.TDC], + BOXKEY_TDC_OR | 1, + + stateStr[0][!RO(Shm)->Proc.Power.Feature.TDC], + stateAttr[!RO(Shm)->Proc.Power.Feature.TDC], + BOXKEY_TDC_OR | 2, + + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL, + RSC(BOX_AMP_OFFSET_07).CODE(), stateAttr[0], key[ 7], + RSC(BOX_AMP_OFFSET_08).CODE(), stateAttr[0], key[ 8], + RSC(BOX_AMP_OFFSET_09).CODE(), stateAttr[0], key[ 9], + RSC(BOX_AMP_OFFSET_10).CODE(), stateAttr[0], key[10], + RSC(BOX_AMP_OFFSET_11).CODE(), stateAttr[0], key[11], + RSC(BOX_AMP_OFFSET_12).CODE(), stateAttr[0], key[12], + RSC(BOX_AMP_OFFSET_13).CODE(), stateAttr[0], key[13], + RSC(BOX_BLANK_DESC).CODE(), blankAttr,SCANKEY_NULL), + &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case BOXKEY_THM: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) { + AppendWindow(CreateThermalOffsetWindow(scan->key), &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case BOXKEY_LIMIT_IDLE_STATE: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) { + AppendWindow(CreateSelectIdle(scan->key), &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case BOXKEY_LIMIT_IDLE_ST00: + case BOXKEY_LIMIT_IDLE_ST01: + case BOXKEY_LIMIT_IDLE_ST02: + case BOXKEY_LIMIT_IDLE_ST03: + case BOXKEY_LIMIT_IDLE_ST04: + case BOXKEY_LIMIT_IDLE_ST05: + case BOXKEY_LIMIT_IDLE_ST06: + case BOXKEY_LIMIT_IDLE_ST07: + case BOXKEY_LIMIT_IDLE_ST08: + case BOXKEY_LIMIT_IDLE_ST09: + case BOXKEY_LIMIT_IDLE_ST10: + { + const unsigned long newLim = (scan->key - BOXKEY_LIMIT_IDLE_ST00) >> 4; + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_MACHINE, + newLim, + MACHINE_LIMIT_IDLE ); + } + } + break; + + case BOXKEY_CLR_ALL_EVENTS: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_CLEAR_EVENTS, + EVENT_ALL_OF_THEM ); + } + break; + + case BOXKEY_CLR_THM_SENSOR: + case BOXKEY_CLR_PROCHOT_LOG: + case BOXKEY_CLR_THM_CRIT: + case BOXKEY_CLR_THM_THOLD1: + case BOXKEY_CLR_THM_THOLD2: + case BOXKEY_CLR_PWR_LIMIT: + case BOXKEY_CLR_CUR_LIMIT: + case BOXKEY_CLR_X_DOMAIN: + case BOXKEY_CLR_CORE_HOT: + case BOXKEY_CLR_CORE_THM: + case BOXKEY_CLR_CORE_RES: + case BOXKEY_CLR_CORE_AVG: + case BOXKEY_CLR_CORE_VRT: + case BOXKEY_CLR_CORE_TDC: + case BOXKEY_CLR_CORE_PL1: + case BOXKEY_CLR_CORE_PL2: + case BOXKEY_CLR_CORE_EDP: + case BOXKEY_CLR_CORE_BST: + case BOXKEY_CLR_CORE_ATT: + case BOXKEY_CLR_CORE_TVB: + case BOXKEY_CLR_GFX_HOT: + case BOXKEY_CLR_GFX_THM: + case BOXKEY_CLR_GFX_AVG: + case BOXKEY_CLR_GFX_VRT: + case BOXKEY_CLR_GFX_TDC: + case BOXKEY_CLR_GFX_PL1: + case BOXKEY_CLR_GFX_PL2: + case BOXKEY_CLR_GFX_EDP: + case BOXKEY_CLR_GFX_EFF: + case BOXKEY_CLR_RING_HOT: + case BOXKEY_CLR_RING_THM: + case BOXKEY_CLR_RING_AVG: + case BOXKEY_CLR_RING_VRT: + case BOXKEY_CLR_RING_TDC: + case BOXKEY_CLR_RING_PL1: + case BOXKEY_CLR_RING_PL2: + case BOXKEY_CLR_RING_EDP: + { + const enum EVENT_LOG lshift = (scan->key & CLEAR_EVENT_MASK) >> 1; + const enum THERM_PWR_EVENTS event = 0x1LLU << lshift; + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE(RW(Shm)->Ring[0], COREFREQ_IOCTL_CLEAR_EVENTS, event); + } + } + break; + + case BOXKEY_TURBO_CLOCK_1C: + case BOXKEY_TURBO_CLOCK_2C: + case BOXKEY_TURBO_CLOCK_3C: + case BOXKEY_TURBO_CLOCK_4C: + case BOXKEY_TURBO_CLOCK_5C: + case BOXKEY_TURBO_CLOCK_6C: + case BOXKEY_TURBO_CLOCK_7C: + case BOXKEY_TURBO_CLOCK_8C: + case BOXKEY_TURBO_CLOCK_9C: + case BOXKEY_TURBO_CLOCK_10C: + case BOXKEY_TURBO_CLOCK_11C: + case BOXKEY_TURBO_CLOCK_12C: + case BOXKEY_TURBO_CLOCK_13C: + case BOXKEY_TURBO_CLOCK_14C: + case BOXKEY_TURBO_CLOCK_15C: + case BOXKEY_TURBO_CLOCK_16C: + case BOXKEY_TURBO_CLOCK_17C: + case BOXKEY_TURBO_CLOCK_18C: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + unsigned long long id = scan->key | BOXKEY_RATIO_SELECT_OR, + i18C = (((id >> 32) & RATIO_MASK) % 18) - 1; + + PKG_ITEM_CALLBACK Pkg_Item_Turbo_Freq[18] = { + Pkg_Item_Turbo_1C, + Pkg_Item_Turbo_2C, + Pkg_Item_Turbo_3C, + Pkg_Item_Turbo_4C, + Pkg_Item_Turbo_5C, + Pkg_Item_Turbo_6C, + Pkg_Item_Turbo_7C, + Pkg_Item_Turbo_8C, + Pkg_Item_Turbo_9C, + Pkg_Item_Turbo_10C, + Pkg_Item_Turbo_11C, + Pkg_Item_Turbo_12C, + Pkg_Item_Turbo_13C, + Pkg_Item_Turbo_14C, + Pkg_Item_Turbo_15C, + Pkg_Item_Turbo_16C, + Pkg_Item_Turbo_17C, + Pkg_Item_Turbo_18C + }; + CPU_ITEM_CALLBACK CPU_Item_Turbo_Freq[18] = { + CPU_Item_Turbo_1C, + CPU_Item_Turbo_2C, + CPU_Item_Turbo_3C, + CPU_Item_Turbo_4C, + CPU_Item_Turbo_5C, + CPU_Item_Turbo_6C, + CPU_Item_Turbo_7C, + CPU_Item_Turbo_8C, + CPU_Item_Turbo_9C, + CPU_Item_Turbo_10C, + CPU_Item_Turbo_11C, + CPU_Item_Turbo_12C, + CPU_Item_Turbo_13C, + CPU_Item_Turbo_14C, + CPU_Item_Turbo_15C, + CPU_Item_Turbo_16C, + CPU_Item_Turbo_17C, + CPU_Item_Turbo_18C + }; + UPDATE_CALLBACK Pkg_Turbo_Freq_Update[18] = { + Pkg_Update_Turbo_1C, + Pkg_Update_Turbo_2C, + Pkg_Update_Turbo_3C, + Pkg_Update_Turbo_4C, + Pkg_Update_Turbo_5C, + Pkg_Update_Turbo_6C, + Pkg_Update_Turbo_7C, + Pkg_Update_Turbo_8C, + Pkg_Update_Turbo_9C, + Pkg_Update_Turbo_10C, + Pkg_Update_Turbo_11C, + Pkg_Update_Turbo_12C, + Pkg_Update_Turbo_13C, + Pkg_Update_Turbo_14C, + Pkg_Update_Turbo_15C, + Pkg_Update_Turbo_16C, + Pkg_Update_Turbo_17C, + Pkg_Update_Turbo_18C + }; + UPDATE_CALLBACK CPU_Turbo_Freq_Update[18] = { + CPU_Update_Turbo_1C, + CPU_Update_Turbo_2C, + CPU_Update_Turbo_3C, + CPU_Update_Turbo_4C, + CPU_Update_Turbo_5C, + CPU_Update_Turbo_6C, + CPU_Update_Turbo_7C, + CPU_Update_Turbo_8C, + CPU_Update_Turbo_9C, + CPU_Update_Turbo_10C, + CPU_Update_Turbo_11C, + CPU_Update_Turbo_12C, + CPU_Update_Turbo_13C, + CPU_Update_Turbo_14C, + CPU_Update_Turbo_15C, + CPU_Update_Turbo_16C, + CPU_Update_Turbo_17C, + CPU_Update_Turbo_18C + }; + + AppendWindow( CreateSelectFreq( id, + Pkg_Item_Turbo_Freq[i18C], + CPU_Item_Turbo_Freq[i18C], + Pkg_Turbo_Freq_Update[i18C], + CPU_Turbo_Freq_Update[i18C] ), + &winList ); + } else { + SetHead(&winList, win); + } + } + break; + + case BOXKEY_RATIO_CLOCK_TGT: + { + unsigned long long id = scan->key | BOXKEY_RATIO_SELECT_OR; + Window *win = SearchWinListById(id, &winList); + if (win == NULL) { + AppendWindow( CreateSelectFreq( id, + Pkg_Item_Target_Freq, + CPU_Item_Target_Freq, + Pkg_Target_Freq_Update, + CPU_Target_Freq_Update ), + &winList ); + } else { + SetHead(&winList, win); + } + } + break; + + case BOXKEY_RATIO_CLOCK_HWP_TGT: + { + unsigned long long id = scan->key | BOXKEY_RATIO_SELECT_OR; + Window *win = SearchWinListById(id, &winList); + if (win == NULL) { + AppendWindow( CreateSelectFreq( id, + Pkg_Item_HWP_Target_Freq, + CPU_Item_HWP_Target_Freq, + Pkg_HWP_Target_Freq_Update, + CPU_HWP_Target_Freq_Update ), + &winList ); + } else { + SetHead(&winList, win); + } + } + break; + + case BOXKEY_RATIO_CLOCK_HWP_MAX: + { + unsigned long long id = scan->key | BOXKEY_RATIO_SELECT_OR; + Window *win = SearchWinListById(id, &winList); + if (win == NULL) { + AppendWindow( CreateSelectFreq( id, + Pkg_Item_HWP_Max_Freq, + CPU_Item_HWP_Max_Freq, + Pkg_HWP_Max_Freq_Update, + CPU_HWP_Max_Freq_Update ), + &winList ); + } else { + SetHead(&winList, win); + } + } + break; + + case BOXKEY_RATIO_CLOCK_HWP_MIN: + { + unsigned long long id = scan->key | BOXKEY_RATIO_SELECT_OR; + Window *win = SearchWinListById(id, &winList); + if (win == NULL) { + AppendWindow( CreateSelectFreq( id, + Pkg_Item_HWP_Min_Freq, + CPU_Item_HWP_Min_Freq, + Pkg_HWP_Min_Freq_Update, + CPU_HWP_Min_Freq_Update ), + &winList ); + } else { + SetHead(&winList, win); + } + } + break; + + case BOXKEY_RATIO_CLOCK_MAX: + { + unsigned long long id = scan->key | BOXKEY_RATIO_SELECT_OR; + Window *win = SearchWinListById(id, &winList); + if (win == NULL) { + AppendWindow( CreateSelectFreq( id, + Pkg_Item_Max_Freq, + CPU_Item_Max_Freq, + Pkg_Max_Freq_Update, + CPU_Max_Freq_Update ), + &winList ); + } else { + SetHead(&winList, win); + } + } + break; + + case BOXKEY_RATIO_CLOCK_MIN: + { + unsigned long long id = scan->key | BOXKEY_RATIO_SELECT_OR; + Window *win = SearchWinListById(id, &winList); + if (win == NULL) { + AppendWindow( CreateSelectFreq( id, + Pkg_Item_Min_Freq, + CPU_Item_Min_Freq, + Pkg_Min_Freq_Update, + CPU_Min_Freq_Update ), + &winList ); + } else { + SetHead(&winList, win); + } + } + break; + + case BOXKEY_RATIO_ACTIVATION: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + CPU_STRUCT *SProc = &RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core]; + struct FLIP_FLOP *CFlop = &SProc->FlipFlop[ + !RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Toggle + ]; + CLOCK_ARG clockMod = {.ullong = scan->key}; + const unsigned int NC = clockMod.NC & CLOCKMOD_RATIO_MASK; + + signed int lowestShift, highestShift; + ComputeRatioShifts( SProc->Boost[BOOST(ACT)], + 0, + MAXCLOCK_TO_RATIO(unsigned int,CFlop->Clock.Hz), + &lowestShift, + &highestShift ); + AppendWindow( + CreateRatioClock(scan->key, + SProc->Boost[BOOST(ACT)], + -1, + NC, + lowestShift, + highestShift, + + (int) ((SProc->Boost[BOOST(MIN)] + + RO(Shm)->Proc.Features.Factory.Ratio) >> 1), + + (int) (RO(Shm)->Proc.Features.Factory.Ratio + + ((MAXCLOCK_TO_RATIO(unsigned int, CFlop->Clock.Hz) + - RO(Shm)->Proc.Features.Factory.Ratio) >> 1)), + + BOXKEY_CFGTDP_CLOCK, + TitleForRatioClock, + 35), + &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case BOXKEY_UNCORE_CLOCK_MAX: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + CPU_STRUCT *SProc = &RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core]; + struct FLIP_FLOP *CFlop = &SProc->FlipFlop[ + !RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Toggle + ]; + CLOCK_ARG clockMod = {.ullong = scan->key}; + const unsigned int NC = clockMod.NC & CLOCKMOD_RATIO_MASK; + + signed int lowestShift, highestShift; + ComputeRatioShifts( RO(Shm)->Uncore.Boost[BOOST(MAX)], + RO(Shm)->Uncore.Boost[BOOST(MIN)], + MAXCLOCK_TO_RATIO(unsigned int,CFlop->Clock.Hz), + &lowestShift, + &highestShift ); + AppendWindow( + CreateRatioClock(scan->key, + RO(Shm)->Uncore.Boost[BOOST(MAX)], + -1, + NC, + lowestShift, + highestShift, + + (int) ((RO(Shm)->Uncore.Boost[BOOST(MIN)] + + RO(Shm)->Proc.Features.Factory.Ratio ) >> 1), + + (int) (RO(Shm)->Proc.Features.Factory.Ratio + + ((MAXCLOCK_TO_RATIO(unsigned int, CFlop->Clock.Hz) + - RO(Shm)->Proc.Features.Factory.Ratio) >> 1)), + + BOXKEY_UNCORE_CLOCK, + TitleForUncoreClock, + 36), + &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case BOXKEY_UNCORE_CLOCK_MIN: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) { + CLOCK_ARG clockMod = {.ullong = scan->key}; + const unsigned int NC = clockMod.NC & CLOCKMOD_RATIO_MASK, + highestOperating = KMAX(RO(Shm)->Proc.Features.Factory.Ratio, + RO(Shm)->Uncore.Boost[BOOST(MAX)]); + + signed int lowestShift, highestShift; + ComputeRatioShifts( RO(Shm)->Uncore.Boost[BOOST(MIN)], + 1, + highestOperating, + &lowestShift, + &highestShift ); + AppendWindow( + CreateRatioClock(scan->key, + RO(Shm)->Uncore.Boost[BOOST(MIN)], + -1, + NC, + lowestShift, + highestShift, + + (int) (RO(Shm)->Proc.Features.Factory.Ratio >> 1), + (int) (RO(Shm)->Proc.Features.Factory.Ratio - 1), + + BOXKEY_UNCORE_CLOCK, + TitleForUncoreClock, + 37), + &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case SCANKEY_F10: + case BOXKEY_TOOLS_MACHINE: + if (!RING_FULL(RW(Shm)->Ring[1])) { + RING_WRITE( RW(Shm)->Ring[1], + COREFREQ_ORDER_MACHINE, + COREFREQ_TOGGLE_OFF); + } + break; + + case SCANKEY_SHIFT_o: + if (RO(Shm)->Registration.Experimental) + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + const Coordinate origin = { + .col = 13, + .row = TOP_HEADER_ROW + 2 + }, select = { + .col = 0, + .row = 0 + }; + Window *wBox; + wBox = CreateBox(scan->key, origin, select, + (char*) RSC(BOX_TOOLS_TITLE).CODE(), + RSC(BOX_TOOLS_STOP_BURN).CODE(), + BITVAL(RW(Shm)->Proc.Sync, BURN) ? + RSC(UI).ATTR()[UI_BOX_TOOLS_STOP] : blankAttr, + BITVAL(RW(Shm)->Proc.Sync, BURN) ? + BOXKEY_TOOLS_MACHINE : SCANKEY_NULL, + RSC(BOX_TOOLS_ATOMIC_BURN).CODE(),stateAttr[0], + BOXKEY_TOOLS_ATOMIC, + RSC(BOX_TOOLS_CRC32_BURN).CODE() ,stateAttr[0], + BOXKEY_TOOLS_CRC32, + RSC(BOX_TOOLS_CONIC_BURN).CODE() ,stateAttr[0], + BOXKEY_TOOLS_CONIC, + RSC(BOX_TOOLS_RANDOM_CPU).CODE() ,stateAttr[0], + BOXKEY_TOOLS_TURBO_RND, + RSC(BOX_TOOLS_ROUND_ROBIN_CPU).CODE(), stateAttr[0], + BOXKEY_TOOLS_TURBO_RR, + RSC(BOX_TOOLS_USER_CPU).CODE(), stateAttr[0], + BOXKEY_TOOLS_TURBO_CPU, + RSC(BOX_TOOLS_MONTE_CARLO).CODE(), stateAttr[0], + BOXKEY_TOOLS_MONTE_CARLO); + + if (wBox != NULL) { + AppendWindow(wBox, &winList); + } else { + SetHead(&winList, win); + } + } else { + SetHead(&winList, win); + } + } + break; + + case BOXKEY_TOOLS_ATOMIC: + if (!RING_FULL(RW(Shm)->Ring[1])) { + RING_WRITE( RW(Shm)->Ring[1], + COREFREQ_ORDER_ATOMIC, + RO(Shm)->Proc.Service.Core, + COREFREQ_TOGGLE_ON); + } + break; + + case BOXKEY_TOOLS_CRC32: + if (!RING_FULL(RW(Shm)->Ring[1])) { + RING_WRITE( RW(Shm)->Ring[1], + COREFREQ_ORDER_CRC32, + RO(Shm)->Proc.Service.Core, + COREFREQ_TOGGLE_ON); + } + break; + + case BOXKEY_TOOLS_CONIC: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + const Coordinate origin = { + .col = 13 + 27 + 3, + .row = TOP_HEADER_ROW + 2 + 4 + }, select = { + .col = 0, + .row = 0 + }; + Window *wBox; + wBox = CreateBox(scan->key, origin, select, + (char*) RSC(BOX_CONIC_TITLE).CODE(), + RSC(BOX_CONIC_ITEM_1).CODE(), stateAttr[0],BOXKEY_TOOLS_CONIC0, + RSC(BOX_CONIC_ITEM_2).CODE(), stateAttr[0],BOXKEY_TOOLS_CONIC1, + RSC(BOX_CONIC_ITEM_3).CODE(), stateAttr[0],BOXKEY_TOOLS_CONIC2, + RSC(BOX_CONIC_ITEM_4).CODE(), stateAttr[0],BOXKEY_TOOLS_CONIC3, + RSC(BOX_CONIC_ITEM_5).CODE(), stateAttr[0],BOXKEY_TOOLS_CONIC4, + RSC(BOX_CONIC_ITEM_6).CODE(), stateAttr[0],BOXKEY_TOOLS_CONIC5); + + if (wBox != NULL) { + AppendWindow(wBox, &winList); + } else { + SetHead(&winList, win); + } + } else { + SetHead(&winList, win); + } + } + break; + + case BOXKEY_TOOLS_CONIC0: + if (!RING_FULL(RW(Shm)->Ring[1])) { + RING_WRITE_SUB_CMD( CONIC_ELLIPSOID, + RW(Shm)->Ring[1], + COREFREQ_ORDER_CONIC, + RO(Shm)->Proc.Service.Core ); + } + break; + + case BOXKEY_TOOLS_CONIC1: + if (!RING_FULL(RW(Shm)->Ring[1])) { + RING_WRITE_SUB_CMD( CONIC_HYPERBOLOID_ONE_SHEET, + RW(Shm)->Ring[1], + COREFREQ_ORDER_CONIC, + RO(Shm)->Proc.Service.Core ); + } + break; + + case BOXKEY_TOOLS_CONIC2: + if (!RING_FULL(RW(Shm)->Ring[1])) { + RING_WRITE_SUB_CMD( CONIC_HYPERBOLOID_TWO_SHEETS, + RW(Shm)->Ring[1], + COREFREQ_ORDER_CONIC, + RO(Shm)->Proc.Service.Core ); + } + break; + + case BOXKEY_TOOLS_CONIC3: + if (!RING_FULL(RW(Shm)->Ring[1])) { + RING_WRITE_SUB_CMD( CONIC_ELLIPTICAL_CYLINDER, + RW(Shm)->Ring[1], + COREFREQ_ORDER_CONIC, + RO(Shm)->Proc.Service.Core ); + } + break; + + case BOXKEY_TOOLS_CONIC4: + if (!RING_FULL(RW(Shm)->Ring[1])) { + RING_WRITE_SUB_CMD( CONIC_HYPERBOLIC_CYLINDER, + RW(Shm)->Ring[1], + COREFREQ_ORDER_CONIC, + RO(Shm)->Proc.Service.Core ); + } + break; + + case BOXKEY_TOOLS_CONIC5: + if (!RING_FULL(RW(Shm)->Ring[1])) { + RING_WRITE_SUB_CMD( CONIC_TWO_PARALLEL_PLANES, + RW(Shm)->Ring[1], + COREFREQ_ORDER_CONIC, + RO(Shm)->Proc.Service.Core ); + } + break; + + case BOXKEY_TOOLS_TURBO_RND: + if (!RING_FULL(RW(Shm)->Ring[1])) { + RING_WRITE_SUB_CMD( RAND_SMT, + RW(Shm)->Ring[1], + COREFREQ_ORDER_TURBO, + RO(Shm)->Proc.Service.Core ); + } + break; + + case BOXKEY_TOOLS_TURBO_RR: + if (!RING_FULL(RW(Shm)->Ring[1])) { + RING_WRITE_SUB_CMD( RR_SMT, + RW(Shm)->Ring[1], + COREFREQ_ORDER_TURBO, + RO(Shm)->Proc.Service.Core ); + } + break; + + case BOXKEY_TOOLS_TURBO_CPU: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + AppendWindow(CreateSelectCPU(scan->key), &winList); + else + SetHead(&winList, win); + } + break; + + case BOXKEY_TOOLS_MONTE_CARLO: + if (!RING_FULL(RW(Shm)->Ring[1])) { + RING_WRITE( RW(Shm)->Ring[1], + COREFREQ_ORDER_MONTE_CARLO, + RO(Shm)->Proc.Service.Core, + COREFREQ_TOGGLE_ON); + } + break; + + case SCANKEY_k: + case SCANKEY_e: + case SCANKEY_o: + case SCANKEY_p: + case SCANKEY_t: + case SCANKEY_w: + case SCANKEY_SHIFT_b: + case SCANKEY_z: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) { + AppendWindow(CreateSysInfo(scan->key), &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case SCANKEY_CTRL_p: + if (DumpStatus()) + { + AbortDump(); + } + else if (StartDump("corefreq_%llx.asc", 0, DUMP_TO_ANSI) == 0) + { + Draw.Flag.layout = 1; + } + break; + + case SCANKEY_ALT_p: + case SCANCON_ALT_p: + if (DumpStatus()) + { + AbortDump(); + } + else if (StartDump( "corefreq_%llx.cast", + (int) (Recorder.Reset - 1), + DUMP_TO_JSON) == 0 ) + { + Draw.Flag.layout = 1; + } + break; + + case OPS_RECORDER_RESET: + case OPS_RECORDER_X002: + case OPS_RECORDER_X010: + case OPS_RECORDER_X020: + case OPS_RECORDER_X060: + case OPS_RECORDER_X090: + case OPS_RECORDER_X120: + case OPS_RECORDER_X240: + { + __typeof__(Recorder.Select) select=(scan->key & OPS_RECORDER_MASK) >> 4; + Recorder.Select = select; + RECORDER_COMPUTE(Recorder, RO(Shm)->Sleep.Interval); + } + break; + + case OPS_RECORDER: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) { + AppendWindow(CreateRecorder(scan->key), &winList); + } else { + SetHead(&winList, win); + } + } + break; + + default: + if ((scan->key & TRACK_TASK) && !RING_FULL(RW(Shm)->Ring[1])) { + RING_WRITE_SUB_CMD( TASK_TRACKING, + RW(Shm)->Ring[1], + COREFREQ_TASK_MONITORING, + (pid_t) scan->key & TRACK_MASK ); + } + else if (scan->key & SMBIOS_STRING_INDEX) + { + if (Draw.Disposal == D_MAINVIEW) { + enum SMB_STRING usrIdx = scan->key & SMBIOS_STRING_MASK; + if (usrIdx < SMB_STRING_COUNT) { + Draw.SmbIndex = usrIdx; + Draw.Flag.layout = 1; + } + } + } + else if (scan->key & CPU_ONLINE) + { + const unsigned long cpu = scan->key & CPU_MASK; + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE(RW(Shm)->Ring[0], COREFREQ_IOCTL_CPU_ON, cpu); + } + } + else if (scan->key & CPU_OFFLINE) + { + const unsigned long cpu = scan->key & CPU_MASK; + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE(RW(Shm)->Ring[0], COREFREQ_IOCTL_CPU_OFF, cpu); + } + } + else if (scan->key & CPU_SELECT) + { + const unsigned short cpu = scan->key & CPU_MASK; + if (!RING_FULL(RW(Shm)->Ring[1])) { + RING_WRITE_SUB_CMD( USR_CPU, + RW(Shm)->Ring[1], + COREFREQ_ORDER_TURBO, + cpu ); + } + } + else + { + switch (scan->key & (~BOXKEY_RATIO_SELECT_OR ^ RATIO_MASK)) { + case BOXKEY_TURBO_CLOCK_1C: + case BOXKEY_TURBO_CLOCK_2C: + case BOXKEY_TURBO_CLOCK_3C: + case BOXKEY_TURBO_CLOCK_4C: + case BOXKEY_TURBO_CLOCK_5C: + case BOXKEY_TURBO_CLOCK_6C: + case BOXKEY_TURBO_CLOCK_7C: + case BOXKEY_TURBO_CLOCK_8C: + case BOXKEY_TURBO_CLOCK_9C: + case BOXKEY_TURBO_CLOCK_10C: + case BOXKEY_TURBO_CLOCK_11C: + case BOXKEY_TURBO_CLOCK_12C: + case BOXKEY_TURBO_CLOCK_13C: + case BOXKEY_TURBO_CLOCK_14C: + case BOXKEY_TURBO_CLOCK_15C: + case BOXKEY_TURBO_CLOCK_16C: + case BOXKEY_TURBO_CLOCK_17C: + case BOXKEY_TURBO_CLOCK_18C: + if (RO(Shm)->Proc.Features.Turbo_Unlock) + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + struct FLIP_FLOP *CFlop; + CLOCK_ARG clockMod = {.ullong = scan->key}; + unsigned int COF; + const unsigned int lowestOperating = 1; + const unsigned int NC = clockMod.NC & CLOCKMOD_RATIO_MASK; + const enum RATIO_BOOST boost = BOOST(SIZE) - NC; + signed int lowestShift, highestShift; + + const signed short cpu = (signed short) ( + (scan->key & RATIO_MASK) ^ CORE_COUNT + ); + if (cpu == -1) { + COF = RO(Shm)->Cpu[ Ruler.Top[boost] ].Boost[boost]; + CFlop = &RO(Shm)->Cpu[ Ruler.Top[boost] ].FlipFlop[ + !RO(Shm)->Cpu[ Ruler.Top[boost] ].Toggle + ]; + } else { + COF = RO(Shm)->Cpu[cpu].Boost[boost]; + CFlop = &RO(Shm)->Cpu[cpu].FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + } + ComputeRatioShifts(COF, + lowestOperating, + MAXCLOCK_TO_RATIO(unsigned int,CFlop->Clock.Hz), + &lowestShift, + &highestShift); + + AppendWindow( + CreateRatioClock(scan->key, + COF, + cpu, + NC, + lowestShift, + highestShift, + + (int) ((lowestOperating + + RO(Shm)->Proc.Features.Factory.Ratio) >> 1), + + (int) (RO(Shm)->Proc.Features.Factory.Ratio + + ((MAXCLOCK_TO_RATIO(unsigned int, CFlop->Clock.Hz) + - RO(Shm)->Proc.Features.Factory.Ratio) >> 1)), + + BOXKEY_TURBO_CLOCK, + TitleForTurboClock, + 34), + &winList ); + } else { + SetHead(&winList, win); + } + } + break; + + case BOXKEY_RATIO_CLOCK_TGT: + if (RO(Shm)->Proc.Features.TgtRatio_Unlock) + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + CLOCK_ARG clockMod = {.ullong = scan->key}; + unsigned int COF, lowestOperating, highestOperating; + const unsigned int NC = clockMod.NC & CLOCKMOD_RATIO_MASK; + signed int lowestShift, highestShift; + + const signed short cpu = (signed short) ( + (scan->key & RATIO_MASK) ^ CORE_COUNT + ); + if (cpu == -1) { + COF = RO(Shm)->Cpu[ Ruler.Top[BOOST(TGT)] ].Boost[BOOST(TGT)]; + lowestOperating = RO(Shm)->Cpu[ + Ruler.Top[ BOOST(TGT) ] + ].Boost[ BOOST(MIN) ]; + highestOperating = RO(Shm)->Cpu[ + Ruler.Top[ BOOST(TGT) ] + ].Boost[ BOOST(MAX) ]; + } else { + COF = RO(Shm)->Cpu[cpu].Boost[BOOST(TGT)]; + lowestOperating = RO(Shm)->Cpu[cpu].Boost[BOOST(MIN)]; + highestOperating = RO(Shm)->Cpu[cpu].Boost[BOOST(MAX)]; + } + ComputeRatioShifts( COF, + 0, /* AUTO Frequency */ + GetTopOfRuler(), + &lowestShift, + &highestShift ); + + AppendWindow( + CreateRatioClock(scan->key, + COF, + cpu, + NC, + lowestShift, + highestShift, + + (int) ((lowestOperating + + highestOperating) >> 1), + + (int) (CUMIN( RO(Shm)->Proc.Features.Factory.Ratio, + GetTopOfRuler() )), + + BOXKEY_RATIO_CLOCK, + TitleForRatioClock, + 35), + &winList ); + } else { + SetHead(&winList, win); + } + } + break; + + case BOXKEY_RATIO_CLOCK_HWP_TGT: + if ((RO(Shm)->Proc.Features.HWP_Enable == 1) + || (RO(Shm)->Proc.Features.ACPI_CPPC == 1)) + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + struct FLIP_FLOP *CFlop; + CLOCK_ARG clockMod = {.ullong = scan->key}; + struct HWP_STRUCT *pHWP; + const unsigned int NC = clockMod.NC & CLOCKMOD_RATIO_MASK; + unsigned int COF; + signed int lowestShift, highestShift; + + const signed short cpu = (signed short) ( + (scan->key & RATIO_MASK) ^ CORE_COUNT + ); + if (cpu == -1) { + pHWP = &RO(Shm)->Cpu[ + Ruler.Top[BOOST(HWP_TGT)] + ].PowerThermal.HWP; + COF = pHWP->Request.Desired_Perf; + + CFlop = &RO(Shm)->Cpu[Ruler.Top[ BOOST(MAX)] ].FlipFlop[ + !RO(Shm)->Cpu[Ruler.Top[BOOST(MAX)] + ].Toggle]; + } else { + pHWP = &RO(Shm)->Cpu[cpu].PowerThermal.HWP; + COF = pHWP->Request.Desired_Perf; + CFlop = &RO(Shm)->Cpu[cpu].FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + } + ComputeRatioShifts(COF, + 0, + MAXCLOCK_TO_RATIO(unsigned int,CFlop->Clock.Hz), + &lowestShift, + &highestShift); + + AppendWindow( + CreateRatioClock(scan->key, + COF, + cpu, + NC, + lowestShift, + highestShift, + + (int) ((pHWP->Capabilities.Lowest + + pHWP->Capabilities.Guaranteed) >> 1), + + (int) pHWP->Capabilities.Highest, + + BOXKEY_RATIO_CLOCK, + TitleForRatioClock, + 38), + &winList ); + } else { + SetHead(&winList, win); + } + } + break; + + case BOXKEY_RATIO_CLOCK_HWP_MAX: + if ((RO(Shm)->Proc.Features.HWP_Enable == 1) + || (RO(Shm)->Proc.Features.ACPI_CPPC == 1)) + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + struct FLIP_FLOP *CFlop; + CLOCK_ARG clockMod = {.ullong = scan->key}; + struct HWP_STRUCT *pHWP; + const unsigned int NC = clockMod.NC & CLOCKMOD_RATIO_MASK; + unsigned int COF; + signed int lowestShift, highestShift; + + const signed short cpu = (signed short) ( + (scan->key & RATIO_MASK) ^ CORE_COUNT + ); + if (cpu == -1) { + pHWP = &RO(Shm)->Cpu[ + Ruler.Top[BOOST(HWP_MAX)] + ].PowerThermal.HWP; + COF = pHWP->Request.Maximum_Perf; + + CFlop = &RO(Shm)->Cpu[Ruler.Top[ BOOST(MAX)] ].FlipFlop[ + !RO(Shm)->Cpu[Ruler.Top[BOOST(MAX)] + ].Toggle]; + } else { + pHWP = &RO(Shm)->Cpu[cpu].PowerThermal.HWP; + COF = pHWP->Request.Maximum_Perf; + CFlop = &RO(Shm)->Cpu[cpu].FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + } + ComputeRatioShifts(COF, + 0, + MAXCLOCK_TO_RATIO(unsigned int,CFlop->Clock.Hz), + &lowestShift, + &highestShift); + + AppendWindow( + CreateRatioClock(scan->key, + COF, + cpu, + NC, + lowestShift, + highestShift, + + (int) ((pHWP->Capabilities.Lowest + + pHWP->Capabilities.Guaranteed) >> 1), + + (int) pHWP->Capabilities.Highest, + + BOXKEY_RATIO_CLOCK, + TitleForRatioClock, + 39), + &winList ); + } else { + SetHead(&winList, win); + } + } + break; + + case BOXKEY_RATIO_CLOCK_HWP_MIN: + if ((RO(Shm)->Proc.Features.HWP_Enable == 1) + || (RO(Shm)->Proc.Features.ACPI_CPPC == 1)) + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + struct FLIP_FLOP *CFlop; + CLOCK_ARG clockMod = {.ullong = scan->key}; + struct HWP_STRUCT *pHWP; + const unsigned int NC = clockMod.NC & CLOCKMOD_RATIO_MASK; + unsigned int COF; + signed int lowestShift, highestShift; + + const signed short cpu = (signed short) ( + (scan->key & RATIO_MASK) ^ CORE_COUNT + ); + if (cpu == -1) { + pHWP = &RO(Shm)->Cpu[ + Ruler.Top[BOOST(HWP_MIN)] + ].PowerThermal.HWP; + COF = pHWP->Request.Minimum_Perf; + + CFlop = &RO(Shm)->Cpu[Ruler.Top[ BOOST(MAX)] ].FlipFlop[ + !RO(Shm)->Cpu[Ruler.Top[BOOST(MAX)] + ].Toggle]; + } else { + pHWP = &RO(Shm)->Cpu[cpu].PowerThermal.HWP; + COF = pHWP->Request.Minimum_Perf; + CFlop = &RO(Shm)->Cpu[cpu].FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + } + ComputeRatioShifts(COF, + 0, + MAXCLOCK_TO_RATIO(unsigned int,CFlop->Clock.Hz), + &lowestShift, + &highestShift); + + AppendWindow( + CreateRatioClock(scan->key, + COF, + cpu, + NC, + lowestShift, + highestShift, + + (int) ((pHWP->Capabilities.Lowest + + pHWP->Capabilities.Guaranteed) >> 1), + + (int) pHWP->Capabilities.Highest, + + BOXKEY_RATIO_CLOCK, + TitleForRatioClock, + 40), + &winList ); + } else { + SetHead(&winList, win); + } + } + break; + + case BOXKEY_RATIO_CLOCK_MAX: + if ((RO(Shm)->Proc.Features.ClkRatio_Unlock & 0b10) == 0b10) + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + struct FLIP_FLOP *CFlop; + CLOCK_ARG clockMod = {.ullong = scan->key}; + const unsigned int NC = clockMod.NC & CLOCKMOD_RATIO_MASK; + unsigned int COF, lowestOperating; + signed int lowestShift, highestShift; + + const signed short cpu = (signed short) ( + (scan->key & RATIO_MASK) ^ CORE_COUNT + ); + if (cpu == -1) { + COF = RO(Shm)->Cpu[ Ruler.Top[BOOST(MAX)] ].Boost[BOOST(MAX)]; + + lowestOperating = KMIN( RO(Shm)->Cpu[ + Ruler.Top[BOOST(MAX)] + ].Boost[BOOST(MIN)], + RO(Shm)->Proc.Features.Factory.Ratio ); + + CFlop = &RO(Shm)->Cpu[Ruler.Top[ BOOST(MAX)] ].FlipFlop[ + !RO(Shm)->Cpu[Ruler.Top[BOOST(MAX)] + ].Toggle]; + } else { + COF = RO(Shm)->Cpu[cpu].Boost[BOOST(MAX)]; + lowestOperating = KMIN( RO(Shm)->Cpu[cpu].Boost[BOOST(MIN)], + RO(Shm)->Proc.Features.Factory.Ratio ); + CFlop = &RO(Shm)->Cpu[cpu].FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + } + ComputeRatioShifts(COF, + lowestOperating, + MAXCLOCK_TO_RATIO(unsigned int,CFlop->Clock.Hz), + &lowestShift, + &highestShift); + + AppendWindow( + CreateRatioClock(scan->key, + COF, + cpu, + NC, + lowestShift, + highestShift, + + (int) ((lowestOperating + + RO(Shm)->Proc.Features.Factory.Ratio) >> 1), + + (int) (RO(Shm)->Proc.Features.Factory.Ratio + + ((MAXCLOCK_TO_RATIO(unsigned int, CFlop->Clock.Hz) + - RO(Shm)->Proc.Features.Factory.Ratio) >> 1)), + + BOXKEY_RATIO_CLOCK, + TitleForRatioClock, + 36), &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case BOXKEY_RATIO_CLOCK_MIN: + if ((RO(Shm)->Proc.Features.ClkRatio_Unlock & 0b01) == 0b01) + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + CLOCK_ARG clockMod = {.ullong = scan->key}; + const unsigned int NC = clockMod.NC & CLOCKMOD_RATIO_MASK; + unsigned int COF, lowestOperating; + signed int lowestShift, highestShift; + + const signed short cpu = (signed short) ( + (scan->key & RATIO_MASK) ^ CORE_COUNT + ); + if (cpu == -1) { + COF = RO(Shm)->Cpu[ Ruler.Top[BOOST(MIN)] ].Boost[BOOST(MIN)]; + lowestOperating = KMIN( RO(Shm)->Cpu[ + Ruler.Top[BOOST(MIN)] + ].Boost[BOOST(MIN)], + RO(Shm)->Proc.Features.Factory.Ratio ); + } else { + COF = RO(Shm)->Cpu[cpu].Boost[BOOST(MIN)]; + lowestOperating = KMIN( RO(Shm)->Cpu[cpu].Boost[BOOST(MIN)], + RO(Shm)->Proc.Features.Factory.Ratio ); + } + ComputeRatioShifts(COF, + 0, + RO(Shm)->Proc.Features.Factory.Ratio, + &lowestShift, + &highestShift); + + AppendWindow( + CreateRatioClock(scan->key, + COF, + cpu, + NC, + lowestShift, + highestShift, + + (int) ((lowestOperating + + RO(Shm)->Proc.Features.Factory.Ratio) >> 1), + + (int) (RO(Shm)->Proc.Features.Factory.Ratio - 1), + + BOXKEY_RATIO_CLOCK, + TitleForRatioClock, + 37), &winList); + } else { + SetHead(&winList, win); + } + } + break; + + default: { + CLOCK_ARG clockMod = {.ullong = scan->key}; + if (clockMod.NC & BOXKEY_TURBO_CLOCK) + { + clockMod.NC &= CLOCKMOD_RATIO_MASK; + + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_TURBO_CLOCK, clockMod.ullong ); + } + } + else if (clockMod.NC & BOXKEY_RATIO_CLOCK) + { + clockMod.NC &= CLOCKMOD_RATIO_MASK; + + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_RATIO_CLOCK, clockMod.ullong ); + } + } + else if (clockMod.NC & BOXKEY_UNCORE_CLOCK) + { + clockMod.NC &= CLOCKMOD_RATIO_MASK; + + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_UNCORE_CLOCK, clockMod.ullong ); + } + } else { + return -1; + } + } + break; + } + } + break; + } + return 0; +} + +#ifndef NO_FOOTER +void PrintTaskMemory(Layer *layer, CUINT row, + unsigned short procCount, + unsigned long freeRAM, + unsigned long totalRAM) +{ + StrFormat(Buffer, 6+20+20+1, + "%6u" "%9lu" "%-9lu", + procCount, + freeRAM >> Draw.Unit.Memory, + totalRAM >> Draw.Unit.Memory); + + memcpy(&LayerAt(layer, code, Draw.Area.Footer.TaskMem.Total, row), + &Buffer[0], 6); + + memcpy(&LayerAt(layer, code, Draw.Area.Footer.TaskMem.Free, row), + &Buffer[6], 9); + + memcpy(&LayerAt(layer, code, Draw.Area.Footer.TaskMem.Count, row), + &Buffer[15], 9); +} +#endif + +#ifndef NO_HEADER +void Layout_Header(Layer *layer, CUINT row) +{ + int len; + const CUINT lProc0 = RSZ(LAYOUT_HEADER_PROC), + xProc0 = 12, + lProc1 = RSZ(LAYOUT_HEADER_CPU), + xProc1 = Draw.Size.width - lProc1, + lArch0 = RSZ(LAYOUT_HEADER_ARCH), + xArch0 = 12, + lArch1 = RSZ(LAYOUT_HEADER_CACHE_L1), + xArch1 = Draw.Size.width-lArch1, + lBClk0 = RSZ(LAYOUT_HEADER_BCLK), + xBClk0 = 12, + lArch2 = RSZ(LAYOUT_HEADER_CACHES), + xArch2 = Draw.Size.width-lArch2; + + PrintLCD(layer, 0, row, RSZ(LAYOUT_LCD_RESET), + (char *) RSC(LAYOUT_LCD_RESET).CODE(), + RSC(UI).ATTR()[UI_LAYOUT_LCD_RESET]); + + LayerDeclare(LAYOUT_HEADER_PROC, lProc0, xProc0, row, hProc0); + LayerDeclare(LAYOUT_HEADER_CPU , lProc1, xProc1, row, hProc1); + + row++; + + LayerDeclare(LAYOUT_HEADER_ARCH, lArch0, xArch0, row, hArch0); + LayerDeclare(LAYOUT_HEADER_CACHE_L1,lArch1,xArch1,row,hArch1); + + row++; + + LayerDeclare(LAYOUT_HEADER_BCLK, lBClk0, xBClk0, row, hBClk0); + LayerDeclare(LAYOUT_HEADER_CACHES,lArch2,xArch2, row, hArch2); + + row++; + + if (StrFormat(Buffer, 10+10+1, + "%3u" "%-3u", + RO(Shm)->Proc.CPU.OnLine, + RO(Shm)->Proc.CPU.Count) > 0) + { + hProc1.code[2] = (ASCII) Buffer[0]; + hProc1.code[3] = (ASCII) Buffer[1]; + hProc1.code[4] = (ASCII) Buffer[2]; + hProc1.code[6] = (ASCII) Buffer[3]; + hProc1.code[7] = (ASCII) Buffer[4]; + hProc1.code[8] = (ASCII) Buffer[5]; + } + unsigned int L1I_Size = 0, L1D_Size = 0, L2U_Size = 0, L3U_Size = 0; + + L1I_Size = \ + RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Topology.Cache[0].Size / 1024; + + L1D_Size = \ + RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Topology.Cache[1].Size / 1024; + + L2U_Size = \ + RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Topology.Cache[2].Size / 1024; + + L3U_Size = \ + RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Topology.Cache[3].Size / 1024; + + if (StrFormat(Buffer, 10+10+1, "%-3u" "%-3u", L1I_Size, L1D_Size) > 0) + { + hArch1.code[17] = (ASCII) Buffer[0]; + hArch1.code[18] = (ASCII) Buffer[1]; + hArch1.code[19] = (ASCII) Buffer[2]; + hArch1.code[25] = (ASCII) Buffer[3]; + hArch1.code[26] = (ASCII) Buffer[4]; + hArch1.code[27] = (ASCII) Buffer[5]; + } + if (StrFormat(Buffer, 10+10+1, "%-4u" "%-5u", L2U_Size, L3U_Size) > 0) + { + hArch2.code[ 3] = (ASCII) Buffer[0]; + hArch2.code[ 4] = (ASCII) Buffer[1]; + hArch2.code[ 5] = (ASCII) Buffer[2]; + hArch2.code[ 6] = (ASCII) Buffer[3]; + hArch2.code[13] = (ASCII) Buffer[4]; + hArch2.code[14] = (ASCII) Buffer[5]; + hArch2.code[15] = (ASCII) Buffer[6]; + hArch2.code[16] = (ASCII) Buffer[7]; + hArch2.code[17] = (ASCII) Buffer[8]; + } + len = CUMIN(xProc1 - (hProc0.origin.col + hProc0.length), + (CUINT) strlen(RO(Shm)->Proc.Brand)); + /* RED DOT */ + hProc0.code[0] = BITVAL(RW(Shm)->Proc.Sync, BURN) ? '.' : 0x20; + + LayerCopyAt( layer, hProc0.origin.col, hProc0.origin.row, + hProc0.length, hProc0.attr, hProc0.code ); + + LayerFillAt( layer, + (hProc0.origin.col + hProc0.length), hProc0.origin.row, + len, RO(Shm)->Proc.Brand, + RSC(UI).ATTR()[UI_LAYOUT_HEADER_PROC_BRAND] ); + + if ((hProc1.origin.col - len) > 0) { + LayerFillAt( layer, + (hProc0.origin.col + hProc0.length + len), + hProc0.origin.row, + (hProc1.origin.col - len), hSpace, + RSC(UI).ATTR()[UI_LAYOUT_HEADER_PROC_BRAND_FILL] ); + } + LayerCopyAt( layer, hProc1.origin.col, hProc1.origin.row, + hProc1.length, hProc1.attr, hProc1.code ); + + len = CUMIN(xArch1 - (hArch0.origin.col + hArch0.length), + (CUINT) strlen(RO(Shm)->Proc.Architecture)); + /* DUMP DOT */ + hArch0.code[0] = DumpStatus() ? '.' : 0x20; + + LayerCopyAt( layer, hArch0.origin.col, hArch0.origin.row, + hArch0.length, hArch0.attr, hArch0.code ); + + LayerFillAt( layer, + (hArch0.origin.col + hArch0.length), hArch0.origin.row, + len, RO(Shm)->Proc.Architecture, + RSC(UI).ATTR()[UI_LAYOUT_HEADER_ARCHITECTURE] ); + + if ((hArch1.origin.col - len) > 0) { + LayerFillAt( layer, + (hArch0.origin.col + hArch0.length + len), + hArch0.origin.row, + (hArch1.origin.col - len), hSpace, + RSC(UI).ATTR()[UI_LAYOUT_HEADER_ARCH_FILL] ); + } + LayerCopyAt( layer, hArch1.origin.col, hArch1.origin.row, + hArch1.length, hArch1.attr, hArch1.code ); + + LayerCopyAt( layer, hBClk0.origin.col, hBClk0.origin.row, + hBClk0.length, hBClk0.attr, hBClk0.code ); + + LayerFillAt( layer, + (hBClk0.origin.col + hBClk0.length), hBClk0.origin.row, + (hArch2.origin.col - hBClk0.origin.col + hBClk0.length), + hSpace, + RSC(UI).ATTR()[UI_LAYOUT_HEADER_BCLK_FILL] ); + + LayerCopyAt( layer, hArch2.origin.col, hArch2.origin.row, + hArch2.length, hArch2.attr, hArch2.code ); +} +#endif /* NO_HEADER */ + +#ifndef NO_UPPER +void Layout_Ruler_Load(Layer *layer, CUINT row) +{ + LayerDeclare(LAYOUT_RULER_LOAD, Draw.Size.width, 0, row, hLoad0); + + struct { + Coordinate origin; + CUINT length; + ATTRIBUTE *attr[2]; + ASCII *code[2]; + } hLoad1 = { + .origin = { + .col = hLoad0.origin.col + 6, + .row = hLoad0.origin.row + }, + .length = RSZ(LAYOUT_RULER_REL_LOAD), + .attr = { + RSC(LAYOUT_RULER_REL_LOAD).ATTR(), + RSC(LAYOUT_RULER_ABS_LOAD).ATTR() + }, + .code = { + RSC(LAYOUT_RULER_REL_LOAD).CODE(), + RSC(LAYOUT_RULER_ABS_LOAD).CODE() + } + }; + const ATTRIBUTE attr[2] = { + RSC(UI).ATTR()[UI_LAYOUT_RULER_LOAD_TAB_DIM], + RSC(UI).ATTR()[UI_LAYOUT_RULER_LOAD_TAB_BRIGHT] + }; + unsigned int idx = Ruler.Count, bright = 1; + const CUINT margin = 4; + CUINT lPos = Draw.Area.LoadWidth + margin; + + LayerCopyAt(layer, hLoad0.origin.col, hLoad0.origin.row, + hLoad0.length, hLoad0.attr, hLoad0.code); + + /* Alternate the color of the frequency ratios */ + while (idx--) + { + double fPos = (Ruler.Uniq[idx] * Draw.Area.LoadWidth) / Ruler.Maximum; + CUINT hPos = (CUINT) fPos; + + ASCII tabStop[10+1] = "00"; + if ((StrFormat(tabStop, 10+1, "%2u", Ruler.Uniq[idx]) > 0) && (hPos < lPos)) + { + hPos = hLoad0.origin.col + hPos + 2; + if (tabStop[0] != 0x20) { + LayerAt(layer,code, hPos, hLoad0.origin.row) = tabStop[0]; + LayerAt(layer,attr, hPos, hLoad0.origin.row) = attr[bright]; + } + LayerAt(layer, code, (hPos + 1), hLoad0.origin.row) = tabStop[1]; + LayerAt(layer, attr, (hPos + 1), hLoad0.origin.row) = attr[bright]; + + bright = !bright; + } + lPos = hPos >= margin ? hPos - margin : margin; + } + LayerCopyAt(layer, hLoad1.origin.col, hLoad1.origin.row, hLoad1.length, + hLoad1.attr[Draw.Load], hLoad1.code[Draw.Load]); +} +#endif /* NO_UPPER */ + +#ifndef NO_LOWER +CUINT Layout_Monitor_Frequency(Layer *layer, const unsigned int cpu, CUINT row) +{ + LayerDeclare( LAYOUT_MONITOR_FREQUENCY, RSZ(LAYOUT_MONITOR_FREQUENCY), + (LOAD_LEAD - 1), row, hMon0 ); + + LayerCopyAt( layer, hMon0.origin.col, hMon0.origin.row, + hMon0.length, hMon0.attr, hMon0.code ); + UNUSED(cpu); + + return 0; +} + +CUINT Layout_Monitor_Instructions(Layer *layer,const unsigned int cpu,CUINT row) +{ + LayerDeclare( LAYOUT_MONITOR_INST, RSZ(LAYOUT_MONITOR_INST), + (LOAD_LEAD - 1), row, hMon0 ); + + LayerCopyAt( layer, hMon0.origin.col, hMon0.origin.row, + hMon0.length, hMon0.attr, hMon0.code ); + UNUSED(cpu); + + return 0; +} + +CUINT Layout_Monitor_Common(Layer *layer, const unsigned int cpu, CUINT row) +{ + LayerDeclare( LAYOUT_MONITOR_COMMON, RSZ(LAYOUT_MONITOR_COMMON), + (LOAD_LEAD - 1), row, hMon0 ); + + LayerCopyAt( layer, hMon0.origin.col, hMon0.origin.row, + hMon0.length, hMon0.attr, hMon0.code ); + UNUSED(cpu); + + return 0; +} + +CUINT Layout_Monitor_Package(Layer *layer, const unsigned int cpu, CUINT row) +{ + UNUSED(layer); + UNUSED(cpu); + UNUSED(row); + + return 0; +} + +CUINT Layout_Monitor_Tasks(Layer *layer, const unsigned int cpu, CUINT row) +{ + LayerDeclare( LAYOUT_MONITOR_TASKS, (MAX_WIDTH - LOAD_LEAD + 1), + (LOAD_LEAD - 1), row, hMon0 ); + + LayerCopyAt( layer, hMon0.origin.col, hMon0.origin.row, + hMon0.length, hMon0.attr, hMon0.code ); + + cTask[cpu].col = LOAD_LEAD + 8; + cTask[cpu].row = hMon0.origin.row; + + return 0; +} + +CUINT Layout_Monitor_Slice(Layer *layer, const unsigned int cpu, CUINT row) +{ + LayerDeclare( LAYOUT_MONITOR_SLICE, RSZ(LAYOUT_MONITOR_SLICE), + (LOAD_LEAD - 1), row, hMon0 ); + UNUSED(cpu); + + LayerCopyAt( layer, hMon0.origin.col, hMon0.origin.row, + hMon0.length, hMon0.attr, hMon0.code ); + + return 0; +} + +CUINT Layout_Monitor_Custom(Layer *layer, const unsigned int cpu, CUINT row) +{ + LayerDeclare( LAYOUT_CUSTOM_FIELD, RSZ(LAYOUT_CUSTOM_FIELD), + (LOAD_LEAD - 1), row, hCustom0 ); + UNUSED(cpu); + + LayerCopyAt( layer, hCustom0.origin.col, hCustom0.origin.row, + hCustom0.length, hCustom0.attr, hCustom0.code ); + + return 0; +} + +CUINT Layout_Ruler_Frequency(Layer *layer, const unsigned int cpu, CUINT row) +{ + LayerDeclare( LAYOUT_RULER_FREQUENCY, Draw.Size.width, + 0, row, hFreq0 ); + UNUSED(cpu); + + LayerCopyAt( layer, hFreq0.origin.col, hFreq0.origin.row, + hFreq0.length, hFreq0.attr, hFreq0.code ); + + if (!Draw.Flag.avgOrPC) { + LayerDeclare( LAYOUT_RULER_FREQUENCY_AVG, Draw.Size.width, + 0, (row + Draw.Area.MaxRows + 1), hAvg0 ); + + LayerCopyAt( layer, hAvg0.origin.col, hAvg0.origin.row, + hAvg0.length, hAvg0.attr, hAvg0.code ); + } else { + LayerDeclare( LAYOUT_RULER_FREQUENCY_PKG, Draw.Size.width, + 0, (row + Draw.Area.MaxRows + 1), hPkg0) ; + + LayerCopyAt( layer, hPkg0.origin.col, hPkg0.origin.row, + hPkg0.length, hPkg0.attr, hPkg0.code ); + } + row += Draw.Area.MaxRows + 2; + return row; +} + +CUINT Layout_Ruler_Instructions(Layer *layer, const unsigned int cpu,CUINT row) +{ + LayerDeclare( LAYOUT_RULER_INST, Draw.Size.width, + 0, row, hInstr ); + UNUSED(cpu); + + LayerCopyAt( layer, hInstr.origin.col, hInstr.origin.row, + hInstr.length, hInstr.attr, hInstr.code ); + + LayerFillAt( layer, 0, (row + Draw.Area.MaxRows + 1), + Draw.Size.width, hLine, + RSC(UI).ATTR()[UI_LAYOUT_RULER_INSTRUCTIONS] ); + + row += Draw.Area.MaxRows + 2; + return row; +} + +CUINT Layout_Ruler_Cycles(Layer *layer, const unsigned int cpu, CUINT row) +{ + LayerDeclare( LAYOUT_RULER_CYCLES, Draw.Size.width, + 0, row, hCycles ); + UNUSED(cpu); + + LayerCopyAt( layer, hCycles.origin.col, hCycles.origin.row, + hCycles.length, hCycles.attr, hCycles.code ); + + LayerFillAt( layer, 0, (row + Draw.Area.MaxRows + 1), + Draw.Size.width, hLine, + RSC(UI).ATTR()[UI_LAYOUT_RULER_CYCLES] ); + + row += Draw.Area.MaxRows + 2; + return row; +} + +CUINT Layout_Ruler_CStates(Layer *layer, const unsigned int cpu, CUINT row) +{ + LayerDeclare( LAYOUT_RULER_CSTATES, Draw.Size.width, + 0, row, hCStates ); + UNUSED(cpu); + + LayerCopyAt( layer, hCStates.origin.col, hCStates.origin.row, + hCStates.length, hCStates.attr, hCStates.code ); + + LayerFillAt( layer, 0, (row + Draw.Area.MaxRows + 1), + Draw.Size.width, hLine, + RSC(UI).ATTR()[UI_LAYOUT_RULER_CSTATES] ); + + row += Draw.Area.MaxRows + 2; + return row; +} + +CUINT Layout_Ruler_Interrupts(Layer *layer, const unsigned int cpu, CUINT row) +{ + LayerDeclare( LAYOUT_RULER_INTERRUPTS, Draw.Size.width, + 0, row, hIntr0 ); + UNUSED(cpu); + + LayerCopyAt( layer, hIntr0.origin.col, hIntr0.origin.row, + hIntr0.length, hIntr0.attr, hIntr0.code ); + + LayerFillAt( layer, 0, (row + Draw.Area.MaxRows + 1), + Draw.Size.width, hLine, + RSC(UI).ATTR()[UI_LAYOUT_RULER_INTERRUPTS] ); + + row += Draw.Area.MaxRows + 2; + return row; +} + +CUINT Layout_Ruler_Package(Layer *layer, const unsigned int cpu, CUINT row) +{ + const ASCII *Pkg_CState[9] = { + RSC(LAYOUT_PACKAGE_PC02).CODE(), + RSC(LAYOUT_PACKAGE_PC03).CODE(), + RSC(LAYOUT_PACKAGE_PC04).CODE(), + RSC(LAYOUT_PACKAGE_PC06).CODE(), + RSC(LAYOUT_PACKAGE_PC07).CODE(), + RSC(LAYOUT_PACKAGE_PC08).CODE(), + RSC(LAYOUT_PACKAGE_PC09).CODE(), + RSC(LAYOUT_PACKAGE_PC10).CODE(), + RSC(LAYOUT_PACKAGE_MC06).CODE() + }, **hCState = Pkg_CState; + + LayerFillAt( layer, 0, row, Draw.Size.width, + RSC(LAYOUT_RULER_PACKAGE).CODE(), + RSC(LAYOUT_RULER_PACKAGE).ATTR()[0]); + + unsigned int idx; + UNUSED(cpu); + + for (idx = 0; idx < 9; idx++) + { + LayerCopyAt( layer, 0, (row + idx + 1), + Draw.Size.width, + RSC(LAYOUT_PACKAGE_PC).ATTR(), + RSC(LAYOUT_PACKAGE_PC).CODE()); + + LayerAt(layer, code, 0, (row + idx + 1)) = hCState[idx][0]; + LayerAt(layer, code, 1, (row + idx + 1)) = hCState[idx][1]; + LayerAt(layer, code, 2, (row + idx + 1)) = hCState[idx][2]; + LayerAt(layer, code, 3, (row + idx + 1)) = hCState[idx][3]; + } + + LayerDeclare( LAYOUT_PACKAGE_UNCORE, Draw.Size.width, + 0, (row + 10), Pkg_Uncore); + + const LAYER_DECL_ST *hUncore = &Pkg_Uncore; + + LayerCopyAt( layer, hUncore->origin.col, hUncore->origin.row, + hUncore->length, hUncore->attr, hUncore->code); + + LayerFillAt( layer, 0, (row + 11), + Draw.Size.width, hLine, + RSC(UI).ATTR()[UI_LAYOUT_RULER_PACKAGE] ); + + row += 2 + 10; + return row; +} + +CUINT Layout_Ruler_Tasks(Layer *layer, const unsigned int cpu, CUINT row) +{ + LayerDeclare(LAYOUT_RULER_TASKS, Draw.Size.width, 0, row, hTask0); + + struct { + ATTRIBUTE *attr; + ASCII *code; + } hSort[SORTBYCOUNT] = { + { + .attr = RSC(LAYOUT_TASKS_STATE_SORTED).ATTR(), + .code = RSC(LAYOUT_TASKS_STATE_SORTED).CODE() + }, + { + .attr = RSC(LAYOUT_TASKS_RUNTIME_SORTED).ATTR(), + .code = RSC(LAYOUT_TASKS_RUNTIME_SORTED).CODE() + }, + { + .attr = RSC(LAYOUT_TASKS_USRTIME_SORTED).ATTR(), + .code = RSC(LAYOUT_TASKS_USRTIME_SORTED).CODE() + }, + { + .attr = RSC(LAYOUT_TASKS_SYSTIME_SORTED).ATTR(), + .code = RSC(LAYOUT_TASKS_SYSTIME_SORTED).CODE() + }, + { + .attr = RSC(LAYOUT_TASKS_PROCESS_SORTED).ATTR(), + .code = RSC(LAYOUT_TASKS_PROCESS_SORTED).CODE() + }, + { + .attr = RSC(LAYOUT_TASKS_COMMAND_SORTED).ATTR(), + .code = RSC(LAYOUT_TASKS_COMMAND_SORTED).CODE() + } + }; + + struct { + Coordinate origin; + CUINT length; + ATTRIBUTE *attr; + ASCII *code; + } hTask1 = { + .origin = { + .col = 23, + .row = row + }, + .length = 21, + .attr = hSort[RO(Shm)->SysGate.sortByField].attr, + .code = hSort[RO(Shm)->SysGate.sortByField].code + }; + + struct { + ATTRIBUTE *attr; + ASCII *code; + } hReverse[2] = { + { + .attr = RSC(LAYOUT_TASKS_REVERSE_SORT_OFF).ATTR(), + .code = RSC(LAYOUT_TASKS_REVERSE_SORT_OFF).CODE() + }, + { + .attr = RSC(LAYOUT_TASKS_REVERSE_SORT_ON).ATTR(), + .code = RSC(LAYOUT_TASKS_REVERSE_SORT_ON).CODE() + } + }; + + struct { + Coordinate origin; + CUINT length; + ATTRIBUTE *attr; + ASCII *code; + } hTask2 = { + .origin = { + .col = (Draw.Size.width - 18), + .row = (row + Draw.Area.MaxRows + 1) + }, + .length = 15, + .attr = hReverse[RO(Shm)->SysGate.reverseOrder].attr, + .code = hReverse[RO(Shm)->SysGate.reverseOrder].code + }; + + LayerDeclare(LAYOUT_TASKS_VALUE_SWITCH, RSZ(LAYOUT_TASKS_VALUE_SWITCH), + (Draw.Size.width - 34), + (row + Draw.Area.MaxRows + 1), + hTask3); + + struct { + ATTRIBUTE *attr; + ASCII *code; + } hTaskVal[2] = { + { + .attr = RSC(LAYOUT_TASKS_VALUE_OFF).ATTR(), + .code = RSC(LAYOUT_TASKS_VALUE_OFF).CODE() + }, + { + .attr = RSC(LAYOUT_TASKS_VALUE_ON).ATTR(), + .code = RSC(LAYOUT_TASKS_VALUE_ON).CODE() + } + }; + UNUSED(cpu); + + memcpy(&hTask3.attr[8], hTaskVal[Draw.Flag.taskVal].attr, 3); + memcpy(&hTask3.code[8], hTaskVal[Draw.Flag.taskVal].code, 3); + + LayerDeclare( LAYOUT_TASKS_TRACKING, RSZ(LAYOUT_TASKS_TRACKING), + 53, row, hTrack0 ); + + LayerCopyAt( layer, hTask0.origin.col, hTask0.origin.row, + hTask0.length, hTask0.attr, hTask0.code ); + + LayerCopyAt( layer, hTask1.origin.col, hTask1.origin.row, + hTask1.length, hTask1.attr, hTask1.code ); + + LayerFillAt( layer, 0, (row + Draw.Area.MaxRows + 1), + Draw.Size.width, hLine, + RSC(UI).ATTR()[UI_LAYOUT_RULER_TASKS_FILL] ); + + LayerCopyAt( layer, hTask2.origin.col, hTask2.origin.row, + hTask2.length, hTask2.attr, hTask2.code ); + + LayerCopyAt( layer, hTask3.origin.col, hTask3.origin.row, + hTask3.length, hTask3.attr, hTask3.code ); + + LayerCopyAt( layer, hTrack0.origin.col, hTrack0.origin.row, + hTrack0.length, hTrack0.attr, hTrack0.code ); + + if (RO(Shm)->SysGate.trackTask) + { + StrFormat(Buffer, 11+1, "%7d", RO(Shm)->SysGate.trackTask); + LayerFillAt( layer, + (hTrack0.origin.col + 15), hTrack0.origin.row, + 7, Buffer, + RSC(UI).ATTR()[UI_LAYOUT_RULER_TASKS_TRACKING]); + } + row += Draw.Area.MaxRows + 2; + return row; +} + +CUINT Layout_Ruler_Sensors(Layer *layer, const unsigned int cpu, CUINT row) +{ + CUINT oRow; + + LayerDeclare(LAYOUT_RULER_SENSORS, Draw.Size.width, 0, row, hSensors); + + UNUSED(cpu); + + LayerCopyAt( layer, hSensors.origin.col, hSensors.origin.row, + hSensors.length, hSensors.attr, hSensors.code ); + + LayerAt(layer,code,32,hSensors.origin.row)=Setting.fahrCels ? 'F':'C'; + + LayerDeclare( LAYOUT_RULER_PWR_SOC, Draw.Size.width, + 0, (row + Draw.Area.MaxRows + 1), hPwrSoC ); + + LayerCopyAt( layer, hPwrSoC.origin.col, hPwrSoC.origin.row, + hPwrSoC.length, hPwrSoC.attr, hPwrSoC.code ); + + oRow = hPwrSoC.origin.row; + + LayerAt(layer,code, 45, oRow) = '0' + + RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Topology.PackageID; + + LayerAt(layer,code, 14, oRow) = \ + LayerAt(layer,code, 35, oRow) = \ + LayerAt(layer,code, 57, oRow) = \ + LayerAt(layer,code, 77, oRow) = Setting.jouleWatt ? 'W':'J'; + + row += Draw.Area.MaxRows + 2; + return row; +} + +CUINT Layout_Ruler_Voltage(Layer *layer, const unsigned int cpu, CUINT row) +{ + LayerDeclare( LAYOUT_RULER_VOLTAGE, Draw.Size.width, 0, row, hVolt ); + + UNUSED(cpu); + + LayerCopyAt( layer, hVolt.origin.col, hVolt.origin.row, + hVolt.length, hVolt.attr, hVolt.code ); + + LayerDeclare( LAYOUT_RULER_VPKG_SOC, Draw.Size.width, + 0, (row + Draw.Area.MaxRows + 1), hVPkg ); + + LayerCopyAt( layer, hVPkg.origin.col, hVPkg.origin.row, + hVPkg.length, hVPkg.attr, hVPkg.code ); + + row += Draw.Area.MaxRows + 2; + return row; +} + +CUINT Layout_Ruler_Energy(Layer *layer, const unsigned int cpu, CUINT row) +{ + CUINT oRow; + UNUSED(cpu); + + if (Setting.jouleWatt) + { + LayerDeclare(LAYOUT_RULER_POWER, Draw.Size.width, 0, row, hPwr0); + + LayerCopyAt( layer, hPwr0.origin.col, hPwr0.origin.row, + hPwr0.length, hPwr0.attr, hPwr0.code ); + } + else + { + LayerDeclare(LAYOUT_RULER_ENERGY, Draw.Size.width, 0, row, hPwr0); + + LayerCopyAt( layer, hPwr0.origin.col, hPwr0.origin.row, + hPwr0.length, hPwr0.attr, hPwr0.code ); + } + LayerFillAt( layer, 0, (row + Draw.Area.MaxRows + 1), + Draw.Size.width, hLine, + RSC(UI).ATTR()[UI_LAYOUT_RULER_ENERGY] ); + + LayerDeclare( LAYOUT_RULER_PWR_SOC, Draw.Size.width, + 0, (row + Draw.Area.MaxRows + 1), hPwrSoC); + + LayerCopyAt( layer, hPwrSoC.origin.col, hPwrSoC.origin.row, + hPwrSoC.length, hPwrSoC.attr, hPwrSoC.code ); + + oRow = hPwrSoC.origin.row; + + LayerAt(layer,code, 45, oRow) = '0' + + RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Topology.PackageID; + + LayerAt(layer,code, 14, oRow) = \ + LayerAt(layer,code, 35, oRow) = \ + LayerAt(layer,code, 57, oRow) = \ + LayerAt(layer,code, 77, oRow) = Setting.jouleWatt ? 'W':'J'; + + row += Draw.Area.MaxRows + 2; + return row; +} + +CUINT Layout_Ruler_Slice(Layer *layer, const unsigned int cpu, CUINT row) +{ + LayerDeclare(LAYOUT_RULER_SLICE, Draw.Size.width, 0, row, hSlice0); + + UNUSED(cpu); + + LayerCopyAt( layer, hSlice0.origin.col, hSlice0.origin.row, + hSlice0.length, hSlice0.attr, hSlice0.code ); + + LayerFillAt( layer, 0, (row + Draw.Area.MaxRows + 1), + Draw.Size.width, hLine, + RSC(UI).ATTR()[UI_LAYOUT_RULER_SLICE] ); + + row += Draw.Area.MaxRows + 2; + return row; +} + +CUINT Layout_Ruler_Custom(Layer *layer, const unsigned int cpu, CUINT row) +{ + LayerDeclare(LAYOUT_RULER_CUSTOM, Draw.Size.width, 0, row, hCust0); + + UNUSED(cpu); + + LayerCopyAt( layer, hCust0.origin.col, hCust0.origin.row, + hCust0.length, hCust0.attr, hCust0.code ); + + LayerFillAt( layer, 0, (row + Draw.Area.MaxRows + 1), + Draw.Size.width, hLine, + RSC(UI).ATTR()[UI_LAYOUT_RULER_CUSTOM] ); + + LayerAt(layer, code, 99, hCust0.origin.row) = \ + LayerAt(layer, code, 117, hCust0.origin.row) = \ + Setting.jouleWatt ? 'W':'J'; + + row += Draw.Area.MaxRows + 2; + return row; +} +#endif /* NO_LOWER */ + +#ifndef NO_FOOTER +void Layout_Footer(Layer *layer, CUINT row) +{ + size_t len; + CUINT col = 0; + + LayerDeclare( LAYOUT_FOOTER_TECH_TSC, RSZ(LAYOUT_FOOTER_TECH_TSC), + 0, row, hTech0 ); + + LayerDeclare( LAYOUT_FOOTER_VOLT_TEMP, RSZ(LAYOUT_FOOTER_VOLT_TEMP), + Draw.Size.width - 15, row, hVoltTemp0 ); + /* Pre-compute right-aligned position of Voltage & Temperature items */ + Draw.Area.Footer.VoltTemp.Hot[0] = hVoltTemp0.origin.col + 2; + + const struct { ASCII *code; ATTRIBUTE attr; } TSC[] = { + {RSC(LAYOUT_FOOTER_TSC_NONE).CODE(), + RSC(UI).ATTR()[UI_LAYOUT_FOOTER_TSC_NONE]}, + {RSC(LAYOUT_FOOTER_TSC_VAR).CODE(), + RSC(UI).ATTR()[UI_LAYOUT_FOOTER_TSC_VAR]}, + {RSC(LAYOUT_FOOTER_TSC_INV).CODE(), + RSC(UI).ATTR()[UI_LAYOUT_FOOTER_TSC_INV]} + }; + + hTech0.code[ 6] = TSC[RO(Shm)->Proc.Features.InvariantTSC].code[0]; + hTech0.code[ 7] = TSC[RO(Shm)->Proc.Features.InvariantTSC].code[1]; + hTech0.code[ 8] = TSC[RO(Shm)->Proc.Features.InvariantTSC].code[2]; + hTech0.code[ 9] = TSC[RO(Shm)->Proc.Features.InvariantTSC].code[3]; + hTech0.code[10] = TSC[RO(Shm)->Proc.Features.InvariantTSC].code[4]; + hTech0.code[11] = TSC[RO(Shm)->Proc.Features.InvariantTSC].code[5]; + hTech0.code[12] = TSC[RO(Shm)->Proc.Features.InvariantTSC].code[6]; + + hTech0.attr[ 6] = hTech0.attr[ 7] = hTech0.attr[ 8] = \ + hTech0.attr[ 9] = hTech0.attr[10] = hTech0.attr[11] = \ + hTech0.attr[12] = TSC[RO(Shm)->Proc.Features.InvariantTSC].attr; + + LayerCopyAt( layer, hTech0.origin.col, hTech0.origin.row, + hTech0.length, hTech0.attr, hTech0.code ); + + LayerCopyAt(layer, hVoltTemp0.origin.col, hVoltTemp0.origin.row, + hVoltTemp0.length, hVoltTemp0.attr, hVoltTemp0.code); + + LayerAt(layer, code, Draw.Area.Footer.VoltTemp.Hot[0] + 11, row) = \ + Setting.fahrCels ? 'F' : 'C'; + + row++; + + StrLenFormat(len, Buffer, MAX_UTS_LEN, "%s", + BITWISEAND(LOCKLESS, RO(Shm)->SysGate.Operation, 0x1) ? + RO(Shm)->SysGate.sysname + : (char *) RSC(SYSGATE).CODE()); + + LayerFillAt( layer, col, row, + len, Buffer, + RSC(UI).ATTR()[UI_LAYOUT_FOOTER_GATE]); + col += len; + + LayerAt(layer, attr, col, row) = RSC(UI).ATTR()[UI_LAYOUT_FOOTER_SPACE]; + LayerAt(layer, code, col, row) = 0x20; + + col++; + + LayerAt(layer, attr, col, row) = \ + RSC(UI).ATTR()[UI_LAYOUT_FOOTER_LEFT_BRACE]; + + LayerAt(layer, code, col, row) = '['; + + col++; + + if (BITWISEAND(LOCKLESS, RO(Shm)->SysGate.Operation, 0x1)) { + StrLenFormat(len, Buffer, 2+5+5+5+1, "%hu.%hu.%hu", + RO(Shm)->SysGate.kernel.version, + RO(Shm)->SysGate.kernel.major, + RO(Shm)->SysGate.kernel.minor); + + LayerFillAt( layer, col, row, + len, Buffer, + RSC(UI).ATTR()[UI_LAYOUT_FOOTER_KERNEL_VERSION] ); + + col += len; + } else { + LayerFillAt( layer, col, row, + 3, "OFF", + RSC(UI).ATTR()[UI_LAYOUT_FOOTER_UNMAP_GATE]); + col += 3; + } + LayerAt(layer, attr, col, row) = \ + RSC(UI).ATTR()[UI_LAYOUT_FOOTER_RIGHT_BRACE]; + + LayerAt(layer, code, col, row) = ']'; + + col++; + + LayerDeclare( LAYOUT_FOOTER_SYSTEM, RSZ(LAYOUT_FOOTER_SYSTEM), + (Draw.Size.width-RSZ(LAYOUT_FOOTER_SYSTEM)),row, hSys1); + + LayerCopyAt( layer, hSys1.origin.col, hSys1.origin.row, + hSys1.length, hSys1.attr, hSys1.code ); + /* Center the DMI string */ + if ((len = strlen(RO(Shm)->SMB.String[Draw.SmbIndex])) > 0) { + const CSINT mlt = (CSINT) (hSys1.origin.col - col - 1), + mrt = (CSINT) len, + can = CUMIN(mlt, mrt), + ctr = ((hSys1.origin.col + col) - can) / 2; + + LayerFillAt( layer, ctr, hSys1.origin.row, + can, ScrambleSMBIOS(Draw.SmbIndex, 4, '-'), + RSC(UI).ATTR()[UI_LAYOUT_FOOTER_DMI_STRING] ); + } + /* Pre-compute position of Tasks count & Memory usage */ + Draw.Area.Footer.TaskMem.Total = Draw.Size.width - 35; + Draw.Area.Footer.TaskMem.Free = Draw.Size.width - 22; + Draw.Area.Footer.TaskMem.Count = Draw.Size.width - 12; + /* Reset Tasks count & Memory usage */ + if (BITWISEAND(LOCKLESS, RO(Shm)->SysGate.Operation, 0x1)) { + PrintTaskMemory(layer, row, + RO(Shm)->SysGate.procCount, + RO(Shm)->SysGate.memInfo.freeram, + RO(Shm)->SysGate.memInfo.totalram); + } + /* Print the memory unit character */ + LayerAt(layer, code, + hSys1.origin.col + (RSZ(LAYOUT_FOOTER_SYSTEM) - 3), + hSys1.origin.row) = Draw.Unit.Memory == 0 ? 'K' + : Draw.Unit.Memory == 10 ? 'M' + : Draw.Unit.Memory == 20 ? 'G' : 0x20; +} +#endif /* NO_FOOTER */ + +void Layout_CPU_To_String(const unsigned int cpu) +{ + StrFormat(Buffer, 10+1, "%03u", cpu); +} + +void Layout_CPU_To_View(Layer *layer, const CUINT col, const CUINT row) +{ + LayerAt(layer, code, col + 0, row) = (ASCII) Buffer[0]; + LayerAt(layer, code, col + 1, row) = (ASCII) Buffer[1]; + LayerAt(layer, code, col + 2, row) = (ASCII) Buffer[2]; +} + +void Layout_BCLK_To_View(Layer *layer, const CUINT col, const CUINT row) +{ + LayerAt(layer, attr, col + 3, row) = \ + RSC(UI).ATTR()[UI_LAYOUT_BCLK_TO_VIEW]; + + LayerAt(layer, code, col + 3, row) = 0x20; +} + +#ifndef NO_UPPER +CUINT Draw_Frequency_Load( Layer *layer, CUINT row, + const unsigned int cpu, double ratio ) +{ /* Upper view area: draw bar chart iff load exists: */ + const double fPos = ((ratio > Ruler.Maximum ? Ruler.Maximum : ratio) + * Draw.Area.LoadWidth) / Ruler.Maximum; + const CUINT col = (CUINT) fPos; + UNUSED(cpu); + + if (col > 0) { + const ATTRIBUTE attr = ratio > Ruler.Median ? + RSC(UI).ATTR()[UI_DRAW_FREQUENCY_LOAD_HIGH] + : ratio > Ruler.Minimum ? + RSC(UI).ATTR()[UI_DRAW_FREQUENCY_LOAD_MEDIUM] + : RSC(UI).ATTR()[UI_DRAW_FREQUENCY_LOAD_LOW]; + + LayerFillAt(layer, LOAD_LEAD, row, col, hBar, attr); + } + if (BITVAL_CC(Draw.garbage, row)) { + struct { + const CUINT col, wth; + } garbage = { + .col = col + LOAD_LEAD, + .wth = Draw.Area.LoadWidth - col + }; + ClearGarbage( layer, attr, garbage.col, row, garbage.wth, + RSC(UI).ATTR()[UI_DRAW_FREQUENCY_LOAD_CLEAR].value ); + + ClearGarbage( layer, code, garbage.col, row, garbage.wth, 0x0 ); + } + if (!col) { + BITCLR_CC(LOCKLESS, Draw.garbage, row); + } else { + BITSET_CC(LOCKLESS, Draw.garbage, row); + } + return 0; +} + +CUINT Draw_Relative_Load(Layer *layer, const unsigned int cpu, CUINT row) +{ + struct FLIP_FLOP *CFlop = \ + &RO(Shm)->Cpu[cpu].FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + /* Draw the relative Core frequency ratio */ + return Draw_Frequency_Load(layer, row, cpu, CFlop->Relative.Ratio); +} + +CUINT Draw_Absolute_Load(Layer *layer, const unsigned int cpu, CUINT row) +{ + struct FLIP_FLOP *CFlop = \ + &RO(Shm)->Cpu[cpu].FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + /* Draw the absolute Core frequency ratio */ + return Draw_Frequency_Load(layer, row, cpu, CFlop->Absolute.Ratio.Perf); +} +#endif /* NO_UPPER */ + +#ifndef NO_LOWER +size_t Draw_Relative_Freq_Spaces( struct FLIP_FLOP *CFlop, + CPU_STRUCT *Cpu, + const unsigned int cpu ) +{ + size_t len; + UNUSED(Cpu); + UNUSED(cpu); + + StrLenFormat(len, Buffer, 17+8+6+7+7+7+7+7+7+11+1, + "%7.2f" " (" "%5.2f" ") " \ + "%6.2f" "%% " "%6.2f" "%% " "%6.2f" "%% " \ + "%6.2f" "%% " "%6.2f" "%% " "%6.2f" "%% " \ + "%.*s", + CFlop->Relative.Freq, + CFlop->Relative.Ratio, + 100.f * CFlop->State.Turbo, + 100.f * CFlop->State.C0, + 100.f * CFlop->State.C1, + 100.f * CFlop->State.C3, + 100.f * CFlop->State.C6, + 100.f * CFlop->State.C7, + 11, hSpace); + + return len; +} + +size_t Draw_Absolute_Freq_Spaces( struct FLIP_FLOP *CFlop, + CPU_STRUCT *Cpu, + const unsigned int cpu ) +{ + size_t len; + UNUSED(Cpu); + UNUSED(cpu); + + StrLenFormat(len, Buffer, 17+8+6+7+7+7+7+7+7+11+1, + "%7.2f" " (" "%5.2f" ") " \ + "%6.2f" "%% " "%6.2f" "%% " "%6.2f" "%% " \ + "%6.2f" "%% " "%6.2f" "%% " "%6.2f" "%% " \ + "%.*s", + CFlop->Absolute.Freq, + CFlop->Absolute.Ratio.Perf, + 100.f * CFlop->State.Turbo, + 100.f * CFlop->State.C0, + 100.f * CFlop->State.C1, + 100.f * CFlop->State.C3, + 100.f * CFlop->State.C6, + 100.f * CFlop->State.C7, + 11, hSpace); + + return len; +} + +size_t (*Draw_Freq_Spaces_Matrix[2])( struct FLIP_FLOP*, + CPU_STRUCT*, + const unsigned int ) = \ +{ + Draw_Relative_Freq_Spaces, + Draw_Absolute_Freq_Spaces +}; + +size_t Draw_Freq_Spaces(struct FLIP_FLOP *CFlop, + CPU_STRUCT *Cpu, + const unsigned int cpu) +{ + return Draw_Freq_Spaces_Matrix[Draw.Load](CFlop, Cpu, cpu); +} + +size_t Draw_Relative_Freq_Celsius( struct FLIP_FLOP *CFlop, + CPU_STRUCT *Cpu, + const unsigned int cpu ) +{ + size_t len; + UNUSED(cpu); + + StrLenFormat(len, Buffer, 19+8+6+7+7+7+7+7+7+10+10+10+1, + "%7.2f" " (" "%5.2f" ") " \ + "%6.2f" "%% " "%6.2f" "%% " "%6.2f" "%% " \ + "%6.2f" "%% " "%6.2f" "%% " "%6.2f" "%% " \ + "%-3u" "/" "%3u" "/" "%3u", + CFlop->Relative.Freq, + CFlop->Relative.Ratio, + 100.f * CFlop->State.Turbo, + 100.f * CFlop->State.C0, + 100.f * CFlop->State.C1, + 100.f * CFlop->State.C3, + 100.f * CFlop->State.C6, + 100.f * CFlop->State.C7, + Cpu->PowerThermal.Limit[SENSOR_LOWEST], + CFlop->Thermal.Temp, + Cpu->PowerThermal.Limit[SENSOR_HIGHEST]); + + return len; +} + +size_t Draw_Absolute_Freq_Celsius( struct FLIP_FLOP *CFlop, + CPU_STRUCT *Cpu, + const unsigned int cpu ) +{ + size_t len; + UNUSED(cpu); + + StrLenFormat(len, Buffer, 19+8+6+7+7+7+7+7+7+10+10+10+1, + "%7.2f" " (" "%5.2f" ") " \ + "%6.2f" "%% " "%6.2f" "%% " "%6.2f" "%% " \ + "%6.2f" "%% " "%6.2f" "%% " "%6.2f" "%% " \ + "%-3u" "/" "%3u" "/" "%3u", + CFlop->Absolute.Freq, + CFlop->Absolute.Ratio.Perf, + 100.f * CFlop->State.Turbo, + 100.f * CFlop->State.C0, + 100.f * CFlop->State.C1, + 100.f * CFlop->State.C3, + 100.f * CFlop->State.C6, + 100.f * CFlop->State.C7, + Cpu->PowerThermal.Limit[SENSOR_LOWEST], + CFlop->Thermal.Temp, + Cpu->PowerThermal.Limit[SENSOR_HIGHEST]); + + return len; +} + +size_t (*Draw_Freq_Celsius_Matrix[2])( struct FLIP_FLOP*, + CPU_STRUCT*, + const unsigned int ) = \ +{ + Draw_Relative_Freq_Celsius, + Draw_Absolute_Freq_Celsius +}; + +size_t Draw_Freq_Celsius( struct FLIP_FLOP *CFlop, + CPU_STRUCT *Cpu, + const unsigned int cpu ) +{ + return Draw_Freq_Celsius_Matrix[Draw.Load](CFlop, Cpu, cpu); +}; + +size_t Draw_Relative_Freq_Fahrenheit( struct FLIP_FLOP *CFlop, + CPU_STRUCT *Cpu, + const unsigned int cpu ) +{ + size_t len; + UNUSED(cpu); + + StrLenFormat(len, Buffer, 19+8+6+7+7+7+7+7+7+10+10+10+1, + "%7.2f" " (" "%5.2f" ") " \ + "%6.2f" "%% " "%6.2f" "%% " "%6.2f" "%% " \ + "%6.2f" "%% " "%6.2f" "%% " "%6.2f" "%% " \ + "%-3u" "/" "%3u" "/" "%3u", + CFlop->Relative.Freq, + CFlop->Relative.Ratio, + 100.f * CFlop->State.Turbo, + 100.f * CFlop->State.C0, + 100.f * CFlop->State.C1, + 100.f * CFlop->State.C3, + 100.f * CFlop->State.C6, + 100.f * CFlop->State.C7, + Cels2Fahr(Cpu->PowerThermal.Limit[SENSOR_LOWEST]), + Cels2Fahr(CFlop->Thermal.Temp), + Cels2Fahr(Cpu->PowerThermal.Limit[SENSOR_HIGHEST])); + + return len; +} + +size_t Draw_Absolute_Freq_Fahrenheit( struct FLIP_FLOP *CFlop, + CPU_STRUCT *Cpu, + const unsigned int cpu ) +{ + size_t len; + UNUSED(cpu); + + StrLenFormat(len, Buffer, 19+8+6+7+7+7+7+7+7+10+10+10+1, + "%7.2f" " (" "%5.2f" ") " \ + "%6.2f" "%% " "%6.2f" "%% " "%6.2f" "%% " \ + "%6.2f" "%% " "%6.2f" "%% " "%6.2f" "%% " \ + "%-3u" "/" "%3u" "/" "%3u", + CFlop->Absolute.Freq, + CFlop->Absolute.Ratio.Perf, + 100.f * CFlop->State.Turbo, + 100.f * CFlop->State.C0, + 100.f * CFlop->State.C1, + 100.f * CFlop->State.C3, + 100.f * CFlop->State.C6, + 100.f * CFlop->State.C7, + Cels2Fahr(Cpu->PowerThermal.Limit[SENSOR_LOWEST]), + Cels2Fahr(CFlop->Thermal.Temp), + Cels2Fahr(Cpu->PowerThermal.Limit[SENSOR_HIGHEST])); + + return len; +} + +size_t (*Draw_Freq_Fahrenheit_Matrix[2])( struct FLIP_FLOP*, + CPU_STRUCT*, + const unsigned int ) = \ +{ + Draw_Relative_Freq_Fahrenheit, + Draw_Absolute_Freq_Fahrenheit +}; + +size_t Draw_Freq_Fahrenheit( struct FLIP_FLOP *CFlop, + CPU_STRUCT *Cpu, + const unsigned int cpu ) +{ + return Draw_Freq_Fahrenheit_Matrix[Draw.Load](CFlop, Cpu, cpu); +}; + +size_t Draw_Freq_Celsius_PerCore( struct FLIP_FLOP *CFlop, + CPU_STRUCT *Cpu, + const unsigned int cpu ) +{ + UNUSED(Cpu); + + if ((RO(Shm)->Cpu[cpu].Topology.ThreadID == 0) + || (RO(Shm)->Cpu[cpu].Topology.ThreadID == -1)) { + return Draw_Freq_Celsius(CFlop, &RO(Shm)->Cpu[cpu], cpu); + } else { + return Draw_Freq_Spaces(CFlop, NULL, cpu); + } +} + +size_t Draw_Freq_Fahrenheit_PerCore( struct FLIP_FLOP *CFlop, + CPU_STRUCT *Cpu, + const unsigned int cpu ) +{ + UNUSED(Cpu); + + if ((RO(Shm)->Cpu[cpu].Topology.ThreadID == 0) + || (RO(Shm)->Cpu[cpu].Topology.ThreadID == -1)) { + return Draw_Freq_Fahrenheit(CFlop, &RO(Shm)->Cpu[cpu], cpu); + } else { + return Draw_Freq_Spaces(CFlop, NULL, cpu); + } +} + +size_t Draw_Freq_Celsius_PerPkg( struct FLIP_FLOP *CFlop, + CPU_STRUCT *Cpu, + const unsigned int cpu ) +{ + UNUSED(Cpu); + + if (cpu == RO(Shm)->Proc.Service.Core) { + return Draw_Freq_Celsius(CFlop, &RO(Shm)->Cpu[cpu], cpu); + } else { + return Draw_Freq_Spaces(CFlop, NULL, cpu); + } +} + +size_t Draw_Freq_Fahrenheit_PerPkg( struct FLIP_FLOP *CFlop, + CPU_STRUCT *Cpu, + const unsigned int cpu ) +{ + UNUSED(Cpu); + + if (cpu == RO(Shm)->Proc.Service.Core) { + return Draw_Freq_Fahrenheit(CFlop, &RO(Shm)->Cpu[cpu], cpu); + } else { + return Draw_Freq_Spaces(CFlop, NULL, cpu); + } +} + +size_t (*Draw_Freq_Temp_Matrix[4][2])( struct FLIP_FLOP*, + CPU_STRUCT*, + const unsigned int) = \ +{ + [FORMULA_SCOPE_NONE] = { + [0] = Draw_Freq_Spaces, + [1] = Draw_Freq_Spaces + }, + [FORMULA_SCOPE_SMT ] = { + [0] = Draw_Freq_Celsius, + [1] = Draw_Freq_Fahrenheit + }, + [FORMULA_SCOPE_CORE] = { + [0] = Draw_Freq_Celsius_PerCore, + [1] = Draw_Freq_Fahrenheit_PerCore + }, + [FORMULA_SCOPE_PKG ] = { + [0] = Draw_Freq_Celsius_PerPkg, + [1] = Draw_Freq_Fahrenheit_PerPkg + } +}; + +CUINT Draw_Monitor_Frequency(Layer *layer, const unsigned int cpu, CUINT row) +{ + struct FLIP_FLOP *CFlop = \ + &RO(Shm)->Cpu[cpu].FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + + const enum FORMULA_SCOPE + thermalScope = SCOPE_OF_FORMULA(RO(Shm)->Proc.thermalFormula); + + size_t len = Draw_Freq_Temp_Matrix[thermalScope][Setting.fahrCels]( + CFlop, &RO(Shm)->Cpu[cpu], cpu + ); + memcpy(&LayerAt(layer, code, LOAD_LEAD, row), Buffer, len); + + ATTRIBUTE warning = RSC(UI).ATTR()[UI_DRAW_MONITOR_FREQUENCY_NOMINAL]; + + if (CFlop->Thermal.Temp <= RO(Shm)->Cpu[ + cpu + ].PowerThermal.Limit[SENSOR_LOWEST]) + { + warning = RSC(UI).ATTR()[UI_DRAW_MONITOR_FREQUENCY_LOW]; + } else { + if (CFlop->Thermal.Temp >= RO(Shm)->Cpu[ + cpu + ].PowerThermal.Limit[SENSOR_HIGHEST]) + warning = RSC(UI).ATTR()[UI_DRAW_MONITOR_FREQUENCY_HIGH]; + } + if (CFlop->Thermal.Events[eSTS] & STATUS_EVENT_FILTER) + { + warning = RSC(UI).ATTR()[UI_DRAW_MONITOR_FREQUENCY_HOT]; + } + LayerAt(layer, attr, (LOAD_LEAD + 69), row) = \ + LayerAt(layer, attr, (LOAD_LEAD + 70), row) = \ + LayerAt(layer, attr, (LOAD_LEAD + 71), row) = warning; + + return 0; +} + +CUINT Draw_Monitor_Instructions(Layer *layer, const unsigned int cpu, CUINT row) +{ + struct FLIP_FLOP *CFlop = \ + &RO(Shm)->Cpu[cpu].FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + + size_t len; + StrLenFormat(len, Buffer, 6+18+18+18+20+1, + "%17.6f" "/s" \ + "%17.6f" "/c" \ + "%17.6f" "/i" \ + "%18llu", + CFlop->State.IPS, + CFlop->State.IPC, + CFlop->State.CPI, + CFlop->Delta.INST); + + memcpy(&LayerAt(layer, code, LOAD_LEAD, row), Buffer, len); + + return 0; +} + +CUINT Draw_Monitor_Cycles(Layer *layer, const unsigned int cpu, CUINT row) +{ + struct FLIP_FLOP *CFlop = \ + &RO(Shm)->Cpu[cpu].FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + + size_t len; + StrLenFormat(len, Buffer, 20+20+20+20+1, + "%18llu%18llu%18llu%18llu", + CFlop->Delta.C0.UCC, + CFlop->Delta.C0.URC, + CFlop->Delta.C1, + CFlop->Delta.TSC); + + memcpy(&LayerAt(layer, code, LOAD_LEAD, row), Buffer, len); + + return 0; +} + +CUINT Draw_Monitor_CStates(Layer *layer, const unsigned int cpu, CUINT row) +{ + struct FLIP_FLOP *CFlop = \ + &RO(Shm)->Cpu[cpu].FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + + size_t len; + StrLenFormat(len, Buffer, 20+20+20+20+1, + "%18llu%18llu%18llu%18llu", + CFlop->Delta.C1, + CFlop->Delta.C3, + CFlop->Delta.C6, + CFlop->Delta.C7); + + memcpy(&LayerAt(layer, code, LOAD_LEAD, row), Buffer, len); + + return 0; +} + +CUINT Draw_Monitor_Package(Layer *layer, const unsigned int cpu, CUINT row) +{ + UNUSED(layer); + UNUSED(cpu); + UNUSED(row); + + return 0; +} + +size_t Draw_Monitor_Tasks_Relative_Freq(struct FLIP_FLOP *CFlop) +{ + size_t len; + StrLenFormat(len, Buffer, 8+1, "%7.2f", CFlop->Relative.Freq); + return len; +} + +size_t Draw_Monitor_Tasks_Absolute_Freq(struct FLIP_FLOP *CFlop) +{ + size_t len; + StrLenFormat(len, Buffer, 8+1, "%7.2f", CFlop->Absolute.Freq); + return len; +} + +size_t (*Draw_Monitor_Tasks_Matrix[2])(struct FLIP_FLOP *CFlop) = \ +{ + Draw_Monitor_Tasks_Relative_Freq, + Draw_Monitor_Tasks_Absolute_Freq +}; + +CUINT Draw_Monitor_Tasks(Layer *layer, const unsigned int cpu, CUINT row) +{ + struct FLIP_FLOP *CFlop = \ + &RO(Shm)->Cpu[cpu].FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + + size_t len = Draw_Monitor_Tasks_Matrix[Draw.Load](CFlop); + + memcpy(&LayerAt(layer, code, LOAD_LEAD, row), Buffer, len); + cTask[cpu].col = LOAD_LEAD + 8; + + return 0; +} + +CUINT Draw_Monitor_Interrupts(Layer *layer, const unsigned int cpu, CUINT row) +{ + struct FLIP_FLOP *CFlop = \ + &RO(Shm)->Cpu[cpu].FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + size_t len; + + StrLenFormat(len, Buffer, 10+1, "%10u", CFlop->Counter.SMI); + memcpy(&LayerAt(layer, code, LOAD_LEAD, row), Buffer, len); + + if (BITVAL(RO(Shm)->Registration.NMI, BIT_NMI_LOCAL) == 1) { + StrLenFormat(len, Buffer, 10+1, "%10u", CFlop->Counter.NMI.LOCAL); + memcpy(&LayerAt(layer,code,(LOAD_LEAD + 24),row), Buffer, len); + } else { + memcpy(&LayerAt(layer,code,(LOAD_LEAD + 24),row), hSpace, 10); + } + if (BITVAL(RO(Shm)->Registration.NMI, BIT_NMI_UNKNOWN) == 1) { + StrLenFormat(len, Buffer, 10+1,"%10u",CFlop->Counter.NMI.UNKNOWN); + memcpy(&LayerAt(layer,code,(LOAD_LEAD + 34),row), Buffer, len); + } else { + memcpy(&LayerAt(layer,code,(LOAD_LEAD + 34),row), hSpace, 10); + } + if (BITVAL(RO(Shm)->Registration.NMI, BIT_NMI_SERR) == 1) { + StrLenFormat(len, Buffer, 10+1,"%10u",CFlop->Counter.NMI.PCISERR); + memcpy(&LayerAt(layer,code,(LOAD_LEAD + 44),row), Buffer, len); + } else { + memcpy(&LayerAt(layer,code,(LOAD_LEAD + 44),row), hSpace, 10); + } + if (BITVAL(RO(Shm)->Registration.NMI, BIT_NMI_IO_CHECK) == 1) { + StrLenFormat(len, Buffer, 10+1,"%10u",CFlop->Counter.NMI.IOCHECK); + memcpy(&LayerAt(layer,code,(LOAD_LEAD + 54),row), Buffer, len); + } else { + memcpy(&LayerAt(layer,code,(LOAD_LEAD + 54),row), hSpace, 10); + } + return 0; +} + +size_t Draw_Sensors_V0_T0_P0(Layer *layer, const unsigned int cpu, CUINT row) +{ + struct FLIP_FLOP *CFlop = \ + &RO(Shm)->Cpu[cpu].FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + size_t len; + UNUSED(layer); + UNUSED(row); + + StrLenFormat(len, Buffer, 80+1, + "%7.2f%.*s", + Draw.Load ? CFlop->Absolute.Freq:CFlop->Relative.Freq, + 69, hSpace); + return len; +} + +size_t Draw_Sensors_V0_T0_P1(Layer *layer, const unsigned int cpu, CUINT row) +{ + struct FLIP_FLOP *CFlop = \ + &RO(Shm)->Cpu[cpu].FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + size_t len; + UNUSED(layer); + UNUSED(row); + + StrLenFormat(len, Buffer, 80+1, + "%7.2f%.*s" \ + "%8.4f\x20\x20\x20\x20\x20\x20" \ + "%8.4f%.*s", + Draw.Load ? CFlop->Absolute.Freq:CFlop->Relative.Freq, + 26, hSpace, + CFlop->State.Energy, + CFlop->State.Power, + 21, hSpace); + return len; +} + +size_t Draw_Sensors_V0_T0_P2(Layer *layer, const unsigned int cpu, CUINT row) +{ + if ((RO(Shm)->Cpu[cpu].Topology.ThreadID == 0) + || (RO(Shm)->Cpu[cpu].Topology.ThreadID == -1)) { + return Draw_Sensors_V0_T0_P1(layer, cpu, row); + } else { + return Draw_Sensors_V0_T0_P0(layer, cpu, row); + } +} + +size_t Draw_Sensors_V0_T0_P3(Layer *layer, const unsigned int cpu, CUINT row) +{ + if (cpu == RO(Shm)->Proc.Service.Core) { + return Draw_Sensors_V0_T0_P1(layer, cpu, row); + } else { + return Draw_Sensors_V0_T0_P0(layer, cpu, row); + } +} + +size_t Draw_Sensors_V0_T1_P0(Layer *layer, const unsigned int cpu, CUINT row) +{ + struct FLIP_FLOP *CFlop = \ + &RO(Shm)->Cpu[cpu].FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + size_t len; + UNUSED(layer); + UNUSED(row); + + StrLenFormat(len, Buffer, 80+1, + "%7.2f%.*s" \ + "%3u%.*s", + Draw.Load ? CFlop->Absolute.Freq:CFlop->Relative.Freq, + 17, hSpace, + Setting.fahrCels ? Cels2Fahr(CFlop->Thermal.Temp) + : CFlop->Thermal.Temp, + 49, hSpace); + return len; +} + +size_t Draw_Sensors_V0_T1_P1(Layer *layer, const unsigned int cpu, CUINT row) +{ + struct FLIP_FLOP *CFlop = \ + &RO(Shm)->Cpu[cpu].FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + size_t len; + UNUSED(layer); + UNUSED(row); + + StrLenFormat(len, Buffer, 80+1, + "%7.2f%.*s" \ + "%3u\x20\x20\x20\x20\x20\x20" \ + "%8.4f\x20\x20\x20\x20\x20\x20" \ + "%8.4f%.*s", + Draw.Load ? CFlop->Absolute.Freq:CFlop->Relative.Freq, + 17, hSpace, + Setting.fahrCels ? Cels2Fahr(CFlop->Thermal.Temp) + : CFlop->Thermal.Temp, + CFlop->State.Energy, + CFlop->State.Power, + 21, hSpace); + return len; +} + +size_t Draw_Sensors_V0_T1_P2(Layer *layer, const unsigned int cpu, CUINT row) +{ + if ((RO(Shm)->Cpu[cpu].Topology.ThreadID == 0) + || (RO(Shm)->Cpu[cpu].Topology.ThreadID == -1)) { + return Draw_Sensors_V0_T1_P1(layer, cpu, row); + } else { + return Draw_Sensors_V0_T1_P0(layer, cpu, row); + } +} + +size_t Draw_Sensors_V0_T1_P3(Layer *layer, const unsigned int cpu, CUINT row) +{ + if (cpu == RO(Shm)->Proc.Service.Core) { + return Draw_Sensors_V0_T1_P1(layer, cpu, row); + } else { + return Draw_Sensors_V0_T1_P0(layer, cpu, row); + } +} + +size_t Draw_Sensors_V0_T2_P0(Layer *layer, const unsigned int cpu, CUINT row) +{ + if ((RO(Shm)->Cpu[cpu].Topology.ThreadID == 0) + || (RO(Shm)->Cpu[cpu].Topology.ThreadID == -1)) { + return Draw_Sensors_V0_T1_P0(layer, cpu, row); + } else { + return Draw_Sensors_V0_T0_P0(layer, cpu, row); + } +} + +size_t Draw_Sensors_V0_T2_P1(Layer *layer, const unsigned int cpu, CUINT row) +{ + if ((RO(Shm)->Cpu[cpu].Topology.ThreadID == 0) + || (RO(Shm)->Cpu[cpu].Topology.ThreadID == -1)) { + return Draw_Sensors_V0_T1_P1(layer, cpu, row); + } else { + return Draw_Sensors_V0_T0_P1(layer, cpu, row); + } +} + +size_t Draw_Sensors_V0_T2_P2(Layer *layer, const unsigned int cpu, CUINT row) +{ + if ((RO(Shm)->Cpu[cpu].Topology.ThreadID == 0) + || (RO(Shm)->Cpu[cpu].Topology.ThreadID == -1)) { + return Draw_Sensors_V0_T1_P1(layer, cpu, row); + } else { + return Draw_Sensors_V0_T0_P0(layer, cpu, row); + } +} + +size_t Draw_Sensors_V0_T2_P3(Layer *layer, const unsigned int cpu, CUINT row) +{ + if ((RO(Shm)->Cpu[cpu].Topology.ThreadID == 0) + || (RO(Shm)->Cpu[cpu].Topology.ThreadID == -1)) { + return Draw_Sensors_V0_T1_P3(layer, cpu, row); + } else { + return Draw_Sensors_V0_T0_P0(layer, cpu, row); + } +} + +size_t Draw_Sensors_V0_T3_P0(Layer *layer, const unsigned int cpu, CUINT row) +{ + if (cpu == RO(Shm)->Proc.Service.Core) { + return Draw_Sensors_V0_T1_P0(layer, cpu, row); + } else { + return Draw_Sensors_V0_T0_P0(layer, cpu, row); + } +} + +size_t Draw_Sensors_V0_T3_P1(Layer *layer, const unsigned int cpu, CUINT row) +{ + if (cpu == RO(Shm)->Proc.Service.Core) { + return Draw_Sensors_V0_T1_P1(layer, cpu, row); + } else { + return Draw_Sensors_V0_T0_P1(layer, cpu, row); + } +} + +size_t Draw_Sensors_V0_T3_P2(Layer *layer, const unsigned int cpu, CUINT row) +{ + if (cpu == RO(Shm)->Proc.Service.Core) { + return Draw_Sensors_V0_T1_P2(layer, cpu, row); + } else { + return Draw_Sensors_V0_T0_P2(layer, cpu, row); + } +} + +size_t Draw_Sensors_V0_T3_P3(Layer *layer, const unsigned int cpu, CUINT row) +{ + if (cpu == RO(Shm)->Proc.Service.Core) { + return Draw_Sensors_V0_T1_P3(layer, cpu, row); + } else { + return Draw_Sensors_V0_T0_P3(layer, cpu, row); + } +} + +size_t Draw_Sensors_V1_T0_P0(Layer *layer, const unsigned int cpu, CUINT row) +{ + struct FLIP_FLOP *CFlop = \ + &RO(Shm)->Cpu[cpu].FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + size_t len; + UNUSED(layer); + UNUSED(row); + + StrLenFormat(len, Buffer, 80+1, + "%7.2f\x20\x20\x20\x20\x20\x20\x20" \ + "%5.4f%.*s", + Draw.Load ? CFlop->Absolute.Freq:CFlop->Relative.Freq, + CFlop->Voltage.Vcore, + 56, hSpace); + return len; +} + +size_t Draw_Sensors_V1_T0_P1(Layer *layer, const unsigned int cpu, CUINT row) +{ + struct FLIP_FLOP *CFlop = \ + &RO(Shm)->Cpu[cpu].FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + size_t len; + UNUSED(layer); + UNUSED(row); + + StrLenFormat(len, Buffer, 80+1, + "%7.2f\x20\x20\x20\x20\x20\x20\x20" \ + "%5.4f\x20\x20\x20\x20" \ + "\x20\x20\x20\x20\x20\x20\x20\x20\x20" \ + "%8.4f\x20\x20\x20\x20\x20\x20" \ + "%8.4f%.*s", + Draw.Load ? CFlop->Absolute.Freq:CFlop->Relative.Freq, + CFlop->Voltage.Vcore, + CFlop->State.Energy, + CFlop->State.Power, + 21, hSpace); + return len; +} + +size_t Draw_Sensors_V1_T0_P2(Layer *layer, const unsigned int cpu, CUINT row) +{ + if ((RO(Shm)->Cpu[cpu].Topology.ThreadID == 0) + || (RO(Shm)->Cpu[cpu].Topology.ThreadID == -1)) { + return Draw_Sensors_V1_T0_P1(layer, cpu, row); + } else { + return Draw_Sensors_V1_T0_P0(layer, cpu, row); + } +} + +size_t Draw_Sensors_V1_T0_P3(Layer *layer, const unsigned int cpu, CUINT row) +{ + if (cpu == RO(Shm)->Proc.Service.Core) { + return Draw_Sensors_V1_T0_P1(layer, cpu, row); + } else { + return Draw_Sensors_V1_T0_P0(layer, cpu, row); + } +} + +size_t Draw_Sensors_V1_T1_P0(Layer *layer, const unsigned int cpu, CUINT row) +{ + struct FLIP_FLOP *CFlop = \ + &RO(Shm)->Cpu[cpu].FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + size_t len; + UNUSED(layer); + UNUSED(row); + + StrLenFormat(len, Buffer, 80+1, + "%7.2f\x20\x20\x20\x20\x20\x20\x20" \ + "%5.4f\x20\x20\x20\x20" \ + "%3u%.*s", \ + Draw.Load ? CFlop->Absolute.Freq:CFlop->Relative.Freq, + CFlop->Voltage.Vcore, + Setting.fahrCels ? Cels2Fahr(CFlop->Thermal.Temp) + : CFlop->Thermal.Temp, + 49, hSpace); + return len; +} + +size_t Draw_Sensors_V1_T1_P1(Layer *layer, const unsigned int cpu, CUINT row) +{ + struct FLIP_FLOP *CFlop = \ + &RO(Shm)->Cpu[cpu].FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + size_t len; + UNUSED(layer); + UNUSED(row); + + StrLenFormat(len, Buffer, 80+1, + "%7.2f\x20\x20\x20\x20\x20\x20\x20" \ + "%5.4f\x20\x20\x20\x20" \ + "%3u\x20\x20\x20\x20\x20\x20" \ + "%8.4f\x20\x20\x20\x20\x20\x20" \ + "%8.4f%.*s", + Draw.Load ? CFlop->Absolute.Freq:CFlop->Relative.Freq, + CFlop->Voltage.Vcore, + Setting.fahrCels ? Cels2Fahr(CFlop->Thermal.Temp) + : CFlop->Thermal.Temp, + CFlop->State.Energy, + CFlop->State.Power, + 21, hSpace); + return len; +} + +size_t Draw_Sensors_V1_T1_P2(Layer *layer, const unsigned int cpu, CUINT row) +{ + if ((RO(Shm)->Cpu[cpu].Topology.ThreadID == 0) + || (RO(Shm)->Cpu[cpu].Topology.ThreadID == -1)) { + return Draw_Sensors_V1_T1_P1(layer, cpu, row); + } else { + return Draw_Sensors_V1_T1_P0(layer, cpu, row); + } +} + +size_t Draw_Sensors_V1_T1_P3(Layer *layer, const unsigned int cpu, CUINT row) +{ + if (cpu == RO(Shm)->Proc.Service.Core) { + return Draw_Sensors_V1_T1_P1(layer, cpu, row); + } else { + return Draw_Sensors_V1_T1_P0(layer, cpu, row); + } +} + +size_t Draw_Sensors_V1_T2_P0(Layer *layer, const unsigned int cpu, CUINT row) +{ + if ((RO(Shm)->Cpu[cpu].Topology.ThreadID == 0) + || (RO(Shm)->Cpu[cpu].Topology.ThreadID == -1)) { + return Draw_Sensors_V1_T1_P0(layer, cpu, row); + } else { + return Draw_Sensors_V1_T0_P0(layer, cpu, row); + } +} + +size_t Draw_Sensors_V1_T2_P1(Layer *layer, const unsigned int cpu, CUINT row) +{ + if ((RO(Shm)->Cpu[cpu].Topology.ThreadID == 0) + || (RO(Shm)->Cpu[cpu].Topology.ThreadID == -1)) { + return Draw_Sensors_V1_T1_P1(layer, cpu, row); + } else { + return Draw_Sensors_V1_T0_P1(layer, cpu, row); + } +} + +size_t Draw_Sensors_V1_T2_P2(Layer *layer, const unsigned int cpu, CUINT row) +{ + if ((RO(Shm)->Cpu[cpu].Topology.ThreadID == 0) + || (RO(Shm)->Cpu[cpu].Topology.ThreadID == -1)) { + return Draw_Sensors_V1_T1_P2(layer, cpu, row); + } else { + return Draw_Sensors_V1_T0_P2(layer, cpu, row); + } +} + +size_t Draw_Sensors_V1_T2_P3(Layer *layer, const unsigned int cpu, CUINT row) +{ + if ((RO(Shm)->Cpu[cpu].Topology.ThreadID == 0) + || (RO(Shm)->Cpu[cpu].Topology.ThreadID == -1)) { + return Draw_Sensors_V1_T1_P3(layer, cpu, row); + } else { + return Draw_Sensors_V1_T0_P3(layer, cpu, row); + } +} + +size_t Draw_Sensors_V1_T3_P0(Layer *layer, const unsigned int cpu, CUINT row) +{ + if (cpu == RO(Shm)->Proc.Service.Core) { + return Draw_Sensors_V1_T1_P0(layer, cpu, row); + } else { + return Draw_Sensors_V1_T0_P0(layer, cpu, row); + } +} + +size_t Draw_Sensors_V1_T3_P1(Layer *layer, const unsigned int cpu, CUINT row) +{ + if (cpu == RO(Shm)->Proc.Service.Core) { + return Draw_Sensors_V1_T1_P1(layer, cpu, row); + } else { + return Draw_Sensors_V1_T0_P1(layer, cpu, row); + } +} + +size_t Draw_Sensors_V1_T3_P2(Layer *layer, const unsigned int cpu, CUINT row) +{ + if (cpu == RO(Shm)->Proc.Service.Core) { + return Draw_Sensors_V1_T1_P2(layer, cpu, row); + } else { + return Draw_Sensors_V1_T0_P2(layer, cpu, row); + } +} + +size_t Draw_Sensors_V1_T3_P3(Layer *layer, const unsigned int cpu, CUINT row) +{ + if (cpu == RO(Shm)->Proc.Service.Core) { + return Draw_Sensors_V1_T1_P3(layer, cpu, row); + } else { + return Draw_Sensors_V1_T0_P3(layer, cpu, row); + } +} + +size_t Draw_Sensors_V2_T0_P0(Layer *layer, const unsigned int cpu, CUINT row) +{ + if ((RO(Shm)->Cpu[cpu].Topology.ThreadID == 0) + || (RO(Shm)->Cpu[cpu].Topology.ThreadID == -1)) { + return Draw_Sensors_V1_T0_P0(layer, cpu, row); + } else { + return Draw_Sensors_V0_T0_P0(layer, cpu, row); + } +} + +size_t Draw_Sensors_V2_T0_P1(Layer *layer, const unsigned int cpu, CUINT row) +{ + if ((RO(Shm)->Cpu[cpu].Topology.ThreadID == 0) + || (RO(Shm)->Cpu[cpu].Topology.ThreadID == -1)) { + return Draw_Sensors_V1_T0_P1(layer, cpu, row); + } else { + return Draw_Sensors_V0_T0_P1(layer, cpu, row); + } +} + +size_t Draw_Sensors_V2_T0_P2(Layer *layer, const unsigned int cpu, CUINT row) +{ + if ((RO(Shm)->Cpu[cpu].Topology.ThreadID == 0) + || (RO(Shm)->Cpu[cpu].Topology.ThreadID == -1)) { + return Draw_Sensors_V1_T0_P2(layer, cpu, row); + } else { + return Draw_Sensors_V0_T0_P2(layer, cpu, row); + } +} + +size_t Draw_Sensors_V2_T0_P3(Layer *layer, const unsigned int cpu, CUINT row) +{ + if ((RO(Shm)->Cpu[cpu].Topology.ThreadID == 0) + || (RO(Shm)->Cpu[cpu].Topology.ThreadID == -1)) { + return Draw_Sensors_V1_T0_P3(layer, cpu, row); + } else { + return Draw_Sensors_V0_T0_P3(layer, cpu, row); + } +} + +size_t Draw_Sensors_V2_T1_P0(Layer *layer, const unsigned int cpu, CUINT row) +{ + if ((RO(Shm)->Cpu[cpu].Topology.ThreadID == 0) + || (RO(Shm)->Cpu[cpu].Topology.ThreadID == -1)) { + return Draw_Sensors_V1_T1_P0(layer, cpu, row); + } else { + return Draw_Sensors_V0_T1_P0(layer, cpu, row); + } +} + +size_t Draw_Sensors_V2_T1_P1(Layer *layer, const unsigned int cpu, CUINT row) +{ + if ((RO(Shm)->Cpu[cpu].Topology.ThreadID == 0) + || (RO(Shm)->Cpu[cpu].Topology.ThreadID == -1)) { + return Draw_Sensors_V1_T1_P1(layer, cpu, row); + } else { + return Draw_Sensors_V0_T1_P1(layer, cpu, row); + } +} + +size_t Draw_Sensors_V2_T1_P2(Layer *layer, const unsigned int cpu, CUINT row) +{ + if ((RO(Shm)->Cpu[cpu].Topology.ThreadID == 0) + || (RO(Shm)->Cpu[cpu].Topology.ThreadID == -1)) { + return Draw_Sensors_V1_T1_P2(layer, cpu, row); + } else { + return Draw_Sensors_V0_T1_P2(layer, cpu, row); + } +} + +size_t Draw_Sensors_V2_T1_P3(Layer *layer, const unsigned int cpu, CUINT row) +{ + if ((RO(Shm)->Cpu[cpu].Topology.ThreadID == 0) + || (RO(Shm)->Cpu[cpu].Topology.ThreadID == -1)) { + return Draw_Sensors_V1_T1_P3(layer, cpu, row); + } else { + return Draw_Sensors_V0_T1_P3(layer, cpu, row); + } +} + +size_t Draw_Sensors_V2_T2_P0(Layer *layer, const unsigned int cpu, CUINT row) +{ + if ((RO(Shm)->Cpu[cpu].Topology.ThreadID == 0) + || (RO(Shm)->Cpu[cpu].Topology.ThreadID == -1)) { + return Draw_Sensors_V1_T2_P0(layer, cpu, row); + } else { + return Draw_Sensors_V0_T2_P0(layer, cpu, row); + } +} + +size_t Draw_Sensors_V2_T2_P1(Layer *layer, const unsigned int cpu, CUINT row) +{ + if ((RO(Shm)->Cpu[cpu].Topology.ThreadID == 0) + || (RO(Shm)->Cpu[cpu].Topology.ThreadID == -1)) { + return Draw_Sensors_V1_T2_P1(layer, cpu, row); + } else { + return Draw_Sensors_V0_T2_P1(layer, cpu, row); + } +} + +size_t Draw_Sensors_V2_T2_P2(Layer *layer, const unsigned int cpu, CUINT row) +{ + if ((RO(Shm)->Cpu[cpu].Topology.ThreadID == 0) + || (RO(Shm)->Cpu[cpu].Topology.ThreadID == -1)) { + return Draw_Sensors_V1_T2_P2(layer, cpu, row); + } else { + return Draw_Sensors_V0_T2_P2(layer, cpu, row); + } +} + +size_t Draw_Sensors_V2_T2_P3(Layer *layer, const unsigned int cpu, CUINT row) +{ + if ((RO(Shm)->Cpu[cpu].Topology.ThreadID == 0) + || (RO(Shm)->Cpu[cpu].Topology.ThreadID == -1)) { + return Draw_Sensors_V1_T2_P3(layer, cpu, row); + } else { + return Draw_Sensors_V0_T2_P3(layer, cpu, row); + } +} + +size_t Draw_Sensors_V2_T3_P0(Layer *layer, const unsigned int cpu, CUINT row) +{ + if ((RO(Shm)->Cpu[cpu].Topology.ThreadID == 0) + || (RO(Shm)->Cpu[cpu].Topology.ThreadID == -1)) { + return Draw_Sensors_V1_T3_P0(layer, cpu, row); + } else { + return Draw_Sensors_V0_T3_P0(layer, cpu, row); + } +} + +size_t Draw_Sensors_V2_T3_P1(Layer *layer, const unsigned int cpu, CUINT row) +{ + if ((RO(Shm)->Cpu[cpu].Topology.ThreadID == 0) + || (RO(Shm)->Cpu[cpu].Topology.ThreadID == -1)) { + return Draw_Sensors_V1_T3_P1(layer, cpu, row); + } else { + return Draw_Sensors_V0_T3_P1(layer, cpu, row); + } +} + +size_t Draw_Sensors_V2_T3_P2(Layer *layer, const unsigned int cpu, CUINT row) +{ + if ((RO(Shm)->Cpu[cpu].Topology.ThreadID == 0) + || (RO(Shm)->Cpu[cpu].Topology.ThreadID == -1)) { + return Draw_Sensors_V1_T3_P2(layer, cpu, row); + } else { + return Draw_Sensors_V0_T3_P2(layer, cpu, row); + } +} + +size_t Draw_Sensors_V2_T3_P3(Layer *layer, const unsigned int cpu, CUINT row) +{ + if ((RO(Shm)->Cpu[cpu].Topology.ThreadID == 0) + || (RO(Shm)->Cpu[cpu].Topology.ThreadID == -1)) { + return Draw_Sensors_V1_T3_P3(layer, cpu, row); + } else { + return Draw_Sensors_V0_T3_P3(layer, cpu, row); + } +} + +size_t Draw_Sensors_V3_T0_P0(Layer *layer, const unsigned int cpu, CUINT row) +{ + if (cpu == RO(Shm)->Proc.Service.Core) { + return Draw_Sensors_V1_T0_P0(layer, cpu, row); + } else { + return Draw_Sensors_V0_T0_P0(layer, cpu, row); + } +} + +size_t Draw_Sensors_V3_T0_P1(Layer *layer, const unsigned int cpu, CUINT row) +{ + if (cpu == RO(Shm)->Proc.Service.Core) { + return Draw_Sensors_V1_T0_P1(layer, cpu, row); + } else { + return Draw_Sensors_V0_T0_P1(layer, cpu, row); + } +} + +size_t Draw_Sensors_V3_T0_P2(Layer *layer, const unsigned int cpu, CUINT row) +{ + if (cpu == RO(Shm)->Proc.Service.Core) { + return Draw_Sensors_V1_T0_P2(layer, cpu, row); + } else { + return Draw_Sensors_V0_T0_P2(layer, cpu, row); + } +} + +size_t Draw_Sensors_V3_T0_P3(Layer *layer, const unsigned int cpu, CUINT row) +{ + if (cpu == RO(Shm)->Proc.Service.Core) { + return Draw_Sensors_V1_T0_P3(layer, cpu, row); + } else { + return Draw_Sensors_V0_T0_P3(layer, cpu, row); + } +} + +size_t Draw_Sensors_V3_T1_P0(Layer *layer, const unsigned int cpu, CUINT row) +{ + if (cpu == RO(Shm)->Proc.Service.Core) { + return Draw_Sensors_V1_T1_P0(layer, cpu, row); + } else { + return Draw_Sensors_V0_T1_P0(layer, cpu, row); + } +} + +size_t Draw_Sensors_V3_T1_P1(Layer *layer, const unsigned int cpu, CUINT row) +{ + if (cpu == RO(Shm)->Proc.Service.Core) { + return Draw_Sensors_V1_T1_P1(layer, cpu, row); + } else { + return Draw_Sensors_V0_T1_P1(layer, cpu, row); + } +} + +size_t Draw_Sensors_V3_T1_P2(Layer *layer, const unsigned int cpu, CUINT row) +{ + if (cpu == RO(Shm)->Proc.Service.Core) { + return Draw_Sensors_V1_T1_P2(layer, cpu, row); + } else { + return Draw_Sensors_V0_T1_P2(layer, cpu, row); + } +} + +size_t Draw_Sensors_V3_T1_P3(Layer *layer, const unsigned int cpu, CUINT row) +{ + if (cpu == RO(Shm)->Proc.Service.Core) { + return Draw_Sensors_V1_T1_P3(layer, cpu, row); + } else { + return Draw_Sensors_V0_T1_P3(layer, cpu, row); + } +} + +size_t Draw_Sensors_V3_T2_P0(Layer *layer, const unsigned int cpu, CUINT row) +{ + if (cpu == RO(Shm)->Proc.Service.Core) { + return Draw_Sensors_V1_T2_P0(layer, cpu, row); + } else { + return Draw_Sensors_V0_T2_P0(layer, cpu, row); + } +} + +size_t Draw_Sensors_V3_T2_P1(Layer *layer, const unsigned int cpu, CUINT row) +{ + if (cpu == RO(Shm)->Proc.Service.Core) { + return Draw_Sensors_V1_T2_P1(layer, cpu, row); + } else { + return Draw_Sensors_V0_T2_P1(layer, cpu, row); + } +} + +size_t Draw_Sensors_V3_T2_P2(Layer *layer, const unsigned int cpu, CUINT row) +{ + if (cpu == RO(Shm)->Proc.Service.Core) { + return Draw_Sensors_V1_T2_P2(layer, cpu, row); + } else { + return Draw_Sensors_V0_T2_P2(layer, cpu, row); + } +} + +size_t Draw_Sensors_V3_T2_P3(Layer *layer, const unsigned int cpu, CUINT row) +{ + if (cpu == RO(Shm)->Proc.Service.Core) { + return Draw_Sensors_V1_T2_P3(layer, cpu, row); + } else { + return Draw_Sensors_V0_T2_P3(layer, cpu, row); + } +} + +size_t Draw_Sensors_V3_T3_P0(Layer *layer, const unsigned int cpu, CUINT row) +{ + if (cpu == RO(Shm)->Proc.Service.Core) { + return Draw_Sensors_V1_T3_P0(layer, cpu, row); + } else { + return Draw_Sensors_V0_T3_P0(layer, cpu, row); + } +} + +size_t Draw_Sensors_V3_T3_P1(Layer *layer, const unsigned int cpu, CUINT row) +{ + if (cpu == RO(Shm)->Proc.Service.Core) { + return Draw_Sensors_V1_T3_P1(layer, cpu, row); + } else { + return Draw_Sensors_V0_T3_P1(layer, cpu, row); + } +} + +size_t Draw_Sensors_V3_T3_P2(Layer *layer, const unsigned int cpu, CUINT row) +{ + if (cpu == RO(Shm)->Proc.Service.Core) { + return Draw_Sensors_V1_T3_P2(layer, cpu, row); + } else { + return Draw_Sensors_V0_T3_P2(layer, cpu, row); + } +} + +size_t Draw_Sensors_V3_T3_P3(Layer *layer, const unsigned int cpu, CUINT row) +{ + if (cpu == RO(Shm)->Proc.Service.Core) { + return Draw_Sensors_V1_T3_P3(layer, cpu, row); + } else { + return Draw_Sensors_V0_T3_P3(layer, cpu, row); + } +} + +size_t (*Draw_Sensors_VTP_Matrix[4][4][4])(Layer*, const unsigned int, CUINT)=\ +{ +[FORMULA_SCOPE_NONE] = { + [FORMULA_SCOPE_NONE] = { + [FORMULA_SCOPE_NONE] = Draw_Sensors_V0_T0_P0, + [FORMULA_SCOPE_SMT ] = Draw_Sensors_V0_T0_P1, + [FORMULA_SCOPE_CORE] = Draw_Sensors_V0_T0_P2, + [FORMULA_SCOPE_PKG ] = Draw_Sensors_V0_T0_P3 + }, + [FORMULA_SCOPE_SMT ] = { + [FORMULA_SCOPE_NONE] = Draw_Sensors_V0_T1_P0, + [FORMULA_SCOPE_SMT ] = Draw_Sensors_V0_T1_P1, + [FORMULA_SCOPE_CORE] = Draw_Sensors_V0_T1_P2, + [FORMULA_SCOPE_PKG ] = Draw_Sensors_V0_T1_P3 + }, + [FORMULA_SCOPE_CORE] = { + [FORMULA_SCOPE_NONE] = Draw_Sensors_V0_T2_P0, + [FORMULA_SCOPE_SMT ] = Draw_Sensors_V0_T2_P1, + [FORMULA_SCOPE_CORE] = Draw_Sensors_V0_T2_P2, + [FORMULA_SCOPE_PKG ] = Draw_Sensors_V0_T2_P3 + }, + [FORMULA_SCOPE_PKG ] = { + [FORMULA_SCOPE_NONE] = Draw_Sensors_V0_T3_P0, + [FORMULA_SCOPE_SMT ] = Draw_Sensors_V0_T3_P1, + [FORMULA_SCOPE_CORE] = Draw_Sensors_V0_T3_P2, + [FORMULA_SCOPE_PKG ] = Draw_Sensors_V0_T3_P3 + } + }, +[FORMULA_SCOPE_SMT ] = { + [FORMULA_SCOPE_NONE] = { + [FORMULA_SCOPE_NONE] = Draw_Sensors_V1_T0_P0, + [FORMULA_SCOPE_SMT ] = Draw_Sensors_V1_T0_P1, + [FORMULA_SCOPE_CORE] = Draw_Sensors_V1_T0_P2, + [FORMULA_SCOPE_PKG ] = Draw_Sensors_V1_T0_P3 + }, + [FORMULA_SCOPE_SMT ] = { + [FORMULA_SCOPE_NONE] = Draw_Sensors_V1_T1_P0, + [FORMULA_SCOPE_SMT ] = Draw_Sensors_V1_T1_P1, + [FORMULA_SCOPE_CORE] = Draw_Sensors_V1_T1_P2, + [FORMULA_SCOPE_PKG ] = Draw_Sensors_V1_T1_P3 + }, + [FORMULA_SCOPE_CORE] = { + [FORMULA_SCOPE_NONE] = Draw_Sensors_V1_T2_P0, + [FORMULA_SCOPE_SMT ] = Draw_Sensors_V1_T2_P1, + [FORMULA_SCOPE_CORE] = Draw_Sensors_V1_T2_P2, + [FORMULA_SCOPE_PKG ] = Draw_Sensors_V1_T2_P3 + }, + [FORMULA_SCOPE_PKG ] = { + [FORMULA_SCOPE_NONE] = Draw_Sensors_V1_T3_P0, + [FORMULA_SCOPE_SMT ] = Draw_Sensors_V1_T3_P1, + [FORMULA_SCOPE_CORE] = Draw_Sensors_V1_T3_P2, + [FORMULA_SCOPE_PKG ] = Draw_Sensors_V1_T3_P3 + } + }, +[FORMULA_SCOPE_CORE] = { + [FORMULA_SCOPE_NONE] = { + [FORMULA_SCOPE_NONE] = Draw_Sensors_V2_T0_P0, + [FORMULA_SCOPE_SMT ] = Draw_Sensors_V2_T0_P1, + [FORMULA_SCOPE_CORE] = Draw_Sensors_V2_T0_P2, + [FORMULA_SCOPE_PKG ] = Draw_Sensors_V2_T0_P3 + }, + [FORMULA_SCOPE_SMT ] = { + [FORMULA_SCOPE_NONE] = Draw_Sensors_V2_T1_P0, + [FORMULA_SCOPE_SMT ] = Draw_Sensors_V2_T1_P1, + [FORMULA_SCOPE_CORE] = Draw_Sensors_V2_T1_P2, + [FORMULA_SCOPE_PKG ] = Draw_Sensors_V2_T1_P3 + }, + [FORMULA_SCOPE_CORE] = { + [FORMULA_SCOPE_NONE] = Draw_Sensors_V2_T2_P0, + [FORMULA_SCOPE_SMT ] = Draw_Sensors_V2_T2_P1, + [FORMULA_SCOPE_CORE] = Draw_Sensors_V2_T2_P2, + [FORMULA_SCOPE_PKG ] = Draw_Sensors_V2_T2_P3 + }, + [FORMULA_SCOPE_PKG ] = { + [FORMULA_SCOPE_NONE] = Draw_Sensors_V2_T3_P0, + [FORMULA_SCOPE_SMT ] = Draw_Sensors_V2_T3_P1, + [FORMULA_SCOPE_CORE] = Draw_Sensors_V2_T3_P2, + [FORMULA_SCOPE_PKG ] = Draw_Sensors_V2_T3_P3 + } + }, +[FORMULA_SCOPE_PKG ] = { + [FORMULA_SCOPE_NONE] = { + [FORMULA_SCOPE_NONE] = Draw_Sensors_V3_T0_P0, + [FORMULA_SCOPE_SMT ] = Draw_Sensors_V3_T0_P1, + [FORMULA_SCOPE_CORE] = Draw_Sensors_V3_T0_P2, + [FORMULA_SCOPE_PKG ] = Draw_Sensors_V3_T0_P3 + }, + [FORMULA_SCOPE_SMT ] = { + [FORMULA_SCOPE_NONE] = Draw_Sensors_V3_T1_P0, + [FORMULA_SCOPE_SMT ] = Draw_Sensors_V3_T1_P1, + [FORMULA_SCOPE_CORE] = Draw_Sensors_V3_T1_P2, + [FORMULA_SCOPE_PKG ] = Draw_Sensors_V3_T1_P3 + }, + [FORMULA_SCOPE_CORE] = { + [FORMULA_SCOPE_NONE] = Draw_Sensors_V3_T2_P0, + [FORMULA_SCOPE_SMT ] = Draw_Sensors_V3_T2_P1, + [FORMULA_SCOPE_CORE] = Draw_Sensors_V3_T2_P2, + [FORMULA_SCOPE_PKG ] = Draw_Sensors_V3_T2_P3 + }, + [FORMULA_SCOPE_PKG ] = { + [FORMULA_SCOPE_NONE] = Draw_Sensors_V3_T3_P0, + [FORMULA_SCOPE_SMT ] = Draw_Sensors_V3_T3_P1, + [FORMULA_SCOPE_CORE] = Draw_Sensors_V3_T3_P2, + [FORMULA_SCOPE_PKG ] = Draw_Sensors_V3_T3_P3 + } + } +}; + +CUINT Draw_Monitor_Sensors(Layer *layer, const unsigned int cpu, CUINT row) +{ + size_t len; + const enum FORMULA_SCOPE + voltageScope = SCOPE_OF_FORMULA(RO(Shm)->Proc.voltageFormula), + thermalScope = SCOPE_OF_FORMULA(RO(Shm)->Proc.thermalFormula), + powerScope = SCOPE_OF_FORMULA(RO(Shm)->Proc.powerFormula); + + len = Draw_Sensors_VTP_Matrix [voltageScope] + [thermalScope] + [powerScope] (layer, cpu, row); + + memcpy(&LayerAt(layer, code, LOAD_LEAD, row), Buffer, len); + + return 0; +} + +#define Draw_Voltage_None Draw_Sensors_V0_T0_P0 + +size_t Draw_Voltage_SMT(Layer *layer, const unsigned int cpu, CUINT row) +{ + struct FLIP_FLOP *CFlop = \ + &RO(Shm)->Cpu[cpu].FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + size_t len; + UNUSED(layer); + UNUSED(row); + + StrLenFormat(len, Buffer, 80+1, + "%7.2f\x20%7d" \ + "\x20\x20\x20\x20\x20%5.4f" \ + "\x20\x20\x20%5.4f" \ + "\x20\x20\x20%5.4f" \ + "%.*s", + Draw.Load ? CFlop->Absolute.Freq:CFlop->Relative.Freq, + CFlop->Voltage.VID, + RO(Shm)->Cpu[cpu].Sensors.Voltage.Limit[SENSOR_LOWEST], + CFlop->Voltage.Vcore, + RO(Shm)->Cpu[cpu].Sensors.Voltage.Limit[SENSOR_HIGHEST], + 32, hSpace); + return len; +} + +size_t Draw_Voltage_Core(Layer *layer, const unsigned int cpu, CUINT row) +{ + if ((RO(Shm)->Cpu[cpu].Topology.ThreadID == 0) + || (RO(Shm)->Cpu[cpu].Topology.ThreadID == -1)) { + return Draw_Voltage_SMT(layer, cpu, row); + } else { + return Draw_Voltage_None(layer, cpu, row); + } +} + +size_t Draw_Voltage_Pkg(Layer *layer, const unsigned int cpu, CUINT row) +{ + if (cpu == RO(Shm)->Proc.Service.Core) { + return Draw_Voltage_SMT(layer, cpu, row); + } else { + return Draw_Voltage_None(layer, cpu, row); + } +} + +size_t (*Draw_Voltage_Matrix[4])(Layer*, const unsigned int, CUINT) = \ +{ + [FORMULA_SCOPE_NONE] = Draw_Voltage_None, + [FORMULA_SCOPE_SMT ] = Draw_Voltage_SMT, + [FORMULA_SCOPE_CORE] = Draw_Voltage_Core, + [FORMULA_SCOPE_PKG ] = Draw_Voltage_Pkg +}; + +CUINT Draw_Monitor_Voltage(Layer *layer, const unsigned int cpu, CUINT row) +{ + size_t len; + const enum FORMULA_SCOPE + voltageScope = SCOPE_OF_FORMULA(RO(Shm)->Proc.voltageFormula); + + len = Draw_Voltage_Matrix[voltageScope](layer, cpu, row); + + memcpy(&LayerAt(layer, code, LOAD_LEAD, row), Buffer, len); + + return 0; +} + +#define Draw_Energy_None Draw_Sensors_V0_T0_P0 + +size_t Draw_Energy_Joule(Layer *layer, const unsigned int cpu, CUINT row) +{ + struct FLIP_FLOP *CFlop = \ + &RO(Shm)->Cpu[cpu].FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + size_t len; + UNUSED(layer); + UNUSED(row); + + StrLenFormat(len, Buffer, 80+1, + "%7.2f\x20\x20\x20%018llu\x20\x20\x20\x20" \ + "%10.6f\x20\x20%10.6f\x20\x20%10.6f", + Draw.Load ? CFlop->Absolute.Freq:CFlop->Relative.Freq, + CFlop->Delta.Power.ACCU, + RO(Shm)->Cpu[cpu].Sensors.Energy.Limit[SENSOR_LOWEST], + CFlop->State.Energy, + RO(Shm)->Cpu[cpu].Sensors.Energy.Limit[SENSOR_HIGHEST]); + return len; +} + +size_t Draw_Power_Watt(Layer *layer, const unsigned int cpu, CUINT row) +{ + struct FLIP_FLOP *CFlop = \ + &RO(Shm)->Cpu[cpu].FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + size_t len; + UNUSED(layer); + UNUSED(row); + + StrLenFormat(len, Buffer, 80+1, + "%7.2f\x20\x20\x20%018llu\x20\x20\x20\x20" \ + "%10.6f\x20\x20%10.6f\x20\x20%10.6f", + Draw.Load ? CFlop->Absolute.Freq:CFlop->Relative.Freq, + CFlop->Delta.Power.ACCU, + RO(Shm)->Cpu[cpu].Sensors.Power.Limit[SENSOR_LOWEST], + CFlop->State.Power, + RO(Shm)->Cpu[cpu].Sensors.Power.Limit[SENSOR_HIGHEST]); + return len; +} + +size_t (*Draw_Energy_Power_Matrix[])(Layer*, const unsigned int, CUINT) = { + Draw_Energy_Joule, + Draw_Power_Watt +}; + +size_t Draw_Energy_SMT(Layer *layer, const unsigned int cpu, CUINT row) +{ + return Draw_Energy_Power_Matrix[Setting.jouleWatt](layer, cpu, row); +} + +size_t Draw_Energy_Core(Layer *layer, const unsigned int cpu, CUINT row) +{ + if ((RO(Shm)->Cpu[cpu].Topology.ThreadID == 0) + || (RO(Shm)->Cpu[cpu].Topology.ThreadID == -1)) { + return Draw_Energy_SMT(layer, cpu, row); + } else { + return Draw_Energy_None(layer, cpu, row); + } +} + +size_t Draw_Energy_Pkg(Layer *layer, const unsigned int cpu, CUINT row) +{ + if (cpu == RO(Shm)->Proc.Service.Core) { + return Draw_Energy_SMT(layer, cpu, row); + } else { + return Draw_Energy_None(layer, cpu, row); + } +} + +size_t (*Draw_Energy_Matrix[4])(Layer*, const unsigned int, CUINT) = \ +{ + [FORMULA_SCOPE_NONE] = Draw_Energy_None, + [FORMULA_SCOPE_SMT ] = Draw_Energy_SMT, + [FORMULA_SCOPE_CORE] = Draw_Energy_Core, + [FORMULA_SCOPE_PKG ] = Draw_Energy_Pkg +}; + +CUINT Draw_Monitor_Energy(Layer *layer, const unsigned int cpu, CUINT row) +{ + size_t len; + const enum FORMULA_SCOPE + powerScope = SCOPE_OF_FORMULA(RO(Shm)->Proc.powerFormula); + + len = Draw_Energy_Matrix[powerScope](layer, cpu, row); + + memcpy(&LayerAt(layer, code, LOAD_LEAD, row), Buffer, len); + + return 0; +} + +size_t Draw_Monitor_Slice_Error_Relative_Freq( struct FLIP_FLOP *CFlop, + struct SLICE_STRUCT *pSlice ) +{ + size_t len; + StrLenFormat(len, Buffer, 8+20+20+20+20+20+1, + "%7.2f " \ + "%16llu%16llu%18llu%18llu%18llu", + CFlop->Relative.Freq, + pSlice->Delta.TSC, + pSlice->Delta.INST, + pSlice->Counter[1].TSC, + pSlice->Counter[1].INST, + pSlice->Error); + return len; +} + +size_t Draw_Monitor_Slice_Error_Absolute_Freq( struct FLIP_FLOP *CFlop, + struct SLICE_STRUCT *pSlice ) +{ + size_t len; + StrLenFormat(len, Buffer, 8+20+20+20+20+20+1, + "%7.2f " \ + "%16llu%16llu%18llu%18llu%18llu", + CFlop->Absolute.Freq, + pSlice->Delta.TSC, + pSlice->Delta.INST, + pSlice->Counter[1].TSC, + pSlice->Counter[1].INST, + pSlice->Error); + return len; +} + +size_t Draw_Monitor_Slice_NoError_Relative_Freq(struct FLIP_FLOP *CFlop, + struct SLICE_STRUCT *pSlice) +{ + size_t len; + StrLenFormat(len, Buffer, 8+20+20+20+20+18+1, + "%7.2f " \ + "%16llu%16llu%18llu%18llu%.*s", + CFlop->Relative.Freq, + pSlice->Delta.TSC, + pSlice->Delta.INST, + pSlice->Counter[1].TSC, + pSlice->Counter[1].INST, + 18, hSpace); + return len; +} + +size_t Draw_Monitor_Slice_NoError_Absolute_Freq(struct FLIP_FLOP *CFlop, + struct SLICE_STRUCT *pSlice) +{ + size_t len; + StrLenFormat(len, Buffer, 8+20+20+20+20+18+1, + "%7.2f " \ + "%16llu%16llu%18llu%18llu%.*s", + CFlop->Absolute.Freq, + pSlice->Delta.TSC, + pSlice->Delta.INST, + pSlice->Counter[1].TSC, + pSlice->Counter[1].INST, + 18, hSpace); + return len; +} + +size_t (*Draw_Monitor_Slice_Matrix[2][2])(struct FLIP_FLOP *CFlop, + struct SLICE_STRUCT *pSlice) = \ +{ + { + Draw_Monitor_Slice_NoError_Relative_Freq, + Draw_Monitor_Slice_NoError_Absolute_Freq + }, + { + Draw_Monitor_Slice_Error_Relative_Freq, + Draw_Monitor_Slice_Error_Absolute_Freq + } +}; + +CUINT Draw_Monitor_Slice(Layer *layer, const unsigned int cpu, CUINT row) +{ + struct FLIP_FLOP *CFlop = \ + &RO(Shm)->Cpu[cpu].FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + + struct SLICE_STRUCT *pSlice = &RO(Shm)->Cpu[cpu].Slice; + + const unsigned int flagError = (RO(Shm)->Cpu[cpu].Slice.Error > 0); + size_t len; + len = Draw_Monitor_Slice_Matrix[flagError][Draw.Load](CFlop, pSlice); + + memcpy(&LayerAt(layer, code, LOAD_LEAD, row), Buffer, len); + + return 0; +} + +CUINT Draw_Monitor_Custom(Layer *layer, const unsigned int cpu, CUINT row) +{ + CPU_STRUCT *Cpu = &RO(Shm)->Cpu[cpu]; + struct FLIP_FLOP *CFlop = &Cpu->FlipFlop[!RO(Shm)->Cpu[cpu].Toggle]; + + size_t len; + StrLenFormat(len, Buffer, MAX_WIDTH, + "%7.2f %7.2f %7.2f" \ + "\x20\x20\x20" "%7.2f %7.2f %7.2f" \ + "\x20\x20" "%3u %3u %3u" \ + "\x20\x20" "%7.4f %7.4f %7.4f" \ + "\x20\x20" "%8.4f %8.4f %8.4f" \ + "\x20\x20" "%6.2f %6.2f %6.2f %6.2f %6.2f %6.2f" \ + "\x20\x20" "%10.6f" "%10.6f" "%10.6f", +/* [ 1] MIN_REL_FREQ */ + Cpu->Relative.Freq[SENSOR_LOWEST], +/* [ 2] RELATIVE_FREQ */ + CFlop->Relative.Freq, +/* [ 3] MAX_REL_FREQ */ + Cpu->Relative.Freq[SENSOR_HIGHEST], +/* [ 4] MIN_ABS_FREQ */ + Cpu->Absolute.Freq[SENSOR_LOWEST], +/* [ 5] ABSOLUTE_FREQ */ + CFlop->Absolute.Freq, +/* [ 6] MAX_ABS_FREQ */ + Cpu->Absolute.Freq[SENSOR_HIGHEST], +/* [ 7] MIN_TEMP */ + Setting.fahrCels ? Cels2Fahr(Cpu->PowerThermal.Limit[SENSOR_LOWEST]) + : Cpu->PowerThermal.Limit[SENSOR_LOWEST], +/* [ 8] TEMPERATURE */ + Setting.fahrCels ? Cels2Fahr(CFlop->Thermal.Temp) + : CFlop->Thermal.Temp, +/* [ 9] MAX_TEMP */ + Setting.fahrCels ? Cels2Fahr(Cpu->PowerThermal.Limit[SENSOR_HIGHEST]) + : Cpu->PowerThermal.Limit[SENSOR_HIGHEST], +/* [10] MIN_VOLT */ + Cpu->Sensors.Voltage.Limit[SENSOR_LOWEST], +/* [11] CORE_VOLTAGE */ + CFlop->Voltage.Vcore, +/* [12] MAX_VOLT */ + Cpu->Sensors.Voltage.Limit[SENSOR_HIGHEST], +/* [13] MIN_POWER */ + Setting.jouleWatt ? Cpu->Sensors.Energy.Limit[SENSOR_LOWEST] + : Cpu->Sensors.Power.Limit[SENSOR_LOWEST], +/* [14] ENERGY_POWER */ + Setting.jouleWatt ? CFlop->State.Energy : CFlop->State.Power, +/* [15] MAX_POWER */ + Setting.jouleWatt ? Cpu->Sensors.Energy.Limit[SENSOR_HIGHEST] + : Cpu->Sensors.Power.Limit[SENSOR_HIGHEST], +/* [16] PERCENT_TURBO */ + 100.f * CFlop->State.Turbo, +/* [17 ... 21] C-STATES */ + 100.f * CFlop->State.C0, + 100.f * CFlop->State.C1, + 100.f * CFlop->State.C3, + 100.f * CFlop->State.C6, + 100.f * CFlop->State.C7, +/* [22 ... 24] INST */ + CFlop->State.IPS, + CFlop->State.IPC, + CFlop->State.CPI); + + memcpy(&LayerAt(layer, code, LOAD_LEAD, row), Buffer, len); + + return 0; +} + +CUINT Draw_AltMonitor_Frequency(Layer *layer, const unsigned int cpu, CUINT row) +{ + size_t len; + UNUSED(cpu); + + row += 1 + Draw.Area.MaxRows; + if (!Draw.Flag.avgOrPC) { + StrLenFormat(len, Buffer, ((5*2)+1)+(6*7)+1, + "%6.2f" "%% " "%6.2f" "%% " "%6.2f" "%% " \ + "%6.2f" "%% " "%6.2f" "%% " "%6.2f" "%%", + 100.f * RO(Shm)->Proc.Avg.Turbo, + 100.f * RO(Shm)->Proc.Avg.C0, + 100.f * RO(Shm)->Proc.Avg.C1, + 100.f * RO(Shm)->Proc.Avg.C3, + 100.f * RO(Shm)->Proc.Avg.C6, + 100.f * RO(Shm)->Proc.Avg.C7); + + memcpy(&LayerAt(layer, code, 20, row), Buffer, len); + } else { + #if defined(ARCH_PMC) && (ARCH_PMC == UMC) + struct PKG_FLIP_FLOP *PFlop = \ + &RO(Shm)->Proc.FlipFlop[!RO(Shm)->Proc.Toggle]; + + StrLenFormat(len, Buffer, ((20*8)+(4*6)+1), + " %5llu" " :%5llu" " :%5llu" \ + " :%5llu" " :%5llu" " :%5llu" \ + " :%5llu" " :%5llu", + PFlop->Delta.PC02 / (1000LLU * 1000LLU), + PFlop->Delta.PC03 / (1000LLU * 1000LLU), + PFlop->Delta.PC04 / (1000LLU * 1000LLU), + PFlop->Delta.PC06 / (1000LLU * 1000LLU), + PFlop->Delta.PC07 / (1000LLU * 1000LLU), + PFlop->Delta.PC08 / (1000LLU * 1000LLU), + PFlop->Delta.PC09 / (1000LLU * 1000LLU), + PFlop->Delta.PC10 / (1000LLU * 1000LLU)); + #else + StrLenFormat(len, Buffer, ((6*4)+3+5)+(8*6)+1, + "c2:%-5.1f" " c3:%-5.1f" " c4:%-5.1f" \ + " c6:%-5.1f" " c7:%-5.1f" " c8:%-5.1f" \ + " c9:%-5.1f" " c10:%-5.1f", + 100.f * RO(Shm)->Proc.State.PC02, + 100.f * RO(Shm)->Proc.State.PC03, + 100.f * RO(Shm)->Proc.State.PC04, + 100.f * RO(Shm)->Proc.State.PC06, + 100.f * RO(Shm)->Proc.State.PC07, + 100.f * RO(Shm)->Proc.State.PC08, + 100.f * RO(Shm)->Proc.State.PC09, + 100.f * RO(Shm)->Proc.State.PC10); + #endif + memcpy(&LayerAt(layer, code, 7, row), Buffer, len); + } + row += 1; + return row; +} + +CUINT Draw_AltMonitor_Common(Layer *layer, const unsigned int cpu, CUINT row) +{ + UNUSED(layer); + UNUSED(cpu); + + row += 2 + Draw.Area.MaxRows; + return row; +} + +CUINT Draw_AltMonitor_Package(Layer *layer, const unsigned int cpu, CUINT row) +{ + struct PKG_FLIP_FLOP *PFlop = \ + &RO(Shm)->Proc.FlipFlop[!RO(Shm)->Proc.Toggle]; + + CUINT bar0, bar1, margin = Draw.Area.LoadWidth - 28; + size_t len; + UNUSED(cpu); + + row += 1; +/* PC02 */ + bar0 = (CUINT) (RO(Shm)->Proc.State.PC02 * margin); + bar1 = margin - bar0; + + StrLenFormat(len, Buffer, Draw.Area.LoadWidth, + "%18llu" "%7.2f" "%% " "%.*s" "%.*s", + PFlop->Delta.PC02, 100.f * RO(Shm)->Proc.State.PC02, + bar0, hBar, bar1, hSpace); + + memcpy(&LayerAt(layer, code, 5, row), Buffer, len); +/* PC03 */ + bar0 = (CUINT) (RO(Shm)->Proc.State.PC03 * margin); + bar1 = margin - bar0; + + StrLenFormat(len, Buffer, Draw.Area.LoadWidth, + "%18llu" "%7.2f" "%% " "%.*s" "%.*s", + PFlop->Delta.PC03, 100.f * RO(Shm)->Proc.State.PC03, + bar0, hBar, bar1, hSpace); + + memcpy(&LayerAt(layer, code, 5, (row + 1)), Buffer, len); +/* PC04 */ + bar0 = (CUINT) (RO(Shm)->Proc.State.PC04 * margin); + bar1 = margin - bar0; + + StrLenFormat(len, Buffer, Draw.Area.LoadWidth, + "%18llu" "%7.2f" "%% " "%.*s" "%.*s", + PFlop->Delta.PC04, 100.f * RO(Shm)->Proc.State.PC04, + bar0, hBar, bar1, hSpace); + + memcpy(&LayerAt(layer, code, 5, (row + 2)), Buffer, len); +/* PC06 */ + bar0 = (CUINT) (RO(Shm)->Proc.State.PC06 * margin); + bar1 = margin - bar0; + + StrLenFormat(len, Buffer, Draw.Area.LoadWidth, + "%18llu" "%7.2f" "%% " "%.*s" "%.*s", + PFlop->Delta.PC06, 100.f * RO(Shm)->Proc.State.PC06, + bar0, hBar, bar1, hSpace); + + memcpy(&LayerAt(layer, code, 5, (row + 3)), Buffer, len); +/* PC07 */ + bar0 = (CUINT) (RO(Shm)->Proc.State.PC07 * margin); + bar1 = margin - bar0; + + StrLenFormat(len, Buffer, Draw.Area.LoadWidth, + "%18llu" "%7.2f" "%% " "%.*s" "%.*s", + PFlop->Delta.PC07, 100.f * RO(Shm)->Proc.State.PC07, + bar0, hBar, bar1, hSpace); + + memcpy(&LayerAt(layer, code, 5, (row + 4)), Buffer, len); +/* PC08 */ + bar0 = (CUINT) (RO(Shm)->Proc.State.PC08 * margin); + bar1 = margin - bar0; + + StrLenFormat(len, Buffer, Draw.Area.LoadWidth, + "%18llu" "%7.2f" "%% " "%.*s" "%.*s", + PFlop->Delta.PC08, 100.f * RO(Shm)->Proc.State.PC08, + bar0, hBar, bar1, hSpace); + + memcpy(&LayerAt(layer, code, 5, (row + 5)), Buffer, len); +/* PC09 */ + bar0 = (CUINT) (RO(Shm)->Proc.State.PC09 * margin); + bar1 = margin - bar0; + + StrLenFormat(len, Buffer, Draw.Area.LoadWidth, + "%18llu" "%7.2f" "%% " "%.*s" "%.*s", + PFlop->Delta.PC09, 100.f * RO(Shm)->Proc.State.PC09, + bar0, hBar, bar1, hSpace); + + memcpy(&LayerAt(layer, code, 5, (row + 6)), Buffer, len); +/* PC10 */ + bar0 = (CUINT) (RO(Shm)->Proc.State.PC10 * margin); + bar1 = margin - bar0; + + StrLenFormat(len, Buffer, Draw.Area.LoadWidth, + "%18llu" "%7.2f" "%% " "%.*s" "%.*s", + PFlop->Delta.PC10, 100.f * RO(Shm)->Proc.State.PC10, + bar0, hBar, bar1, hSpace); + + memcpy(&LayerAt(layer, code, 5, (row + 7)), Buffer, len); +/* MC6 */ + bar0 = (CUINT) (RO(Shm)->Proc.State.MC6 * margin); + bar1 = margin - bar0; + + StrLenFormat(len, Buffer, Draw.Area.LoadWidth, + "%18llu" "%7.2f" "%% " "%.*s" "%.*s", + PFlop->Delta.MC6, 100.f * RO(Shm)->Proc.State.MC6, + bar0, hBar, bar1, hSpace); + + memcpy(&LayerAt(layer, code, 5, (row + 8)), Buffer, len); +/* TSC */ + StrLenFormat(len, Buffer, Draw.Area.LoadWidth, + "%18llu", PFlop->Delta.PCLK); + + memcpy(&LayerAt(layer, code, 5, (row + 9)), Buffer, len); +/* UNCORE */ + StrLenFormat(len, Buffer, Draw.Area.LoadWidth, + "%18llu", PFlop->Uncore.FC0); + + memcpy(&LayerAt(layer, code, 5+18+7+2+18+7, (row + 9)), Buffer, len); + + row += 1 + 10; + return row; +} + +CUINT Draw_AltMonitor_Tasks(Layer *layer, const unsigned int cpu, CUINT row) +{ + UNUSED(cpu); + + if (RO(Shm)->SysGate.tickStep == RO(Shm)->SysGate.tickReset) + { + ssize_t len = 0; + signed int idx; + char stateStr[TASK_COMM_LEN]; + ATTRIBUTE *stateAttr; + + /* Clear the trailing garbage chars left by the previous drawing. */ + FillLayerArea( layer, (LOAD_LEAD + 8), (row + 1), + (Draw.Size.width - (LOAD_LEAD + 8)), Draw.Area.MaxRows, + hSpace, RSC(UI).ATTR()[UI_DRAW_ALTMONITOR_TASKS_CLEAR]); + + for (idx = 0; idx < RO(Shm)->SysGate.taskCount; idx++) + { + if(!BITVAL(RO(Shm)->Cpu[RO(Shm)->SysGate.taskList[idx].wake_cpu].OffLine,OS) + && (RO(Shm)->SysGate.taskList[idx].wake_cpu >= (short int)Draw.cpuScroll) + && (RO(Shm)->SysGate.taskList[idx].wake_cpu < (short int)(Draw.cpuScroll + + Draw.Area.MaxRows))) + { + unsigned int ldx = 2; + CSINT dif = Draw.Size.width + - cTask[RO(Shm)->SysGate.taskList[idx].wake_cpu].col; + + if (dif > 0) + { + stateAttr=StateToSymbol(RO(Shm)->SysGate.taskList[idx].state, stateStr); + + if (RO(Shm)->SysGate.taskList[idx].pid == RO(Shm)->SysGate.trackTask) + { + stateAttr = RSC(TRACKER_STATE_COLOR).ATTR(); + } + if (!Draw.Flag.taskVal) { + StrLenFormat(len, Buffer, TASK_COMM_LEN, "%s", + RO(Shm)->SysGate.taskList[idx].comm); + } else { + switch (RO(Shm)->SysGate.sortByField) { + case F_STATE: + StrLenFormat(len, Buffer, 2 * TASK_COMM_LEN + 2, + "%s(%s)", + RO(Shm)->SysGate.taskList[idx].comm, + stateStr); + break; + case F_RTIME: + StrLenFormat(len, Buffer, TASK_COMM_LEN + 20 + 2, + "%s(%llu)", + RO(Shm)->SysGate.taskList[idx].comm, + RO(Shm)->SysGate.taskList[idx].runtime); + break; + case F_UTIME: + StrLenFormat(len, Buffer, TASK_COMM_LEN + 20 + 2, + "%s(%llu)", + RO(Shm)->SysGate.taskList[idx].comm, + RO(Shm)->SysGate.taskList[idx].usertime); + break; + case F_STIME: + StrLenFormat(len, Buffer, TASK_COMM_LEN + 20 + 2, + "%s(%llu)", + RO(Shm)->SysGate.taskList[idx].comm, + RO(Shm)->SysGate.taskList[idx].systime); + break; + case F_PID: + fallthrough; + case F_COMM: + StrLenFormat(len, Buffer, TASK_COMM_LEN + 11 + 2, + "%s(%d)", + RO(Shm)->SysGate.taskList[idx].comm, + RO(Shm)->SysGate.taskList[idx].pid); + break; + } + } + if (dif >= len) { + LayerCopyAt(layer, + cTask[RO(Shm)->SysGate.taskList[idx].wake_cpu].col, + cTask[RO(Shm)->SysGate.taskList[idx].wake_cpu].row, + len, stateAttr, Buffer); + + cTask[RO(Shm)->SysGate.taskList[idx].wake_cpu].col += len; + /* Add a blank spacing between items: up to (ldx) chars */ + while ((dif = Draw.Size.width + - cTask[RO(Shm)->SysGate.taskList[idx].wake_cpu].col) > 0 + && ldx--) + { + LayerAt(layer, attr, + cTask[RO(Shm)->SysGate.taskList[idx].wake_cpu].col, + cTask[RO(Shm)->SysGate.taskList[idx].wake_cpu].row) = + RSC(UI).ATTR()[UI_DRAW_ALTMONITOR_TASKS_SPACE]; + LayerAt(layer, code, + cTask[RO(Shm)->SysGate.taskList[idx].wake_cpu].col, + cTask[RO(Shm)->SysGate.taskList[idx].wake_cpu].row) = 0x20; + + cTask[RO(Shm)->SysGate.taskList[idx].wake_cpu].col++; + } + } else { + LayerCopyAt(layer, + cTask[RO(Shm)->SysGate.taskList[idx].wake_cpu].col, + cTask[RO(Shm)->SysGate.taskList[idx].wake_cpu].row, + dif, stateAttr, Buffer); + + cTask[RO(Shm)->SysGate.taskList[idx].wake_cpu].col += dif; + } + } + } + } + } + row += 2 + Draw.Area.MaxRows; + return row; +} + +void Draw_AltMonitor_Energy_Joule(void) +{ + StrFormat(Buffer, 9+9+9+9+1, + "%8.4f" "%8.4f" "%8.4f" "%8.4f", + RO(Shm)->Proc.State.Energy[PWR_DOMAIN(PKG)].Current, + RO(Shm)->Proc.State.Energy[PWR_DOMAIN(CORES)].Current, + RO(Shm)->Proc.State.Energy[PWR_DOMAIN(UNCORE)].Current, + RO(Shm)->Proc.State.Energy[PWR_DOMAIN(RAM)].Current); +} + +void Draw_AltMonitor_Power_Watt(void) +{ + StrFormat(Buffer, 9+9+9+9+1, + "%8.4f" "%8.4f" "%8.4f" "%8.4f", + RO(Shm)->Proc.State.Power[PWR_DOMAIN(PKG)].Current, + RO(Shm)->Proc.State.Power[PWR_DOMAIN(CORES)].Current, + RO(Shm)->Proc.State.Power[PWR_DOMAIN(UNCORE)].Current, + RO(Shm)->Proc.State.Power[PWR_DOMAIN(RAM)].Current); +} + +void (*Draw_AltMonitor_Power_Matrix[])(void) = { + Draw_AltMonitor_Energy_Joule, + Draw_AltMonitor_Power_Watt +}; + +CUINT Draw_AltMonitor_Power(Layer *layer, const unsigned int cpu, CUINT row) +{ + const CUINT col = LOAD_LEAD; + UNUSED(cpu); + + row += 1 + Draw.Area.MaxRows; + + Draw_AltMonitor_Power_Matrix[Setting.jouleWatt](); + + memcpy(&LayerAt(layer, code, col + 1, row), &Buffer[24], 8); + memcpy(&LayerAt(layer, code, col + 22, row), &Buffer[16], 8); + memcpy(&LayerAt(layer, code, col + 44, row), &Buffer[ 0], 8); + memcpy(&LayerAt(layer, code, col + 64, row), &Buffer[ 8], 8); + + row += 1; + return row; +} + +CUINT Draw_AltMonitor_Voltage(Layer *layer, const unsigned int cpu, CUINT row) +{ + const CUINT col = LOAD_LEAD + 8; + UNUSED(cpu); + + row += 1 + Draw.Area.MaxRows; + + struct PKG_FLIP_FLOP *PFlop = \ + &RO(Shm)->Proc.FlipFlop[!RO(Shm)->Proc.Toggle]; + + StrFormat(Buffer, 2*11+4*6+1, + "%7d" "%05.4f" "%05.4f" "%05.4f" "%7d" "%05.4f", + PFlop->Voltage.VID.CPU, + RO(Shm)->Proc.State.Voltage.Limit[SENSOR_LOWEST], + PFlop->Voltage.CPU, + RO(Shm)->Proc.State.Voltage.Limit[SENSOR_HIGHEST], + PFlop->Voltage.VID.SOC, + PFlop->Voltage.SOC); + + memcpy(&LayerAt(layer, code, col, row), &Buffer[ 0], 7); + memcpy(&LayerAt(layer, code, col + 12, row), &Buffer[ 7], 6); + memcpy(&LayerAt(layer, code, col + 21, row), &Buffer[13], 6); + memcpy(&LayerAt(layer, code, col + 30, row), &Buffer[19], 6); + memcpy(&LayerAt(layer, code, col + 49, row), &Buffer[25], 7); + memcpy(&LayerAt(layer, code, col + 59, row), &Buffer[32], 6); + + row += 1; + return row; +} + +#define CUST_CTR_FMT " c2:%-5.1f" " c3:%-5.1f" " c4:%-5.1f" \ + " c6:%-5.1f" " c7:%-5.1f" " c8:%-5.1f" \ + " c9:%-5.1f" " c10:%-5.1f" + +#define CUST_CTR_VAR0 100.f * RO(Shm)->Proc.State.PC02 +#define CUST_CTR_VAR1 100.f * RO(Shm)->Proc.State.PC03 +#define CUST_CTR_VAR2 100.f * RO(Shm)->Proc.State.PC04 +#define CUST_CTR_VAR3 100.f * RO(Shm)->Proc.State.PC06 +#define CUST_CTR_VAR4 100.f * RO(Shm)->Proc.State.PC07 +#define CUST_CTR_VAR5 100.f * RO(Shm)->Proc.State.PC08 +#define CUST_CTR_VAR6 100.f * RO(Shm)->Proc.State.PC09 +#define CUST_CTR_VAR7 100.f * RO(Shm)->Proc.State.PC10 + +/*#endif ARCH_PMC */ + +#define CUST_PMC(unit) " RAM:%8.4f(" COREFREQ_STRINGIFY(unit) ") -" \ + "- SA:%8.4f(" COREFREQ_STRINGIFY(unit) ")/%5.4f(V)" \ + " - Pkg[%c]:%8.4f(" COREFREQ_STRINGIFY(unit) ") - " \ + "%5.4f %5.4f %5.4f %8.4f %8.4f %8.4f -" + +size_t Draw_AltMonitor_Custom_Energy_Joule(void) +{ + struct PKG_FLIP_FLOP *PFlop = \ + &RO(Shm)->Proc.FlipFlop[!RO(Shm)->Proc.Toggle]; + + size_t len; + StrLenFormat(len, Buffer, MAX_WIDTH, + CUST_PMC(J) CUST_CTR_FMT, + + RO(Shm)->Proc.State.Energy[PWR_DOMAIN(RAM)].Current, + RO(Shm)->Proc.State.Energy[PWR_DOMAIN(UNCORE)].Current, + PFlop->Voltage.SOC, + + '0'+RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Topology.PackageID, + RO(Shm)->Proc.State.Energy[PWR_DOMAIN(PKG)].Current, + + RO(Shm)->Proc.State.Voltage.Limit[SENSOR_LOWEST], + PFlop->Voltage.CPU, + RO(Shm)->Proc.State.Voltage.Limit[SENSOR_HIGHEST], + + RO(Shm)->Proc.State.Energy[PWR_DOMAIN(CORES)].Limit[SENSOR_LOWEST], + RO(Shm)->Proc.State.Energy[PWR_DOMAIN(CORES)].Current, + RO(Shm)->Proc.State.Energy[PWR_DOMAIN(CORES)].Limit[SENSOR_HIGHEST], + + CUST_CTR_VAR0, + CUST_CTR_VAR1, + CUST_CTR_VAR2, + CUST_CTR_VAR3, + CUST_CTR_VAR4, + CUST_CTR_VAR5, + CUST_CTR_VAR6, + CUST_CTR_VAR7); + return len; +} + +size_t Draw_AltMonitor_Custom_Power_Watt(void) +{ + struct PKG_FLIP_FLOP *PFlop = \ + &RO(Shm)->Proc.FlipFlop[!RO(Shm)->Proc.Toggle]; + + size_t len; + StrLenFormat(len, Buffer, MAX_WIDTH, + CUST_PMC(W) CUST_CTR_FMT, + + RO(Shm)->Proc.State.Power[PWR_DOMAIN(RAM)].Current, + RO(Shm)->Proc.State.Power[PWR_DOMAIN(UNCORE)].Current, + PFlop->Voltage.SOC, + + '0'+RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Topology.PackageID, + RO(Shm)->Proc.State.Power[PWR_DOMAIN(PKG)].Current, + + RO(Shm)->Proc.State.Voltage.Limit[SENSOR_LOWEST], + PFlop->Voltage.CPU, + RO(Shm)->Proc.State.Voltage.Limit[SENSOR_HIGHEST], + + RO(Shm)->Proc.State.Power[PWR_DOMAIN(CORES)].Limit[SENSOR_LOWEST], + RO(Shm)->Proc.State.Power[PWR_DOMAIN(CORES)].Current, + RO(Shm)->Proc.State.Power[PWR_DOMAIN(CORES)].Limit[SENSOR_HIGHEST], + + CUST_CTR_VAR0, + CUST_CTR_VAR1, + CUST_CTR_VAR2, + CUST_CTR_VAR3, + CUST_CTR_VAR4, + CUST_CTR_VAR5, + CUST_CTR_VAR6, + CUST_CTR_VAR7); + return len; +} + +#undef CUST_CTR_FMT +#undef CUST_CTR_VAR0 +#undef CUST_CTR_VAR1 +#undef CUST_CTR_VAR2 +#undef CUST_CTR_VAR3 +#undef CUST_CTR_VAR4 +#undef CUST_CTR_VAR5 +#undef CUST_CTR_VAR6 +#undef CUST_CTR_VAR7 +#undef CUST_PMC + +size_t (*Draw_AltMonitor_Custom_Matrix[])(void) = { + Draw_AltMonitor_Custom_Energy_Joule, + Draw_AltMonitor_Custom_Power_Watt +}; + +CUINT Draw_AltMonitor_Custom(Layer *layer, const unsigned int cpu, CUINT row) +{ + UNUSED(cpu); + + row += 1 + Draw.Area.MaxRows; + + size_t len = Draw_AltMonitor_Custom_Matrix[Setting.jouleWatt](); + + memcpy(&LayerAt(layer, code, 1, row), &Buffer[ 0], len); + + row += 1; + return row; +} +#endif /* NO_LOWER */ + +#ifndef NO_FOOTER +/* >>> GLOBALS >>> */ +char *Format_Temp_Voltage[2][2] = { + [0]={ [0]="\x20\x20\x20\x20\x20\x20\x20", [1]="\x20\x20\x20%2$4.2f" }, + [1]={ [0]="%1$3u\x20\x20\x20\x20" , [1]="%1$3u%2$4.2f" } +}; +/* <<< GLOBALS <<< */ + +void Draw_Footer_Voltage_Fahrenheit(struct PKG_FLIP_FLOP *PFlop) +{ + const enum FORMULA_SCOPE fmt[2] = { + (SCOPE_OF_FORMULA(RO(Shm)->Proc.thermalFormula) != FORMULA_SCOPE_NONE), + (SCOPE_OF_FORMULA(RO(Shm)->Proc.voltageFormula) != FORMULA_SCOPE_NONE) + }; + + StrFormat(Buffer, 10+5+1, Format_Temp_Voltage[ fmt[0] ] [ fmt[1] ], + Cels2Fahr(PFlop->Thermal.Temp), + PFlop->Voltage.CPU); +} + +void Draw_Footer_Voltage_Celsius(struct PKG_FLIP_FLOP *PFlop) +{ + const enum FORMULA_SCOPE fmt[2] = { + (SCOPE_OF_FORMULA(RO(Shm)->Proc.thermalFormula) != FORMULA_SCOPE_NONE), + (SCOPE_OF_FORMULA(RO(Shm)->Proc.voltageFormula) != FORMULA_SCOPE_NONE) + }; + + StrFormat(Buffer, 10+5+1, Format_Temp_Voltage[ fmt[0] ] [ fmt[1] ], + PFlop->Thermal.Temp, + PFlop->Voltage.CPU); +} + +void (*Draw_Footer_Voltage_Temp[])(struct PKG_FLIP_FLOP*) = { + Draw_Footer_Voltage_Celsius, + Draw_Footer_Voltage_Fahrenheit +}; + +void Draw_Footer(Layer *layer, CUINT row) +{ /* Update Footer view area */ + struct PKG_FLIP_FLOP *PFlop = \ + &RO(Shm)->Proc.FlipFlop[!RO(Shm)->Proc.Toggle]; + + ATTRIBUTE *eventAttr[] = { + RSC(HOT_EVENT_COND0).ATTR(), + RSC(HOT_EVENT_COND1).ATTR(), + RSC(HOT_EVENT_COND2).ATTR(), + RSC(HOT_EVENT_COND3).ATTR(), + RSC(HOT_EVENT_COND4).ATTR() + }; + register unsigned int _hot = 0, _tmp = 0; + + if (!RO(Shm)->ProcessorEvents[eLOG] && !RO(Shm)->ProcessorEvents[eSTS]) + { + _hot = 0; + _tmp = 3; + } + else + { + if ((RO(Shm)->ProcessorEvents[eLOG] & HOT_LOG_EVENT_FILTER) + || (RO(Shm)->ProcessorEvents[eSTS] & HOT_STS_EVENT_FILTER)) + { + _hot = 4; + _tmp = 1; + } else { + _hot = 2; + _tmp = 3; + } + } + CUINT col[2] = { + Draw.Area.Footer.VoltTemp.Hot[0], + Draw.Area.Footer.VoltTemp.Hot[1] + }; + + LayerAt(layer, attr, col[1] , row) = eventAttr[_hot][0]; + LayerAt(layer, attr, col[1] + 1 , row) = eventAttr[_hot][1]; + LayerAt(layer, attr, col[1] + 2 , row) = eventAttr[_hot][2]; + LayerAt(layer, attr, col[0] + 8 , row) = eventAttr[_tmp][0]; + LayerAt(layer, attr, col[0] + 9 , row) = eventAttr[_tmp][1]; + LayerAt(layer, attr, col[0] + 10, row) = eventAttr[_tmp][2]; + + Draw_Footer_Voltage_Temp[Setting.fahrCels](PFlop); + + LayerAt(layer, code, col[0] + 8 , row) = (ASCII) Buffer[0]; + LayerAt(layer, code, col[0] + 9 , row) = (ASCII) Buffer[1]; + LayerAt(layer, code, col[0] + 10, row) = (ASCII) Buffer[2]; + LayerAt(layer, code, col[0] , row) = (ASCII) Buffer[3]; + LayerAt(layer, code, col[0] + 1 , row) = (ASCII) Buffer[4]; + LayerAt(layer, code, col[0] + 2 , row) = (ASCII) Buffer[5]; + LayerAt(layer, code, col[0] + 3 , row) = (ASCII) Buffer[6]; + + if (BITWISEAND(LOCKLESS, RO(Shm)->SysGate.Operation, 0x1) + && (RO(Shm)->SysGate.tickStep == RO(Shm)->SysGate.tickReset)) { + if ((Draw.Cache.procCount != RO(Shm)->SysGate.procCount) + || (Draw.Cache.FreeRAM != RO(Shm)->SysGate.memInfo.freeram)) + { + Draw.Cache.procCount = RO(Shm)->SysGate.procCount; + Draw.Cache.FreeRAM = RO(Shm)->SysGate.memInfo.freeram; + + PrintTaskMemory(layer, (row + 1), + RO(Shm)->SysGate.procCount, + RO(Shm)->SysGate.memInfo.freeram, + RO(Shm)->SysGate.memInfo.totalram); + } + } +} +#endif /* NO_FOOTER */ + +#ifndef NO_HEADER +void Draw_Header(Layer *layer, CUINT row) +{ /* Update Header view area */ + struct FLIP_FLOP *CFlop; + unsigned int digit[9]; + + /* Print the Top frequency in MHz Or the C0 C-State % load */ + if (!Draw.Flag.clkOrLd) + { + if (Draw.Load) { + const unsigned int top = RO(Shm)->Proc.Top.Abs; + CFlop = &RO(Shm)->Cpu[top].FlipFlop[!RO(Shm)->Cpu[top].Toggle]; + + Clock2LCD(layer, 0,row, CFlop->Absolute.Freq, + CFlop->Absolute.Ratio.Perf); + } else { + const unsigned int top = RO(Shm)->Proc.Top.Rel; + CFlop = &RO(Shm)->Cpu[top].FlipFlop[!RO(Shm)->Cpu[top].Toggle]; + + Clock2LCD(layer, 0,row, CFlop->Relative.Freq, + CFlop->Relative.Ratio); + } + } else { + if (Draw.Cache.TopAvg != RO(Shm)->Proc.Avg.C0) { + double percent = 100.f * RO(Shm)->Proc.Avg.C0; + Draw.Cache.TopAvg = RO(Shm)->Proc.Avg.C0; + + Load2LCD(layer, 0, row, percent); + } + } + /* Print the focused BCLK */ + row += 2; + + CFlop = &RO(Shm)->Cpu[ Draw.iClock + Draw.cpuScroll ] \ + .FlipFlop[ !RO(Shm)->Cpu[Draw.iClock + Draw.cpuScroll].Toggle ]; + + Dec2Digit(CFlop->Clock.Hz, digit); + + LayerAt(layer, code, 26 + 0, row) = digit[0] + '0'; + LayerAt(layer, code, 26 + 1, row) = digit[1] + '0'; + LayerAt(layer, code, 26 + 2, row) = digit[2] + '0'; + LayerAt(layer, code, 26 + 4, row) = digit[3] + '0'; + LayerAt(layer, code, 26 + 5, row) = digit[4] + '0'; + LayerAt(layer, code, 26 + 6, row) = digit[5] + '0'; + LayerAt(layer, code, 26 + 8, row) = digit[6] + '0'; + LayerAt(layer, code, 26 + 9, row) = digit[7] + '0'; + LayerAt(layer, code, 26 + 10, row) = digit[8] + '0'; +} +#endif /* NO_HEADER */ + +/* >>> GLOBALS >>> */ +#ifndef NO_LOWER +VIEW_FUNC Matrix_Layout_Monitor[VIEW_SIZE] = { + Layout_Monitor_Frequency, + Layout_Monitor_Instructions, + Layout_Monitor_Common, + Layout_Monitor_Common, + Layout_Monitor_Package, + Layout_Monitor_Tasks, + Layout_Monitor_Common, + Layout_Monitor_Common, + Layout_Monitor_Common, + Layout_Monitor_Common, + Layout_Monitor_Slice, + Layout_Monitor_Custom +}; + +VIEW_FUNC Matrix_Layout_Ruler[VIEW_SIZE] = { + Layout_Ruler_Frequency, + Layout_Ruler_Instructions, + Layout_Ruler_Cycles, + Layout_Ruler_CStates, + Layout_Ruler_Package, + Layout_Ruler_Tasks, + Layout_Ruler_Interrupts, + Layout_Ruler_Sensors, + Layout_Ruler_Voltage, + Layout_Ruler_Energy, + Layout_Ruler_Slice, + Layout_Ruler_Custom +}; +#endif /* NO_LOWER */ + +#ifndef NO_UPPER +VIEW_FUNC Matrix_Draw_Load[] = { + Draw_Relative_Load, + Draw_Absolute_Load +}; +#endif /* NO_UPPER */ + +#ifndef NO_LOWER +VIEW_FUNC Matrix_Draw_Monitor[VIEW_SIZE] = { + Draw_Monitor_Frequency, + Draw_Monitor_Instructions, + Draw_Monitor_Cycles, + Draw_Monitor_CStates, + Draw_Monitor_Package, + Draw_Monitor_Tasks, + Draw_Monitor_Interrupts, + Draw_Monitor_Sensors, + Draw_Monitor_Voltage, + Draw_Monitor_Energy, + Draw_Monitor_Slice, + Draw_Monitor_Custom +}; + +VIEW_FUNC Matrix_Draw_AltMon[VIEW_SIZE] = { + Draw_AltMonitor_Frequency, + Draw_AltMonitor_Common, + Draw_AltMonitor_Common, + Draw_AltMonitor_Common, + Draw_AltMonitor_Package, + Draw_AltMonitor_Tasks, + Draw_AltMonitor_Common, + Draw_AltMonitor_Power, + Draw_AltMonitor_Voltage, + Draw_AltMonitor_Power, + Draw_AltMonitor_Common, + Draw_AltMonitor_Custom +}; +#endif /* NO_LOWER */ +/* <<< GLOBALS <<< */ + +#ifndef NO_UPPER + #define Illuminates_Upper_CPU_At(_layer, _col, _row) \ + LayerAt(_layer, attr, _col, _row) = +#else + #define Illuminates_Upper_CPU_At(_layer, _col, _row) +#endif + +#ifndef NO_LOWER +#ifndef NO_UPPER + #define Illuminates_Lower_CPU_At(_layer, _col, _row) \ + LayerAt(_layer, attr, _col, (1 + _row + Draw.Area.MaxRows)) = +#else + #define Illuminates_Lower_CPU_At(_layer, _col, _row) \ + LayerAt(_layer, attr, _col, (_row)) = +#endif +#else + #define Illuminates_Lower_CPU_At(_layer, _col, _row) +#endif + +#define Illuminates_CPU(_layer, _row, _attr) \ +({ \ + Illuminates_Upper_CPU_At(_layer, 0, _row) \ + Illuminates_Lower_CPU_At(_layer, 0, _row) \ + Illuminates_Upper_CPU_At(_layer, 1, _row) \ + Illuminates_Lower_CPU_At(_layer, 1, _row) \ + Illuminates_Upper_CPU_At(_layer, 2, _row) \ + Illuminates_Lower_CPU_At(_layer, 2, _row) \ + \ + _attr; \ + \ +}) + +void Layout_Header_DualView_Footer(Layer *layer) +{ + unsigned int cpu; + CUINT row = 0; + +#ifndef NO_HEADER + Layout_Header(layer, row); +#endif + row += TOP_HEADER_ROW; +#ifndef NO_UPPER + Layout_Ruler_Load(layer, row); +#endif + for (cpu = Draw.cpuScroll; cpu < (Draw.cpuScroll + Draw.Area.MaxRows); cpu++) + { + Layout_CPU_To_String(cpu); +#ifndef NO_UPPER + Layout_CPU_To_View(layer, 0, row + 1); + + Layout_BCLK_To_View(layer, 0, row + 1); +#endif + row = row + 1; +#ifndef NO_LOWER +#ifndef NO_UPPER + if (Draw.View != V_PACKAGE) { + Layout_CPU_To_View(layer, 0, row + Draw.Area.MaxRows + 1); + } +#else + if (Draw.View != V_PACKAGE) { + Layout_CPU_To_View(layer, 0, row); + } +#endif +#endif + if (!BITVAL(RO(Shm)->Cpu[cpu].OffLine, OS)) + { + if (cpu == RO(Shm)->Proc.Service.Core) { + Illuminates_CPU(layer, row, RSC(UI).ATTR()[UI_ILLUMINATES_CPU_SP]); + } else if ((signed short) cpu == RO(Shm)->Proc.Service.Thread) { + Illuminates_CPU(layer, row, RSC(UI).ATTR()[UI_ILLUMINATES_CPU_SP]); + } else if ((signed short) cpu == RO(Shm)->Proc.Service.Hybrid) { + Illuminates_CPU(layer,row,RSC(UI).ATTR()[UI_ILLUMINATES_CPU_SP_HYBRID]); + } else { + Illuminates_CPU(layer, row, RSC(UI).ATTR()[UI_ILLUMINATES_CPU_ON]); + } +#ifndef NO_LOWER +#ifndef NO_UPPER + Matrix_Layout_Monitor[Draw.View](layer,cpu,row + Draw.Area.MaxRows + 1); +#else + Matrix_Layout_Monitor[Draw.View](layer,cpu,row); +#endif +#endif + } + else + { + Illuminates_CPU(layer, row, RSC(UI).ATTR()[UI_ILLUMINATES_CPU_OFF]); + +#ifndef NO_UPPER + ClearGarbage( dLayer, code, + (LOAD_LEAD - 1), row, + (Draw.Size.width - LOAD_LEAD + 1), 0x0); +#endif +#ifndef NO_LOWER +#ifndef NO_UPPER + ClearGarbage( dLayer, attr, + (LOAD_LEAD - 1), (row + Draw.Area.MaxRows + 1), + (Draw.Size.width - LOAD_LEAD + 1), + RSC(UI).ATTR()[UI_LAYOUT_ROW_CPU_OFFLINE].value ); + + ClearGarbage( dLayer, code, + (LOAD_LEAD - 1), (row + Draw.Area.MaxRows + 1), + (Draw.Size.width - LOAD_LEAD + 1), 0x0 ); +#else + ClearGarbage( dLayer, code, + (LOAD_LEAD - 1), row, + (Draw.Size.width - LOAD_LEAD + 1), 0x0 ); +#endif +#endif + } + } + row++; +#ifndef NO_LOWER +#ifndef NO_UPPER + row = Matrix_Layout_Ruler[Draw.View](layer, 0, row); +#else + row = Matrix_Layout_Ruler[Draw.View](layer, 0, TOP_HEADER_ROW); +#endif +#endif +#ifndef NO_FOOTER + Layout_Footer(layer, row); +#endif +} + +void Dynamic_Header_DualView_Footer(Layer *layer) +{ + unsigned int cpu; + CUINT row = 0; +#ifndef NO_HEADER + Draw_Header(layer, row); +#endif + row += TOP_HEADER_ROW; + + for (cpu = Draw.cpuScroll; cpu < (Draw.cpuScroll + Draw.Area.MaxRows); cpu++) + { + row++; + + if (!BITVAL(RO(Shm)->Cpu[cpu].OffLine, OS)) + { + if (!BITVAL(RO(Shm)->Cpu[cpu].OffLine, HW)) + { +#ifndef NO_UPPER + Matrix_Draw_Load[Draw.Load](layer, cpu, row); +#endif + } + /* Print the Per Core BCLK indicator (yellow) */ +#ifdef NO_UPPER + if (Draw.View != V_PACKAGE) { +#endif +#if !defined(NO_LOWER) || !defined(NO_UPPER) + LayerAt(layer, code, (LOAD_LEAD - 1), row) = + (Draw.iClock == (cpu - Draw.cpuScroll)) ? '~' : 0x20; +#endif +#ifdef NO_UPPER + } +#endif + +#ifndef NO_LOWER +#ifndef NO_UPPER + Matrix_Draw_Monitor[Draw.View](layer, cpu, row + Draw.Area.MaxRows + 1); +#else + Matrix_Draw_Monitor[Draw.View](layer, cpu, row); +#endif +#endif + } + } + row++; +#ifndef NO_LOWER +#ifndef NO_UPPER + row = Matrix_Draw_AltMon[Draw.View](layer, 0, row); +#else + row = Matrix_Draw_AltMon[Draw.View](layer, 0, TOP_HEADER_ROW); +#endif +#endif +#ifndef NO_FOOTER + Draw_Footer(layer, row); +#endif +} + +void Layout_Card_Core(Layer *layer, Card *card) +{ + unsigned int digit[3]; + unsigned int _cpu = card->data.dword.lo; + + Dec2Digit(_cpu, digit); + + if (!BITVAL(RO(Shm)->Cpu[_cpu].OffLine, OS)) + { + if (Setting.fahrCels) { + LayerDeclare( LAYOUT_CARD_CORE_ONLINE_COND1,(4 * INTER_WIDTH), + card->origin.col, (card->origin.row + 3), + hOnLine); + + LayerCopyAt(layer, hOnLine.origin.col, hOnLine.origin.row, + hOnLine.length, hOnLine.attr, hOnLine.code); + } else { + LayerDeclare( LAYOUT_CARD_CORE_ONLINE_COND0,(4 * INTER_WIDTH), + card->origin.col, (card->origin.row + 3), + hOnLine); + + LayerCopyAt(layer, hOnLine.origin.col, hOnLine.origin.row, + hOnLine.length, hOnLine.attr, hOnLine.code); + } + } else { + LayerDeclare( LAYOUT_CARD_CORE_OFFLINE, (4 * INTER_WIDTH), + card->origin.col, (card->origin.row + 3), + hOffLine); + + card->data.dword.hi = RENDER_KO; + + LayerFillAt(layer, card->origin.col, (card->origin.row + 1), + (4 * INTER_WIDTH), " _ _ _ _ ", + RSC(UI).ATTR()[UI_LAYOUT_CARD_CORE_OFFLINE]); + + LayerCopyAt(layer, hOffLine.origin.col, hOffLine.origin.row, + hOffLine.length, hOffLine.attr, hOffLine.code); + } + LayerAt(layer, code, + (card->origin.col + 2), + (card->origin.row + 3)) = digit[0] + '0'; + + LayerAt(layer, code, + (card->origin.col + 3), + (card->origin.row + 3)) = digit[1] + '0'; + + LayerAt(layer, code, + (card->origin.col + 4), + (card->origin.row + 3)) = digit[2] + '0'; +} + +void Layout_Card_CLK(Layer *layer, Card *card) +{ + LayerDeclare( LAYOUT_CARD_CLK, (4 * INTER_WIDTH), + card->origin.col, (card->origin.row + 3), + hCLK); + + LayerCopyAt( layer, hCLK.origin.col, hCLK.origin.row, + hCLK.length, hCLK.attr, hCLK.code); +} + +void Layout_Card_Uncore(Layer *layer, Card *card) +{ + LayerDeclare( LAYOUT_CARD_UNCORE, (4 * INTER_WIDTH), + card->origin.col, (card->origin.row + 3), + hUncore); + + StrFormat(Buffer, 10+1, "x%2u", + RO(Shm)->Uncore.Boost[UNCORE_BOOST(MAX)]); + + hUncore.code[ 8] = (ASCII) Buffer[0]; + hUncore.code[ 9] = (ASCII) Buffer[1]; + hUncore.code[10] = (ASCII) Buffer[2]; + + LayerCopyAt( layer, hUncore.origin.col, hUncore.origin.row, + hUncore.length, hUncore.attr, hUncore.code); +} + +void Layout_Card_Bus(Layer *layer, Card *card) +{ + LayerDeclare( LAYOUT_CARD_BUS, (4 * INTER_WIDTH), + card->origin.col, (card->origin.row + 3), + hBus); + + StrFormat(Buffer, 10+1, "%4u", RO(Shm)->Uncore.Bus.Rate); + hBus.code[5] = (ASCII) Buffer[0]; + hBus.code[6] = (ASCII) Buffer[1]; + hBus.code[7] = (ASCII) Buffer[2]; + hBus.code[8] = (ASCII) Buffer[3]; + + switch (RO(Shm)->Uncore.Unit.Bus_Rate) { + case MC_MHZ: + hBus.code[ 9] = 'H'; + hBus.code[10] = 'z'; + break; + case MC_MTS: + hBus.code[ 9] = 'M'; + hBus.code[10] = 'T'; + break; + case MC_MBS: + hBus.code[ 9] = 'B'; + hBus.code[10] = 's'; + break; + } + + LayerCopyAt( layer, hBus.origin.col, hBus.origin.row, + hBus.length, hBus.attr, hBus.code); + + Counter2LCD( layer, card->origin.col, card->origin.row, + (double) RO(Shm)->Uncore.Bus.Speed); +} + +static char Card_MC_Timing[(5*10)+5+1]; + +void Layout_Card_MC(Layer *layer, Card *card) +{ + LayerDeclare( LAYOUT_CARD_MC, (4 * INTER_WIDTH), + card->origin.col, (card->origin.row + 3), + hRAM); + + card->data.word.lo[0] = 0; + StrLenFormat(card->data.word.lo[1], Card_MC_Timing, + (5*10)+5+1, "%s", " - - - - - " ); + + unsigned short mc, cha, gotTimings = 0; + if (RO(Shm)->Uncore.CtrlCount > 0) { + for (mc = 0; mc < RO(Shm)->Uncore.CtrlCount && !gotTimings; mc++) { + if (RO(Shm)->Uncore.MC[mc].ChannelCount > 0) { + for (cha = 0; + cha < RO(Shm)->Uncore.MC[mc].ChannelCount && !gotTimings; + cha++) + { + if (RO(Shm)->Uncore.MC[mc].Channel[cha].Timing.tCL + || RO(Shm)->Uncore.MC[mc].Channel[cha].Timing.tRCD + || RO(Shm)->Uncore.MC[mc].Channel[cha].Timing.tRP + || RO(Shm)->Uncore.MC[mc].Channel[cha].Timing.tRAS) + { + StrLenFormat(card->data.word.lo[1], + Card_MC_Timing, (5*10)+5+1, "%u-%u-%u-%u-%uT", + RO(Shm)->Uncore.MC[mc].Channel[cha].Timing.tCL, + RO(Shm)->Uncore.MC[mc].Channel[cha].Timing.tRCD, + RO(Shm)->Uncore.MC[mc].Channel[cha].Timing.tRP, + RO(Shm)->Uncore.MC[mc].Channel[cha].Timing.tRAS, + RO(Shm)->Uncore.MC[mc].Channel[cha].Timing.CMD_Rate); + + gotTimings = 1; + } + } + } + } + Counter2LCD(layer, card->origin.col, card->origin.row, + (double) RO(Shm)->Uncore.CtrlSpeed); + } + LayerCopyAt( layer, hRAM.origin.col, hRAM.origin.row, + hRAM.length, hRAM.attr, hRAM.code); +} + +void Layout_Card_Load(Layer *layer, Card *card) +{ + LayerDeclare( LAYOUT_CARD_LOAD, (4 * INTER_WIDTH), + card->origin.col, (card->origin.row + 3), + hLoad); + + LayerCopyAt( layer, hLoad.origin.col, hLoad.origin.row, + hLoad.length, hLoad.attr, hLoad.code); +} + +void Layout_Card_Idle(Layer *layer, Card *card) +{ + LayerDeclare( LAYOUT_CARD_IDLE, (4 * INTER_WIDTH), + card->origin.col, (card->origin.row + 3), + hIdle); + + LayerCopyAt( layer, hIdle.origin.col, hIdle.origin.row, + hIdle.length, hIdle.attr, hIdle.code); +} + +void Layout_Card_RAM(Layer *layer, Card *card) +{ + LayerDeclare( LAYOUT_CARD_RAM, (4 * INTER_WIDTH), + card->origin.col, (card->origin.row + 3), + hMem); + + if (BITWISEAND(LOCKLESS, RO(Shm)->SysGate.Operation, 0x1)) { + unsigned long totalRAM, totalDimm = 0; + int unit; + char symbol = 0x20; + + if (RO(Shm)->Uncore.CtrlCount > 0) { + unsigned short mc, cha, slot; + for (mc = 0; mc < RO(Shm)->Uncore.CtrlCount; mc++) + for (cha = 0; cha < RO(Shm)->Uncore.MC[mc].ChannelCount; cha++) + for (slot = 0; slot < RO(Shm)->Uncore.MC[mc].SlotCount; slot++) { + totalDimm +=RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Size; + } + unit = ByteReDim(totalDimm, 3, &totalRAM); + if ((unit >= 0) && (unit < 4)) { + char symbols[4] = {'M', 'G', 'T', 'P'}; + symbol = symbols[unit]; + } + } else { + unit = ByteReDim(RO(Shm)->SysGate.memInfo.totalram, 3, &totalRAM); + if ((unit >= 0) && (unit < 4)) { + char symbols[4] = {'K', 'M', 'G', 'T'}; + symbol = symbols[unit]; + } + } + if (totalRAM > 99) { + hMem.attr[hMem.length-2] = RSC(UI).ATTR()[UI_LAYOUT_CARD_RAM_3DIGITS]; + StrFormat(Buffer, 20+1+1, "%3lu", totalRAM); + } else { + hMem.attr[hMem.length-2] = RSC(UI).ATTR()[UI_LAYOUT_CARD_RAM_2DIGITS]; + StrFormat(Buffer, 20+1+1, "%2lu%c", totalRAM, symbol); + } + memcpy(&hMem.code[8], Buffer, 3); + + LayerCopyAt( layer, hMem.origin.col, hMem.origin.row, + hMem.length, hMem.attr, hMem.code); + } else { + card->data.dword.hi = RENDER_KO; + } +} + +void Layout_Card_Task(Layer *layer, Card *card) +{ + LayerDeclare( LAYOUT_CARD_TASK, (4 * INTER_WIDTH), + card->origin.col, (card->origin.row + 3), + hSystem); + + if (BITWISEAND(LOCKLESS, RO(Shm)->SysGate.Operation, 0x1)) { + LayerCopyAt( layer, hSystem.origin.col, hSystem.origin.row, + hSystem.length, hSystem.attr, hSystem.code); + } else { + card->data.dword.hi = RENDER_KO; + } +} + +unsigned int MoveDashboardCursor(Coordinate *coord) +{ + const CUINT marginWidth = MARGIN_WIDTH + (4 * INTER_WIDTH); + const CUINT marginHeight = MARGIN_HEIGHT + INTER_HEIGHT; + const CUINT rightEdge = Draw.Size.width - marginWidth, + bottomEdge = Draw.Size.height + marginHeight; + + coord->col += marginWidth; + if (coord->col > rightEdge) { + coord->col = LEADING_LEFT; + coord->row += marginHeight; + } + if (coord->row > bottomEdge) { + return RENDER_KO; + } + return RENDER_OK; +} + +void Layout_Dashboard(Layer *layer) +{ + Coordinate coord = {.col = LEADING_LEFT, .row = LEADING_TOP}; + + Card *walker = cardList.head; + while (walker != NULL) { + walker->origin.col = coord.col; + walker->origin.row = coord.row; + walker->data.dword.hi = MoveDashboardCursor(&coord); + if (walker->data.dword.hi == RENDER_OK) { + walker->hook.Layout(layer, walker); + } + walker = GetNext(walker); + } +} + +void Draw_Card_Core(Layer *layer, Card *card) +{ + if (card->data.dword.hi == RENDER_OK) + { + const enum FORMULA_SCOPE + thermalScope = SCOPE_OF_FORMULA(RO(Shm)->Proc.thermalFormula); + + unsigned int _cpu = card->data.dword.lo; + + struct FLIP_FLOP *CFlop = \ + &RO(Shm)->Cpu[_cpu].FlipFlop[!RO(Shm)->Cpu[_cpu].Toggle]; + + ATTRIBUTE warning = RSC(UI).ATTR()[UI_DRAW_CARD_CORE_NOMINAL]; + + Clock2LCD(layer, card->origin.col, card->origin.row, + CFlop->Relative.Freq, CFlop->Relative.Ratio); + + if (CFlop->Thermal.Temp <= RO(Shm)->Cpu[ + _cpu + ].PowerThermal.Limit[SENSOR_LOWEST]) + { + warning = RSC(UI).ATTR()[UI_DRAW_CARD_CORE_LOW]; + } else { + if(CFlop->Thermal.Temp >= RO(Shm)->Cpu[ + _cpu + ].PowerThermal.Limit[SENSOR_HIGHEST]) + { + warning = RSC(UI).ATTR()[UI_DRAW_CARD_CORE_MEDIUM]; + } + } + if (CFlop->Thermal.Events[eSTS]) { + warning = RSC(UI).ATTR()[UI_DRAW_CARD_CORE_HIGH]; + } + + LayerAt(layer, attr, (card->origin.col + 6), (card->origin.row + 3)) = \ + LayerAt(layer, attr, (card->origin.col + 7), (card->origin.row + 3)) = \ + LayerAt(layer, attr, (card->origin.col + 8), (card->origin.row + 3)) = \ + warning; + LayerAt(layer, code, (card->origin.col + 6), (card->origin.row + 3)) = \ + LayerAt(layer, code, (card->origin.col + 7), (card->origin.row + 3)) = \ + LayerAt(layer, code, (card->origin.col + 8), (card->origin.row + 3)) = \ + 0x20; + switch (thermalScope) { + case FORMULA_SCOPE_NONE: + break; + case FORMULA_SCOPE_PKG: + if ( !(_cpu == RO(Shm)->Proc.Service.Core) ) { + break; + } + fallthrough; + case FORMULA_SCOPE_CORE: + if ( !( (RO(Shm)->Cpu[_cpu].Topology.ThreadID == 0) + || (RO(Shm)->Cpu[_cpu].Topology.ThreadID == -1)) ) { + break; + } + fallthrough; + case FORMULA_SCOPE_SMT: + { + unsigned int digit[3]; + Dec2Digit( Setting.fahrCels ? Cels2Fahr(CFlop->Thermal.Temp) + : CFlop->Thermal.Temp, digit ); + + LayerAt(layer, code, (card->origin.col + 6), (card->origin.row + 3)) = \ + digit[0] ? digit[0] + '0':0x20; + + LayerAt(layer, code, (card->origin.col + 7), (card->origin.row + 3)) = \ + (digit[0] | digit[1]) ? digit[1] + '0' : 0x20; + + LayerAt(layer, code, (card->origin.col + 8), (card->origin.row + 3)) = \ + digit[2] + '0'; + } + break; + } + } + else if (card->data.dword.hi == RENDER_KO) + { + CUINT row; + + card->data.dword.hi = RENDER_OFF; + + for (row = card->origin.row; row < card->origin.row + 4; row++) { + memset(&LayerAt(layer, attr, card->origin.col, row), 0, 4*INTER_WIDTH); + memset(&LayerAt(layer, code, card->origin.col, row), 0, 4*INTER_WIDTH); + } + } +} + +void Draw_Card_CLK(Layer *layer, Card *card) +{ + struct FLIP_FLOP *CFlop = \ + &RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].FlipFlop[ + !RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Toggle + ]; + struct PKG_FLIP_FLOP *PFlop = \ + &RO(Shm)->Proc.FlipFlop[!RO(Shm)->Proc.Toggle]; + + double bclk = (double)(PFlop->Delta.PCLK / RO(Shm)->Sleep.Interval); + + Counter2LCD(layer, card->origin.col, card->origin.row, bclk); + + StrFormat(Buffer, 6+1, "%5.1f", CLOCK_MHz(double, CFlop->Clock.Hz)); + + memcpy(&LayerAt(layer, code, (card->origin.col+2),(card->origin.row+3)), + Buffer, 5); +} + +void Draw_Card_Uncore(Layer *layer, Card *card) +{ + struct PKG_FLIP_FLOP *PFlop = \ + &RO(Shm)->Proc.FlipFlop[!RO(Shm)->Proc.Toggle]; + + double Uncore = CLOCK_MHz(double, PFlop->Uncore.FC0); + + Idle2LCD(layer, card->origin.col, card->origin.row, Uncore); +} + +void Draw_Card_MC(Layer *layer, Card *card) +{ + memcpy( &LayerAt(layer,code, (card->origin.col+1),(card->origin.row+3)), + &Card_MC_Timing[card->data.word.lo[0]], 10); + + card->data.word.lo[0]++; + if ((card->data.word.lo[0] + 10) > card->data.word.lo[1]) { + card->data.word.lo[0] = 0; + } +} + +void Draw_Card_Load(Layer *layer, Card* card) +{ + double percent = 100.f * RO(Shm)->Proc.Avg.C0; + + Load2LCD(layer, card->origin.col, card->origin.row, percent); +} + +void Draw_Card_Idle(Layer *layer, Card* card) +{ + double percent =( RO(Shm)->Proc.Avg.C1 + + RO(Shm)->Proc.Avg.C3 + + RO(Shm)->Proc.Avg.C6 + + RO(Shm)->Proc.Avg.C7 ) * 100.f; + + Idle2LCD(layer, card->origin.col, card->origin.row, percent); +} + +void Draw_Card_RAM(Layer *layer, Card *card) +{ + if (card->data.dword.hi == RENDER_OK) + { + if (RO(Shm)->SysGate.tickStep == RO(Shm)->SysGate.tickReset) { + unsigned long freeRAM; + int unit; + char symbol[4] = {'K', 'M', 'G', 'T'}; + double percent = (100.f * RO(Shm)->SysGate.memInfo.freeram) + / RO(Shm)->SysGate.memInfo.totalram; + + Sys2LCD(layer, card->origin.col, card->origin.row, percent); + + unit = ByteReDim(RO(Shm)->SysGate.memInfo.freeram, 6, &freeRAM); + StrFormat(Buffer, 20+1+1, "%5lu%c", freeRAM, symbol[unit]); + memcpy(&LayerAt(layer,code, (card->origin.col+1), (card->origin.row+3)), + Buffer, 6); + } + } + else if (card->data.dword.hi == RENDER_KO) { + CUINT row; + + card->data.dword.hi = RENDER_OFF; + + for (row = card->origin.row; row < card->origin.row + 4; row++) { + memset(&LayerAt(layer, attr, card->origin.col, row), 0, 4*INTER_WIDTH); + memset(&LayerAt(layer, code, card->origin.col, row), 0, 4*INTER_WIDTH); + } + } +} + +void Draw_Card_Task(Layer *layer, Card *card) +{ + if (card->data.dword.hi == RENDER_OK) + { + if (RO(Shm)->SysGate.tickStep == RO(Shm)->SysGate.tickReset) { + size_t pb, pe; + const int cl = (int) strnlen(RO(Shm)->SysGate.taskList[0].comm, 12), + hl = ((12 - cl) / 2) % 12, hr = (hl + (cl & 1)) % 12; + char stateStr[TASK_COMM_LEN]; + ATTRIBUTE *stateAttr; + stateAttr = StateToSymbol(RO(Shm)->SysGate.taskList[0].state, stateStr); + + StrFormat(Buffer, 3*12+11+3+5+1+1, "%.*s%.*s%.*s%zn%7d(%c)%zn%5u", + hl, hSpace, + cl, RO(Shm)->SysGate.taskList[0].comm, + hr, hSpace, + (ssize_t*)&pb, + RO(Shm)->SysGate.taskList[0].pid, + stateStr[0], + (ssize_t*)&pe, + RO(Shm)->SysGate.procCount); + + LayerCopyAt(layer, (card->origin.col + 0), + (card->origin.row + 1), + pb, + stateAttr, + Buffer); + + LayerFillAt(layer, (card->origin.col + 1), + (card->origin.row + 2), + pe - pb, + &Buffer[pb], + RSC(UI).ATTR()[UI_DRAW_CARD_TASK_FILL]); + + memcpy(&LayerAt(layer, code, (card->origin.col+6),(card->origin.row+3)), + &Buffer[pe], 5); + } + } + else if (card->data.dword.hi == RENDER_KO) { + CUINT row; + + card->data.dword.hi = RENDER_OFF; + + for (row = card->origin.row; row < card->origin.row + 4; row++) { + memset(&LayerAt(layer, attr, card->origin.col, row), 0, 4*INTER_WIDTH); + memset(&LayerAt(layer, code, card->origin.col, row), 0, 4*INTER_WIDTH); + } + } +} + +void Dont_Draw_Card(Layer *layer, Card *card) +{ + UNUSED(layer); + UNUSED(card); +} + +void Draw_Dashboard(Layer *layer) +{ + Card *walker = cardList.head; + while (walker != NULL) { + walker->hook.Draw(layer, walker); + walker = GetNext(walker); + } +} + +void AllocDashboard(void) +{ + unsigned int cpu; + Card *card = NULL; + for (cpu=0; (cpu < RO(Shm)->Proc.CPU.Count) && !BITVAL(Shutdown, SYNC); cpu++) + { + if ((card = CreateCard()) != NULL) { + card->data.dword.lo = cpu; + card->data.dword.hi = RENDER_OK; + + AppendCard(card, &cardList); + StoreCard(card, .Layout, Layout_Card_Core); + StoreCard(card, .Draw, Draw_Card_Core); + } + } + if ((card = CreateCard()) != NULL) { + card->data.dword.lo = 0; + card->data.dword.hi = RENDER_OK; + + AppendCard(card, &cardList); + StoreCard(card, .Layout, Layout_Card_CLK); + StoreCard(card, .Draw, Draw_Card_CLK); + } + if ((card = CreateCard()) != NULL) { + card->data.dword.lo = 0; + card->data.dword.hi = RENDER_OK; + + AppendCard(card, &cardList); + StoreCard(card, .Layout, Layout_Card_Uncore); + StoreCard(card, .Draw, Draw_Card_Uncore); + } + if ((card = CreateCard()) != NULL) { + card->data.dword.lo = 0; + card->data.dword.hi = RENDER_OK; + + AppendCard(card, &cardList); + StoreCard(card, .Layout, Layout_Card_Bus); + StoreCard(card, .Draw, Dont_Draw_Card); + } + if ((card = CreateCard()) != NULL) { + card->data.dword.lo = 0; + card->data.dword.hi = RENDER_OK; + + AppendCard(card, &cardList); + StoreCard(card, .Layout, Layout_Card_MC); + StoreCard(card, .Draw, Draw_Card_MC); + } + if ((card = CreateCard()) != NULL) { + card->data.dword.lo = 0; + card->data.dword.hi = RENDER_OK; + + AppendCard(card, &cardList); + StoreCard(card, .Layout, Layout_Card_Load); + StoreCard(card, .Draw, Draw_Card_Load); + } + if ((card = CreateCard()) != NULL) { + card->data.dword.lo = 0; + card->data.dword.hi = RENDER_OK; + + AppendCard(card, &cardList); + StoreCard(card, .Layout, Layout_Card_Idle); + StoreCard(card, .Draw, Draw_Card_Idle); + } + if ((card = CreateCard()) != NULL) { + card->data.dword.lo = 0; + card->data.dword.hi = RENDER_OK; + + AppendCard(card, &cardList); + StoreCard(card, .Layout, Layout_Card_RAM); + StoreCard(card, .Draw, Draw_Card_RAM); + } + if ((card = CreateCard()) != NULL) { + card->data.dword.lo = 0; + card->data.dword.hi = RENDER_OK; + + AppendCard(card, &cardList); + StoreCard(card, .Layout, Layout_Card_Task); + StoreCard(card, .Draw, Draw_Card_Task); + } +} + +void Layout_NoHeader_SingleView_NoFooter(Layer *layer) +{ + UNUSED(layer); +} + +void Dynamic_NoHeader_SingleView_NoFooter(Layer *layer) +{ + UNUSED(layer); +} + +REASON_CODE Top(char option) +{ +/* + SCREEN + __________________________ __________________________ +| MENU | | MENU | +| T | | | +| L HEADER | | NO_HEADER | +| R | | | +|--E ----------------------| | | +| A | | | +| A LOAD | | NO_UPPER | +| I | | | +|--D ----------------------| | | +| L | | | +| I MONITOR | | NO_LOWER | +| I | | | +|--N ----------------------| | | +| N | | | +| G FOOTER | | NO_FOOTER | +| G | | | +`__________________________' `__________________________' +*/ + + REASON_INIT(reason); + + TrapScreenSize(SIGWINCH); + + if (signal(SIGWINCH, TrapScreenSize) == SIG_ERR) { + REASON_SET(reason); + } + else if ((cTask=calloc(RO(Shm)->Proc.CPU.Count, sizeof(Coordinate))) == NULL) + { + REASON_SET(reason, RC_MEM_ERR); + } + else if (AllocAll(&Buffer) == ENOMEM) { + REASON_SET(reason, RC_MEM_ERR, ENOMEM); + } + else + { + AllocDashboard(); + + DISPOSAL_FUNC LayoutView[DISPOSAL_SIZE] = { + Layout_Header_DualView_Footer, + Layout_Dashboard, + Layout_NoHeader_SingleView_NoFooter + }; + DISPOSAL_FUNC DynamicView[DISPOSAL_SIZE] = { + Dynamic_Header_DualView_Footer, + Draw_Dashboard, + Dynamic_NoHeader_SingleView_NoFooter + }; + + Draw.Disposal = (option == 'd') ? D_DASHBOARD : D_MAINVIEW; + + AggregateRatio(); + + RECORDER_COMPUTE(Recorder, RO(Shm)->Sleep.Interval); + + LoadGeometries(BuildConfigFQN("CoreFreq")); + + SET_THEME(Draw.Theme); + + /* MAIN LOOP */ + while (!BITVAL(Shutdown, SYNC)) + { + do + { + if ((Draw.Flag.daemon=BITCLR(LOCKLESS, RW(Shm)->Proc.Sync, SYNC0)) == 0) + { + SCANKEY scan = {.key = 0}; + + if (GetKey(&scan, &RO(Shm)->Sleep.pollingWait) > 0) { + if (Shortcut(&scan) == -1) { + if (IsDead(&winList)) { + AppendWindow(CreateMenu(SCANKEY_F2, 0), &winList); + } + else if (Motion_Trigger(&scan,GetFocus(&winList),&winList) > 0) + { + Shortcut(&scan); + } + } + PrintWindowStack(&winList); + + break; + } else { + WindowsUpdate(&winList); + } + } + if (!RING_NULL(RW(Shm)->Error)) + { + RING_CTRL ctrl __attribute__ ((aligned(16))); + RING_READ(RW(Shm)->Error, ctrl); + + AppendWindow( + PopUpMessage(RSC(POPUP_DRIVER_TITLE).CODE(), &ctrl), + &winList ); + } + if (BITCLR(LOCKLESS, RW(Shm)->Proc.Sync, COMP0)) { + AggregateRatio(); + Draw.Flag.clear = 1; /* Compute required,clear the layout */ + } + if (BITCLR(LOCKLESS, RW(Shm)->Proc.Sync, NTFY0)) { + ClientFollowService(&localService, &RO(Shm)->Proc.Service, 0); + RECORDER_COMPUTE(Recorder, RO(Shm)->Sleep.Interval); + Draw.Flag.layout = 1; /* Platform changed, redraw layout */ + } + } while ( !BITVAL(Shutdown, SYNC) + && !Draw.Flag.daemon + && !Draw.Flag.layout + && !Draw.Flag.clear ) ; + + if (Draw.Flag.height & Draw.Flag.width) + { + if (Draw.Flag.clear) { + Draw.Flag.clear = 0; + Draw.Flag.layout = 1; + ResetLayer(dLayer, RSC(UI).ATTR()[UI_FUSE_RESET_LAYER]); + } + if (Draw.Flag.layout) { + Draw.Flag.layout = 0; + ResetLayer(sLayer, RSC(UI).ATTR()[UI_FUSE_PAINT_LAYER]); + LayoutView[Draw.Disposal](sLayer); + } + if (Draw.Flag.daemon) + { + DynamicView[Draw.Disposal](dLayer); + + /* Increment the BCLK indicator (skip offline CPU) */ + do { + Draw.iClock++; + if (Draw.iClock >= Draw.Area.MaxRows) { + Draw.iClock = 0; + } + } while (BITVAL(RO(Shm)->Cpu[Draw.iClock].OffLine, OS) + && (Draw.iClock != RO(Shm)->Proc.Service.Core)) ; + } + Draw_uBenchmark(dLayer); + UBENCH_RDCOUNTER(1); + + /* Write to the standard output. */ + Draw.Flag.layout = WriteConsole(Draw.Size); + + UBENCH_RDCOUNTER(2); + UBENCH_COMPUTE(); + } else { + fprintf(stderr, CUH RoK "Term(%d x %d) < View(%d x %u)\n", + Draw.Size.width,Draw.Size.height,MIN_WIDTH,Draw.Area.MinHeight); + } + } + SaveGeometries(BuildConfigFQN("CoreFreq")); + } + FreeAll(Buffer); + + if (cTask != NULL) { + free(cTask); + } + DestroyAllCards(&cardList); + + return reason; +} + +REASON_CODE Help(REASON_CODE reason, ...) +{ + va_list ap; + va_start(ap, reason); + switch (reason.rc) { + case RC_SUCCESS: + case RC_OK_SYSGATE: + case RC_OK_COMPUTE: + case RC_DRIVER_BASE ... RC_DRIVER_LAST: + break; + case RC_PERM_ERR: + case RC_MEM_ERR: + case RC_EXEC_ERR: + break; + case RC_CMD_SYNTAX: { + char *appName = va_arg(ap, char *); + printf((char *) RSC(ERROR_CMD_SYNTAX).CODE(), appName, + RC_SUCCESS, + RC_CMD_SYNTAX, + RC_SHM_FILE, + RC_SHM_MMAP, + RC_PERM_ERR, + RC_MEM_ERR, + RC_EXEC_ERR, + RC_SYS_CALL); + } + break; + case RC_SHM_FILE: + case RC_SHM_MMAP: { + char *shmFileName = va_arg(ap, char *); + char *sysMsg = strerror_l(reason.no, SYS_LOCALE()); + fprintf(stderr, (char *) RSC(ERROR_SHARED_MEM).CODE(), + reason.no, shmFileName, sysMsg, reason.ln); + } + break; + case RC_SYS_CALL: { + char *sysMsg = strerror(reason.no); + fprintf(stderr, (char *) RSC(ERROR_SYS_CALL).CODE(), + reason.no, sysMsg, reason.ln); + } + break; + } + va_end(ap); + return reason; +} + +void Emergency(int caught) +{ + switch (caught) { + case SIGINT: /* Press [CTRL] + [C] twice to force quit. */ + if (Buffer != NULL) + { /* UI is running if buffer is allocated */ + Window *win = SearchWinListById(SCANKEY_CTRL_x, &winList); + if (win == NULL) { + if (Shortcut(&(SCANKEY){.key = SCANKEY_CTRL_x}) == 0) + { + PrintWindowStack(&winList); + break; + } + } + } + fallthrough; + case SIGBUS: + case SIGFPE: + case SIGHUP: /* Terminal lost */ + case SIGILL: + case SIGSYS: + case SIGQUIT: + case SIGTERM: + case SIGSEGV: + case SIGTSTP: /* [CTRL] + [Z] */ + case SIGXCPU: + case SIGXFSZ: + case SIGSTKFLT: + BITSET(LOCKLESS, Shutdown, SYNC); + break; + } +} + +void TrapSignal(int operation) +{ + if (operation == 0) { + RING_WRITE_SUB_CMD( SESSION_CLI, RW(Shm)->Ring[1], + COREFREQ_SESSION_APP, (pid_t) 0 ); + } else { + const int ignored[] = { + SIGUSR1, SIGUSR2, SIGTTIN, SIGTTOU, SIGPWR, + SIGTRAP, SIGALRM, SIGPROF, SIGPIPE, SIGABRT, + SIGVTALRM, SIGCHLD, SIGWINCH, SIGIO, SIGSEGV + }, handled[] = { + SIGBUS, SIGFPE, SIGHUP, SIGILL, SIGINT, + SIGQUIT, SIGSYS, SIGTERM, SIGTSTP, + SIGXCPU, SIGXFSZ, SIGSTKFLT + }; + /* SIGKILL,SIGCONT,SIGSTOP,SIGURG : Reserved */ + const ssize_t ignoredCount = sizeof(ignored) / sizeof(int), + handledCount = sizeof(handled) / sizeof(int); + int signo; + + RING_WRITE_SUB_CMD( SESSION_CLI, RW(Shm)->Ring[1], + COREFREQ_SESSION_APP, getpid() ); + + for (signo = SIGRTMIN; signo <= SIGRTMAX; signo++) { + signal(signo, SIG_IGN); + } + for (signo = 0; signo < ignoredCount; signo++) { + signal(ignored[signo], SIG_IGN); + } + for (signo = 0; signo < handledCount; signo++) { + signal(handled[signo], Emergency); + } + } +} + +CHECK_DUPLICATE_KEY(0LLU); + +int main(int argc, char *argv[]) +{ + struct { + struct stat ro, rw; + } stat_st = { + .ro = {0}, + .rw = {0} + }; + struct + { + int ro, rw; + } fd = { + .ro = -1, + .rw = -1 + }; + int idx = 0; + char *program = strdup(argv[0]), + *appName = program != NULL ? basename(program) : argv[idx], + option = 't', trailing = '\0'; + + REASON_INIT(reason); + + LOCALE(IN); + + if ((argc >= 2) && (argv[++idx][0] == '-')) { + option = argv[idx][1]; + } + if (option == 'h') { + REASON_SET(reason, RC_CMD_SYNTAX, 0); + reason = Help(reason, appName); + } else if (option == 'v') { + printf(COREFREQ_VERSION"\n"); + } else if ( ((fd.ro = shm_open(RO(SHM_FILENAME), O_RDONLY, + S_IRUSR|S_IWUSR + |S_IRGRP|S_IROTH) ) !=-1) + && ((fd.rw = shm_open(RW(SHM_FILENAME), O_RDWR, + S_IRUSR|S_IWUSR + |S_IRGRP|S_IWGRP + |S_IROTH|S_IWOTH) ) !=-1) ) + { + if ((fstat(fd.ro, &stat_st.ro) != -1) + && (fstat(fd.rw, &stat_st.rw) != -1)) + { + const size_t roSize = (size_t) stat_st.ro.st_size, + rwSize = (size_t) stat_st.rw.st_size; + + if (((RO(Shm) = mmap( NULL, roSize, + PROT_READ, MAP_SHARED, + fd.ro, 0)) != MAP_FAILED ) + && ((RW(Shm) = mmap( NULL, rwSize, + PROT_READ|PROT_WRITE, MAP_SHARED, + fd.rw, 0)) != MAP_FAILED )) + { + if (CHK_FOOTPRINT(RO(Shm)->FootPrint,MAX_FREQ_HZ, + CORE_COUNT, + TASK_ORDER, + COREFREQ_MAJOR, + COREFREQ_MINOR, + COREFREQ_REV)) + { + ClientFollowService(&localService, &RO(Shm)->Proc.Service, 0); + + #define CONDITION_RDTSCP() \ + ( (RO(Shm)->Proc.Features.Inv_TSC == 1) \ + || (RO(Shm)->Proc.Features.RDTSCP == 1) ) + + #define CONDITION_RDPMC() \ + ((RO(Shm)->Proc.PM_version >= 1) \ + && (BITVAL(RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].SystemRegister.CR4,\ + CR4_PCE) == 1) ) + + UBENCH_SETUP(CONDITION_RDTSCP(), CONDITION_RDPMC()); + + do { + switch (option) { + case 'n': + printf("\n"); + break; + case 'O': + switch (argv[idx][2]) { + case 'a': + Draw.Load = 1; + break; + case 'p': + Draw.Flag.avgOrPC = 1; + break; + case 'k': + Draw.Unit.Memory = 10 * 0; + break; + case 'm': + Draw.Unit.Memory = 10 * 1; + break; + case 'g': + Draw.Unit.Memory = 10 * 2; + break; + case 'W': + Setting.jouleWatt = !Setting.jouleWatt; + break; + case 'F': + Setting.fahrCels = 1; + break; + case 'J': + if (++idx < argc) { + enum SMB_STRING usrIdx = SMB_BOARD_NAME; + if ((sscanf(argv[idx], "%u%c", &usrIdx, &trailing) != 1) + || (usrIdx >= SMB_STRING_COUNT)) { + goto SYNTAX_ERROR; + } else { + Draw.SmbIndex = usrIdx; + } + } + break; + case 'Y': + Setting.secret = 0; + break; + case 'E': + if (++idx < argc) { + enum THEMES theme; + if ((sscanf(argv[idx], "%u%c", &theme, &trailing) != 1) + || (theme >= THM_CNT)) { + goto SYNTAX_ERROR; + } else { + Draw.Theme = theme; + } + } + break; + default: /* `/0' */ + goto SYNTAX_ERROR; + break; + } + break; + case 'B': + reason = SysInfoSMBIOS(NULL, 80, NULL, NULL); + break; + case 'k': + if (BITWISEAND(LOCKLESS, RO(Shm)->SysGate.Operation, 0x1)) { + reason = SysInfoKernel(NULL, 80, NULL, NULL); + } + break; + case 's': + { + Window tty = {.matrix.size.wth = 4}; + + AggregateRatio(); + reason = SysInfoProc(NULL, 80, NULL, NULL); + if (IS_REASON_SUCCESSFUL(reason) == 0) { break; } + + Print_v1(NULL, NULL, SCANKEY_VOID, NULL, NULL, 80, 0, ""); + Print_v1(NULL, NULL, SCANKEY_VOID, NULL, NULL, + 80, 0, (char *) &(RSC(ISA_TITLE).CODE()[1])); + reason = SysInfoISA(&tty, NULL, NULL); + if (IS_REASON_SUCCESSFUL(reason) == 0) { break; } + + Print_v1(NULL, NULL, SCANKEY_VOID, NULL, NULL, 80, 0, ""); + Print_v1(NULL, NULL, SCANKEY_VOID, NULL, NULL, + 80, 0, (char *) &(RSC(FEATURES_TITLE).CODE()[1])); + reason = SysInfoFeatures(NULL, 80, NULL, NULL); + if (IS_REASON_SUCCESSFUL(reason) == 0) { break; } + + Print_v1(NULL, NULL, SCANKEY_VOID, NULL, NULL, 80, 0, ""); + Print_v1(NULL, NULL, SCANKEY_VOID, NULL, NULL, + 80, 0, (char *) &(RSC(TECHNOLOGIES_TITLE).CODE()[1])); + reason = SysInfoTech(NULL, 80, NULL, NULL); + if (IS_REASON_SUCCESSFUL(reason) == 0) { break; } + + Print_v1(NULL, NULL, SCANKEY_VOID, NULL, NULL, 80, 0, ""); + Print_v1(NULL, NULL, SCANKEY_VOID, NULL, NULL, + 80, 0, (char *) &(RSC(PERF_MON_TITLE).CODE()[1])); + reason = SysInfoPerfMon(NULL, 80, NULL, NULL); + if (IS_REASON_SUCCESSFUL(reason) == 0) { break; } + + Print_v1(NULL, NULL, SCANKEY_VOID, NULL, NULL, 80, 0, ""); + Print_v1(NULL, NULL, SCANKEY_VOID, NULL, NULL, + 80, 0, (char *) &(RSC(POWER_THERMAL_TITLE).CODE()[1])); + reason = SysInfoPwrThermal(NULL, 80, NULL, NULL); + if (IS_REASON_SUCCESSFUL(reason) == 0) { break; } + } + break; + case 'z': + reason = SysInfoPerfCaps(NULL, 80, NULL, NULL); + break; + case 'j': + JsonSysInfo(RO(Shm)); + break; + case 'm': + { + Window tty = {.matrix.size.wth = 6}; + Topology(&tty, NULL, NULL); + } + break; + case 'M': + { + Window tty = {.matrix.size.wth = MC_MATX}; + + switch (RO(Shm)->Uncore.Unit.DDR_Ver) { + case 5: + case 4: + case 3: + case 2: + default: + MemoryController(&tty, NULL, NULL, Timing_DDR3); + break; + } + } + break; + case 'R': + { + Window tty = {.matrix.size.wth = 17}; + SystemRegisters(&tty, NULL, NULL); + } + break; + case 'i': + { + int iter = -1; + if (++idx < argc) { + if ((sscanf(argv[idx], "%d%c", &iter, &trailing) != 1) + || (iter <= 0)) + { + goto SYNTAX_ERROR; + } + } + TrapSignal(1); + Instructions((unsigned int) iter); + TrapSignal(0); + } + break; + case 'c': + { + int iter = -1; + if (++idx < argc) { + if ((sscanf(argv[idx], "%d%c", &iter, &trailing) != 1) + || (iter <= 0)) + { + goto SYNTAX_ERROR; + } + } + TrapSignal(1); + Counters((unsigned int) iter); + TrapSignal(0); + } + break; + case 'C': + { + int iter = -1; + if (++idx < argc) { + if ((sscanf(argv[idx], "%d%c", &iter, &trailing) != 1) + || (iter <= 0)) + { + goto SYNTAX_ERROR; + } + } + TrapSignal(1); + Sensors((unsigned int) iter); + TrapSignal(0); + } + break; + case 'V': + { + int iter = -1; + if (++idx < argc) { + if ((sscanf(argv[idx], "%d%c", &iter, &trailing) != 1) + || (iter <= 0)) + { + goto SYNTAX_ERROR; + } + } + TrapSignal(1); + Voltage((unsigned int) iter); + TrapSignal(0); + } + break; + case 'W': + { + int iter = -1; + if (++idx < argc) { + if ((sscanf(argv[idx], "%d%c", &iter, &trailing) != 1) + || (iter <= 0)) + { + goto SYNTAX_ERROR; + } + } + TrapSignal(1); + Power((unsigned int) iter); + TrapSignal(0); + } + break; + case 'g': + { + int iter = -1; + if (++idx < argc) { + if ((sscanf(argv[idx], "%d%c", &iter, &trailing) != 1) + || (iter <= 0)) + { + goto SYNTAX_ERROR; + } + } + TrapSignal(1); + Package((unsigned int) iter); + TrapSignal(0); + } + break; + case 'd': + fallthrough; + case 't': + if (++idx < argc) { + struct { + enum VIEW view; + char *first; + } opt[] = { + { V_FREQ , "frequency" }, + { V_INST , "instructions"}, + { V_CYCLES , "core" }, + { V_CSTATES , "idle" }, + { V_PACKAGE , "package" }, + { V_TASKS , "tasks" }, + { V_INTR , "interrupts" }, + { V_SENSORS , "sensors" }, + { V_VOLTAGE , "voltage" }, + { V_ENERGY , "power" }, + { V_SLICE , "slices" }, + { V_CUSTOM , "custom" } + }, *pOpt, *lOpt = &opt[sizeof(opt)/sizeof(opt[0])]; + for (pOpt = opt; pOpt < lOpt; pOpt++) + { + const size_t llen = strlen(pOpt->first); + const size_t rlen = strlen(argv[idx]); + const ssize_t nlen = (ssize_t) llen - (ssize_t) rlen; + if ((nlen >= 0) + && (strncmp(pOpt->first, argv[idx], rlen) == 0)) + { + Draw.View = pOpt->view; + break; + } + } + if (pOpt == lOpt) { + goto SYNTAX_ERROR; + } + } + TERMINAL(IN); + + TrapSignal(1); + reason = Top(option); + TrapSignal(0); + + TERMINAL(OUT); + break; + default: + SYNTAX_ERROR: + { + REASON_SET(reason, RC_CMD_SYNTAX, 0); + reason = Help(reason, appName); + idx = argc; + } + break; + } + } while ( (++idx < argc) + && (argv[idx][0] == '-') + && ((option = argv[idx][1]) != '\0') ); + + if (munmap(RO(Shm), roSize) == -1) { + REASON_SET(reason, RC_SHM_MMAP); + reason = Help(reason, RO(SHM_FILENAME)); + } + if (munmap(RW(Shm), rwSize) == -1) { + REASON_SET(reason, RC_SHM_MMAP); + reason = Help(reason, RW(SHM_FILENAME)); + } + } else { + char *wrongVersion = malloc(10+5+5+5+1); + REASON_SET(reason, RC_SHM_MMAP, EPERM); + if (wrongVersion != NULL) { + StrFormat(wrongVersion, 10+5+5+5+1, + "Version %hu.%hu.%hu", + RO(Shm)->FootPrint.major, + RO(Shm)->FootPrint.minor, + RO(Shm)->FootPrint.rev); + reason = Help(reason, wrongVersion); + free(wrongVersion); + } + munmap(RO(Shm), roSize); + munmap(RW(Shm), rwSize); + } + } else { + REASON_SET(reason, RC_SHM_MMAP); + reason = Help(reason, RO(SHM_FILENAME)); + } + } else { + REASON_SET(reason, RC_SHM_FILE); + reason = Help(reason, RO(SHM_FILENAME)); + } + if (close(fd.ro) == -1) { + REASON_SET(reason, RC_SHM_FILE); + reason = Help(reason, RO(SHM_FILENAME)); + } + if (close(fd.rw) == -1) { + REASON_SET(reason, RC_SHM_FILE); + reason = Help(reason, RO(SHM_FILENAME)); + } + } else { + REASON_SET(reason, RC_SHM_FILE); + reason = Help(reason, RO(SHM_FILENAME)); + } + LOCALE(OUT); + + if (program != NULL) { + free(program); + } + return reason.rc; +} diff --git a/aarch64/corefreq-cli.h b/aarch64/corefreq-cli.h new file mode 100644 index 00000000..955d9540 --- /dev/null +++ b/aarch64/corefreq-cli.h @@ -0,0 +1,724 @@ +/* + * CoreFreq + * Copyright (C) 2015-2024 CYRIL COURTIAT + * Licenses: GPL2 + */ + +#define CLEAR_EVENT_MASK 0x000000000000007eLLU + +#define CLOCK_SOURCE_MASK 0x000000000000000fLLU + +#define TRACK_TASK 0x0200000000000000LLU +#define TRACK_MASK 0x00000000007fffffLLU + +#define CPU_ONLINE 0x0000080000000000LLU +#define CPU_OFFLINE 0x0000100000000000LLU +#define CPU_STATE_MASK 0x0000180000000000LLU +#define CPU_SELECT 0x0000200000000000LLU +#define CPU_MASK 0x00000000000000ffLLU +#define RATIO_MASK 0x000000000000ffffLLU + +#define BOXKEY_CSTATE_MASK 0x00000000000000f0LLU + +#define BOXKEY_TURBO_CLOCK 0x00010000 +#define BOXKEY_TURBO_CLOCK_NC 0x00020000LLU + +#define BOXKEY_RATIO_CLOCK 0x00040000 +#define BOXKEY_RATIO_CLOCK_OR 0x00080000LLU + +#define BOXKEY_CFGTDP_CLOCK 0x00220000 +#define BOXKEY_CFGTDP_CLOCK_OR 0x00200000LLU + +#define BOXKEY_UNCORE_CLOCK 0x00400000 +#define BOXKEY_UNCORE_CLOCK_OR 0x00800000LLU + +#define BOXKEY_RATIO_SELECT_OR 0x08000000LLU + +#define CLOCKMOD_RATIO_MASK 0x0000ffff + +#define OPS_RECORDER_MASK 0x00000000000000f0LLU + +#define SMBIOS_STRING_INDEX 0x0010000000000000 +#define SMBIOS_STRING_MASK 0x00000000000000ffLLU + +#define BOXKEY_EVT_OR 0x3000000000020001LLU +#define BOXKEY_TDP_OR 0x3000000000021100LLU +#define BOXKEY_PLX_OP 0x3000000000021200LLU +#define BOXKEY_PL1_OR (BOXKEY_PLX_OP | (0x8 << PL1)) +#define BOXKEY_PL2_OR (BOXKEY_PLX_OP | (0x8 << PL2)) + +#define BOXKEY_TDP_MASK 0x0000000000000007LLU + +#define BOXKEY_TDC_OR 0x3000000000021400LLU +#define BOXKEY_TDC_MASK 0x3000000000021410LLU + + +#define BOXKEY_THM_OR 0x3000000000021800LLU +#define BOXKEY_THM_OP 0x3000000000021810LLU + +#define BOXKEY_TW_OR 0x3000000000024100LLU +#define BOXKEY_TW_OP 0x3000000000024200LLU + +#define BOXKEY_ROUTE_MASK 0x00000000000000f0LLU + +enum KEY_ENUM { + SORTBY_STATE = 0x0100000000000009LLU + F_STATE, + SORTBY_RTIME = 0x0100000000000009LLU + F_RTIME, + SORTBY_UTIME = 0x0100000000000009LLU + F_UTIME, + SORTBY_STIME = 0x0100000000000009LLU + F_STIME, + SORTBY_PID = 0x0100000000000009LLU + F_PID, + SORTBY_COMM = 0x0100000000000009LLU + F_COMM, + + OPS_INTERVAL = 0x1000000000001000LLU, + OPS_INTERVAL_100 = 0x1000000000001001LLU, + OPS_INTERVAL_150 = 0x1000000000001011LLU, + OPS_INTERVAL_250 = 0x1000000000001021LLU, + OPS_INTERVAL_500 = 0x1000000000001031LLU, + OPS_INTERVAL_750 = 0x1000000000001041LLU, + OPS_INTERVAL_1000 = 0x1000000000001051LLU, + OPS_INTERVAL_1500 = 0x1000000000001061LLU, + OPS_INTERVAL_2000 = 0x1000000000001071LLU, + OPS_INTERVAL_2500 = 0x1000000000001081LLU, + OPS_INTERVAL_3000 = 0x1000000000001091LLU, + OPS_AUTOCLOCK = 0x1000000000002000LLU, + OPS_AUTOCLOCK_OFF = 0x1000000000002001LLU, + OPS_AUTOCLOCK_ON = 0x1000000000002002LLU, + OPS_EXPERIMENTAL = 0x1000000000004000LLU, + OPS_EXPERIMENTAL_OFF = 0x1000000000004001LLU, + OPS_EXPERIMENTAL_ON = 0x1000000000004002LLU, + OPS_INTERRUPTS = 0x1000000000008000LLU, + OPS_INTERRUPTS_OFF = 0x1000000000008001LLU, + OPS_INTERRUPTS_ON = 0x1000000000008002LLU, + OPS_CPU_IDLE = 0x1000000000008010LLU, + OPS_CPU_IDLE_OFF = 0x1000000000008011LLU, + OPS_CPU_IDLE_ON = 0x1000000000008012LLU, + OPS_CPU_FREQ = 0x1000000000008020LLU, + OPS_CPU_FREQ_OFF = 0x1000000000008021LLU, + OPS_CPU_FREQ_ON = 0x1000000000008022LLU, + OPS_GOVERNOR = 0x1000000000008040LLU, + OPS_GOVERNOR_OFF = 0x1000000000008041LLU, + OPS_GOVERNOR_ON = 0x1000000000008042LLU, + OPS_CLOCK_SOURCE = 0x1000000000008080LLU, + OPS_CLOCK_SOURCE_1 = 0x1000000000008081LLU, + OPS_CLOCK_SOURCE_2 = 0x1000000000008082LLU, + OPS_CLOCK_SOURCE_3 = 0x1000000000008083LLU, + OPS_CLOCK_SOURCE_4 = 0x1000000000008084LLU, + OPS_CLOCK_SOURCE_5 = 0x1000000000008085LLU, + OPS_CLOCK_SOURCE_6 = 0x1000000000008086LLU, + OPS_CLOCK_SOURCE_7 = 0x1000000000008087LLU, + OPS_CLOCK_SOURCE_SEL = 0x100000000000808dLLU, + OPS_CLOCK_SOURCE_OFF = 0x100000000000808eLLU, + OPS_CLOCK_SOURCE_ON = 0x100000000000808fLLU, + OPS_IDLE_ROUTE = 0x1000000000008100LLU, + OPS_ROUTE_DFLT = OPS_IDLE_ROUTE | 1 | ( ROUTE_DEFAULT << 4 ), + OPS_ROUTE_IO = OPS_IDLE_ROUTE | 1 | ( ROUTE_IO << 4 ), + OPS_ROUTE_HALT = OPS_IDLE_ROUTE | 1 | ( ROUTE_HALT << 4 ), + OPS_ROUTE_MWAIT = OPS_IDLE_ROUTE | 1 | ( ROUTE_MWAIT << 4 ), + OPS_RECORDER = 0x1000000000010000LLU, + OPS_RECORDER_RESET = 0x1000000000010010LLU, + OPS_RECORDER_X002 = 0x1000000000010020LLU, + OPS_RECORDER_X010 = 0x1000000000010030LLU, + OPS_RECORDER_X020 = 0x1000000000010040LLU, + OPS_RECORDER_X060 = 0x1000000000010050LLU, + OPS_RECORDER_X090 = 0x1000000000010060LLU, + OPS_RECORDER_X120 = 0x1000000000010070LLU, + OPS_RECORDER_X240 = 0x1000000000010080LLU, + OPS_THERMAL_SCOPE = 0x1000000000020000LLU, + OPS_VOLTAGE_SCOPE = 0x1000000000021000LLU, + OPS_POWER_SCOPE = 0x1000000000022000LLU, + OPS_THERMAL_SCOPE_NONE = OPS_THERMAL_SCOPE|(7 ^ FORMULA_SCOPE_NONE), + OPS_THERMAL_SCOPE_SMT = OPS_THERMAL_SCOPE|(7 ^ FORMULA_SCOPE_SMT), + OPS_THERMAL_SCOPE_CORE = OPS_THERMAL_SCOPE|(7 ^ FORMULA_SCOPE_CORE), + OPS_THERMAL_SCOPE_PKG = OPS_THERMAL_SCOPE|(7 ^ FORMULA_SCOPE_PKG), + OPS_VOLTAGE_SCOPE_NONE = OPS_VOLTAGE_SCOPE|(7 ^ FORMULA_SCOPE_NONE), + OPS_VOLTAGE_SCOPE_SMT = OPS_VOLTAGE_SCOPE|(7 ^ FORMULA_SCOPE_SMT), + OPS_VOLTAGE_SCOPE_CORE = OPS_VOLTAGE_SCOPE|(7 ^ FORMULA_SCOPE_CORE), + OPS_VOLTAGE_SCOPE_PKG = OPS_VOLTAGE_SCOPE|(7 ^ FORMULA_SCOPE_PKG), + OPS_POWER_SCOPE_NONE = OPS_POWER_SCOPE | (7 ^ FORMULA_SCOPE_NONE), + OPS_POWER_SCOPE_SMT = OPS_POWER_SCOPE | (7 ^ FORMULA_SCOPE_SMT), + OPS_POWER_SCOPE_CORE = OPS_POWER_SCOPE | (7 ^ FORMULA_SCOPE_CORE), + OPS_POWER_SCOPE_PKG = OPS_POWER_SCOPE | (7 ^ FORMULA_SCOPE_PKG), + + BOXKEY_HWP = 0x3000000000004020LLU, + BOXKEY_HWP_ON = 0x3000000000004021LLU, + BOXKEY_HWP_EPP = 0x3000000000004040LLU, + BOXKEY_HWP_EPP_MIN = 0x3000000000004041LLU, + BOXKEY_HWP_EPP_020 = 0x3000000000004042LLU, + BOXKEY_HWP_EPP_040 = 0x3000000000004043LLU, + BOXKEY_HWP_EPP_060 = 0x3000000000004044LLU, + BOXKEY_HWP_EPP_MED = 0x3000000000004045LLU, + BOXKEY_HWP_EPP_0A0 = 0x3000000000004046LLU, + BOXKEY_HWP_EPP_PWR = 0x3000000000004047LLU, + BOXKEY_HWP_EPP_0E0 = 0x3000000000004048LLU, + BOXKEY_HWP_EPP_MAX = 0x3000000000004049LLU, + BOXKEY_FMW_CPPC = 0x3000000000004025LLU, + BOXKEY_FMW_CPPC_OFF = 0x3000000000004027LLU, + + BOXKEY_TOOLS_MACHINE = 0x3000000000010000LLU, + BOXKEY_TOOLS_ATOMIC = 0x3000000000010010LLU, + BOXKEY_TOOLS_CRC32 = 0x3000000000010020LLU, + BOXKEY_TOOLS_CONIC = 0x3000000000011000LLU, + BOXKEY_TOOLS_CONIC0 = 0x3000000000011401LLU, + BOXKEY_TOOLS_CONIC1 = 0x3000000000011411LLU, + BOXKEY_TOOLS_CONIC2 = 0x3000000000011421LLU, + BOXKEY_TOOLS_CONIC3 = 0x3000000000011431LLU, + BOXKEY_TOOLS_CONIC4 = 0x3000000000011441LLU, + BOXKEY_TOOLS_CONIC5 = 0x3000000000011451LLU, + BOXKEY_TOOLS_TURBO_RND = 0x3000000000012001LLU, + BOXKEY_TOOLS_TURBO_RR = 0x3000000000012011LLU, + BOXKEY_TOOLS_TURBO_CPU = 0x3000000000012021LLU, + BOXKEY_TOOLS_MONTE_CARLO= 0x3000000000012041LLU, + + BOXKEY_LANG_ENGLISH = 0x3000000000014021LLU, + BOXKEY_LANG_FRENCH = 0x3000000000014022LLU, + BOXKEY_THEME_DFLT = 0x3000000000014081LLU, + BOXKEY_THEME_USR1 = 0x3000000000014082LLU, + BOXKEY_THEME_USR2 = 0x3000000000014083LLU, + + BOXKEY_LIMIT_IDLE_STATE = 0x3000000000014800LLU, + BOXKEY_LIMIT_IDLE_ST00 = 0x3000000000014801LLU, + BOXKEY_LIMIT_IDLE_ST01 = 0x3000000000014811LLU, + BOXKEY_LIMIT_IDLE_ST02 = 0x3000000000014821LLU, + BOXKEY_LIMIT_IDLE_ST03 = 0x3000000000014831LLU, + BOXKEY_LIMIT_IDLE_ST04 = 0x3000000000014841LLU, + BOXKEY_LIMIT_IDLE_ST05 = 0x3000000000014851LLU, + BOXKEY_LIMIT_IDLE_ST06 = 0x3000000000014861LLU, + BOXKEY_LIMIT_IDLE_ST07 = 0x3000000000014871LLU, + BOXKEY_LIMIT_IDLE_ST08 = 0x3000000000014881LLU, + BOXKEY_LIMIT_IDLE_ST09 = 0x3000000000014891LLU, + BOXKEY_LIMIT_IDLE_ST10 = 0x30000000000148a1LLU, + + BOXKEY_CLR_ALL_EVENTS = BOXKEY_EVT_OR ^ 0x1, + BOXKEY_CLR_THM_SENSOR = BOXKEY_EVT_OR | (LSHIFT_THERMAL_LOG << 1), + BOXKEY_CLR_PROCHOT_LOG = BOXKEY_EVT_OR | (LSHIFT_PROCHOT_LOG << 1), + BOXKEY_CLR_THM_CRIT = BOXKEY_EVT_OR | (LSHIFT_CRITIC_LOG << 1), + BOXKEY_CLR_THM_THOLD1 = BOXKEY_EVT_OR | (LSHIFT_THOLD1_LOG << 1), + BOXKEY_CLR_THM_THOLD2 = BOXKEY_EVT_OR | (LSHIFT_THOLD2_LOG << 1), + BOXKEY_CLR_PWR_LIMIT = BOXKEY_EVT_OR | (LSHIFT_POWER_LIMIT << 1), + BOXKEY_CLR_CUR_LIMIT = BOXKEY_EVT_OR | (LSHIFT_CURRENT_LIMIT << 1), + BOXKEY_CLR_X_DOMAIN = BOXKEY_EVT_OR | (LSHIFT_CROSS_DOMAIN << 1), + BOXKEY_CLR_CORE_HOT = BOXKEY_EVT_OR | (LSHIFT_CORE_HOT_LOG << 1), + BOXKEY_CLR_CORE_THM = BOXKEY_EVT_OR | (LSHIFT_CORE_THM_LOG << 1), + BOXKEY_CLR_CORE_RES = BOXKEY_EVT_OR | (LSHIFT_CORE_RES_LOG << 1), + BOXKEY_CLR_CORE_AVG = BOXKEY_EVT_OR | (LSHIFT_CORE_AVG_LOG << 1), + BOXKEY_CLR_CORE_VRT = BOXKEY_EVT_OR | (LSHIFT_CORE_VRT_LOG << 1), + BOXKEY_CLR_CORE_TDC = BOXKEY_EVT_OR | (LSHIFT_CORE_TDC_LOG << 1), + BOXKEY_CLR_CORE_PL1 = BOXKEY_EVT_OR | (LSHIFT_CORE_PL1_LOG << 1), + BOXKEY_CLR_CORE_PL2 = BOXKEY_EVT_OR | (LSHIFT_CORE_PL2_LOG << 1), + BOXKEY_CLR_CORE_EDP = BOXKEY_EVT_OR | (LSHIFT_CORE_EDP_LOG << 1), + BOXKEY_CLR_CORE_BST = BOXKEY_EVT_OR | (LSHIFT_CORE_BST_LOG << 1), + BOXKEY_CLR_CORE_ATT = BOXKEY_EVT_OR | (LSHIFT_CORE_ATT_LOG << 1), + BOXKEY_CLR_CORE_TVB = BOXKEY_EVT_OR | (LSHIFT_CORE_TVB_LOG << 1), + BOXKEY_CLR_GFX_HOT = BOXKEY_EVT_OR | (LSHIFT_GFX_HOT_LOG << 1), + BOXKEY_CLR_GFX_THM = BOXKEY_EVT_OR | (LSHIFT_GFX_THM_LOG << 1), + BOXKEY_CLR_GFX_AVG = BOXKEY_EVT_OR | (LSHIFT_GFX_AVG_LOG << 1), + BOXKEY_CLR_GFX_VRT = BOXKEY_EVT_OR | (LSHIFT_GFX_VRT_LOG << 1), + BOXKEY_CLR_GFX_TDC = BOXKEY_EVT_OR | (LSHIFT_GFX_TDC_LOG << 1), + BOXKEY_CLR_GFX_PL1 = BOXKEY_EVT_OR | (LSHIFT_GFX_PL1_LOG << 1), + BOXKEY_CLR_GFX_PL2 = BOXKEY_EVT_OR | (LSHIFT_GFX_PL2_LOG << 1), + BOXKEY_CLR_GFX_EDP = BOXKEY_EVT_OR | (LSHIFT_GFX_EDP_LOG << 1), + BOXKEY_CLR_GFX_EFF = BOXKEY_EVT_OR | (LSHIFT_GFX_EFF_LOG << 1), + BOXKEY_CLR_RING_HOT = BOXKEY_EVT_OR | (LSHIFT_RING_HOT_LOG << 1), + BOXKEY_CLR_RING_THM = BOXKEY_EVT_OR | (LSHIFT_RING_THM_LOG << 1), + BOXKEY_CLR_RING_AVG = BOXKEY_EVT_OR | (LSHIFT_RING_AVG_LOG << 1), + BOXKEY_CLR_RING_VRT = BOXKEY_EVT_OR | (LSHIFT_RING_VRT_LOG << 1), + BOXKEY_CLR_RING_TDC = BOXKEY_EVT_OR | (LSHIFT_RING_TDC_LOG << 1), + BOXKEY_CLR_RING_PL1 = BOXKEY_EVT_OR | (LSHIFT_RING_PL1_LOG << 1), + BOXKEY_CLR_RING_PL2 = BOXKEY_EVT_OR | (LSHIFT_RING_PL2_LOG << 1), + BOXKEY_CLR_RING_EDP = BOXKEY_EVT_OR | (LSHIFT_RING_EDP_LOG << 1), + + BOXKEY_TDP_PKG = BOXKEY_TDP_OR | (PWR_DOMAIN(PKG) << 5), + BOXKEY_TDP_CORES = BOXKEY_TDP_OR | (PWR_DOMAIN(CORES) << 5), + BOXKEY_TDP_UNCORE = BOXKEY_TDP_OR | (PWR_DOMAIN(UNCORE) << 5), + BOXKEY_TDP_RAM = BOXKEY_TDP_OR | (PWR_DOMAIN(RAM) << 5), + BOXKEY_TDP_PLATFORM = BOXKEY_TDP_OR | (PWR_DOMAIN(PLATFORM) << 5), + + BOXKEY_TW1_PKG = BOXKEY_TW_OR | (PWR_DOMAIN(PKG) << 5)|PL1, + BOXKEY_TW1_CORES = BOXKEY_TW_OR | (PWR_DOMAIN(CORES) << 5)|PL1, + BOXKEY_TW1_UNCORE = BOXKEY_TW_OR | (PWR_DOMAIN(UNCORE) << 5)|PL1, + BOXKEY_TW1_RAM = BOXKEY_TW_OR | (PWR_DOMAIN(RAM) << 5)|PL1, + BOXKEY_TW1_PLATFORM = BOXKEY_TW_OR | (PWR_DOMAIN(PLATFORM)<< 5)|PL1, + BOXKEY_TW2_PKG = BOXKEY_TW_OR | (PWR_DOMAIN(PKG) << 5)|PL2, + BOXKEY_TW2_CORES = BOXKEY_TW_OR | (PWR_DOMAIN(CORES) << 5)|PL2, + BOXKEY_TW2_UNCORE = BOXKEY_TW_OR | (PWR_DOMAIN(UNCORE) << 5)|PL2, + BOXKEY_TW2_RAM = BOXKEY_TW_OR | (PWR_DOMAIN(RAM) << 5)|PL2, + BOXKEY_TW2_PLATFORM = BOXKEY_TW_OR | (PWR_DOMAIN(PLATFORM)<< 5)|PL2, + + BOXKEY_TDC = BOXKEY_TDC_OR, + + BOXKEY_THM = BOXKEY_THM_OR, + + BOXKEY_TURBO_CLOCK_1C = ((BOXKEY_TURBO_CLOCK_NC | 1) << 32), + BOXKEY_TURBO_CLOCK_2C = ((BOXKEY_TURBO_CLOCK_NC | 2) << 32), + BOXKEY_TURBO_CLOCK_3C = ((BOXKEY_TURBO_CLOCK_NC | 3) << 32), + BOXKEY_TURBO_CLOCK_4C = ((BOXKEY_TURBO_CLOCK_NC | 4) << 32), + BOXKEY_TURBO_CLOCK_5C = ((BOXKEY_TURBO_CLOCK_NC | 5) << 32), + BOXKEY_TURBO_CLOCK_6C = ((BOXKEY_TURBO_CLOCK_NC | 6) << 32), + BOXKEY_TURBO_CLOCK_7C = ((BOXKEY_TURBO_CLOCK_NC | 7) << 32), + BOXKEY_TURBO_CLOCK_8C = ((BOXKEY_TURBO_CLOCK_NC | 8) << 32), + BOXKEY_TURBO_CLOCK_9C = ((BOXKEY_TURBO_CLOCK_NC | 9) << 32), + BOXKEY_TURBO_CLOCK_10C = ((BOXKEY_TURBO_CLOCK_NC | 10) << 32), + BOXKEY_TURBO_CLOCK_11C = ((BOXKEY_TURBO_CLOCK_NC | 11) << 32), + BOXKEY_TURBO_CLOCK_12C = ((BOXKEY_TURBO_CLOCK_NC | 12) << 32), + BOXKEY_TURBO_CLOCK_13C = ((BOXKEY_TURBO_CLOCK_NC | 13) << 32), + BOXKEY_TURBO_CLOCK_14C = ((BOXKEY_TURBO_CLOCK_NC | 14) << 32), + BOXKEY_TURBO_CLOCK_15C = ((BOXKEY_TURBO_CLOCK_NC | 15) << 32), + BOXKEY_TURBO_CLOCK_16C = ((BOXKEY_TURBO_CLOCK_NC | 16) << 32), + BOXKEY_TURBO_CLOCK_17C = ((BOXKEY_TURBO_CLOCK_NC | 17) << 32), + BOXKEY_TURBO_CLOCK_18C = ((BOXKEY_TURBO_CLOCK_NC | 18) << 32), + + BOXKEY_RATIO_CLOCK_TGT = ((BOXKEY_RATIO_CLOCK_OR|CLOCK_MOD_TGT) << 32), + BOXKEY_RATIO_CLOCK_MAX = ((BOXKEY_RATIO_CLOCK_OR|CLOCK_MOD_MAX) << 32), + BOXKEY_RATIO_CLOCK_MIN = ((BOXKEY_RATIO_CLOCK_OR|CLOCK_MOD_MIN) << 32), + BOXKEY_RATIO_CLOCK_HWP_TGT =((BOXKEY_RATIO_CLOCK_OR|CLOCK_MOD_HWP_TGT)<<32), + BOXKEY_RATIO_CLOCK_HWP_MAX =((BOXKEY_RATIO_CLOCK_OR|CLOCK_MOD_HWP_MAX)<<32), + BOXKEY_RATIO_CLOCK_HWP_MIN =((BOXKEY_RATIO_CLOCK_OR|CLOCK_MOD_HWP_MIN)<<32), + + BOXKEY_RATIO_ACTIVATION =((BOXKEY_CFGTDP_CLOCK_OR|CLOCK_MOD_ACT) << 32), + + BOXKEY_UNCORE_CLOCK_MAX =((BOXKEY_UNCORE_CLOCK_OR|CLOCK_MOD_MAX) << 32), + BOXKEY_UNCORE_CLOCK_MIN =((BOXKEY_UNCORE_CLOCK_OR|CLOCK_MOD_MIN) << 32) +}; + +#if defined(FEAT_DBG) && (FEAT_DBG >= 9) && (FEAT_DBG < 100) +#define CHECK_DUPLICATE_KEY(_val) \ +int CheckDuplicateKey(void) \ +{ enum KEY_ENUM _key = _val; \ + switch (_key) { \ + case SORTBY_STATE: \ + case SORTBY_RTIME: \ + case SORTBY_UTIME: \ + case SORTBY_STIME: \ + case SORTBY_PID: \ + case SORTBY_COMM: \ + \ + case OPS_INTERVAL: \ + case OPS_INTERVAL_100: \ + case OPS_INTERVAL_150: \ + case OPS_INTERVAL_250: \ + case OPS_INTERVAL_500: \ + case OPS_INTERVAL_750: \ + case OPS_INTERVAL_1000: \ + case OPS_INTERVAL_1500: \ + case OPS_INTERVAL_2000: \ + case OPS_INTERVAL_2500: \ + case OPS_INTERVAL_3000: \ + case OPS_AUTOCLOCK: \ + case OPS_AUTOCLOCK_OFF: \ + case OPS_AUTOCLOCK_ON: \ + case OPS_EXPERIMENTAL: \ + case OPS_EXPERIMENTAL_OFF: \ + case OPS_EXPERIMENTAL_ON: \ + case OPS_INTERRUPTS: \ + case OPS_INTERRUPTS_OFF: \ + case OPS_INTERRUPTS_ON: \ + case OPS_CPU_IDLE: \ + case OPS_CPU_IDLE_OFF: \ + case OPS_CPU_IDLE_ON: \ + case OPS_CPU_FREQ: \ + case OPS_CPU_FREQ_OFF: \ + case OPS_CPU_FREQ_ON: \ + case OPS_GOVERNOR: \ + case OPS_GOVERNOR_OFF: \ + case OPS_GOVERNOR_ON: \ + case OPS_CLOCK_SOURCE: \ + case OPS_CLOCK_SOURCE_1: \ + case OPS_CLOCK_SOURCE_2: \ + case OPS_CLOCK_SOURCE_3: \ + case OPS_CLOCK_SOURCE_4: \ + case OPS_CLOCK_SOURCE_5: \ + case OPS_CLOCK_SOURCE_6: \ + case OPS_CLOCK_SOURCE_7: \ + case OPS_CLOCK_SOURCE_SEL: \ + case OPS_CLOCK_SOURCE_OFF: \ + case OPS_CLOCK_SOURCE_ON: \ + case OPS_IDLE_ROUTE: \ + case OPS_ROUTE_DFLT: \ + case OPS_ROUTE_IO: \ + case OPS_ROUTE_HALT: \ + case OPS_ROUTE_MWAIT: \ + case OPS_RECORDER: \ + case OPS_RECORDER_RESET: \ + case OPS_RECORDER_X002: \ + case OPS_RECORDER_X010: \ + case OPS_RECORDER_X020: \ + case OPS_RECORDER_X060: \ + case OPS_RECORDER_X090: \ + case OPS_RECORDER_X120: \ + case OPS_RECORDER_X240: \ + case OPS_THERMAL_SCOPE: \ + case OPS_VOLTAGE_SCOPE: \ + case OPS_POWER_SCOPE: \ + case OPS_THERMAL_SCOPE_NONE: \ + case OPS_THERMAL_SCOPE_SMT: \ + case OPS_THERMAL_SCOPE_CORE: \ + case OPS_THERMAL_SCOPE_PKG: \ + case OPS_VOLTAGE_SCOPE_NONE: \ + case OPS_VOLTAGE_SCOPE_SMT: \ + case OPS_VOLTAGE_SCOPE_CORE: \ + case OPS_VOLTAGE_SCOPE_PKG: \ + case OPS_POWER_SCOPE_NONE: \ + case OPS_POWER_SCOPE_SMT: \ + case OPS_POWER_SCOPE_CORE: \ + case OPS_POWER_SCOPE_PKG: \ + case BOXKEY_HWP: \ + case BOXKEY_HWP_ON: \ + case BOXKEY_HWP_EPP: \ + case BOXKEY_HWP_EPP_MIN: \ + case BOXKEY_HWP_EPP_020: \ + case BOXKEY_HWP_EPP_040: \ + case BOXKEY_HWP_EPP_060: \ + case BOXKEY_HWP_EPP_MED: \ + case BOXKEY_HWP_EPP_0A0: \ + case BOXKEY_HWP_EPP_PWR: \ + case BOXKEY_HWP_EPP_0E0: \ + case BOXKEY_HWP_EPP_MAX: \ + case BOXKEY_FMW_CPPC: \ + case BOXKEY_FMW_CPPC_OFF: \ + \ + case BOXKEY_TOOLS_MACHINE: \ + case BOXKEY_TOOLS_ATOMIC: \ + case BOXKEY_TOOLS_CRC32: \ + case BOXKEY_TOOLS_CONIC: \ + case BOXKEY_TOOLS_CONIC0: \ + case BOXKEY_TOOLS_CONIC1: \ + case BOXKEY_TOOLS_CONIC2: \ + case BOXKEY_TOOLS_CONIC3: \ + case BOXKEY_TOOLS_CONIC4: \ + case BOXKEY_TOOLS_CONIC5: \ + case BOXKEY_TOOLS_TURBO_RND: \ + case BOXKEY_TOOLS_TURBO_RR: \ + case BOXKEY_TOOLS_TURBO_CPU: \ + case BOXKEY_TOOLS_MONTE_CARLO: \ + \ + case BOXKEY_LANG_ENGLISH: \ + case BOXKEY_LANG_FRENCH: \ + case BOXKEY_THEME_DFLT: \ + case BOXKEY_THEME_USR1: \ + case BOXKEY_THEME_USR2: \ + \ + case BOXKEY_LIMIT_IDLE_STATE: \ + case BOXKEY_LIMIT_IDLE_ST00: \ + case BOXKEY_LIMIT_IDLE_ST01: \ + case BOXKEY_LIMIT_IDLE_ST02: \ + case BOXKEY_LIMIT_IDLE_ST03: \ + case BOXKEY_LIMIT_IDLE_ST04: \ + case BOXKEY_LIMIT_IDLE_ST05: \ + case BOXKEY_LIMIT_IDLE_ST06: \ + case BOXKEY_LIMIT_IDLE_ST07: \ + case BOXKEY_LIMIT_IDLE_ST08: \ + case BOXKEY_LIMIT_IDLE_ST09: \ + case BOXKEY_LIMIT_IDLE_ST10: \ + \ + case BOXKEY_CLR_ALL_EVENTS: \ + case BOXKEY_CLR_THM_SENSOR: \ + case BOXKEY_CLR_PROCHOT_LOG: \ + case BOXKEY_CLR_THM_CRIT: \ + case BOXKEY_CLR_THM_THOLD1: \ + case BOXKEY_CLR_THM_THOLD2: \ + case BOXKEY_CLR_PWR_LIMIT: \ + case BOXKEY_CLR_CUR_LIMIT: \ + case BOXKEY_CLR_X_DOMAIN: \ + case BOXKEY_CLR_CORE_HOT: \ + case BOXKEY_CLR_CORE_THM: \ + case BOXKEY_CLR_CORE_RES: \ + case BOXKEY_CLR_CORE_AVG: \ + case BOXKEY_CLR_CORE_VRT: \ + case BOXKEY_CLR_CORE_TDC: \ + case BOXKEY_CLR_CORE_PL1: \ + case BOXKEY_CLR_CORE_PL2: \ + case BOXKEY_CLR_CORE_EDP: \ + case BOXKEY_CLR_CORE_BST: \ + case BOXKEY_CLR_CORE_ATT: \ + case BOXKEY_CLR_CORE_TVB: \ + case BOXKEY_CLR_GFX_HOT: \ + case BOXKEY_CLR_GFX_THM: \ + case BOXKEY_CLR_GFX_AVG: \ + case BOXKEY_CLR_GFX_VRT: \ + case BOXKEY_CLR_GFX_TDC: \ + case BOXKEY_CLR_GFX_PL1: \ + case BOXKEY_CLR_GFX_PL2: \ + case BOXKEY_CLR_GFX_EDP: \ + case BOXKEY_CLR_GFX_EFF: \ + case BOXKEY_CLR_RING_HOT: \ + case BOXKEY_CLR_RING_THM: \ + case BOXKEY_CLR_RING_AVG: \ + case BOXKEY_CLR_RING_VRT: \ + case BOXKEY_CLR_RING_TDC: \ + case BOXKEY_CLR_RING_PL1: \ + case BOXKEY_CLR_RING_PL2: \ + case BOXKEY_CLR_RING_EDP: \ + \ + case BOXKEY_TDP_PKG: \ + case BOXKEY_TDP_CORES: \ + case BOXKEY_TDP_UNCORE: \ + case BOXKEY_TDP_RAM: \ + case BOXKEY_TDP_PLATFORM: \ + \ + case BOXKEY_TW1_PKG: \ + case BOXKEY_TW1_CORES: \ + case BOXKEY_TW1_UNCORE: \ + case BOXKEY_TW1_RAM: \ + case BOXKEY_TW1_PLATFORM: \ + case BOXKEY_TW2_PKG: \ + case BOXKEY_TW2_CORES: \ + case BOXKEY_TW2_UNCORE: \ + case BOXKEY_TW2_RAM: \ + case BOXKEY_TW2_PLATFORM: \ + \ + case BOXKEY_TDC: \ + \ + case BOXKEY_THM: \ + \ + case BOXKEY_TURBO_CLOCK_1C: \ + case BOXKEY_TURBO_CLOCK_2C: \ + case BOXKEY_TURBO_CLOCK_3C: \ + case BOXKEY_TURBO_CLOCK_4C: \ + case BOXKEY_TURBO_CLOCK_5C: \ + case BOXKEY_TURBO_CLOCK_6C: \ + case BOXKEY_TURBO_CLOCK_7C: \ + case BOXKEY_TURBO_CLOCK_8C: \ + case BOXKEY_TURBO_CLOCK_9C: \ + case BOXKEY_TURBO_CLOCK_10C: \ + case BOXKEY_TURBO_CLOCK_11C: \ + case BOXKEY_TURBO_CLOCK_12C: \ + case BOXKEY_TURBO_CLOCK_13C: \ + case BOXKEY_TURBO_CLOCK_14C: \ + case BOXKEY_TURBO_CLOCK_15C: \ + case BOXKEY_TURBO_CLOCK_16C: \ + case BOXKEY_TURBO_CLOCK_17C: \ + case BOXKEY_TURBO_CLOCK_18C: \ + \ + case BOXKEY_RATIO_CLOCK_TGT: \ + case BOXKEY_RATIO_CLOCK_MAX: \ + case BOXKEY_RATIO_CLOCK_MIN: \ + case BOXKEY_RATIO_CLOCK_HWP_TGT: \ + case BOXKEY_RATIO_CLOCK_HWP_MAX: \ + case BOXKEY_RATIO_CLOCK_HWP_MIN: \ + \ + case BOXKEY_RATIO_ACTIVATION: \ + \ + case BOXKEY_UNCORE_CLOCK_MAX: \ + case BOXKEY_UNCORE_CLOCK_MIN: \ + return 0; \ + } \ + return -1; \ +} +#else +#define CHECK_DUPLICATE_KEY(_val) +#endif /* FEAT_DBG */ + +#define POWERED(bit) ( (bit) ? (char*) RSC(PRESENT).CODE() \ + : (char*) RSC(MISSING).CODE() ) + +#define ENABLED(bit) ( (bit) ? (char*) RSC(ON).CODE() \ + : (char*) RSC(OFF).CODE() ) + +#define MARGIN_WIDTH 2 +#define MARGIN_HEIGHT 1 +#define INTER_WIDTH 3 +#define INTER_HEIGHT (3 + 1) +#define LEADING_LEFT (MIN_WIDTH / (MARGIN_WIDTH + (4 * INTER_WIDTH))) +#define LEADING_TOP 1 + +#define LOAD_LEAD 4 + +typedef struct { + Coordinate origin; + CUINT length; + ATTRIBUTE *attr; + ASCII *code; +} LAYER_DECL_ST; + +#define LayerDeclare(_ID, _len, _col, _row, _var) \ + LAYER_DECL_ST _var = { \ + .origin = { \ + .col = _col, \ + .row = _row \ + }, \ + .length = _len, \ + .attr = RSC(_ID).ATTR(), \ + .code = RSC(_ID).CODE() \ + } + +typedef char HBCLK[11 + 1]; + +enum DISPOSAL { + D_MAINVIEW, + D_DASHBOARD, + D_ASCIITEST +}; + +#define DISPOSAL_SIZE (1 + D_ASCIITEST) + +enum VIEW { + V_FREQ, + V_INST, + V_CYCLES, + V_CSTATES, + V_PACKAGE, + V_TASKS, + V_INTR, + V_SENSORS, + V_VOLTAGE, + V_ENERGY, + V_SLICE, + V_CUSTOM +}; + +#define VIEW_SIZE (1 + V_CUSTOM) + +typedef void (*DISPOSAL_FUNC)(Layer*); + +typedef CUINT (*VIEW_FUNC)(Layer*, const unsigned int, CUINT); + +#define CELL_ARGS Window *win, \ + unsigned long long key, \ + ATTRIBUTE *attrib, \ + ASCII *item, \ + unsigned int *cellPadding + +typedef TGrid* (*CELL_FUNC)(CELL_ARGS); +typedef void (*CPU_ITEM_CALLBACK)(unsigned int, ASCII*); +typedef void (*PKG_ITEM_CALLBACK)(ASCII*); +typedef void (*UPDATE_CALLBACK)(TGrid*, DATA_TYPE[]); + +#define RENDER_OK 0x000 +#define RENDER_KO 0x010 +#define RENDER_OFF 0x100 + +#define RECORDER_DEFAULT 30 + +#define RECORDER_COMPUTE(_recorder, _interval) \ +({ \ + _recorder.Reset = ( (_recorder.Ratios[_recorder.Select] \ + * RECORDER_DEFAULT \ + * 1000) / _interval ); \ +}) + +#define RECORDER_SECONDS(_tick, _interval) \ + ((_interval * _tick) / 1000) + +#if defined(UBENCH) && UBENCH == 1 + #define Draw_uBenchmark(layer) \ + ({ \ + if (Draw.Flag.uBench) { \ + int len = snprintf(Buffer, 20+1, "%llu", UBENCH_METRIC(0)); \ + if (len > 0) \ + LayerFillAt( layer, 0, 0, len, Buffer, \ + RSC(UI).ATTR()[UI_LAYOUT_UBENCH] ); \ + } \ + }) +#else + #define Draw_uBenchmark(layer) {} +#endif /* UBENCH */ + +struct SETTING_ST { + unsigned int + fahrCels: 1-0, /* 0:Celsius || 1:Fahrenheit */ + jouleWatt: 2-1, /* 0:Joule || 1:Watt */ + secret : 3-2, /* 0:Show || 1:Hide Secret Data */ + _padding: 32-3; +}; + +struct RULER_ST { + double Minimum, + Maximum, + Median; + + unsigned int Top[BOOST(SIZE)], + Uniq[BOOST(SIZE)], + Count; + struct TOPOF { + unsigned int Top; + enum RATIO_BOOST Boost; + } TopOf; +}; + +struct DRAW_ST { + struct { + #ifndef NO_HEADER + double TopAvg; + #endif + #ifndef NO_FOOTER + unsigned long FreeRAM; + int procCount; + #endif + } Cache; + struct { + unsigned int + layout : 1-0 , /* Draw layout */ + clear : 2-1 , /* Clear screen */ + height : 3-2 , /* Valid height */ + width : 4-3 , /* Valid width */ + daemon : 5-4 , /* Draw dynamic */ + taskVal : 6-5 , /* Display task's value */ + avgOrPC : 7-6 , /* C-states average || % pkg states */ + clkOrLd : 8-7 , /* Relative freq. || % load */ + #if defined(UBENCH) && UBENCH == 1 + uBench : 9-8 , /* Display UI micro-benchmark */ + #endif + _padding: 32-9 ; + } Flag; + enum VIEW View; + enum DISPOSAL Disposal; + SCREEN_SIZE Size; + struct { + CUINT MinHeight; + CUINT MaxRows; + CUINT LoadWidth; + #ifndef NO_FOOTER + struct { + struct { + CUINT Hot[2]; + } VoltTemp; + struct { + CUINT Count, + Free, + Total; + } TaskMem; + } Footer; + #endif + } Area; + unsigned int iClock, + cpuScroll, + Load; + struct { + unsigned int Memory; + } Unit; + enum SMB_STRING SmbIndex; + enum THEMES Theme; + #ifndef NO_UPPER + BitCC garbage; + #endif /* NO_UPPER */ +}; + +struct RECORDER_ST { + unsigned int Reset, + Select, + Ratios[]; +}; + +#define HOT_LOG_EVENT_FILTER ( EVENT_PROCHOT_LOG \ + | EVENT_CRITIC_LOG \ + | EVENT_CORE_HOT_LOG \ + | EVENT_GFX_HOT_LOG \ + | EVENT_RING_HOT_LOG ) + +#define HOT_STS_EVENT_FILTER ( EVENT_THERMAL_STS \ + | EVENT_PROCHOT_STS \ + | EVENT_CRITIC_TMP \ + | EVENT_THOLD1_STS \ + | EVENT_THOLD2_STS \ + | EVENT_CORE_THM_STS \ + | EVENT_CORE_HOT_STS \ + | EVENT_GFX_THM_STS \ + | EVENT_GFX_HOT_STS \ + | EVENT_RING_THM_STS \ + | EVENT_RING_HOT_STS ) + +#define STATUS_EVENT_FILTER ( EVENT_THERMAL_STS \ + | EVENT_PROCHOT_STS \ + | EVENT_CRITIC_TMP \ + | EVENT_THOLD1_STS \ + | EVENT_THOLD2_STS ) diff --git a/corefreq-ui.c b/aarch64/corefreq-ui.c similarity index 99% rename from corefreq-ui.c rename to aarch64/corefreq-ui.c index d06e0262..34e40c03 100644 --- a/corefreq-ui.c +++ b/aarch64/corefreq-ui.c @@ -1,6 +1,6 @@ /* * CoreFreq - * Copyright (C) 2015-2023 CYRIL COURTIAT + * Copyright (C) 2015-2024 CYRIL COURTIAT * Licenses: GPL2 */ @@ -2225,7 +2225,11 @@ void _LOCALE_IN(void) SysLoc = newlocale(LC_MESSAGES_MASK, "", (locale_t) 0); if (SysLoc != NULL) { + #ifdef __GLIBC__ const char *s18n = SysLoc->__names[5]; + #else + const char *s18n = "en_US.UTF-8"; + #endif struct LOCALE_LOOKUP *lookUp = LocaleLookUp; while (lookUp->i18n != NULL) { I18N *i18n = lookUp->i18n; diff --git a/corefreq-ui.h b/aarch64/corefreq-ui.h similarity index 99% rename from corefreq-ui.h rename to aarch64/corefreq-ui.h index 2309343b..0cc91e62 100644 --- a/corefreq-ui.h +++ b/aarch64/corefreq-ui.h @@ -1,6 +1,6 @@ /* * CoreFreq - * Copyright (C) 2015-2023 CYRIL COURTIAT + * Copyright (C) 2015-2024 CYRIL COURTIAT * Licenses: GPL2 */ diff --git a/aarch64/corefreq.h b/aarch64/corefreq.h new file mode 100644 index 00000000..b5f43d58 --- /dev/null +++ b/aarch64/corefreq.h @@ -0,0 +1,571 @@ +/* + * CoreFreq + * Copyright (C) 2015-2024 CYRIL COURTIAT + * Licenses: GPL2 + */ + +#define OF( _ptr_ , ...) _ptr_ __VA_ARGS__ +#define RO( _ptr_ , ...) OF( _ptr_##_RO , __VA_ARGS__ ) +#define RW( _ptr_ , ...) OF( _ptr_##_RW , __VA_ARGS__ ) + +#define SHM_FILENAME_RO "corefreq-ro-shm" +#define SHM_FILENAME_RW "corefreq-rw-shm" + +#define SIG_RING_MS (500 * 1000000LU) +#define CHILD_PS_MS (500 * 1000000LU) +#define CHILD_TH_MS (500 * 1000000LU) + +enum CHIPSET { + IC_CHIPSET, + CHIPSETS +}; + +/* Circular buffer */ +#define RING_SIZE 16 + +typedef struct +{ + Bit64 Toggle __attribute__ ((aligned (8))); + + Bit64 OffLine __attribute__ ((aligned (8))); + + unsigned int Boost[BOOST(SIZE)]; + + struct + { + unsigned int Revision; + + struct { + unsigned short int CfgLock : 1-0, + IORedir : 2-1, + SCTLRX : 3-2, + Unused : 16-3; + }; + unsigned short int CStateLimit; + unsigned short int CStateBaseAddr; /* Any I/O BAR */ + } Query; + + struct { + struct { + unsigned int PN : 12-0, + BSP : 32-12; + }; + signed int MPID, + CoreID, + ThreadID, + PackageID; + struct CLUSTER_ST Cluster; + struct { + unsigned int Set, + Size; + unsigned short LineSz, + Way; + struct { + unsigned short WriteBack: 1-0, + Inclusive: 2-1, + _pad16 : 16-2; + } Feature; + } Cache[CACHE_MAX_LEVEL]; + } Topology; + + struct { + unsigned int Limit[SENSOR_LIMITS_DIM]; + struct { + unsigned int ClockMod : 16-0, + Extended : 32-16; + } DutyCycle; + unsigned int PowerPolicy; + struct HWP_STRUCT { + struct { + unsigned int Highest, + Guaranteed, + Most_Efficient, + Lowest; + } Capabilities; + struct { + unsigned int Minimum_Perf, + Maximum_Perf, + Desired_Perf, + Energy_Pref; + } Request; + } HWP; + } PowerThermal; + + THERMAL_POINT ThermalPoint; + + struct { + struct { + double Limit[SENSOR_LIMITS_DIM]; + } Voltage; + struct { + double Limit[SENSOR_LIMITS_DIM]; + } Energy; + struct { + double Limit[SENSOR_LIMITS_DIM]; + } Power; + } Sensors; + + struct FLIP_FLOP { + + struct + { + unsigned long long + INST; + struct { + unsigned long long + UCC, + URC; + } C0; + unsigned long long + C3, + C6, + C7, + TSC, + C1; + struct { + unsigned long long ACCU; + } Power; + } Delta __attribute__ ((aligned (8))); + + CLOCK Clock; + + struct { + double IPS, + IPC, + CPI, + Turbo, + C0, + C3, + C6, + C7, + C1, + Energy, + Power; + } State; + + struct { + double Ratio, + Freq; + } Relative; + + struct { + double Freq; + struct { + double Perf; /* STATUS or BOOST P-State */ + } Ratio; + } Absolute; + + struct { + unsigned int Sensor, + Temp; + enum THERM_PWR_EVENTS Events[eDIM]; + THERMAL_PARAM Param; + } Thermal; + + struct { + int VID; + double Vcore; + } Voltage; + + struct { + unsigned int SMI; + struct { + unsigned int LOCAL, + UNKNOWN, + PCISERR, + IOCHECK; + } NMI; + } Counter; + } FlipFlop[2]; + + struct { + double Freq[SENSOR_LIMITS_DIM]; + } Relative; + struct { + double Freq[SENSOR_LIMITS_DIM]; + } Absolute; + + struct { + Bit64 FLAGS __attribute__ ((aligned (8))); + Bit64 SCTLR __attribute__ ((aligned (8))); + Bit64 SCTLR2 __attribute__ ((aligned (8))); + Bit64 EL __attribute__ ((aligned (8))); + Bit64 FPSR __attribute__ ((aligned (8))); + Bit64 SVCR __attribute__ ((aligned (8))); + } SystemRegister; + + struct SLICE_STRUCT { + struct + { + unsigned long long TSC, + INST; + } Delta; + + struct { + unsigned long long TSC, + INST; + } Counter[3]; + + unsigned long long Error; + + #ifdef __GLIBC__ + struct { + struct random_data data; + char state[128]; + int value[2]; + } Random; + #else + struct { + char state[128]; + int value[2]; + } Random; + #endif /* __GLIBC__ */ + + struct { + unsigned long long inside, + trials; + } Monte_Carlo; + } Slice __attribute__ ((aligned (8))); +} CPU_STRUCT; + +typedef struct +{ + Bit64 Toggle __attribute__ ((aligned (8))); + + FEATURES Features; + + struct { + unsigned long long + _Unused1_ : 13-0, + VM : 14-13, + IOMMU : 15-14, + _Unused2_ : 20-15, + IOMMU_Ver_Major : 24-20, + IOMMU_Ver_Minor : 28-24, + _Unused3_ : 64-28; + } Technology; + + struct { + unsigned long long + CLRBHB : 2-0, + CSV2 : 6-2, + CSV3 : 8-6, + SSBS : 10-8, + _UnusedMechBits : 64-10; + } Mechanisms; + + enum THERMAL_FORMULAS thermalFormula; + enum VOLTAGE_FORMULAS voltageFormula; + enum POWER_FORMULAS powerFormula; + + struct { + unsigned int Count, + OnLine; + } CPU; + + SERVICE_PROC Service; + + union { + unsigned int PM_version; + struct PMU_ST { + unsigned short v, p; + } PM_ext; + }; + struct { + unsigned int Rel, + Abs; + } Top; + + struct PKG_FLIP_FLOP { + struct { + unsigned long long PCLK; + struct { + unsigned long long PC02, + PC03, + PC04, + PC06, + PC07, + PC08, + PC09, + PC10; + }; + unsigned long long MC6, + ACCU[PWR_DOMAIN(SIZE)]; + } Delta; + + struct { + unsigned long long FC0; + } Uncore; + + struct { + unsigned int Sensor, + Temp; + enum THERM_PWR_EVENTS Events[eDIM]; + } Thermal; + + struct { + struct { + int CPU, SOC; + } VID; + double CPU, SOC; + } Voltage; + } FlipFlop[2] __attribute__ ((aligned (8))); + + struct { + double PC02, + PC03, + PC04, + PC06, + PC07, + PC08, + PC09, + PC10, + MC6; + struct { + double Limit[SENSOR_LIMITS_DIM]; + } Voltage; + + struct { + double Current, + Limit[SENSOR_LIMITS_DIM]; + } Energy[PWR_DOMAIN(SIZE)]; + + struct { + double Current, + Limit[SENSOR_LIMITS_DIM]; + } Power[PWR_DOMAIN(SIZE)]; + } State; + + struct { + double Turbo, + C0, + C3, + C6, + C7, + C1, + MC6; + } Avg; + + struct { + struct { + double Watts, + Joules, + Times; + } Unit; + struct { + double TAU[PWR_LIMIT_SIZE]; + unsigned short PWL[PWR_LIMIT_SIZE]; + struct { + unsigned char Enable : 1-0, + Clamping: 2-1, + Unlock : 3-2, + _Unused : 8-3; + union { + unsigned char TW; + struct { + unsigned char TW_Y : 5-0, + TW_Z : 7-5, + MaskBit : 8-7; + }; + }; + } Feature[PWR_LIMIT_SIZE]; + } Domain[PWR_DOMAIN(SIZE)]; + unsigned short TDP, Min, Max; + unsigned short PPT, EDC, TDC; + struct { + unsigned short TDC : 1-0, + _Unused : 16-1; + } Feature; + } Power; + + THERMAL_POINT ThermalPoint; + + signed int ArchID; + enum HYPERVISOR HypervisorID; + char Architecture[CODENAME_LEN], + Brand[BRAND_SIZE]; +} PROC_STRUCT; + +typedef struct +{ + FOOTPRINT FootPrint; + + BitCC roomSched __attribute__ ((aligned (16))); + + enum THERM_PWR_EVENTS ProcessorEvents[eDIM]; + + struct { /* NMI bits: 0 is Unregistered; 1 is Registered */ + Bit64 NMI __attribute__ ((aligned (8))); + signed int AutoClock, /* 10: Auto, 01: Init, 00: Specs */ + Experimental,/* 0: Disable, 1: Enable */ + HotPlug, /* < 0: Disable, Other: Enable */ + PCI; /* < 0: Disable, other: Enable */ + KERNEL_DRIVER Driver; /*0:Disable, 1:Enable, 2:Full-control*/ + } Registration; + + struct { + Bit64 Operation __attribute__ ((aligned (8))); + + OS_DRIVER OS; + + unsigned int tickReset, + tickStep; + + pid_t trackTask; + enum SORTBYFIELD sortByField; + int reverseOrder, + taskCount; + TASK_MCB taskList[TASK_LIMIT]; + + MEM_MCB memInfo; + + struct { + unsigned short version, + major, + minor; + } kernel; + + unsigned short procCount; + + char sysname[MAX_UTS_LEN], + release[MAX_UTS_LEN], + version[MAX_UTS_LEN], + machine[MAX_UTS_LEN]; + } SysGate; + + struct { + unsigned char index[8]; + char array[MAX_UTS_LEN]; + } CS; + + struct { + unsigned int Interval; + struct timespec pollingWait, + ringWaiting, + childWaiting, + sliceWaiting; + } Sleep; + + time_t StartedAt; + + char ShmName[TASK_COMM_LEN]; + struct { + pid_t Svr, + Cli, + GUI; + } App; + + struct { + unsigned int Boost[UNCORE_BOOST(SIZE)]; + struct + { + unsigned long long Speed; + unsigned int Rate; + } Bus; + + struct { + struct { + RAM_TIMING Timing; + RAM_GEOMETRY DIMM[MC_MAX_DIMM]; + } Channel[MC_MAX_CHA]; + unsigned short SlotCount, ChannelCount; + } MC[MC_MAX_CTRL]; + + unsigned long long CtrlSpeed; + unsigned short CtrlCount, + ChipID; + + struct { + unsigned short /* 00:MHz , 01:MT/s , 10:MB/s , 11:VOID */ + Bus_Rate: 2-0, + BusSpeed: 4-2, + DDR_Rate: 6-4, + DDRSpeed: 8-6, + DDR_Std : 12-8, + DDR_Ver : 16-12; + } Unit; + + struct { + enum CHIPSET ArchID; + char CodeName[CODENAME_LEN]; + } Chipset; + } Uncore; + + SMBIOS_ST SMB; + + PROC_STRUCT Proc; + CPU_STRUCT Cpu[]; +} SHM_STRUCT_RO; + +typedef struct { + struct { + Bit64 Sync __attribute__ ((aligned (8))); + } Proc; + + struct { + RING_CTRL buffer[RING_SIZE] __attribute__((aligned(16))); + unsigned int head, tail; + } Ring[2]; /* [0] Parent ; [1] Child */ + + struct { + RING_CTRL buffer[RING_SIZE] __attribute__((aligned(16))); + unsigned int head, tail; + } Error; +} SHM_STRUCT_RW; + +/* Error Reasons management. */ +typedef struct { + __typeof__ (errno) no: 32; + __typeof__ (__LINE__) ln: 26; + enum REASON_CLASS rc: 6; +} REASON_CODE; + +#define REASON_SET_2xARG(_reason, _rc, _no) \ +{ \ + _reason.no = _no; \ + _reason.ln = __LINE__; \ + _reason.rc = _rc; \ +} + +#define REASON_SET_1xARG(_reason, _rc) \ +{ \ + _reason.no = errno; \ + _reason.ln = __LINE__; \ + _reason.rc = _rc; \ +} + +#define REASON_SET_0xARG(_reason) \ +{ \ + _reason.no = errno; \ + _reason.ln = __LINE__; \ + _reason.rc = RC_SYS_CALL; \ +} + +#define REASON_DISPATCH(_1,_2,_3,REASON_CURSOR, ... ) REASON_CURSOR + +#define REASON_SET( ... ) \ + REASON_DISPATCH( __VA_ARGS__ , REASON_SET_2xARG, \ + REASON_SET_1xARG, \ + REASON_SET_0xARG)( __VA_ARGS__ ) + +#define REASON_INIT(_reason) \ + REASON_CODE _reason = {.no = 0, .ln = 0, .rc = RC_SUCCESS} + +#define IS_REASON_SUCCESSFUL(_reason) (_reason.rc == RC_SUCCESS) + +#if defined(UBENCH) && UBENCH == 1 + #define Print_uBenchmark(quiet) \ + ({ \ + if (quiet) \ + printf("%llu\t%llu\n",UBENCH_METRIC(0),UBENCH_METRIC(1));\ + }) +#else + #define Print_uBenchmark(quiet) {} +#endif /* UBENCH */ + +#define ELAPSED(ref) \ +({ \ + time_t now; \ + time(&now); \ + now - ref; \ +}) diff --git a/aarch64/corefreqd.c b/aarch64/corefreqd.c new file mode 100644 index 00000000..17769f68 --- /dev/null +++ b/aarch64/corefreqd.c @@ -0,0 +1,2556 @@ +/* + * CoreFreq + * Copyright (C) 2015-2024 CYRIL COURTIAT + * Licenses: GPL2 + */ + +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "bitasm.h" +#include "arm_reg.h" +#include "coretypes.h" +#include "corefreq.h" +#include "corefreqm.h" +#include "corefreq-api.h" + +#define AT( _loc_ ) [ _loc_ ] + +#define PAGE_SIZE \ +( \ + sysconf(_SC_PAGESIZE) > 0 ? sysconf(_SC_PAGESIZE) : 4096 \ +) + +/* AArch64 LDAXP/STLXP alignment, 128-Byte Blocks of Memory */ +static BitCC roomSeed __attribute__ ((aligned (16))) = InitCC(0x0); +static BitCC roomCore __attribute__ ((aligned (16))) = InitCC(0x0); +static BitCC roomClear __attribute__ ((aligned (16))) = InitCC(0x0); +static BitCC roomReady __attribute__ ((aligned (16))) = InitCC(0x0); +static Bit64 Shutdown __attribute__ ((aligned (8))) = 0x0; +static Bit64 PendingSync __attribute__ ((aligned (8))) = 0x0; +unsigned int Quiet = 0x001, SysGateStartUp = 1; + +UBENCH_DECLARE() + +typedef struct +{ + int drv, + ro, + rw; +} FD; + +typedef struct { + sigset_t Signal; + pid_t CPID; + pthread_t KID; + int Started; + struct { + SLICE_FUNC Func; + unsigned long arg; + enum PATTERN pattern; + } Slice; + FD *fd; + RO(SHM_STRUCT) *RO(Shm); + RW(SHM_STRUCT) *RW(Shm); + RO(PROC) *RO(Proc); + RW(PROC) *RW(Proc); + RO(CORE) **RO(Core); + RW(CORE) **RW(Core); + RO(SYSGATE) *RO(SysGate); +} REF; + +void Core_ResetSensorLimits(CPU_STRUCT *Cpu) +{ + RESET_SENSOR_LIMIT(THERMAL, LOWEST, Cpu->PowerThermal.Limit); + RESET_SENSOR_LIMIT(VOLTAGE, LOWEST, Cpu->Sensors.Voltage.Limit); + RESET_SENSOR_LIMIT(ENERGY, LOWEST, Cpu->Sensors.Energy.Limit); + RESET_SENSOR_LIMIT(POWER, LOWEST, Cpu->Sensors.Power.Limit); + RESET_SENSOR_LIMIT(REL_FREQ, LOWEST, Cpu->Relative.Freq); + RESET_SENSOR_LIMIT(ABS_FREQ, LOWEST, Cpu->Absolute.Freq); + + RESET_SENSOR_LIMIT(THERMAL, HIGHEST, Cpu->PowerThermal.Limit); + RESET_SENSOR_LIMIT(VOLTAGE, HIGHEST, Cpu->Sensors.Voltage.Limit); + RESET_SENSOR_LIMIT(ENERGY, HIGHEST, Cpu->Sensors.Energy.Limit); + RESET_SENSOR_LIMIT(POWER, HIGHEST, Cpu->Sensors.Power.Limit); + RESET_SENSOR_LIMIT(REL_FREQ, HIGHEST, Cpu->Relative.Freq); + RESET_SENSOR_LIMIT(ABS_FREQ, HIGHEST, Cpu->Absolute.Freq); +} + +void Core_ComputeThermalLimits(CPU_STRUCT *Cpu, struct FLIP_FLOP *CFlip) +{ /* Per Core, computes the Min temperature. */ + TEST_AND_SET_SENSOR( THERMAL, LOWEST, CFlip->Thermal.Temp, + Cpu->PowerThermal.Limit ); + /* Per Core, computes the Max temperature. */ + TEST_AND_SET_SENSOR( THERMAL, HIGHEST, CFlip->Thermal.Temp, + Cpu->PowerThermal.Limit ); +} + +static void ComputeThermal_None( struct FLIP_FLOP *CFlip, + RO(SHM_STRUCT) *RO(Shm), + unsigned int cpu ) +{ + UNUSED(RO(Shm)); + UNUSED(cpu); + CFlip->Thermal.Temp = 0; +} + +#define ComputeThermal_None_PerSMT ComputeThermal_None +#define ComputeThermal_None_PerCore ComputeThermal_None +#define ComputeThermal_None_PerPkg ComputeThermal_None + +static void (*ComputeThermal_None_Matrix[4])( struct FLIP_FLOP*, + RO(SHM_STRUCT)*, + unsigned int ) = \ +{ + [FORMULA_SCOPE_NONE] = ComputeThermal_None, + [FORMULA_SCOPE_SMT ] = ComputeThermal_None_PerSMT, + [FORMULA_SCOPE_CORE] = ComputeThermal_None_PerCore, + [FORMULA_SCOPE_PKG ] = ComputeThermal_None_PerPkg +}; + +void Core_ComputeVoltageLimits(CPU_STRUCT *Cpu, struct FLIP_FLOP *CFlip) +{ /* Per Core, computes the Min CPU voltage. */ + TEST_AND_SET_SENSOR( VOLTAGE, LOWEST, CFlip->Voltage.Vcore, + Cpu->Sensors.Voltage.Limit ); + /* Per Core, computes the Max CPU voltage. */ + TEST_AND_SET_SENSOR( VOLTAGE, HIGHEST, CFlip->Voltage.Vcore, + Cpu->Sensors.Voltage.Limit ); +} + +static void ComputeVoltage_None( struct FLIP_FLOP *CFlip, + RO(SHM_STRUCT) *RO(Shm), + unsigned int cpu ) +{ + UNUSED(CFlip); + UNUSED(RO(Shm)); + UNUSED(cpu); +} + +#define ComputeVoltage_None_PerSMT ComputeVoltage_None +#define ComputeVoltage_None_PerCore ComputeVoltage_None +#define ComputeVoltage_None_PerPkg ComputeVoltage_None + +static void (*ComputeVoltage_None_Matrix[4])( struct FLIP_FLOP*, + RO(SHM_STRUCT)*, + unsigned int ) = \ +{ + [FORMULA_SCOPE_NONE] = ComputeVoltage_None, + [FORMULA_SCOPE_SMT ] = ComputeVoltage_None_PerSMT, + [FORMULA_SCOPE_CORE] = ComputeVoltage_None_PerCore, + [FORMULA_SCOPE_PKG ] = ComputeVoltage_None_PerPkg +}; + +void Core_ComputePowerLimits(CPU_STRUCT *Cpu, struct FLIP_FLOP *CFlip) +{ /* Per Core, computes the Min CPU Energy consumed. */ + TEST_AND_SET_SENSOR( ENERGY, LOWEST, CFlip->State.Energy, + Cpu->Sensors.Energy.Limit ); + /* Per Core, computes the Max CPU Energy consumed. */ + TEST_AND_SET_SENSOR( ENERGY, HIGHEST, CFlip->State.Energy, + Cpu->Sensors.Energy.Limit ); + /* Per Core, computes the Min CPU Power consumed. */ + TEST_AND_SET_SENSOR( POWER, LOWEST, CFlip->State.Power, + Cpu->Sensors.Power.Limit); + /* Per Core, computes the Max CPU Power consumed. */ + TEST_AND_SET_SENSOR( POWER, HIGHEST, CFlip->State.Power, + Cpu->Sensors.Power.Limit ); +} + +static void ComputePower_None( struct FLIP_FLOP *CFlip, + RO(SHM_STRUCT) *RO(Shm), + unsigned int cpu ) +{ + UNUSED(CFlip); + UNUSED(RO(Shm)); + UNUSED(cpu); +} + +#define ComputePower_None_PerSMT ComputePower_None +#define ComputePower_None_PerCore ComputePower_None +#define ComputePower_None_PerPkg ComputePower_None + +static void (*ComputePower_None_Matrix[4])( struct FLIP_FLOP*, + RO(SHM_STRUCT)*, + unsigned int ) = \ +{ + [FORMULA_SCOPE_NONE] = ComputePower_None, + [FORMULA_SCOPE_SMT ] = ComputePower_None_PerSMT, + [FORMULA_SCOPE_CORE] = ComputePower_None_PerCore, + [FORMULA_SCOPE_PKG ] = ComputePower_None_PerPkg +}; + +typedef struct { + REF *Ref; + unsigned int Bind; + pthread_t TID; +} ARG; + +static void *Core_Cycle(void *arg) +{ + ARG *Arg = (ARG *) arg; + unsigned int cpu = Arg->Bind; + RO(SHM_STRUCT) *RO(Shm) = Arg->Ref->RO(Shm); + RO(CORE) *RO(Core) = Arg->Ref->RO(Core, AT(cpu)); + RW(CORE) *RW(Core) = Arg->Ref->RW(Core, AT(cpu)); + CPU_STRUCT *Cpu = &RO(Shm)->Cpu[cpu]; + + pthread_t tid = pthread_self(); + cpu_set_t cpuset; + CPU_ZERO(&cpuset); + CPU_SET(cpu, &cpuset); + if (pthread_setaffinity_np(tid, sizeof(cpu_set_t), &cpuset) != 0) { + goto EXIT; + } + char *comm = malloc(TASK_COMM_LEN+10+1); + if (comm != NULL) { + snprintf(comm, TASK_COMM_LEN+10+1, "corefreqd/%u", cpu); + pthread_setname_np(tid, comm); + free(comm); + } + + void (**ComputeThermalFormula)( struct FLIP_FLOP*, + RO(SHM_STRUCT)*, + unsigned int ); + + void (**ComputeVoltageFormula)( struct FLIP_FLOP*, + RO(SHM_STRUCT)*, + unsigned int ); + + void (**ComputePowerFormula)( struct FLIP_FLOP*, + RO(SHM_STRUCT)*, + unsigned int ); + + switch (KIND_OF_FORMULA(RO(Shm)->Proc.thermalFormula)) { + case THERMAL_KIND_NONE: + default: + ComputeThermalFormula = ComputeThermal_None_Matrix; + break; + } + + switch (KIND_OF_FORMULA(RO(Shm)->Proc.voltageFormula)) { + case VOLTAGE_KIND_NONE: + default: + ComputeVoltageFormula = ComputeVoltage_None_Matrix; + break; + } + + switch (KIND_OF_FORMULA(RO(Shm)->Proc.powerFormula)) { + case POWER_KIND_NONE: + default: + ComputePowerFormula = ComputePower_None_Matrix; + break; + } + + if (Quiet & 0x100) { + printf(" Thread [%lx] Init CYCLE %03u\n", (long) tid, cpu); + fflush(stdout); + } + BITSET_CC(BUS_LOCK, roomSeed, cpu); + BITSET_CC(BUS_LOCK, roomCore, cpu); + + do { + while (!BITCLR(LOCKLESS, RW(Core)->Sync.V, NTFY) + && !BITVAL(Shutdown, SYNC) + && !BITVAL(RO(Core)->OffLine, OS)) { + nanosleep(&RO(Shm)->Sleep.pollingWait, NULL); + } + + if (!BITVAL(Shutdown, SYNC) && !BITVAL(RO(Core)->OffLine, OS)) + { + if (BITCLR_CC(BUS_LOCK, roomCore, cpu)) { + Cpu->Toggle = !Cpu->Toggle; + } + struct FLIP_FLOP *CFlip = &Cpu->FlipFlop[Cpu->Toggle]; + + /* Refresh this Base Clock. */ + CFlip->Clock.Q = RO(Core)->Clock.Q; + CFlip->Clock.R = RO(Core)->Clock.R; + CFlip->Clock.Hz = RO(Core)->Clock.Hz; + + /* Copy the Performance & C-States Counters. */ + CFlip->Delta.INST = RO(Core)->Delta.INST; + CFlip->Delta.C0.UCC = RO(Core)->Delta.C0.UCC; + CFlip->Delta.C0.URC = RO(Core)->Delta.C0.URC; + CFlip->Delta.C3 = RO(Core)->Delta.C3; + CFlip->Delta.C6 = RO(Core)->Delta.C6; + CFlip->Delta.C7 = RO(Core)->Delta.C7; + CFlip->Delta.TSC = RO(Core)->Delta.TSC; + CFlip->Delta.C1 = RO(Core)->Delta.C1; + + /* Update all clock ratios. */ + memcpy(Cpu->Boost, RO(Core)->Boost, (BOOST(SIZE))*sizeof(unsigned int)); + + const double FRQ = Cpu->Boost[BOOST(MAX)] * CFlip->Clock.Hz; + + CFlip->Absolute.Ratio.Perf = (double)RO(Core)->Ratio.COF.Q; + CFlip->Absolute.Ratio.Perf +=(double)RO(Core)->Ratio.COF.R /UNIT_KHz(1); + + /* Compute IPS=Instructions per Hz */ + CFlip->State.IPS = (double)CFlip->Delta.INST / FRQ; + + /* Compute IPC=Instructions per non-halted reference cycle. + ( Protect against a division by zero ) */ + if (CFlip->Delta.C0.URC != 0) { + CFlip->State.IPC = (double)CFlip->Delta.INST + / (double)CFlip->Delta.C0.URC; + } else { + CFlip->State.IPC = 0.0f; + } + /* Compute CPI=Non-halted reference cycles per instruction. + ( Protect against a division by zero ) */ + if (CFlip->Delta.INST != 0) { + CFlip->State.CPI = (double)CFlip->Delta.C0.URC + / (double)CFlip->Delta.INST; + } else { + CFlip->State.CPI = 0.0f; + } + /* Compute the Turbo State. */ + CFlip->State.Turbo = (double)CFlip->Delta.C0.UCC / FRQ; + + /* Compute the C-States. */ + CFlip->State.C0 = (double)CFlip->Delta.C0.URC / FRQ; + + CFlip->State.C3 = (double)CFlip->Delta.C3 / FRQ; + + CFlip->State.C6 = (double)CFlip->Delta.C6 / FRQ; + + CFlip->State.C7 = (double)CFlip->Delta.C7 / FRQ; + + CFlip->State.C1 = (double)CFlip->Delta.C1 / FRQ; + + /* Relative Frequency = Relative Ratio x Bus Clock Frequency */ + CFlip->Relative.Ratio = (double)(CFlip->Delta.C0.URC + * Cpu->Boost[BOOST(MAX)]) / FRQ; + + CFlip->Relative.Freq = REL_FREQ_MHz( double, + CFlip->Relative.Ratio, + CFlip->Clock, + RO(Shm)->Sleep.Interval ); + + /* Per Core, compute the Relative Frequency limits. */ + TEST_AND_SET_SENSOR( REL_FREQ, LOWEST, CFlip->Relative.Freq, + Cpu->Relative.Freq ); + + TEST_AND_SET_SENSOR( REL_FREQ, HIGHEST, CFlip->Relative.Freq, + Cpu->Relative.Freq ); + /* Per Core, compute the Absolute Frequency limits. */ + CFlip->Absolute.Freq = ABS_FREQ_MHz(double, CFlip->Absolute.Ratio.Perf, + (double)CFlip->Clock); + + TEST_AND_SET_SENSOR( ABS_FREQ, LOWEST, CFlip->Absolute.Freq, + Cpu->Absolute.Freq ); + + TEST_AND_SET_SENSOR( ABS_FREQ, HIGHEST, CFlip->Absolute.Freq, + Cpu->Absolute.Freq ); + /* Core Processor events */ + memcpy( CFlip->Thermal.Events, RO(Core)->PowerThermal.Events, + sizeof(CFlip->Thermal.Events) ); + /* Per Core, evaluate thermal properties. */ + CFlip->Thermal.Sensor = RO(Core)->PowerThermal.Sensor; + CFlip->Thermal.Param = RO(Core)->PowerThermal.Param; + + ComputeThermalFormula[SCOPE_OF_FORMULA(RO(Shm)->Proc.thermalFormula)]( + CFlip, RO(Shm), cpu + ); + + /* Per Core, evaluate the voltage properties. */ + CFlip->Voltage.VID = RO(Core)->PowerThermal.VID; + + ComputeVoltageFormula[SCOPE_OF_FORMULA(RO(Shm)->Proc.voltageFormula)]( + CFlip, RO(Shm), cpu + ); + + /* Per Core, evaluate the Power properties. */ + CFlip->Delta.Power.ACCU = RO(Core)->Delta.Power.ACCU; + + ComputePowerFormula[SCOPE_OF_FORMULA(RO(Shm)->Proc.powerFormula)]( + CFlip, RO(Shm), cpu + ); + + /* Copy the Interrupts counters. */ + CFlip->Counter.SMI = RO(Core)->Interrupt.SMI; + + /* If driver registered, copy any NMI counter. */ + if (BITVAL(RO(Shm)->Registration.NMI, BIT_NMI_LOCAL) == 1) { + CFlip->Counter.NMI.LOCAL = RO(Core)->Interrupt.NMI.LOCAL; + } + if (BITVAL(RO(Shm)->Registration.NMI, BIT_NMI_UNKNOWN) == 1) { + CFlip->Counter.NMI.UNKNOWN = RO(Core)->Interrupt.NMI.UNKNOWN; + } + if (BITVAL(RO(Shm)->Registration.NMI, BIT_NMI_SERR) == 1) { + CFlip->Counter.NMI.PCISERR = RO(Core)->Interrupt.NMI.PCISERR; + } + if (BITVAL(RO(Shm)->Registration.NMI, BIT_NMI_IO_CHECK) == 1) { + CFlip->Counter.NMI.IOCHECK = RO(Core)->Interrupt.NMI.IOCHECK; + } + } + } while (!BITVAL(Shutdown, SYNC) && !BITVAL(RO(Core)->OffLine, OS)) ; + + BITCLR_CC(BUS_LOCK, roomCore, cpu); + BITCLR_CC(BUS_LOCK, roomSeed, cpu); +EXIT: + if (Quiet & 0x100) { + printf(" Thread [%lx] %s CYCLE %03u\n", (long) tid, + BITVAL(RO(Core)->OffLine, OS) ? "Offline" : "Shutdown", + cpu); + fflush(stdout); + } + return NULL; +} + +void SliceScheduling( RO(SHM_STRUCT) *RO(Shm), + unsigned int cpu, enum PATTERN pattern ) +{ + unsigned int seek = 0; + switch (pattern) { + case RESET_CSP: + for (seek = 0; seek < RO(Shm)->Proc.CPU.Count; seek++) { + if (seek == RO(Shm)->Proc.Service.Core) { + BITSET_CC(LOCKLESS, RO(Shm)->roomSched, seek); + } else { + BITCLR_CC(LOCKLESS, RO(Shm)->roomSched, seek); + } + } + break; + case ALL_SMT: + if (cpu == RO(Shm)->Proc.Service.Core) { + BITSTOR_CC(LOCKLESS, RO(Shm)->roomSched, roomSeed); + } + break; + case RAND_SMT: + do { + #ifdef __GLIBC__ + if (random_r(&RO(Shm)->Cpu[cpu].Slice.Random.data, + &RO(Shm)->Cpu[cpu].Slice.Random.value[0]) == 0) + #else + RO(Shm)->Cpu[cpu].Slice.Random.value[0] = (int) random(); + #endif /* __GLIBC__ */ + { + seek = RO(Shm)->Cpu[cpu].Slice.Random.value[0] + % RO(Shm)->Proc.CPU.Count; + } + } while (BITVAL(RO(Shm)->Cpu[seek].OffLine, OS)); + BITCLR_CC(LOCKLESS, RO(Shm)->roomSched, cpu); + BITSET_CC(LOCKLESS, RO(Shm)->roomSched, seek); + break; + case RR_SMT: + seek = cpu; + do { + seek++; + if (seek >= RO(Shm)->Proc.CPU.Count) { + seek = 0; + } + } while (BITVAL(RO(Shm)->Cpu[seek].OffLine, OS)); + BITCLR_CC(LOCKLESS, RO(Shm)->roomSched, cpu); + BITSET_CC(LOCKLESS, RO(Shm)->roomSched, seek); + break; + case USR_CPU: + /* NOP */ + break; + } +} + +static void *Child_Thread(void *arg) +{ + ARG *Arg = (ARG *) arg; + unsigned int cpu = Arg->Bind; + + RO(SHM_STRUCT) *RO(Shm) = Arg->Ref->RO(Shm); + RW(SHM_STRUCT) *RW(Shm) = Arg->Ref->RW(Shm); + CPU_STRUCT *Cpu = &RO(Shm)->Cpu[cpu]; + + CALL_FUNC MatrixCallFunc[2] = { + CallWith_RDTSC_No_RDPMC, CallWith_RDTSC_RDPMC + }; + const int withRDPMC = ((RO(Shm)->Proc.PM_version >= 1)); + + CALL_FUNC CallSliceFunc = MatrixCallFunc[withRDPMC]; + + pthread_t tid = pthread_self(); + cpu_set_t cpuset; + CPU_ZERO(&cpuset); + CPU_SET(cpu, &cpuset); + if (pthread_setaffinity_np(tid, sizeof(cpu_set_t), &cpuset) != 0) { + goto EXIT; + } + char *comm = malloc(TASK_COMM_LEN+10+1); + if (comm != NULL) { + snprintf(comm, TASK_COMM_LEN+10+1, "corefreqd#%u", cpu); + pthread_setname_np(tid, comm); + free(comm); + } + if (Quiet & 0x100) { + printf(" Thread [%lx] Init CHILD %03u\n", (long) tid, cpu); + fflush(stdout); + } + + BITSET_CC(BUS_LOCK, roomSeed, cpu); + + do { + while (!BITVAL(RW(Shm)->Proc.Sync, BURN) + && !BITVAL(Shutdown, SYNC) + && !BITVAL(Cpu->OffLine, OS)) { + nanosleep(&RO(Shm)->Sleep.sliceWaiting, NULL); + } + + BITSET_CC(BUS_LOCK, roomCore, cpu); + + RESET_Slice(Cpu->Slice); + + while ( BITVAL(RW(Shm)->Proc.Sync, BURN) + && !BITVAL(Shutdown, SYNC) ) + { + if (BITVAL_CC(RO(Shm)->roomSched, cpu)) { + CallSliceFunc( RO(Shm), RW(Shm), cpu, + Arg->Ref->Slice.Func, + Arg->Ref->Slice.arg); + + SliceScheduling(RO(Shm), cpu, Arg->Ref->Slice.pattern); + + if (BITVAL(Cpu->OffLine, OS)) { /* ReSchedule to Service */ + SliceScheduling(RO(Shm), RO(Shm)->Proc.Service.Core, RESET_CSP); + break; + } + } else { + nanosleep(&RO(Shm)->Sleep.sliceWaiting, NULL); + + if (BITVAL(Cpu->OffLine, OS)) { + break; + } + } + } + + BITCLR_CC(BUS_LOCK, roomCore, cpu); + + } while (!BITVAL(Shutdown, SYNC) && !BITVAL(Cpu->OffLine, OS)) ; + + BITCLR_CC(BUS_LOCK, roomSeed, cpu); + + RESET_Slice(Cpu->Slice); +EXIT: + if (Quiet & 0x100) { + printf(" Thread [%lx] %s CHILD %03u\n", (long) tid, + BITVAL(Cpu->OffLine, OS) ? "Offline" : "Shutdown",cpu); + fflush(stdout); + } + return NULL; +} + +void Architecture(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc)) +{ + Bit32 fTSC = RO(Proc)->Features.TSC, + aTSC = RO(Proc)->Features.Inv_TSC; + + /* Copy all initial CPUID features. */ + memcpy(&RO(Shm)->Proc.Features, &RO(Proc)->Features, sizeof(FEATURES)); + /* Copy the fomula identifiers */ + RO(Shm)->Proc.thermalFormula = RO(Proc)->thermalFormula; + RO(Shm)->Proc.voltageFormula = RO(Proc)->voltageFormula; + RO(Shm)->Proc.powerFormula = RO(Proc)->powerFormula; + /* Copy the numbers of total & online CPU. */ + RO(Shm)->Proc.CPU.Count = RO(Proc)->CPU.Count; + RO(Shm)->Proc.CPU.OnLine = RO(Proc)->CPU.OnLine; + RO(Shm)->Proc.Service.Proc = RO(Proc)->Service.Proc; + /* Architecture and Hypervisor identifiers. */ + RO(Shm)->Proc.ArchID = RO(Proc)->ArchID; + RO(Shm)->Proc.HypervisorID = RO(Proc)->HypervisorID; + /* Copy the Architecture name and Brand string. */ + StrCopy(RO(Shm)->Proc.Architecture,RO(Proc)->Architecture,CODENAME_LEN); + StrCopy(RO(Shm)->Proc.Brand, RO(Proc)->Features.Info.Brand, BRAND_SIZE); + /* Compute the TSC mode: None, Variant, Invariant */ + RO(Shm)->Proc.Features.InvariantTSC = fTSC << aTSC; +} + +void PerformanceMonitoring(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc)) +{ + switch (RO(Proc)->Features.PerfMon.Version) { + case 0b0001: RO(Shm)->Proc.PM_ext = (struct PMU_ST){.v = 3, .p = 0x0}; + break; + case 0b0100: RO(Shm)->Proc.PM_ext = (struct PMU_ST){.v = 3, .p = 0x1}; + break; + case 0b0101: RO(Shm)->Proc.PM_ext = (struct PMU_ST){.v = 3, .p = 0x4}; + break; + case 0b0110: RO(Shm)->Proc.PM_ext = (struct PMU_ST){.v = 3, .p = 0x5}; + break; + case 0b0111: RO(Shm)->Proc.PM_ext = (struct PMU_ST){.v = 3, .p = 0x7}; + break; + case 0b1000: RO(Shm)->Proc.PM_ext = (struct PMU_ST){.v = 3, .p = 0x8}; + break; + case 0b1001: RO(Shm)->Proc.PM_ext = (struct PMU_ST){.v = 3, .p = 0x9}; + break; + case 0b1010: RO(Shm)->Proc.PM_ext = (struct PMU_ST){.v = 3, .p = 0xa}; + break; + default: RO(Shm)->Proc.PM_version = 0; + break; + } +} + +void HyperThreading(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc)) +{ /* Update the HyperThreading state. */ + RO(Shm)->Proc.Features.HyperThreading = RO(Proc)->Features.HTT_Enable; +} + +double ComputeTAU(unsigned char Y, unsigned char Z, double TU) +{ + return COMPUTE_TAU(Y, Z, TU); +} + +void PowerInterface(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc)) +{ + unsigned short pwrUnits = 0, pwrVal; + enum PWR_DOMAIN pw; + UNUSED(pwrUnits); + UNUSED(pwrVal); + UNUSED(pw); + switch (KIND_OF_FORMULA(RO(Proc)->powerFormula)) { + case POWER_KIND_NONE: + break; + } +} + +void ThermalPoint(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc)) +{ + memcpy(&RO(Shm)->Proc.ThermalPoint, &RO(Proc)->ThermalPoint, + sizeof(THERMAL_POINT)); +} + +void Technology_Update( RO(SHM_STRUCT) *RO(Shm), + RO(PROC) *RO(Proc), RW(PROC) *RW(Proc) ) +{ /* Technologies aggregation. */ + RO(Shm)->Proc.Technology.VM = BITWISEAND_CC(LOCKLESS, + RW(Proc)->VM, + RO(Proc)->CR_Mask) != 0; +} + +void Mitigation_Stage( RO(SHM_STRUCT) *RO(Shm), + RO(PROC) *RO(Proc), RW(PROC) *RW(Proc) ) +{ + const unsigned short + CLRBHB = BITWISEAND_CC( LOCKLESS, + RW(Proc)->CLRBHB, + RO(Proc)->SPEC_CTRL_Mask) != 0, + + CSV2_1 = BITWISEAND_CC( LOCKLESS, + RW(Proc)->CSV2_1, + RO(Proc)->SPEC_CTRL_Mask) != 0, + + CSV2_2 = BITWISEAND_CC( LOCKLESS, + RW(Proc)->CSV2_2, + RO(Proc)->SPEC_CTRL_Mask) != 0, + + CSV2_3 = BITWISEAND_CC( LOCKLESS, + RW(Proc)->CSV2_3, + RO(Proc)->SPEC_CTRL_Mask) != 0, + + CSV3 = BITWISEAND_CC( LOCKLESS, + RW(Proc)->CSV3, + RO(Proc)->SPEC_CTRL_Mask) != 0, + + SSBS = BITCMP_CC( LOCKLESS, + RW(Proc)->SSBS, + RO(Proc)->SPEC_CTRL_Mask ); + + RO(Shm)->Proc.Mechanisms.CLRBHB = CLRBHB ? 0b11 : 0b00; + + RO(Shm)->Proc.Mechanisms.CSV2 = CSV_NONE; + if (CSV2_1) { + if (RO(Shm)->Proc.Features.CSV2 == 0b0001) { + RO(Shm)->Proc.Mechanisms.CSV2 = CSV2_1p1; + } else if (RO(Shm)->Proc.Features.CSV2 == 0b0010) { + RO(Shm)->Proc.Mechanisms.CSV2 = CSV2_1p2; + } else if (RO(Shm)->Proc.Features.CSV2 == 0b0000) { + RO(Shm)->Proc.Mechanisms.CSV2 = CSV2_1p0; + } + } else if (CSV2_2) { + RO(Shm)->Proc.Mechanisms.CSV2 = CSV2_2p0; + } else if (CSV2_3) { + RO(Shm)->Proc.Mechanisms.CSV2 = CSV2_3p0; + } + RO(Shm)->Proc.Mechanisms.CSV3 = CSV3 ? 0b11 : 0b00; + + switch (RO(Shm)->Proc.Features.SSBS) { + case 0b0001: + case 0b0010: + RO(Shm)->Proc.Mechanisms.SSBS = 1; + break; + case 0b0000: + default: + RO(Shm)->Proc.Mechanisms.SSBS = 0; + break; + } + RO(Shm)->Proc.Mechanisms.SSBS += (2 * SSBS); +} + +static char *Chipset[CHIPSETS] = { + [IC_CHIPSET] = NULL, +}; + + +void Uncore_Update( RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), + RO(CORE) *RO(Core) ) +{ + /* Copy the # of controllers. */ + RO(Shm)->Uncore.CtrlCount = RO(Proc)->Uncore.CtrlCount; + /* Decode the Memory Controller for each found vendor:device */ + Chipset[IC_CHIPSET] = RO(Proc)->Features.Info.Vendor.ID; + RO(Shm)->Uncore.ChipID = RO(Proc)->Uncore.ClusterRev.Revision + | (RO(Proc)->Uncore.ClusterRev.Variant << 4); + RO(Shm)->Uncore.Chipset.ArchID = IC_CHIPSET; + /* Copy the chipset codename. */ + StrCopy(RO(Shm)->Uncore.Chipset.CodeName, + Chipset[RO(Shm)->Uncore.Chipset.ArchID], + CODENAME_LEN); + /* Copy the Uncore clock ratios. */ + memcpy( RO(Shm)->Uncore.Boost, + RO(Proc)->Uncore.Boost, + (UNCORE_BOOST(SIZE)) * sizeof(unsigned int) ); +} + +void Topology(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) **RO(Core), + unsigned int cpu) +{ + unsigned int level; + /* Copy each Core topology. */ + RO(Shm)->Cpu[cpu].Topology.PN = RO(Core, AT(cpu))->T.PN; + RO(Shm)->Cpu[cpu].Topology.BSP = RO(Core, AT(cpu))->T.BSP ? 1:0; + RO(Shm)->Cpu[cpu].Topology.MPID = RO(Core, AT(cpu))->T.MPID; + RO(Shm)->Cpu[cpu].Topology.CoreID = RO(Core, AT(cpu))->T.CoreID; + RO(Shm)->Cpu[cpu].Topology.ThreadID = RO(Core, AT(cpu))->T.ThreadID; + RO(Shm)->Cpu[cpu].Topology.PackageID = RO(Core, AT(cpu))->T.PackageID; + RO(Shm)->Cpu[cpu].Topology.Cluster.ID = RO(Core, AT(cpu))->T.Cluster.ID; + RO(Shm)->Cpu[cpu].Topology.Cluster.Hybrid_ID = \ + RO(Core, AT(cpu))->T.Cluster.Hybrid_ID; + /* Aggregate the Caches topology. */ + for (level = 0; level < CACHE_MAX_LEVEL; level++) + if (RO(Core, AT(cpu))->T.Cache[level].ccsid.value != 0) { + RO(Shm)->Cpu[cpu].Topology.Cache[level].LineSz = \ + RO(Core, AT(cpu))->T.Cache[level].ccsid.LineSz + 4; + + RO(Shm)->Cpu[cpu].Topology.Cache[level].Set = \ + RO(Core, AT(cpu))->T.Cache[level].ccsid.Set + 1; + + RO(Shm)->Cpu[cpu].Topology.Cache[level].Way = \ + RO(Core, AT(cpu))->T.Cache[level].ccsid.Assoc + 1; + + RO(Shm)->Cpu[cpu].Topology.Cache[level].Size = \ + RO(Shm)->Cpu[cpu].Topology.Cache[level].Way + << RO(Shm)->Cpu[cpu].Topology.Cache[level].LineSz; + + RO(Shm)->Cpu[cpu].Topology.Cache[level].Size = \ + RO(Shm)->Cpu[cpu].Topology.Cache[level].Set + * RO(Shm)->Cpu[cpu].Topology.Cache[level].Size; + + RO(Shm)->Cpu[cpu].Topology.Cache[level].Feature.WriteBack = \ + RO(Core, AT(cpu))->T.Cache[level].ccsid.WrBack; + } +} + +void CStates(RO(SHM_STRUCT) *RO(Shm), RO(CORE) **RO(Core), unsigned int cpu) +{ /* Copy the C-State Configuration Control */ + RO(Shm)->Cpu[cpu].Query.CfgLock = RO(Core, AT(cpu))->Query.CfgLock; + + RO(Shm)->Cpu[cpu].Query.CStateLimit = \ + RO(Core, AT(cpu))->Query.CStateLimit; + /* Copy the Max C-State Inclusion */ + RO(Shm)->Cpu[cpu].Query.IORedir = RO(Core, AT(cpu))->Query.IORedir; + /* Copy any architectural C-States I/O Base Address */ + RO(Shm)->Cpu[cpu].Query.CStateBaseAddr = \ + RO(Core, AT(cpu))->Query.CStateBaseAddr; +} + +void PowerThermal( RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), + RO(CORE) **RO(Core), unsigned int cpu ) +{ + UNUSED(RO(Proc)); + + RO(Shm)->Cpu[cpu].PowerThermal.HWP.Capabilities.Highest = \ + RO(Core, AT(cpu))->PowerThermal.HWP_Capabilities.Highest; + + RO(Shm)->Cpu[cpu].PowerThermal.HWP.Capabilities.Guaranteed = \ + RO(Core, AT(cpu))->PowerThermal.HWP_Capabilities.Guaranteed; + + RO(Shm)->Cpu[cpu].PowerThermal.HWP.Capabilities.Most_Efficient = \ + RO(Core, AT(cpu))->PowerThermal.HWP_Capabilities.Most_Efficient; + + RO(Shm)->Cpu[cpu].PowerThermal.HWP.Capabilities.Lowest = \ + RO(Core, AT(cpu))->PowerThermal.HWP_Capabilities.Lowest; + + RO(Shm)->Cpu[cpu].PowerThermal.HWP.Request.Minimum_Perf = \ + RO(Core, AT(cpu))->PowerThermal.HWP_Request.Minimum_Perf; + + RO(Shm)->Cpu[cpu].PowerThermal.HWP.Request.Maximum_Perf = \ + RO(Core, AT(cpu))->PowerThermal.HWP_Request.Maximum_Perf; + + RO(Shm)->Cpu[cpu].PowerThermal.HWP.Request.Desired_Perf = \ + RO(Core, AT(cpu))->PowerThermal.HWP_Request.Desired_Perf; + + RO(Shm)->Cpu[cpu].PowerThermal.HWP.Request.Energy_Pref = \ + RO(Core, AT(cpu))->PowerThermal.HWP_Request.Energy_Pref; + + memcpy( &RO(Shm)->Cpu[cpu].ThermalPoint, + &RO(Core, AT(cpu))->ThermalPoint, + sizeof(THERMAL_POINT) ); +} + +void SystemRegisters( RO(SHM_STRUCT) *RO(Shm), RO(CORE) **RO(Core), + unsigned int cpu ) +{ + RO(Shm)->Cpu[cpu].SystemRegister.FLAGS = \ + RO(Core, AT(cpu))->SystemRegister.FLAGS; + + RO(Shm)->Cpu[cpu].SystemRegister.SCTLR = \ + RO(Core, AT(cpu))->SystemRegister.SCTLR; + + RO(Shm)->Cpu[cpu].SystemRegister.SCTLR2 = \ + RO(Core, AT(cpu))->SystemRegister.SCTLR2; + + RO(Shm)->Cpu[cpu].SystemRegister.EL = \ + RO(Core, AT(cpu))->SystemRegister.EL; + + RO(Shm)->Cpu[cpu].SystemRegister.FPSR = \ + RO(Core, AT(cpu))->SystemRegister.FPSR; + + RO(Shm)->Cpu[cpu].SystemRegister.SVCR = \ + RO(Core, AT(cpu))->SystemRegister.SVCR; + + RO(Shm)->Cpu[cpu].Query.SCTLRX = RO(Core, AT(cpu))->Query.SCTLRX; +} + +void SysGate_OS_Driver(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc)) +{ + memset(&RO(Shm)->SysGate.OS, 0, sizeof(OS_DRIVER)); + if (strlen(RO(Proc)->OS.IdleDriver.Name) > 0) { + int idx; + + StrCopy(RO(Shm)->SysGate.OS.IdleDriver.Name, + RO(Proc)->OS.IdleDriver.Name, + CPUIDLE_NAME_LEN); + + RO(Shm)->SysGate.OS.IdleDriver.stateCount = \ + RO(Proc)->OS.IdleDriver.stateCount; + + RO(Shm)->SysGate.OS.IdleDriver.stateLimit = \ + RO(Proc)->OS.IdleDriver.stateLimit; + + for (idx = 0; idx < RO(Shm)->SysGate.OS.IdleDriver.stateCount; idx++) + { + StrCopy(RO(Shm)->SysGate.OS.IdleDriver.State[idx].Name, + RO(Proc)->OS.IdleDriver.State[idx].Name, + CPUIDLE_NAME_LEN); + + StrCopy(RO(Shm)->SysGate.OS.IdleDriver.State[idx].Desc, + RO(Proc)->OS.IdleDriver.State[idx].Desc, + CPUIDLE_NAME_LEN); + + RO(Shm)->SysGate.OS.IdleDriver.State[idx].exitLatency = \ + RO(Proc)->OS.IdleDriver.State[idx].exitLatency; + + RO(Shm)->SysGate.OS.IdleDriver.State[idx].powerUsage = \ + RO(Proc)->OS.IdleDriver.State[idx].powerUsage; + + RO(Shm)->SysGate.OS.IdleDriver.State[idx].targetResidency = \ + RO(Proc)->OS.IdleDriver.State[idx].targetResidency; + } + } + if (strlen(RO(Proc)->OS.FreqDriver.Name) > 0) { + StrCopy(RO(Shm)->SysGate.OS.FreqDriver.Name, + RO(Proc)->OS.FreqDriver.Name, + CPUFREQ_NAME_LEN); + } + if (strlen(RO(Proc)->OS.FreqDriver.Governor) > 0) { + StrCopy(RO(Shm)->SysGate.OS.FreqDriver.Governor, + RO(Proc)->OS.FreqDriver.Governor, + CPUFREQ_NAME_LEN); + } +} + +void SysGate_Kernel(REF *Ref) +{ + RO(SHM_STRUCT) *RO(Shm) = Ref->RO(Shm); + RO(SYSGATE) *SysGate = Ref->RO(SysGate); + + RO(Shm)->SysGate.kernel.version = SysGate->kernelVersionNumber >> 16; + RO(Shm)->SysGate.kernel.major = SysGate->kernelVersionNumber >> 8; + RO(Shm)->SysGate.kernel.major = RO(Shm)->SysGate.kernel.major & 0xff; + RO(Shm)->SysGate.kernel.minor = SysGate->kernelVersionNumber & 0xff; + + memcpy(RO(Shm)->SysGate.sysname, SysGate->sysname, MAX_UTS_LEN); + memcpy(RO(Shm)->SysGate.release, SysGate->release, MAX_UTS_LEN); + memcpy(RO(Shm)->SysGate.version, SysGate->version, MAX_UTS_LEN); + memcpy(RO(Shm)->SysGate.machine, SysGate->machine, MAX_UTS_LEN); +} + +#define CS_Reset_Array(_CS) \ +({ \ + _CS.index[0] = 0; \ +}) + +#define CS_Seek_Store(_fd, _ptr, _CS) \ +({ \ + size_t length; \ + if (fscanf(_fd, "%s", _ptr) == 1) { \ + unsigned char offset; \ + length = strlen(_ptr); \ + _ptr += length; \ + (*_ptr) = 0x0; \ + _ptr++; \ + length = _ptr - _CS.array; \ + offset = (unsigned char) length; \ + _CS.index[0]++; \ + _CS.index[_CS.index[0]] = offset; \ + } \ +}) + +void ClockSource_Update(RO(SHM_STRUCT) *RO(Shm)) +{ + FILE *fd; + + CS_Reset_Array(RO(Shm)->CS); + + if ((fd = fopen(CLOCKSOURCE_PATH"/current_clocksource", "r")) != NULL) + { + char *ptr = RO(Shm)->CS.array; + + CS_Seek_Store(fd, ptr, RO(Shm)->CS); + + fclose(fd); + if ((fd = fopen(CLOCKSOURCE_PATH"/available_clocksource", "r")) != NULL) + { + do { + CS_Seek_Store(fd, ptr, RO(Shm)->CS); + } while (!feof(fd) && (RO(Shm)->CS.index[0] < 7)); + fclose(fd); + } + } +} + +long ClockSource_Submit(RO(SHM_STRUCT) *RO(Shm), unsigned char index) +{ + if (index <= RO(Shm)->CS.index[0]) + { + FILE *fd; + if ((fd = fopen(CLOCKSOURCE_PATH"/current_clocksource", "w")) != NULL) + { + char *ptr = &RO(Shm)->CS.array[RO(Shm)->CS.index[index]]; + fprintf(fd, "%s", ptr); + fclose(fd); + return 0; + } + } + return -EINVAL; +} + +static const int reverseSign[2] = {+1, -1}; + +static int SortByRuntime(const void *p1, const void *p2, void *arg) +{ + TASK_MCB *task1 = (TASK_MCB*) p1, *task2 = (TASK_MCB*) p2; + REF *Ref = (REF*) arg; + + int sort = task1->runtime < task2->runtime ? +1 : -1; + sort *= reverseSign[Ref->RO(Shm)->SysGate.reverseOrder]; + return sort; +} + +static int SortByUsertime(const void *p1, const void *p2, void *arg) +{ + TASK_MCB *task1 = (TASK_MCB*) p1, *task2 = (TASK_MCB*) p2; + REF *Ref = (REF*) arg; + + int sort = task1->usertime < task2->usertime ? +1 : -1; + sort *= reverseSign[Ref->RO(Shm)->SysGate.reverseOrder]; + return sort; +} + +static int SortBySystime(const void *p1, const void *p2, void *arg) +{ + TASK_MCB *task1 = (TASK_MCB*) p1, *task2 = (TASK_MCB*) p2; + REF *Ref = (REF*) arg; + + int sort = task1->systime < task2->systime ? +1 : -1; + sort *= reverseSign[Ref->RO(Shm)->SysGate.reverseOrder]; + return sort; +} + +static int SortByState(const void *p1, const void *p2, void *arg) +{ + TASK_MCB *task1 = (TASK_MCB*) p1, *task2 = (TASK_MCB*) p2; + REF *Ref = (REF*) arg; + + int sort = task1->state < task2->state ? -1 : +1; + sort *= reverseSign[Ref->RO(Shm)->SysGate.reverseOrder]; + return sort; +} + +static int SortByPID(const void *p1, const void *p2, void *arg) +{ + TASK_MCB *task1 = (TASK_MCB*) p1, *task2 = (TASK_MCB*) p2; + REF *Ref = (REF*) arg; + + int sort = task1->pid < task2->pid ? -1 : +1; + sort *= reverseSign[Ref->RO(Shm)->SysGate.reverseOrder]; + return sort; +} + +static int SortByCommand(const void *p1, const void *p2, void *arg) +{ + TASK_MCB *task1 = (TASK_MCB*) p1, *task2 = (TASK_MCB*) p2; + REF *Ref = (REF*) arg; + + int sort = strncmp(task1->comm, task2->comm, TASK_COMM_LEN); + sort *= reverseSign[Ref->RO(Shm)->SysGate.reverseOrder]; + return sort; +} + +typedef int (*SORTBYFUNC)(const void *, const void *, void *); + +static SORTBYFUNC SortByFunc[SORTBYCOUNT] = { + SortByState, + SortByRuntime, + SortByUsertime, + SortBySystime, + SortByPID, + SortByCommand +}; + +static int SortByTracker(const void *p1, const void *p2, void *arg) +{ + TASK_MCB *task1 = (TASK_MCB*) p1, *task2 = (TASK_MCB*) p2; + REF *Ref = (REF*) arg; + + int sort = (task1->pid == Ref->RO(Shm)->SysGate.trackTask) ? + -1 : (task2->pid == Ref->RO(Shm)->SysGate.trackTask) ? + +1 : SortByFunc[Ref->RO(Shm)->SysGate.sortByField](p1, p2, Ref); + return sort; +} + +void SysGate_Update(REF *Ref) +{ + struct sysinfo info; + RO(SHM_STRUCT) *RO(Shm) = Ref->RO(Shm); + RO(SYSGATE) *SysGate = Ref->RO(SysGate); + RO(PROC) *RO(Proc) = Ref->RO(Proc); + + RO(Shm)->SysGate.taskCount = SysGate->taskCount; + + memcpy( RO(Shm)->SysGate.taskList, SysGate->taskList, + (size_t) RO(Shm)->SysGate.taskCount * sizeof(TASK_MCB)); + + qsort_r(RO(Shm)->SysGate.taskList, + (size_t) RO(Shm)->SysGate.taskCount, sizeof(TASK_MCB), + RO(Shm)->SysGate.trackTask ? + SortByTracker + : SortByFunc[RO(Shm)->SysGate.sortByField], Ref); + + if (sysinfo(&info) == 0) { + RO(Shm)->SysGate.memInfo.totalram = info.totalram >> 10; + RO(Shm)->SysGate.memInfo.sharedram = info.sharedram >> 10; + RO(Shm)->SysGate.memInfo.freeram = info.freeram >> 10; + RO(Shm)->SysGate.memInfo.bufferram = info.bufferram >> 10; + RO(Shm)->SysGate.memInfo.totalhigh = info.totalhigh >> 10; + RO(Shm)->SysGate.memInfo.freehigh = info.freehigh >> 10; + RO(Shm)->SysGate.procCount = info.procs; + } + RO(Shm)->SysGate.OS.IdleDriver.stateLimit = + RO(Proc)->OS.IdleDriver.stateLimit; +} + +void Package_Update( RO(SHM_STRUCT) *RO(Shm), + RO(PROC) *RO(Proc), RW(PROC) *RW(Proc) ) +{ /* Copy the operational settings. */ + RO(Shm)->Registration.AutoClock = RO(Proc)->Registration.AutoClock; + RO(Shm)->Registration.Experimental= RO(Proc)->Registration.Experimental; + RO(Shm)->Registration.HotPlug = RO(Proc)->Registration.HotPlug; + RO(Shm)->Registration.PCI = RO(Proc)->Registration.PCI; + BITSTOR(LOCKLESS,RO(Shm)->Registration.NMI, RO(Proc)->Registration.NMI); + RO(Shm)->Registration.Driver = RO(Proc)->Registration.Driver; + /* Copy the timer interval delay. */ + RO(Shm)->Sleep.Interval = RO(Proc)->SleepInterval; + /* Compute the polling wait time based on the timer interval. */ + RO(Shm)->Sleep.pollingWait=TIMESPEC((RO(Shm)->Sleep.Interval * 1000000L) + / WAKEUP_RATIO); + /* Copy the SysGate tick steps. */ + RO(Shm)->SysGate.tickReset = RO(Proc)->tickReset; + RO(Shm)->SysGate.tickStep = RO(Proc)->tickStep; + + Architecture(RO(Shm), RO(Proc)); + + PerformanceMonitoring(RO(Shm), RO(Proc)); + + HyperThreading(RO(Shm), RO(Proc)); + + PowerInterface(RO(Shm), RO(Proc)); + + ThermalPoint(RO(Shm), RO(Proc)); + + Mitigation_Stage(RO(Shm), RO(Proc), RW(Proc)); + /* Aggregate OS idle driver data and Clock Source */ + SysGate_OS_Driver(RO(Shm), RO(Proc)); + ClockSource_Update(RO(Shm)); +} + +void PerCore_Update( RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), + RO(CORE) **RO(Core), unsigned int cpu ) +{ + if (BITVAL(RO(Core, AT(cpu))->OffLine, HW)) { + BITSET(LOCKLESS, RO(Shm)->Cpu[cpu].OffLine, HW); + } else { + BITCLR(LOCKLESS, RO(Shm)->Cpu[cpu].OffLine, HW); + } + /* Initialize all clock ratios. */ + memcpy( RO(Shm)->Cpu[cpu].Boost, RO(Core, AT(cpu))->Boost, + (BOOST(SIZE)) * sizeof(unsigned int) ); + + RO(Shm)->Cpu[cpu].Query.Revision = RO(Core, AT(cpu))->Query.Revision; + + Topology(RO(Shm), RO(Proc), RO(Core), cpu); + + CStates(RO(Shm), RO(Core), cpu); + + PowerThermal(RO(Shm), RO(Proc), RO(Core), cpu); + + SystemRegisters(RO(Shm), RO(Core), cpu); +} + +#define SysOnce(drv) ioctl(drv, COREFREQ_IOCTL_SYSONCE) + +int SysGate_OnDemand(REF *Ref, int operation) +{ + int rc = -1; + const size_t allocPages = \ + (size_t)PAGE_SIZE << Ref->RO(Proc)->Gate.ReqMem.Order; + + if (operation == 0) { + if (Ref->RO(SysGate) != NULL) { + if ((rc = munmap(Ref->RO(SysGate), allocPages)) == 0) { + Ref->RO(SysGate) = NULL; + } + } else { + rc = -1; + } + } else { + if (Ref->RO(SysGate) == NULL) { + const off_t vm_pgoff = ID_RO_VMA_GATE * PAGE_SIZE; + RO(SYSGATE) *MapGate = mmap(NULL, allocPages, + PROT_READ, + MAP_SHARED, + Ref->fd->drv, vm_pgoff); + if (MapGate != MAP_FAILED) { + Ref->RO(SysGate) = MapGate; + rc = 0; + } + } else { + rc = 0; + } + } + return rc; +} + +void SysGate_Toggle(REF *Ref, unsigned int state) +{ + if (state == 0) { + if (BITWISEAND(LOCKLESS, Ref->RO(Shm)->SysGate.Operation, 0x1)) { + /* Stop SysGate */ + BITCLR(LOCKLESS, Ref->RO(Shm)->SysGate.Operation, 0); + /* Notify */ + BITWISESET(LOCKLESS, PendingSync, BIT_MASK_NTFY); + } + } else { + if (!BITWISEAND(LOCKLESS, Ref->RO(Shm)->SysGate.Operation, 0x1)) { + if (SysGate_OnDemand(Ref, 1) == 0) { + /* Start SysGate */ + BITSET(LOCKLESS, Ref->RO(Shm)->SysGate.Operation, 0); + /* Notify */ + BITWISESET(LOCKLESS, PendingSync,BIT_MASK_NTFY); + } + } + } + if (BITWISEAND(LOCKLESS, Ref->RO(Shm)->SysGate.Operation, 0x1)) + if (SysOnce(Ref->fd->drv) == RC_OK_SYSGATE) { + /* Copy system information. */ + SysGate_Kernel(Ref); + } +} + +void Master_Ring_Handler(REF *Ref, unsigned int rid) +{ + if (!RING_NULL(Ref->RW(Shm)->Ring[rid])) + { + RING_CTRL ctrl __attribute__ ((aligned(16))); + RING_READ(Ref->RW(Shm)->Ring[rid], ctrl); + int rc = -EPERM, drc = -EPERM; + + if ( (ctrl.cmd >= COREFREQ_IOCTL_SYSUPDT) + && (ctrl.cmd <= COREFREQ_IOCTL_CLEAR_EVENTS) ) + { + rc = ioctl(Ref->fd->drv, ctrl.cmd, ctrl.arg); + drc = errno; + } + if (Quiet & 0x100) { + printf("\tRING[%u](%x,%x)(%llx)>(%d,%d)\n", + rid, ctrl.cmd, ctrl.sub, ctrl.arg, rc, drc); + } + switch (rc) { + case -EPERM: + { + RING_CTRL error __attribute__ ((aligned(16))) = { + .arg = ctrl.arg, + .cmd = ctrl.cmd, + .drc = (unsigned int) drc, + .tds = ELAPSED(Ref->RO(Shm)->StartedAt) + }; + RING_WRITE_1xPARAM( error.sub, + Ref->RW(Shm)->Error, + error.cmd, + error.arg ); + } + break; + case RC_OK_SYSGATE: + SysGate_OS_Driver(Ref->RO(Shm), Ref->RO(Proc)); + fallthrough; + case RC_SUCCESS: /* Platform changed -> pending notification. */ + BITWISESET(LOCKLESS, PendingSync, BIT_MASK_NTFY); + break; + case RC_OK_COMPUTE: /* Compute claimed -> pending notification. */ + BITWISESET(LOCKLESS, PendingSync, BIT_MASK_COMP); + break; + } + } +} + +void Child_Ring_Handler(REF *Ref, unsigned int rid) +{ + if (!RING_NULL(Ref->RW(Shm)->Ring[rid])) + { + RING_CTRL ctrl __attribute__ ((aligned(16))); + RING_READ(Ref->RW(Shm)->Ring[rid], ctrl); + + switch (ctrl.cmd) { + case COREFREQ_KERNEL_MISC: + switch (ctrl.dl.hi) { + case MACHINE_CLOCK_SOURCE: + if (ClockSource_Submit(Ref->RO(Shm), (unsigned char) ctrl.dl.lo) == 0) { + ClockSource_Update(Ref->RO(Shm)); + } + break; + } + break; + case COREFREQ_SESSION_APP: + switch (ctrl.sub) { + case SESSION_CLI: + Ref->RO(Shm)->App.Cli = (pid_t) ctrl.arg; + break; + case SESSION_GUI: + Ref->RO(Shm)->App.GUI = (pid_t) ctrl.arg; + break; + } + break; + case COREFREQ_TASK_MONITORING: + switch (ctrl.sub) { + case TASK_TRACKING: + Ref->RO(Shm)->SysGate.trackTask = (pid_t) ctrl.arg; + break; + case TASK_SORTING: + { + enum SORTBYFIELD sortByField = (enum SORTBYFIELD) ctrl.dl.lo; + Ref->RO(Shm)->SysGate.sortByField = sortByField % SORTBYCOUNT; + } + break; + case TASK_INVERSING: + { + const int reverseOrder = !!!Ref->RO(Shm)->SysGate.reverseOrder; + Ref->RO(Shm)->SysGate.reverseOrder = reverseOrder; + } + break; + } + BITWISESET(LOCKLESS, Ref->RW(Shm)->Proc.Sync, BIT_MASK_NTFY); + break; + case COREFREQ_TOGGLE_SYSGATE: + switch (ctrl.arg) { + case COREFREQ_TOGGLE_OFF: + case COREFREQ_TOGGLE_ON: + SysGate_Toggle(Ref, ctrl.arg); + BITWISESET(LOCKLESS, Ref->RW(Shm)->Proc.Sync, BIT_MASK_NTFY); + break; + } + break; + case COREFREQ_ORDER_MACHINE: + switch (ctrl.arg) { + case COREFREQ_TOGGLE_OFF: + SCHEDULER_STOP: + if (BITVAL(Ref->RW(Shm)->Proc.Sync, BURN)) + { + BITCLR(BUS_LOCK, Ref->RW(Shm)->Proc.Sync, BURN); + + while (BITWISEAND_CC(BUS_LOCK, roomCore, roomSeed)) + { + if (BITVAL(Shutdown, SYNC)) { /* SpinLock */ + break; + } + } + BITSTOR_CC(BUS_LOCK, Ref->RO(Shm)->roomSched, roomClear); + + Ref->Slice.Func = Slice_NOP; + Ref->Slice.arg = 0; + Ref->Slice.pattern = RESET_CSP; + /* Notify the Slice module has stopped */ + BITWISESET(LOCKLESS, Ref->RW(Shm)->Proc.Sync, BIT_MASK_NTFY); + } + break; + } + break; + default: + { + RING_SLICE *porder = order_list; + + while (porder->func != NULL) + { + if ((porder->ctrl.cmd == ctrl.cmd) && (porder->ctrl.sub == ctrl.sub)) + { + if ( !BITVAL(Ref->RW(Shm)->Proc.Sync, BURN) + || ((Ref->Slice.Func == Slice_Turbo) && (Ref->Slice.pattern == USR_CPU) + && (ctrl.cmd == COREFREQ_ORDER_TURBO) && (ctrl.sub == USR_CPU))) + { + if (ctrl.sub == USR_CPU) { + if (BITVAL_CC(Ref->RO(Shm)->roomSched, ctrl.dl.lo)) + { + BITCLR_CC(LOCKLESS, Ref->RO(Shm)->roomSched, ctrl.dl.lo); + + if (!BITWISEAND_CC(BUS_LOCK, Ref->RO(Shm)->roomSched, roomSeed)) + { + goto SCHEDULER_STOP; + } + } else { + BITSET_CC(LOCKLESS, Ref->RO(Shm)->roomSched, ctrl.dl.lo); + + goto SCHEDULER_START; + } + } else { + SliceScheduling(Ref->RO(Shm), ctrl.dl.lo, porder->pattern); + + SCHEDULER_START: + Ref->Slice.Func = porder->func; + Ref->Slice.arg = porder->ctrl.dl.lo; + Ref->Slice.pattern = porder->pattern; + + BITSET(BUS_LOCK, Ref->RW(Shm)->Proc.Sync, BURN); + } + /* Notify the Slice module is starting up */ + BITWISESET(LOCKLESS, Ref->RW(Shm)->Proc.Sync, BIT_MASK_NTFY); + } + break; + } + porder++; + } + } + break; + } + if (Quiet & 0x100) { + printf("\tRING[%u](%x,%x)(%hx:%hx,%hx:%hx)\n", + rid, ctrl.cmd, ctrl.sub, + ctrl.dh.hi, ctrl.dh.lo, ctrl.dl.hi, ctrl.dl.lo); + } + } +} + +int ServerFollowService(SERVICE_PROC *pSlave, + SERVICE_PROC *pMaster, + pthread_t tid) +{ + if (pSlave->Proc != pMaster->Proc) { + pSlave->Proc = pMaster->Proc; + + cpu_set_t cpuset; + CPU_ZERO(&cpuset); + CPU_SET(pSlave->Core, &cpuset); + if (pSlave->Thread != -1) { + const signed int cpu = pSlave->Thread; + CPU_SET(cpu , &cpuset); + } + return pthread_setaffinity_np(tid, sizeof(cpu_set_t), &cpuset); + } + return -1; +} + +static void *Emergency_Handler(void *pRef) +{ + REF *Ref = (REF *) pRef; + unsigned int rid = (Ref->CPID == 0); + SERVICE_PROC localService = RESET_SERVICE; + int caught = 0, leave = 0; + char handlerName[TASK_COMM_LEN] = { + 'c','o','r','e','f','r','e','q','d','-','r','i','n','g','0',0 + }; + handlerName[14] += (char) rid; + + pthread_t tid = pthread_self(); + + if(ServerFollowService(&localService, &Ref->RO(Shm)->Proc.Service,tid) == 0) + { + pthread_setname_np(tid, handlerName); + } + while (!leave) { + caught=sigtimedwait(&Ref->Signal,NULL,&Ref->RO(Shm)->Sleep.ringWaiting); + if (caught != -1) { + switch (caught) { + case SIGUSR2: + if (Ref->CPID) { /* Stop SysGate */ + SysGate_Toggle(Ref, 0); + } + break; + case SIGUSR1: + if (Ref->CPID) { /* Start SysGate */ + SysGate_Toggle(Ref, 1); + } + break; + case SIGCHLD: /* Exit Ring Thread */ + leave = 0x1; + fallthrough; + case SIGSTKFLT: + case SIGXFSZ: + case SIGXCPU: + case SIGSEGV: + case SIGTERM: + case SIGQUIT: + case SIGALRM: + case SIGABRT: + case SIGPIPE: + case SIGTRAP: + case SIGSYS: + case SIGFPE: + case SIGBUS: + case SIGILL: + case SIGINT: /* [CTRL] + [C] */ + BITSET(LOCKLESS, Shutdown, SYNC); + break; + case SIGVTALRM: + case SIGWINCH: + case SIGTTOU: + case SIGTTIN: + case SIGTSTP: + case SIGPROF: + case SIGHUP: + case SIGPWR: + case SIGIO: + default: /* RTMIN ... RTMAX */ + break; + } + } else if (errno == EAGAIN) { + if (Ref->CPID) { + Master_Ring_Handler(Ref, rid); + } else { + Child_Ring_Handler(Ref, rid); + } + } + ServerFollowService(&localService, &Ref->RO(Shm)->Proc.Service, tid); + } + return NULL; +} + +void Emergency_Command(REF *Ref, unsigned int cmd) +{ + switch (cmd) { + case 0: + if (Ref->Started) { + if (!pthread_kill(Ref->KID, SIGCHLD)) { + if (!pthread_join(Ref->KID, NULL)) { + Ref->Started = 0; + } + } + } + break; + case 1: { + const int ignored[] = { + SIGIO, SIGPROF, SIGPWR, SIGHUP, SIGTSTP, + SIGTTIN, SIGTTOU, SIGVTALRM, SIGWINCH + }, handled[] = { + SIGUSR1, SIGUSR2, SIGCHLD, SIGINT, SIGILL, SIGBUS, + SIGFPE, SIGSYS, SIGTRAP, SIGPIPE, SIGABRT, SIGALRM, + SIGQUIT, SIGTERM, SIGSEGV, SIGXCPU, SIGXFSZ, SIGSTKFLT + }; + /* SIGKILL,SIGCONT,SIGSTOP,SIGURG: Reserved */ + const ssize_t ignoredCount = sizeof(ignored) / sizeof(int), + handledCount = sizeof(handled) / sizeof(int); + int signo; + + sigemptyset(&Ref->Signal); + for (signo = SIGRTMIN; signo <= SIGRTMAX; signo++) { + sigaddset(&Ref->Signal, signo); + } + for (signo = 0; signo < ignoredCount; signo++) { + sigaddset(&Ref->Signal, ignored[signo]); + } + for (signo = 0; signo < handledCount; signo++) { + sigaddset(&Ref->Signal, handled[signo]); + } + if (!pthread_sigmask(SIG_BLOCK, &Ref->Signal, NULL)) + { + if(!pthread_create(&Ref->KID, NULL, Emergency_Handler, Ref)) + { + Ref->Started = 1; + } + } + } + break; + } +} + +static void Pkg_ComputeThermal_None( struct PKG_FLIP_FLOP *PFlip, + struct FLIP_FLOP *SProc ) +{ + UNUSED(PFlip); + UNUSED(SProc); +} + +static void Pkg_ComputeVoltage_None(struct PKG_FLIP_FLOP *PFlip) +{ + UNUSED(PFlip); +} + +static void Pkg_ComputePower_None(RW(PROC) *RW(Proc), struct FLIP_FLOP *CFlop) +{ + UNUSED(RW(Proc)); + UNUSED(CFlop); +} + +static void Pkg_ResetPower_None(PROC_RW *Proc) +{ + UNUSED(Proc); +} + +void Pkg_ResetSensorLimits(PROC_STRUCT *Pkg) +{ + enum PWR_DOMAIN pw; + for (pw = PWR_DOMAIN(PKG); pw < PWR_DOMAIN(SIZE); pw++) + { + RESET_SENSOR_LIMIT(ENERGY, LOWEST , Pkg->State.Energy[pw].Limit); + RESET_SENSOR_LIMIT(ENERGY, HIGHEST, Pkg->State.Energy[pw].Limit ); + RESET_SENSOR_LIMIT(POWER , LOWEST , Pkg->State.Power[pw].Limit ); + RESET_SENSOR_LIMIT(POWER , HIGHEST, Pkg->State.Power[pw].Limit ); + } + RESET_SENSOR_LIMIT(VOLTAGE, LOWEST, Pkg->State.Voltage.Limit ); + RESET_SENSOR_LIMIT(VOLTAGE, HIGHEST,Pkg->State.Voltage.Limit ); +} + +REASON_CODE Core_Manager(REF *Ref) +{ + RO(SHM_STRUCT) *RO(Shm) = Ref->RO(Shm); + RW(SHM_STRUCT) *RW(Shm) = Ref->RW(Shm); + RO(PROC) *RO(Proc) = Ref->RO(Proc); + RW(PROC) *RW(Proc) = Ref->RW(Proc); + RO(CORE) **RO(Core) = Ref->RO(Core); + struct PKG_FLIP_FLOP *PFlip; + struct FLIP_FLOP *SProc; + SERVICE_PROC localService = RESET_SERVICE; + struct { + double RelFreq, + AbsFreq; + } prevTop; + REASON_INIT (reason); + unsigned int cpu = 0; + + pthread_t tid = pthread_self(); + #ifdef __GLIBC__ + RO(Shm)->App.Svr = tid; + #else + RO(Shm)->App.Svr = getpid(); + #endif + + if (ServerFollowService(&localService, &RO(Shm)->Proc.Service, tid) == 0) { + pthread_setname_np(tid, "corefreqd-pmgr"); + } + ARG *Arg = calloc(RO(Shm)->Proc.CPU.Count, sizeof(ARG)); + if (Arg != NULL) + { + void (*Pkg_ComputeThermalFormula)( struct PKG_FLIP_FLOP*, + struct FLIP_FLOP* ); + + void (*Pkg_ComputeVoltageFormula)( struct PKG_FLIP_FLOP* ); + + void (*Pkg_ComputePowerFormula)( PROC_RW*, struct FLIP_FLOP* ); + + void (*Pkg_ResetPowerFormula)(PROC_RW*); + + switch (KIND_OF_FORMULA(RO(Shm)->Proc.thermalFormula)) { + case THERMAL_KIND_NONE: + default: + Pkg_ComputeThermalFormula = Pkg_ComputeThermal_None; + } + + switch (KIND_OF_FORMULA(RO(Shm)->Proc.voltageFormula)) { + case VOLTAGE_KIND_NONE: + default: + Pkg_ComputeVoltageFormula = Pkg_ComputeVoltage_None; + break; + } + + switch (KIND_OF_FORMULA(RO(Shm)->Proc.powerFormula)) { + case POWER_KIND_NONE: + default: + Pkg_ComputePowerFormula = Pkg_ComputePower_None; + Pkg_ResetPowerFormula = Pkg_ResetPower_None; + break; + } + + #if defined(LEGACY) && LEGACY > 0 + #define ROOM_CLEAR(_room_) \ + BITZERO(BUS_LOCK, _room_##Core[CORE_WORD_TOP(CORE_COUNT)]) + #else + #define ROOM_CLEAR(_room_) \ + BITCMP_CC(BUS_LOCK, _room_##Core, _room_##Clear) + #endif + + #define ROOM_RESET(_room_) \ + BITSTOR_CC(BUS_LOCK, _room_##Core, _room_##Seed) + + #define ROOM_READY(_room_) \ + BITCMP_CC(BUS_LOCK, _room_##Ready, _room_##Seed) + + #define CONDITION_RDTSCP() \ + ( (RO(Proc)->Features.Inv_TSC == 1) \ + || (RO(Proc)->Features.RDTSCP == 1) ) + + #define CONDITION_RDPMC() \ + ( (RO(Proc)->Features.PerfMon.Version >= 1) \ + && (BITVAL(RO(Core, AT(RO(Proc)->Service.Core))->SystemRegister.CR4, \ + CR4_PCE) == 1) ) + + UBENCH_SETUP(CONDITION_RDTSCP(), CONDITION_RDPMC()); + Print_uBenchmark((Quiet & 0x100)); + + while (!BITVAL(Shutdown, SYNC)) + { /* Loop while all the cpu room bits are not cleared. */ + while (!BITVAL(Shutdown, SYNC) && !ROOM_CLEAR(room)) + { + nanosleep(&RO(Shm)->Sleep.pollingWait, NULL); + } + + UBENCH_RDCOUNTER(1); + + RO(Shm)->Proc.Toggle = !RO(Shm)->Proc.Toggle; + PFlip = &RO(Shm)->Proc.FlipFlop[RO(Shm)->Proc.Toggle]; + + SProc = &RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].FlipFlop[ + !RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Toggle + ]; + + PFlip->Thermal.Temp = 0; + /* Reset the averages & the max frequency */ + RO(Shm)->Proc.Avg.Turbo = 0; + RO(Shm)->Proc.Avg.C0 = 0; + RO(Shm)->Proc.Avg.C3 = 0; + RO(Shm)->Proc.Avg.C6 = 0; + RO(Shm)->Proc.Avg.C7 = 0; + RO(Shm)->Proc.Avg.C1 = 0; + + prevTop.RelFreq = 0.0; + prevTop.AbsFreq = 0.0; + + Pkg_ResetPowerFormula(RW(Proc)); + /* Reset with Package Events */ + memcpy( RO(Shm)->ProcessorEvents, PFlip->Thermal.Events, + sizeof(RO(Shm)->ProcessorEvents) ); + + for (cpu=0; !BITVAL(Shutdown, SYNC)&&(cpu < RO(Shm)->Proc.CPU.Count);cpu++) + { + if (BITVAL(RO(Core, AT(cpu))->OffLine, OS) == 1) + { + if (Arg[cpu].TID) + { /* Remove this cpu. */ + if (pthread_join(Arg[cpu].TID, NULL) == 0) + { + BITCLR_CC(BUS_LOCK, roomReady, cpu); + Arg[cpu].TID = 0; + + PerCore_Update(RO(Shm), RO(Proc), RO(Core), cpu); + + if (ServerFollowService( &localService, + &RO(Shm)->Proc.Service, + tid ) == 0) + { + SProc = &RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].FlipFlop[ + !RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Toggle + ]; + } + /* Raise these bits up to notify a platform change. */ + BITWISESET(LOCKLESS, PendingSync, BIT_MASK_NTFY); + } + } + BITSET(LOCKLESS, RO(Shm)->Cpu[cpu].OffLine, OS); + } else { + struct FLIP_FLOP *CFlop = &RO(Shm)->Cpu[cpu].FlipFlop[ + !RO(Shm)->Cpu[cpu].Toggle + ]; + if (!Arg[cpu].TID) + { /* Add this cpu. */ + Arg[cpu].Ref = Ref; + Arg[cpu].Bind = cpu; + if (pthread_create( &Arg[cpu].TID, + NULL, + Core_Cycle, + &Arg[cpu]) == 0) + { + BITSET_CC(BUS_LOCK, roomReady, cpu); + + PerCore_Update(RO(Shm), RO(Proc), RO(Core), cpu); + + if (ServerFollowService(&localService, + &RO(Shm)->Proc.Service, + tid) == 0) + { + SProc = &RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].FlipFlop[ + !RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Toggle + ]; + } + if (Quiet & 0x100) { + printf( " CPU #%03u @ %.2f MHz\n", cpu, + ABS_FREQ_MHz(double , RO(Shm)->Cpu[cpu].Boost[BOOST(MAX)], + RO(Core, AT(cpu))->Clock) ); + } + /* Notify a CPU has been brought up */ + BITWISESET(LOCKLESS, PendingSync, BIT_MASK_NTFY); + } + } + BITCLR(LOCKLESS, RO(Shm)->Cpu[cpu].OffLine, OS); + + /* Index CPU with the highest Rel. and Abs frequencies. */ + if (CFlop->Relative.Freq > prevTop.RelFreq) { + prevTop.RelFreq = CFlop->Relative.Freq; + RO(Shm)->Proc.Top.Rel = cpu; + } + if (CFlop->Absolute.Freq > prevTop.AbsFreq) { + prevTop.AbsFreq = CFlop->Absolute.Freq; + RO(Shm)->Proc.Top.Abs = cpu; + } + + /* Workaround to Package Thermal Management: the hottest Core */ + if (!RO(Shm)->Proc.Features.Power.PTM) { + if (CFlop->Thermal.Temp > PFlip->Thermal.Temp) + PFlip->Thermal.Temp = CFlop->Thermal.Temp; + } + + /* Workaround to RAPL Package counter: sum of all Cores */ + Pkg_ComputePowerFormula(RW(Proc), CFlop); + + /* Sum counters. */ + RO(Shm)->Proc.Avg.Turbo += CFlop->State.Turbo; + RO(Shm)->Proc.Avg.C0 += CFlop->State.C0; + RO(Shm)->Proc.Avg.C3 += CFlop->State.C3; + RO(Shm)->Proc.Avg.C6 += CFlop->State.C6; + RO(Shm)->Proc.Avg.C7 += CFlop->State.C7; + RO(Shm)->Proc.Avg.C1 += CFlop->State.C1; + /* Aggregate all Cores Events. */ + RO(Shm)->ProcessorEvents[eLOG] |= CFlop->Thermal.Events[eLOG]; + RO(Shm)->ProcessorEvents[eSTS] |= CFlop->Thermal.Events[eSTS]; + } + } + if (!BITVAL(Shutdown, SYNC) && ROOM_READY(room)) + { + unsigned char fRESET = 0; + /* Compute the counters averages. */ + RO(Shm)->Proc.Avg.Turbo /= RO(Shm)->Proc.CPU.OnLine; + RO(Shm)->Proc.Avg.C0 /= RO(Shm)->Proc.CPU.OnLine; + RO(Shm)->Proc.Avg.C3 /= RO(Shm)->Proc.CPU.OnLine; + RO(Shm)->Proc.Avg.C6 /= RO(Shm)->Proc.CPU.OnLine; + RO(Shm)->Proc.Avg.C7 /= RO(Shm)->Proc.CPU.OnLine; + RO(Shm)->Proc.Avg.C1 /= RO(Shm)->Proc.CPU.OnLine; + /* Package scope counters */ + PFlip->Delta.PCLK = RO(Proc)->Delta.PCLK; + PFlip->Delta.PC02 = RO(Proc)->Delta.PC02; + PFlip->Delta.PC03 = RO(Proc)->Delta.PC03; + PFlip->Delta.PC04 = RO(Proc)->Delta.PC04; + PFlip->Delta.PC06 = RO(Proc)->Delta.PC06; + PFlip->Delta.PC07 = RO(Proc)->Delta.PC07; + PFlip->Delta.PC08 = RO(Proc)->Delta.PC08; + PFlip->Delta.PC09 = RO(Proc)->Delta.PC09; + PFlip->Delta.PC10 = RO(Proc)->Delta.PC10; + PFlip->Delta.MC6 = RO(Proc)->Delta.MC6; + /* Package C-state Residency counters */ + RO(Shm)->Proc.State.PC02= (double)PFlip->Delta.PC02 + / (double)PFlip->Delta.PCLK; + + RO(Shm)->Proc.State.PC03= (double)PFlip->Delta.PC03 + / (double)PFlip->Delta.PCLK; + + RO(Shm)->Proc.State.PC04= (double)PFlip->Delta.PC04 + / (double)PFlip->Delta.PCLK; + + RO(Shm)->Proc.State.PC06= (double)PFlip->Delta.PC06 + / (double)PFlip->Delta.PCLK; + + RO(Shm)->Proc.State.PC07= (double)PFlip->Delta.PC07 + / (double)PFlip->Delta.PCLK; + + RO(Shm)->Proc.State.PC08= (double)PFlip->Delta.PC08 + / (double)PFlip->Delta.PCLK; + + RO(Shm)->Proc.State.PC09= (double)PFlip->Delta.PC09 + / (double)PFlip->Delta.PCLK; + + RO(Shm)->Proc.State.PC10= (double)PFlip->Delta.PC10 + / (double)PFlip->Delta.PCLK; + + RO(Shm)->Proc.State.MC6 = (double)PFlip->Delta.MC6 + / (double)PFlip->Delta.PCLK; + /* Uncore scope counters */ + PFlip->Uncore.FC0 = RO(Proc)->Delta.Uncore.FC0; + /* Power & Energy counters */ + enum PWR_DOMAIN pw; + for (pw = PWR_DOMAIN(PKG); pw < PWR_DOMAIN(SIZE); pw++) + { + PFlip->Delta.ACCU[pw] = RW(Proc)->Delta.Power.ACCU[pw]; + + RO(Shm)->Proc.State.Energy[pw].Current = PFlip->Delta.ACCU[pw]; + RO(Shm)->Proc.State.Energy[pw].Current *= \ + RO(Shm)->Proc.Power.Unit.Joules; + + RO(Shm)->Proc.State.Power[pw].Current = \ + RO(Shm)->Proc.State.Energy[pw].Current; + + RO(Shm)->Proc.State.Power[pw].Current *= 1000.0; + RO(Shm)->Proc.State.Power[pw].Current /= RO(Shm)->Sleep.Interval; + + /* Processor scope: computes Min and Max energy consumed. */ + TEST_AND_SET_SENSOR( ENERGY, LOWEST, + RO(Shm)->Proc.State.Energy[pw].Current, + RO(Shm)->Proc.State.Energy[pw].Limit ); + + TEST_AND_SET_SENSOR( ENERGY, HIGHEST, + RO(Shm)->Proc.State.Energy[pw].Current, + RO(Shm)->Proc.State.Energy[pw].Limit ); + /* Processor scope: computes Min and Max power consumed. */ + TEST_AND_SET_SENSOR( POWER, LOWEST, + RO(Shm)->Proc.State.Power[pw].Current, + RO(Shm)->Proc.State.Power[pw].Limit ); + + TEST_AND_SET_SENSOR( POWER, HIGHEST, + RO(Shm)->Proc.State.Power[pw].Current, + RO(Shm)->Proc.State.Power[pw].Limit ); + } + /* Package Processor & Plaftorm events */ + memcpy( PFlip->Thermal.Events, RO(Proc)->PowerThermal.Events, + sizeof(PFlip->Thermal.Events) ); + /* Package thermal formulas */ + if (RO(Shm)->Proc.Features.Power.PTM) + { + PFlip->Thermal.Sensor = RO(Proc)->PowerThermal.Sensor; + Pkg_ComputeThermalFormula(PFlip, SProc); + } + /* Package Voltage formulas */ + PFlip->Voltage.VID.CPU = RO(Proc)->PowerThermal.VID.CPU; + PFlip->Voltage.VID.SOC = RO(Proc)->PowerThermal.VID.SOC; + + Pkg_ComputeVoltageFormula(PFlip); + /* Computes the Min Processor voltage. */ + TEST_AND_SET_SENSOR( VOLTAGE, LOWEST, PFlip->Voltage.CPU, + RO(Shm)->Proc.State.Voltage.Limit ); + /* Computes the Max Processor voltage. */ + TEST_AND_SET_SENSOR( VOLTAGE, HIGHEST, PFlip->Voltage.CPU, + RO(Shm)->Proc.State.Voltage.Limit ); + /* + The Driver tick is bound to the Service Core: + 1- Tasks collection; Tasks count; and Memory usage. + 2- Processor has resumed from Suspend To RAM. + */ + RO(Shm)->SysGate.tickStep = RO(Proc)->tickStep; + if (RO(Shm)->SysGate.tickStep == RO(Shm)->SysGate.tickReset) + { + if (BITWISEAND(LOCKLESS, RO(Shm)->SysGate.Operation, 0x1)) + { + if (SysGate_OnDemand(Ref, 1) == 0) { + SysGate_Update(Ref); + } + } + /* OS notifications: such as Resumed from Suspend */ + if ( (fRESET = BITCLR(BUS_LOCK, RW(Proc)->OS.Signal, NTFY )) == 1) + { + BITWISESET(LOCKLESS, PendingSync, BIT_MASK_COMP|BIT_MASK_NTFY); + } + } + if (BITWISEAND(LOCKLESS, PendingSync, BIT_MASK_COMP|BIT_MASK_NTFY)) + { + Package_Update(RO(Shm), RO(Proc), RW(Proc)); + + Uncore_Update(RO(Shm), RO(Proc), RO(Core, AT(RO(Proc)->Service.Core))); + + for (cpu = 0; cpu < Ref->RO(Shm)->Proc.CPU.Count; cpu++) + { + if (fRESET == 1) + { + Core_ResetSensorLimits(&RO(Shm)->Cpu[cpu]); + } + if (BITVAL(RO(Ref->Core, AT(cpu))->OffLine, OS) == 0) + { + PerCore_Update(Ref->RO(Shm), RO(Ref->Proc), RO(Ref->Core), cpu); + } + } + if (fRESET == 1) + { + Pkg_ResetSensorLimits(&RO(Shm)->Proc); + } + Technology_Update(RO(Shm), RO(Proc), RW(Proc)); + + if (ServerFollowService(&localService, + &RO(Shm)->Proc.Service, + tid) == 0) + { + SProc = &RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].FlipFlop[ + !RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Toggle + ]; + } + if (Quiet & 0x100) { + printf("\t%s || %s\n", + BITVAL(PendingSync, NTFY0) ? "NTFY":"....", + BITVAL(PendingSync, COMP0) ? "COMP":"...."); + } + } + /* All aggregations done: Notify Clients. */ + BITWISESET(LOCKLESS, PendingSync, BIT_MASK_SYNC); + BITWISESET(LOCKLESS, RW(Shm)->Proc.Sync, PendingSync); + BITWISECLR(LOCKLESS, PendingSync); + } + /* Reset the Room mask */ + ROOM_RESET(room); + + UBENCH_RDCOUNTER(2); + + UBENCH_COMPUTE(); + Print_uBenchmark((Quiet & 0x100)); + } + #undef CONDITION_RDPMC + #undef CONDITION_RDTSCP + #undef ROOM_RESET + #undef ROOM_READY + #undef ROOM_CLEAR + for (cpu = 0; cpu < RO(Shm)->Proc.CPU.Count; cpu++) { + if (Arg[cpu].TID) { + pthread_join(Arg[cpu].TID, NULL); + } + } + free(Arg); + } else { + REASON_SET(reason, RC_MEM_ERR, (errno == 0 ? ENOMEM : errno)); + } + return reason; +} + +REASON_CODE Child_Manager(REF *Ref) +{ + RO(SHM_STRUCT) *RO(Shm) = Ref->RO(Shm); + SERVICE_PROC localService = RESET_SERVICE; + REASON_INIT(reason); + unsigned int cpu = 0; + + pthread_t tid = pthread_self(); + + if (ServerFollowService(&localService, &RO(Shm)->Proc.Service, tid) == 0) { + pthread_setname_np(tid, "corefreqd-cmgr"); + } + ARG *Arg = calloc(RO(Shm)->Proc.CPU.Count, sizeof(ARG)); + if (Arg != NULL) + { + do { + for(cpu=0; !BITVAL(Shutdown, SYNC) && (cpu < RO(Shm)->Proc.CPU.Count);cpu++) + { + if (BITVAL(RO(Shm)->Cpu[cpu].OffLine, OS) == 1) { + if (Arg[cpu].TID) { + /* Remove this child thread. */ + pthread_join(Arg[cpu].TID, NULL); + Arg[cpu].TID = 0; + } + } else { + unsigned int seed32; + __asm__ volatile + ( + "isb" "\n\t" + "mrs %0, cntvct_el0" + : "=r" (seed32) + : + : + ); + #ifdef __GLIBC__ + initstate_r( seed32, + RO(Shm)->Cpu[cpu].Slice.Random.state, + sizeof(RO(Shm)->Cpu[cpu].Slice.Random.state), + &RO(Shm)->Cpu[cpu].Slice.Random.data ); + #else + initstate(seed32, RO(Shm)->Cpu[cpu].Slice.Random.state, 128); + #endif + if (!Arg[cpu].TID) { + /* Add this child thread. */ + Arg[cpu].Ref = Ref; + Arg[cpu].Bind = cpu; + pthread_create( &Arg[cpu].TID, + NULL, + Child_Thread, + &Arg[cpu]); + } + } + } + ServerFollowService(&localService, &RO(Shm)->Proc.Service, tid); + + nanosleep(&RO(Shm)->Sleep.childWaiting, NULL); + } + while (!BITVAL(Shutdown, SYNC)) ; + + for (cpu = 0; cpu < RO(Shm)->Proc.CPU.Count; cpu++) { + if (Arg[cpu].TID) { + pthread_join(Arg[cpu].TID, NULL); + } + } + free(Arg); + } else { + REASON_SET(reason, RC_MEM_ERR, (errno == 0 ? ENOMEM : errno)); + } + return reason; +} + +REASON_CODE Shm_Manager(FD *fd, RO(PROC) *RO(Proc), RW(PROC) *RW(Proc), + uid_t uid, uid_t gid, mode_t cmask[2]) +{ + unsigned int cpu = 0; + RO(CORE) **RO(Core); + RW(CORE) **RW(Core); + RO(SHM_STRUCT) *RO(Shm) = NULL; + RW(SHM_STRUCT) *RW(Shm) = NULL; + struct { + const size_t RO(Core), + RW(Core); + } Size = { + ROUND_TO_PAGES(sizeof(RO(CORE))), + ROUND_TO_PAGES(sizeof(RW(CORE))) + }; + REASON_INIT(reason); + + if ((RO(Core) = calloc(RO(Proc)->CPU.Count, sizeof(RO(Core)))) == NULL) { + REASON_SET(reason, RC_MEM_ERR, (errno == 0 ? ENOMEM : errno)); + } + if ((RW(Core) = calloc(RO(Proc)->CPU.Count, sizeof(RW(Core)))) == NULL) { + REASON_SET(reason, RC_MEM_ERR, (errno == 0 ? ENOMEM : errno)); + } + for(cpu = 0;(reason.rc == RC_SUCCESS) && (cpu < RO(Proc)->CPU.Count); cpu++) + { + const off_t vm_ro_pgoff = (ID_RO_VMA_CORE + cpu) * PAGE_SIZE, + vm_rw_pgoff = (ID_RW_VMA_CORE + cpu) * PAGE_SIZE; + + if ((RO(Core, AT(cpu)) = mmap(NULL, Size.RO(Core), + PROT_READ, + MAP_SHARED, + fd->drv, vm_ro_pgoff)) == MAP_FAILED) + { + REASON_SET(reason, RC_SHM_MMAP); + } + if ((RW(Core, AT(cpu)) = mmap(NULL, Size.RW(Core), + PROT_READ|PROT_WRITE, + MAP_SHARED, + fd->drv, vm_rw_pgoff)) == MAP_FAILED) + { + REASON_SET(reason, RC_SHM_MMAP); + } + } + if (reason.rc == RC_SUCCESS) { + if (gid != 0) { + if (setregid((gid_t) -1, gid) != 0) { + REASON_SET(reason, RC_SYS_CALL); + } + } + } + if (reason.rc == RC_SUCCESS) { + if (uid != 0) { + if (setreuid((uid_t) -1, uid) != 0) { + REASON_SET(reason, RC_SYS_CALL); + } + } + } + if (reason.rc == RC_SUCCESS) + { /* Initialize shared memory. */ + const size_t shmCpuSize = sizeof(CPU_STRUCT) * RO(Proc)->CPU.Count, + roSize = ROUND_TO_PAGES((sizeof(RO(SHM_STRUCT)) + + shmCpuSize)), + rwSize = ROUND_TO_PAGES(sizeof(RW(SHM_STRUCT))); + + if ( ((fd->ro = shm_open(RO(SHM_FILENAME), O_CREAT|O_TRUNC|O_RDWR, + S_IRUSR|S_IWUSR + |S_IRGRP|S_IWGRP + |S_IROTH|S_IWOTH)) != -1) + && ((fd->rw = shm_open(RW(SHM_FILENAME), O_CREAT|O_TRUNC|O_RDWR, + S_IRUSR|S_IWUSR + |S_IRGRP|S_IWGRP + |S_IROTH|S_IWOTH)) != -1) ) + { + pid_t CPID = -1; + + if ( (ftruncate(fd->ro, (off_t) roSize) != -1) + && (ftruncate(fd->rw, (off_t) rwSize) != -1) ) + { + fchmod(fd->ro, cmask[0]); + fchmod(fd->rw, cmask[1]); + + if ( ( ( RO(Shm) = mmap(NULL, roSize, + PROT_READ|PROT_WRITE, MAP_SHARED, + fd->ro, 0) ) != MAP_FAILED ) + && ( ( RW(Shm) = mmap(NULL, rwSize, + PROT_READ|PROT_WRITE, MAP_SHARED, + fd->rw, 0) ) != MAP_FAILED ) ) + { + __typeof__ (errno) fork_err = 0; + /* Clear SHM */ + memset(RO(Shm), 0, roSize); + memset(RW(Shm), 0, rwSize); + /* Store version footprint into SHM */ + SET_FOOTPRINT(RO(Shm)->FootPrint,MAX_FREQ_HZ, + CORE_COUNT, + TASK_ORDER, + COREFREQ_MAJOR, + COREFREQ_MINOR, + COREFREQ_REV ); + /* Reference time the Server is starting at. */ + time(&RO(Shm)->StartedAt); + /* Store the daemon gate name. */ + StrCopy(RO(Shm)->ShmName, RO(SHM_FILENAME), TASK_COMM_LEN); + /* Initialize the busy wait times. */ + RO(Shm)->Sleep.ringWaiting = TIMESPEC(SIG_RING_MS); + RO(Shm)->Sleep.childWaiting = TIMESPEC(CHILD_PS_MS); + RO(Shm)->Sleep.sliceWaiting = TIMESPEC(CHILD_TH_MS); + + REF Ref = { + .CPID = -1, + .KID = 0, + .Started = 0, + .Slice.Func = NULL, + .Slice.arg = 0, + .fd = fd, + .RO(Shm) = RO(Shm), + .RW(Shm) = RW(Shm), + .RO(Proc) = RO(Proc), + .RW(Proc) = RW(Proc), + .RO(Core) = RO(Core), + .RW(Core) = RW(Core), + .RO(SysGate) = NULL + }; + sigemptyset(&Ref.Signal); + + Package_Update(RO(Shm), RO(Proc), RW(Proc)); + + memcpy(&RO(Shm)->SMB, &RO(Proc)->SMB, sizeof(SMBIOS_ST)); + + /* Clear notification. */ + BITWISECLR(LOCKLESS, RW(Shm)->Proc.Sync); + + SysGate_Toggle(&Ref, SysGateStartUp); + + /* Welcomes with brand and per CPU base clock. */ + if (Quiet & 0x001) { + printf( "CoreFreq Daemon %s" \ + " Copyright (C) 2015-2024 CYRIL COURTIAT\n", + COREFREQ_VERSION ); + } + if (Quiet & 0x010) { + printf( "\n" \ + " Processor [%s]\n" \ + " Architecture [%s] %u/%u CPU Online.\n", + RO(Shm)->Proc.Brand, + RO(Shm)->Proc.Architecture, + RO(Shm)->Proc.CPU.OnLine, + RO(Shm)->Proc.CPU.Count ); + } + if (Quiet & 0x100) { + printf( " SleepInterval(%u), SysGate(%u), %ld tasks\n\n", + RO(Shm)->Sleep.Interval, + !BITVAL(RO(Shm)->SysGate.Operation, 0) ? + 0:RO(Shm)->Sleep.Interval * RO(Shm)->SysGate.tickReset, + TASK_LIMIT ); + } + if (Quiet) { + fflush(stdout); + } + CPID = Ref.CPID = fork(); + /*-----[ Resources inherited ]----------------------------------*/ + fork_err = errno; + + Emergency_Command(&Ref, 1); + + switch (Ref.CPID) { + case 0: + reason = Child_Manager(&Ref); + break; + case -1: + REASON_SET(reason, RC_EXEC_ERR, fork_err); + break; + default: + reason = Core_Manager(&Ref); + + if (gid != 0) { + if (setregid((gid_t) -1, 0) != 0) { + REASON_SET(reason, RC_SYS_CALL); + } + } + if (uid != 0) { + if (setreuid((uid_t) -1, 0) != 0) { + REASON_SET(reason, RC_SYS_CALL); + } + } + if (RO(Shm)->App.Cli) { + if (kill(RO(Shm)->App.Cli, SIGTERM) == -1) { + if (errno != ESRCH) + REASON_SET(reason, RC_EXEC_ERR); + } + } + if (RO(Shm)->App.GUI) { + if (kill(RO(Shm)->App.GUI, SIGTERM) == -1) { + if (errno != ESRCH) + REASON_SET(reason, RC_EXEC_ERR); + } + } + SysGate_OnDemand(&Ref, 0); + + if (kill(Ref.CPID, SIGQUIT) == 0) { + if (waitpid(Ref.CPID, NULL, 0) == -1) { + REASON_SET(reason, RC_EXEC_ERR); + } + } else { + REASON_SET(reason, RC_EXEC_ERR); + } + break; + } + Emergency_Command(&Ref, 0); + + if (munmap(RO(Shm), roSize) == -1) { + REASON_SET(reason, RC_SHM_MMAP); + } + if (munmap(RW(Shm), rwSize) == -1) { + REASON_SET(reason, RC_SHM_MMAP); + } + } else { + REASON_SET(reason, RC_SHM_MMAP); + } + } else { + REASON_SET(reason, RC_SHM_FILE); + } + if (close(fd->ro) == -1) { + REASON_SET(reason, RC_SHM_FILE); + } + if (close(fd->rw) == -1) { + REASON_SET(reason, RC_SHM_FILE); + } + if (CPID != 0) { + if (shm_unlink(RO(SHM_FILENAME)) == -1) { + REASON_SET(reason, RC_SHM_FILE); + } + if (shm_unlink(RW(SHM_FILENAME)) == -1) { + REASON_SET(reason, RC_SHM_FILE); + } + } + } else { + REASON_SET(reason, RC_SHM_FILE); + } + } + for (cpu = 0; cpu < RO(Proc)->CPU.Count; cpu++) + { + if (RO(Core, AT(cpu)) != NULL) { + if (munmap(RO(Core, AT(cpu)), Size.RO(Core)) == -1) { + REASON_SET(reason, RC_SHM_MMAP); + } + } + if (RW(Core, AT(cpu)) != NULL) { + if (munmap(RW(Core, AT(cpu)), Size.RW(Core)) == -1) { + REASON_SET(reason, RC_SHM_MMAP); + } + } + } + if (RO(Core) != NULL) { + free(RO(Core)); + } + if (RW(Core) != NULL) { + free(RW(Core)); + } + return reason; +} + +REASON_CODE Help(REASON_CODE reason, ...) +{ + va_list ap; + va_start(ap, reason); + switch (reason.rc) { + case RC_SUCCESS: + case RC_OK_SYSGATE: + case RC_OK_COMPUTE: + case RC_DRIVER_BASE ... RC_DRIVER_LAST: + break; + case RC_CMD_SYNTAX: { + char *appName = va_arg(ap, char *); + printf( "Usage:\t%s [-option ]\n" \ + "\t-q\t\tQuiet\n" \ + "\t-i\t\tInfo\n" \ + "\t-d\t\tDebug\n" \ + "\t-gon\t\tEnable SysGate\n" \ + "\t-goff\t\tDisable SysGate\n" \ + "\t-U \tSet the effective user ID\n" \ + "\t-G \tSet the effective group ID\n" \ + "\t-M ,\tShared Memories permission\n"\ + "\t-h\t\tPrint out this message\n" \ + "\t-v\t\tPrint the version number\n" \ + "\nExit status:\n" \ + "\t%u\tSUCCESS\t\tSuccessful execution\n" \ + "\t%u\tCMD_SYNTAX\tCommand syntax error\n" \ + "\t%u\tSHM_FILE\tShared memory file error\n" \ + "\t%u\tSHM_MMAP\tShared memory mapping error\n" \ + "\t%u\tPERM_ERR\tExecution not permitted\n" \ + "\t%u\tMEM_ERR\t\tMemory operation error\n" \ + "\t%u\tEXEC_ERR\tGeneral execution error\n" \ + "\t%u\tSYS_CALL\tSystem call error\n" \ + "\nReport bugs to labs[at]cyring.fr\n", appName, + RC_SUCCESS, + RC_CMD_SYNTAX, + RC_SHM_FILE, + RC_SHM_MMAP, + RC_PERM_ERR, + RC_MEM_ERR, + RC_EXEC_ERR, + RC_SYS_CALL); + } + break; + case RC_PERM_ERR: + case RC_MEM_ERR: + case RC_EXEC_ERR: { + char *appName = va_arg(ap, char *); + char *sysMsg = strerror(reason.no); + fprintf(stderr, "%s execution error code %d\n%s @ line %d\n", + appName, reason.no, sysMsg, reason.ln); + } + break; + case RC_SHM_FILE: + case RC_SHM_MMAP: { + char *shmFileName = va_arg(ap, char *); + char *sysMsg = strerror(reason.no); + fprintf(stderr , "Driver connection error code %d\n" \ + "%s: '%s' @ line %d\n", + reason.no, shmFileName, sysMsg, reason.ln); + } + break; + case RC_SYS_CALL: { + char *sysMsg = strerror(reason.no); + fprintf(stderr, "System error code %d\n%s @ line %d\n", + reason.no, sysMsg, reason.ln); + } + break; + } + va_end(ap); + return reason; +} + +int main(int argc, char *argv[]) +{ + FD fd = {0, 0, 0}; + RO(PROC) *RO(Proc) = NULL; /* Kernel module anchor points. */ + RW(PROC) *RW(Proc) = NULL; + uid_t uid = 0, gid = 0; + mode_t cmask[2] = { + S_IRUSR|S_IRGRP|S_IROTH, + S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH|S_IWOTH + }; + char *program = strdup(argv[0]), + *appName = program != NULL ? basename(program) : argv[0]; + + REASON_INIT(reason); + int i; + for (i = 1; i < argc; i++) + { + if (strlen(argv[i]) > 1) { + if (argv[i][0] == '-') + { + char option = argv[i][1]; + switch (option) { + case 'q': + Quiet = 0x000; + break; + case 'i': + Quiet = 0x011; + break; + case 'd': + Quiet = 0x111; + break; + case 'g': + if (argv[i][2]=='o' + && argv[i][3]=='f' + && argv[i][4]=='f') { + SysGateStartUp = 0; + } else if ( argv[i][2]=='o' + && argv[i][3]=='n') { + SysGateStartUp = 1; + } else { + REASON_SET(reason, RC_CMD_SYNTAX, 0); + reason = Help(reason, appName); + } + break; + case 'v': + printf("%s\n", COREFREQ_VERSION); + reason.rc = RC_CMD_SYNTAX; + break; + case 'U': { + char trailing = '\0'; + if (argv[++i] == NULL) { + REASON_SET(reason, RC_CMD_SYNTAX, 0); + reason = Help(reason, appName); + } else if (sscanf(argv[i], "%d%c", + &uid, + &trailing) != 1) { + REASON_SET(reason, RC_CMD_SYNTAX); + reason = Help(reason, appName); + } + } + break; + case 'G': { + char trailing = '\0'; + if (argv[++i] == NULL) { + REASON_SET(reason, RC_CMD_SYNTAX, 0); + reason = Help(reason, appName); + } else if (sscanf(argv[i], "%d%c", + &gid, + &trailing) != 1) { + REASON_SET(reason, RC_CMD_SYNTAX); + reason = Help(reason, appName); + } + } + break; + case 'M': { + char trailing = '\0'; + if (argv[++i] == NULL) { + REASON_SET(reason, RC_CMD_SYNTAX, 0); + reason = Help(reason, appName); + } else if (sscanf(argv[i] , "%o,%o%c", + &cmask[0], + &cmask[1], + &trailing) > 2) { + REASON_SET(reason, RC_CMD_SYNTAX); + reason = Help(reason, appName); + } + } + break; + case 'h': + default: { + REASON_SET(reason, RC_CMD_SYNTAX, 0); + reason = Help(reason, appName); + } + break; + } + } else { + REASON_SET(reason, RC_CMD_SYNTAX, 0); + reason = Help(reason, appName); + } + } else { + REASON_SET(reason, RC_CMD_SYNTAX, 0); + reason = Help(reason, appName); + } + } + if (reason.rc == RC_SUCCESS) + { + if (geteuid() == 0) + { + if ((fd.drv = open(DRV_FILENAME, O_RDWR|O_SYNC)) != -1) + { + const size_t packageSize[] = { + ROUND_TO_PAGES(sizeof(RO(PROC))), + ROUND_TO_PAGES(sizeof(RW(PROC))) + }; + const off_t vm_pgoff[] = { + ID_RO_VMA_PROC * PAGE_SIZE, + ID_RW_VMA_PROC * PAGE_SIZE + }; + if ((RO(Proc) = mmap(NULL, packageSize[0], + PROT_READ, MAP_SHARED, + fd.drv, vm_pgoff[0])) != MAP_FAILED) + { + if ((RW(Proc) = mmap(NULL, packageSize[1], + PROT_READ|PROT_WRITE, MAP_SHARED, + fd.drv, vm_pgoff[1])) != MAP_FAILED) + { + if (CHK_FOOTPRINT(RO(Proc)->FootPrint,MAX_FREQ_HZ, + CORE_COUNT, + TASK_ORDER, + COREFREQ_MAJOR, + COREFREQ_MINOR, + COREFREQ_REV)) + { + reason = Shm_Manager( &fd, RO(Proc), RW(Proc), + uid, gid, cmask ); + + switch (reason.rc) { + case RC_SUCCESS: + case RC_OK_SYSGATE: + case RC_OK_COMPUTE: + case RC_DRIVER_BASE ... RC_DRIVER_LAST: + break; + case RC_CMD_SYNTAX: + case RC_PERM_ERR: + break; + case RC_SHM_FILE: + case RC_SHM_MMAP: + reason = Help(reason, RO(SHM_FILENAME)); + break; + case RC_MEM_ERR: + case RC_EXEC_ERR: + reason = Help(reason, appName); + break; + case RC_SYS_CALL: + reason = Help(reason); + break; + } + } else { + char *wrongVersion = malloc(10+5+5+5+1); + REASON_SET(reason, RC_SHM_MMAP, EACCES); + if (wrongVersion != NULL) { + snprintf(wrongVersion, 10+5+5+5+1, + "Version %hu.%hu.%hu", + RO(Proc)->FootPrint.major, + RO(Proc)->FootPrint.minor, + RO(Proc)->FootPrint.rev); + reason = Help(reason, wrongVersion); + free(wrongVersion); + } + } + if (munmap(RW(Proc), packageSize[1]) == -1) { + REASON_SET(reason, RC_SHM_MMAP); + reason = Help(reason, DRV_FILENAME); + } + } + if (munmap(RO(Proc), packageSize[0]) == -1) { + REASON_SET(reason, RC_SHM_MMAP); + reason = Help(reason, DRV_FILENAME); + } + } else { + REASON_SET(reason, RC_SHM_MMAP); + reason = Help(reason, DRV_FILENAME); + } + if (close(fd.drv) == -1) { + REASON_SET(reason, RC_SHM_FILE); + reason = Help(reason, DRV_FILENAME); + } + } else { + REASON_SET(reason, RC_SHM_FILE); + reason = Help(reason, DRV_FILENAME); + } + } else { + REASON_SET(reason, RC_PERM_ERR, EACCES); + reason = Help(reason, appName); + } + } + if (program != NULL) { + free(program); + } + return reason.rc; +} diff --git a/aarch64/corefreqk.c b/aarch64/corefreqk.c new file mode 100644 index 00000000..e1d006b7 --- /dev/null +++ b/aarch64/corefreqk.c @@ -0,0 +1,6153 @@ +/* + * CoreFreq + * Copyright (C) 2015-2024 CYRIL COURTIAT + * Licenses: GPL2 + */ + +#include +#include +#include +#include +#ifdef CONFIG_DMI +#include +#endif /* CONFIG_DMI */ +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_CPU_IDLE +#include +#endif /* CONFIG_CPU_IDLE */ +#ifdef CONFIG_CPU_FREQ +#include +#endif /* CONFIG_CPU_FREQ */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0) +#include +#endif /* KERNEL_VERSION(4, 11, 0) */ +#include +#ifdef CONFIG_XEN +#include +#endif /* CONFIG_XEN */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 17, 0) +#include +#endif +#ifdef CONFIG_ACPI +#include +#include +#endif +#ifdef CONFIG_ACPI_CPPC_LIB +#include +#endif + +#ifdef CONFIG_HAVE_NMI +enum { + NMI_LOCAL=0, + NMI_UNKNOWN, + NMI_SERR, + NMI_IO_CHECK, + NMI_MAX +}; +#define NMI_DONE 0 +#define NMI_HANDLED 1 + +#define register_nmi_handler(t, fn, fg, n, init...) \ +({ \ + UNUSED(fn); \ + 0; \ +}) +#define unregister_nmi_handler(type, name) ({}) +#endif /* CONFIG_HAVE_NMI */ + +#include "bitasm.h" +#include "arm_reg.h" +#include "coretypes.h" +#include "corefreq-api.h" +#include "corefreqk.h" + +MODULE_AUTHOR ("CYRIL COURTIAT "); +MODULE_DESCRIPTION ("CoreFreq Processor Driver"); +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 12, 0) +MODULE_SUPPORTED_DEVICE ("ARM"); +#endif +MODULE_LICENSE ("GPL"); +MODULE_VERSION (COREFREQ_VERSION); + +static signed int ArchID = -1; +module_param(ArchID, int, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(ArchID, "Force an architecture (ID)"); + +static signed int AutoClock = 0b11; +module_param(AutoClock, int, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(AutoClock, "Estimate Clock Frequency 0:Spec; 1:Once; 2:Auto"); + +static unsigned int SleepInterval = 0; +module_param(SleepInterval, uint, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(SleepInterval, "Timer interval (ms)"); + +static unsigned int TickInterval = 0; +module_param(TickInterval, uint, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(TickInterval, "System requested interval (ms)"); + +static signed int Experimental = 0; +module_param(Experimental, int, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(Experimental, "Enable features under development"); + +static signed int CPU_Count = -1; +module_param(CPU_Count, int, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(CPU_Count, "-1:Kernel(default); 0:Hardware; >0: User value"); + +static signed short Target_Ratio_Unlock = -1; +module_param(Target_Ratio_Unlock, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(Target_Ratio_Unlock, "1:Target Ratio Unlock; 0:Lock"); + +static signed short Clock_Ratio_Unlock = -1; +module_param(Clock_Ratio_Unlock, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(Clock_Ratio_Unlock, "1:MinRatio; 2:MaxRatio; 3:Both Unlock"); + +static signed short Turbo_Ratio_Unlock = -1; +module_param(Turbo_Ratio_Unlock, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(Turbo_Ratio_Unlock, "1:Turbo Ratio Unlock; 0:Lock"); + +static signed short Uncore_Ratio_Unlock = -1; +module_param(Uncore_Ratio_Unlock, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(Uncore_Ratio_Unlock, "1:Uncore Ratio Unlock; 0:Lock"); + +static signed int ServiceProcessor = -1; /* -1=ANY ; 0=BSP */ +module_param(ServiceProcessor, int, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(ServiceProcessor, "Select a CPU to run services with"); + +static SERVICE_PROC DefaultSMT = RESET_SERVICE; + +static unsigned short NMI_Disable = 1; +module_param(NMI_Disable, ushort, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(NMI_Disable, "Disable the NMI Handler"); + +static enum RATIO_BOOST Ratio_Boost_Count = 0; +static signed int Ratio_Boost[BOOST(SIZE) - BOOST(18C)] = { + /* 18C */ -1, + /* 17C */ -1, + /* 16C */ -1, + /* 15C */ -1, + /* 14C */ -1, + /* 13C */ -1, + /* 12C */ -1, + /* 11C */ -1, + /* 10C */ -1, + /* 9C */ -1, + /* 8C */ -1, + /* 7C */ -1, + /* 6C */ -1, + /* 5C */ -1, + /* 4C */ -1, + /* 3C */ -1, + /* 2C */ -1, + /* 1C */ -1 +}; +module_param_array(Ratio_Boost, int, &Ratio_Boost_Count, \ + S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(Ratio_Boost, "Turbo Boost Frequency ratios"); + +static signed int Ratio_PPC = -1; +module_param(Ratio_PPC, int, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(Ratio_PPC, "Target Performance ratio"); + +static signed short HWP_Enable = -1; +module_param(HWP_Enable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(HWP_Enable, "Hardware-Controlled Performance States"); + +static signed short HWP_EPP = -1; +module_param(HWP_EPP, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(HWP_EPP, "Energy Performance Preference"); + +static enum RATIO_BOOST Ratio_HWP_Count = 0; +static signed int Ratio_HWP[1 + (BOOST(HWP_TGT) - BOOST(HWP_MIN))] = { + /* HWP_MIN */ -1, + /* HWP_MAX */ -1, + /* HWP_TGT */ -1 +}; +module_param_array(Ratio_HWP, int, &Ratio_HWP_Count, \ + S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(Ratio_HWP, "Hardware-Controlled Performance ratios"); + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 17, 0) +static unsigned long Clear_Events = 0; +module_param(Clear_Events, ulong, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +#else +static unsigned long long Clear_Events = 0; +module_param(Clear_Events, ullong, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +#endif +MODULE_PARM_DESC(Clear_Events, "Clear Thermal and Power Events"); + +static int ThermalScope = -1; +module_param(ThermalScope, int, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(ThermalScope, "[0:None; 1:SMT; 2:Core; 3:Package]"); + +static int VoltageScope = -1; +module_param(VoltageScope, int, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(VoltageScope, "[0:None; 1:SMT; 2:Core; 3:Package]"); + +static int PowerScope = -1; +module_param(PowerScope, int, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(PowerScope, "[0:None; 1:SMT; 2:Core; 3:Package]"); + +static signed short Register_CPU_Idle = -1; +module_param(Register_CPU_Idle, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(Register_CPU_Idle, "Register the Kernel cpuidle driver"); + +static signed short Register_CPU_Freq = -1; +module_param(Register_CPU_Freq, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(Register_CPU_Freq, "Register the Kernel cpufreq driver"); + +static signed short Register_Governor = -1; +module_param(Register_Governor, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(Register_Governor, "Register the Kernel governor"); + +static signed short Register_ClockSource = -1; +module_param(Register_ClockSource, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(Register_ClockSource, "Register Clock Source driver"); + +static signed short Idle_Route = -1; +module_param(Idle_Route, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(Idle_Route, "[0:Default; 1:I/O; 2:HALT; 3:MWAIT]"); + +static struct { + signed int Major; + struct cdev *kcdev; + dev_t nmdev, mkdev; + struct class *clsdev; +#ifdef CONFIG_CPU_IDLE + struct cpuidle_device __percpu *IdleDevice; + struct cpuidle_driver IdleDriver; +#endif /* CONFIG_CPU_IDLE */ +#ifdef CONFIG_CPU_FREQ + struct cpufreq_driver FreqDriver; + struct cpufreq_governor FreqGovernor; +#endif /* CONFIG_CPU_FREQ */ +#ifdef CONFIG_PM_SLEEP + bool ResumeFromSuspend; +#endif /* CONFIG_PM_SLEEP */ + unsigned int SubCstate[SUB_CSTATE_COUNT]; +} CoreFreqK = { +#ifdef CONFIG_CPU_IDLE + .IdleDriver = { + .name = "corefreqk-idle", + .owner = THIS_MODULE + }, +#endif /* CONFIG_CPU_IDLE */ +#ifdef CONFIG_CPU_FREQ + .FreqDriver = { + .name = "corefreqk-perf", + .flags = CPUFREQ_CONST_LOOPS, + .exit = CoreFreqK_Policy_Exit, + /*MANDATORY*/ .init = CoreFreqK_Policy_Init, + /*MANDATORY*/ .verify = CoreFreqK_Policy_Verify, + /*MANDATORY*/ .setpolicy = CoreFreqK_SetPolicy, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0) + .bios_limit= CoreFreqK_Bios_Limit, +#else + .bios_limit= CoreFreqK_Bios_Limit +#endif + }, + .FreqGovernor = { + .name = "corefreq-policy", + .owner = THIS_MODULE, + .show_setspeed = CoreFreqK_Show_SetSpeed, + .store_setspeed = CoreFreqK_Store_SetSpeed + }, +#endif /* CONFIG_CPU_FREQ */ +#ifdef CONFIG_PM_SLEEP + .ResumeFromSuspend = false, +#endif /* CONFIG_PM_SLEEP */ +}; + +static KPUBLIC *KPublic = NULL; +static KPRIVATE *KPrivate = NULL; +static ktime_t RearmTheTimer; + +#define AT( _loc_ ) [ _loc_ ] +#define OF( _ptr_ , ...) -> _ptr_ __VA_ARGS__ +#define RO( _ptr_ , ...) OF( _ptr_##_RO , __VA_ARGS__ ) +#define RW( _ptr_ , ...) OF( _ptr_##_RW , __VA_ARGS__ ) +#define ADDR( _head_ , _mbr_ ) ( _head_ _mbr_ ) +#define PUBLIC(...) ADDR( KPublic , __VA_ARGS__ ) +#define PRIVATE(...) ADDR( KPrivate, __VA_ARGS__ ) + +#define RESET_ARRAY(_array, _cnt, _val, ... ) \ +({ \ + unsigned int rst; \ + for (rst = 0; rst < _cnt; rst++) { \ + _array[rst] __VA_ARGS__ = _val; \ + } \ +}) + +static long CoreFreqK_Thermal_Scope(int scope) +{ + if ((scope >= FORMULA_SCOPE_NONE) && (scope <= FORMULA_SCOPE_PKG)) + { + PUBLIC(RO(Proc))->thermalFormula = \ + (KIND_OF_FORMULA(PUBLIC(RO(Proc))->thermalFormula) << 8)|scope; + + return RC_SUCCESS; + } else { + return -EINVAL; + } +} + +static long CoreFreqK_Voltage_Scope(int scope) +{ + if ((scope >= FORMULA_SCOPE_NONE) && (scope <= FORMULA_SCOPE_PKG)) + { + PUBLIC(RO(Proc))->voltageFormula = \ + (KIND_OF_FORMULA(PUBLIC(RO(Proc))->voltageFormula) << 8)|scope; + + return RC_SUCCESS; + } else { + return -EINVAL; + } +} + +static long CoreFreqK_Power_Scope(int scope) +{ + if ((scope >= FORMULA_SCOPE_NONE) && (scope <= FORMULA_SCOPE_PKG)) + { + PUBLIC(RO(Proc))->powerFormula = \ + (KIND_OF_FORMULA(PUBLIC(RO(Proc))->powerFormula) << 8)|scope; + + return RC_SUCCESS; + } else { + return -EINVAL; + } +} + +static unsigned int FixMissingRatioAndFrequency(unsigned int r32, CLOCK *pClock) +{ + unsigned long long r64 = r32; + if (PUBLIC(RO(Proc))->Features.Factory.Freq != 0) + { + if ((r32 == 0) && (pClock->Q > 0)) + { /* Fix missing ratio. */ + r64=DIV_ROUND_CLOSEST(PUBLIC(RO(Proc))->Features.Factory.Freq, pClock->Q); + PUBLIC(RO(Core,AT(PUBLIC(RO(Proc))->Service.Core)))->Boost[BOOST(MAX)]=\ + (unsigned int) r64; + } + } + else if (r32 > 0) + { /* Fix the Factory frequency (unit: MHz) */ + r64 = pClock->Hz * r32; + r64 = r64 / 1000000LLU; + PUBLIC(RO(Proc))->Features.Factory.Freq = (unsigned int) r64; + } + PUBLIC(RO(Proc))->Features.Factory.Clock.Q = pClock->Q; + PUBLIC(RO(Proc))->Features.Factory.Clock.R = pClock->R; + PUBLIC(RO(Proc))->Features.Factory.Clock.Hz = pClock->Hz; + + if (PUBLIC(RO(Proc))->Features.Factory.Clock.Hz > 0) + { + r64 = PUBLIC(RO(Proc))->Features.Factory.Freq * 1000000LLU; + r64 = DIV_ROUND_CLOSEST(r64, PUBLIC(RO(Proc))->Features.Factory.Clock.Hz); + PUBLIC(RO(Proc))->Features.Factory.Ratio = (unsigned int) r64; + } + return (unsigned int) r64; +} + +static unsigned long long CoreFreqK_Read_CS_From_TSC(struct clocksource *cs) +{ + unsigned long long TSC __attribute__ ((aligned (8))); + UNUSED(cs); + RDTSC64(TSC); + SERIALIZE(); + return TSC; +} + +static struct clocksource CoreFreqK_CS = { + .name = "corefreq_tsc", + .rating = 300, + .mask = CLOCKSOURCE_MASK(64), + .flags = CLOCK_SOURCE_IS_CONTINUOUS + | CLOCK_SOURCE_VALID_FOR_HRES, +}; + +static long CoreFreqK_UnRegister_ClockSource(void) +{ + long rc = -EINVAL; + if (PUBLIC(RO(Proc))->Registration.Driver.CS & REGISTRATION_ENABLE) + { + int rx = clocksource_unregister(&CoreFreqK_CS); + switch ( rx ) { + case 0: + PUBLIC(RO(Proc))->Registration.Driver.CS = REGISTRATION_DISABLE; + rc = RC_SUCCESS; + break; + default: + rc = (long) rx; + break; + } + } + return rc; +} + +static long CoreFreqK_Register_ClockSource(unsigned int cpu) +{ + long rc = -EINVAL; + if (Register_ClockSource == 1) + { + unsigned long long Freq_Hz; + unsigned int Freq_KHz; + + CoreFreqK_CS.read = CoreFreqK_Read_CS_From_TSC; + + Freq_Hz = PUBLIC(RO(Core, AT(cpu)))->Boost[BOOST(MAX)] + * PUBLIC(RO(Core, AT(cpu)))->Clock.Hz; + Freq_KHz = Freq_Hz / 1000U; + if (Freq_KHz != 0) + { + int rx = clocksource_register_khz(&CoreFreqK_CS, Freq_KHz); + switch (rx) { + default: + fallthrough; + case -EBUSY: + PUBLIC(RO(Proc))->Registration.Driver.CS = REGISTRATION_DISABLE; + rc = (long) rx; + break; + case 0: + PUBLIC(RO(Proc))->Registration.Driver.CS = REGISTRATION_ENABLE; + rc = RC_SUCCESS; + break; + } + } + } else { + PUBLIC(RO(Proc))->Registration.Driver.CS = REGISTRATION_DISABLE; + } + return rc; +} + +static void VendorFromMainID( MIDR midr, char *pVendorID, unsigned int *pCRC, + enum HYPERVISOR *pHypervisor ) +{ +static const struct { + unsigned short implementer; + char *vendorID; + size_t vendorLen; + enum CRC_MANUFACTURER mfrCRC; + enum HYPERVISOR hypervisor; + } mfrTbl[] = { + { 0x00, VENDOR_RESERVED, __builtin_strlen(VENDOR_RESERVED), + CRC_RESERVED, BARE_METAL }, + { 0x41, VENDOR_ARM, __builtin_strlen(VENDOR_ARM), + CRC_ARM, BARE_METAL }, + { 0x42, VENDOR_BROADCOM, __builtin_strlen(VENDOR_BROADCOM), + CRC_BROADCOM, BARE_METAL }, + { 0x43, VENDOR_CAVIUM, __builtin_strlen(VENDOR_CAVIUM), + CRC_CAVIUM, BARE_METAL }, + { 0x44, VENDOR_DEC, __builtin_strlen(VENDOR_DEC), + CRC_DEC, BARE_METAL }, + { 0x46, VENDOR_FUJITSU, __builtin_strlen(VENDOR_FUJITSU), + CRC_FUJITSU, BARE_METAL }, + { 0x49, VENDOR_INFINEON, __builtin_strlen(VENDOR_INFINEON), + CRC_INFINEON, BARE_METAL }, + { 0x4d, VENDOR_MOTOROLA, __builtin_strlen(VENDOR_MOTOROLA), + CRC_MOTOROLA, BARE_METAL }, + { 0x4e, VENDOR_NVIDIA, __builtin_strlen(VENDOR_NVIDIA), + CRC_NVIDIA, BARE_METAL }, + { 0x50, VENDOR_APM, __builtin_strlen(VENDOR_APM), + CRC_APM, BARE_METAL }, + { 0x51, VENDOR_QUALCOMM, __builtin_strlen(VENDOR_QUALCOMM), + CRC_QUALCOMM, BARE_METAL }, + { 0x56, VENDOR_MARVELL, __builtin_strlen(VENDOR_MARVELL), + CRC_MARVELL, BARE_METAL }, + { 0x69, VENDOR_INTEL, __builtin_strlen(VENDOR_INTEL), + CRC_INTEL, BARE_METAL }, + { 0xc0, VENDOR_AMPERE, __builtin_strlen(VENDOR_AMPERE), + CRC_AMPERE, BARE_METAL }, + + { 0xff, VENDOR_HYPERV, __builtin_strlen(VENDOR_HYPERV), + CRC_HYPERV, HYPERV_HYPERV } + }; + unsigned int idx; + for (idx = 0; idx < sizeof(mfrTbl) / sizeof(mfrTbl[0]); idx++) { + if (midr.Implementer == mfrTbl[idx].implementer) + { + memcpy(pVendorID, mfrTbl[idx].vendorID, mfrTbl[idx].vendorLen); + (*pCRC) = mfrTbl[idx].mfrCRC; + (*pHypervisor) = mfrTbl[idx].hypervisor; + + return; + } + } +} + +static signed int SearchArchitectureID(void) +{ + signed int id; + for (id = ARCHITECTURES - 1; id > 0; id--) + { /* Search for an architecture signature. */ + if ( (PUBLIC(RO(Proc))->Features.Info.Signature.ExtFamily \ + == Arch[id].Signature.ExtFamily) + && (PUBLIC(RO(Proc))->Features.Info.Signature.Family \ + == Arch[id].Signature.Family) + && ( ( (PUBLIC(RO(Proc))->Features.Info.Signature.ExtModel \ + == Arch[id].Signature.ExtModel) + && (PUBLIC(RO(Proc))->Features.Info.Signature.Model \ + == Arch[id].Signature.Model) ) + || (!Arch[id].Signature.ExtModel \ + && !Arch[id].Signature.Model) ) ) + { + break; + } + } + return id; +} + +/* Retreive the Processor(BSP) features. */ +static void Query_Features(void *pArg) +{ + INIT_ARG *iArg = (INIT_ARG *) pArg; + + volatile MIDR midr; + volatile CNTFRQ cntfrq; + volatile CNTPCT cntpct; + volatile PMCR pmcr; + volatile AA64DFR0 dfr0; + volatile AA64DFR1 dfr1; + volatile AA64ISAR0 isar0; + volatile AA64ISAR1 isar1; + volatile AA64ISAR2 isar2; + volatile AA64MMFR0 mmfr0; + volatile AA64MMFR1 mmfr1; + volatile AA64MMFR2 mmfr2; + volatile AA64PFR0 pfr0; + volatile AA64PFR1 pfr1; + + iArg->Features->Info.Vendor.CRC = CRC_RESERVED; + iArg->SMT_Count = 1; + iArg->HypervisorID = HYPERV_NONE; + + __asm__ __volatile__( + "mrs %[midr] , midr_el1" "\n\t" + "mrs %[cntfrq], cntfrq_el0" "\n\t" + "mrs %[cntpct], cntpct_el0" "\n\t" + "mrs %[pmcr] , pmcr_el0" "\n\t" + "mrs %[dfr0] , id_aa64dfr0_el1""\n\t" + "mrs %[dfr1] , id_aa64dfr1_el1""\n\t" + "mrs %[isar0], id_aa64isar0_el1""\n\t" + "mrs %[isar1], id_aa64isar1_el1""\n\t" + "mrs %[mmfr0], id_aa64mmfr0_el1""\n\t" + "mrs %[mmfr1], id_aa64mmfr1_el1""\n\t" + "mrs %[pfr0] , id_aa64pfr0_el1""\n\t" + "mrs %[pfr1] , id_aa64pfr1_el1""\n\t" + "isb" + : [midr] "=r" (midr), + [cntfrq] "=r" (cntfrq), + [cntpct] "=r" (cntpct), + [pmcr] "=r" (pmcr), + [dfr0] "=r" (dfr0), + [dfr1] "=r" (dfr1), + [isar0] "=r" (isar0), + [isar1] "=r" (isar1), + [mmfr0] "=r" (mmfr0), + [mmfr1] "=r" (mmfr1), + [pfr0] "=r" (pfr0), + [pfr1] "=r" (pfr1) + : + : "memory" + ); + + isar2.value = SysRegRead(ID_AA64ISAR2_EL1); + mmfr2.value = SysRegRead(ID_AA64MMFR2_EL1); + + iArg->Features->Info.Signature.Stepping = midr.Revision + | (midr.Variant << 4); + iArg->Features->Info.Signature.Family = midr.PartNum & 0x00f; + iArg->Features->Info.Signature.ExtFamily = (midr.PartNum & 0xff0) >> 4; + iArg->Features->Info.Signature.Model = pmcr.IDcode & 0x0f; + iArg->Features->Info.Signature.ExtModel = (pmcr.IDcode & 0xf0) >> 4; + + VendorFromMainID(midr, iArg->Features->Info.Vendor.ID, + &iArg->Features->Info.Vendor.CRC, &iArg->HypervisorID); + + iArg->Features->Factory.Freq = cntfrq.ClockFreq_Hz; + iArg->Features->Factory.Freq = iArg->Features->Factory.Freq / 10000; + +#if defined(CONFIG_ACPI) + iArg->Features->ACPI = acpi_disabled == 0; +#else + iArg->Features->ACPI = 0; +#endif + iArg->Features->TSC = \ + iArg->Features->Inv_TSC = \ + iArg->Features->RDTSCP = cntpct.PhysicalCount != 0; + + iArg->Features->PerfMon.FixCtrs = 1; /* Fixed Cycle Counter */ + iArg->Features->PerfMon.MonCtrs = pmcr.NumEvtCtrs; + iArg->Features->PerfMon.Version = dfr0.PMUVer; + + /*TODO(Memory-mapped PMU register at offset 0xe00): pmcfgr */ + iArg->Features->PerfMon.MonWidth = \ + iArg->Features->PerfMon.FixWidth = 0b111111 == 0b111111 ? 64 : 0; + + switch (dfr1.PMICNTR) { /* Performance Monitors Instruction Counter */ + case 0b0001: + iArg->Features->PerfMon.FixCtrs++; + break; + case 0b0000: + default: + break; + } + switch (dfr1.EBEP) { + case 0b0001: + iArg->Features->EBEP = 1; + break; + case 0b0000: + default: + iArg->Features->EBEP = 0; + break; + } + switch (isar0.AES) { + case 0b0010: + iArg->Features->PMULL = 1; + fallthrough; + case 0b0001: + iArg->Features->AES = 1; + break; + case 0b0000: + default: + iArg->Features->PMULL = \ + iArg->Features->AES = 0; + break; + } + switch (isar0.SHA1) { + case 0b0001: + iArg->Features->SHA1 = 1; + break; + case 0b0000: + default: + iArg->Features->SHA1 = 0; + break; + } + switch (isar0.SHA2) { + case 0b0010: + iArg->Features->SHA512 = 1; + fallthrough; + case 0b0001: + iArg->Features->SHA256 = 1; + break; + case 0b0000: + default: + iArg->Features->SHA512 = 0; + iArg->Features->SHA256 = 0; + break; + } + switch (isar0.SHA3) { + case 0b0001: + iArg->Features->SHA3 = 1; + break; + case 0b0000: + default: + iArg->Features->SHA3 = 0; + break; + } + switch (isar0.CRC32) { + case 0b0001: + iArg->Features->CRC32 = 1; + break; + case 0b0000: + default: + iArg->Features->CRC32 = 0; + break; + } + switch (isar0.CAS) { + case 0b0011: + iArg->Features->LSE128 = 1; + fallthrough; + case 0b0010: + iArg->Features->LSE = 1; + break; + case 0b0000: + default: + iArg->Features->LSE128 = \ + iArg->Features->LSE = 0; + break; + } + switch (isar0.TME) { + case 0b0001: + iArg->Features->TME = 1; + break; + case 0b0000: + default: + iArg->Features->TME = 0; + break; + } + switch (isar0.RDM) { + case 0b0001: + iArg->Features->RDMA = 1; + break; + case 0b0000: + default: + iArg->Features->RDMA = 0; + break; + } + switch (isar0.DP) { + case 0b0001: + iArg->Features->DP = 1; + break; + case 0b0000: + default: + iArg->Features->DP = 0; + break; + } + switch (isar0.SM3) { + case 0b0001: + iArg->Features->SM3 = 1; + break; + case 0b0000: + default: + iArg->Features->SM3 = 0; + break; + } + switch (isar0.SM4) { + case 0b0001: + iArg->Features->SM4 = 1; + break; + case 0b0000: + default: + iArg->Features->SM4 = 0; + break; + } + switch (isar0.FHM) { + case 0b0001: + iArg->Features->FHM = 1; + break; + case 0b0000: + default: + iArg->Features->FHM = 0; + break; + } + switch (isar0.TS) { + case 0b0010: + iArg->Features->FlagM2 = 1; + fallthrough; + case 0b0001: + iArg->Features->FlagM = 1; + break; + case 0b0000: + default: + iArg->Features->FlagM2 = \ + iArg->Features->FlagM = 0; + break; + } + switch (isar0.TLB) { + case 0b0010: + iArg->Features->TLBIRANGE = 1; + fallthrough; + case 0b0001: + iArg->Features->TLBIOS = 1; + break; + case 0b0000: + default: + iArg->Features->TLBIRANGE = \ + iArg->Features->TLBIOS = 0; + break; + } + switch (isar0.RNDR) { + case 0b0001: + iArg->Features->RAND = 1; + break; + case 0b0000: + default: + iArg->Features->RAND = 0; + break; + } + switch (isar1.FCMA) { + case 0b0001: + iArg->Features->FCMA = 1; + break; + case 0b0000: + default: + iArg->Features->FCMA = 0; + break; + } + switch (isar1.GPI) { + case 0b0001: + iArg->Features->PACIMP = 1; + break; + case 0b0000: + iArg->Features->PACIMP = 0; + break; + } + switch (isar1.GPA) { + case 0b0001: + iArg->Features->PACQARMA5 = 1; + break; + case 0b0000: + iArg->Features->PACQARMA5 = 0; + break; + } + switch (isar1.LRCPC) { + case 0b0011: + iArg->Features->LRCPC3 = 1; + fallthrough; + case 0b0010: + iArg->Features->LRCPC2 = 1; + fallthrough; + case 0b0001: + iArg->Features->LRCPC = 1; + break; + case 0b0000: + default: + iArg->Features->LRCPC3 = \ + iArg->Features->LRCPC2 = \ + iArg->Features->LRCPC = 0; + break; + } + switch (isar1.JSCVT) { + case 0b0001: + iArg->Features->JSCVT = 1; + break; + case 0b0000: + default: + iArg->Features->JSCVT = 0; + break; + } + switch (isar1.FRINTTS) { + case 0b0001: + iArg->Features->FRINTTS = 1; + break; + case 0b0000: + default: + iArg->Features->FRINTTS = 0; + break; + } + switch (isar1.SPECRES) { + case 0b0010: + iArg->Features->SPECRES2 = 1; + fallthrough; + case 0b0001: + iArg->Features->SPECRES = 1; + break; + case 0b0000: + default: + iArg->Features->SPECRES2 = \ + iArg->Features->SPECRES = 0; + break; + } + switch (isar1.BF16) { + case 0b0010: + iArg->Features->EBF16 = 1; + fallthrough; + case 0b0001: + iArg->Features->BF16 = 1; + break; + case 0b0000: + default: + iArg->Features->EBF16 = \ + iArg->Features->BF16 = 0; + break; + } + switch (isar1.I8MM) { + case 0b0001: + iArg->Features->I8MM = 1; + break; + case 0b0000: + default: + iArg->Features->I8MM = 0; + break; + } + switch (isar1.SB) { + case 0b0001: + iArg->Features->SB = 1; + break; + case 0b0000: + default: + iArg->Features->SB = 0; + break; + } + switch (isar1.XS) { + case 0b0001: + iArg->Features->XS = 1; + break; + case 0b0000: + default: + iArg->Features->XS = 0; + break; + } + switch (isar1.LS64) { + case 0b0011: + iArg->Features->LS64_ACCDATA = 1; + fallthrough; + case 0b0010: + iArg->Features->LS64_V = 1; + fallthrough; + case 0b0001: + iArg->Features->LS64 = 1; + break; + case 0b0000: + default: + iArg->Features->LS64_ACCDATA = \ + iArg->Features->LS64_V = \ + iArg->Features->LS64 = 0; + break; + } + switch (isar1.DGH) { + case 0b0001: + iArg->Features->DGH = 1; + break; + case 0b0000: + default: + iArg->Features->DGH = 0; + break; + } + switch (isar1.DPB) { + case 0b0010: + iArg->Features->DPB2 = 1; + fallthrough; + case 0b0001: + iArg->Features->DPB = 1; + break; + case 0b0000: + default: + iArg->Features->DPB2 = \ + iArg->Features->DPB = 0; + break; + } + switch (isar2.GPA3) { + case 0b0001: + iArg->Features->PACQARMA3 = 1; + break; + case 0b0000: + default: + iArg->Features->PACQARMA3 = 0; + break; + } + + iArg->Features->PAuth = (isar2.APA3 == 0b0001) || (isar1.API == 0b0001) + || (isar1.APA == 0b0001); + + iArg->Features->EPAC = (isar2.APA3 == 0b0010) || (isar1.API == 0b0010) + || (isar1.APA == 0b0010); + + iArg->Features->PAuth2 = (isar2.APA3 == 0b0011) || (isar1.API == 0b0011) + || (isar1.APA == 0b0011); + + iArg->Features->FPAC = (isar2.APA3 == 0b0100) || (isar1.API == 0b0100) + || (isar1.APA == 0b0100); + + iArg->Features->FPACCOMBINE = (isar2.APA3 == 0b0101) + || (isar1.API == 0b0101)||(isar1.APA == 0b0101); + + iArg->Features->PAuth_LR = (isar2.APA3 == 0b0110) + || (isar1.API == 0b0110)||(isar1.APA == 0b0110); + + switch (isar2.WFxT) { + case 0b0001: + iArg->Features->WFxT = 1; + break; + case 0b0000: + default: + iArg->Features->WFxT = 0; + break; + } + switch (isar2.RPRES) { + case 0b0001: + iArg->Features->RPRES = 1; + break; + case 0b0000: + default: + iArg->Features->RPRES = 0; + break; + } + switch (isar2.MOPS) { + case 0b0001: + iArg->Features->MOPS = 1; + break; + case 0b0000: + default: + iArg->Features->MOPS = 0; + break; + } + switch (isar2.BC) { + case 0b0001: + iArg->Features->HBC = 1; + break; + case 0b0000: + default: + iArg->Features->HBC = 0; + break; + } + switch (isar2.SYSREG_128) { + case 0b0001: + iArg->Features->SYSREG128 = 1; + break; + case 0b0000: + default: + iArg->Features->SYSREG128 = 0; + break; + } + switch (isar2.SYSINSTR_128) { + case 0b0001: + iArg->Features->SYSINSTR128 = 1; + break; + case 0b0000: + default: + iArg->Features->SYSINSTR128 = 0; + break; + } + switch (isar2.PRFMSLC) { + case 0b0001: + iArg->Features->PRFMSLC = 1; + break; + case 0b0000: + default: + iArg->Features->PRFMSLC = 0; + break; + } + switch (isar2.RPRFM) { + case 0b0001: + iArg->Features->RPRFM = 1; + break; + case 0b0000: + default: + iArg->Features->RPRFM = 0; + break; + } + switch (isar2.CSSC) { + case 0b0001: + iArg->Features->CSSC = 1; + break; + case 0b0000: + default: + iArg->Features->CSSC = 0; + break; + } + switch (isar2.LUT) { + case 0b0001: + iArg->Features->LUT = 1; + break; + case 0b0000: + default: + iArg->Features->LUT = 0; + break; + } + switch (isar2.ATS1A) { + case 0b0001: + iArg->Features->ATS1A = 1; + break; + case 0b0000: + default: + iArg->Features->ATS1A = 0; + break; + } + switch (isar2.PAC_frac) { + case 0b0001: + iArg->Features->CONSTPACFIELD = 1; + break; + case 0b0000: + default: + iArg->Features->CONSTPACFIELD = 0; + break; + } + + switch (mmfr0.ECV) { + case 0b0010: + case 0b0001: + iArg->Features->ECV = 1; + break; + case 0b0000: + default: + iArg->Features->ECV = 0; + break; + } + switch (mmfr0.FGT) { + case 0b0010: + iArg->Features->FGT2 = 1; + fallthrough; + case 0b0001: + iArg->Features->FGT = 1; + break; + case 0b0000: + default: + iArg->Features->FGT2 = \ + iArg->Features->FGT = 0; + } + switch (mmfr0.ExS) { + case 0b0001: + iArg->Features->ExS = 1; + break; + case 0b0000: + default: + iArg->Features->ExS = 0; + break; + } + switch (mmfr0.BigEnd_EL0) { + case 0b0001: + iArg->Features->BigEnd_EL0 = 1; + break; + case 0b0000: + default: + iArg->Features->BigEnd_EL0 = 0; + break; + } + switch (mmfr0.BigEnd) { + case 0b0001: + iArg->Features->BigEnd_EE = 1; + break; + case 0b0000: + default: + iArg->Features->BigEnd_EE = 0; + break; + } + + iArg->Features->PARange = mmfr0.PARange; + + switch (mmfr1.VH) { + case 0b0001: + iArg->Features->VHE = 1; + break; + case 0b0000: + default: + iArg->Features->VHE = 0; + break; + } + switch (mmfr1.PAN) { + case 0b0001: + case 0b0010: + case 0b0011: + iArg->Features->PAN = 1; + break; + case 0b0000: + default: + iArg->Features->PAN = 0; + break; + } + switch (mmfr1.ECBHB) { + case 0b0001: + iArg->Features->ECBHB = 1; + break; + case 0b0000: + default: + iArg->Features->ECBHB = 0; + break; + } + + switch (mmfr2.UAO) { + case 0b0001: + iArg->Features->UAO = 1; + break; + case 0b0000: + default: + iArg->Features->UAO = 0; + break; + } + if (mmfr2.VARange < 0b0011) { + iArg->Features->VARange = mmfr2.VARange; + } else { + iArg->Features->VARange = 0b11; + } + + switch (pfr0.FP) { + case 0b0000: + case 0b0001: + iArg->Features->FP = 1; + break; + case 0b1111: + default: + iArg->Features->FP = 0; + break; + } + switch (pfr0.AdvSIMD) { + case 0b0000: + case 0b0001: + iArg->Features->SIMD = 1; + break; + case 0b1111: + default: + iArg->Features->SIMD = 0; + break; + } + switch (pfr0.GIC) { + case 0b0011: + iArg->Features->GIC_frac = 1; + fallthrough; + case 0b0001: + iArg->Features->GIC_vers = 1; + break; + case 0b0000: + default: + iArg->Features->GIC_frac = \ + iArg->Features->GIC_vers = 0; + break; + } + switch (pfr0.SVE) { + case 0b0001: + iArg->Features->SVE = 1; + break; + case 0b0000: + default: + iArg->Features->SVE = 0; + break; + } + switch (pfr0.DIT) { + case 0b0001: + case 0b0010: + iArg->Features->DIT = 1; + break; + case 0b0000: + default: + iArg->Features->DIT = 0; + break; + } + switch (pfr0.RAS) { + case 0b0010: + iArg->Features->RAS_frac = 1; + iArg->Features->RAS = 1; + break; + case 0b0001: + switch (pfr1.RAS_frac) { + case 0b0001: + iArg->Features->RAS_frac = 1; + break; + case 0b0000: + default: + iArg->Features->RAS_frac = 0; + break; + } + iArg->Features->RAS = 1; + break; + case 0b0000: + default: + iArg->Features->RAS_frac = 0; + iArg->Features->RAS = 0; + break; + } + switch (pfr0.MPAM) { + case 0b0000: + case 0b0001: + iArg->Features->MPAM_vers = pfr0.MPAM; + switch (pfr1.MPAM_frac) { + case 0b0000: + case 0b0001: + iArg->Features->MPAM_frac = pfr1.MPAM_frac; + break; + default: + iArg->Features->MPAM_frac = 0; + break; + } + break; + default: + iArg->Features->MPAM_vers = \ + iArg->Features->MPAM_frac = 0; + break; + } + switch (pfr0.AMU) { + case 0b0001: + iArg->Features->AMU_vers = 1; + iArg->Features->AMU_frac = 0; + break; + case 0b0010: + iArg->Features->AMU_vers = 1; + iArg->Features->AMU_frac = 1; + break; + case 0b0000: + default: + iArg->Features->AMU_vers = 0; + iArg->Features->AMU_frac = 0; + break; + } + if (iArg->Features->AMU_vers > 0) { + AMCGCR amcgc = {.value = SysRegRead(AMCGCR_EL0)}; + iArg->Features->AMU.CG0NC = amcgc.CG0NC; + iArg->Features->AMU.CG1NC = amcgc.CG1NC; + } + switch (pfr0.RME) { + case 0b0001: + iArg->Features->RME = 1; + break; + case 0b0000: + default: + iArg->Features->RME = 0; + break; + } + switch (pfr0.SEL2) { + case 0b0001: + iArg->Features->SEL2 = 1; + break; + case 0b0000: + default: + iArg->Features->SEL2 = 0; + break; + } + + switch (pfr1.BT) { + case 0b0001: + iArg->Features->BTI = 1; + break; + case 0b0000: + default: + iArg->Features->BTI = 0; + break; + } + + iArg->Features->SSBS = pfr1.SSBS; + + switch (pfr1.MTE) { + case 0b0010: + switch (pfr1.MTE_frac) { + case 0b0000: + iArg->Features->MTE = 3; + break; + case 0b1111: + iArg->Features->MTE = 2; + break; + default: + iArg->Features->MTE = 1; + break; + } + break; + case 0b0011: + default: + switch (pfr1.MTEX) { + case 0b0001: + iArg->Features->MTE = 4; + break; + case 0b0000: + default: + iArg->Features->MTE = 3; + break; + } + break; + case 0b0001: + iArg->Features->MTE = 1; + break; + case 0b0000: + iArg->Features->MTE = 0; + break; + } + switch (pfr1.SME) { + case 0b0001: + case 0b0010: + iArg->Features->SME = 1; + break; + case 0b0000: + default: + iArg->Features->SME = 0; + break; + } + switch (pfr1.RNDR_trap) { + case 0b0001: + iArg->Features->RNG_TRAP = 1; + break; + case 0b0000: + default: + iArg->Features->RNG_TRAP = 0; + break; + } + + iArg->Features->CSV2 = pfr1.CSV2_frac; + + switch (pfr1.NMI) { + case 0b0001: + iArg->Features->NMI = 1; + break; + case 0b0000: + default: + iArg->Features->NMI = 0; + break; + } + switch (pfr1.GCS) { + case 0b0001: + iArg->Features->GCS = 1; + break; + case 0b0000: + default: + iArg->Features->GCS = 0; + break; + } + switch (pfr1.THE) { + case 0b0001: + iArg->Features->THE = 1; + break; + case 0b0000: + default: + iArg->Features->THE = 0; + break; + } + switch (pfr1.DF2) { + case 0b0001: + iArg->Features->DF2 = 1; + break; + case 0b0000: + default: + iArg->Features->DF2 = 0; + break; + } + switch (pfr1.PFAR) { + case 0b0001: + iArg->Features->PFAR = 1; + break; + case 0b0000: + default: + iArg->Features->PFAR = 0; + break; + } + if (iArg->Features->SVE | iArg->Features->SME) + { + volatile AA64ZFR0 zfr0 = {.value = SysRegRead(ID_AA64ZFR0_EL1)}; + + switch (zfr0.SVE_F64MM) { + case 0b0001: + iArg->Features->SVE_F64MM = 1; + break; + case 0b0000: + default: + iArg->Features->SVE_F64MM = 0; + break; + } + switch (zfr0.SVE_F32MM) { + case 0b0001: + iArg->Features->SVE_F32MM = 1; + break; + case 0b0000: + default: + iArg->Features->SVE_F32MM = 0; + break; + } + switch (zfr0.SVE_I8MM) { + case 0b0001: + iArg->Features->SVE_I8MM = 1; + break; + case 0b0000: + default: + iArg->Features->SVE_I8MM = 0; + break; + } + switch (zfr0.SVE_SM4) { + case 0b0001: + iArg->Features->SVE_SM4 = 1; + break; + case 0b0000: + default: + iArg->Features->SVE_SM4 = 0; + break; + } + switch (zfr0.SVE_SHA3) { + case 0b0001: + iArg->Features->SVE_SHA3 = 1; + break; + case 0b0000: + default: + iArg->Features->SVE_SHA3 = 0; + break; + } + switch (zfr0.SVE_BF16) { + case 0b0010: + iArg->Features->SVE_EBF16 = 1; + fallthrough; + case 0b0001: + iArg->Features->SVE_BF16 = 1; + break; + case 0b0000: + default: + iArg->Features->SVE_EBF16 = \ + iArg->Features->SVE_BF16 = 0; + break; + } + switch (zfr0.BitPerm) { + case 0b0001: + iArg->Features->SVE_BitPerm = 1; + break; + case 0b0000: + default: + iArg->Features->SVE_BitPerm = 0; + break; + } + switch (zfr0.SVE_AES) { + case 0b0010: + iArg->Features->SVE_PMULL128 = 1; + fallthrough; + case 0b0001: + iArg->Features->SVE_AES = 1; + break; + case 0b0000: + default: + iArg->Features->SVE_PMULL128 = \ + iArg->Features->SVE_AES = 0; + } + switch (zfr0.SVE_Ver) { + case 0b0001: + iArg->Features->SVE2 = 1; + break; + default: + iArg->Features->SVE2 = 0; + break; + } + } + if (iArg->Features->SME) { + volatile AA64SMFR0 smfr0 = {.value = SysRegRead(ID_AA64SMFR0_EL1)}; + + switch (smfr0.SMEver) { + case 0b0010: + iArg->Features->SME2p1 = 1; + fallthrough; + case 0b0001: + iArg->Features->SME2 = 1; + break; + default: + iArg->Features->SME2p1 = \ + iArg->Features->SME2 = 0; + break; + } + + iArg->Features->SME_FA64 = smfr0.FA64; + iArg->Features->SME_LUTv2 = smfr0.LUTv2; + + switch (smfr0.I16I64) { + case 0b1111: + iArg->Features->SME_I16I64 = 1; + break; + case 0b0000: + default: + iArg->Features->SME_I16I64 = 0; + break; + } + + iArg->Features->SME_F64F64 = smfr0.F64F64; + + switch (smfr0.I16I32) { + case 0b0101: + iArg->Features->SME_I16I32 = 1; + break; + case 0b0000: + default: + iArg->Features->SME_I16I32 = 0; + break; + } + + iArg->Features->SME_B16B16 = smfr0.B16B16; + iArg->Features->SME_F16F16 = smfr0.F16F16; + iArg->Features->SME_F8F16 = smfr0.F8F16; + iArg->Features->SME_F8F32 = smfr0.F8F32; + + switch (smfr0.I8I32) { + case 0b1111: + iArg->Features->SME_I8I32 = 1; + break; + case 0b0000: + default: + iArg->Features->SME_I8I32 = 0; + break; + } + + iArg->Features->SME_F16F32 = smfr0.F16F32; + iArg->Features->SME_B16F32 = smfr0.B16F32; + iArg->Features->SME_BI32I32 = smfr0.BI32I32; + iArg->Features->SME_F32F32 = smfr0.F32F32; + iArg->Features->SME_SF8FMA = smfr0.SF8FMA; + iArg->Features->SME_SF8DP4 = smfr0.SF8DP4; + iArg->Features->SME_SF8DP2 = smfr0.SF8DP2; + } + /* Reset the performance features bits: present is 0b1 */ + iArg->Features->PerfMon.CoreCycles = 0b0; + iArg->Features->PerfMon.InstrRetired = 0b0; +} + +static void Compute_Interval(void) +{ + if ( (SleepInterval >= LOOP_MIN_MS) + && (SleepInterval <= LOOP_MAX_MS)) + { + PUBLIC(RO(Proc))->SleepInterval = SleepInterval; + } else { + PUBLIC(RO(Proc))->SleepInterval = LOOP_DEF_MS; + } + /* Compute the tick steps . */ + PUBLIC(RO(Proc))->tickReset = \ + ( (TickInterval >= PUBLIC(RO(Proc))->SleepInterval) + && (TickInterval <= LOOP_MAX_MS) ) ? + TickInterval + : KMAX(TICK_DEF_MS, PUBLIC(RO(Proc))->SleepInterval); + + PUBLIC(RO(Proc))->tickReset /= PUBLIC(RO(Proc))->SleepInterval; + PUBLIC(RO(Proc))->tickStep = PUBLIC(RO(Proc))->tickReset; + + RearmTheTimer = ktime_set( 0, PUBLIC(RO(Proc))->SleepInterval + * 1000000LU ); +} + +#ifdef CONFIG_SMP +/*TODO #define THIS_LPJ this_cpu_read(cpu_info.loops_per_jiffy)*/ + #define THIS_LPJ loops_per_jiffy +#else + #define THIS_LPJ loops_per_jiffy +#endif + +#define COMPUTE_LPJ(BCLK_Hz, COF) ( (BCLK_Hz * COF) / HZ ) + +#if defined(DELAY_TSC) && (DELAY_TSC == 1) +/* udelay() built with TSC implementation */ +#define CLOCK_TSC( CYCLES, _TIMER, CTR ) \ +({ \ +/*TODO __asm__ volatile \ + ( \ + ASM_RD##_TIMER(r14) \ + "addq %[cycles], %%rax" "\n\t" \ + "movq %%rax , %%r15" "\n\t" \ + "1:" "\n\t" \ + ASM_RD##_TIMER(r13) \ + "cmpq %%r15 , %%r13" "\n\t" \ + "jc 1b" "\n\t" \ + "movq %%r14 , %[ctr0]" "\n\t" \ + "movq %%r13 , %[ctr1]" \ + : [ctr0] "=m" (CTR[0]), \ + [ctr1] "=m" (CTR[1]) \ + : [cycles] "ir" (CYCLES) \ + : "%rax", "%rbx", "%rcx", "%rdx", \ + "%r13", "%r14", "%r15", \ + "cc", "memory" \ + ); */ \ +}) + +#define CLOCK2CYCLE(INTERVAL_NS) ((INTERVAL_NS * THIS_LPJ * HZ) / 1000000LLU) + +#define CLOCK_DELAY(INTERVAL_NS, _TIMER, CTR) \ +({ \ + CLOCK_TSC( CLOCK2CYCLE(INTERVAL_NS), _TIMER, CTR ); \ +}) + +#define CLOCK_OVERHEAD(_TIMER, CTR) CLOCK_TSC( 1LLU, _TIMER, CTR ) + +#else + +#define CLOCK_DELAY(INTERVAL_NS, _TIMER, CTR) \ +({ \ + RD##_TIMER##64(CTR[0]); \ + udelay(INTERVAL_NS); \ + RD##_TIMER##64(CTR[1]); \ +}) + +#define CLOCK_OVERHEAD(_TIMER, CTR) CLOCK_DELAY( 0LLU, _TIMER, CTR ) + +#endif + +static void Measure_TSC(COMPUTE_ARG *pCompute) +{ + unsigned int loop; + /* Writeback and Invalidate Caches. */ + WBINVD(); + /* Warm-up & Overhead */ + for (loop = 0; loop < OCCURRENCES; loop++) + { + CLOCK_OVERHEAD(TSC, pCompute->TSC[0][loop].V); + } + /* Estimation */ + for (loop = 0; loop < OCCURRENCES; loop++) + { + CLOCK_DELAY(1000LLU, TSC, pCompute->TSC[1][loop].V); + } +} + +static void Compute_TSC(void *arg) +{ + COMPUTE_ARG *pCompute = (COMPUTE_ARG *) arg; + unsigned long long D[2][OCCURRENCES]; + unsigned int ratio = (unsigned int) pCompute->Clock.Q; + unsigned int loop = 0, what = 0, best[2] = {0, 0}, top[2] = {0, 0}; +/* + TSC[0] stores the overhead + TSC[1] stores the estimation +*/ + Measure_TSC(pCompute); + + /* Select the best clock. */ + for (loop = 0; loop < OCCURRENCES; loop++) { + for (what = 0; what < 2; what++) { + D[what][loop] = pCompute->TSC[what][loop].V[1] + - pCompute->TSC[what][loop].V[0]; + } + } + for (loop = 0; loop < OCCURRENCES; loop++) { + unsigned int inner = 0, count[2] = {0, 0}; + for (inner = loop; inner < OCCURRENCES; inner++) { + for (what = 0; what < 2; what++) { + if (D[what][loop] == D[what][inner]) + count[what]++; + } + } + for (what = 0; what < 2; what++) { + if ((count[what] > top[what]) + || ((count[what] == top[what]) + && (D[what][loop] < D[what][best[what]]))) { + + top[what] = count[what]; + best[what] = loop; + + } + } + } + /* Substract the overhead . */ + D[1][best[1]] -= D[0][best[0]]; + /* Compute the Base Clock . */ + REL_BCLK(pCompute->Clock, ratio, D[1][best[1]], 1LLU); +} + +static CLOCK Compute_Clock(unsigned int cpu, COMPUTE_ARG *pCompute) +{ +/* Synchronously call the Base Clock estimation on a pinned CPU. + * 1/ Preemption is disabled by smp_call_function_single() > get_cpu() + * 2/ IRQ are suspended by generic_exec_single(func) > local_irq_save() + * 3/ Function 'func' is executed + * 4/ IRQ are resumed > local_irq_restore() + * 5/ Preemption is enabled > put_cpu() + */ + smp_call_function_single(cpu, Compute_TSC, pCompute, 1); + + return pCompute->Clock; +} + +inline void ClockToHz(CLOCK *clock) +{ + clock->Hz = clock->Q * 1000000L; + clock->Hz += clock->R * PRECISION; +} + +static CLOCK BaseClock_GenericMachine(unsigned int ratio) +{ + CLOCK clock = {.Q = 100, .R = 0, .Hz = 100000000L}; + UNUSED(ratio); + return clock; +}; + +static void Cache_Level(CORE_RO *Core, unsigned int level, unsigned int select) +{ + const CSSELR cssel[CACHE_MAX_LEVEL] = { + [0] = { .InD = 1, .Level = 0 }, /* L1I */ + [1] = { .InD = 0, .Level = 0 }, /* L1D */ + [2] = { .InD = 0, .Level = 1 }, /* L2 */ + [3] = { .InD = 0, .Level = 2 } /* L3 */ + }; + __asm__ volatile + ( + "msr csselr_el1, %[cssel]" "\n\t" + "mrs %[ccsid], ccsidr_el1" "\n\t" + "isb" + : [ccsid] "=r" (Core->T.Cache[level].ccsid) + : [cssel] "r" (cssel[select]) + : "memory" + ); +} + +static void Cache_Topology(CORE_RO *Core) +{ + volatile CLIDR clidr; + __asm__ volatile + ( + "mrs %[clidr], clidr_el1" "\n\t" + "isb" + : [clidr] "=r" (clidr) + : + : "memory" + ); + + if (clidr.Ctype1 == 0b011) { + Cache_Level(Core, 0, 0); /* L1I */ + Cache_Level(Core, 1, 1); /* L1D */ + } else if (clidr.Ctype1 == 0b010) { + /* Skip L1I */ + Cache_Level(Core, 1, 1); /* L1D */ + } else if (clidr.Ctype1 == 0b001) { + Cache_Level(Core, 0, 0); /* L1I */ + /* Skip L1D */ + } + if (clidr.Ctype2 == 0b100) { /* L2 */ + Cache_Level(Core, 2, 2); + } + if (clidr.Ctype3 == 0b100) { /* L3 */ + Cache_Level(Core, 3, 3); + } +} + +static void Map_Generic_Topology(void *arg) +{ + if (arg != NULL) { + CORE_RO *Core = (CORE_RO *) arg; + + volatile MIDR midr; + volatile MPIDR mpid; + __asm__ volatile + ( + "mrs %[midr] , midr_el1" "\n\t" + "mrs %[mpid] , mpidr_el1" "\n\t" + "isb" + : [midr] "=r" (midr), + [mpid] "=r" (mpid) + : + : "memory" + ); + Core->T.PN = midr.PartNum; + if (mpid.MT) { + Core->T.MPID = mpid.value & 0xfffff; + Core->T.Cluster.CMP = mpid.Aff3; + Core->T.PackageID = mpid.Aff2; + Core->T.CoreID = mpid.Aff1; + Core->T.ThreadID = mpid.Aff0; + } else { + Core->T.MPID = mpid.value & 0xfffff; + Core->T.PackageID = mpid.Aff2; + Core->T.Cluster.CMP = mpid.Aff1; + Core->T.CoreID = mpid.Aff0; + } + Cache_Topology(Core); + } +} + +static int Core_Topology(unsigned int cpu) +{ + int rc = smp_call_function_single(cpu , Map_Generic_Topology, + PUBLIC(RO(Core, AT(cpu))), 1); + if ( !rc + && (PUBLIC(RO(Proc))->Features.HTT_Enable == 0) + && (PUBLIC(RO(Core, AT(cpu)))->T.ThreadID > 0) ) + { + PUBLIC(RO(Proc))->Features.HTT = 1; + PUBLIC(RO(Proc))->Features.HTT_Enable = 1; + } + return rc; +} + +static unsigned int Proc_Topology(void) +{ + unsigned int cpu, PN = 0, CountEnabledCPU = 0; + struct SIGNATURE SoC; + + for (cpu = 0; cpu < PUBLIC(RO(Proc))->CPU.Count; cpu++) { + PUBLIC(RO(Core, AT(cpu)))->T.PN = 0; + PUBLIC(RO(Core, AT(cpu)))->T.BSP = 0; + PUBLIC(RO(Core, AT(cpu)))->T.MPID = -1; + PUBLIC(RO(Core, AT(cpu)))->T.CoreID = -1; + PUBLIC(RO(Core, AT(cpu)))->T.ThreadID = -1; + PUBLIC(RO(Core, AT(cpu)))->T.PackageID = -1; + PUBLIC(RO(Core, AT(cpu)))->T.Cluster.ID = 0; + + BITSET(LOCKLESS, PUBLIC(RO(Core, AT(cpu)))->OffLine, HW); + BITSET(LOCKLESS, PUBLIC(RO(Core, AT(cpu)))->OffLine, OS); + + if (cpu_present(cpu)) { /* CPU state probed by the OS. */ + if (Core_Topology(cpu) == 0) { + /* CPU state based on the hardware. */ + if (PUBLIC(RO(Core, AT(cpu)))->T.MPID >= 0) + { + BITCLR(LOCKLESS, PUBLIC(RO(Core, AT(cpu)))->OffLine,HW); + + CountEnabledCPU++; + } + BITCLR(LOCKLESS, PUBLIC(RO(Core, AT(cpu)))->OffLine, OS); + } + } + PN = ( PN ^ PUBLIC(RO(Core, AT(cpu)))->T.PN ) + | PUBLIC(RO(Core, AT(cpu)))->T.PN; + } + SoC.Family = PN & 0x00f; + SoC.ExtFamily = (PN & 0xff0) >> 4; + + PUBLIC(RO(Proc))->Features.Hybrid = !( + SoC.Family == PUBLIC(RO(Proc))->Features.Info.Signature.Family + && SoC.ExtFamily == PUBLIC(RO(Proc))->Features.Info.Signature.ExtFamily + ); + return CountEnabledCPU; +} + +#define HyperThreading_Technology() \ +( \ + PUBLIC(RO(Proc))->CPU.OnLine = Proc_Topology() \ +) + +static void Package_Init_Reset(void) +{ + PUBLIC(RO(Proc))->Features.TgtRatio_Unlock = 1; + PUBLIC(RO(Proc))->Features.ClkRatio_Unlock = 0; + PUBLIC(RO(Proc))->Features.TDP_Unlock = 0; + PUBLIC(RO(Proc))->Features.Turbo_Unlock = 0; + PUBLIC(RO(Proc))->Features.Turbo_OPP = 0; + PUBLIC(RO(Proc))->Features.TDP_Cfg_Lock = 1; + PUBLIC(RO(Proc))->Features.Uncore_Unlock = 0; +} + +static void Default_Unlock_Reset(void) +{ + switch (Target_Ratio_Unlock) { + case COREFREQ_TOGGLE_OFF: + case COREFREQ_TOGGLE_ON: + PUBLIC(RO(Proc))->Features.TgtRatio_Unlock = Target_Ratio_Unlock; + break; + } + switch (Clock_Ratio_Unlock) { + case COREFREQ_TOGGLE_OFF: + case 0b01: + case 0b10: + case 0b11: + PUBLIC(RO(Proc))->Features.ClkRatio_Unlock = Clock_Ratio_Unlock; + break; + } + switch (Turbo_Ratio_Unlock) { + case COREFREQ_TOGGLE_OFF: + case COREFREQ_TOGGLE_ON: + PUBLIC(RO(Proc))->Features.Turbo_Unlock = Turbo_Ratio_Unlock; + break; + } + switch (Uncore_Ratio_Unlock) { + case COREFREQ_TOGGLE_OFF: + case COREFREQ_TOGGLE_ON: + PUBLIC(RO(Proc))->Features.Uncore_Unlock = Uncore_Ratio_Unlock; + break; + } +} + +static void OverrideCodeNameString(PROCESSOR_SPECIFIC *pSpecific) +{ + StrCopy(PUBLIC(RO(Proc))->Architecture, + Arch[ + PUBLIC(RO(Proc))->ArchID + ].Architecture.Brand[pSpecific->CodeNameIdx], CODENAME_LEN); +} + +static void OverrideUnlockCapability(PROCESSOR_SPECIFIC *pSpecific) +{ + if (pSpecific->Latch & LATCH_TGT_RATIO_UNLOCK) { + PUBLIC(RO(Proc))->Features.TgtRatio_Unlock=pSpecific->TgtRatioUnlocked; + } + if (pSpecific->Latch & LATCH_CLK_RATIO_UNLOCK) { + PUBLIC(RO(Proc))->Features.ClkRatio_Unlock=pSpecific->ClkRatioUnlocked; + } + if (pSpecific->Latch & LATCH_TURBO_UNLOCK) { + PUBLIC(RO(Proc))->Features.Turbo_Unlock = pSpecific->TurboUnlocked; + } + if (pSpecific->Latch & LATCH_UNCORE_UNLOCK) { + PUBLIC(RO(Proc))->Features.Uncore_Unlock = pSpecific->UncoreUnlocked; + } + if (pSpecific->Latch & LATCH_OTHER_CAPABLE) { + PUBLIC(RO(Proc))->Features.Other_Capable = pSpecific->Other_Capable; + } +} + +static PROCESSOR_SPECIFIC *LookupProcessor(void) +{ + PROCESSOR_SPECIFIC *pSpecific; + for (pSpecific = Arch[PUBLIC(RO(Proc))->ArchID].Specific; + (pSpecific != NULL) && (pSpecific->Brand != NULL); + pSpecific++) + { + char **brands, *brand; + for (brands = pSpecific->Brand, brand = *brands; + brand != NULL; + brands++, brand = *brands) + { + if (strstr(PUBLIC(RO(Proc))->Features.Info.Brand, brand)) { + return pSpecific; + } + } + } + return NULL; +} + +static void Query_DeviceTree(unsigned int cpu) +{ + CORE_RO *Core = (CORE_RO *) PUBLIC(RO(Core, AT(cpu))); +#ifdef CONFIG_CPU_FREQ + struct cpufreq_policy *pFreqPolicy = \ + &PRIVATE(OF(Core, AT(cpu)))->FreqPolicy; +#endif + volatile CNTFRQ cntfrq; + unsigned int max_freq = 0, min_freq = 0, cur_freq = 0; + + __asm__ __volatile__( + "mrs %[cntfrq], cntfrq_el0" "\n\t" + "isb" + : [cntfrq] "=r" (cntfrq) + : + : "memory" + ); + cntfrq.value = cntfrq.value / 1000000U; +#ifdef CONFIG_CPU_FREQ + if (cpufreq_get_policy(pFreqPolicy,cpu) == 0) + { +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0) + struct cpufreq_frequency_table *table; + enum RATIO_BOOST boost = BOOST(MIN); +#endif + max_freq = pFreqPolicy->cpuinfo.max_freq; + min_freq = pFreqPolicy->cpuinfo.min_freq; + cur_freq = pFreqPolicy->cur; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0) + cpufreq_for_each_valid_entry(table, pFreqPolicy->freq_table) + { + if (table->frequency != min_freq) { + if (boost < (BOOST(SIZE) - BOOST(18C))) + { + Core->Boost[BOOST(18C) + boost] = table->frequency + / UNIT_KHz(PRECISION); + boost++; + } + } + if ((table->flags & CPUFREQ_BOOST_FREQ) == CPUFREQ_BOOST_FREQ) { + const unsigned int COF = table->frequency / UNIT_KHz(PRECISION); + if (COF > Core->Boost[BOOST(TBH)]) { + Core->Boost[BOOST(TBO)] = Core->Boost[BOOST(TBH)]; + Core->Boost[BOOST(TBH)] = COF; + } + PUBLIC(RO(Proc))->Features.Turbo_OPP = 1; + } + } + if (boost > BOOST(MIN)) { + const enum RATIO_BOOST diff = BOOST(SIZE) - (BOOST(18C) + boost); + + memmove(&Core->Boost[BOOST(18C) + diff], &Core->Boost[BOOST(18C)], + boost * sizeof(enum RATIO_BOOST)); + + memset(&Core->Boost[BOOST(18C)], 0, diff * sizeof(enum RATIO_BOOST)); + } +#endif + } +#endif /* CONFIG_CPU_FREQ */ + Core->Boost[BOOST(MAX)] = max_freq > 0 ? max_freq / UNIT_KHz(PRECISION) + : cntfrq.ClockFreq_Hz; + + Core->Boost[BOOST(MIN)] = min_freq > 0 ? min_freq / UNIT_KHz(PRECISION) + : 4; + + Core->Boost[BOOST(TGT)] = cur_freq / UNIT_KHz(PRECISION); +} + +static void Compute_ACPI_CPPC_Bounds(unsigned int cpu) +{ + CORE_RO *Core = (CORE_RO *) PUBLIC(RO(Core, AT(cpu))); + + if (Core->PowerThermal.ACPI_CPPC.Highest > \ + PUBLIC(RO(Proc))->PowerThermal.ACPI_CPPC.Maximum) + { + PUBLIC(RO(Proc))->PowerThermal.ACPI_CPPC.Maximum = \ + Core->PowerThermal.ACPI_CPPC.Highest; + } + if (Core->PowerThermal.ACPI_CPPC.Highest < \ + PUBLIC(RO(Proc))->PowerThermal.ACPI_CPPC.Minimum) + { + PUBLIC(RO(Proc))->PowerThermal.ACPI_CPPC.Minimum = \ + Core->PowerThermal.ACPI_CPPC.Highest; + } +} + +inline signed int Disable_ACPI_CPPC(unsigned int cpu, void *arg) +{ +#if defined(CONFIG_ACPI_CPPC_LIB) \ + && LINUX_VERSION_CODE >= KERNEL_VERSION(5, 17, 0) + signed int rc = cppc_set_enable((signed int) cpu, false); +#else + signed int rc = -ENODEV; +#endif /* CONFIG_ACPI_CPPC_LIB */ + UNUSED(arg); + + if (rc != 0) { + pr_debug("CoreFreq: cppc_set_enable(cpu=%u, false) error %d\n", + cpu, rc); + } + Compute_ACPI_CPPC_Bounds(cpu); + + return rc; +} + +inline signed int Enable_ACPI_CPPC(unsigned int cpu, void *arg) +{ +#if defined(CONFIG_ACPI_CPPC_LIB) \ + && LINUX_VERSION_CODE >= KERNEL_VERSION(5, 17, 0) + signed int rc = cppc_set_enable((signed int) cpu, true); +#else + signed int rc = -ENODEV; +#endif /* CONFIG_ACPI_CPPC_LIB */ + UNUSED(arg); + + if (rc != 0) { + pr_debug("CoreFreq: cppc_set_enable(cpu=%u, true) error %d\n", + cpu, rc); + } + Compute_ACPI_CPPC_Bounds(cpu); + + return rc; +} + +static signed int Get_ACPI_CPPC_Registers(unsigned int cpu, void *arg) +{ +#ifdef CONFIG_ACPI_CPPC_LIB + struct cppc_perf_fb_ctrs CPPC_Perf; + struct cppc_perf_caps CPPC_Caps; + + CORE_RO *Core = (CORE_RO *) PUBLIC(RO(Core, AT(cpu))); + + signed int rc = 0; + UNUSED(arg); + + if ((rc = cppc_get_perf_ctrs(Core->Bind, &CPPC_Perf)) == 0) { + if ((rc = cppc_get_perf_caps(Core->Bind, &CPPC_Caps)) != 0) + pr_debug("CoreFreq: cppc_get_perf_caps(cpu=%u) error %d\n", + Core->Bind, rc); + } else { + pr_debug("CoreFreq: cppc_get_perf_ctrs(cpu=%u) error %d\n", + Core->Bind, rc); + } + if (rc == 0) { + #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 1, 0) + unsigned long long desired_perf = 0; + #endif + Core->PowerThermal.ACPI_CPPC = (struct ACPI_CPPC_STRUCT) { + .Highest = CPPC_Caps.highest_perf, + #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0) + .Guaranteed = CPPC_Caps.guaranteed_perf == 0 ? + CPPC_Caps.nominal_perf + : CPPC_Caps.guaranteed_perf, + #else + .Guaranteed = CPPC_Caps.nominal_perf, + #endif + #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 18, 0) + .Efficient = CPPC_Caps.nominal_freq, + .Lowest = CPPC_Caps.lowest_freq, + .Minimum = CPPC_Caps.lowest_freq, + #else + .Efficient = CPPC_Caps.nominal_perf, + .Lowest = CPPC_Caps.lowest_perf, + .Minimum = CPPC_Caps.lowest_perf, + #endif + .Maximum = CPPC_Caps.highest_perf, + #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0) + .Desired = CPPC_Perf.reference_perf, + #elif LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0) + .Desired = CPPC_Caps.reference_perf, + #else + .Desired = 0, + #endif + .Energy = 0 + }; + #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 1, 0) + #if (defined(CONFIG_SCHED_BORE) || defined(CONFIG_CACHY)) \ + && (LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0)) + rc = cppc_get_desired_perf(Core->Bind, &desired_perf); + rc = rc == -EINVAL ? 0 : rc; + #else + rc = cppc_get_desired_perf(Core->Bind, &desired_perf); + #endif + if (rc == 0) { + Core->PowerThermal.ACPI_CPPC.Desired = desired_perf; + } else { + pr_debug("CoreFreq: cppc_get_desired_perf(cpu=%u) error %d\n", + Core->Bind, rc); + } + #endif + } + return rc; +#else + return -ENODEV; +#endif /* CONFIG_ACPI_CPPC_LIB */ +} + +static signed int Get_EPP_ACPI_CPPC(unsigned int cpu) +{ + signed int rc = -ENODEV; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) + u64 epp_perf; + + if ((rc = cppc_get_epp_perf((signed int) cpu, &epp_perf)) == 0) + { + CORE_RO *Core = (CORE_RO *) PUBLIC(RO(Core, AT(cpu))); + + Core->PowerThermal.ACPI_CPPC.Energy = epp_perf; + } else { + pr_debug("CoreFreq: cppc_get_epp_perf(cpu=%u) error %d\n", cpu, rc); + } +#endif + return rc; +} + +static signed int Put_EPP_ACPI_CPPC(unsigned int cpu, signed short epp) +{ + signed int rc = -ENODEV; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) + struct cppc_perf_ctrls perf_ctrls = { + .max_perf = 0, + .min_perf = 0, + .desired_perf = 0, + .energy_perf = epp + }; + if ((rc = cppc_set_epp_perf((signed int) cpu, &perf_ctrls, true)) < 0) { + pr_debug("CoreFreq: cppc_set_epp_perf(cpu=%u) error %d\n", cpu, rc); + } +#endif + return rc; +} + +static signed int Set_EPP_ACPI_CPPC(unsigned int cpu, void *arg) +{ + signed int rc = 0; + UNUSED(arg); + + if ((HWP_EPP >= 0) && (HWP_EPP <= 0xff)) { + if ((rc = Put_EPP_ACPI_CPPC(cpu, HWP_EPP)) == 0) { + rc = Get_EPP_ACPI_CPPC(cpu); + } + } + return rc; +} + +static signed int Read_ACPI_CPPC_Registers(unsigned int cpu, void *arg) +{ + signed int rc = Get_ACPI_CPPC_Registers(cpu, arg); + + Compute_ACPI_CPPC_Bounds(cpu); + + if (Get_EPP_ACPI_CPPC(cpu) == 0) { + PUBLIC(RO(Proc))->Features.OSPM_EPP = 1; + } + Set_EPP_ACPI_CPPC(cpu, arg); + + return rc; +} + +static void For_All_ACPI_CPPC( signed int (*CPPC_Func)(unsigned int, void*), + void *arg ) +{ + #if defined(CONFIG_ACPI_CPPC_LIB) \ + && LINUX_VERSION_CODE >= KERNEL_VERSION(5, 11, 0) + signed int rc = acpi_cpc_valid() == false; + #elif defined(CONFIG_ACPI) + signed int rc = acpi_disabled; + #else + signed int rc = false; + #endif + unsigned int cpu; + + PUBLIC(RO(Proc))->Features.OSPM_CPC = !rc; + PUBLIC(RO(Proc))->PowerThermal.ACPI_CPPC.Minimum = 255U; + PUBLIC(RO(Proc))->PowerThermal.ACPI_CPPC.Maximum = 1U; + + for (cpu = 0; (cpu < PUBLIC(RO(Proc))->CPU.Count) && (rc == 0); cpu++) + { + if (!BITVAL(PUBLIC(RO(Core, AT(cpu)))->OffLine, OS)) { + rc = CPPC_Func(cpu, arg); + } + } + PUBLIC(RO(Proc))->Features.ACPI_CPPC = (rc == 0); +} + +static void CoreFreqK_ResetChip(struct pci_dev *dev) +{ + UNUSED(dev); + + memset( PUBLIC(RO(Proc))->Uncore.Chip, 0, + CHIP_MAX_PCI*sizeof(struct CHIP_ST) ); +} + +static void CoreFreqK_AppendChip(struct pci_dev *dev) +{ + unsigned int idx; + for (idx = 0; idx < CHIP_MAX_PCI; idx++) + { + if (PUBLIC(RO(Proc))->Uncore.Chip[idx].VID == 0) + { + PUBLIC(RO(Proc))->Uncore.Chip[idx].VID = dev->vendor; + PUBLIC(RO(Proc))->Uncore.Chip[idx].DID = dev->device; + + break; + } + } +} + +static int CoreFreqK_ProbePCI( struct pci_device_id PCI_ids[], + void (*PreProbe)(struct pci_dev*), + void (*PostProbe)(struct pci_dev*) ) +{ + struct pci_device_id *id = PCI_ids; + struct pci_dev *dev = NULL; + int rc = -ENODEV; + + if (PreProbe != NULL) { + PreProbe(dev); + } + while (id->vendor || id->subvendor || id->class_mask) + { + dev = pci_get_device(id->vendor, id->device, NULL); + if (dev != NULL) { + if (!pci_enable_device(dev)) + { + PCI_CALLBACK Callback = (PCI_CALLBACK) id->driver_data; + + if ((rc = (int) Callback(dev)) == 0) + { + if (PostProbe != NULL) { + PostProbe(dev); + } + } + pci_disable_device(dev); + } + pci_dev_put(dev); + } + id++; + } + return rc; +} + +static void Query_Same_Genuine_Features(void) +{ + if ((PRIVATE(OF(Specific)) = LookupProcessor()) != NULL) + { + OverrideCodeNameString(PRIVATE(OF(Specific))); + OverrideUnlockCapability(PRIVATE(OF(Specific))); + } + Default_Unlock_Reset(); + + if (PUBLIC(RO(Proc))->Features.Turbo_Unlock) + { + PUBLIC(RO(Proc))->Features.SpecTurboRatio = 1; + } else { + PUBLIC(RO(Proc))->Features.SpecTurboRatio = 0; + } +#if defined(CONFIG_CPU_FREQ) && LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0) + PUBLIC(RO(Proc))->Features.SpecTurboRatio += (BOOST(SIZE) - BOOST(18C)); +#endif +} + +static void Query_GenericMachine(unsigned int cpu) +{ + Query_Same_Genuine_Features(); + + Query_DeviceTree(cpu); + + if (PRIVATE(OF(Specific)) != NULL) { + /* Save the thermal parameters if specified */ + PUBLIC(RO(Proc))->PowerThermal.Param = PRIVATE(OF(Specific))->Param; + } else { + PUBLIC(RO(Proc))->PowerThermal.Param.Target = 0; + } + HyperThreading_Technology(); + + For_All_ACPI_CPPC(Read_ACPI_CPPC_Registers, NULL); +} + +static void Query_DynamIQ(unsigned int cpu) +{ + Query_GenericMachine(cpu); + + if (PUBLIC(RO(Proc))->HypervisorID == BARE_METAL) { + /* Query the Cluster Configuration on Bare Metal only */ + PUBLIC(RO(Proc))->Uncore.ClusterCfg.value = SysRegRead(CLUSTERCFR_EL1); + PUBLIC(RO(Proc))->Uncore.ClusterRev.value = SysRegRead(CLUSTERIDR_EL1); + } +} + +static void SystemRegisters(CORE_RO *Core) +{ + volatile AA64ISAR2 isar2; + volatile AA64MMFR1 mmfr1; + volatile AA64PFR0 pfr0; + + isar2.value = SysRegRead(ID_AA64ISAR2_EL1); + + __asm__ __volatile__( + "mrs %[sctlr], sctlr_el1" "\n\t" + "mrs %[mmfr1], id_aa64mmfr1_el1""\n\t" + "mrs %[pfr0] , id_aa64pfr0_el1""\n\t" + "mrs %[fpsr] , fpsr" "\n\t" + "cmp xzr , xzr, lsl #0" "\n\t" + "mrs x14 , nzcv" "\n\t" + "mrs x13 , daif" "\n\t" + "mrs x12 , currentel" "\n\t" + "mrs x11 , spsel" "\n\t" + "isb" "\n\t" + "mov %[flags], xzr" "\n\t" + "orr %[flags], x14, x13" "\n\t" + "orr %[flags], %[flags], x12" "\n\t" + "orr %[flags], %[flags], x11" + : [sctlr] "=r" (Core->SystemRegister.SCTLR), + [mmfr1] "=r" (mmfr1), + [pfr0] "=r" (pfr0), + [fpsr] "=r" (Core->SystemRegister.FPSR), + [flags] "=r" (Core->SystemRegister.FLAGS) + : + : "cc", "memory", "%x11", "%x12", "%x13", "%x14" + ); + if (mmfr1.VH) { + BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->VM, Core->Bind); + } else { + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->VM, Core->Bind); + } + Core->Query.SCTLRX = 0; + if (Experimental) { + volatile AA64MMFR3 mmfr3 = {.value = SysRegRead(ID_AA64MMFR3_EL1)}; + if ((Core->Query.SCTLRX = mmfr3.SCTLRX) == 0b0001) { + Core->SystemRegister.SCTLR2 = SysRegRead(SCTLR2_EL1); + } + } + if (PUBLIC(RO(Proc))->Features.DIT) { + Core->SystemRegister.FLAGS |= ( + SysRegRead(MRS_DIT) & (1LLU << FLAG_DIT) + ); + } + if (isar2.CLRBHB == 0b0001) { + BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->CLRBHB, Core->Bind); + } else { + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CLRBHB, Core->Bind); + } + switch (pfr0.EL3) { + case 0b0010: + BITSET(LOCKLESS, Core->SystemRegister.EL, EL3_32); + fallthrough; + case 0b0001: + BITSET(LOCKLESS, Core->SystemRegister.EL, EL3_64); + break; + } + switch (pfr0.EL2) { + case 0b0010: + BITSET(LOCKLESS, Core->SystemRegister.EL, EL2_32); + fallthrough; + case 0b0001: + BITSET(LOCKLESS, Core->SystemRegister.EL, EL2_64); + break; + } + switch (pfr0.SEL2) { + case 0b0001: + BITSET(LOCKLESS, Core->SystemRegister.EL, EL2_SEC); + break; + } + switch (pfr0.EL1) { + case 0b0010: + BITSET(LOCKLESS, Core->SystemRegister.EL, EL1_32); + fallthrough; + case 0b0001: + BITSET(LOCKLESS, Core->SystemRegister.EL, EL1_64); + break; + } + switch (pfr0.EL0) { + case 0b0010: + BITSET(LOCKLESS, Core->SystemRegister.EL, EL0_32); + fallthrough; + case 0b0001: + BITSET(LOCKLESS, Core->SystemRegister.EL, EL0_64); + break; + } + switch (pfr0.CSV2) { + case 0b0001: + BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_1, Core->Bind); + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_2, Core->Bind); + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_3, Core->Bind); + break; + case 0b0010: + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_1, Core->Bind); + BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_2, Core->Bind); + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_3, Core->Bind); + break; + case 0b0011: + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_1, Core->Bind); + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_2, Core->Bind); + BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_3, Core->Bind); + break; + default: + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_1, Core->Bind); + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_2, Core->Bind); + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_3, Core->Bind); + } + if (pfr0.CSV3) { + BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV3, Core->Bind); + } else { + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV3, Core->Bind); + } + if (PUBLIC(RO(Proc))->Features.SSBS == 0b0010) + { + SSBS2 mrs_ssbs = {.value = SysRegRead(MRS_SSBS2)}; + + if (mrs_ssbs.SSBS) { + BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->SSBS, Core->Bind); + } else { + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->SSBS, Core->Bind); + } + Core->SystemRegister.FLAGS |= (1LLU << FLAG_SSBS); + } + if (PUBLIC(RO(Proc))->Features.PAN) { + Core->SystemRegister.FLAGS |= ( + SysRegRead(MRS_PAN) & (1LLU << FLAG_PAN) + ); + } + if (PUBLIC(RO(Proc))->Features.UAO) { + Core->SystemRegister.FLAGS |= ( + SysRegRead(MRS_UAO) & (1LLU << FLAG_UAO) + ); + } + if (PUBLIC(RO(Proc))->Features.MTE) { + Core->SystemRegister.FLAGS |= ( + SysRegRead(MRS_TCO) & (1LLU << FLAG_TCO) + ); + } + if (PUBLIC(RO(Proc))->Features.NMI) { + Core->SystemRegister.FLAGS |= ( + SysRegRead(MRS_ALLINT) & (1LLU << FLAG_NMI) + ); + } + if (PUBLIC(RO(Proc))->Features.EBEP) { + Core->SystemRegister.FLAGS |= ( + SysRegRead(MRS_PM) & (1LLU << FLAG_PM) + ); + } + if (PUBLIC(RO(Proc))->Features.SME) { + Core->SystemRegister.SVCR = SysRegRead(MRS_SVCR); + } + BITSET_CC(LOCKLESS, PUBLIC(RO(Proc))->CR_Mask, Core->Bind); +} + +#define Pkg_Reset_ThermalPoint(Pkg) \ +({ \ + BITWISECLR(LOCKLESS, Pkg->ThermalPoint.Mask); \ + BITWISECLR(LOCKLESS, Pkg->ThermalPoint.Kind); \ + BITWISECLR(LOCKLESS, Pkg->ThermalPoint.State); \ +}) + +static void PerCore_Reset(CORE_RO *Core) +{ + BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->HWP_Mask , Core->Bind); + BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->CR_Mask , Core->Bind); + + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->HWP , Core->Bind); + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_1 , Core->Bind); + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_2 , Core->Bind); + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_3 , Core->Bind); + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV3 , Core->Bind); + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->SSBS , Core->Bind); + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->VM , Core->Bind); + + BITWISECLR(LOCKLESS, Core->ThermalPoint.Mask); + BITWISECLR(LOCKLESS, Core->ThermalPoint.Kind); + BITWISECLR(LOCKLESS, Core->ThermalPoint.State); +} + +static void PerCore_GenericMachine(void *arg) +{ + volatile CPUPWRCTLR cpuPwrCtl; + volatile REVIDR revid; + CORE_RO *Core = (CORE_RO *) arg; + + Query_DeviceTree(Core->Bind); + + if (PUBLIC(RO(Proc))->Features.Hybrid) { + Core->T.Cluster.Hybrid_ID = \ + Core->Boost[BOOST(MAX)] < PUBLIC(RO(Proc))->Features.Factory.Ratio ? + Hybrid_Secondary : Hybrid_Primary; + } + if (Experimental && (PUBLIC(RO(Proc))->HypervisorID == BARE_METAL)) { + cpuPwrCtl.value = SysRegRead(CPUPWRCTLR_EL1); + Core->Query.CStateBaseAddr = cpuPwrCtl.WFI_RET_CTRL; + } + if (Core->Bind == PUBLIC(RO(Proc))->Service.Core) { + volatile PMUSERENR pmuser; + + __asm__ __volatile__( + "mrs %[pmuser], pmuserenr_el0" "\n\t" + "isb" + : [pmuser] "=r" (pmuser) + : + : "memory" + ); + PUBLIC(RO(Proc))->Features.PerfMon.CoreCycles = pmuser.CR; + PUBLIC(RO(Proc))->Features.PerfMon.InstrRetired = pmuser.IR; + + } + __asm__ __volatile__( + "mrs %[revid], revidr_el1" "\n\t" + "isb" + : [revid] "=r" (revid) + : + : "memory" + ); + Core->Query.Revision = revid.Revision; + + SystemRegisters(Core); + + BITSET_CC(LOCKLESS, PUBLIC(RO(Proc))->SPEC_CTRL_Mask, Core->Bind); +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 56) +inline void Sys_DumpTask(SYSGATE_RO *SysGate) +{ + SysGate->taskCount = 0; +} +#else /* KERNEL_VERSION(3, 10, 56) */ +static void Sys_DumpTask(SYSGATE_RO *SysGate) +{ /* Source: /include/linux/sched.h */ + struct task_struct *process, *thread; + int cnt = 0; + + rcu_read_lock(); + for_each_process_thread(process, thread) { + if (cnt < TASK_LIMIT) { +#if defined(CONFIG_SCHED_MUQSS) \ + || defined(CONFIG_SCHED_BMQ) \ + || defined(CONFIG_SCHED_PDS) + SysGate->taskList[cnt].runtime = tsk_seruntime(thread); +#else + SysGate->taskList[cnt].runtime = thread->se.sum_exec_runtime; +#endif /* CONFIG_SCHED_* */ + SysGate->taskList[cnt].usertime = thread->utime; + SysGate->taskList[cnt].systime = thread->stime; + SysGate->taskList[cnt].pid = thread->pid; + SysGate->taskList[cnt].tgid = thread->tgid; + SysGate->taskList[cnt].ppid = thread->parent->pid; +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 14, 0) + SysGate->taskList[cnt].state = (short int) thread->state; +#else + SysGate->taskList[cnt].state = (short int) thread->__state; +#endif +#if defined(CONFIG_SCHED_ALT) + SysGate->taskList[cnt].wake_cpu = (short int) task_cpu(thread); +#elif defined(CONFIG_SCHED_BMQ) || defined(CONFIG_SCHED_PDS) + SysGate->taskList[cnt].wake_cpu = (short int) thread->cpu; +#else + SysGate->taskList[cnt].wake_cpu = (short int) thread->wake_cpu; +#endif /* CONFIG_SCHED_BMQ */ + memcpy(SysGate->taskList[cnt].comm, thread->comm,TASK_COMM_LEN); + + cnt++; + } + } + rcu_read_unlock(); + SysGate->taskCount = cnt; +} +#endif /* KERNEL_VERSION(3, 10, 56) */ + +#define Sys_Tick(Pkg, ...) \ +({ \ + if (PUBLIC(OF(Gate)) != NULL) \ + { \ + Pkg->tickStep--; \ + if (!Pkg->tickStep) { \ + Pkg->tickStep = Pkg->tickReset ; \ + Sys_DumpTask( PUBLIC(OF(Gate)) ); \ + __VA_ARGS__ \ + } \ + } \ +}) + +static void InitTimer(void *Cycle_Function) +{ + unsigned int cpu = smp_processor_id(); + + if (BITVAL(PRIVATE(OF(Core, AT(cpu)))->Join.TSM, CREATED) == 0) + { + hrtimer_init( &PRIVATE(OF(Core, AT(cpu)))->Join.Timer, + CLOCK_MONOTONIC, + HRTIMER_MODE_REL_PINNED); + + PRIVATE(OF(Core, AT(cpu)))->Join.Timer.function = Cycle_Function; + BITSET(LOCKLESS, PRIVATE(OF(Core, AT(cpu)))->Join.TSM, CREATED); + } +} + +static void Controller_Init(void) +{ + CLOCK sClock = {.Q = 0, .R = 0, .Hz = 0}; + unsigned int cpu = PUBLIC(RO(Proc))->CPU.Count, ratio = 0; + + Package_Init_Reset(); + + if (Arch[PUBLIC(RO(Proc))->ArchID].Query != NULL) + { + Arch[PUBLIC(RO(Proc))->ArchID].Query(PUBLIC(RO(Proc))->Service.Core); + } + + ratio=PUBLIC(RO(Core,AT(PUBLIC(RO(Proc))->Service.Core)))->Boost[BOOST(MAX)]; + + if (Arch[PUBLIC(RO(Proc))->ArchID].BaseClock != NULL) + { + sClock = Arch[PUBLIC(RO(Proc))->ArchID].BaseClock(ratio); + } + if (sClock.Hz == 0) { /* Fallback to 100 MHz */ + sClock.Q = 100; + sClock.R = 0; + sClock.Hz = 100000000LLU; + } + ratio = FixMissingRatioAndFrequency(ratio, &sClock); + + if ((AutoClock & 0b01) || PUBLIC(RO(Proc))->Features.Hyperv) + { + CLOCK vClock = {.Q = 0, .R =0, .Hz = 0}; + COMPUTE_ARG Compute; + struct kmem_cache *hwCache = NULL; + /* Allocate Cache aligned resources. */ + hwCache = kmem_cache_create( "CoreFreqCache", + STRUCT_SIZE, 0, + SLAB_HWCACHE_ALIGN, NULL); + if (hwCache != NULL) + { + do { /* from last AP to BSP */ + cpu--; + + if (!BITVAL(PUBLIC(RO(Core, AT(cpu)))->OffLine, OS)) + { + Compute.TSC[0] = kmem_cache_alloc(hwCache, GFP_ATOMIC); + if (Compute.TSC[0] != NULL) + { + Compute.TSC[1] = kmem_cache_alloc(hwCache, GFP_ATOMIC); + if (Compute.TSC[1] != NULL) + { + if (ratio != 0) + { + Compute.Clock.Q = ratio; + Compute.Clock.R = 0; + Compute.Clock.Hz = 0; + + PUBLIC(RO(Core, AT(cpu)))->Clock = Compute_Clock(cpu,&Compute); + + PUBLIC(RO(Core, AT(cpu)))->Boost[BOOST(MAX)] = ratio; + } + else + { + vClock.Q = 0; vClock.R = 0; vClock.Hz = 0; + Compute.Clock.Q = sClock.Q; + Compute.Clock.R = 0; + Compute.Clock.Hz = 0; + + vClock = Compute_Clock(cpu, &Compute); + + PUBLIC(RO(Core, AT(cpu)))->Boost[BOOST(MAX)] = vClock.Q; + } + /* Release memory resources. */ + kmem_cache_free(hwCache, Compute.TSC[1]); + } + kmem_cache_free(hwCache, Compute.TSC[0]); + } + } + } while (cpu != 0) ; + + kmem_cache_destroy(hwCache); + } + if ((ratio == 0) && (vClock.Hz != 0)) { + ratio = FixMissingRatioAndFrequency(vClock.Q, &sClock); + } + } + /* Launch a high resolution timer per online CPU. */ + for (cpu = 0; cpu < PUBLIC(RO(Proc))->CPU.Count; cpu++) + { + if (!BITVAL(PUBLIC(RO(Core, AT(cpu)))->OffLine, OS)) { + if (!PUBLIC(RO(Core, AT(cpu)))->Clock.Hz) + { + PUBLIC(RO(Core, AT(cpu)))->Clock = sClock; + } + if (Arch[PUBLIC(RO(Proc))->ArchID].Timer != NULL) + { + Arch[PUBLIC(RO(Proc))->ArchID].Timer(cpu); + } + } + } +} + +static void Controller_Start(int wait) +{ + if (Arch[PUBLIC(RO(Proc))->ArchID].Start != NULL) + { + unsigned int cpu; + for (cpu = 0; cpu < PUBLIC(RO(Proc))->CPU.Count; cpu++) + { + if ((BITVAL(PRIVATE(OF(Core, AT(cpu)))->Join.TSM, CREATED) == 1) + && (BITVAL(PRIVATE(OF(Core, AT(cpu)))->Join.TSM, STARTED) == 0)) + { + smp_call_function_single(cpu, + Arch[PUBLIC(RO(Proc))->ArchID].Start, + NULL, wait); + } + } + } +} + +static void Controller_Stop(int wait) +{ + if (Arch[PUBLIC(RO(Proc))->ArchID].Stop != NULL) + { + unsigned int cpu; + for (cpu = 0; cpu < PUBLIC(RO(Proc))->CPU.Count; cpu++) + if ((BITVAL(PRIVATE(OF(Core, AT(cpu)))->Join.TSM, CREATED) == 1) + && (BITVAL(PRIVATE(OF(Core, AT(cpu)))->Join.TSM, STARTED) == 1)) + { + smp_call_function_single(cpu, + Arch[PUBLIC(RO(Proc))->ArchID].Stop, + NULL, wait); + } + } +} + +static void Controller_Exit(void) +{ + unsigned int cpu; + + if (Arch[PUBLIC(RO(Proc))->ArchID].Exit != NULL) + { + Arch[PUBLIC(RO(Proc))->ArchID].Exit(); + } + for (cpu = 0; cpu < PUBLIC(RO(Proc))->CPU.Count; cpu++) + { + BITCLR(LOCKLESS, PRIVATE(OF(Core, AT(cpu)))->Join.TSM, CREATED); + } +} + +static void Generic_Core_Counters_Set(union SAVE_AREA_CORE *Save, CORE_RO *Core) +{ + __asm__ __volatile__ + ( + "# Assign an event number per counter" "\n\t" + "mrs x12 , pmselr_el0" "\n\t" + "str x12 , %[PMSELR]" "\n\t" + "orr x12 , x12, #3" "\n\t" + "msr pmselr_el0, x12" "\n\t" + + "# Choosen [EVENT#] to collect from" "\n\t" + "mrs x12 , pmxevtyper_el0" "\n\t" + "str x12 , %[PMTYPE3]" "\n\t" + "orr x12 , x12, %[EVENT3]" "\n\t" + "msr pmxevtyper_el0, x12" "\n\t" + + "ldr x12 , %[PMSELR]" "\n\t" + "orr x12 , x12, #2" "\n\t" + "msr pmselr_el0, x12" "\n\t" + "mrs x12 , pmxevtyper_el0" "\n\t" + "str x12 , %[PMTYPE2]" "\n\t" + "orr x12 , x12, %[EVENT2]" "\n\t" + "msr pmxevtyper_el0, x12" "\n\t" + + "ldr x12 , %[PMSELR]" "\n\t" + "orr x12 , x12, #0b11111" "\n\t" + "msr pmselr_el0, x12" "\n\t" + "mrs x12 , pmxevtyper_el0" "\n\t" + "str x12 , %[PMTYPE1]" "\n\t" + "orr x12 , x12, %[FILTR1]" "\n\t" + "msr pmxevtyper_el0, x12" "\n\t" + + "# No filtered EL within Cycle counter" "\n\t" + "mrs x12 , pmccfiltr_el0" "\n\t" + "str x12 , %[PMCCFILTR]" "\n\t" + "msr pmccfiltr_el0, xzr" "\n\t" + + "# Enable counters at position [ENSET]" "\n\t" + "mrs x12 , pmcntenset_el0" "\n\t" + "str x12 , %[PMCNTEN]" "\n\t" + "orr x12 , x12, %[ENSET]" "\n\t" + "msr pmcntenset_el0, x12" "\n\t" + + "# Enable all PMU counters" "\n\t" + "mrs x12 , pmcr_el0" "\n\t" + "str x12 , %[PMCR]" "\n\t" + "mov x12 , %[CTRL]" "\n\t" + "msr pmcr_el0, x12" "\n\t" + "isb" + : [PMCR] "+m" (Save->PMCR), + [PMSELR] "+m" (Save->PMSELR), + [PMTYPE3] "+m" (Save->PMTYPE[2]), + [PMTYPE2] "+m" (Save->PMTYPE[1]), + [PMTYPE1] "+m" (Save->PMTYPE[0]), + [PMCCFILTR] "+m" (Save->PMCCFILTR), + [PMCNTEN] "+m" (Save->PMCNTEN) + : [EVENT3] "r" (0x0008), + [EVENT2] "r" (0x0011), + [FILTR1] "r" (0x0), + [ENSET] "r" (0b10000000000000000000000000001100), + [CTRL] "i" (0b0000000010000111) + : "memory", "%x12" + ); +} + +static void Generic_Core_Counters_Clear(union SAVE_AREA_CORE *Save, + CORE_RO *Core) +{ + __asm__ __volatile__( + "# Restore PMU configuration registers" "\n\t" + "ldr x12 , %[PMCR]" "\n\t" + "msr pmcr_el0, x12" "\n\t" + + "ldr x12 , %[PMCNTEN]" "\n\t" + "msr pmcntenset_el0, x12" "\n\t" + + "ldr x12 , %[PMCCFILTR]" "\n\t" + "msr pmccfiltr_el0, x12" "\n\t" + + "ldr x12 , %[PMSELR]" "\n\t" + "orr x12 , x12, #0b11111" "\n\t" + "msr pmselr_el0, x12" "\n\t" + "ldr x12 , %[PMTYPE1]" "\n\t" + "msr pmxevtyper_el0, x12" "\n\t" + + "ldr x12 , %[PMSELR]" "\n\t" + "orr x12 , x12, #2" "\n\t" + "msr pmselr_el0, x12" "\n\t" + "ldr x12 , %[PMTYPE2]" "\n\t" + "msr pmxevtyper_el0, x12" "\n\t" + + "ldr x12 , %[PMSELR]" "\n\t" + "orr x12 , x12, #3" "\n\t" + "msr pmselr_el0, x12" "\n\t" + "ldr x12 , %[PMTYPE3]" "\n\t" + "msr pmxevtyper_el0, x12" "\n\t" + + "ldr x12 , %[PMSELR]" "\n\t" + "msr pmselr_el0, x12" "\n\t" + + "isb" + : + : [PMCR] "m" (Save->PMCR), + [PMSELR] "m" (Save->PMSELR), + [PMTYPE3] "m" (Save->PMTYPE[2]), + [PMTYPE2] "m" (Save->PMTYPE[1]), + [PMTYPE1] "m" (Save->PMTYPE[0]), + [PMCCFILTR] "m" (Save->PMCCFILTR), + [PMCNTEN] "m" (Save->PMCNTEN) + : "memory", "%x12" + ); +} + +#define Counters_Generic(Core, T) \ +({ \ + RDTSC_COUNTERx3(Core->Counter[T].TSC, \ + pmevcntr2_el0, Core->Counter[T].C0.UCC, \ + pmccntr_el0, Core->Counter[T].C0.URC, \ + pmevcntr3_el0, Core->Counter[T].INST ); \ + /* Normalize frequency: */ \ + Core->Counter[T].C1 = ( \ + Core->Counter[T].TSC \ + * PUBLIC(RO(Proc))->Features.Factory.Clock.Q \ + * Core->Boost[BOOST(MAX)] \ + ) / PUBLIC(RO(Proc))->Features.Factory.Ratio; \ + /* Derive C1: */ \ + Core->Counter[T].C1 = \ + (Core->Counter[T].C1 > Core->Counter[T].C0.URC) ? \ + Core->Counter[T].C1 - Core->Counter[T].C0.URC : 0; \ +}) + +#define Mark_OVH(Core) \ +({ \ + RDTSC64(Core->Overhead.TSC); \ +}) + +#define Core_OVH(Core) \ +({ \ + Core->Delta.TSC -= (Core->Counter[1].TSC - Core->Overhead.TSC); \ +}) + +#define Delta_TSC(Core) \ +({ \ + Core->Delta.TSC = Core->Counter[1].TSC \ + - Core->Counter[0].TSC; \ +}) + +#define Delta_TSC_OVH(Core) \ +({ \ + Delta_TSC(Core); \ + \ + if (AutoClock & 0b10) { \ + Core_OVH(Core); \ + \ + REL_BCLK(Core->Clock, \ + (PUBLIC(RO(Proc))->Features.Hybrid == 1 ? \ + PUBLIC(RO(Proc))->Features.Factory.Ratio\ + : Core->Boost[BOOST(MAX)]), \ + Core->Delta.TSC, \ + PUBLIC(RO(Proc))->SleepInterval); \ + } \ +}) + +#define Delta_C0(Core) \ +({ /* Absolute Delta of Unhalted (Core & Ref) C0 Counter. */ \ + Core->Delta.C0.UCC = ( \ + Core->Counter[0].C0.UCC > Core->Counter[1].C0.UCC \ + ) ? Core->Counter[0].C0.UCC - Core->Counter[1].C0.UCC \ + : Core->Counter[1].C0.UCC - Core->Counter[0].C0.UCC; \ + \ + Core->Delta.C0.URC = ( \ + Core->Counter[0].C0.URC > Core->Counter[1].C0.URC \ + ) ? Core->Counter[0].C0.URC - Core->Counter[1].C0.URC \ + : Core->Counter[1].C0.URC - Core->Counter[0].C0.URC; \ +}) + +#define Delta_C1(Core) \ +({ \ + Core->Delta.C1 = (Core->Counter[0].C1 > Core->Counter[1].C1) ? \ + Core->Counter[0].C1 - Core->Counter[1].C1 \ + : Core->Counter[1].C1 - Core->Counter[0].C1; \ +}) + +#define Delta_C3(Core) \ +({ \ + Core->Delta.C3 = Core->Counter[1].C3 \ + - Core->Counter[0].C3; \ +}) + +#define Delta_C6(Core) \ +({ \ + Core->Delta.C6 = Core->Counter[1].C6 \ + - Core->Counter[0].C6; \ +}) + +#define Delta_C7(Core) \ +({ \ + Core->Delta.C7 = Core->Counter[1].C7 \ + - Core->Counter[0].C7; \ +}) + +#define Delta_INST(Core) \ +({ /* Delta of Retired Instructions */ \ + Core->Delta.INST = ( \ + Core->Counter[0].INST > Core->Counter[1].INST \ + ) ? Core->Counter[0].INST - Core->Counter[1].INST \ + : Core->Counter[1].INST - Core->Counter[0].INST; \ +}) + +#define PKG_Counters_Generic(Core, T) \ +({ \ + volatile CNTPCT cntpct; \ + __asm__ volatile \ + ( \ + "mrs %[cntpct], cntpct_el0" \ + : [cntpct] "=r" (cntpct) \ + : \ + : "cc", "memory" \ + ); \ + PUBLIC(RO(Proc))->Counter[T].PCLK = cntpct.PhysicalCount; \ +}) + +#define Pkg_OVH(Pkg, Core) \ +({ \ + Pkg->Delta.PCLK -= (Pkg->Counter[1].PCLK - Core->Overhead.TSC); \ +}) + +#define Delta_PTSC(Pkg) \ +({ \ + Pkg->Delta.PCLK = Pkg->Counter[1].PCLK \ + - Pkg->Counter[0].PCLK; \ +}) + +#define Delta_PTSC_OVH(Pkg, Core) \ +({ \ + Delta_PTSC(Pkg); \ + \ + if (AutoClock & 0b10) \ + Pkg_OVH(Pkg, Core); \ +}) + +#define Delta_PC02(Pkg) \ +({ \ + Pkg->Delta.PC02 = Pkg->Counter[1].PC02 \ + - Pkg->Counter[0].PC02; \ +}) + +#define Delta_PC03(Pkg) \ +({ \ + Pkg->Delta.PC03 = Pkg->Counter[1].PC03 \ + - Pkg->Counter[0].PC03; \ +}) + +#define Delta_PC04(Pkg) \ +({ \ + Pkg->Delta.PC04 = Pkg->Counter[1].PC04 \ + - Pkg->Counter[0].PC04; \ +}) + +#define Delta_PC06(Pkg) \ +({ \ + Pkg->Delta.PC06 = Pkg->Counter[1].PC06 \ + - Pkg->Counter[0].PC06; \ +}) + +#define Delta_PC07(Pkg) \ +({ \ + Pkg->Delta.PC07 = Pkg->Counter[1].PC07 \ + - Pkg->Counter[0].PC07; \ +}) + +#define Delta_PC08(Pkg) \ +({ \ + Pkg->Delta.PC08 = Pkg->Counter[1].PC08 \ + - Pkg->Counter[0].PC08; \ +}) + +#define Delta_PC09(Pkg) \ +({ \ + Pkg->Delta.PC09 = Pkg->Counter[1].PC09 \ + - Pkg->Counter[0].PC09; \ +}) + +#define Delta_PC10(Pkg) \ +({ \ + Pkg->Delta.PC10 = Pkg->Counter[1].PC10 \ + - Pkg->Counter[0].PC10; \ +}) + +#define Delta_MC6(Pkg) \ +({ \ + Pkg->Delta.MC6 = Pkg->Counter[1].MC6 \ + - Pkg->Counter[0].MC6; \ +}) + +#define Delta_UNCORE_FC0(Pkg) \ +({ \ + Pkg->Delta.Uncore.FC0 = \ + (Pkg->Counter[0].Uncore.FC0 > \ + Pkg->Counter[1].Uncore.FC0) ? \ + Pkg->Counter[0].Uncore.FC0 \ + - Pkg->Counter[1].Uncore.FC0 \ + : Pkg->Counter[1].Uncore.FC0 \ + - Pkg->Counter[0].Uncore.FC0; \ +}) + +#define Save_TSC(Core) \ +({ /* Save Time Stamp Counter. */ \ + Core->Counter[0].TSC = Core->Counter[1].TSC; \ +}) + +#define Save_C0(Core) \ +({ /* Save the Unhalted Core & Reference Counter */ \ + Core->Counter[0].C0.UCC = Core->Counter[1].C0.UCC; \ + Core->Counter[0].C0.URC = Core->Counter[1].C0.URC; \ +}) + +#define Save_C1(Core) \ +({ \ + Core->Counter[0].C1 = Core->Counter[1].C1; \ +}) + +#define Save_C3(Core) \ +({ \ + Core->Counter[0].C3 = Core->Counter[1].C3; \ +}) + +#define Save_C6(Core) \ +({ \ + Core->Counter[0].C6 = Core->Counter[1].C6; \ +}) + +#define Save_C7(Core) \ +({ \ + Core->Counter[0].C7 = Core->Counter[1].C7; \ +}) + +#define Save_INST(Core) \ +({ /* Save the Instructions counter. */ \ + Core->Counter[0].INST = Core->Counter[1].INST; \ +}) + +#define Save_PTSC(Pkg) \ +({ \ + Pkg->Counter[0].PCLK = Pkg->Counter[1].PCLK; \ +}) + +#define Save_PC02(Pkg) \ +({ \ + Pkg->Counter[0].PC02 = Pkg->Counter[1].PC02; \ +}) + +#define Save_PC03(Pkg) \ +({ \ + Pkg->Counter[0].PC03 = Pkg->Counter[1].PC03; \ +}) + +#define Save_PC04(Pkg) \ +({ \ + Pkg->Counter[0].PC04 = Pkg->Counter[1].PC04; \ +}) + +#define Save_PC06(Pkg) \ +({ \ + Pkg->Counter[0].PC06 = Pkg->Counter[1].PC06; \ +}) + +#define Save_PC07(Pkg) \ +({ \ + Pkg->Counter[0].PC07 = Pkg->Counter[1].PC07; \ +}) + +#define Save_PC08(Pkg) \ +({ \ + Pkg->Counter[0].PC08 = Pkg->Counter[1].PC08; \ +}) + +#define Save_PC09(Pkg) \ +({ \ + Pkg->Counter[0].PC09 = Pkg->Counter[1].PC09; \ +}) + +#define Save_PC10(Pkg) \ +({ \ + Pkg->Counter[0].PC10 = Pkg->Counter[1].PC10; \ +}) + +#define Save_MC6(Pkg) \ +({ \ + Pkg->Counter[0].MC6 = Pkg->Counter[1].MC6; \ +}) + +#define Save_UNCORE_FC0(Pkg) \ +({ \ + Pkg->Counter[0].Uncore.FC0 = Pkg->Counter[1].Uncore.FC0; \ +}) + +#ifdef CONFIG_CPU_FREQ +inline COF_UNION Compute_COF_From_CPU_Freq(struct cpufreq_policy *pFreqPolicy) +{ + register unsigned long long Q = pFreqPolicy->cur, + D = UNIT_KHz(PRECISION); + COF_UNION ratio = {.COF = { + .Q = Q / D, + .R = (Q - (ratio.COF.Q * D)) / PRECISION } + }; + return ratio; +} +#endif /* CONFIG_CPU_FREQ */ + +inline COF_UNION Compute_COF_From_PMU_Counter( unsigned long long cnt, + CLOCK clk, + unsigned int limit ) +{ + register unsigned long long \ + Q = cnt * clk.Q, + D = UNIT_MHz(10LLU * PUBLIC(RO(Proc))->SleepInterval); + + COF_UNION ratio = {.COF = { + .Q = Q / D } + }; + if (ratio.COF.Q < limit) { + ratio.Perf = limit; + } else { + ratio.COF.R = (Q - (ratio.COF.Q * D)) / UNIT_MHz(10LLU); + } + return ratio; +} + +static enum hrtimer_restart Cycle_GenericMachine(struct hrtimer *pTimer) +{ + CORE_RO *Core; + #ifdef CONFIG_CPU_FREQ + struct cpufreq_policy *pFreqPolicy; + #endif + const unsigned int cpu = smp_processor_id(); + Core = (CORE_RO *) PUBLIC(RO(Core, AT(cpu))); + + RDTSC64(Core->Overhead.TSC); + + if (BITVAL(PRIVATE(OF(Core, AT(cpu)))->Join.TSM, MUSTFWD) == 1) + { + hrtimer_forward(pTimer, + hrtimer_cb_get_time(pTimer), + RearmTheTimer); + + Counters_Generic(Core, 1); + + if (Core->Bind == PUBLIC(RO(Proc))->Service.Core) + { + PKG_Counters_Generic(Core, 1); + + Delta_PTSC_OVH(PUBLIC(RO(Proc)), Core); + + Save_PTSC(PUBLIC(RO(Proc))); + + Sys_Tick(PUBLIC(RO(Proc))); + } + + Delta_INST(Core); + + Delta_C0(Core); + + Delta_TSC_OVH(Core); + + Delta_C1(Core); + + Save_INST(Core); + + Save_TSC(Core); + + Save_C0(Core); + + Save_C1(Core); + + #ifdef CONFIG_CPU_FREQ + pFreqPolicy = &PRIVATE(OF(Core, AT(cpu)))->FreqPolicy; + if (cpufreq_get_policy(pFreqPolicy, cpu) == 0) + { + Core->Ratio = Compute_COF_From_CPU_Freq(pFreqPolicy); + } + else + { + Core->Ratio = Compute_COF_From_PMU_Counter(Core->Delta.C0.URC, + Core->Clock, + Core->Boost[BOOST(MIN)]); + } + #else + Core->Ratio = Compute_COF_From_PMU_Counter(Core->Delta.C0.URC, + Core->Clock, + Core->Boost[BOOST(MIN)]); + #endif + PUBLIC(RO(Core, AT(cpu)))->Boost[BOOST(TGT)] = Core->Ratio.COF.Q; + + BITSET(LOCKLESS, PUBLIC(RW(Core, AT(cpu)))->Sync.V, NTFY); + + return HRTIMER_RESTART; + } else + return HRTIMER_NORESTART; +} + +static void InitTimer_GenericMachine(unsigned int cpu) +{ + smp_call_function_single(cpu, InitTimer, Cycle_GenericMachine, 1); +} + +static void Start_GenericMachine(void *arg) +{ + unsigned int cpu = smp_processor_id(); + CORE_RO *Core = (CORE_RO *) PUBLIC(RO(Core, AT(cpu))); + union SAVE_AREA_CORE *Save = &PRIVATE(OF(Core, AT(cpu)))->SaveArea; + UNUSED(arg); + + if (Arch[PUBLIC(RO(Proc))->ArchID].Update != NULL) { + Arch[PUBLIC(RO(Proc))->ArchID].Update(Core); + } + + Generic_Core_Counters_Set(Save, Core); + + Counters_Generic(Core, 0); + + if (Core->Bind == PUBLIC(RO(Proc))->Service.Core) { + if (Arch[PUBLIC(RO(Proc))->ArchID].Uncore.Start != NULL) { + Arch[PUBLIC(RO(Proc))->ArchID].Uncore.Start(NULL); + } + PKG_Counters_Generic(Core, 0); + } + + BITSET(LOCKLESS, PRIVATE(OF(Core, AT(cpu)))->Join.TSM, MUSTFWD); + + hrtimer_start( &PRIVATE(OF(Core, AT(cpu)))->Join.Timer, + RearmTheTimer, + HRTIMER_MODE_REL_PINNED); + + BITSET(LOCKLESS, PRIVATE(OF(Core, AT(cpu)))->Join.TSM, STARTED); +} + +static void Stop_GenericMachine(void *arg) +{ + unsigned int cpu = smp_processor_id(); + CORE_RO *Core = (CORE_RO *) PUBLIC(RO(Core, AT(cpu))); + union SAVE_AREA_CORE *Save = &PRIVATE(OF(Core, AT(cpu)))->SaveArea; + UNUSED(arg); + + BITCLR(LOCKLESS, PRIVATE(OF(Core, AT(cpu)))->Join.TSM, MUSTFWD); + + hrtimer_cancel(&PRIVATE(OF(Core, AT(cpu)))->Join.Timer); + + Generic_Core_Counters_Clear(Save, Core); + + if (Core->Bind == PUBLIC(RO(Proc))->Service.Core) { + if (Arch[PUBLIC(RO(Proc))->ArchID].Uncore.Stop != NULL) { + Arch[PUBLIC(RO(Proc))->ArchID].Uncore.Stop(NULL); + } + Pkg_Reset_ThermalPoint(PUBLIC(RO(Proc))); + } + PerCore_Reset(Core); + + BITCLR(LOCKLESS, PRIVATE(OF(Core, AT(cpu)))->Join.TSM, STARTED); +} + +static long Sys_OS_Driver_Query(void) +{ + int rc = RC_SUCCESS; +#ifdef CONFIG_CPU_FREQ + const char *pFreqDriver; + struct cpufreq_policy *pFreqPolicy = \ + &PRIVATE(OF(Core, AT(PUBLIC(RO(Proc))->Service.Core)))->FreqPolicy; +#endif /* CONFIG_CPU_FREQ */ +#ifdef CONFIG_CPU_IDLE + struct cpuidle_driver *pIdleDriver; +#endif /* CONFIG_CPU_IDLE */ + memset(&PUBLIC(RO(Proc))->OS, 0, sizeof(OS_DRIVER)); +#ifdef CONFIG_CPU_IDLE + if ((pIdleDriver = cpuidle_get_driver()) != NULL) + { + int idx; + + StrCopy(PUBLIC(RO(Proc))->OS.IdleDriver.Name, + pIdleDriver->name, + CPUIDLE_NAME_LEN); + + if (pIdleDriver->state_count < CPUIDLE_STATE_MAX) { + PUBLIC(RO(Proc))->OS.IdleDriver.stateCount = pIdleDriver->state_count; + } else { + PUBLIC(RO(Proc))->OS.IdleDriver.stateCount = CPUIDLE_STATE_MAX; + } + PUBLIC(RO(Proc))->OS.IdleDriver.stateLimit = pIdleDriver->state_count; + + for (idx = 0; idx < PUBLIC(RO(Proc))->OS.IdleDriver.stateCount; idx++) + { + StrCopy(PUBLIC(RO(Proc))->OS.IdleDriver.State[idx].Name, + pIdleDriver->states[idx].name, CPUIDLE_NAME_LEN); + + StrCopy(PUBLIC(RO(Proc))->OS.IdleDriver.State[idx].Desc, + pIdleDriver->states[idx].desc, CPUIDLE_NAME_LEN); + + PUBLIC(RO(Proc))->OS.IdleDriver.State[idx].exitLatency = \ + pIdleDriver->states[idx].exit_latency; + + PUBLIC(RO(Proc))->OS.IdleDriver.State[idx].powerUsage = \ + pIdleDriver->states[idx].power_usage; + + PUBLIC(RO(Proc))->OS.IdleDriver.State[idx].targetResidency = \ + pIdleDriver->states[idx].target_residency; + } + if(PUBLIC(RO(Proc))->Registration.Driver.CPUidle == REGISTRATION_ENABLE) + { + for (idx = SUB_CSTATE_COUNT - 1; idx >= 0 ; idx--) + { + if (CoreFreqK.SubCstate[idx] > 0) + { + PUBLIC(RO(Proc))->OS.IdleDriver.stateLimit = 1 + idx; + break; + } + } + } + } +#endif /* CONFIG_CPU_IDLE */ +#ifdef CONFIG_CPU_FREQ + if ((pFreqDriver = cpufreq_get_current_driver()) != NULL) { + StrCopy(PUBLIC(RO(Proc))->OS.FreqDriver.Name, + pFreqDriver, CPUFREQ_NAME_LEN); + } + if ((rc=cpufreq_get_policy(pFreqPolicy,PUBLIC(RO(Proc))->Service.Core)) == 0) + { + struct cpufreq_governor *pGovernor = pFreqPolicy->governor; + if (pGovernor != NULL) { + StrCopy(PUBLIC(RO(Proc))->OS.FreqDriver.Governor, + pGovernor->name, CPUFREQ_NAME_LEN); + } else { + PUBLIC(RO(Proc))->OS.FreqDriver.Governor[0] = '\0'; + } + } else { + PUBLIC(RO(Proc))->OS.FreqDriver.Governor[0] = '\0'; + } +#endif /* CONFIG_CPU_FREQ */ + return rc; +} + +static long Sys_Kernel(SYSGATE_RO *SysGate) +{ /* Sources: /include/generated/uapi/linux/version.h + /include/uapi/linux/utsname.h */ + if (SysGate != NULL) { + SysGate->kernelVersionNumber = LINUX_VERSION_CODE; + memcpy(SysGate->sysname, utsname()->sysname, MAX_UTS_LEN); + memcpy(SysGate->release, utsname()->release, MAX_UTS_LEN); + memcpy(SysGate->version, utsname()->version, MAX_UTS_LEN); + memcpy(SysGate->machine, utsname()->machine, MAX_UTS_LEN); + + return RC_OK_SYSGATE; + } else { + return -ENXIO; + } +} + +static long SysGate_OnDemand(void) +{ + long rc = -1; + if (PUBLIC(OF(Gate)) == NULL) + { /* On-demand allocation. */ + PUBLIC(OF(Gate)) = alloc_pages_exact(PUBLIC(RO(Proc))->Gate.ReqMem.Size, + GFP_KERNEL); + if (PUBLIC(OF(Gate)) != NULL) + { + const size_t + allocPages = PAGE_SIZE << PUBLIC(RO(Proc))->Gate.ReqMem.Order; + memset(PUBLIC(OF(Gate)), 0, allocPages); + rc = 0; + } + } else { /* Already allocated */ + rc = 1; + } + return rc; +} + +#define Atomic_Write_VPMC( _Core, cycles, _lvl) \ +{ \ + switch (_lvl) { \ + case 0: \ + Atomic_Add_VPMC(LOCKLESS, _Core->VPMC.C1, cycles); \ + break; \ + case 1: \ + Atomic_Add_VPMC(LOCKLESS, _Core->VPMC.C2, cycles); \ + break; \ + case 2: \ + Atomic_Add_VPMC(LOCKLESS, _Core->VPMC.C3, cycles); \ + break; \ + case 3: \ + Atomic_Add_VPMC(LOCKLESS, _Core->VPMC.C4, cycles); \ + break; \ + case 4: \ + Atomic_Add_VPMC(LOCKLESS, _Core->VPMC.C5, cycles); \ + break; \ + case 5: \ + Atomic_Add_VPMC(LOCKLESS, _Core->VPMC.C6, cycles); \ + break; \ + case 6: \ + Atomic_Add_VPMC(LOCKLESS, _Core->VPMC.C7, cycles); \ + break; \ + }; \ +} + +#undef Atomic_Write_VPMC + +static void CoreFreqK_IdleDriver_UnInit(void) +{ +#if defined(CONFIG_CPU_IDLE) && LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0) + struct cpuidle_device *device; + unsigned int cpu; + + for (cpu = 0; cpu < PUBLIC(RO(Proc))->CPU.Count; cpu++) { + if (!BITVAL(PUBLIC(RO(Core, AT(cpu)))->OffLine, HW)) { + if ((device=per_cpu_ptr(CoreFreqK.IdleDevice, cpu)) != NULL) + { + cpuidle_unregister_device(device); + } + } + } + cpuidle_unregister_driver(&CoreFreqK.IdleDriver); + free_percpu(CoreFreqK.IdleDevice); +#endif /* CONFIG_CPU_IDLE and 4.14.0 */ + PUBLIC(RO(Proc))->Registration.Driver.Route = ROUTE_DEFAULT; +} + +static int CoreFreqK_IdleDriver_Init(void) +{ + int rc = -RC_UNIMPLEMENTED; +#if defined(CONFIG_CPU_IDLE) && LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0) + if (Arch[PUBLIC(RO(Proc))->ArchID].SystemDriver.IdleState != NULL) + { + IDLE_STATE *pIdleState; + pIdleState = Arch[PUBLIC(RO(Proc))->ArchID].SystemDriver.IdleState; + if ((pIdleState != NULL) && PUBLIC(RO(Proc))->Features.MONITOR) + { + if ((CoreFreqK.IdleDevice=alloc_percpu(struct cpuidle_device)) == NULL) + { + rc = -ENOMEM; + } + else + { + struct cpuidle_device *device; + unsigned int cpu, enroll = 0; + /* Kernel polling loop */ + cpuidle_poll_state_init(&CoreFreqK.IdleDriver); + + CoreFreqK.IdleDriver.state_count = 1; + /* Idle States */ + while (pIdleState->Name != NULL) + { + if (CoreFreqK.IdleDriver.state_count < SUB_CSTATE_COUNT) + { + CoreFreqK.IdleDriver.states[ + CoreFreqK.IdleDriver.state_count + ].flags = pIdleState->flags; + + if (CoreFreqK.SubCstate[CoreFreqK.IdleDriver.state_count] == 0) + { + CoreFreqK.IdleDriver.states[ + CoreFreqK.IdleDriver.state_count + ].flags |= CPUIDLE_FLAG_UNUSABLE; + } + StrCopy(CoreFreqK.IdleDriver.states[ + CoreFreqK.IdleDriver.state_count + ].name, pIdleState->Name, CPUIDLE_NAME_LEN); + + StrCopy(CoreFreqK.IdleDriver.states[ + CoreFreqK.IdleDriver.state_count + ].desc, pIdleState->Desc, CPUIDLE_NAME_LEN); + + CoreFreqK.IdleDriver.states[ + CoreFreqK.IdleDriver.state_count + ].exit_latency = pIdleState->Latency; + + CoreFreqK.IdleDriver.states[ + CoreFreqK.IdleDriver.state_count + ].target_residency = pIdleState->Residency; + + switch (Idle_Route) { + case ROUTE_MWAIT: + { + goto IDLE_DEFAULT; + } + CoreFreqK.IdleDriver.states[ + CoreFreqK.IdleDriver.state_count + ].desc[0] = 'M'; + + CoreFreqK.IdleDriver.states[ + CoreFreqK.IdleDriver.state_count + ].desc[1] = 'W'; + + CoreFreqK.IdleDriver.states[ + CoreFreqK.IdleDriver.state_count + ].desc[2] = 'T'; + + PUBLIC(RO(Proc))->Registration.Driver.Route = ROUTE_MWAIT; + break; + + case ROUTE_HALT: + { + goto IDLE_DEFAULT; + } + CoreFreqK.IdleDriver.states[ + CoreFreqK.IdleDriver.state_count + ].desc[0] = 'H'; + + CoreFreqK.IdleDriver.states[ + CoreFreqK.IdleDriver.state_count + ].desc[1] = 'L'; + + CoreFreqK.IdleDriver.states[ + CoreFreqK.IdleDriver.state_count + ].desc[2] = 'T'; + + PUBLIC(RO(Proc))->Registration.Driver.Route = ROUTE_HALT; + break; + + case ROUTE_IO: + { + { + goto IDLE_DEFAULT; + } + CoreFreqK.IdleDriver.states[ + CoreFreqK.IdleDriver.state_count + ].desc[0] = 'I'; + + CoreFreqK.IdleDriver.states[ + CoreFreqK.IdleDriver.state_count + ].desc[1] = '/'; + + CoreFreqK.IdleDriver.states[ + CoreFreqK.IdleDriver.state_count + ].desc[2] = 'O'; + } + + PUBLIC(RO(Proc))->Registration.Driver.Route = ROUTE_IO; + break; + + case ROUTE_DEFAULT: + IDLE_DEFAULT: + default: + PUBLIC(RO(Proc))->Registration.Driver.Route = ROUTE_DEFAULT; + break; + } + CoreFreqK.IdleDriver.state_count++; + } + pIdleState++; + } + if ((rc = cpuidle_register_driver(&CoreFreqK.IdleDriver)) == 0) + { + for (cpu = 0; cpu < PUBLIC(RO(Proc))->CPU.Count; cpu++) + { + if (!BITVAL(PUBLIC(RO(Core, AT(cpu)))->OffLine, HW)) + { + device = per_cpu_ptr(CoreFreqK.IdleDevice, cpu); + if (device != NULL) + { + device->cpu = cpu; + if ((rc = cpuidle_register_device(device)) == 0) { + continue; + } + } + break; + } + } + enroll = cpu; + } + if (rc != 0) + { /* Cancel the registration if the driver and/or a device failed */ + for (cpu = 0; cpu < enroll; cpu++) + { + device = per_cpu_ptr(CoreFreqK.IdleDevice, cpu); + if (device != NULL) + { + cpuidle_unregister_device(device); + } + } + cpuidle_unregister_driver(&CoreFreqK.IdleDriver); + free_percpu(CoreFreqK.IdleDevice); + } + } + } + } +#endif /* CONFIG_CPU_IDLE and 4.14.0 */ + return rc; +} + +#ifdef CONFIG_CPU_IDLE +static void CoreFreqK_Idle_State_Withdraw(int idx, bool disable) +{ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 5, 0) || (RHEL_MAJOR == 8) + struct cpuidle_device *device; + unsigned int cpu; + for (cpu = 0; cpu < PUBLIC(RO(Proc))->CPU.Count; cpu++) + { + if (!BITVAL(PUBLIC(RO(Core, AT(cpu)))->OffLine, HW) + && ((device = per_cpu_ptr(CoreFreqK.IdleDevice, cpu)) != NULL)) + { + if (disable) { + device->states_usage[idx].disable |= CPUIDLE_STATE_DISABLED_BY_DRIVER; + } else { + device->states_usage[idx].disable &= ~CPUIDLE_STATE_DISABLED_BY_DRIVER; + } + } + } +#else + CoreFreqK.IdleDriver.states[idx].disabled = disable; +#endif /* 5.5.0 */ +} +#endif /* CONFIG_CPU_IDLE */ + +static long CoreFreqK_Limit_Idle(int target) +{ + long rc = -EINVAL; +#ifdef CONFIG_CPU_IDLE + int idx, floor = -1; + + if ((target > 0) && (target <= CoreFreqK.IdleDriver.state_count)) + { + for (idx = 0; idx < CoreFreqK.IdleDriver.state_count; idx++) + { + if (idx < target) + { + CoreFreqK_Idle_State_Withdraw(idx, false); + + floor = idx; + } else { + CoreFreqK_Idle_State_Withdraw(idx, true); + } + } + rc = RC_SUCCESS; + } + else if (target == 0) + { + for (idx = 0; idx < CoreFreqK.IdleDriver.state_count; idx++) + { + CoreFreqK_Idle_State_Withdraw(idx, false); + + floor = idx; + } + rc = RC_SUCCESS; + } + if (floor != -1) { + PUBLIC(RO(Proc))->OS.IdleDriver.stateLimit = 1 + floor; + } +#endif /* CONFIG_CPU_IDLE */ + return rc; +} + +#ifdef CONFIG_CPU_FREQ +static int CoreFreqK_Policy_Exit(struct cpufreq_policy *policy) +{ + UNUSED(policy); + return 0; +} + +static int CoreFreqK_Policy_Init(struct cpufreq_policy *policy) +{ + if (policy != NULL) { + if (policy->cpu < PUBLIC(RO(Proc))->CPU.Count) + { + CORE_RO *Core = (CORE_RO *) PUBLIC(RO(Core, AT(policy->cpu))); + + policy->cpuinfo.min_freq = (Core->Boost[BOOST(MIN)] + * Core->Clock.Hz) / 1000LLU; + + policy->cpuinfo.max_freq = (Core->Boost[BOOST(MAX)] + * Core->Clock.Hz) / 1000LLU; + + /* MANDATORY Per-CPU Initialization */ + policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; + policy->cur = policy->cpuinfo.max_freq; + policy->min = policy->cpuinfo.min_freq; + policy->max = policy->cpuinfo.max_freq; + policy->policy = CPUFREQ_POLICY_PERFORMANCE; + if (Register_Governor == 1) { + policy->governor = &CoreFreqK.FreqGovernor; + } else { + policy->governor = NULL; + } + } + } + return 0; +} + +#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 19)) \ + && (LINUX_VERSION_CODE <= KERNEL_VERSION(5, 5, 0))) \ + || (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 5, 3)) \ + || (RHEL_MAJOR == 8) +static int CoreFreqK_Policy_Verify(struct cpufreq_policy_data *policy) +#else +static int CoreFreqK_Policy_Verify(struct cpufreq_policy *policy) +#endif +{ + if (policy != NULL) { + cpufreq_verify_within_cpu_limits(policy); + } + return 0; +} + +static int CoreFreqK_SetPolicy(struct cpufreq_policy *policy) +{ + UNUSED(policy); + return 0; +} + +static int CoreFreqK_Bios_Limit(int cpu, unsigned int *limit) +{ + if ((cpu >= 0) && (cpu < PUBLIC(RO(Proc))->CPU.Count) && (limit != NULL)) + { + CORE_RO *Core = (CORE_RO *) PUBLIC(RO(Core, AT(cpu))); + + (*limit) = (Core->Boost[BOOST(MAX)] * Core->Clock.Hz) / 1000LLU; + } + return 0; +} + +static ssize_t CoreFreqK_Show_SetSpeed(struct cpufreq_policy *policy,char *buf) +{ + if (policy != NULL) + { + CORE_RO *Core; + enum RATIO_BOOST boost; + + if (policy->cpu < PUBLIC(RO(Proc))->CPU.Count) + { + Core = (CORE_RO *) PUBLIC(RO(Core, AT(policy->cpu))); + } else { + Core = (CORE_RO *) PUBLIC(RO(Core, AT(PUBLIC(RO(Proc))->Service.Core))); + } + if (PUBLIC(RO(Proc))->Features.HWP_Enable) { + boost = BOOST(HWP_TGT); + } else { + boost = BOOST(TGT); + } + return sprintf( buf, "%7llu\n", + (Core->Boost[boost] * Core->Clock.Hz) / 1000LLU ); + } + return 0; +} + +static int CoreFreqK_Store_SetSpeed(struct cpufreq_policy *policy, + unsigned int freq) +{ + if (policy != NULL) + { + void (*SetTarget)(void *arg) = NULL; + + SetTarget = Arch[PUBLIC(RO(Proc))->ArchID].SystemDriver.SetTarget; + + if ((policy->cpu < PUBLIC(RO(Proc))->CPU.Count) && (SetTarget != NULL)) + { + CORE_RO *Core = (CORE_RO *) PUBLIC(RO(Core, AT(policy->cpu))); + unsigned int ratio = (freq * 1000LLU) / Core->Clock.Hz; + + if (ratio > 0) { + if (smp_call_function_single( policy->cpu, + SetTarget, + &ratio, 1) == 0 ) + { + BITSET(BUS_LOCK, PUBLIC(RW(Proc))->OS.Signal, NTFY); + } + return 0; + } + } + } + return -EINVAL; +} +#endif /* CONFIG_CPU_FREQ */ + +static unsigned int Policy_GetFreq(unsigned int cpu) +{ + unsigned int CPU_Freq = PUBLIC(RO(Proc))->Features.Factory.Freq * 1000U; + + if (cpu < PUBLIC(RO(Proc))->CPU.Count) + { + CORE_RO *Core = (CORE_RO *) PUBLIC(RO(Core, AT(cpu))); + + unsigned int Freq_MHz = Core->Delta.C0.UCC + / PUBLIC(RO(Proc))->SleepInterval; + + if (Freq_MHz > 0) { /* at least 1 interval must have been elapsed */ + CPU_Freq = Freq_MHz; + } + } + return CPU_Freq; +} + +static int CoreFreqK_FreqDriver_UnInit(void) +{ + int rc = -EINVAL; +#ifdef CONFIG_CPU_FREQ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 3, 0)) && (!defined(CONFIG_CACHY)) + rc = +#else + rc = 0; +#endif + cpufreq_unregister_driver(&CoreFreqK.FreqDriver); +#endif /* CONFIG_CPU_FREQ */ + return rc; +} + +static int CoreFreqK_FreqDriver_Init(void) +{ + int rc = -RC_UNIMPLEMENTED; +#ifdef CONFIG_CPU_FREQ + if (Arch[PUBLIC(RO(Proc))->ArchID].SystemDriver.IdleState != NULL) + { + if (Arch[PUBLIC(RO(Proc))->ArchID].SystemDriver.GetFreq != NULL) + { + CoreFreqK.FreqDriver.get=Arch[PUBLIC(RO(Proc))->ArchID].SystemDriver.GetFreq; + + rc = cpufreq_register_driver(&CoreFreqK.FreqDriver); + } + } +#endif /* CONFIG_CPU_FREQ */ + return rc; +} + +static void CoreFreqK_Governor_UnInit(void) +{ +#ifdef CONFIG_CPU_FREQ + cpufreq_unregister_governor(&CoreFreqK.FreqGovernor); +#endif /* CONFIG_CPU_FREQ */ +} + +static int CoreFreqK_Governor_Init(void) +{ + int rc = -RC_UNIMPLEMENTED; +#ifdef CONFIG_CPU_FREQ + if (Arch[PUBLIC(RO(Proc))->ArchID].SystemDriver.IdleState != NULL) + { + if (Arch[PUBLIC(RO(Proc))->ArchID].SystemDriver.SetTarget != NULL) + { + rc = cpufreq_register_governor(&CoreFreqK.FreqGovernor); + } + } +#endif /* CONFIG_CPU_FREQ */ + return rc; +} + +static signed int Seek_Topology_Core_Peer(unsigned int cpu, signed int exclude) +{ + unsigned int seek; + + for (seek = 0; seek < PUBLIC(RO(Proc))->CPU.Count; seek++) { + if ( ((exclude ^ cpu) > 0) + && (PUBLIC(RO(Core, AT(seek)))->T.MPID \ + != PUBLIC(RO(Core, AT(cpu)))->T.MPID) + && (PUBLIC(RO(Core, AT(seek)))->T.CoreID \ + == PUBLIC(RO(Core, AT(cpu)))->T.CoreID) + && (PUBLIC(RO(Core, AT(seek)))->T.ThreadID \ + != PUBLIC(RO(Core, AT(cpu)))->T.ThreadID) + && (PUBLIC(RO(Core, AT(seek)))->T.PackageID \ + == PUBLIC(RO(Core, AT(cpu)))->T.PackageID) + && (PUBLIC(RO(Core, AT(seek)))->T.ThreadID == 0) + && !BITVAL(PUBLIC(RO(Core, AT(seek)))->OffLine, OS) ) + { + return (signed int) seek; + } + } + return -1; +} + +static signed int Seek_Topology_Thread_Peer(unsigned int cpu,signed int exclude) +{ + unsigned int seek; + + for (seek = 0; seek < PUBLIC(RO(Proc))->CPU.Count; seek++) { + if ( ((exclude ^ cpu) > 0) + && (PUBLIC(RO(Core, AT(seek)))->T.MPID \ + != PUBLIC(RO(Core, AT(cpu)))->T.MPID) + && (PUBLIC(RO(Core, AT(seek)))->T.CoreID \ + == PUBLIC(RO(Core, AT(cpu)))->T.CoreID) + && (PUBLIC(RO(Core, AT(seek)))->T.ThreadID \ + != PUBLIC(RO(Core, AT(cpu)))->T.ThreadID) + && (PUBLIC(RO(Core, AT(seek)))->T.PackageID \ + == PUBLIC(RO(Core, AT(cpu)))->T.PackageID) + && (PUBLIC(RO(Core, AT(seek)))->T.ThreadID > 0) + && !BITVAL(PUBLIC(RO(Core, AT(seek)))->OffLine, OS) ) + { + return (signed int) seek; + } + } + return -1; +} + +static signed int Seek_Topology_Hybrid_Core(unsigned int cpu) +{ + signed int any = (signed int) PUBLIC(RO(Proc))->CPU.Count, seek; + + do { + any--; + } while (BITVAL(PUBLIC(RO(Core, AT(any)))->OffLine, OS) && (any > 0)) ; + + for (seek = any; seek != 0; seek--) + { + if ((PUBLIC(RO(Core, AT(seek)))->T.Cluster.Hybrid_ID == Hybrid_Secondary) + && (PUBLIC(RO(Core, AT(seek)))->T.PackageID \ + == PUBLIC(RO(Core, AT(cpu)))->T.PackageID) + && !BITVAL(PUBLIC(RO(Core, AT(seek)))->OffLine, OS)) + { + any = seek; + break; + } + } + return any; +} + +static void MatchCoreForService(SERVICE_PROC *pService, + unsigned int cpi, signed int cpx) +{ + unsigned int cpu; + + for (cpu = 0; cpu < PUBLIC(RO(Proc))->CPU.Count; cpu++) { + if ( ((cpx ^ cpu) > 0) + && (PUBLIC(RO(Core, AT(cpu)))->T.PackageID \ + == PUBLIC(RO(Core, AT(cpi)))->T.PackageID) + && !BITVAL(PUBLIC(RO(Core, AT(cpu)))->OffLine, OS) ) + { + pService->Core = cpu; + pService->Thread = -1; + break; + } + } +} + +static int MatchPeerForService(SERVICE_PROC *pService, + unsigned int cpi, signed int cpx) +{ + unsigned int cpu = cpi, cpn = 0; + signed int seek; +MATCH: + if (PUBLIC(RO(Core, AT(cpu)))->T.ThreadID == 0) + { + if ((seek = Seek_Topology_Thread_Peer(cpu, cpx)) != -1) { + pService->Core = cpu; + pService->Thread = seek; + return 0; + } + } + else if (PUBLIC(RO(Core, AT(cpu)))->T.ThreadID > 0) + { + if ((seek = Seek_Topology_Core_Peer(cpu, cpx)) != -1) { + pService->Core = seek; + pService->Thread = cpu; + return 0; + } + } + while (cpn < PUBLIC(RO(Proc))->CPU.Count) { + cpu = cpn++; + if (!BITVAL(PUBLIC(RO(Core, AT(cpu)))->OffLine, OS)) { + goto MATCH; + } + } + return -1; +} + +static void MatchPeerForDefaultService(SERVICE_PROC *pService, unsigned int cpu) +{ + if (PUBLIC(RO(Proc))->Features.HTT_Enable) { + if (MatchPeerForService(pService, cpu, -1) == -1) + { + MatchCoreForService(pService, cpu, -1); + } + } else { + pService->Core = cpu; + pService->Thread = -1; + } + if (PUBLIC(RO(Proc))->Features.Hybrid) { + pService->Hybrid = Seek_Topology_Hybrid_Core(cpu); + } else { + pService->Hybrid = -1; + } + if (ServiceProcessor != -1) { + DefaultSMT.Core = pService->Core; + DefaultSMT.Thread = pService->Thread; + } +} + +static void MatchPeerForUpService(SERVICE_PROC *pService, unsigned int cpu) +{ /* Try to restore the initial Service affinity or move to SMT peer. */ + SERVICE_PROC hService = { + .Core = cpu, + .Thread = -1, + .Hybrid = -1 + }; + if (PUBLIC(RO(Proc))->Features.HTT_Enable) + { + signed int seek; + + if ((PUBLIC(RO(Core, AT(cpu)))->T.ThreadID == 0) + && ((seek = Seek_Topology_Thread_Peer(cpu, -1)) != -1)) + { + hService.Core = cpu; + hService.Thread = seek; + } else { + if ((PUBLIC(RO(Core, AT(cpu)))->T.ThreadID > 0) + && ((seek = Seek_Topology_Core_Peer(cpu, -1)) != -1)) + { + hService.Core = seek; + hService.Thread = cpu; + } + } + } + if ((pService->Core != DefaultSMT.Core) + || (pService->Thread != DefaultSMT.Thread)) + { + if ((hService.Core == DefaultSMT.Core) + && (hService.Thread == DefaultSMT.Thread)) + { + pService->Core = hService.Core; + pService->Thread = hService.Thread; + } else { + if ((pService->Thread == -1) && (hService.Thread > 0)) + { + pService->Core = hService.Core; + pService->Thread = hService.Thread; + } + } + } + if (PUBLIC(RO(Proc))->Features.Hybrid) { + pService->Hybrid = Seek_Topology_Hybrid_Core(cpu); + } +} + +static void MatchPeerForDownService(SERVICE_PROC *pService, unsigned int cpu) +{ + int rc = -1; + + if (PUBLIC(RO(Proc))->Features.HTT_Enable) { + rc = MatchPeerForService(pService, cpu, cpu); + } + if (rc == -1) { + MatchCoreForService(pService, cpu, cpu); + } +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0) +#if defined(CONFIG_HAVE_NMI) +static int CoreFreqK_NMI_Handler(unsigned int type, struct pt_regs *pRegs) +{ + unsigned int cpu = smp_processor_id(); + UNUSED(pRegs); + + switch (type) { + case NMI_LOCAL: + PUBLIC(RO(Core, AT(cpu)))->Interrupt.NMI.LOCAL++; + break; + case NMI_UNKNOWN: + PUBLIC(RO(Core, AT(cpu)))->Interrupt.NMI.UNKNOWN++; + break; + case NMI_SERR: + PUBLIC(RO(Core, AT(cpu)))->Interrupt.NMI.PCISERR++; + break; + case NMI_IO_CHECK: + PUBLIC(RO(Core, AT(cpu)))->Interrupt.NMI.IOCHECK++; + break; + } + return NMI_DONE; +} +#endif /* CONFIG_HAVE_NMI */ + +static long CoreFreqK_UnRegister_CPU_Idle(void) +{ + long rc = -EINVAL; + if (PUBLIC(RO(Proc))->Registration.Driver.CPUidle & REGISTRATION_ENABLE) + { + CoreFreqK_IdleDriver_UnInit(); + PUBLIC(RO(Proc))->Registration.Driver.CPUidle = REGISTRATION_DISABLE; + rc = RC_SUCCESS; + } + return rc; +} + +static long CoreFreqK_Register_CPU_Idle(void) +{ + long rc = -EINVAL; + if (Register_CPU_Idle == 1) + { + int rx = CoreFreqK_IdleDriver_Init(); + switch ( rx ) { + default: + fallthrough; + case -ENODEV: + case -ENOMEM: + PUBLIC(RO(Proc))->Registration.Driver.CPUidle = REGISTRATION_DISABLE; + rc = (long) rx; + break; + case 0: /* Registration succeeded. */ + PUBLIC(RO(Proc))->Registration.Driver.CPUidle = REGISTRATION_ENABLE; + rc = RC_SUCCESS; + break; + } + } else { /* Nothing requested by User. */ + PUBLIC(RO(Proc))->Registration.Driver.CPUidle = REGISTRATION_DISABLE; + } + return rc; +} + +static long CoreFreqK_UnRegister_CPU_Freq(void) +{ + long rc = -EINVAL; + if (PUBLIC(RO(Proc))->Registration.Driver.CPUfreq & REGISTRATION_ENABLE) + { + int rx = CoreFreqK_FreqDriver_UnInit(); + switch ( rx ) { + case 0: + PUBLIC(RO(Proc))->Registration.Driver.CPUfreq=REGISTRATION_DISABLE; + rc = RC_SUCCESS; + break; + default: + rc = (long) rx; + break; + } + } + return rc; +} + +static long CoreFreqK_Register_CPU_Freq(void) +{ /* Source: cpufreq_register_driver @ /drivers/cpufreq/cpufreq.c */ + long rc = -EINVAL; + if (Register_CPU_Freq == 1) + { + int rx = CoreFreqK_FreqDriver_Init(); + switch ( rx ) { + default: + fallthrough; + case -EEXIST: /* Another driver is in control. */ + PUBLIC(RO(Proc))->Registration.Driver.CPUfreq = REGISTRATION_DISABLE; + rc = (long) rx; + break; + case -ENODEV: /* Missing CPU-Freq or Interfaces. */ + case -EPROBE_DEFER: /* CPU probing failed */ + case -EINVAL: /* Missing CPU-Freq prerequisites. */ + PUBLIC(RO(Proc))->Registration.Driver.CPUfreq = REGISTRATION_FULLCTRL; + rc = (long) rx; + break; + case 0: /* Registration succeeded . */ + PUBLIC(RO(Proc))->Registration.Driver.CPUfreq = REGISTRATION_ENABLE; + rc = RC_SUCCESS; + break; + } + } else { /* Invalid or no User request. */ +#ifdef CONFIG_CPU_FREQ + PUBLIC(RO(Proc))->Registration.Driver.CPUfreq = REGISTRATION_DISABLE; +#else /* No CPU-FREQ built in Kernel, presume we have the full control. */ + PUBLIC(RO(Proc))->Registration.Driver.CPUfreq = REGISTRATION_FULLCTRL; +#endif /* CONFIG_CPU_FREQ */ + } + return rc; +} + +static long CoreFreqK_UnRegister_Governor(void) +{ + long rc = EINVAL; + if (PUBLIC(RO(Proc))->Registration.Driver.Governor & REGISTRATION_ENABLE) + { + CoreFreqK_Governor_UnInit(); + PUBLIC(RO(Proc))->Registration.Driver.Governor = REGISTRATION_DISABLE; + rc = RC_SUCCESS; + } + return rc; +} + +static long CoreFreqK_Register_Governor(void) +{ + long rc = -EINVAL; + if (Register_Governor == 1) + { + int rx = CoreFreqK_Governor_Init(); + switch ( rx ) { + default: + case -ENODEV: + PUBLIC(RO(Proc))->Registration.Driver.Governor = REGISTRATION_DISABLE; + rc = (long) rx; + break; + case 0: /* Registration succeeded . */ + PUBLIC(RO(Proc))->Registration.Driver.Governor = REGISTRATION_ENABLE; + rc = RC_SUCCESS; + break; + } + } else { /* Nothing requested by User. */ + PUBLIC(RO(Proc))->Registration.Driver.Governor = REGISTRATION_DISABLE; + } + return rc; +} + +static void CoreFreqK_Register_NMI(void) +{ +#if defined(CONFIG_HAVE_NMI) + if (BITVAL(PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_LOCAL) == 0) + { + if(register_nmi_handler(NMI_LOCAL, + CoreFreqK_NMI_Handler, + 0, + "corefreqk") == 0) + { + BITSET(LOCKLESS, PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_LOCAL); + } else { + BITCLR(LOCKLESS, PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_LOCAL); + } + } + if (BITVAL(PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_UNKNOWN) == 0) + { + if(register_nmi_handler(NMI_UNKNOWN, + CoreFreqK_NMI_Handler, + 0, + "corefreqk") == 0) + { + BITSET(LOCKLESS, PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_UNKNOWN); + } else { + BITCLR(LOCKLESS, PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_UNKNOWN); + } + } + if (BITVAL(PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_SERR) == 0) + { + if(register_nmi_handler(NMI_SERR, + CoreFreqK_NMI_Handler, + 0, + "corefreqk") == 0) + { + BITSET(LOCKLESS, PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_SERR); + } else { + BITCLR(LOCKLESS, PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_SERR); + } + } + if (BITVAL(PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_IO_CHECK) == 0) + { + if(register_nmi_handler(NMI_IO_CHECK, + CoreFreqK_NMI_Handler, + 0, + "corefreqk") == 0) + { + BITSET(LOCKLESS, PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_IO_CHECK); + } else { + BITCLR(LOCKLESS, PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_IO_CHECK); + } + } +#endif /* CONFIG_HAVE_NMI */ +} + +static void CoreFreqK_UnRegister_NMI(void) +{ +#if defined(CONFIG_HAVE_NMI) + if (BITVAL(PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_LOCAL) == 1) + { + unregister_nmi_handler(NMI_LOCAL, "corefreqk"); + BITCLR(LOCKLESS, PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_LOCAL); + } + if (BITVAL(PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_UNKNOWN) == 1) + { + unregister_nmi_handler(NMI_UNKNOWN, "corefreqk"); + BITCLR(LOCKLESS, PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_UNKNOWN); + } + if (BITVAL(PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_SERR) == 1) + { + unregister_nmi_handler(NMI_SERR, "corefreqk"); + BITCLR(LOCKLESS, PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_SERR); + } + if (BITVAL(PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_IO_CHECK) == 1) + { + unregister_nmi_handler(NMI_IO_CHECK, "corefreqk"); + BITCLR(LOCKLESS, PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_IO_CHECK); + } +#endif /* CONFIG_HAVE_NMI */ +} +#else +static void CoreFreqK_Register_NMI(void) {} +static void CoreFreqK_UnRegister_NMI(void) {} +#endif /* KERNEL_VERSION(3, 5, 0) */ + +#define SYSGATE_UPDATE(_rc) \ +({ \ + _rc = Sys_OS_Driver_Query(); \ + _rc = (_rc != -ENXIO) ? RC_OK_SYSGATE : _rc; \ +}) + +static long CoreFreqK_ioctl( struct file *filp, + unsigned int cmd, + unsigned long arg ) +{ + long rc = -EPERM; + UNUSED(filp); + + switch ((enum COREFREQ_MAGIC_COMMAND) cmd) + { + case COREFREQ_IOCTL_SYSUPDT: + Controller_Stop(1); + SYSGATE_UPDATE(rc); + Controller_Start(1); + BITSET(BUS_LOCK, PUBLIC(RW(Proc))->OS.Signal, NTFY); + break; + + case COREFREQ_IOCTL_SYSONCE: + rc = Sys_OS_Driver_Query(); + rc = (rc != -ENXIO) ? Sys_Kernel(PUBLIC(OF(Gate))) : rc; + break; + + case COREFREQ_IOCTL_MACHINE: + { + RING_ARG_QWORD prm = {.arg = arg}; + + switch (prm.dl.hi) + { + case MACHINE_CONTROLLER: + switch (prm.dl.lo) + { + case COREFREQ_TOGGLE_OFF: + Controller_Stop(1); + rc = RC_SUCCESS; + break; + case COREFREQ_TOGGLE_ON: + Controller_Start(1); + rc = RC_OK_COMPUTE; + break; + } + break; + + case MACHINE_INTERVAL: + Controller_Stop(1); + SleepInterval = prm.dl.lo; + Compute_Interval(); + Controller_Start(1); + rc = RC_SUCCESS; + break; + + case MACHINE_AUTOCLOCK: + switch (prm.dl.lo) + { + case COREFREQ_TOGGLE_OFF: + Controller_Stop(1); + BITCLR(LOCKLESS, AutoClock, 1); + PUBLIC(RO(Proc))->Registration.AutoClock = AutoClock; + Controller_Start(1); + rc = RC_SUCCESS; + break; + case COREFREQ_TOGGLE_ON: + Controller_Stop(1); + BITSET(LOCKLESS, AutoClock, 1); + PUBLIC(RO(Proc))->Registration.AutoClock = AutoClock; + Controller_Start(1); + rc = RC_SUCCESS; + break; + } + break; + + case MACHINE_EXPERIMENTAL: + switch (prm.dl.lo) { + case COREFREQ_TOGGLE_OFF: + case COREFREQ_TOGGLE_ON: + Controller_Stop(1); + PUBLIC(RO(Proc))->Registration.Experimental = prm.dl.lo; + Controller_Start(1); + if (PUBLIC(RO(Proc))->Registration.Experimental) + { + if ( !PUBLIC(RO(Proc))->Registration.PCI ) { + PUBLIC(RO(Proc))->Registration.PCI = \ + CoreFreqK_ProbePCI( + Arch[PUBLIC(RO(Proc))->ArchID].PCI_ids, + CoreFreqK_ResetChip, CoreFreqK_AppendChip + ) == 0; + rc = RC_OK_COMPUTE; + } else { + rc = RC_SUCCESS; + } + } else { + rc = RC_SUCCESS; + } + break; + } + break; + + case MACHINE_INTERRUPTS: + switch (prm.dl.lo) + { + case COREFREQ_TOGGLE_OFF: + Controller_Stop(1); + CoreFreqK_UnRegister_NMI(); + Controller_Start(1); + rc = RC_SUCCESS; + break; + case COREFREQ_TOGGLE_ON: + Controller_Stop(1); + CoreFreqK_Register_NMI(); + Controller_Start(1); + rc = RC_SUCCESS; + break; + } + break; + + case MACHINE_LIMIT_IDLE: + if (PUBLIC(RO(Proc))->Registration.Driver.CPUidle & REGISTRATION_ENABLE) + { + rc = CoreFreqK_Limit_Idle(prm.dl.lo); + } + break; + + case MACHINE_CPU_IDLE: + switch (prm.dl.lo) + { + case COREFREQ_TOGGLE_OFF: + Controller_Stop(1); + rc = CoreFreqK_UnRegister_CPU_Idle(); + Register_CPU_Idle = -1; + if (rc == RC_SUCCESS) { + SYSGATE_UPDATE(rc); + } + Controller_Start(1); + break; + case COREFREQ_TOGGLE_ON: + Controller_Stop(1); + Register_CPU_Idle = 1; + rc = CoreFreqK_Register_CPU_Idle(); + if (rc == RC_SUCCESS) { + SYSGATE_UPDATE(rc); + } + Controller_Start(1); + break; + } + break; + + case MACHINE_IDLE_ROUTE: + if (PUBLIC(RO(Proc))->Registration.Driver.CPUidle & REGISTRATION_ENABLE) + { + Controller_Stop(1); + rc = CoreFreqK_UnRegister_CPU_Idle(); + Register_CPU_Idle = -1; + if (rc == RC_SUCCESS) + { + Register_CPU_Idle = 1; + Idle_Route = prm.dl.lo; + rc = CoreFreqK_Register_CPU_Idle(); + if (rc == RC_SUCCESS) { + SYSGATE_UPDATE(rc); + } + } + Controller_Start(1); + } + break; + + case MACHINE_CPU_FREQ: + switch (prm.dl.lo) + { + case COREFREQ_TOGGLE_OFF: + Controller_Stop(1); + rc = CoreFreqK_UnRegister_CPU_Freq(); + Register_CPU_Freq = -1; + if (rc == RC_SUCCESS) { + SYSGATE_UPDATE(rc); + } + Controller_Start(1); + break; + case COREFREQ_TOGGLE_ON: + Controller_Stop(1); + Register_CPU_Freq = 1; + rc = CoreFreqK_Register_CPU_Freq(); + if (rc == RC_SUCCESS) { + SYSGATE_UPDATE(rc); + } + Controller_Start(1); + break; + } + break; + + case MACHINE_GOVERNOR: + switch (prm.dl.lo) + { + case COREFREQ_TOGGLE_OFF: + Controller_Stop(1); + rc = CoreFreqK_UnRegister_Governor(); + Register_Governor = -1; + if (rc == RC_SUCCESS) { + SYSGATE_UPDATE(rc); + } + Controller_Start(1); + break; + case COREFREQ_TOGGLE_ON: + Controller_Stop(1); + Register_Governor = 1; + rc = CoreFreqK_Register_Governor(); + if (rc == RC_SUCCESS) { + SYSGATE_UPDATE(rc); + } + Controller_Start(1); + break; + } + break; + + case MACHINE_CLOCK_SOURCE: + switch (prm.dl.lo) + { + case COREFREQ_TOGGLE_OFF: + Controller_Stop(1); + rc = CoreFreqK_UnRegister_ClockSource(); + Register_ClockSource = -1; + Controller_Start(1); + break; + case COREFREQ_TOGGLE_ON: + Controller_Stop(1); + Register_ClockSource = 1; + rc=CoreFreqK_Register_ClockSource(PUBLIC(RO(Proc))->Service.Core); + Controller_Start(1); + break; + } + break; + + case MACHINE_FORMULA_SCOPE: + switch (prm.dl.lo) + { + case 0: + rc = CoreFreqK_Thermal_Scope(prm.dh.lo); + break; + case 1: + rc = CoreFreqK_Voltage_Scope(prm.dh.lo); + break; + case 2: + rc = CoreFreqK_Power_Scope(prm.dh.lo); + break; + } + break; + } + } + break; + + case COREFREQ_IOCTL_TECHNOLOGY: + { + RING_ARG_QWORD prm = {.arg = arg}; + + switch (prm.dl.hi) + { + case TECHNOLOGY_HWP: + switch (prm.dl.lo) { + case COREFREQ_TOGGLE_ON: + Controller_Stop(1); + HWP_Enable = prm.dl.lo; + { + if (PUBLIC(RO(Proc))->Features.ACPI_CPPC) { + For_All_ACPI_CPPC(Enable_ACPI_CPPC, NULL); + } + } + Controller_Start(1); + HWP_Enable = -1; + rc = RC_SUCCESS; + break; + case COREFREQ_TOGGLE_OFF: + { + if (PUBLIC(RO(Proc))->Features.ACPI_CPPC) { + Controller_Stop(1); + For_All_ACPI_CPPC(Disable_ACPI_CPPC, NULL); + Controller_Start(1); + rc = RC_SUCCESS; + } + } + break; + } + break; + + case TECHNOLOGY_HWP_EPP: + Controller_Stop(1); + HWP_EPP = prm.dl.lo; + if (PUBLIC(RO(Proc))->Features.OSPM_EPP == 1) + { + For_All_ACPI_CPPC(Set_EPP_ACPI_CPPC, NULL); + } + Controller_Start(1); + HWP_EPP = -1; + rc = RC_SUCCESS; + break; + } + break; + } + break; + + case COREFREQ_IOCTL_CPU_OFF: + #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0) + { + unsigned int cpu = (unsigned int) arg; + + if (cpu < PUBLIC(RO(Proc))->CPU.Count) { + if (!cpu_is_hotpluggable(cpu)) { + rc = -EBUSY; + } else { + #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 7, 0) + if ((rc = remove_cpu(cpu)) == 0) { + rc = RC_OK_COMPUTE; + } + #else + if ((rc = cpu_down(cpu)) == 0) { + rc = RC_OK_COMPUTE; + } + #endif + } + } + } + #else + rc = -EINVAL; + #endif + break; + + case COREFREQ_IOCTL_CPU_ON: + #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0) + { + unsigned int cpu = (unsigned int) arg; + + if (cpu < PUBLIC(RO(Proc))->CPU.Count) { + if (!cpu_is_hotpluggable(cpu)) { + rc = -EBUSY; + } else { + #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 7, 0) + if ((rc = add_cpu(cpu)) == 0) { + rc = RC_OK_COMPUTE; + } + #else + if ((rc = cpu_up(cpu)) == 0) { + rc = RC_OK_COMPUTE; + } + #endif + } + } + } + #else + rc = -EINVAL; + #endif + break; + + case COREFREQ_IOCTL_TURBO_CLOCK: + if (Arch[PUBLIC(RO(Proc))->ArchID].TurboClock) { + CLOCK_ARG clockMod = {.sllong = arg}; + Controller_Stop(1); + rc = Arch[PUBLIC(RO(Proc))->ArchID].TurboClock(&clockMod); + Controller_Start(1); + } else { + rc = -RC_UNIMPLEMENTED; + } + break; + + case COREFREQ_IOCTL_RATIO_CLOCK: + if (Arch[PUBLIC(RO(Proc))->ArchID].ClockMod) { + CLOCK_ARG clockMod = {.sllong = arg}; + Controller_Stop(1); + rc = Arch[PUBLIC(RO(Proc))->ArchID].ClockMod(&clockMod); + Controller_Start(1); + } else { + rc = -RC_UNIMPLEMENTED; + } + break; + + case COREFREQ_IOCTL_UNCORE_CLOCK: + if (Arch[PUBLIC(RO(Proc))->ArchID].Uncore.ClockMod) { + CLOCK_ARG clockMod = {.sllong = arg}; + Controller_Stop(1); + rc = Arch[PUBLIC(RO(Proc))->ArchID].Uncore.ClockMod(&clockMod); + Controller_Start(1); + } else { + rc = -RC_UNIMPLEMENTED; + } + break; + + case COREFREQ_IOCTL_CLEAR_EVENTS: + switch (arg) { + case EVENT_THERMAL_LOG: + case EVENT_PROCHOT_LOG: + case EVENT_CRITIC_LOG: + case EVENT_THOLD1_LOG: + case EVENT_THOLD2_LOG: + case EVENT_POWER_LIMIT: + case EVENT_CURRENT_LIMIT: + case EVENT_CROSS_DOMAIN: + case EVENT_CORE_HOT_LOG: + case EVENT_CORE_THM_LOG: + case EVENT_CORE_RES_LOG: + case EVENT_CORE_AVG_LOG: + case EVENT_CORE_VRT_LOG: + case EVENT_CORE_TDC_LOG: + case EVENT_CORE_PL1_LOG: + case EVENT_CORE_PL2_LOG: + case EVENT_CORE_EDP_LOG: + case EVENT_CORE_BST_LOG: + case EVENT_CORE_ATT_LOG: + case EVENT_CORE_TVB_LOG: + case EVENT_GFX_HOT_LOG: + case EVENT_GFX_THM_LOG: + case EVENT_GFX_AVG_LOG: + case EVENT_GFX_VRT_LOG: + case EVENT_GFX_TDC_LOG: + case EVENT_GFX_PL1_LOG: + case EVENT_GFX_PL2_LOG: + case EVENT_GFX_EDP_LOG: + case EVENT_GFX_EFF_LOG: + case EVENT_RING_HOT_LOG: + case EVENT_RING_THM_LOG: + case EVENT_RING_AVG_LOG: + case EVENT_RING_VRT_LOG: + case EVENT_RING_TDC_LOG: + case EVENT_RING_PL1_LOG: + case EVENT_RING_PL2_LOG: + case EVENT_RING_EDP_LOG: + Controller_Stop(1); + Clear_Events = arg; + Controller_Start(1); + Clear_Events = 0; + rc = RC_OK_COMPUTE; + break; + case EVENT_ALL_OF_THEM: + Controller_Stop(1); + #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 17, 0) + Clear_Events = (unsigned long)(-1); + #else + Clear_Events = (unsigned long long)(-1); + #endif + Controller_Start(1); + Clear_Events = 0; + rc = RC_OK_COMPUTE; + break; + } + break; + + default: + rc = -EINVAL; + break; + } + return rc; +} + +#undef SYSGATE_UPDATE + +static int CoreFreqK_mmap(struct file *pfile, struct vm_area_struct *vma) +{ + unsigned long reqSize = vma->vm_end - vma->vm_start; + #if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) + vm_flags_t vm_ro = VM_READ; + #endif + int rc = -EIO; + UNUSED(pfile); + + if (vma->vm_pgoff == ID_RO_VMA_PROC) { + if (PUBLIC(RO(Proc)) != NULL) + { + const unsigned long secSize = ROUND_TO_PAGES(sizeof(PROC_RO)); + if (reqSize != secSize) { + rc = -EAGAIN; + goto EXIT_PAGE; + } + + #if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) + vm_flags_reset_once(vma, vm_ro); + #else + vma->vm_flags = VM_READ; + #endif + vma->vm_page_prot = PAGE_READONLY; + + rc = remap_pfn_range( vma, + vma->vm_start, + virt_to_phys((void *) PUBLIC(RO(Proc))) >> PAGE_SHIFT, + reqSize, + vma->vm_page_prot); + } + } else if (vma->vm_pgoff == ID_RW_VMA_PROC) { + if (PUBLIC(RW(Proc)) != NULL) + { + const unsigned long secSize = ROUND_TO_PAGES(sizeof(PROC_RW)); + if (reqSize != secSize) { + rc = -EAGAIN; + goto EXIT_PAGE; + } + + rc = remap_pfn_range( vma, + vma->vm_start, + virt_to_phys((void *) PUBLIC(RW(Proc))) >> PAGE_SHIFT, + reqSize, + vma->vm_page_prot); + } + } else if (vma->vm_pgoff == ID_RO_VMA_GATE) { + if (PUBLIC(RO(Proc)) != NULL) + { + switch (SysGate_OnDemand()) { + default: + case -1: + break; + case 1: + fallthrough; + case 0: { + const unsigned long + secSize = PAGE_SIZE << PUBLIC(RO(Proc))->Gate.ReqMem.Order; + if (reqSize != secSize) { + return -EAGAIN; + } + + #if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) + vm_flags_reset_once(vma, vm_ro); + #else + vma->vm_flags = VM_READ; + #endif + vma->vm_page_prot = PAGE_READONLY; + + rc = remap_pfn_range( vma, + vma->vm_start, + virt_to_phys((void *) PUBLIC(OF(Gate))) >> PAGE_SHIFT, + reqSize, + vma->vm_page_prot); + } + break; + } + } + } else if ((vma->vm_pgoff >= ID_RO_VMA_CORE) + && (vma->vm_pgoff < ID_RW_VMA_CORE)) + { + signed int cpu = vma->vm_pgoff - ID_RO_VMA_CORE; + + if (PUBLIC(RO(Proc)) != NULL) { + if ((cpu >= 0) && (cpu < PUBLIC(RO(Proc))->CPU.Count)) { + if (PUBLIC(RO(Core, AT(cpu))) != NULL) + { + const unsigned long secSize = ROUND_TO_PAGES(sizeof(CORE_RO)); + if (reqSize != secSize) { + rc = -EAGAIN; + goto EXIT_PAGE; + } + + #if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) + vm_flags_reset_once(vma, vm_ro); + #else + vma->vm_flags = VM_READ; + #endif + vma->vm_page_prot = PAGE_READONLY; + + rc = remap_pfn_range( vma, + vma->vm_start, + virt_to_phys((void *) PUBLIC(RO(Core, AT(cpu)))) >> PAGE_SHIFT, + reqSize, + vma->vm_page_prot); + } + } + } + } else if ((vma->vm_pgoff >= ID_RW_VMA_CORE) + && (vma->vm_pgoff < ID_ANY_VMA_JAIL)) + { + signed int cpu = vma->vm_pgoff - ID_RW_VMA_CORE; + + if (PUBLIC(RO(Proc)) != NULL) { + if ((cpu >= 0) && (cpu < PUBLIC(RO(Proc))->CPU.Count)) { + if (PUBLIC(RW(Core, AT(cpu))) != NULL) + { + const unsigned long secSize = ROUND_TO_PAGES(sizeof(CORE_RW)); + if (reqSize != secSize) { + rc = -EAGAIN; + goto EXIT_PAGE; + } + + rc = remap_pfn_range( vma, + vma->vm_start, + virt_to_phys((void *) PUBLIC(RW(Core, AT(cpu)))) >> PAGE_SHIFT, + reqSize, + vma->vm_page_prot); + } + } + } + } +EXIT_PAGE: + return rc; +} + +static DEFINE_MUTEX(CoreFreqK_mutex); /* Only one driver instance. */ + +static int CoreFreqK_open(struct inode *inode, struct file *pfile) +{ + UNUSED(inode); + UNUSED(pfile); + + if (!mutex_trylock(&CoreFreqK_mutex)) + return -EBUSY; + else + return 0; +} + +static int CoreFreqK_release(struct inode *inode, struct file *pfile) +{ + UNUSED(inode); + UNUSED(pfile); + + mutex_unlock(&CoreFreqK_mutex); + return 0; +} + +static struct file_operations CoreFreqK_fops = { + .open = CoreFreqK_open, + .release = CoreFreqK_release, + .mmap = CoreFreqK_mmap, + .unlocked_ioctl = CoreFreqK_ioctl, + .owner = THIS_MODULE, +}; + +#ifdef CONFIG_PM_SLEEP +inline void Print_SuspendResume(void) +{ + pr_notice("CoreFreq: %s(%u:%d:%d)\n", + CoreFreqK.ResumeFromSuspend ? "Suspend" : "Resume", + PUBLIC(RO(Proc))->Service.Core, + PUBLIC(RO(Proc))->Service.Thread, + PUBLIC(RO(Proc))->Service.Hybrid); +} + +static int CoreFreqK_Suspend(struct device *dev) +{ + UNUSED(dev); + + CoreFreqK.ResumeFromSuspend = true; + + Controller_Stop(1); + + Print_SuspendResume(); + return 0; +} + +static int CoreFreqK_Resume(struct device *dev) +{ /* Probe Processor again */ + UNUSED(dev); + + if (Arch[PUBLIC(RO(Proc))->ArchID].Query != NULL) { + Arch[PUBLIC(RO(Proc))->ArchID].Query(PUBLIC(RO(Proc))->Service.Core); + } + /* Probe PCI again */ + if (PUBLIC(RO(Proc))->Registration.PCI) { + PUBLIC(RO(Proc))->Registration.PCI = \ + CoreFreqK_ProbePCI(Arch[PUBLIC(RO(Proc))->ArchID].PCI_ids, + CoreFreqK_ResetChip, CoreFreqK_AppendChip) == 0; + } + Controller_Start(1); + + BITSET(BUS_LOCK, PUBLIC(RW(Proc))->OS.Signal, NTFY); /* Notify Daemon*/ + + CoreFreqK.ResumeFromSuspend = false; + + Print_SuspendResume(); + return 0; +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 17, 0) +static DEFINE_SIMPLE_DEV_PM_OPS(CoreFreqK_pm_ops, \ + CoreFreqK_Suspend, \ + CoreFreqK_Resume); +#else +static SIMPLE_DEV_PM_OPS(CoreFreqK_pm_ops, CoreFreqK_Suspend, CoreFreqK_Resume); +#endif /* KERNEL_VERSION(5, 17, 0) */ +#define COREFREQ_PM_OPS (&CoreFreqK_pm_ops) +#else /* CONFIG_PM_SLEEP */ +#define COREFREQ_PM_OPS NULL +#endif /* CONFIG_PM_SLEEP */ + + +#ifdef CONFIG_HOTPLUG_CPU +static int CoreFreqK_HotPlug_CPU_Online(unsigned int cpu) +{ + if (cpu < PUBLIC(RO(Proc))->CPU.Count) + { + /* Is this the very first time the processor is online ? */ + if (PUBLIC(RO(Core, AT(cpu)))->T.MPID == -1) + { + if (Core_Topology(cpu) == 0) + { + if (PUBLIC(RO(Core, AT(cpu)))->T.MPID >= 0) + { + BITCLR(LOCKLESS, PUBLIC(RO(Core, AT(cpu)))->OffLine, HW); + /* Is the BCLK frequency missing ? */ + if (PUBLIC(RO(Core, AT(cpu)))->Clock.Hz == 0) + { + if (AutoClock & 0b01) + { + COMPUTE_ARG Compute = { + .TSC = {NULL, NULL}, + .Clock = { + .Q = PUBLIC(RO(Proc))->Features.Hybrid == 1 ? + PUBLIC(RO(Proc))->Features.Factory.Ratio + : PUBLIC( + RO(Core, AT(PUBLIC(RO(Proc))->Service.Core)) + )->Boost[BOOST(MAX)], + .R = 0, .Hz = 0 + } + }; + if ((Compute.TSC[0] = kmalloc(STRUCT_SIZE, GFP_KERNEL)) != NULL) + { + if ((Compute.TSC[1] = kmalloc(STRUCT_SIZE, GFP_KERNEL)) != NULL) + { + PUBLIC(RO(Core, AT(cpu)))->Clock = Compute_Clock(cpu, &Compute); + + kfree(Compute.TSC[1]); + } + kfree(Compute.TSC[0]); + } + } else { + PUBLIC(RO(Core, AT(cpu)))->Clock = \ + PUBLIC(RO(Core, AT(PUBLIC(RO(Proc))->Service.Core)))->Clock; + } + } + } + } else { + BITSET(LOCKLESS, PUBLIC(RO(Core, AT(cpu)))->OffLine, HW); + } + } + PUBLIC(RO(Proc))->CPU.OnLine++; + BITCLR(LOCKLESS, PUBLIC(RO(Core, AT(cpu)))->OffLine, OS); + + MatchPeerForUpService(&PUBLIC(RO(Proc))->Service, cpu); + + if (PUBLIC(RO(Proc))->Features.ACPI_CPPC == 1) { + Read_ACPI_CPPC_Registers(cpu, NULL); + } + + /* Start the collect timer dedicated to this CPU iff not STR resuming */ +#ifdef CONFIG_PM_SLEEP + if (CoreFreqK.ResumeFromSuspend == false) +#endif /* CONFIG_PM_SLEEP */ + { + if (Arch[PUBLIC(RO(Proc))->ArchID].Timer != NULL) { + Arch[PUBLIC(RO(Proc))->ArchID].Timer(cpu); + } + if ((BITVAL(PRIVATE(OF(Core, AT(cpu)))->Join.TSM, STARTED) == 0) + && (Arch[PUBLIC(RO(Proc))->ArchID].Start != NULL)) { + smp_call_function_single(cpu, + Arch[PUBLIC(RO(Proc))->ArchID].Start, + NULL, 0); + } + } +#if defined(CONFIG_CPU_IDLE) && LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0) + if (PUBLIC(RO(Proc))->Registration.Driver.CPUidle & REGISTRATION_ENABLE) { + struct cpuidle_device *device = per_cpu_ptr(CoreFreqK.IdleDevice, cpu); + if (device != NULL) { + if (device->registered == 0) { + device->cpu = cpu; + cpuidle_register_device(device); + } + } + } +#endif /* CONFIG_CPU_IDLE */ + + return 0; + } else + return -EINVAL; +} + +static int CoreFreqK_HotPlug_CPU_Offline(unsigned int cpu) +{ + if (cpu < PUBLIC(RO(Proc))->CPU.Count) + { /* Stop the associated collect timer. */ + if ((BITVAL(PRIVATE(OF(Core, AT(cpu)))->Join.TSM, CREATED) == 1) + && (BITVAL(PRIVATE(OF(Core, AT(cpu)))->Join.TSM, STARTED) == 1) + && (Arch[PUBLIC(RO(Proc))->ArchID].Stop != NULL)) { + smp_call_function_single(cpu, + Arch[PUBLIC(RO(Proc))->ArchID].Stop, + NULL, 1); + } + PUBLIC(RO(Proc))->CPU.OnLine--; + BITSET(LOCKLESS, PUBLIC(RO(Core, AT(cpu)))->OffLine, OS); + + /* Seek for an alternate Service Processor. */ +#ifdef CONFIG_PM_SLEEP + if (CoreFreqK.ResumeFromSuspend == false) +#endif /* CONFIG_PM_SLEEP */ + { + if ((cpu == PUBLIC(RO(Proc))->Service.Core) + || (cpu == PUBLIC(RO(Proc))->Service.Thread)) + { + MatchPeerForDownService(&PUBLIC(RO(Proc))->Service, cpu); + + if (PUBLIC(RO(Proc))->Service.Core != cpu) + { + const unsigned int alt = PUBLIC(RO(Proc))->Service.Core; + + if (BITVAL(PRIVATE(OF(Core, AT(alt)))->Join.TSM, CREATED) == 1) + { + if ((BITVAL(PRIVATE(OF(Core, AT(alt)))->Join.TSM, STARTED) == 1) + && (Arch[PUBLIC(RO(Proc))->ArchID].Stop != NULL)) { + smp_call_function_single(alt, + Arch[PUBLIC(RO(Proc))->ArchID].Stop, + NULL, 1); + } + if ((BITVAL(PRIVATE(OF(Core, AT(alt)))->Join.TSM, STARTED) == 0) + && (Arch[PUBLIC(RO(Proc))->ArchID].Start != NULL)) { + smp_call_function_single(alt, + Arch[PUBLIC(RO(Proc))->ArchID].Start, + NULL, 0); + } + } + } + } else if ((cpu == PUBLIC(RO(Proc))->Service.Hybrid) + && (PUBLIC(RO(Proc))->Features.Hybrid)) + { + PUBLIC(RO(Proc))->Service.Hybrid = Seek_Topology_Hybrid_Core(cpu); + } + } + return 0; + } else + return -EINVAL; +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 10, 0) +static int CoreFreqK_HotPlug( struct notifier_block *nfb, + unsigned long action, + void *hcpu) +{ + unsigned int cpu = (unsigned long) hcpu, rc = 0; + + switch (action) { + case CPU_ONLINE: + case CPU_DOWN_FAILED: +/*TODO case CPU_ONLINE_FROZEN: */ + rc = CoreFreqK_HotPlug_CPU_Online(cpu); + break; + case CPU_DOWN_PREPARE: +/*TODO case CPU_DOWN_PREPARE_FROZEN: */ + rc = CoreFreqK_HotPlug_CPU_Offline(cpu); + break; + default: + break; + } + return NOTIFY_OK; +} + +static struct notifier_block CoreFreqK_notifier_block = { + .notifier_call = CoreFreqK_HotPlug, +}; +#endif /* KERNEL_VERSION(4, 10, 0) */ +#endif /* CONFIG_HOTPLUG_CPU */ + +static void SMBIOS_Collect(void) +{ +#ifdef CONFIG_DMI + struct { + enum dmi_field field; + char *recipient; + } dmi_collect[] = { + { DMI_BIOS_VENDOR, PUBLIC(RO(Proc))->SMB.BIOS.Vendor }, + { DMI_BIOS_VERSION, PUBLIC(RO(Proc))->SMB.BIOS.Version }, + { DMI_BIOS_DATE, PUBLIC(RO(Proc))->SMB.BIOS.Release }, + { DMI_SYS_VENDOR, PUBLIC(RO(Proc))->SMB.System.Vendor }, + { DMI_PRODUCT_NAME, PUBLIC(RO(Proc))->SMB.Product.Name }, + { DMI_PRODUCT_VERSION, PUBLIC(RO(Proc))->SMB.Product.Version}, + { DMI_PRODUCT_SERIAL, PUBLIC(RO(Proc))->SMB.Product.Serial }, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 18, 0) + { DMI_PRODUCT_SKU, PUBLIC(RO(Proc))->SMB.Product.SKU }, +#endif +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0) + { DMI_PRODUCT_FAMILY, PUBLIC(RO(Proc))->SMB.Product.Family }, +#endif + { DMI_BOARD_VENDOR, PUBLIC(RO(Proc))->SMB.Board.Vendor }, + { DMI_BOARD_NAME, PUBLIC(RO(Proc))->SMB.Board.Name }, + { DMI_BOARD_VERSION, PUBLIC(RO(Proc))->SMB.Board.Version }, + { DMI_BOARD_SERIAL, PUBLIC(RO(Proc))->SMB.Board.Serial } + }; + const size_t count = sizeof(dmi_collect) / sizeof(dmi_collect[0]); + size_t idx; + for (idx = 0; idx < count; idx++) { + const char *pInfo = dmi_get_system_info(dmi_collect[idx].field); + if ((pInfo != NULL) && (strlen(pInfo) > 0)) { + StrCopy(dmi_collect[idx].recipient, pInfo, MAX_UTS_LEN); + } + } +#endif /* CONFIG_DMI */ +} + +#ifdef CONFIG_DMI +static char *SMBIOS_String(const struct dmi_header *dh, u8 id) +{ + char *pStr = (char *) dh; + pStr += dh->length; + while (id > 1 && *pStr) { + pStr += strlen(pStr); + pStr++; + id--; + } + if (!*pStr) { + return NULL; + } + return pStr; +} + +#define safe_strim(pStr) (strim(pStr == NULL ? "" : pStr)) + +static void SMBIOS_Entries(const struct dmi_header *dh, void *priv) +{ + size_t *count = (size_t*) priv; + switch (dh->type) { + case DMI_ENTRY_PHYS_MEM_ARRAY: + { + const struct SMBIOS16 *entry = (struct SMBIOS16*) dh; + + StrFormat(PUBLIC(RO(Proc))->SMB.Phys.Memory.Array, MAX_UTS_LEN, + "Number Of Devices:%d\\Maximum Capacity:%lld kilobytes", + entry->number_devices, + entry->maximum_capacity >= 0x80000000 ? + entry->extended_capacity : entry->maximum_capacity); + } + break; + case DMI_ENTRY_MEM_DEVICE: + { + const struct SMBIOS17 *entry = (struct SMBIOS17*) dh; + if ((entry->length > 0x1a) && (entry->size > 0)) + { + if ((*count) < MC_MAX_DIMM) + { + const char *locator[2] = { + safe_strim(SMBIOS_String(dh, entry->device_locator_id)), + safe_strim(SMBIOS_String(dh, entry->bank_locator_id)) + }; + const size_t len[2] = { + strlen(locator[0]) > 0 ? strlen(locator[0]) : 0, + strlen(locator[1]) > 0 ? strlen(locator[1]) : 0 + }, prop = (len[0] + len[1]) > 0 ? (len[0] + len[1]) : 1; + + const int ratio[2] = { + DIV_ROUND_CLOSEST(len[0] * (MAX_UTS_LEN - (1+1)), prop), + DIV_ROUND_CLOSEST(len[1] * (MAX_UTS_LEN - (1+1)), prop) + }; + StrFormat(PUBLIC(RO(Proc))->SMB.Memory.Locator[(*count)], + MAX_UTS_LEN, "%.*s\\%.*s", + ratio[0], locator[0], + ratio[1], locator[1]); + + StrCopy(PUBLIC(RO(Proc))->SMB.Memory.Manufacturer[(*count)], + safe_strim(SMBIOS_String(dh, entry->manufacturer_id)), + MAX_UTS_LEN); + + StrCopy(PUBLIC(RO(Proc))->SMB.Memory.PartNumber[(*count)], + safe_strim(SMBIOS_String(dh, entry->part_number_id)), + MAX_UTS_LEN); + } + } + (*count) = (*count) + 1; + } + break; + } +} +#undef safe_strim +#endif /* CONFIG_DMI */ + +inline void SMBIOS_Decoder(void) +{ +#ifdef CONFIG_DMI + size_t count = 0; + dmi_walk(SMBIOS_Entries, &count); +#endif /* CONFIG_DMI */ +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 2, 0) +static char *CoreFreqK_DevNode(const struct device *dev, umode_t *mode) +#else +static char *CoreFreqK_DevNode(struct device *dev, umode_t *mode) +#endif +{ + UNUSED(dev); + + if (mode != NULL) { + (*mode) = 0600 ; /* Device access is crw------ */ + } + return NULL; +} + +static void CoreFreqK_Empty_Func_Level_Down(void) +{ +} + +static void CoreFreqK_Alloc_Features_Level_Down(void) +{ + pr_notice("CoreFreq: Unload\n"); +} + +static int CoreFreqK_Alloc_Features_Level_Up(INIT_ARG *pArg) +{ + pArg->Features = kmalloc(sizeof(FEATURES), GFP_KERNEL); + if (pArg->Features == NULL) + { + return -ENOMEM; + } else { + memset(pArg->Features, 0, sizeof(FEATURES)); + } + return 0; +} + +#define CoreFreqK_Query_Features_Level_Down CoreFreqK_Empty_Func_Level_Down + +static int CoreFreqK_Query_Features_Level_Up(INIT_ARG *pArg) +{ + int rc = 0; + + if ((CPU_Count > 0) && (CPU_Count <= CORE_COUNT) + && (CPU_Count <= NR_CPUS) + && ((ServiceProcessor == -1) || (ServiceProcessor >= CPU_Count))) + { /* Force Service to a Core with allocated memory */ + ServiceProcessor = CPU_Count - 1; + } + if (ServiceProcessor == -1) + { /* Query features on any processor. */ + pArg->localProcessor = get_cpu(); /* TODO(preempt_disable) */ + Query_Features(pArg); + put_cpu(); /* TODO(preempt_enable) */ + rc = pArg->rc; + } else { /* Query features on User selected processor. */ + if (ServiceProcessor >= 0) + { + pArg->localProcessor = ServiceProcessor; + if ((rc = smp_call_function_single(pArg->localProcessor, + Query_Features, + pArg, 1)) == 0) + { + rc = pArg->rc; + } + } else { + rc = -ENXIO; + } + } + if (rc == 0) + { + switch (CPU_Count) { + case -1: + { /* Rely on the operating system's cpu counting. */ + unsigned int OS_Count = num_present_cpus(); + if (pArg->SMT_Count != OS_Count) { + pArg->SMT_Count = OS_Count; + } + } + break; + default: + if ((CPU_Count > 0) && (CPU_Count <= CORE_COUNT) + && (CPU_Count <= NR_CPUS)) + { /* Hardware probing unless User override value */ + pArg->SMT_Count = (unsigned int) CPU_Count; + } + break; + } + } else { + rc = -ENXIO; + } + return rc; +} + +static void CoreFreqK_Alloc_Device_Level_Down(void) +{ + unregister_chrdev_region(CoreFreqK.mkdev, 1); +} + +static int CoreFreqK_Alloc_Device_Level_Up(INIT_ARG *pArg) +{ + UNUSED(pArg); + + CoreFreqK.kcdev = cdev_alloc(); + CoreFreqK.kcdev->ops = &CoreFreqK_fops; + CoreFreqK.kcdev->owner = THIS_MODULE; + + if (alloc_chrdev_region(&CoreFreqK.nmdev, 0, 1, DRV_FILENAME) >= 0) + { + return 0; + } else { + return -EBUSY; + } +} + +static void CoreFreqK_Make_Device_Level_Down(void) +{ + cdev_del(CoreFreqK.kcdev); +} + +static int CoreFreqK_Make_Device_Level_Up(INIT_ARG *pArg) +{ + UNUSED(pArg); + + CoreFreqK.Major = MAJOR(CoreFreqK.nmdev); + CoreFreqK.mkdev = MKDEV(CoreFreqK.Major, 0); + + if (cdev_add(CoreFreqK.kcdev, CoreFreqK.mkdev, 1) >= 0) + { + return 0; + } else { + return -EBUSY; + } +} + +static void CoreFreqK_Create_Device_Level_Down(void) +{ + device_destroy(CoreFreqK.clsdev, CoreFreqK.mkdev); + class_destroy(CoreFreqK.clsdev); +} + +static int CoreFreqK_Create_Device_Level_Up(INIT_ARG *pArg) +{ + struct device *tmpDev; + UNUSED(pArg); + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 4, 0) + CoreFreqK.clsdev = class_create(DRV_DEVNAME); +#else + CoreFreqK.clsdev = class_create(THIS_MODULE, DRV_DEVNAME); +#endif + CoreFreqK.clsdev->pm = COREFREQ_PM_OPS; + CoreFreqK.clsdev->devnode = CoreFreqK_DevNode; + + if ((tmpDev = device_create( CoreFreqK.clsdev, NULL, + CoreFreqK.mkdev, NULL, + DRV_DEVNAME)) != NULL) + { + return 0; + } else { + return -EBUSY; + } +} + +static void CoreFreqK_Alloc_Public_Level_Down(void) +{ + if (PUBLIC() != NULL) + { + kfree(PUBLIC()); + } +} + +static int CoreFreqK_Alloc_Public_Level_Up(INIT_ARG *pArg) +{ + const size_t coreSizeRO = sizeof(CORE_RO*) * pArg->SMT_Count, + coreSizeRW = sizeof(CORE_RW*) * pArg->SMT_Count, + publicSize = sizeof(KPUBLIC), + alloc_size = publicSize + coreSizeRO + coreSizeRW; + + if (((PUBLIC() = kmalloc(alloc_size, GFP_KERNEL)) != NULL)) + { + void *addr; + + memset(PUBLIC(), 0, alloc_size); + + addr = (void*) PUBLIC(); + addr = addr + publicSize; + PUBLIC(RO(Core)) = (CORE_RO**) addr; + + addr = (void*) PUBLIC(RO(Core)); + addr = addr + coreSizeRO; + PUBLIC(RW(Core)) = (CORE_RW**) addr; + + return 0; + } else{ + return -ENOMEM; + } +} + +static void CoreFreqK_Alloc_Private_Level_Down(void) +{ + if (PRIVATE() != NULL) + { + kfree(PRIVATE()); + } +} + +static int CoreFreqK_Alloc_Private_Level_Up(INIT_ARG *pArg) +{ + const unsigned long + privCoreSize = sizeof(struct PRIV_CORE_ST *) * pArg->SMT_Count, + privateSize = sizeof(KPRIVATE) + privCoreSize; + + if (((PRIVATE() = kmalloc(privateSize, GFP_KERNEL)) != NULL)) + { + memset(PRIVATE(), 0, privateSize); + + return 0; + } else { + return -ENOMEM; + } +} + +static void CoreFreqK_Alloc_Processor_RO_Level_Down(void) +{ + if (PUBLIC(RO(Proc)) != NULL) + { + kfree(PUBLIC(RO(Proc))); + } +} + +static int CoreFreqK_Alloc_Processor_RO_Level_Up(INIT_ARG *pArg) +{ + const unsigned long procSize = ROUND_TO_PAGES(sizeof(PROC_RO)); + UNUSED(pArg); + + if ( (PUBLIC(RO(Proc)) = kmalloc(procSize, GFP_KERNEL)) != NULL) + { + memset(PUBLIC(RO(Proc)), 0, procSize); + + return 0; + } else { + return -ENOMEM; + } +} + +static void CoreFreqK_Alloc_Processor_RW_Level_Down(void) +{ + if (PUBLIC(RW(Proc)) != NULL) + { + kfree(PUBLIC(RW(Proc))); + } +} + +static int CoreFreqK_Alloc_Processor_RW_Level_Up(INIT_ARG *pArg) +{ + const unsigned long procSize = ROUND_TO_PAGES(sizeof(PROC_RW)); + UNUSED(pArg); + + if ( (PUBLIC(RW(Proc)) = kmalloc(procSize, GFP_KERNEL)) != NULL) + { + memset(PUBLIC(RW(Proc)), 0, procSize); + + return 0; + } else { + return -ENOMEM; + } +} + +#define CoreFreqK_Scale_And_Compute_Level_Down CoreFreqK_Empty_Func_Level_Down + +static int CoreFreqK_Scale_And_Compute_Level_Up(INIT_ARG *pArg) +{ + SET_FOOTPRINT(PUBLIC(RO(Proc))->FootPrint, \ + MAX_FREQ_HZ, \ + CORE_COUNT, \ + TASK_ORDER, \ + COREFREQ_MAJOR, \ + COREFREQ_MINOR, \ + COREFREQ_REV ); + + PUBLIC(RO(Proc))->CPU.Count = pArg->SMT_Count; + /* PreCompute SysGate memory allocation. */ + PUBLIC(RO(Proc))->Gate.ReqMem.Size = sizeof(SYSGATE_RO); + + PUBLIC(RO(Proc))->Gate.ReqMem.Order = \ + get_order(PUBLIC(RO(Proc))->Gate.ReqMem.Size); + + PUBLIC(RO(Proc))->Registration.AutoClock = AutoClock; + PUBLIC(RO(Proc))->Registration.Experimental = Experimental; + + Compute_Interval(); + + memcpy(&PUBLIC(RO(Proc))->Features, pArg->Features, sizeof(FEATURES)); + + /* Initialize default uArch's codename with the CPUID brand. */ + Arch[GenuineArch].Architecture.Brand[0] = \ + PUBLIC(RO(Proc))->Features.Info.Vendor.ID; + /* Initialize with any hypervisor found so far. */ + PUBLIC(RO(Proc))->HypervisorID = pArg->HypervisorID; + return 0; +} + +static void CoreFreqK_Alloc_Public_Cache_Level_Down(void) +{ + if (PUBLIC(OF(Cache)) != NULL) + { + kmem_cache_destroy(PUBLIC(OF(Cache))); + } +} + +static int CoreFreqK_Alloc_Public_Cache_Level_Up(INIT_ARG *pArg) +{ + const unsigned long cacheSize = KMAX( ROUND_TO_PAGES(sizeof(CORE_RO)), + ROUND_TO_PAGES(sizeof(CORE_RW)) ); + UNUSED(pArg); + + if ( (PUBLIC(OF(Cache)) = kmem_cache_create( "corefreqk-pub", + cacheSize, 0, + SLAB_HWCACHE_ALIGN, + NULL ) ) != NULL) + { + return 0; + } else { + return -ENOMEM; + } +} + +static void CoreFreqK_Alloc_Private_Cache_Level_Down(void) +{ + if (PRIVATE(OF(Cache)) != NULL) + { + kmem_cache_destroy(PRIVATE(OF(Cache))); + } +} + +static int CoreFreqK_Alloc_Private_Cache_Level_Up(INIT_ARG *pArg) +{ + const unsigned long joinSize = \ + ROUND_TO_PAGES(sizeof(struct PRIV_CORE_ST)); + UNUSED(pArg); + + if ( (PRIVATE(OF(Cache)) = kmem_cache_create( "corefreqk-priv", + joinSize, 0, + SLAB_HWCACHE_ALIGN, + NULL ) ) != NULL) + { + return 0; + } else { + return -ENOMEM; + } +} + +static void CoreFreqK_Alloc_Per_CPU_Level_Down(void) +{ + unsigned int cpu; + for (cpu = 0; cpu < PUBLIC(RO(Proc))->CPU.Count; cpu++) + { + if (PUBLIC(OF(Cache)) != NULL) + { + if (PUBLIC(RO(Core, AT(cpu))) != NULL) { + kmem_cache_free(PUBLIC(OF(Cache)), PUBLIC(RO(Core, AT(cpu)))); + } + if (PUBLIC(RW(Core, AT(cpu))) != NULL) { + kmem_cache_free(PUBLIC(OF(Cache)), PUBLIC(RW(Core, AT(cpu)))); + } + } + if (PRIVATE(OF(Cache)) != NULL) + { + if (PRIVATE(OF(Core, AT(cpu))) != NULL) { + kmem_cache_free(PRIVATE(OF(Cache)), PRIVATE(OF(Core, AT(cpu)))); + } + } + } +} + +static int CoreFreqK_Alloc_Per_CPU_Level_Up(INIT_ARG *pArg) +{ + const unsigned long cacheSize = KMAX( ROUND_TO_PAGES(sizeof(CORE_RO)), + ROUND_TO_PAGES(sizeof(CORE_RW)) ); + const unsigned long joinSize = \ + ROUND_TO_PAGES(sizeof(struct PRIV_CORE_ST)); + unsigned int cpu; + int rc = 0; + UNUSED(pArg); + + for (cpu = 0; cpu < PUBLIC(RO(Proc))->CPU.Count; cpu++) + { + void *kcache = NULL; + + kcache = kmem_cache_alloc(PUBLIC(OF(Cache)), GFP_KERNEL); + if (kcache != NULL) { + memset(kcache, 0, cacheSize); + PUBLIC(RO(Core, AT(cpu))) = kcache; + } else { + rc = -ENOMEM; + break; + } + kcache = kmem_cache_alloc(PUBLIC(OF(Cache)), GFP_KERNEL); + if (kcache != NULL) { + memset(kcache, 0, cacheSize); + PUBLIC(RW(Core, AT(cpu))) = kcache; + } else { + rc = -ENOMEM; + break; + } + kcache = kmem_cache_alloc(PRIVATE(OF(Cache)), GFP_KERNEL); + if (kcache != NULL) { + memset(kcache, 0, joinSize); + PRIVATE(OF(Core, AT(cpu))) = kcache; + } else { + rc = -ENOMEM; + break; + } + if (rc == 0) { + BITCLR(LOCKLESS, PUBLIC(RW(Core, AT(cpu)))->Sync.V, NTFY); + + PUBLIC(RO(Core, AT(cpu)))->Bind = cpu; + } + } + return rc; +} + +static void CoreFreqK_Ignition_Level_Down(void) +{ + CoreFreqK_UnRegister_ClockSource(); + CoreFreqK_UnRegister_Governor(); + CoreFreqK_UnRegister_CPU_Freq(); + CoreFreqK_UnRegister_CPU_Idle(); + CoreFreqK_UnRegister_NMI(); + +#ifdef CONFIG_HOTPLUG_CPU + #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 10, 0) + unregister_hotcpu_notifier(&CoreFreqK_notifier_block); + #else /* KERNEL_VERSION(4, 10, 0) */ + if ( !(PUBLIC(RO(Proc))->Registration.HotPlug < 0) ) + { + cpuhp_remove_state_nocalls(PUBLIC(RO(Proc))->Registration.HotPlug); + } + #endif /* KERNEL_VERSION(4, 10, 0) */ +#endif /* CONFIG_HOTPLUG_CPU */ + + Controller_Stop(1); + Controller_Exit(); + + if (PUBLIC(OF(Gate)) != NULL) + { + free_pages_exact(PUBLIC(OF(Gate)), PUBLIC(RO(Proc))->Gate.ReqMem.Size); + } +} + +static int CoreFreqK_Ignition_Level_Up(INIT_ARG *pArg) +{ + /* Is an architecture identifier requested by user ? */ + if ( (ArchID != -1) && (ArchID >= 0) && (ArchID < ARCHITECTURES) ) + { + PUBLIC(RO(Proc))->ArchID = ArchID; + } else { + PUBLIC(RO(Proc))->ArchID = SearchArchitectureID(); + } + /* Set the uArch's name with the first found codename */ + StrCopy(PUBLIC(RO(Proc))->Architecture, + CodeName[Arch[PUBLIC(RO(Proc))->ArchID].Architecture.CN], + CODENAME_LEN); + + StrCopy(PUBLIC(RO(Proc))->Features.Info.Brand, + Arch[PUBLIC(RO(Proc))->ArchID].Architecture.Brand[0], + BRAND_SIZE); + /* Check if the Processor is actually virtualized ? */ + #ifdef CONFIG_XEN + if (xen_pv_domain() || xen_hvm_domain()) + { + PUBLIC(RO(Proc))->HypervisorID = HYPERV_XEN; + PUBLIC(RO(Proc))->Features.Info.Hypervisor.CRC = CRC_KVM; + StrCopy(PUBLIC(RO(Proc))->Features.Info.Hypervisor.ID, + VENDOR_KVM, 12 + 4); + } + #endif /* CONFIG_XEN */ + + PUBLIC(RO(Proc))->thermalFormula = \ + Arch[PUBLIC(RO(Proc))->ArchID].thermalFormula; + + PUBLIC(RO(Proc))->voltageFormula = \ + Arch[PUBLIC(RO(Proc))->ArchID].voltageFormula; + + PUBLIC(RO(Proc))->powerFormula = \ + Arch[PUBLIC(RO(Proc))->ArchID].powerFormula; + + CoreFreqK_Thermal_Scope(ThermalScope); + CoreFreqK_Voltage_Scope(VoltageScope); + CoreFreqK_Power_Scope(PowerScope); + + /* Copy various SMBIOS data [version 3.2] */ + SMBIOS_Collect(); + SMBIOS_Decoder(); + /* Guess virtualization from SMBIOS strings */ + if ((strncmp( PUBLIC(RO(Proc))->SMB.System.Vendor, + "QEMU", + MAX_UTS_LEN) == 0) + + || (strncmp( PUBLIC(RO(Proc))->SMB.Product.Name, + "QEMU Virtual Machine", + MAX_UTS_LEN) == 0)) + { + PUBLIC(RO(Proc))->HypervisorID = HYPERV_KVM; + PUBLIC(RO(Proc))->Features.Info.Hypervisor.CRC = CRC_KVM; + StrCopy(PUBLIC(RO(Proc))->Features.Info.Hypervisor.ID, + VENDOR_KVM, 12 + 4); + } + else if ((strncmp(PUBLIC(RO(Proc))->SMB.BIOS.Version, + "VirtualBox", + MAX_UTS_LEN) == 0) + || (strncmp(PUBLIC(RO(Proc))->SMB.Board.Name, + "VirtualBox", + MAX_UTS_LEN) == 0) + || (strncmp(PUBLIC(RO(Proc))->SMB.Product.Family, + "Virtual Machine", + MAX_UTS_LEN) == 0)) + { + PUBLIC(RO(Proc))->HypervisorID = HYPERV_VBOX; + PUBLIC(RO(Proc))->Features.Info.Hypervisor.CRC = CRC_VBOX; + StrCopy(PUBLIC(RO(Proc))->Features.Info.Hypervisor.ID, + VENDOR_VBOX, 12 + 4); + } + if ((PUBLIC(RO(Proc))->HypervisorID != HYPERV_NONE) + && (PUBLIC(RO(Proc))->HypervisorID != BARE_METAL)) { + if (PUBLIC(RO(Proc))->Features.Hyperv == 0) { + PUBLIC(RO(Proc))->Features.Hyperv = 1; + } + } + /* Initialize the CoreFreq controller */ + Controller_Init(); + + /* Seek for an appropriate service processor */ + MatchPeerForDefaultService( &PUBLIC(RO(Proc))->Service, + pArg->localProcessor ); + + /* Register the Idle & Frequency sub-drivers */ + CoreFreqK_Register_CPU_Idle(); + CoreFreqK_Register_CPU_Freq(); + CoreFreqK_Register_Governor(); + + if (NMI_Disable == 0) { + CoreFreqK_Register_NMI(); + } + + pr_info("CoreFreq(%u:%d:%d):" \ + " Processor [%2X%1X_%1X%1X]" \ + " Architecture [%s] %3s [%u/%u]\n", + PUBLIC(RO(Proc))->Service.Core, + PUBLIC(RO(Proc))->Service.Thread, + PUBLIC(RO(Proc))->Service.Hybrid, + PUBLIC(RO(Proc))->Features.Info.Signature.ExtFamily, + PUBLIC(RO(Proc))->Features.Info.Signature.Family, + PUBLIC(RO(Proc))->Features.Info.Signature.ExtModel, + PUBLIC(RO(Proc))->Features.Info.Signature.Model, + PUBLIC(RO(Proc))->Architecture, + PUBLIC(RO(Proc))->Features.HTT_Enable ? "SMT" : "CPU", + PUBLIC(RO(Proc))->CPU.OnLine, + PUBLIC(RO(Proc))->CPU.Count); + + PUBLIC(RO(Proc))->Registration.PCI = \ + CoreFreqK_ProbePCI(Arch[PUBLIC(RO(Proc))->ArchID].PCI_ids, + CoreFreqK_ResetChip, CoreFreqK_AppendChip) == 0; + + Controller_Start(0); + +#ifdef CONFIG_HOTPLUG_CPU + #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 6, 0) + /* Always returns zero (kernel/notifier.c) */ + PUBLIC(RO(Proc))->Registration.HotPlug = \ + register_hotcpu_notifier(&CoreFreqK_notifier_block); + #else /* Continue with or without cpu hot-plugging. */ + PUBLIC(RO(Proc))->Registration.HotPlug = \ + cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, + "corefreqk/cpu:online", + CoreFreqK_HotPlug_CPU_Online, + CoreFreqK_HotPlug_CPU_Offline); + #endif /* KERNEL_VERSION(4, 6, 0) */ +#endif /* CONFIG_HOTPLUG_CPU */ + + return 0; +} + +#define CoreFreqK_User_Ops_Level_Down CoreFreqK_Empty_Func_Level_Down + +static int CoreFreqK_User_Ops_Level_Up(INIT_ARG *pArg) +{ + UNUSED(pArg); + + if (Register_ClockSource == COREFREQ_TOGGLE_ON) + { + Controller_Stop(1); + Controller_Start(1); + CoreFreqK_Register_ClockSource(PUBLIC(RO(Proc))->Service.Core); + } + if (Ratio_HWP_Count > 0) + { + CLOCK_ARG clockMod; + enum RATIO_BOOST boost; + + Controller_Stop(1); + for (boost = 0; boost < Ratio_HWP_Count; boost++) + { + if (Ratio_HWP[boost] >= 0) + { + long rc = RC_SUCCESS; + + switch (boost) { + case BOOST(HWP_MIN) - BOOST(HWP_MIN): + if (Arch[PUBLIC(RO(Proc))->ArchID].ClockMod) { + clockMod.Ratio = Ratio_HWP[boost]; + clockMod.cpu = -1; + clockMod.NC = CLOCK_MOD_HWP_MIN; + rc = Arch[PUBLIC(RO(Proc))->ArchID].ClockMod(&clockMod); + } + break; + case BOOST(HWP_MAX) - BOOST(HWP_MIN): + if (Arch[PUBLIC(RO(Proc))->ArchID].ClockMod) { + clockMod.Ratio = Ratio_HWP[boost]; + clockMod.cpu = -1; + clockMod.NC = CLOCK_MOD_HWP_MAX; + rc = Arch[PUBLIC(RO(Proc))->ArchID].ClockMod(&clockMod); + } + break; + case BOOST(HWP_TGT) - BOOST(HWP_MIN): + if (Arch[PUBLIC(RO(Proc))->ArchID].ClockMod) { + clockMod.Ratio = Ratio_HWP[boost]; + clockMod.cpu = -1; + clockMod.NC = CLOCK_MOD_HWP_TGT; + rc = Arch[PUBLIC(RO(Proc))->ArchID].ClockMod(&clockMod); + } + break; + default: + rc = -RC_UNIMPLEMENTED; + break; + }; + if (rc < RC_SUCCESS) { + pr_warn("CoreFreq: " \ + "'Ratio_HWP' at #%d Execution failure code %ld\n", + boost, rc); + } + } + } + Controller_Start(1); + + RESET_ARRAY(Ratio_HWP, Ratio_HWP_Count, -1); + Ratio_HWP_Count = 0; + } + if (Ratio_Boost_Count > 0) + { + CLOCK_ARG clockMod; + enum RATIO_BOOST boost; + + Controller_Stop(1); + for (boost = 0; boost < Ratio_Boost_Count; boost++) + { + if (Ratio_Boost[boost] >= 0) + { + long rc = RC_SUCCESS; + + switch (boost) { + case BOOST(1C) - BOOST(1C) ... BOOST(1C) - BOOST(18C): + if (Arch[PUBLIC(RO(Proc))->ArchID].TurboClock) { + clockMod.Ratio = Ratio_Boost[boost]; + clockMod.cpu = -1; + clockMod.NC = BOOST(SIZE) - BOOST(18C) - boost; + rc = Arch[PUBLIC(RO(Proc))->ArchID].TurboClock(&clockMod); + } + break; + default: + rc = -RC_UNIMPLEMENTED; + break; + }; + if (rc < RC_SUCCESS) { + pr_warn("CoreFreq: " \ + "'Ratio_Boost' at #%d Execution failure code %ld\n", + boost, rc); + } + } + } + Controller_Start(1); + + RESET_ARRAY(Ratio_Boost, Ratio_Boost_Count, -1); + Ratio_Boost_Count = 0; + } + if (Ratio_PPC >= 0) + { + long rc = RC_SUCCESS; + + if (Arch[PUBLIC(RO(Proc))->ArchID].ClockMod) { + CLOCK_ARG clockMod={.Ratio = Ratio_PPC, .cpu = -1, .NC = CLOCK_MOD_TGT}; + + Controller_Stop(1); + rc = Arch[PUBLIC(RO(Proc))->ArchID].ClockMod(&clockMod); + Controller_Start(0); + } else { + rc = -RC_UNIMPLEMENTED; + } + if (rc < RC_SUCCESS) { + pr_warn("CoreFreq: 'Ratio_PPC' Execution failure code %ld\n", rc); + } + Ratio_PPC = -1; + } + return 0; +} + +enum RUN_LEVEL { + Alloc_Features_Level, + Query_Features_Level, + Alloc_Device_Level, + Make_Device_Level, + Create_Device_Level, + Alloc_Public_Level, + Alloc_Private_Level, + Alloc_Processor_RO_Level, + Alloc_Processor_RW_Level, + Scale_And_Compute_Level, + Alloc_Public_Cache_Level, + Alloc_Private_Cache_Level, + Alloc_Per_CPU_Level, + Ignition_Level, + User_Ops_Level, + Running_Level +}; + +static enum RUN_LEVEL RunLevel = Alloc_Features_Level; + +#define COREFREQ_RUN( _level, _action ) CoreFreqK_##_level##_##_action + +static void CoreFreqK_ShutDown(void) +{ + void (*LevelFunc[Running_Level])(void) = { + COREFREQ_RUN(Alloc_Features_Level, Down), + COREFREQ_RUN(Query_Features_Level, Down), + COREFREQ_RUN(Alloc_Device_Level, Down), + COREFREQ_RUN(Make_Device_Level, Down), + COREFREQ_RUN(Create_Device_Level, Down), + COREFREQ_RUN(Alloc_Public_Level, Down), + COREFREQ_RUN(Alloc_Private_Level, Down), + COREFREQ_RUN(Alloc_Processor_RO_Level, Down), + COREFREQ_RUN(Alloc_Processor_RW_Level, Down), + COREFREQ_RUN(Scale_And_Compute_Level, Down), + COREFREQ_RUN(Alloc_Public_Cache_Level, Down), + COREFREQ_RUN(Alloc_Private_Cache_Level, Down), + COREFREQ_RUN(Alloc_Per_CPU_Level, Down), + COREFREQ_RUN(Ignition_Level, Down), + COREFREQ_RUN(User_Ops_Level, Down) + }; + + do + { + RunLevel--; + LevelFunc[RunLevel](); + } while (RunLevel != Alloc_Features_Level) ; +} + +static int CoreFreqK_StartUp(void) +{ + int (*LevelFunc[Running_Level])(INIT_ARG *pArg) = { + COREFREQ_RUN(Alloc_Features_Level, Up), + COREFREQ_RUN(Query_Features_Level, Up), + COREFREQ_RUN(Alloc_Device_Level, Up), + COREFREQ_RUN(Make_Device_Level, Up), + COREFREQ_RUN(Create_Device_Level, Up), + COREFREQ_RUN(Alloc_Public_Level, Up), + COREFREQ_RUN(Alloc_Private_Level, Up), + COREFREQ_RUN(Alloc_Processor_RO_Level, Up), + COREFREQ_RUN(Alloc_Processor_RW_Level, Up), + COREFREQ_RUN(Scale_And_Compute_Level, Up), + COREFREQ_RUN(Alloc_Public_Cache_Level, Up), + COREFREQ_RUN(Alloc_Private_Cache_Level, Up), + COREFREQ_RUN(Alloc_Per_CPU_Level, Up), + COREFREQ_RUN(Ignition_Level, Up), + COREFREQ_RUN(User_Ops_Level, Up) + }; + INIT_ARG iArg = { + .Features = NULL, + .SMT_Count = 0, .localProcessor = 0, .rc = 0 + }; + int rc = 0; + + do + { + rc = LevelFunc[RunLevel](&iArg); + RunLevel++; + } while (RunLevel != Running_Level && rc == 0) ; + + /* Free any initialization memory allocation. */ + if (iArg.Features != NULL) + { + kfree(iArg.Features); + } + return rc; +} + +#undef COREFREQ_RUN +#undef CoreFreqK_Scale_And_Compute_Level_Down +#undef CoreFreqK_Query_Features_Level_Down +#undef COREFREQ_PM_OPS + +static int __init CoreFreqK_Init(void) +{ + int rc = CoreFreqK_StartUp(); + + if (rc != 0) { + CoreFreqK_ShutDown(); + } + return rc; +} + +static void __exit CoreFreqK_Exit(void) +{ + CoreFreqK_ShutDown(); +} + +module_init(CoreFreqK_Init) +module_exit(CoreFreqK_Exit) diff --git a/aarch64/corefreqk.h b/aarch64/corefreqk.h new file mode 100644 index 00000000..07039882 --- /dev/null +++ b/aarch64/corefreqk.h @@ -0,0 +1,1300 @@ +/* + * CoreFreq + * Copyright (C) 2015-2024 CYRIL COURTIAT + * Licenses: GPL2 + */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 17, 0) + #define sys_reg(op0, op1, crn, crm, op2) ({ \ + UNUSED(op0); \ + UNUSED(op1); \ + UNUSED(crn); \ + UNUSED(crm); \ + UNUSED(op2); \ + }) +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0) + #define SysRegRead(_reg) read_sysreg_s(_reg) + #define SysRegWrite(_val, _reg) write_sysreg_s(_val, _reg) +#else + #define SysRegRead(_reg) ({ \ + UNUSED(_reg); \ + 0; \ + }) + #define SysRegWrite(_val, _reg) ({ \ + UNUSED(_val); \ + UNUSED(_reg); \ + }) +#endif + +#define Atomic_Read_VPMC(_lock, _dest, _src) \ +{ \ +/* __asm__ volatile \ + ( \ + "xorq %%rax, %%rax" "\n\t" \ + _lock "cmpxchg %%rax, %[src]" "\n\t" \ + "movq %%rax, %[dest]" \ + : [dest] "=m" (_dest) \ + : [src] "m" (_src) \ + : "%rax", "cc", "memory" \ + ); */ \ +} + +#define Atomic_Add_VPMC(_lock, _dest, _src) \ +{ \ +/* __asm__ volatile \ + ( \ + "xorq %%rax, %%rax" "\n\t" \ + _lock "cmpxchg %%rax, %[src]" "\n\t" \ + "addq %%rax, %[dest]" \ + : [dest] "=m" (_dest) \ + : [src] "m" (_src) \ + : "%rax", "cc", "memory" \ + ); */ \ +} + +#define ASM_CODE_RDMSR(_msr, _reg) \ + "# Read PMU counter." "\n\t" \ + "mrs " #_reg ", " #_msr "\n\t" + +#define ASM_RDMSR(_msr, _reg) ASM_CODE_RDMSR(_msr, _reg) + +#define ASM_COUNTERx1( _reg0, _reg1, \ + _tsc_inst, mem_tsc, \ + _msr1, _mem1) \ +__asm__ volatile \ +( \ + _tsc_inst(_reg0) \ + "# Store values into memory." "\n\t" \ + "str " #_reg0 ", %0" "\n\t" \ + "str " #_reg1 ", %1" \ + : "=m" (mem_tsc), "=m" (_mem1) \ + : \ + : "%" #_reg0"", "%" #_reg1"", \ + "cc", "memory" \ +); + + +#define ASM_COUNTERx2( _reg0, _reg1, _reg2, \ + _tsc_inst, mem_tsc, \ + _msr1, _mem1, _msr2, _mem2) \ +__asm__ volatile \ +( \ + _tsc_inst(_reg0) \ + ASM_RDMSR(_msr1, _reg1) \ + ASM_RDMSR(_msr2, _reg2) \ + "# Store values into memory." "\n\t" \ + "str " #_reg0 ", %0" "\n\t" \ + "str " #_reg1 ", %1" "\n\t" \ + "str " #_reg2 ", %2" \ + : "=m" (mem_tsc), "=m" (_mem1), "=m" (_mem2) \ + : \ + : "%" #_reg0"", "%" #_reg1"", "%" #_reg2"", \ + "cc", "memory" \ +); + + +#define ASM_COUNTERx3( _reg0, _reg1, _reg2, _reg3, \ + _tsc_inst, mem_tsc, \ + _msr1, _mem1, _msr2, _mem2, _msr3, _mem3) \ +__asm__ volatile \ +( \ + _tsc_inst(_reg0) \ + ASM_RDMSR(_msr1, _reg1) \ + ASM_RDMSR(_msr2, _reg2) \ + ASM_RDMSR(_msr3, _reg3) \ + "# Store values into memory." "\n\t" \ + "str " #_reg0 ", %0" "\n\t" \ + "str " #_reg1 ", %1" "\n\t" \ + "str " #_reg2 ", %2" "\n\t" \ + "str " #_reg3 ", %3" \ + : "=m" (mem_tsc), "=m" (_mem1), "=m" (_mem2), "=m" (_mem3) \ + : \ + : "%" #_reg0"", "%" #_reg1"", "%" #_reg2"", "%" #_reg3"", \ + "cc", "memory" \ +); + +#define RDTSC_COUNTERx1(mem_tsc, ...) \ +ASM_COUNTERx1(x11, x12, ASM_RDTSC, mem_tsc, __VA_ARGS__) + +#define RDTSC_COUNTERx2(mem_tsc, ...) \ +ASM_COUNTERx2(x11, x12, x13, ASM_RDTSC, mem_tsc, __VA_ARGS__) + +#define RDTSC_COUNTERx3(mem_tsc, ...) \ +ASM_COUNTERx3(x11, x12, x13, x14, ASM_RDTSC, mem_tsc, __VA_ARGS__) + +/* Manufacturers Identifier Strings. */ +#define VENDOR_RESERVED "Reserved" +#define VENDOR_ARM "Arm" +#define VENDOR_BROADCOM "Broadcom" +#define VENDOR_CAVIUM "Cavium" +#define VENDOR_DEC "DEC" /* Digital Equipment Corporation */ +#define VENDOR_FUJITSU "Fujitsu" +#define VENDOR_INFINEON "Infineon" +#define VENDOR_MOTOROLA "Motorola" /* Freescale Semiconductor Inc. */ +#define VENDOR_NVIDIA "NVIDIA" +#define VENDOR_APM "APM" /* Applied Micro Circuits Corporation */ +#define VENDOR_QUALCOMM "Qualcomm" +#define VENDOR_MARVELL "Marvell" +#define VENDOR_INTEL "Intel" +#define VENDOR_AMPERE "Ampere" /* Ampere Computing */ + +#define VENDOR_KVM "TCGTGTCGCGTC" +#define VENDOR_VBOX "VBoxVBoxVBox" +#define VENDOR_KBOX "KVMKM" +#define VENDOR_VMWARE "VMwawarereVM" +#define VENDOR_HYPERV "Micrt Hvosof" + +#define LATCH_NONE 0b000000000000 +#define LATCH_TGT_RATIO_UNLOCK 0b000000000001 /* TgtRatioUnlocked */ +#define LATCH_CLK_RATIO_UNLOCK 0b000000000010 /* ClkRatioUnlocked */ +#define LATCH_TURBO_UNLOCK 0b000000000100 /* TurboUnlocked */ +#define LATCH_UNCORE_UNLOCK 0b000000001000 /* UncoreUnlocked */ +#define LATCH_OTHER_CAPABLE 0b000000010000 /* Other Capability */ + +typedef struct { + char **Brand; + unsigned int Boost[2]; + THERMAL_PARAM Param; + unsigned int CodeNameIdx : 8-0, + TgtRatioUnlocked: 9-8, /* */ + ClkRatioUnlocked: 11-9, /* */ + TurboUnlocked : 12-11, /* */ + UncoreUnlocked : 13-12, /* */ + Other_Capable : 14-13, /* */ + _UnusedLatchBits: 20-14, + /* ----- */ + Latch : 32-20; +} PROCESSOR_SPECIFIC; + +typedef struct { + FEATURES *Features; + unsigned int SMT_Count, + localProcessor; + enum HYPERVISOR HypervisorID; + signed int rc; +} INIT_ARG; + +typedef struct { /* V[0] stores the previous TSC */ + unsigned long long V[2]; /* V[1] stores the current TSC */ +} TSC_STRUCT; + +#define OCCURRENCES 4 +/* OCCURRENCES x 2 (TSC values) needs a 64-byte cache line size. */ +#define STRUCT_SIZE (OCCURRENCES * sizeof(TSC_STRUCT)) + +typedef struct { + TSC_STRUCT *TSC[2]; + CLOCK Clock; +} COMPUTE_ARG; + +typedef struct +{ + PROC_RO *Proc_RO; + PROC_RW *Proc_RW; + SYSGATE_RO *Gate; + struct kmem_cache *Cache; + CORE_RO **Core_RO; + CORE_RW **Core_RW; +} KPUBLIC; + +enum { CREATED, STARTED, MUSTFWD }; + +typedef struct +{ + struct hrtimer Timer; +/* + TSM: Timer State Machine + CREATED: 1-0 + STARTED: 2-1 + MUSTFWD: 3-2 +*/ + Bit64 TSM __attribute__ ((aligned (8))); +} JOIN; + +typedef struct +{ + PROCESSOR_SPECIFIC *Specific; + + struct kmem_cache *Cache; + + struct PRIV_CORE_ST { + JOIN Join; + + union SAVE_AREA_CORE { + struct + { + PMCR PMCR; + PMSELR PMSELR; + PMXEVTYPER PMTYPE[3]; + PMCCFILTR PMCCFILTR; + PMCNTENSET PMCNTEN; + }; + } SaveArea; +#ifdef CONFIG_CPU_FREQ + struct cpufreq_policy FreqPolicy; +#endif /* CONFIG_CPU_FREQ */ + } *Core[]; +} KPRIVATE; + +struct SMBIOS16 +{ /* DMTF 2.7.1 */ + u8 type; /* 0x00 BYTE */ + u8 length; /* 0x01 BYTE */ + u16 handle; /* 0x02 WORD */ + u8 location; /* 0x04 BYTE */ + u8 use; /* 0x05 BYTE */ + u8 error_correction; /* 0x06 BYTE */ + u32 maximum_capacity; /* 0x07 DWORD */ + u16 error_handle; /* 0x0b WORD */ + u16 number_devices; /* 0x0d WORD */ + u64 extended_capacity; /* 0x0f QWORD */ +} __attribute__((__packed__))s; + +struct SMBIOS17 +{ /* DMTF 2.7.1 */ + u8 type; /* 0x00 BYTE */ + u8 length; /* 0x01 BYTE */ + u16 handle; /* 0x02 WORD */ + u16 phys_mem_array_handle; /* 0x04 WORD */ + u16 mem_err_info_handle; /* 0x06 WORD */ + u16 total_width; /* 0x08 WORD */ + u16 data_width; /* 0x0a WORD */ + u16 size; /* 0x0c WORD */ + u8 form_factor; /* 0x0e BYTE */ + u8 device_set; /* 0x0f BYTE */ + u8 device_locator_id; /* 0x10 BYTE STRING */ + u8 bank_locator_id; /* 0x11 BYTE STRING */ + u8 memory_type; /* 0x12 BYTE */ + u16 type_detail; /* 0x13 WORD */ + u16 speed; /* 0x15 WORD */ + u8 manufacturer_id; /* 0x17 BYTE STRING */ + u8 serial_number_id; /* 0x18 BYTE STRING */ + u8 asset_tag_id; /* 0x19 BYTE STRING */ + u8 part_number_id; /* 0x1a BYTE STRING */ + u8 attributes; /* 0x1b BYTE */ + u32 extended_size; /* 0x1c DWORD */ + u16 conf_mem_clk_speed; /* 0x20 WORD */ + /* DMTF 3.2.0 */ + u16 min_voltage; /* 0x22 WORD */ + u16 max_voltage; /* 0x24 WORD */ + u16 configured_voltage; /* 0x26 WORD */ + u8 memory_tech; /* 0x28 BYTE */ + u16 memory_capability; /* 0x29 WORD */ + u8 firmware_version_id; /* 0x2b BYTE STRING */ + u16 manufacturer_spd; /* 0x2c WORD */ + u16 product_spd; /* 0x2e WORD */ + u16 controller_mfr_spd; /* 0x30 WORD */ + u16 controller_pdt_spd; /* 0x32 WORD */ + u64 non_volatile_size; /* 0x34 QWORD */ + u64 volatile_size; /* 0x3c QWORD */ + u64 cache_size; /* 0x44 QWORD */ + u64 logical_size; /* 0x4c QWORD */ + /* DMTF 3.3.0 */ + u32 extended_speed; /* 0x54 DWORD */ + u32 extended_conf_speed; /* 0x58 DWORD */ +} __attribute__((__packed__)); + +#if !defined(RHEL_MAJOR) + #define RHEL_MAJOR 0 +#endif + +#if !defined(RHEL_MINOR) + #define RHEL_MINOR 0 +#endif + +typedef struct { + char *Name, + Desc[CPUIDLE_NAME_LEN]; + unsigned long flags; + unsigned short Latency, + Residency; +} IDLE_STATE; + +typedef struct { + IDLE_STATE *IdleState; + unsigned int (*GetFreq)(unsigned int cpu); + void (*SetTarget)(void *arg); +} SYSTEM_DRIVER; + +typedef struct { + char **Brand; + enum CODENAME CN; +} ARCH_ST; + +typedef struct +{ + struct SIGNATURE Signature; + void (*Query)(unsigned int cpu); + void (*Update)(void *arg); /* Must be static */ + void (*Start)(void *arg); /* Must be static */ + void (*Stop)(void *arg); /* Must be static */ + void (*Exit)(void); + void (*Timer)(unsigned int cpu); + CLOCK (*BaseClock)(unsigned int ratio); + long (*ClockMod)(CLOCK_ARG *pClockMod); + long (*TurboClock)(CLOCK_ARG *pClockMod); + enum THERMAL_FORMULAS thermalFormula; + enum VOLTAGE_FORMULAS voltageFormula; + enum POWER_FORMULAS powerFormula; + struct pci_device_id *PCI_ids; + struct { + void (*Start)(void *arg); /* Must be static */ + void (*Stop)(void *arg); /* Must be static */ + long (*ClockMod)(CLOCK_ARG *pClockMod); + } Uncore; + PROCESSOR_SPECIFIC *Specific; + SYSTEM_DRIVER SystemDriver; + ARCH_ST Architecture; +} ARCH; + +static CLOCK BaseClock_GenericMachine(unsigned int ratio) ; +static void Query_GenericMachine(unsigned int cpu) ; +static void PerCore_GenericMachine(void *arg) ; +static void Start_GenericMachine(void *arg) ; +static void Stop_GenericMachine(void *arg) ; +static void InitTimer_GenericMachine(unsigned int cpu) ; +static void Query_DynamIQ(unsigned int cpu) ; +/* [Void] */ +#define _Void_Signature {.ExtFamily=0x00, .Family=0x0, .ExtModel=0x0, .Model=0x0} +#define _Cortex_A34 {.ExtFamily=0xd0, .Family=0x2, .ExtModel=0x0, .Model=0x8} +#define _Cortex_A35 {.ExtFamily=0xd0, .Family=0x4, .ExtModel=0x0, .Model=0xa} +#define _Cortex_A510 {.ExtFamily=0xd4, .Family=0x6, .ExtModel=0x0, .Model=0x0} +#define _Cortex_A520 {.ExtFamily=0xd8, .Family=0x0, .ExtModel=0x0, .Model=0x0} +#define _Cortex_A53 {.ExtFamily=0xd0, .Family=0x3, .ExtModel=0x0, .Model=0x3} +#define _Cortex_A55 {.ExtFamily=0xd0, .Family=0x5, .ExtModel=0x4, .Model=0x5} +#define _Cortex_A57 {.ExtFamily=0xd0, .Family=0x7, .ExtModel=0x0, .Model=0x1} +#define _Cortex_A65 {.ExtFamily=0xd0, .Family=0x6, .ExtModel=0x4, .Model=0x6} +#define _Cortex_A65AE {.ExtFamily=0xd4, .Family=0x3, .ExtModel=0x4, .Model=0x7} +#define _Cortex_A710 {.ExtFamily=0xd4, .Family=0x7, .ExtModel=0x0, .Model=0x0} +#define _Cortex_A715 {.ExtFamily=0xd4, .Family=0xd, .ExtModel=0x0, .Model=0x0} +#define _Cortex_A72 {.ExtFamily=0xd0, .Family=0x8, .ExtModel=0x0, .Model=0x2} +#define _Cortex_A720 {.ExtFamily=0xd8, .Family=0x1, .ExtModel=0x0, .Model=0x0} +#define _Cortex_A73 {.ExtFamily=0xd0, .Family=0x9, .ExtModel=0x0, .Model=0x4} +#define _Cortex_A75 {.ExtFamily=0xd0, .Family=0xa, .ExtModel=0x4, .Model=0xa} +#define _Cortex_A76 {.ExtFamily=0xd0, .Family=0xb, .ExtModel=0x0, .Model=0xb} +#define _Cortex_A76AE {.ExtFamily=0xd0, .Family=0xe, .ExtModel=0x1, .Model=0x1} +#define _Cortex_A77 {.ExtFamily=0xd0, .Family=0xd, .ExtModel=0x1, .Model=0x0} +#define _Cortex_A78 {.ExtFamily=0xd4, .Family=0x1, .ExtModel=0x2, .Model=0x1} +#define _Cortex_A78AE {.ExtFamily=0xd4, .Family=0x2, .ExtModel=0x2, .Model=0x2} +#define _Cortex_A78C {.ExtFamily=0xd4, .Family=0xb, .ExtModel=0x2, .Model=0x4} +#define _Cortex_R82 {.ExtFamily=0xd1, .Family=0x5, .ExtModel=0x0, .Model=0x0} +#define _Cortex_X1 {.ExtFamily=0xd4, .Family=0x4, .ExtModel=0x2, .Model=0x3} +#define _Cortex_X1C {.ExtFamily=0xd4, .Family=0xc, .ExtModel=0x2, .Model=0x5} +#define _Cortex_X2 {.ExtFamily=0xd4, .Family=0x8, .ExtModel=0x0, .Model=0x0} +#define _Cortex_X3 {.ExtFamily=0xd4, .Family=0xe, .ExtModel=0x0, .Model=0x0} +#define _Cortex_X4 {.ExtFamily=0xd8, .Family=0x2, .ExtModel=0x0, .Model=0x0} +#define _DynamIQ_DSU {.ExtFamily=0x00, .Family=0x0, .ExtModel=0x4, .Model=0x1} +#define _Neoverse_E1 {.ExtFamily=0xd4, .Family=0xa, .ExtModel=0x4, .Model=0x6} +#define _Neoverse_N1 {.ExtFamily=0xd0, .Family=0xc, .ExtModel=0x0, .Model=0xc} +#define _Neoverse_N2 {.ExtFamily=0xd4, .Family=0x9, .ExtModel=0x0, .Model=0x0} +#define _Neoverse_V1 {.ExtFamily=0xd4, .Family=0x0, .ExtModel=0x2, .Model=0x1} +#define _Neoverse_V2 {.ExtFamily=0xd4, .Family=0xf, .ExtModel=0x0, .Model=0x0} + +typedef kernel_ulong_t (*PCI_CALLBACK)(struct pci_dev *); + +static struct pci_device_id PCI_Void_ids[] = { + {0, } +}; + +static char *CodeName[CODENAMES] = { + [ ARM64] = "AArch64", + [ ARMv8_R] = "ARMv8-R", + [ ARMv8_A] = "ARMv8-A", + [ARMv8_2_A] = "ARMv8.2-A", + [ARMv8_3_A] = "ARMv8.3-A", + [ARMv8_4_A] = "ARMv8.4-A", + [ ARMv8_5] = "ARMv8.5", + [ ARMv8_6] = "ARMv8.6", + [ ARMv8_7] = "ARMv8.7", + [ ARMv9_A] = "ARMv9-A", + [ ARMv9_4] = "ARMv9.4", + [ ARMv9_5] = "ARMv9.5" +}; + +#define Arch_Misc_Processor {.Brand = ZLIST(NULL), .CN = ARM64} +#define Arch_Cortex_A34 {.Brand = ZLIST("Cortex-A34"), .CN = ARMv8_A} +#define Arch_Cortex_A35 {.Brand = ZLIST("Cortex-A35"), .CN = ARMv8_A} +#define Arch_Cortex_A510 {.Brand = ZLIST("Cortex-A510"), .CN = ARMv9_A} +#define Arch_Cortex_A520 {.Brand = ZLIST("Cortex-A520"), .CN = ARMv9_A} +#define Arch_Cortex_A53 {.Brand = ZLIST("Cortex-A53"), .CN = ARMv8_A} +#define Arch_Cortex_A55 {.Brand = ZLIST("Cortex-A55"), .CN = ARMv8_2_A} +#define Arch_Cortex_A57 {.Brand = ZLIST("Cortex-A57"), .CN = ARMv8_A} +#define Arch_Cortex_A65 {.Brand = ZLIST("Cortex-A65"), .CN = ARMv8_2_A} +#define Arch_Cortex_A65AE {.Brand = ZLIST("Cortex-A65AE"), .CN = ARMv8_2_A} +#define Arch_Cortex_A710 {.Brand = ZLIST("Cortex-A710"), .CN = ARMv9_A} +#define Arch_Cortex_A715 {.Brand = ZLIST("Cortex-A715"), .CN = ARMv9_A} +#define Arch_Cortex_A72 {.Brand = ZLIST("Cortex-A72"), .CN = ARMv8_A} +#define Arch_Cortex_A720 {.Brand = ZLIST("Cortex-A720"), .CN = ARMv9_A} +#define Arch_Cortex_A73 {.Brand = ZLIST("Cortex-A73"), .CN = ARMv8_A} +#define Arch_Cortex_A75 {.Brand = ZLIST("Cortex-A75"), .CN = ARMv8_2_A} +#define Arch_Cortex_A76 {.Brand = ZLIST("Cortex-A76"), .CN = ARMv8_2_A} +#define Arch_Cortex_A76AE {.Brand = ZLIST("Cortex-A76AE"), .CN = ARMv8_2_A} +#define Arch_Cortex_A77 {.Brand = ZLIST("Cortex-A77"), .CN = ARMv8_2_A} +#define Arch_Cortex_A78 {.Brand = ZLIST("Cortex-A78"), .CN = ARMv8_2_A} +#define Arch_Cortex_A78AE {.Brand = ZLIST("Cortex-A78AE"), .CN = ARMv8_2_A} +#define Arch_Cortex_A78C {.Brand = ZLIST("Cortex-A78C"), .CN = ARMv8_2_A} +#define Arch_Cortex_R82 {.Brand = ZLIST("Cortex-R82"), .CN = ARMv8_R} +#define Arch_Cortex_X1 {.Brand = ZLIST("Cortex-X1"), .CN = ARMv8_2_A} +#define Arch_Cortex_X1C {.Brand = ZLIST("Cortex-X1C"), .CN = ARMv8_2_A} +#define Arch_Cortex_X2 {.Brand = ZLIST("Cortex-X2"), .CN = ARMv9_A} +#define Arch_Cortex_X3 {.Brand = ZLIST("Cortex-X3"), .CN = ARMv9_A} +#define Arch_Cortex_X4 {.Brand = ZLIST("Cortex-X4"), .CN = ARMv9_A} +#define Arch_DynamIQ_DSU {.Brand = ZLIST("DynamIQ DSU"), .CN = ARMv8_2_A} +#define Arch_Neoverse_E1 {.Brand = ZLIST("Neoverse E1"), .CN = ARMv8_2_A} +#define Arch_Neoverse_N1 {.Brand = ZLIST("Neoverse N1"), .CN = ARMv8_2_A} +#define Arch_Neoverse_N2 {.Brand = ZLIST("Neoverse N2"), .CN = ARMv9_A} +#define Arch_Neoverse_V1 {.Brand = ZLIST("Neoverse V1"), .CN = ARMv8_4_A} +#define Arch_Neoverse_V2 {.Brand = ZLIST("Neoverse V2"), .CN = ARMv9_A} + +static PROCESSOR_SPECIFIC Misc_Specific_Processor[] = { + {0} +}; + +#ifdef CONFIG_CPU_FREQ +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 19) +#define CPUFREQ_POLICY_UNKNOWN (0) +#endif +static int CoreFreqK_Policy_Exit(struct cpufreq_policy*) ; +static int CoreFreqK_Policy_Init(struct cpufreq_policy*) ; +#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 19)) \ + && (LINUX_VERSION_CODE <= KERNEL_VERSION(5, 5, 0))) \ + || (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 5, 3)) \ + || (RHEL_MAJOR == 8) +static int CoreFreqK_Policy_Verify(struct cpufreq_policy_data*) ; +#else +static int CoreFreqK_Policy_Verify(struct cpufreq_policy*) ; +#endif +static int CoreFreqK_SetPolicy(struct cpufreq_policy*) ; +static int CoreFreqK_Bios_Limit(int, unsigned int*) ; +static ssize_t CoreFreqK_Show_SetSpeed(struct cpufreq_policy*, char*); +static int CoreFreqK_Store_SetSpeed(struct cpufreq_policy*, unsigned int) ; +#endif /* CONFIG_CPU_FREQ */ + +static unsigned int Policy_GetFreq(unsigned int cpu) ; + +#define VOID_Driver { \ + .IdleState = NULL , \ + .GetFreq = Policy_GetFreq, \ + .SetTarget = NULL \ +} + +static ARCH Arch[ARCHITECTURES] = { +[GenuineArch] = { /* 0*/ + .Signature = _Void_Signature, + .Query = Query_GenericMachine, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Misc_Processor + }, +[Cortex_A34] = { + .Signature = _Cortex_A34, + .Query = Query_GenericMachine, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Cortex_A34 + }, +[Cortex_A35] = { + .Signature = _Cortex_A35, + .Query = Query_GenericMachine, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Cortex_A35 + }, +[Cortex_A510] = { + .Signature = _Cortex_A510, + .Query = Query_GenericMachine, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Cortex_A510 + }, +[Cortex_A520] = { + .Signature = _Cortex_A520, + .Query = Query_GenericMachine, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Cortex_A520 + }, +[Cortex_A53] = { + .Signature = _Cortex_A53, + .Query = Query_GenericMachine, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Cortex_A53 + }, +[Cortex_A55] = { + .Signature = _Cortex_A55, + .Query = Query_DynamIQ, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Cortex_A55 + }, +[Cortex_A57] = { + .Signature = _Cortex_A57, + .Query = Query_GenericMachine, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Cortex_A57 + }, +[Cortex_A65] = { + .Signature = _Cortex_A65, + .Query = Query_GenericMachine, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Cortex_A65 + }, +[Cortex_A65AE] = { + .Signature = _Cortex_A65AE, + .Query = Query_GenericMachine, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Cortex_A65AE + }, +[Cortex_A710] = { + .Signature = _Cortex_A710, + .Query = Query_GenericMachine, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Cortex_A710 + }, +[Cortex_A715] = { + .Signature = _Cortex_A715, + .Query = Query_GenericMachine, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Cortex_A715 + }, +[Cortex_A72] = { + .Signature = _Cortex_A72, + .Query = Query_GenericMachine, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Cortex_A72 + }, +[Cortex_A720] = { + .Signature = _Cortex_A720, + .Query = Query_GenericMachine, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Cortex_A720 + }, +[Cortex_A73] = { + .Signature = _Cortex_A73, + .Query = Query_GenericMachine, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Cortex_A73 + }, +[Cortex_A75] = { + .Signature = _Cortex_A75, + .Query = Query_DynamIQ, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Cortex_A75 + }, +[Cortex_A76] = { + .Signature = _Cortex_A76, + .Query = Query_DynamIQ, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Cortex_A76 + }, +[Cortex_A76AE] = { + .Signature = _Cortex_A76AE, + .Query = Query_DynamIQ, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Cortex_A76AE + }, +[Cortex_A77] = { + .Signature = _Cortex_A77, + .Query = Query_DynamIQ, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Cortex_A77 + }, +[Cortex_A78] = { + .Signature = _Cortex_A78, + .Query = Query_DynamIQ, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Cortex_A78 + }, +[Cortex_A78AE] = { + .Signature = _Cortex_A78AE, + .Query = Query_DynamIQ, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Cortex_A78AE + }, +[Cortex_A78C] = { + .Signature = _Cortex_A78C, + .Query = Query_DynamIQ, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Cortex_A78C + }, +[Cortex_R82] = { + .Signature = _Cortex_R82, + .Query = Query_DynamIQ, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Cortex_R82 + }, +[Cortex_X1] = { + .Signature = _Cortex_X1, + .Query = Query_DynamIQ, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Cortex_X1 + }, +[Cortex_X1C] = { + .Signature = _Cortex_X1C, + .Query = Query_DynamIQ, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Cortex_X1C + }, +[Cortex_X2] = { + .Signature = _Cortex_X2, + .Query = Query_GenericMachine, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Cortex_X2 + }, +[Cortex_X3] = { + .Signature = _Cortex_X3, + .Query = Query_GenericMachine, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Cortex_X3 + }, +[Cortex_X4] = { + .Signature = _Cortex_X4, + .Query = Query_GenericMachine, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Cortex_X4 + }, +[DynamIQ_DSU] = { + .Signature = _DynamIQ_DSU, + .Query = Query_GenericMachine, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_DynamIQ_DSU + }, +[Neoverse_E1] = { + .Signature = _Neoverse_E1, + .Query = Query_GenericMachine, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Neoverse_E1 + }, +[Neoverse_N1] = { + .Signature = _Neoverse_N1, + .Query = Query_GenericMachine, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Neoverse_N1 + }, +[Neoverse_N2] = { + .Signature = _Neoverse_N2, + .Query = Query_GenericMachine, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Neoverse_N2 + }, +[Neoverse_V1] = { + .Signature = _Neoverse_V1, + .Query = Query_DynamIQ, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Neoverse_V1 + }, +[Neoverse_V2] = { + .Signature = _Neoverse_V2, + .Query = Query_GenericMachine, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, + .voltageFormula = VOLTAGE_FORMULA_NONE, + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Neoverse_V2 + } +}; diff --git a/aarch64/corefreqm.c b/aarch64/corefreqm.c new file mode 100644 index 00000000..a7445664 --- /dev/null +++ b/aarch64/corefreqm.c @@ -0,0 +1,365 @@ +/* + * CoreFreq + * Copyright (C) 2015-2024 CYRIL COURTIAT + * Licenses: GPL2 + */ + +#include +#include +#include +#include +#include + +#include "bitasm.h" +#include "coretypes.h" +#include "corefreq.h" +#include "corefreqm.h" + +#define DeltaTSC(pSlice) \ +({ \ + unsigned long long overhead = pSlice->Counter[1].TSC \ + - pSlice->Counter[0].TSC; \ + pSlice->Delta.TSC = pSlice->Counter[2].TSC \ + - pSlice->Counter[1].TSC; \ + if (overhead <= pSlice->Delta.TSC) \ + pSlice->Delta.TSC -= overhead; \ +}) + +#define DeltaINST(pSlice) \ +({ \ + unsigned long long overhead = pSlice->Counter[1].INST \ + - pSlice->Counter[0].INST; \ + pSlice->Delta.INST = pSlice->Counter[2].INST \ + - pSlice->Counter[1].INST; \ + if (overhead <= pSlice->Delta.INST) \ + pSlice->Delta.INST -= overhead; \ +}) + +void CallWith_RDTSC_RDPMC( RO(SHM_STRUCT) *RO(Shm), + RW(SHM_STRUCT) *RW(Shm), + unsigned int cpu, + SLICE_FUNC SliceFunc, + unsigned long arg ) +{ + struct SLICE_STRUCT *pSlice = &RO(Shm)->Cpu[cpu].Slice; + + RDTSC_PMCx1(pSlice->Counter[0].TSC,0x40000000,pSlice->Counter[0].INST); + + RDTSC_PMCx1(pSlice->Counter[1].TSC,0x40000000,pSlice->Counter[1].INST); + + SliceFunc(RO(Shm), RW(Shm), cpu, arg); + + RDTSC_PMCx1(pSlice->Counter[2].TSC,0x40000000,pSlice->Counter[2].INST); + + if (BITVAL(RW(Shm)->Proc.Sync, BURN)) { + DeltaTSC(pSlice); + DeltaINST(pSlice); + } +} + +void CallWith_RDTSC_No_RDPMC( RO(SHM_STRUCT) *RO(Shm), + RW(SHM_STRUCT) *RW(Shm), + unsigned int cpu, + SLICE_FUNC SliceFunc, + unsigned long arg ) +{ + struct SLICE_STRUCT *pSlice = &RO(Shm)->Cpu[cpu].Slice; + + RDTSC64(pSlice->Counter[0].TSC); + + RDTSC64(pSlice->Counter[1].TSC); + + SliceFunc(RO(Shm), RW(Shm), cpu, arg); + + RDTSC64(pSlice->Counter[2].TSC); + + if (BITVAL(RW(Shm)->Proc.Sync, BURN)) { + DeltaTSC(pSlice); + pSlice->Delta.INST = 0; + } +} + +void Slice_NOP( RO(SHM_STRUCT) *RO(Shm), RW(SHM_STRUCT) *RW(Shm), + unsigned int cpu, unsigned long arg ) +{ + UNUSED(RO(Shm)); + UNUSED(RW(Shm)); + UNUSED(cpu); + UNUSED(arg); + + __asm__ volatile + ( + "nop" + : + : + : + ); +} + +void Slice_Atomic(RO(SHM_STRUCT) *RO(Shm), RW(SHM_STRUCT) *RW(Shm), + unsigned int cpu, unsigned long arg) +{ + UNUSED(RW(Shm)); +/*TODO __asm__ volatile + ( + "movq %[_atom], %%r14" "\n\t" + "movq %[_xchg], %%r15" "\n\t" + "movq %[_loop], %%rcx" "\n\t" + "movq %[i_err], %%r11" "\n\t" + "1:" "\n\t" + "movq %%r14, %%r12" "\n\t" + "movq %%r15, %%r13" "\n\t" + "xchg %%r12, %%r13" "\n\t" + "cmpq %%r13, %%r14" "\n\t" + "jz 2f" "\n\t" + "incq %%r11" "\n\t" + "2:" "\n\t" + "loop 1b" "\n\t" + "movq %%r11, %[o_err]" + : [o_err] "=m" (RO(Shm)->Cpu[cpu].Slice.Error) + : [_loop] "m" (arg), + [_atom] "i" (SLICE_ATOM), + [_xchg] "i" (SLICE_XCHG), + [i_err] "m" (RO(Shm)->Cpu[cpu].Slice.Error) + : "%rcx", "%r11", "%r12", "%r13", "%r14", "%r15", + "cc", "memory" + );*/ +} + +#define CRC32vASM(data, len) \ +({ \ + unsigned int rem = 0; \ +/*TODO __asm__ ( \ + " movl %[_len], %%r8d" "\n\t" \ + " movq %[_data], %%r10" "\n\t" \ + " addq %%r10, %%r8" "\n\t" \ + " movl $0, %%r12d" "\n\t" \ + " movl $0x436f7265, %%r9d" "\n\t" \ + "1:" "\n\t" \ + " cmpq %%r8, %%r10" "\n\t" \ + " je 3f" "\n\t" \ + " addq $1, %%r10" "\n\t" \ + " movzbl -1(%%r10), %%edx" "\n\t" \ + " xorl %%edx, %%r12d" "\n\t" \ + " movl $8, %%edx" "\n\t" \ + "2:" "\n\t" \ + " movl %%r12d, %%r11d" "\n\t" \ + " shrl %%r11d" "\n\t" \ + " andl $1, %%r12d" "\n\t" \ + " cmovne %%r9d, %%r12d" "\n\t" \ + " xorl %%r11d, %%r12d" "\n\t" \ + " subl $1, %%edx" "\n\t" \ + " jne 2b" "\n\t" \ + " jmp 1b" "\n\t" \ + "3:" "\n\t" \ + " movl %%r12d, %[_rem]" \ + : [_rem] "+m" (rem) \ + : [_data] "m" (data), \ + [_len] "im" (len) \ + : "%rdx", "%r8", "%r9", "%r10", "%r11", "%r12" , \ + "cc", "memory" \ + ); */ \ + UNUSED(data); \ + UNUSED(len); \ + rem; \ +}) + +void Slice_CRC32(RO(SHM_STRUCT) *RO(Shm), RW(SHM_STRUCT) *RW(Shm), + unsigned int cpu, unsigned long arg) +{ + unsigned char *data = (unsigned char *) CRC32_SRC; + unsigned int len = 16; + UNUSED(RW(Shm)); + UNUSED(arg); + + if (CRC32vASM(data, len) != CRC32_EXP) + RO(Shm)->Cpu[cpu].Slice.Error++ ; +} + +/* + Source: 1996 Software graduate thesis + Conic: a.X² + b.Y² + c.Z² = k + Variations: + 1 - l'ellipsoïde + 2 - l'hyperboloïde à une nappe + 3 - l'hyperboloïde à deux nappes + 4 - le cylindre elliptique + 5 - le cylindre hyperbolique + 6 - deux plans parallèles +*/ +void Slice_Conic(RO(SHM_STRUCT) *RO(Shm), RW(SHM_STRUCT) *RW(Shm), + unsigned int cpu, unsigned long v) +{ + const double interval = (4.0 * 1024.0) - (double) cpu; + const struct { + double a, b, c, k; + } p[CONIC_VARIATIONS] = { + {.a=+1.0 , .b=+1.0, .c=-1.0 , .k= +0.0}, + {.a=-3.0 , .b=+3.0, .c=-3.0 , .k=-17000.0}, + {.a=+0.01, .b=+0.7, .c=+0.2 , .k= +3000.0}, + {.a=+2.0 , .b=+0.0, .c=+1.0 , .k= +5000.0}, + {.a=-0.5 , .b=+0.0, .c=+0.75, .k= +500.0}, + {.a=+0.0 , .b=+0.0, .c=+1.0 , .k= +3000.0} + }; + double X, Y, Z, Q, k; + + const double step = (double) RO(Shm)->Proc.CPU.Count; + + UNUSED(RW(Shm)); + + for (Y = -interval; Y <= interval; Y += step) + for (X = -interval; X <= interval; X += step) { + Q=(p[v].k - p[v].a * pow(X,2.0) - p[v].b * pow(Y,2.0)) / p[v].c; + Z = sqrt(Q); + + k = p[v].a*pow(X,2.0) + p[v].b*pow(Y,2.0) + p[v].c*pow(Z,2.0); + + if (fabs(k - p[v].k) > CONIC_ERROR) + RO(Shm)->Cpu[cpu].Slice.Error++ ; + } +} + +void Slice_Turbo(RO(SHM_STRUCT) *RO(Shm), RW(SHM_STRUCT) *RW(Shm), + unsigned int cpu, unsigned long arg) +{ + UNUSED(arg); + + Slice_Atomic(RO(Shm), RW(Shm), cpu, TURBO_LOOP); +} + +void Slice_Monte_Carlo(RO(SHM_STRUCT) *RO(Shm), RW(SHM_STRUCT) *RW(Shm), + unsigned int cpu, unsigned long arg) +{ + if (RO(Shm)->Cpu[cpu].Slice.Monte_Carlo.trials < PI_TRIALS) + { + double X, Y, Z; + UNUSED(arg); + #ifdef __GLIBC__ + if (!random_r( &RO(Shm)->Cpu[cpu].Slice.Random.data, + &RO(Shm)->Cpu[cpu].Slice.Random.value[0] ) + && !random_r( &RO(Shm)->Cpu[cpu].Slice.Random.data, + &RO(Shm)->Cpu[cpu].Slice.Random.value[1] )) + #else + RO(Shm)->Cpu[cpu].Slice.Random.value[0] = (int) random(); + RO(Shm)->Cpu[cpu].Slice.Random.value[1] = (int) random(); + #endif /* __GLIBC__ */ + { + X = (double) RO(Shm)->Cpu[cpu].Slice.Random.value[0] / RAND_MAX; + Y = (double) RO(Shm)->Cpu[cpu].Slice.Random.value[1] / RAND_MAX; + + Z = pow(X, 2.0) + pow(Y, 2.0); + + if (Z <= 1.0) { + RO(Shm)->Cpu[cpu].Slice.Monte_Carlo.inside++; + } + } + RO(Shm)->Cpu[cpu].Slice.Monte_Carlo.trials++ ; + } else { + const double fi = (double) RO(Shm)->Cpu[cpu].Slice.Monte_Carlo.inside, + ft = RO(Shm)->Cpu[cpu].Slice.Monte_Carlo.trials ? + (double) RO(Shm)->Cpu[cpu].Slice.Monte_Carlo.trials : 1.0; + + const double PI = (fi / ft) * 4.0; + + RO(Shm)->Cpu[cpu].Slice.Error += (fabs(PI - PI_CONST) > PI_ERROR) ? + +1LLU : RO(Shm)->Cpu[cpu].Slice.Error > 0LLU ? -1LLU : 0LLU; + + RO(Shm)->Cpu[cpu].Slice.Monte_Carlo.inside = 0LLU; + RO(Shm)->Cpu[cpu].Slice.Monte_Carlo.trials = 0LLU; + } +} + +RING_SLICE order_list[] = { + { + .ctrl = { + .cmd = COREFREQ_ORDER_ATOMIC, .sub = 0x0U, + .dl = {.lo = 1 , .hi = COREFREQ_TOGGLE_ON}, + .dh = {.lo = 0x0, .hi = 0x0} + }, + .func = Slice_Atomic, .pattern = ALL_SMT + },{ + .ctrl = { + .cmd=COREFREQ_ORDER_CRC32, .sub = 0x0U, + .dl = {.lo = 1 , .hi = COREFREQ_TOGGLE_ON}, + .dh = {.lo = 0x0, .hi = 0x0} + }, + .func = Slice_CRC32, .pattern = ALL_SMT + },{ + .ctrl = { + .cmd = COREFREQ_ORDER_CONIC, .sub = CONIC_ELLIPSOID, + .dl = {.lo = 1 , .hi = 0x0}, + .dh = {.lo = 0x0, .hi = 0x0} + }, + .func = Slice_Conic, .pattern = ALL_SMT + },{ + .ctrl = { + .cmd = COREFREQ_ORDER_CONIC, .sub = CONIC_HYPERBOLOID_ONE_SHEET, + .dl = {.lo = 1 , .hi = 0x0}, + .dh = {.lo = 0x0, .hi = 0x0} + }, + .func = Slice_Conic, .pattern = ALL_SMT + },{ + .ctrl = { + .cmd = COREFREQ_ORDER_CONIC, .sub = CONIC_HYPERBOLOID_TWO_SHEETS, + .dl = {.lo = 1 , .hi = 0x0}, + .dh = {.lo = 0x0, .hi = 0x0} + }, + .func = Slice_Conic, .pattern = ALL_SMT + },{ + .ctrl = { + .cmd = COREFREQ_ORDER_CONIC, .sub = CONIC_ELLIPTICAL_CYLINDER, + .dl = {.lo = 1 , .hi = 0x0}, + .dh = {.lo = 0x0, .hi = 0x0} + }, + .func = Slice_Conic, .pattern = ALL_SMT + },{ + .ctrl = { + .cmd = COREFREQ_ORDER_CONIC, .sub = CONIC_HYPERBOLIC_CYLINDER, + .dl = {.lo = 1 , .hi = 0x0}, + .dh = {.lo = 0x0, .hi = 0x0} + }, + .func = Slice_Conic, .pattern = ALL_SMT + },{ + .ctrl = { + .cmd = COREFREQ_ORDER_CONIC, .sub = CONIC_TWO_PARALLEL_PLANES, + .dl = {.lo = 1 , .hi = 0x0}, + .dh = {.lo = 0x0, .hi = 0x0} + }, + .func = Slice_Conic, .pattern = ALL_SMT + },{ + .ctrl = { + .cmd = COREFREQ_ORDER_TURBO, .sub = RAND_SMT, + .dl = {.lo = 1 , .hi = 0x0}, + .dh = {.lo = 0x0, .hi = 0x0} + }, + .func = Slice_Turbo, .pattern = RAND_SMT + },{ + .ctrl = { + .cmd = COREFREQ_ORDER_TURBO, .sub = RR_SMT, + .dl = {.lo = 1 , .hi = 0x0}, + .dh = {.lo = 0x0, .hi = 0x0} + }, + .func = Slice_Turbo, .pattern = RR_SMT + },{ + .ctrl = { + .cmd = COREFREQ_ORDER_TURBO, .sub = USR_CPU, + .dl = {.lo = 1 , .hi = 0x0}, + .dh = {.lo = 0x0, .hi = 0x0} + }, + .func = Slice_Turbo, .pattern = USR_CPU + },{ + .ctrl = { + .cmd = COREFREQ_ORDER_MONTE_CARLO, .sub = 0x0U, + .dl = {.lo = 0x0, .hi = 0x0}, + .dh = {.lo = 0x0, .hi = 0x0} + }, + .func = Slice_Monte_Carlo, .pattern = ALL_SMT + },{ + .ctrl = { + .cmd = 0x0U, .sub = 0x0U, + .dl = {.lo = 0x0, .hi = 0x0}, + .dh = {.lo = 0x0, .hi = 0x0} + }, + .func = NULL + } +}; diff --git a/aarch64/corefreqm.h b/aarch64/corefreqm.h new file mode 100644 index 00000000..1c74bf8d --- /dev/null +++ b/aarch64/corefreqm.h @@ -0,0 +1,79 @@ +/* + * CoreFreq + * Copyright (C) 2015-2024 CYRIL COURTIAT + * Licenses: GPL2 + */ + +typedef void (*SLICE_FUNC) ( RO(SHM_STRUCT)*, RW(SHM_STRUCT)*, + unsigned int, unsigned long ); + +void Slice_NOP( RO(SHM_STRUCT)*, RW(SHM_STRUCT)*, + unsigned int, unsigned long ); + +void Slice_Atomic(RO(SHM_STRUCT)*, RW(SHM_STRUCT)*, + unsigned int, unsigned long); + +void Slice_CRC32(RO(SHM_STRUCT)*, RW(SHM_STRUCT)*, + unsigned int, unsigned long); + +void Slice_Conic(RO(SHM_STRUCT)*, RW(SHM_STRUCT)*, + unsigned int, unsigned long); + +void Slice_Turbo(RO(SHM_STRUCT)*, RW(SHM_STRUCT)*, + unsigned int, unsigned long); + +void Slice_Monte_Carlo(RO(SHM_STRUCT)*, RW(SHM_STRUCT)*, + unsigned int, unsigned long); + +typedef struct { + RING_CTRL ctrl; + SLICE_FUNC func; + enum PATTERN pattern; +} RING_SLICE; + +extern RING_SLICE order_list[]; + +typedef void (*CALL_FUNC)( RO(SHM_STRUCT)*, + RW(SHM_STRUCT)*, + unsigned int, + SLICE_FUNC, + unsigned long ); + +void CallWith_RDTSC_RDPMC( RO(SHM_STRUCT)*, + RW(SHM_STRUCT)*, + unsigned int, + SLICE_FUNC, + unsigned long ); + +void CallWith_RDTSC_No_RDPMC( RO(SHM_STRUCT)*, + RW(SHM_STRUCT)*, + unsigned int, + SLICE_FUNC, + unsigned long ); + +#define RESET_Slice(Slice) \ +({ \ + Slice.Counter[0].TSC = 0; \ + Slice.Counter[1].TSC = 0; \ + Slice.Counter[2].TSC = 0; \ + Slice.Counter[0].INST= 0; \ + Slice.Counter[1].INST= 0; \ + Slice.Counter[2].INST= 0; \ + Slice.Delta.TSC = 0; \ + Slice.Delta.INST= 0; \ + Slice.Error = 0; \ +}) + +#define SLICE_XCHG 0x436f757274696174LLU +#define SLICE_ATOM 0x436f726546726571LLU + +#define TURBO_LOOP 0x17fffffffUL + +#define CRC32_SRC "CYRIL_INGENIERIE" +#define CRC32_EXP 0x44f9d7bc + +#define CONIC_ERROR 1e-07 + +#define PI_TRIALS 100000000LLU +#define PI_ERROR 1.0e-04 +#define PI_CONST 3.141592653589793 diff --git a/aarch64/coretypes.h b/aarch64/coretypes.h new file mode 100644 index 00000000..e77e1327 --- /dev/null +++ b/aarch64/coretypes.h @@ -0,0 +1,1760 @@ +/* + * CoreFreq + * Copyright (C) 2015-2024 CYRIL COURTIAT + * Licenses: GPL2 + */ + +#define COREFREQ_MAJOR 1 +#define COREFREQ_MINOR 97 +#define COREFREQ_REV 1 + +#if !defined(CORE_COUNT) + #define CORE_COUNT 256 +#elif !(CORE_COUNT == 64 || CORE_COUNT == 128 || CORE_COUNT == 256 \ + || CORE_COUNT == 512 || CORE_COUNT == 1024) + #error "CORE_COUNT must be 64, 128, 256, 512 or 1024" +#endif + +enum CRC_MANUFACTURER +{ + CRC_RESERVED = 0x0, + CRC_ARM = 0x1, + CRC_BROADCOM = 0x2, + CRC_CAVIUM = 0x3, + CRC_DEC = 0x4, + CRC_FUJITSU = 0x5, + CRC_INFINEON = 0x6, + CRC_MOTOROLA = 0x7, + CRC_NVIDIA = 0x8, + CRC_APM = 0x9, + CRC_QUALCOMM = 0xa, + CRC_MARVELL = 0xb, + CRC_INTEL = 0x75a2ba39, + CRC_AMPERE = 0xc, + /* Virtualization */ + CRC_KVM = 0x0e8c8561, + CRC_VBOX = 0x5091f045, + CRC_KBOX = 0x02b76f04, + CRC_VMWARE = 0x2a974552, + CRC_HYPERV = 0x543a585e +}; + +enum CODENAME +{ + ARM64, + ARMv8_R, + ARMv8_A, + ARMv8_2_A, + ARMv8_3_A, + ARMv8_4_A, + ARMv8_5, + ARMv8_6, + ARMv8_7, + ARMv9_A, + ARMv9_4, + ARMv9_5, + CODENAMES +}; + +enum { GenuineArch = 0, + Cortex_A34, + Cortex_A35, + Cortex_A510, + Cortex_A520, + Cortex_A53, + Cortex_A55, + Cortex_A57, + Cortex_A65, + Cortex_A65AE, + Cortex_A710, + Cortex_A715, + Cortex_A72, + Cortex_A720, + Cortex_A73, + Cortex_A75, + Cortex_A76, + Cortex_A76AE, + Cortex_A77, + Cortex_A78, + Cortex_A78AE, + Cortex_A78C, + Cortex_R82, + Cortex_X1, + Cortex_X1C, + Cortex_X2, + Cortex_X3, + Cortex_X4, + DynamIQ_DSU, + Neoverse_E1, + Neoverse_N1, + Neoverse_N2, + Neoverse_V1, + Neoverse_V2, + ARCHITECTURES +}; + +enum HYBRID_ARCH { + Hybrid_Primary , /* Big */ + Hybrid_Secondary /* Little */ +}; + +enum MECH_CSV2 { + CSV_NONE, + CSV2_1p0, + CSV2_1p1, + CSV2_1p2, + CSV2_2p0, + CSV2_3p0 +}; + +enum HYPERVISOR { + HYPERV_NONE, + BARE_METAL, + HYPERV_XEN, + HYPERV_KVM, + HYPERV_VBOX, + HYPERV_KBOX, + HYPERV_VMWARE, + HYPERV_HYPERV +}; + +#define HYPERVISORS ( 1 + HYPERV_HYPERV ) + +enum SYS_REG { + FLAG_SP = 0, /* [1:0] = [ZA:SM] */ + FLAG_EL = 2, /* [3:2] */ + FLAG_F = 6, + FLAG_I = 7, + FLAG_A = 8, + FLAG_D = 9, + FLAG_SSBS = 12, + FLAG_NMI = 13, + FLAG_PAN = 22, + FLAG_UAO = 23, + FLAG_DIT = 24, + FLAG_TCO = 25, + FLAG_V = 28, + FLAG_C = 29, + FLAG_Z = 30, + FLAG_N = 31, + FLAG_PM = 32, + + SCTLR_TIDCP = 63, + SCTLR_SPINT = 62, + SCTLR_NMI = 61, + SCTLR_EnTP2 = 60, + SCTLR_TCSO1 = 59, + SCTLR_TCSO0 = 58, + SCTLR_EPAN = 57, + SCTLR_EnALS = 56, + SCTLR_EnAS0 = 55, + SCTLR_EnASR = 54, + SCTLR_TME1 = 53, + SCTLR_TME0 = 52, + SCTLR_TMT1 = 51, + SCTLR_TMT0 = 50, + SCTLR_TWEDEL = 46, /* [49:46] */ + SCTLR_TWEDEn = 45, + SCTLR_DSSBS = 44, + SCTLR_ATA1 = 43, + SCTLR_ATA0 = 42, + SCTLR_TCF1 = 40, /* [41:40] */ + SCTLR_TCF0 = 38, /* [39:38] */ + SCTLR_ITFSB = 37, + SCTLR_BT1 = 36, + SCTLR_BT0 = 35, + SCTLR_EnFPM = 34, + SCTLR_MSCEn = 33, + SCTLR_CMOW = 32, + SCTLR_EnIA = 31, + SCTLR_EnIB = 30, + SCTLR_LSMAOE = 29, + SCTLR_nTLSMD = 28, + SCTLR_EnDA = 27, + SCTLR_UCI = 26, + SCTLR_EE = 25, + SCTLR_E0E = 24, + SCTLR_SPAN = 23, + SCTLR_EIS = 22, + SCTLR_IESB = 21, + SCTLR_TSCXT = 20, + SCTLR_WXN = 19, + SCTLR_nTWE = 18, + SCTLR_nTWI = 16, + SCTLR_UCT = 15, + SCTLR_DZE = 14, + SCTLR_EnDB = 13, + SCTLR_I = 12, + SCTLR_EOS = 11, + SCTLR_EnRCTX = 10, + SCTLR_UMA = 9, + SCTLR_SED = 8, + SCTLR_ITD = 7, + SCTLR_nAA = 6, + SCTLR_CP15B = 5, + SCTLR_SA0 = 4, + SCTLR_SA1 = 3, + SCTLR_C = 2, + SCTLR_A = 1, + SCTLR_M = 0, + + SCTLR2_CPTM0 = 12, + SCTLR2_CPTM1 = 11, + SCTLR2_CPTA0 = 10, + SCTLR2_CPTA1 = 9, + SCTLR2_EnPACM0 = 8, + SCTLR2_EnPACM1 = 7, + SCTLR2_IDCP128 = 6, + SCTLR2_EASE = 5, + SCTLR2_EnANERR = 4, + SCTLR2_EnADERR = 3, + SCTLR2_NMEA = 2, + + EL0_64 = 0, + EL0_32 = 1, + EL1_64 = 2, + EL1_32 = 3, + EL2_64 = 4, + EL2_32 = 5, + EL2_SEC = 6, + EL3_64 = 7, + EL3_32 = 8, + + FPSR_N = 31, + FPSR_Z = 30, + FPSR_C = 29, + FPSR_V = 28, + FPSR_QC = 27, + FPSR_IDC = 7, + FPSR_IXC = 4, + FPSR_UFC = 3, + FPSR_OFC = 2, + FPSR_DZC = 1, + FPSR_IOC = 0, + + UNDEF_CR = 64 +}; + +enum CSTATES_ENCODING { + _C0 = 0x0, + _C1 = 0x1, + _C2 = 0x2, + _C3 = 0x3, + _C4 = 0x4, + _C6 = 0x6, + _C6R = 0xb, + _C7 = 0x7, + _C7S = 0xc, + _C8 = 0x8, + _C9 = 0x9, + _C10 = 0xa, + _UNSPEC = 0xf +}; + +#define CSTATES_ENCODING_COUNT 12 + +enum THM_POINTS { + THM_THRESHOLD_1, + THM_THRESHOLD_2, + THM_TRIP_LIMIT, + THM_HTC_LIMIT, + THM_HTC_HYST, + THM_POINTS_DIM +}; + +typedef struct +{ + Bit64 Mask, /* 1=Thermal Point is specified */ + Kind, /* 0=Threshold ; 1=Limit */ + State __attribute__ ((aligned (8))); /*1=Enabled*/ + unsigned short Value[THM_POINTS_DIM]; +} THERMAL_POINT; + +enum EVENT_LOG { + /* MSR_IA32_{PACKAGE}_THERM_STATUS: x8 */ + LSHIFT_THERMAL_LOG, + LSHIFT_PROCHOT_LOG, + LSHIFT_CRITIC_LOG, + LSHIFT_THOLD1_LOG, + LSHIFT_THOLD2_LOG, + LSHIFT_POWER_LIMIT, + LSHIFT_CURRENT_LIMIT, + LSHIFT_CROSS_DOMAIN, + /* MSR_SKL_CORE_PERF_LIMIT_REASONS: x11 */ + LSHIFT_CORE_HOT_LOG, + LSHIFT_CORE_THM_LOG, + LSHIFT_CORE_RES_LOG, + LSHIFT_CORE_AVG_LOG, + LSHIFT_CORE_VRT_LOG, + LSHIFT_CORE_TDC_LOG, + LSHIFT_CORE_PL1_LOG, + LSHIFT_CORE_PL2_LOG, + LSHIFT_CORE_EDP_LOG, + LSHIFT_CORE_BST_LOG, + LSHIFT_CORE_ATT_LOG, + LSHIFT_CORE_TVB_LOG, + /* MSR_GRAPHICS_PERF_LIMIT_REASONS: x9 */ + LSHIFT_GFX_HOT_LOG, + LSHIFT_GFX_THM_LOG, + LSHIFT_GFX_AVG_LOG, + LSHIFT_GFX_VRT_LOG, + LSHIFT_GFX_TDC_LOG, + LSHIFT_GFX_PL1_LOG, + LSHIFT_GFX_PL2_LOG, + LSHIFT_GFX_EDP_LOG, + LSHIFT_GFX_EFF_LOG, + /* MSR_RING_PERF_LIMIT_REASONS: x8 */ + LSHIFT_RING_HOT_LOG, + LSHIFT_RING_THM_LOG, + LSHIFT_RING_AVG_LOG, + LSHIFT_RING_VRT_LOG, + LSHIFT_RING_TDC_LOG, + LSHIFT_RING_PL1_LOG, + LSHIFT_RING_PL2_LOG, + LSHIFT_RING_EDP_LOG +}; + +enum EVENT_STS { + /* MSR_IA32_{PACKAGE}_THERM_STATUS: x4 */ + LSHIFT_THERMAL_STS, + LSHIFT_PROCHOT_STS, + LSHIFT_CRITIC_TMP, + LSHIFT_THOLD1_STS, + LSHIFT_THOLD2_STS, + /* MSR_SKL_CORE_PERF_LIMIT_REASONS: x11 */ + LSHIFT_CORE_THM_STS, + LSHIFT_CORE_HOT_STS, + LSHIFT_CORE_RES_STS, + LSHIFT_CORE_AVG_STS, + LSHIFT_CORE_VRT_STS, + LSHIFT_CORE_TDC_STS, + LSHIFT_CORE_PL1_STS, + LSHIFT_CORE_PL2_STS, + LSHIFT_CORE_EDP_STS, + LSHIFT_CORE_BST_STS, + LSHIFT_CORE_ATT_STS, + LSHIFT_CORE_TVB_STS, + /* MSR_GRAPHICS_PERF_LIMIT_REASONS: x9 */ + LSHIFT_GFX_THM_STS, + LSHIFT_GFX_HOT_STS, + LSHIFT_GFX_AVG_STS, + LSHIFT_GFX_VRT_STS, + LSHIFT_GFX_TDC_STS, + LSHIFT_GFX_PL1_STS, + LSHIFT_GFX_PL2_STS, + LSHIFT_GFX_EDP_STS, + LSHIFT_GFX_EFF_STS, + /* MSR_RING_PERF_LIMIT_REASONS: x8 */ + LSHIFT_RING_THM_STS, + LSHIFT_RING_HOT_STS, + LSHIFT_RING_AVG_STS, + LSHIFT_RING_VRT_STS, + LSHIFT_RING_TDC_STS, + LSHIFT_RING_PL1_STS, + LSHIFT_RING_PL2_STS, + LSHIFT_RING_EDP_STS +}; + +enum { + eLOG, + eSTS, + eDIM +}; + +enum THERM_PWR_EVENTS { + EVENT_THERM_NONE = 0x0LLU, + /* MSR_IA32_{PACKAGE}_THERM_STATUS: */ + EVENT_THERMAL_STS = 0x1LLU << LSHIFT_THERMAL_STS, + EVENT_THERMAL_LOG = 0x1LLU << LSHIFT_THERMAL_LOG, + EVENT_PROCHOT_STS = 0x1LLU << LSHIFT_PROCHOT_STS, + EVENT_PROCHOT_LOG = 0x1LLU << LSHIFT_PROCHOT_LOG, + EVENT_CRITIC_TMP = 0x1LLU << LSHIFT_CRITIC_TMP, + EVENT_CRITIC_LOG = 0x1LLU << LSHIFT_CRITIC_LOG, + EVENT_THOLD1_STS = 0x1LLU << LSHIFT_THOLD1_STS, + EVENT_THOLD2_STS = 0x1LLU << LSHIFT_THOLD2_STS, + EVENT_THOLD1_LOG = 0x1LLU << LSHIFT_THOLD1_LOG, + EVENT_THOLD2_LOG = 0x1LLU << LSHIFT_THOLD2_LOG, + EVENT_POWER_LIMIT = 0x1LLU << LSHIFT_POWER_LIMIT, + EVENT_CURRENT_LIMIT = 0x1LLU << LSHIFT_CURRENT_LIMIT, + EVENT_CROSS_DOMAIN = 0x1LLU << LSHIFT_CROSS_DOMAIN, + /* MSR_SKL_CORE_PERF_LIMIT_REASONS: */ + EVENT_CORE_THM_STS = 0x1LLU << LSHIFT_CORE_THM_STS, + EVENT_CORE_HOT_STS = 0x1LLU << LSHIFT_CORE_HOT_STS, + EVENT_CORE_HOT_LOG = 0x1LLU << LSHIFT_CORE_HOT_LOG, + EVENT_CORE_THM_LOG = 0x1LLU << LSHIFT_CORE_THM_LOG, + EVENT_CORE_RES_STS = 0x1LLU << LSHIFT_CORE_RES_STS, + EVENT_CORE_RES_LOG = 0x1LLU << LSHIFT_CORE_RES_LOG, + EVENT_CORE_AVG_STS = 0x1LLU << LSHIFT_CORE_AVG_STS, + EVENT_CORE_AVG_LOG = 0x1LLU << LSHIFT_CORE_AVG_LOG, + EVENT_CORE_VRT_STS = 0x1LLU << LSHIFT_CORE_VRT_STS, + EVENT_CORE_VRT_LOG = 0x1LLU << LSHIFT_CORE_VRT_LOG, + EVENT_CORE_TDC_STS = 0x1LLU << LSHIFT_CORE_TDC_STS, + EVENT_CORE_TDC_LOG = 0x1LLU << LSHIFT_CORE_TDC_LOG, + EVENT_CORE_PL1_STS = 0x1LLU << LSHIFT_CORE_PL1_STS, + EVENT_CORE_PL1_LOG = 0x1LLU << LSHIFT_CORE_PL1_LOG, + EVENT_CORE_PL2_STS = 0x1LLU << LSHIFT_CORE_PL2_STS, + EVENT_CORE_PL2_LOG = 0x1LLU << LSHIFT_CORE_PL2_LOG, + EVENT_CORE_EDP_STS = 0x1LLU << LSHIFT_CORE_EDP_STS, + EVENT_CORE_EDP_LOG = 0x1LLU << LSHIFT_CORE_EDP_LOG, + EVENT_CORE_BST_STS = 0x1LLU << LSHIFT_CORE_BST_STS, + EVENT_CORE_BST_LOG = 0x1LLU << LSHIFT_CORE_BST_LOG, + EVENT_CORE_ATT_STS = 0x1LLU << LSHIFT_CORE_ATT_STS, + EVENT_CORE_ATT_LOG = 0x1LLU << LSHIFT_CORE_ATT_LOG, + EVENT_CORE_TVB_STS = 0x1LLU << LSHIFT_CORE_TVB_STS, + EVENT_CORE_TVB_LOG = 0x1LLU << LSHIFT_CORE_TVB_LOG, + /* MSR_GRAPHICS_PERF_LIMIT_REASONS: */ + EVENT_GFX_THM_STS = 0x1LLU << LSHIFT_GFX_THM_STS, + EVENT_GFX_HOT_STS = 0x1LLU << LSHIFT_GFX_HOT_STS, + EVENT_GFX_HOT_LOG = 0x1LLU << LSHIFT_GFX_HOT_LOG, + EVENT_GFX_THM_LOG = 0x1LLU << LSHIFT_GFX_THM_LOG, + EVENT_GFX_AVG_STS = 0x1LLU << LSHIFT_GFX_AVG_STS, + EVENT_GFX_AVG_LOG = 0x1LLU << LSHIFT_GFX_AVG_LOG, + EVENT_GFX_VRT_STS = 0x1LLU << LSHIFT_GFX_VRT_STS, + EVENT_GFX_VRT_LOG = 0x1LLU << LSHIFT_GFX_VRT_LOG, + EVENT_GFX_TDC_STS = 0x1LLU << LSHIFT_GFX_TDC_STS, + EVENT_GFX_TDC_LOG = 0x1LLU << LSHIFT_GFX_TDC_LOG, + EVENT_GFX_PL1_STS = 0x1LLU << LSHIFT_GFX_PL1_STS, + EVENT_GFX_PL1_LOG = 0x1LLU << LSHIFT_GFX_PL1_LOG, + EVENT_GFX_PL2_STS = 0x1LLU << LSHIFT_GFX_PL2_STS, + EVENT_GFX_PL2_LOG = 0x1LLU << LSHIFT_GFX_PL2_LOG, + EVENT_GFX_EDP_STS = 0x1LLU << LSHIFT_GFX_EDP_STS, + EVENT_GFX_EDP_LOG = 0x1LLU << LSHIFT_GFX_EDP_LOG, + EVENT_GFX_EFF_STS = 0x1LLU << LSHIFT_GFX_EFF_STS, + EVENT_GFX_EFF_LOG = 0x1LLU << LSHIFT_GFX_EFF_LOG, + /* MSR_RING_PERF_LIMIT_REASONS: */ + EVENT_RING_THM_STS = 0x1LLU << LSHIFT_RING_THM_STS, + EVENT_RING_HOT_STS = 0x1LLU << LSHIFT_RING_HOT_STS, + EVENT_RING_HOT_LOG = 0x1LLU << LSHIFT_RING_HOT_LOG, + EVENT_RING_THM_LOG = 0x1LLU << LSHIFT_RING_THM_LOG, + EVENT_RING_AVG_STS = 0x1LLU << LSHIFT_RING_AVG_STS, + EVENT_RING_AVG_LOG = 0x1LLU << LSHIFT_RING_AVG_LOG, + EVENT_RING_VRT_STS = 0x1LLU << LSHIFT_RING_VRT_STS, + EVENT_RING_VRT_LOG = 0x1LLU << LSHIFT_RING_VRT_LOG, + EVENT_RING_TDC_STS = 0x1LLU << LSHIFT_RING_TDC_STS, + EVENT_RING_TDC_LOG = 0x1LLU << LSHIFT_RING_TDC_LOG, + EVENT_RING_PL1_STS = 0x1LLU << LSHIFT_RING_PL1_STS, + EVENT_RING_PL1_LOG = 0x1LLU << LSHIFT_RING_PL1_LOG, + EVENT_RING_PL2_STS = 0x1LLU << LSHIFT_RING_PL2_STS, + EVENT_RING_PL2_LOG = 0x1LLU << LSHIFT_RING_PL2_LOG, + EVENT_RING_EDP_STS = 0x1LLU << LSHIFT_RING_EDP_STS, + EVENT_RING_EDP_LOG = 0x1LLU << LSHIFT_RING_EDP_LOG, + /* ALL EVENTS */ + EVENT_ALL_OF_THEM = EVENT_RING_EDP_LOG << 1 +}; + +enum SENSOR_LIMITS { + SENSOR_LOWEST, + SENSOR_HIGHEST, + SENSOR_LIMITS_DIM +}; + +enum THERMAL_OFFSET { + THERMAL_TARGET, + THERMAL_OFFSET_P1, + THERMAL_OFFSET_P2, + THERMAL_OFFSET_DIM +}; + +typedef union +{ + unsigned long Target; + unsigned short Offset[THERMAL_OFFSET_DIM]; +} THERMAL_PARAM; + +enum FORMULA_SCOPE { + FORMULA_SCOPE_NONE = 0, + FORMULA_SCOPE_SMT = 1, + FORMULA_SCOPE_CORE = 2, + FORMULA_SCOPE_PKG = 3 +}; + +enum THERMAL_KIND { + THERMAL_KIND_NONE = 0b000000000000000000000000 +}; + +enum THERMAL_FORMULAS { +THERMAL_FORMULA_NONE = (THERMAL_KIND_NONE << 8) | FORMULA_SCOPE_NONE +}; + +enum VOLTAGE_KIND { + VOLTAGE_KIND_NONE = 0b000000000000000000000000 +}; + +enum VOLTAGE_FORMULAS { +VOLTAGE_FORMULA_NONE =(VOLTAGE_KIND_NONE << 8) | FORMULA_SCOPE_NONE +}; + +enum POWER_KIND { + POWER_KIND_NONE = 0b000000000000000000000000 +}; + +enum POWER_FORMULAS { +POWER_FORMULA_NONE =(POWER_KIND_NONE << 8) | FORMULA_SCOPE_NONE +}; + +#define SCOPE_OF_FORMULA(formula) (formula & 0b0011) + +#define KIND_OF_FORMULA(formula) ((formula >> 8) & 0b111111111111111111111111) + +/* Sensors formulas and definitions. + MIN = [SENSOR] > [TRIGGER] AND ([SENSOR] < [LOWEST] OR [LOWEST] <= [CAPPED]) + MAX = [SENSOR] > [HIGHEST] +*/ + +#define THRESHOLD_LOWEST_CAPPED_THERMAL 1 +#define THRESHOLD_LOWEST_CAPPED_VOLTAGE 0.15 +#define THRESHOLD_LOWEST_CAPPED_ENERGY 0.000001 +#define THRESHOLD_LOWEST_CAPPED_POWER 0.000001 +#define THRESHOLD_LOWEST_CAPPED_REL_FREQ 0.0 +#define THRESHOLD_LOWEST_CAPPED_ABS_FREQ 0.0 + +#define THRESHOLD_LOWEST_TRIGGER_THERMAL 0 +#define THRESHOLD_LOWEST_TRIGGER_VOLTAGE 0.0 +#define THRESHOLD_LOWEST_TRIGGER_ENERGY 0.0 +#define THRESHOLD_LOWEST_TRIGGER_POWER 0.0 +#define THRESHOLD_LOWEST_TRIGGER_REL_FREQ 0.0 +#define THRESHOLD_LOWEST_TRIGGER_ABS_FREQ 0.0 + +#define _RESET_SENSOR_LIMIT(THRESHOLD, Limit) \ +({ \ + Limit = THRESHOLD; \ +}) + +#define RESET_SENSOR_LOWEST(CLASS, Limit) \ + _RESET_SENSOR_LIMIT(THRESHOLD_LOWEST_CAPPED_##CLASS, \ + Limit[SENSOR_LOWEST]) + +#define RESET_SENSOR_HIGHEST(CLASS, Limit) \ + _RESET_SENSOR_LIMIT(THRESHOLD_LOWEST_TRIGGER_##CLASS, \ + Limit[SENSOR_HIGHEST]) + +#define RESET_SENSOR_LIMIT(CLASS, STAT, Limit) \ + RESET_SENSOR_##STAT(CLASS, Limit) + +#define TEST_SENSOR_LOWEST(CLASS, TRIGGER, CAPPED, Sensor, Limit) \ + (Sensor > TRIGGER##CLASS) \ + && ((Sensor < Limit) || (Limit <= CAPPED##CLASS)) + +#define TEST_SENSOR_HIGHEST(CLASS, TRIGGER, CAPPED, Sensor, Limit) \ + (Sensor > Limit) + +#define _TEST_SENSOR(CLASS, STAT, THRESHOLD, TRIGGER, CAPPED, Sensor, Limit) \ + TEST_SENSOR_##STAT(CLASS, THRESHOLD##TRIGGER, THRESHOLD##CAPPED, \ + Sensor, Limit) + +#define TEST_SENSOR(CLASS, STAT, Sensor, Limit) \ + _TEST_SENSOR(CLASS, STAT, THRESHOLD_##STAT, _TRIGGER_, _CAPPED_, \ + Sensor, Limit[SENSOR_##STAT]) + +#define TEST_AND_SET_SENSOR(CLASS, STAT, Sensor, Limit) \ +({ \ + if (TEST_SENSOR(CLASS, STAT, Sensor, Limit)) \ + { \ + Limit[SENSOR_##STAT] = Sensor; \ + } \ +}) + +#define COMPUTE_THERMAL(_ARCH_, Temp, Param, Sensor) \ + COMPUTE_THERMAL_##_ARCH_(Temp, Param, Sensor) + +#define COMPUTE_VOLTAGE(_ARCH_, Vcore, VID) \ + COMPUTE_VOLTAGE_##_ARCH_(Vcore, VID) + +#define COMPUTE_TAU(Y, Z, TU) ( \ + (1LLU << Y) * (1.0 + Z / 4.0) * TU \ +) + +#define COMPUTE_TW(Y, Z) ( \ + ((unsigned char) Z << 5) | (unsigned char) Y \ +) + +enum PWR_LIMIT { + PL1 = 0, + PL2 = 1, + PWR_LIMIT_SIZE +}; + +enum PWR_DOMAIN { + DOMAIN_PKG = 0, + DOMAIN_CORES = 1, + DOMAIN_UNCORE = 2, + DOMAIN_RAM = 3, + DOMAIN_PLATFORM = 4, + DOMAIN_SIZE +}; + +#define PWR_DOMAIN(NC) DOMAIN_##NC + +enum RATIO_BOOST { + RATIO_MIN, + RATIO_MAX, + RATIO_TGT, + RATIO_ACT, + RATIO_TDP, + RATIO_TDP1, + RATIO_TDP2, + RATIO_TBO = RATIO_TDP1, + RATIO_TBH = RATIO_TDP2, + RATIO_HWP_MIN, + RATIO_HWP_MAX, + RATIO_HWP_TGT, + RATIO_18C, + RATIO_17C, + RATIO_16C, + RATIO_15C, + RATIO_14C, + RATIO_13C, + RATIO_12C, + RATIO_11C, + RATIO_10C, + RATIO_9C, + RATIO_8C, + RATIO_7C, + RATIO_6C, + RATIO_5C, + RATIO_4C, + RATIO_3C, + RATIO_2C, + RATIO_1C, + RATIO_SIZE +}; + +#define BOOST(NC) RATIO_##NC + +enum UNCORE_BOOST { + UNCORE_RATIO_MIN, + UNCORE_RATIO_MAX, + UNCORE_RATIO_SIZE +}; + +#define UNCORE_BOOST(NC) UNCORE_RATIO_##NC + +#define CACHE_MAX_LEVEL (3 + 1) + +#define PRECISION 100 + +#define UNIT_KHz(_f) (_f * 10 * PRECISION) +#define UNIT_MHz(_f) (_f * UNIT_KHz(1000)) +#define UNIT_GHz(_f) (_f * UNIT_MHz(1000)) +#define CLOCK_KHz(_t, _f) ((_t)(_f) / (_t)UNIT_KHz(1)) +#define CLOCK_MHz(_t, _f) ((_t)(_f) / (_t)UNIT_MHz(1)) +#define CLOCK_GHz(_t, _f) ((_t)(_f) / (_t)UNIT_GHz(1)) + +#if !defined(MAX_FREQ_HZ) + #define MAX_FREQ_HZ 7125000000 +#elif (MAX_FREQ_HZ < 4850000000) + #error "MAX_FREQ_HZ must be at least 4850000000 Hz" +#endif + +#define MAXCLOCK_TO_RATIO(_typeout, BaseClock) \ + ( (_typeout) (MAX_FREQ_HZ / BaseClock) ) + +enum OFFLINE +{ + HW, + OS +}; + +typedef struct +{ + unsigned short Q, + R; +} COF_ST; + +typedef union { + unsigned int Perf; /* STATUS or BOOST P-State */ + COF_ST COF; +} COF_UNION; + +typedef struct +{ + unsigned long long Q, + R, + Hz; +} CLOCK; + +#define REL_BCLK(clock, ratio, delta_tsc, interval) \ +({ /* Compute Clock (Hertz) */ \ + clock.Hz= (1000LLU * PRECISION * delta_tsc) \ + / (interval * ratio); \ + /* Compute Quotient (MHz) */ \ + clock.Q = clock.Hz / (1000LLU * 1000LLU); \ + /* Compute Remainder (MHz) */ \ + clock.R = clock.Hz % (1000LLU * 1000LLU); \ +}) + +#define REL_FREQ_MHz(this_type, this_ratio, clock, interval) \ + ( (this_type)(clock.Hz) \ + * (this_type)(this_ratio) \ + * (this_type)(interval)) \ + / (this_type)UNIT_MHz(interval) + +#define ABS_FREQ_MHz(this_type, this_ratio, this_clock) \ +( \ + CLOCK_MHz(this_type, this_ratio * this_clock.Hz) \ +) + +typedef union { + signed long long sllong; + unsigned long long ullong; + struct { + struct { + union { + signed short Offset; + signed short Ratio; + }; + signed short cpu; + }; + unsigned int NC; + }; +} CLOCK_ARG; + +enum CLOCK_MOD_INDEX { + CLOCK_MOD_ACT = 7, + CLOCK_MOD_HWP_MIN = 6, + CLOCK_MOD_HWP_MAX = 5, + CLOCK_MOD_HWP_TGT = 4, + CLOCK_MOD_MIN = 3, + CLOCK_MOD_MAX = 2, + CLOCK_MOD_TGT = 1 +}; + +enum { /* Stick to the Kernel enumeration in include/asm/nmi.h */ + BIT_NMI_LOCAL = 0, + BIT_NMI_UNKNOWN, + BIT_NMI_SERR, + BIT_NMI_IO_CHECK +}; + +#define BIT_NMI_MASK 0x0fLLU + +typedef union +{ + signed long long Proc; + struct { + unsigned int Core; + struct { + signed short Hybrid, + Thread; + }; + }; +} SERVICE_PROC; + +#define RESET_SERVICE {.Core = -1U, .Thread = -1, .Hybrid = -1} + +struct SIGNATURE { + unsigned int + Stepping : 8-0, + Model : 12-8, + Family : 16-12, + ExtModel : 20-16, + ExtFamily : 28-20, + Reserved : 32-28; +}; + +#define BRAND_PART 12 +#define BRAND_LENGTH (4 * BRAND_PART) +#define BRAND_SIZE (BRAND_LENGTH + 4) + +typedef struct +{ + struct SIGNATURE Signature; + struct { + enum CRC_MANUFACTURER CRC; + char ID[12 + 4]; + } Vendor, Hypervisor; + char Brand[BRAND_SIZE]; +} PROCESSOR_ID; + +struct CLUSTER_ST { + union { + unsigned int ID; + struct { + unsigned int Node : 8-0, + CCX : 16-8, + CCD : 24-16, + CMP : 32-24; + }; + }; + enum HYBRID_ARCH Hybrid_ID; +}; + +typedef struct /* BSP features. */ +{ + PROCESSOR_ID Info; + + struct { + Bit64 + AES : 1-0, + SHA1 : 2-1, + SHA256 : 3-2, + SHA512 : 4-3, + CRC32 : 5-4, + LSE : 6-5, + SHA3 : 7-6, + RAND : 8-7, + FP : 9-8, + SIMD : 10-9, + GIC_vers : 11-10, + SVE : 12-11, + VHE : 13-12, + SME : 14-13, + TME : 15-14, + RDMA : 16-15, + DP : 17-16, + SM3 : 18-17, + SM4 : 19-18, + FHM : 20-19, + LSE128 : 21-20, + TLBIOS : 22-21, + FCMA : 23-22, + LRCPC : 24-23, + JSCVT : 25-24, + FRINTTS : 26-25, + SPECRES : 27-26, + SPECRES2 : 28-27, + BF16 : 29-28, + EBF16 : 30-29, + I8MM : 31-30, + SB : 32-31, + XS : 33-32, + LS64 : 34-33, + LS64_V : 35-34, + LS64_ACCDATA : 36-35, + DGH : 37-36, + DPB : 38-37, + DPB2 : 39-38, + FlagM : 40-39, + FlagM2 : 41-40, + PMULL : 42-41, + GIC_frac : 43-42, + ECV : 44-43, + FGT : 45-44, + FGT2 : 46-45, + ExS : 47-46, + BigEnd_EL0 : 48-47, + BigEnd_EE : 49-48, + PARange : 53-49, + VARange : 62-59, + TLBIRANGE : 63-62, + PACIMP : 64-63; + + Bit64 CSV2 : 4-0, + SSBS : 8-4, + PAN : 9-8, + UAO : 10-9, + DIT : 11-10, + BTI : 12-11, + NMI : 13-12, + EBEP : 14-13, + RAS : 15-14, + RAS_frac : 16-15, + MPAM_vers : 17-16, + MPAM_frac : 18-17, + AMU_vers : 19-18, + AMU_frac : 20-19, + RME : 21-20, + SEL2 : 22-21, + ECBHB : 23-22, + GCS : 24-23, + THE : 25-24, + SVE_F64MM : 26-25, + SVE_F32MM : 27-26, + SVE_I8MM : 28-27, + SVE_SM4 : 29-28, + SVE_SHA3 : 30-29, + SVE_BF16 : 31-30, + SVE_EBF16 : 32-31, + SVE_BitPerm : 33-32, + SVE_AES : 34-33, + SVE_PMULL128 : 35-34, + SVE2 : 36-35, + SME_FA64 : 37-36, + SME_LUTv2 : 38-37, + SME2 : 39-38, + SME2p1 : 40-39, + SME_I16I64 : 41-40, + SME_F64F64 : 42-41, + SME_I16I32 : 43-42, + SME_B16B16 : 44-43, + SME_F16F16 : 45-44, + SME_F8F16 : 46-45, + SME_F8F32 : 47-46, + SME_I8I32 : 48-47, + SME_F16F32 : 49-48, + SME_B16F32 : 50-49, + SME_BI32I32 : 51-50, + SME_F32F32 : 52-51, + SME_SF8FMA : 53-52, + SME_SF8DP4 : 54-53, + SME_SF8DP2 : 55-54, + PACQARMA5 : 56-55, + LRCPC2 : 57-56, + LRCPC3 : 58-57, + PACQARMA3 : 59-58, + PAuth : 60-59, + EPAC : 61-60, + PAuth2 : 62-61, + FPAC : 63-62, + FPACCOMBINE : 64-63; + + Bit64 PAuth_LR : 1-0, + WFxT : 2-1, + RPRES : 3-2, + MOPS : 4-3, + HBC : 5-4, + SYSREG128 : 6-5, + SYSINSTR128 : 7-6, + PRFMSLC : 8-7, + RPRFM : 9-8, + CSSC : 10-9, + LUT : 11-10, + ATS1A : 12-11, + CONSTPACFIELD : 13-12, + RNG_TRAP : 14-13, + MTE : 17-14, + DF2 : 18-17, + PFAR : 19-18, + _Unused1_ : 64-19; + + Bit64 InvariantTSC : 8-0, + HyperThreading : 9-8, + HTT_Enable : 10-9, + TgtRatio_Unlock : 11-10, + ClkRatio_Unlock : 13-11, /* X.Y w/ X=Max and Y=Min */ + Turbo_Unlock : 14-13, + TDP_Unlock : 15-14, + TDP_Levels : 17-15, + TDP_Cfg_Lock : 18-17, + TDP_Cfg_Level : 20-18, + Turbo_OPP : 21-20, + Uncore_Unlock : 22-21, + HWP_Enable : 23-22, + Other_Capable : 24-23, + SpecTurboRatio : 32-24, + HTT : 33-32, + TSC : 34-33, + MONITOR : 35-34, + Inv_TSC : 36-35, + RDTSCP : 37-36, + Hybrid : 38-37, + ACPI : 39-38, + Hyperv : 40-39, + ACPI_PCT_CAP : 41-40, + ACPI_PCT : 42-41, + ACPI_PSS_CAP : 43-42, + ACPI_PSS : 47-43, /* 15 Pstate sub-packages */ + ACPI_PPC_CAP : 48-47, + ACPI_PPC : 52-48, /* Range of states supported */ + ACPI_CPPC : 53-52, + OSPM_CPC : 54-53, + OSPM_EPP : 55-54, + ACPI_CST_CAP : 56-55, + ACPI_CST : 60-56, /* 15 CState sub-packages */ + _Unused2_ : 64-60; + }; + struct + { + unsigned int + SubCstate_MWAIT0: 4-0, + SubCstate_MWAIT1: 8-4, + SubCstate_MWAIT2: 12-8, + SubCstate_MWAIT3: 16-12, + SubCstate_MWAIT4: 20-16, + SubCstate_MWAIT5: 24-20, + SubCstate_MWAIT6: 28-24, + SubCstate_MWAIT7: 32-28; + } MWait; + + struct { + unsigned int + Version : 4-0, + MonCtrs : 9-4, + MonWidth : 17-9, + FixCtrs : 22-17, + FixWidth : 30-22, + CoreCycles : 31-30, + InstrRetired : 32-31; + } PerfMon; + + struct { + unsigned short CG0NC, + CG1NC; + } AMU; + + struct + { + unsigned int + DTS : 1-0, + _Unused1_ : 3-1, + PLN : 4-3, + PTM : 5-4, + HWP_Reg : 6-5, +/* HCF_Cap : 7-6, + HWP_Int : 1 + HWP_Act : 1 + HWP_EPP : 1 + HWP_Pkg : 1 + HWP_HPrf : 1 + HWP_PECI : 1 + HWP_Flex : 1 + HWP_Fast : 1 + HWFB_Cap : 1 + HWP_Idle : 1 */ + _Unused2_ : 32-6; + } Power; + + struct { + unsigned long long PPIN; + CLOCK Clock; + unsigned int Freq, + Ratio; + } Factory; +} FEATURES; + +/* Memory Controller' structures dimensions. */ +#define MC_MAX_CTRL 8 +#define MC_MAX_CHA 12 +#define MC_MAX_DIMM 4 + +#define MC_3D_VECTOR_TO_SCALAR(_mc, _cha, _slot) \ + ((_mc * MC_MAX_CTRL) + (_cha * MC_MAX_CHA) + _slot) + +#define MC_2D_VECTOR_TO_SCALAR(_mc, _cha) \ + ((_mc * MC_MAX_CTRL) + _cha) + +#define MC_VECTOR_DISPATCH(_1, _2, _3, MC_VECTOR_CURSOR, ...) \ + MC_VECTOR_CURSOR + +#define MC_VECTOR_TO_SCALAR( ... ) \ + MC_VECTOR_DISPATCH(__VA_ARGS__, MC_3D_VECTOR_TO_SCALAR, /*3*/ \ + MC_2D_VECTOR_TO_SCALAR, /*2*/ \ + NULL) /*1*/ \ + ( __VA_ARGS__ ) + +#define MC_MHZ 0b00 +#define MC_MTS 0b01 +#define MC_MBS 0b10 +#define MC_NIL 0b11 + +typedef struct +{ + unsigned int tCL; + union { + unsigned int tRCD; + unsigned int tRCD_RD; + }; + unsigned int tRCD_WR, + tRP, + tRAS, + tRC, + + tRCPB, + tRPPB; + union { + unsigned int tRRD; + unsigned int tRRDS; + }; + unsigned int tRRDL, + + tFAW, + tFAWSLR, + tFAWDLR, + + tWTRS, + tWTRL, + tWR; + + unsigned int tRCPage; + union { + unsigned int tRTPr; + unsigned int tRTP; + }; + unsigned int tWTPr, + tCWL; + union { + struct { + unsigned int tddRdTWr, + tddWrTRd, + tddWrTWr, + tddRdTRd, + tsrRdTRd, + tdrRdTRd, + tsrRdTWr, + tdrRdTWr, + tsrWrTRd, + tdrWrTRd, + tsrWrTWr, + tdrWrTWr; + }; /* DDR3 */ + struct { + unsigned int tRDRD_SG, + tRDRD_DG, + tRDRD_DR, + tRDRD_DD, + tRDWR_SG, + tRDWR_DG, + tRDWR_DR, + tRDWR_DD, + tWRRD_SG, + tWRRD_DG, + tWRRD_DR, + tWRRD_DD, + tWRWR_SG, + tWRWR_DG, + tWRWR_DR, + tWRWR_DD; + }; /* DDR4 & DDR5 */ + struct { + unsigned int tddRdTWr, + tddWrTRd, + tddWrTWr, + tddRdTRd, + tRdRdScl, + tWrWrScl, + tscWrTWr, + tsdWrTWr, + tscRdTRd, + tsdRdTRd, + tRdRdScDLR, + tWrWrScDLR, + tWrRdScDLR, + tRRDDLR, + tRdRdBan, + tWrWrBan; + } Zen; + }; + unsigned int tXS, + tXP, + tCKE, + tCPDED; + + unsigned int tREFI; + union { + unsigned int tRFC; + unsigned int tRFC1; + }; + union { + unsigned int tRFC4; + unsigned int tRFCsb; + }; + unsigned int tRFC2, + tMRD, + tMOD, + tMRD_PDA, + tMOD_PDA, + tSTAG, + tPHYWRD, + tPHYWRL, + tPHYRDL, + tRDDATA, + tWRMPR; + + unsigned int CMD_Rate; + union { + unsigned int B2B; + unsigned int GEAR; + }; + struct { + unsigned int GDM : 1-0, + BGS : 2-1, + BGS_ALT : 3-2, + PDM_EN : 4-3, + PDM_MODE: 5-4, + PDM_AGGR: 9-5, + Scramble: 10-9, + TSME : 11-10, + Unused : 32-11; + }; + unsigned int ECC; +} RAM_TIMING; + +typedef struct +{ + struct { + unsigned int Size, + Rows, + Cols; + unsigned short Banks, + Ranks; + }; +} RAM_GEOMETRY; + +enum RAM_STANDARD { + RAM_STD_UNSPEC, + RAM_STD_SDRAM, + RAM_STD_LPDDR, + RAM_STD_RDIMM +}; + +/* Source: /include/uapi/linux/utsname.h */ +#ifdef __NEW_UTS_LEN + #define MAX_UTS_LEN __NEW_UTS_LEN +#else + #define MAX_UTS_LEN 64 +#endif + +/* Sources: /include/linux/cpuidle.h & /include/linux/cpuidle.h */ +#ifndef _LINUX_CPUIDLE_H + #define CPUIDLE_STATE_MAX 10 + #define CPUIDLE_NAME_LEN 16 +#endif +#define SUB_CSTATE_COUNT (CPUIDLE_STATE_MAX - 1) +/* Borrow the Kernel Idle State Flags */ +#ifndef CPUIDLE_FLAG_NONE + #define CPUIDLE_FLAG_NONE (0x00) +#endif +#ifndef CPUIDLE_FLAG_POLLING + #define CPUIDLE_FLAG_POLLING (1UL << (0)) +#endif +#ifndef CPUIDLE_FLAG_COUPLED + #define CPUIDLE_FLAG_COUPLED (1UL << (1)) +#endif +#ifndef CPUIDLE_FLAG_TIMER_STOP + #define CPUIDLE_FLAG_TIMER_STOP (1UL << (2)) +#endif +#ifndef CPUIDLE_FLAG_UNUSABLE + #define CPUIDLE_FLAG_UNUSABLE (1UL << (3)) +#endif +#ifndef CPUIDLE_FLAG_OFF + #define CPUIDLE_FLAG_OFF (1UL << (4)) +#endif +#ifndef CPUIDLE_FLAG_TLB_FLUSHED + #define CPUIDLE_FLAG_TLB_FLUSHED (1UL << (5)) +#endif +#ifndef CPUIDLE_FLAG_RCU_IDLE + #define CPUIDLE_FLAG_RCU_IDLE (1UL << (6)) +#endif + +#ifndef _LINUX_CPUFREQ_H + #define CPUFREQ_NAME_LEN 16 +#endif + +#define REGISTRATION_DISABLE 0b00 +#define REGISTRATION_ENABLE 0b01 +#define REGISTRATION_FULLCTRL 0b10 + +enum IDLE_ROUTE { + ROUTE_DEFAULT = 0, + ROUTE_IO = 1, + ROUTE_HALT = 2, + ROUTE_MWAIT = 3, + ROUTE_SIZE +}; + +#define CLOCKSOURCE_PATH "/sys/devices/system/clocksource/clocksource0" + +typedef struct { /* 0: Disable; 1: Enable; 2: Full-control */ + enum IDLE_ROUTE Route; + unsigned short CPUidle : 2-0, + CPUfreq : 4-2, + Governor: 6-4, + CS : 8-6, + unused : 16-8; +} KERNEL_DRIVER; + +typedef struct { + struct { + int stateCount, + stateLimit; + struct { + unsigned int exitLatency; /* in US */ + int powerUsage; /* in mW */ + unsigned int targetResidency; /* in US */ + char Name[CPUIDLE_NAME_LEN], + Desc[CPUIDLE_NAME_LEN]; + } State[CPUIDLE_STATE_MAX]; + char Name[CPUIDLE_NAME_LEN]; + } IdleDriver; + struct { + char Name[CPUFREQ_NAME_LEN], + Governor[CPUFREQ_NAME_LEN]; + } FreqDriver; +} OS_DRIVER; + +#ifndef TASK_COMM_LEN +#define TASK_COMM_LEN 16 +#endif + +#define CODENAME_LEN 32 + +enum SORTBYFIELD {F_STATE, F_RTIME, F_UTIME, F_STIME, F_PID, F_COMM}; +#define SORTBYCOUNT (1 + F_COMM) + +typedef struct { + unsigned long long runtime, + usertime, + systime; + pid_t pid, /* type of __kernel_pid_t is integer */ + tgid, + ppid; + short int state; /* TASK_STATE_MAX = 0x10000 */ + short int wake_cpu; /* limited to 64K CPUs */ + char comm[TASK_COMM_LEN]; +} TASK_MCB; + +typedef struct { + unsigned long totalram, + sharedram, + freeram, + bufferram, + totalhigh, + freehigh; +} MEM_MCB; + +#define SYSGATE_STRUCT_SIZE ( sizeof(int) \ + + sizeof(unsigned int) \ + + 4 * MAX_UTS_LEN ) + +#if defined(TASK_ORDER) && (TASK_ORDER > 0) +#define TASK_LIMIT (((4096 << TASK_ORDER) - SYSGATE_STRUCT_SIZE) \ + / sizeof(TASK_MCB)) +#else +#define TASK_LIMIT (((4096 << 5) - SYSGATE_STRUCT_SIZE) \ + / sizeof(TASK_MCB)) +#endif + +/* Input-Output Control */ +#define COREFREQ_TOGGLE_OFF 0x0 +#define COREFREQ_TOGGLE_ON 0x1 + +#define COREFREQ_IOCTL_MAGIC 0xc3 + +enum { + MACHINE_CONTROLLER, + MACHINE_INTERVAL, + MACHINE_AUTOCLOCK, + MACHINE_EXPERIMENTAL, + MACHINE_INTERRUPTS, + MACHINE_LIMIT_IDLE, + MACHINE_CPU_IDLE, + MACHINE_CPU_FREQ, + MACHINE_GOVERNOR, + MACHINE_CLOCK_SOURCE, + MACHINE_FORMULA_SCOPE, + MACHINE_IDLE_ROUTE +}; + +enum { + TECHNOLOGY_HWP, + TECHNOLOGY_HWP_EPP, +}; + +#define COREFREQ_ORDER_MAGIC 0xc6 + +enum COREFREQ_MAGIC_COMMAND { +/* Master Ring Commands */ + COREFREQ_IOCTL_SYSUPDT = _IO(COREFREQ_IOCTL_MAGIC, 0x1), + COREFREQ_IOCTL_SYSONCE = _IO(COREFREQ_IOCTL_MAGIC, 0x2), + COREFREQ_IOCTL_MACHINE = _IO(COREFREQ_IOCTL_MAGIC, 0x3), + COREFREQ_IOCTL_TECHNOLOGY = _IO(COREFREQ_IOCTL_MAGIC, 0x4), + COREFREQ_IOCTL_CPU_OFF = _IO(COREFREQ_IOCTL_MAGIC, 0x5), + COREFREQ_IOCTL_CPU_ON = _IO(COREFREQ_IOCTL_MAGIC, 0x6), + COREFREQ_IOCTL_TURBO_CLOCK = _IO(COREFREQ_IOCTL_MAGIC, 0x7), + COREFREQ_IOCTL_RATIO_CLOCK = _IO(COREFREQ_IOCTL_MAGIC, 0x8), +/* COREFREQ_IOCTL_ = _IO(COREFREQ_IOCTL_MAGIC, 0x9),*/ + COREFREQ_IOCTL_UNCORE_CLOCK = _IO(COREFREQ_IOCTL_MAGIC, 0xa), + COREFREQ_IOCTL_CLEAR_EVENTS = _IO(COREFREQ_IOCTL_MAGIC, 0xb), +/* Child Ring Commands */ + COREFREQ_ORDER_MACHINE = _IO(COREFREQ_ORDER_MAGIC, 0x1), + COREFREQ_ORDER_ATOMIC = _IO(COREFREQ_ORDER_MAGIC, 0x2), + COREFREQ_ORDER_CRC32 = _IO(COREFREQ_ORDER_MAGIC, 0x3), + COREFREQ_ORDER_CONIC = _IO(COREFREQ_ORDER_MAGIC, 0x4), + COREFREQ_ORDER_TURBO = _IO(COREFREQ_ORDER_MAGIC, 0x5), + COREFREQ_ORDER_MONTE_CARLO = _IO(COREFREQ_ORDER_MAGIC, 0x6), + COREFREQ_KERNEL_MISC = _IO(COREFREQ_ORDER_MAGIC, 0xc), + COREFREQ_SESSION_APP = _IO(COREFREQ_ORDER_MAGIC, 0xd), + COREFREQ_TASK_MONITORING = _IO(COREFREQ_ORDER_MAGIC, 0xe), + COREFREQ_TOGGLE_SYSGATE = _IO(COREFREQ_ORDER_MAGIC, 0xf) +}; + +enum PATTERN { + RESET_CSP, + ALL_SMT, + RAND_SMT, + RR_SMT, + USR_CPU +}; + +enum { + CONIC_ELLIPSOID, + CONIC_HYPERBOLOID_ONE_SHEET, + CONIC_HYPERBOLOID_TWO_SHEETS, + CONIC_ELLIPTICAL_CYLINDER, + CONIC_HYPERBOLIC_CYLINDER, + CONIC_TWO_PARALLEL_PLANES, + CONIC_VARIATIONS +}; + +enum { + SESSION_CLI, + SESSION_GUI +}; + +enum { + TASK_TRACKING, + TASK_SORTING, + TASK_INVERSING +}; + +/* Linked list */ +#define GetPrev(node) (node->prev) + +#define GetNext(node) (node->next) + +#define GetHead(list) (list)->head + +#define SetHead(list, node) GetHead(list) = node + +#define GetTail(list) (list)->tail + +#define SetDead(list) SetHead(list, NULL) + +#define IsHead(list, node) (GetHead(list) == node) + +#define IsDead(list) (GetHead(list) == NULL) + +#define IsCycling(node) ( \ + (GetNext(node) == node) && (GetPrev(node) == node) \ +) + +#define GetFocus(list) GetHead(list) + +#define RemoveNodeFromList(node, list) \ +({ \ + GetNext(GetPrev(node)) = GetNext(node); \ + GetPrev(GetNext(node)) = GetPrev(node); \ +}) + +#define AppendNodeToList(node, list) \ +({ \ + GetPrev(node) = GetHead(list); \ + GetNext(node) = GetNext(GetHead(list)); \ + GetPrev(GetNext(GetHead(list))) = node; \ + GetNext(GetHead(list)) = node; \ +}) + +/* Error Reasons management: Kernel errno is interleaved into reason codes. */ +enum REASON_CLASS { + RC_SUCCESS = 0, + RC_OK_SYSGATE = 1, + RC_OK_COMPUTE = 2, + RC_CMD_SYNTAX = 3, + RC_SHM_FILE = 4, + RC_SHM_MMAP = 5, + RC_PERM_ERR = 6, + RC_MEM_ERR = 7, + RC_EXEC_ERR = 8, + RC_SYS_CALL = 9, + /* Source: /include/uapi/asm-generic/errno-base.h @ ERANGE + 1 */ + RC_DRIVER_BASE = 35, + RC_UNIMPLEMENTED = RC_DRIVER_BASE + 1, + RC_EXPERIMENTAL = RC_DRIVER_BASE + 2, + RC_TURBO_PREREQ = RC_DRIVER_BASE + 3, + RC_UNCORE_PREREQ = RC_DRIVER_BASE + 4, + RC_PSTATE_NOT_FOUND = RC_DRIVER_BASE + 5, + RC_CLOCKSOURCE = RC_DRIVER_BASE + 6, + RC_DRIVER_LAST = RC_DRIVER_BASE + 6 +}; + +/* Definition of Ring structures - The message is 128 bits long. */ +typedef struct { + unsigned short lo: 16, + hi: 16; +} RING_ARG_DWORD; + +typedef union { + unsigned long long arg: 64; + struct { + RING_ARG_DWORD dl; + RING_ARG_DWORD dh; + }; +} RING_ARG_QWORD; + +typedef struct { + union { + unsigned long long arg: 64; + struct { + RING_ARG_DWORD dl; + RING_ARG_DWORD dh; + }; + }; + enum COREFREQ_MAGIC_COMMAND cmd: 32; + union { + unsigned int sub: 32; + struct { + unsigned int drc: 6-0,/*64 of errno & reason codes*/ + tds: 32-6; /*Epoch time difference sec*/ + }; + }; +} RING_CTRL; + +#define RING_NULL(Ring) \ +({ \ + ( (Ring.head - Ring.tail) == 0 ); \ +}) + +#define RING_FULL(Ring) \ +({ \ + ( (Ring.head - Ring.tail) == RING_SIZE ); \ +}) + +#if defined(FEAT_DBG) && (FEAT_DBG > 2) && (FEAT_DBG < 100) +FEAT_MSG("Macroing:RING_MOVE(XMM)") +#define RING_MOVE(_dst, _src) \ +({ \ + __asm__ volatile \ + ( \ + "movdqa %[src] , %%xmm1" "\n\t" \ + "movdqa %%xmm1 , %[dst]" \ + :[dst] "=m" ( _dst ) \ + :[src] "m" ( _src ) \ + : "%xmm1","memory" \ + ); \ +}) +#else +#define RING_MOVE(_dst, _src) \ +({ \ + _dst.arg = _src.arg; \ + _dst.cmd = _src.cmd; \ + _dst.sub = _src.sub; \ +}) +#endif + +#define RING_READ(Ring, _ctrl) \ +({ \ + unsigned int tail = Ring.tail++ & (RING_SIZE - 1); \ + RING_MOVE(_ctrl, Ring.buffer[tail]); \ +}) + +#define RING_WRITE_0xPARAM( _sub, Ring, _cmd) \ +({ \ + RING_CTRL ctrl = { \ + .arg = 0x0LU, \ + .cmd = (_cmd), .sub = (_sub) \ + }; \ + unsigned int head = Ring.head++ & (RING_SIZE - 1); \ + RING_MOVE(Ring.buffer[head], ctrl); \ +}) + +#define RING_WRITE_1xPARAM( _sub, Ring, _cmd, _arg) \ +({ \ + RING_CTRL ctrl = { \ + .arg = (_arg), \ + .cmd = (_cmd), .sub = (_sub) \ + }; \ + unsigned int head = Ring.head++ & (RING_SIZE - 1); \ + RING_MOVE(Ring.buffer[head], ctrl); \ +}) + +#define RING_WRITE_2xPARAM( _sub, Ring, _cmd, _dllo, _dlhi) \ +({ \ + RING_CTRL ctrl = { \ + .dl = {.lo = (_dllo), .hi = (_dlhi)}, \ + .dh = {.lo = 0x0U , .hi = 0x0U }, \ + .cmd = (_cmd), .sub = (_sub) \ + }; \ + unsigned int head = Ring.head++ & (RING_SIZE - 1); \ + RING_MOVE(Ring.buffer[head], ctrl); \ +}) + +#define RING_WRITE_3xPARAM( _sub, Ring, _cmd, _dllo, _dlhi, _dhlo) \ +({ \ + RING_CTRL ctrl = { \ + .dl = {.lo = (_dllo), .hi = (_dlhi)}, \ + .dh = {.lo = (_dhlo), .hi = 0x0U }, \ + .cmd = (_cmd), .sub = (_sub) \ + }; \ + unsigned int head = Ring.head++ & (RING_SIZE - 1); \ + RING_MOVE(Ring.buffer[head], ctrl); \ +}) + +#define RING_WRITE_4xPARAM(_sub, Ring, _cmd, _dllo, _dlhi, _dhlo, _dhhi)\ +({ \ + RING_CTRL ctrl = { \ + .dl = {.lo = (_dllo), .hi = (_dlhi)}, \ + .dh = {.lo = (_dhlo), .hi = (_dhhi)}, \ + .cmd = (_cmd), .sub = (_sub) \ + }; \ + unsigned int head = Ring.head++ & (RING_SIZE - 1); \ + RING_MOVE(Ring.buffer[head], ctrl); \ +}) + +#define RING_WRITE_DISPATCH(_1,_2,_3,_4,_5,_6,_7,RING_WRITE_CURSOR, ...)\ + RING_WRITE_CURSOR + +#define RING_WRITE_SUB_CMD( ... ) \ + RING_WRITE_DISPATCH(__VA_ARGS__,RING_WRITE_4xPARAM, /*7*/ \ + RING_WRITE_3xPARAM, /*6*/ \ + RING_WRITE_2xPARAM, /*5*/ \ + RING_WRITE_1xPARAM, /*4*/ \ + RING_WRITE_0xPARAM, /*3*/ \ + NULL, /*2*/ \ + NULL) /*1*/ \ + ( __VA_ARGS__ ) + +#define RING_WRITE( ... ) RING_WRITE_SUB_CMD( 0x0U, __VA_ARGS__ ) + +enum SMB_STRING { + SMB_BIOS_VENDOR, + SMB_BIOS_VERSION, + SMB_BIOS_RELEASE, + SMB_SYSTEM_VENDOR, + SMB_PRODUCT_NAME, + SMB_PRODUCT_VERSION, + SMB_PRODUCT_SERIAL, + SMB_PRODUCT_SKU, + SMB_PRODUCT_FAMILY, + SMB_BOARD_VENDOR, + SMB_BOARD_NAME, + SMB_BOARD_VERSION, + SMB_BOARD_SERIAL, + SMB_PHYS_MEM_ARRAY, + SMB_MEM_0_LOCATOR, + SMB_MEM_1_LOCATOR, + SMB_MEM_2_LOCATOR, + SMB_MEM_3_LOCATOR, + SMB_MEM_0_MANUFACTURER, + SMB_MEM_1_MANUFACTURER, + SMB_MEM_2_MANUFACTURER, + SMB_MEM_3_MANUFACTURER, + SMB_MEM_0_PARTNUMBER, + SMB_MEM_1_PARTNUMBER, + SMB_MEM_2_PARTNUMBER, + SMB_MEM_3_PARTNUMBER, + SMB_STRING_COUNT +}; + +typedef union { + char String[SMB_STRING_COUNT][MAX_UTS_LEN]; + struct { + struct { + char Vendor[MAX_UTS_LEN], + Version[MAX_UTS_LEN], + Release[MAX_UTS_LEN]; + } BIOS; + struct { + char Vendor[MAX_UTS_LEN]; + } System; + struct { + char Name[MAX_UTS_LEN], + Version[MAX_UTS_LEN], + Serial[MAX_UTS_LEN], + SKU[MAX_UTS_LEN], + Family[MAX_UTS_LEN]; + } Product; + struct { + char Vendor[MAX_UTS_LEN], + Name[MAX_UTS_LEN], + Version[MAX_UTS_LEN], + Serial[MAX_UTS_LEN]; + } Board; + struct { + struct { + char Array[MAX_UTS_LEN]; + } Memory; + } Phys; + struct { + char Locator[MC_MAX_DIMM][MAX_UTS_LEN], + Manufacturer[MC_MAX_DIMM][MAX_UTS_LEN], + PartNumber[MC_MAX_DIMM][MAX_UTS_LEN]; + } Memory; + }; +} SMBIOS_ST; + +#define ROUND_TO_PAGES(_size) \ +( \ + (__typeof__(_size)) PAGE_SIZE \ + * (((_size) + (__typeof__(_size)) PAGE_SIZE - 1) \ + / (__typeof__(_size)) PAGE_SIZE) \ +) + +#define KMAX(M, m) ((M) > (m) ? (M) : (m)) +#define KMIN(m, M) ((m) < (M) ? (m) : (M)) + +#define StrCopy(_dest, _src, _max) \ +({ \ + size_t _min = KMIN((_max - 1), strlen(_src)); \ + memcpy(_dest, _src, _min); \ + _dest[_min] = '\0'; \ +}) + +#define StrFormat( _str, _size, _fmt, ... ) \ + snprintf((char*) _str, (size_t) _size, (char*) _fmt, __VA_ARGS__) + +#define StrLenFormat( _ret, ... ) \ +({ \ + int lret = StrFormat( __VA_ARGS__ ); \ + _ret = lret > 0 ? ( __typeof__ (_ret) ) lret : 0; \ +}) + +#define ZLIST( ... ) (char *[]) { __VA_ARGS__ , NULL } + +#define TIMESPEC(nsec) \ +({ \ + struct timespec tsec = { \ + .tv_sec = (time_t) 0, \ + .tv_nsec = nsec \ + }; \ + tsec; \ +}) + +#define COREFREQ_STRINGIFY(_number) #_number + +#define COREFREQ_SERIALIZE(_major, _minor, _rev) \ + COREFREQ_STRINGIFY(_major) "." \ + COREFREQ_STRINGIFY(_minor) "." \ + COREFREQ_STRINGIFY(_rev) + +#define COREFREQ_VERSION COREFREQ_SERIALIZE( COREFREQ_MAJOR, \ + COREFREQ_MINOR, \ + COREFREQ_REV ) + +#define COREFREQ_FORMAT_STR(_length) "%" COREFREQ_STRINGIFY(_length) "s" + +typedef struct { + struct { + unsigned long long max_freq_Hz; + unsigned short core_count, + task_order; + } builtIn; + unsigned short major, + minor, + rev; +} FOOTPRINT; + +#define SET_FOOTPRINT(_place, _Hz, _CC, _order, _major, _minor, _rev) \ +({ \ + _place.builtIn.max_freq_Hz = _Hz; \ + _place.builtIn.core_count = _CC; \ + _place.builtIn.task_order = _order; \ + _place.major = _major; \ + _place.minor = _minor; \ + _place.rev = _rev ; \ +}) + +#define CHK_FOOTPRINT(_place, _Hz, _CC, _order, _major, _minor, _rev) \ +( \ + (_place.builtIn.max_freq_Hz == _Hz) && \ + (_place.builtIn.core_count == _CC) && \ + (_place.builtIn.task_order == _order) && \ + (_place.major == _major) && \ + (_place.minor == _minor) && \ + (_place.rev == _rev) \ +) + +#define UNUSED(expr) do { (void)(expr); } while (0) + +#define EMPTY_STMT() do { } while (0) + +#ifndef fallthrough + #if defined __has_attribute + #if __has_attribute(fallthrough) + #define fallthrough __attribute__((fallthrough)) + #else + #define fallthrough /* Fallthrough */ + #endif + #else + #define fallthrough /* Fallthrough */ + #endif +#endif diff --git a/ckms.ini b/ckms.ini new file mode 100644 index 00000000..9bcfb86d --- /dev/null +++ b/ckms.ini @@ -0,0 +1,17 @@ +# CoreFreq +# Copyright (C) 2015-2024 CYRIL COURTIAT +# Licenses: GPL2 +# +# Chimera Kernel Module System +# +[general] +name = corefreqk +version = 1.97 +strip = yes +make = gmake +initramfs = no +[hooks] +build = ${MAKE} ${CKMS_MAKE_ARGS} +[module.corefreqk] +path = build +dest = extra diff --git a/corefreqd.service b/corefreqd.service index 5b0bd11f..0af8ceba 100644 --- a/corefreqd.service +++ b/corefreqd.service @@ -1,5 +1,5 @@ # CoreFreq -# Copyright (C) 2015-2023 CYRIL COURTIAT +# Copyright (C) 2015-2024 CYRIL COURTIAT # Licenses: GPL2 [Unit] diff --git a/dkms.conf b/dkms.conf index 89a2e690..d4db8e58 100644 --- a/dkms.conf +++ b/dkms.conf @@ -1,27 +1,29 @@ # CoreFreq -# Copyright (C) 2015-2023 CYRIL COURTIAT +# Copyright (C) 2015-2024 CYRIL COURTIAT # Licenses: GPL2 # AUTOINSTALL="yes" -REMAKE_INITRD="no" -DRV_PATH=/kernel/drivers/misc -DRV_VERSION=1.96 +## REMAKE_INITRD="no" +DRV_PATH=/updates +DRV_VERSION=1.97 PACKAGE_NAME="corefreqk" PACKAGE_VERSION="$DRV_VERSION" BUILT_MODULE_NAME[0]="corefreqk" +BUILT_MODULE_LOCATION[0]="build/" DEST_MODULE_LOCATION[0]="$DRV_PATH" -CLEAN="make -C $source_tree/$PACKAGE_NAME-$PACKAGE_VERSION KERNELDIR=$kernel_source_dir clean" +# CLEAN="make -C $source_tree/$PACKAGE_NAME-$PACKAGE_VERSION KERNELDIR=$kernel_source_dir clean" MAKE[0]="make -C $source_tree/$PACKAGE_NAME-$PACKAGE_VERSION KERNELDIR=$kernel_source_dir" # -DAEMON="\$source_tree/\$PACKAGE_NAME-\$PACKAGE_VERSION/corefreqd" -CLIENT="\$source_tree/\$PACKAGE_NAME-\$PACKAGE_VERSION/corefreq-cli" +DAEMON="\$source_tree/\$PACKAGE_NAME-\$PACKAGE_VERSION/build/corefreqd" +CLIENT="\$source_tree/\$PACKAGE_NAME-\$PACKAGE_VERSION/build/corefreq-cli" SCRIPT="scripter.sh" COMMAND="install -Dm 0755 -s -t /bin" -OBJECTS="\$source_tree/\$PACKAGE_NAME-\$PACKAGE_VERSION/*.o" +OBJECTS="\$source_tree/\$PACKAGE_NAME-\$PACKAGE_VERSION/build/*.o" BINARIES="/bin/corefreqd /bin/corefreq-cli" CLEANUP="rm -f" # -POST_BUILD="$SCRIPT $COMMAND -- $DAEMON $CLIENT" POST_INSTALL="$SCRIPT $CLEANUP -- $OBJECTS" POST_REMOVE="$SCRIPT $CLEANUP -- $BINARIES" # +PRE_BUILD="$SCRIPT make -- prepare" +PRE_INSTALL="$SCRIPT $COMMAND -- $DAEMON $CLIENT" diff --git a/scripter.sh b/scripter.sh index 343958af..4b99b02b 100755 --- a/scripter.sh +++ b/scripter.sh @@ -1,7 +1,7 @@ #!/bin/bash # # CoreFreq -# Copyright (C) 2015-2023 CYRIL COURTIAT +# Copyright (C) 2015-2024 CYRIL COURTIAT # Licenses: GPL2 # if (( $# > 2 )); then diff --git a/amd_reg.h b/x86_64/amd_reg.h similarity index 95% rename from amd_reg.h rename to x86_64/amd_reg.h index 4d51dd0b..b3937521 100644 --- a/amd_reg.h +++ b/x86_64/amd_reg.h @@ -1,6 +1,6 @@ /* * CoreFreq - * Copyright (C) 2015-2023 CYRIL COURTIAT + * Copyright (C) 2015-2024 CYRIL COURTIAT * Licenses: GPL2 */ @@ -30,6 +30,8 @@ #define MSR_AMD_F17H_IRPERF MSR_F17H_IRPERF #endif +#define MSR_AMD_PREFETCH_CTRL 0xc0000108 + #ifndef MSR_AMD64_SYSCFG #define MSR_AMD64_SYSCFG 0xc0010010 #endif @@ -78,6 +80,7 @@ #define MSR_AMD_F17H_HW_PSTATE_STATUS 0xc0010293 #define MSR_AMD_F17H_CSTATE_POLICY 0xc0010294 #define MSR_AMD_F17H_CSTATE_CONFIG 0xc0010296 +#define MSR_AMD_F17H_PMGT_DEFAULT 0xc0010297 #ifndef MSR_AMD_RAPL_POWER_UNIT #define MSR_AMD_RAPL_POWER_UNIT 0xc0010299 @@ -202,6 +205,9 @@ /* Sources: PPR for AMD Family 19h Model 51h A1 : REGx59800...x59B14 */ #define SMU_AMD_THM_TCTL_CCD_REGISTER_F17H 0x00059954 +#define SMU_AMD_THM_TCTL_CCD_REGISTER_F19H_11H \ + (SMU_AMD_THM_TCTL_REGISTER_F17H + 0x300) + #define SMU_AMD_THM_TCTL_CCD_REGISTER_F19H_61H \ (SMU_AMD_THM_TCTL_REGISTER_F17H + 0x308) @@ -294,6 +300,22 @@ typedef union }; } AMD_PRED_CMD; +typedef union +{ /* MSR 0xc0000108 supported iff CPUID_Fn80000021_EAX[13] */ + unsigned long long value; + struct + { /* Scope[Core] */ + unsigned long long + L1Stream : 1-0, + L1Stride : 2-1, + L1Region : 3-2, + L2Stream : 4-3, + ReservedBits1 : 5-4, + UpDown : 6-5, + ReservedBits2 : 64-6; + }; /* F19_M01, F19_M61, EPYC 9004 */ +} AMD_PREFETCH_CONTROL; + typedef union { unsigned long long value; @@ -370,7 +392,7 @@ typedef union { unsigned long long SmmLock : 1-0, - SLOWFENCE : 2-1, /* Slow SFENCE Enable. */ + SLOWFENCE : 2-1, /* Slow SFENCE Enable. */ Reserved1 : 3-2, TlbCacheDis : 4-3, INVDWBINVD : 5-4, /* This bit is required to be set for CC6 */ @@ -542,9 +564,13 @@ typedef union UnitMask : 16-8, Reserved1 : 22-16, CounterEn : 23-22, - Reserved2 : 48-23, + Reserved2 : 42-23, + CoreID : 45-42, + Reserved3 : 46-45, + EnAllSlices : 47-46, + EnAllCores : 48-47, SliceMask : 52-48, - Reserved3 : 56-52, + Reserved4 : 56-52, ThreadMask : 64-56; }; } ZEN_L3_PERF_CTL; @@ -624,9 +650,11 @@ typedef union MaxCpuCof : 21-15, MaxDFCof : 26-21, CpbCap : 29-26, - Reserved1 : 32-29, + Reserved1 : 30-29, + MaxCpuCofPlus50 : 31-30, /* RO: Add 50 MHz to Max CPU frequency */ + Reserved2 : 32-31, PC6En : 33-32, /* RW: 0=Disable PC6. 1=Enable PC6 */ - Reserved2 : 64-33; + Reserved3 : 64-33; }; } ZEN_PMGT_MISC; @@ -641,7 +669,11 @@ typedef union HYST_TMRSEL : 9-7, HYST_TMRLEN : 14-9, CFOH_TMRLEN : 21-14, - Reserved1 : 32-21, + CFOH_TMRSEL : 22-21, + C1E_TMRSEL : 24-22, + C1E_TMRLEN : 29-24, + C1E_EN : 30-29, + Reserved1 : 32-30, CFSM_DURATION : 39-32, CFSM_THRESHOLD : 42-39, CFSM_MISPREDACT : 44-42, @@ -651,7 +683,8 @@ typedef union IRM_MAXDEPTH : 60-56, CIT_EN : 61-60, CIT_FASTSAMPLE : 62-61, - Reserved2 : 64-62; + CLT_EN : 63-62, + Reserved2 : 64-63; }; } ZEN_CSTATE_POLICY; @@ -669,10 +702,59 @@ typedef union Reserved2 : 16-15, CCR2_CC2DFSID : 22-16, CCR2_CC6EN : 23-22, - Reserved3 : 64-23; + Reserved3 : 32-23, + CCR0_CFOHTMR_LEN: 39-32, + CCR0_CC1E_EN : 40-39, + CCR1_CFOHTMR_LEN: 47-40, + CCR1_CC1E_EN : 48-47, + CCR2_CFOHTMR_LEN: 55-48, + CCR2_CC1E_EN : 56-55, + Reserved4 : 64-56; }; } ZEN_CSTATE_CONFIG; +typedef union +{ + unsigned long long value; /* Per Core: MSR 0xC0010297 (R/0) */ + struct + { + unsigned long long + CC6EXIT_DFSID : 6-0, + CC6EXIT_POPUP_EN: 7-6, + CC6CF_DFSID : 13-7, + CC6CF_POPDN_EN : 14-13, + CC6EXIT_STRETCHEN:15-14, + CC6EX_STRCLKDIV2: 16-15, /* CC6EXIT_STRETCHCLKDIV2 */ + CC6EX_STRALLDIV2: 17-16, /* CC6EXIT_STRETCHALLDIV2 */ + CC6CF_STRETCHEN : 18-17, + CC6CF_STRCLKDIV2: 19-18, /* CC6CF_STRETCHCLKDIV2 */ + CC6CF_STRALLDIV2: 20-19, /* CC6CF_STRETCHALLDIV2 */ + Reserved : 64-20; + }; + struct + { + unsigned long long + CC6CF_PSMID : 14-0, + CC6CF_DSMID : 24-14, + CC6CF_CKS_DSMID : 32-24, + PSTATE_DFSID : 38-32, + PSTATE_POPDN_EN : 39-38, + PSTATE_STRETCHEN: 40-39, + CC6CF_EN : 41-40, + CC6CF_DFSID : 47-41, + CC6CF_STRETCHEN : 48-47, + CC6CF_IVREN : 49-48, + CC6CF_CKS_DSMID2: 51-49, + CC6EXIT_EN : 52-51, + CC6EXIT_DFSID : 58-52, + CC6EXIT_STRETCHEN:59-58, + CC6EXIT_IVREN : 60-59, + CC6EXIT_CKS_DSMID:62-60, + POSTPC6_EN : 63-62, + AUTOSEQCTL_EN : 64-63; + } HWPSTATE; +} ZEN_PMGT_DEFAULT; + typedef union { unsigned long long value; @@ -837,7 +919,8 @@ typedef union F16h_SSBD : 30-29, ReservedBits5 : 33-30, F16h_SSBD_EN : 34-33, /* F16h: 1=Enable SSBD per SMT */ - ReservedBits6 : 54-34, + F17h_AgenPick : 35-34, /* Zen 2: Limited Early Redirect Window */ + ReservedBits6 : 54-35, F15h_SSBD : 55-54, /* F15h,F16h,some F17h: disable SpecLockMap */ ReservedBits7 : 64-55; }; @@ -903,9 +986,11 @@ typedef union unsigned long long ReservedBits1 : 1-0, LFENCE_SER : 2-1, /* F10h: LFENCE as serializing instruction */ - ReservedBits2 : 23-2, + ReservedBits2 : 9-2, + Cross_Proc_Leak : 10-9, /* F17h: CVE-2023-20593 */ + ReservedBits3 : 23-10, CLFLUSH_SER : 24-23, /* F12h: CLFLUSH as serializing instruction */ - ReservedBits3 : 64-24; + ReservedBits4 : 64-24; }; } AMD_DE_CFG; /* Family: 12h ... 17h */ @@ -1203,9 +1288,16 @@ typedef union ReservedBits2 : 50-49, XTEn : 51-50, IntCapXTEn : 52-51, - ReservedBits3 : 54-52, + vCmdEn : 53-52, + vIommuEn : 54-53, GAUpdateDis : 55-54, - ReservedBits4 : 64-55; + GAPPIEn : 56-55, + TMPMEn : 57-56, + ReservedBits3 : 58-57, + GCR3TRPMode : 59-58, + IRTCacheDis : 60-59, + GstBufferTRPMode: 61-60, + SNPAVICEn : 64-61; }; } AMD_IOMMU_CTRL_REG; diff --git a/bitasm.h b/x86_64/bitasm.h similarity index 99% rename from bitasm.h rename to x86_64/bitasm.h index 524cac96..a3aff6c7 100644 --- a/bitasm.h +++ b/x86_64/bitasm.h @@ -1,6 +1,6 @@ /* * CoreFreq - * Copyright (C) 2015-2023 CYRIL COURTIAT + * Copyright (C) 2015-2024 CYRIL COURTIAT * Licenses: GPL2 */ diff --git a/corefreq-api.h b/x86_64/corefreq-api.h similarity index 94% rename from corefreq-api.h rename to x86_64/corefreq-api.h index 7f64d48b..78e9ea73 100644 --- a/corefreq-api.h +++ b/x86_64/corefreq-api.h @@ -1,6 +1,6 @@ /* * CoreFreq - * Copyright (C) 2015-2023 CYRIL COURTIAT + * Copyright (C) 2015-2024 CYRIL COURTIAT * Licenses: GPL2 */ @@ -442,7 +442,9 @@ typedef struct }; Bit64 XCR0 __attribute__ ((aligned (8))); + Bit64 XSS __attribute__ ((aligned (8))); Bit64 SYSCFG __attribute__ ((aligned (8))); + HWCR HWCR __attribute__ ((aligned (8))); } SystemRegister; unsigned int Bind; @@ -896,6 +898,8 @@ typedef struct BitCC TM_Mask __attribute__ ((aligned (16))); BitCC ODCM_Mask __attribute__ ((aligned (16))); BitCC DCU_Mask __attribute__ ((aligned (16))); + BitCC PCORE_Mask __attribute__ ((aligned (16))); + BitCC ECORE_Mask __attribute__ ((aligned (16))); BitCC PowerMgmt_Mask __attribute__ ((aligned (16))); BitCC SpeedStep_Mask __attribute__ ((aligned (16))); BitCC TurboBoost_Mask __attribute__ ((aligned (16))); @@ -911,6 +915,7 @@ typedef struct BitCC ARCH_CAP_Mask __attribute__ ((aligned (16))); BitCC /* AMD */ BTC_NOBR_Mask __attribute__ ((aligned (16))); BitCC WDT_Mask __attribute__ ((aligned (16))); + BitCC /* AMD */ XPROC_LEAK_Mask __attribute__ ((aligned (16))); enum THERMAL_FORMULAS thermalFormula; enum VOLTAGE_FORMULAS voltageFormula; @@ -1030,10 +1035,20 @@ typedef struct BitCC TM1 __attribute__ ((aligned (16))); BitCC TM2 __attribute__ ((aligned (16))); BitCC ODCM __attribute__ ((aligned (16))); - BitCC L1_HW_Prefetch __attribute__ ((aligned (16))); + BitCC L1_HW_Prefetch __attribute__ ((aligned (16))); BitCC L1_HW_IP_Prefetch __attribute__((aligned (16))); - BitCC L2_HW_Prefetch __attribute__ ((aligned (16))); + BitCC /* Intel */ L1_NPP_Prefetch __attribute__ ((aligned (16))); + BitCC /* Intel */ L1_Scrubbing __attribute__ ((aligned (16))); + BitCC L2_HW_Prefetch __attribute__ ((aligned (16))); BitCC L2_HW_CL_Prefetch __attribute__((aligned (16))); + BitCC /* Intel */ L2_AMP_Prefetch __attribute__ ((aligned (16))); + BitCC /* Intel */ L2_NLP_Prefetch __attribute__ ((aligned (16))); + BitCC /* AMD */ L1_Stride_Pf __attribute__ ((aligned (16))); + BitCC /* AMD */ L1_Region_Pf __attribute__ ((aligned (16))); + BitCC /* AMD */ L1_Burst_Pf __attribute__ ((aligned (16))); + BitCC /* AMD */ L2_Stream_HW_Pf __attribute__ ((aligned (16))); + BitCC /* AMD */ L2_UpDown_Pf __attribute__ ((aligned (16))); + BitCC /* Intel */ LLC_Streamer __attribute__ ((aligned (16))); BitCC PowerMgmt __attribute__ ((aligned (16))); BitCC SpeedStep __attribute__ ((aligned (16))); BitCC TurboBoost __attribute__ ((aligned (16))); @@ -1088,6 +1103,11 @@ typedef struct BitCC DDPD_U_DIS __attribute__ ((aligned (16))); BitCC BHI_DIS_S __attribute__ ((aligned (16))); BitCC /* AMD */ BTC_NOBR __attribute__ ((aligned (16))); + BitCC /* AMD */ XPROC_LEAK __attribute__ ((aligned (16))); + BitCC /* AMD */ AGENPICK __attribute__ ((aligned (16))); + BitCC /* Intel */ OC_UTILIZED __attribute__ ((aligned (16))); + BitCC /* Intel */ OC_UNDERVOLT __attribute__ ((aligned (16))); + BitCC /* Intel */ OC_UNLOCKED __attribute__ ((aligned (16))); struct { Bit64 Signal __attribute__ ((aligned (8))); @@ -1133,6 +1153,8 @@ typedef struct #define DID_INTEL_SLM_PTR 0x0f00 /* Source: [Atom/Airmont] Pentium(R) CPU N3700 */ #define DID_INTEL_AIRMONT_HB 0x2280 +/* Source: Intel(R) Celeron(R) CPU J3455 @ 1.50GHz */ +#define DID_INTEL_GOLDMONT_HB 0x5af0 /* Source: /include/linux/pci_ids.h */ #define DID_INTEL_I7_MCR 0x2c18 #define DID_INTEL_I7_MC_CH0_CTRL 0x2c20 @@ -1178,14 +1200,14 @@ typedef struct #define DID_INTEL_IIO_CORE_REG 0x3728 /* Source: /include/linux/pci_ids.h */ #define DID_INTEL_SNB_IMC_HA0 0x3ca0 -/* Source: 2nd Generation Intel® Core™ Processor Family Vol2 */ +/* Source: 2nd Generation Intel Core Processor Family Vol2 */ #define DID_INTEL_SNB_IMC_SA 0x0100 #define DID_INTEL_SNB_IMC_0104 0x0104 /* Source: /drivers/edac/sb_edac.c */ /*TODO( Harware missing )*/ #define DID_INTEL_IVB_IMC_HA0 0x0ea0 #define DID_INTEL_IVB_IMC_HA1 0x0e60 -/* Source: 3rd Generation Intel® Core™ Processor Family Vol2 */ +/* Source: 3rd Generation Intel Core Processor Family Vol2 */ #define DID_INTEL_IVB_IMC_SA 0x0150 #define DID_INTEL_IVB_IMC_0154 0x0154 /* Source: Intel Xeon Processor E5 & E7 v1 Datasheet Vol 2 */ @@ -1309,7 +1331,7 @@ typedef struct /* Power Control Unit */ /* PCU: Device=30 - Function=3 */ #define DID_INTEL_HSW_EP_CAPABILITY 0x2fc0 -/* Source: 4th, 5th Generation Intel® Core™ Processor Family Vol2 §3.0 */ +/* Source: 4th, 5th Generation Intel Core Processor Family Vol2 Chap. 3.0 */ #define DID_INTEL_HASWELL_IMC_HA0 0x2fa0 #define DID_INTEL_HASWELL_IMC_SA 0x0c00 #define DID_INTEL_HASWELL_MH_IMC_HA0 0x0c04 @@ -1318,18 +1340,18 @@ typedef struct #define DID_INTEL_BROADWELL_D_IMC_HA0 0x1610 #define DID_INTEL_BROADWELL_H_IMC_HA0 0x1614 #define DID_INTEL_BROADWELL_U_IMC_HA0 0x1618 -/* Source: 6th Generation Intel® Processor Datasheet for U/Y-Platforms Vol2 */ +/* Source: 6th Generation Intel Processor Datasheet for U/Y-Platforms Vol2 */ #define DID_INTEL_SKYLAKE_U_IMC_HA 0x1904 #define DID_INTEL_SKYLAKE_Y_IMC_HA 0x190c -/* Source: 6th Generation Intel® Processor Datasheet for S-Platforms Vol2 */ +/* Source: 6th Generation Intel Processor Datasheet for S-Platforms Vol2 */ #define DID_INTEL_SKYLAKE_S_IMC_HAD 0x190f #define DID_INTEL_SKYLAKE_S_IMC_HAQ 0x191f -/* Source: 6th Generation Intel® Processor Datasheet for H-Platforms Vol2 */ +/* Source: 6th Generation Intel Processor Datasheet for H-Platforms Vol2 */ #define DID_INTEL_SKYLAKE_H_IMC_HAD 0x1900 #define DID_INTEL_SKYLAKE_H_IMC_HAQ 0x1910 /* Source: Intel Xeon Processor E3-1200 v5 Product Family */ #define DID_INTEL_SKYLAKE_DT_IMC_HA 0x1918 -/* Source:7th Generation Intel® Processor for S-Platforms & Core X-Series Vol2*/ +/* Source:7th Generation Intel Processor for S-Platforms & Core X-Series Vol2*/ #define DID_INTEL_KABYLAKE_H_IMC_HAD 0x5900 #define DID_INTEL_KABYLAKE_U_IMC_HA 0x5904 #define DID_INTEL_KABYLAKE_Y_IMC_HA 0x590c @@ -1340,10 +1362,10 @@ typedef struct #define DID_INTEL_KABYLAKE_U_IMC_HAQ 0x5914 #define DID_INTEL_KABYLAKE_S_IMC_HAQ 0x591f #define DID_INTEL_KABYLAKE_X_IMC_HAQ 0x5906 -/* Source: 8th Generation Intel® Processor for S-Platforms Datasheet Vol2 */ +/* Source: 8th Generation Intel Processor for S-Platforms Datasheet Vol2 */ #define DID_INTEL_COFFEELAKE_S_IMC_HAQ 0x3e1f #define DID_INTEL_COFFEELAKE_S_IMC_HAS 0x3ec2 -/* Source: 8th and 9th Generation Intel® Core™ and Xeon™ E Processor Families */ +/* Source: 8th and 9th Generation Intel Core and Xeon E Processor Families */ #define DID_INTEL_COFFEELAKE_R_S_IMC_HAD 0x3e0f #define DID_INTEL_COFFEELAKE_R_U_IMC_HAD 0x3ecc #define DID_INTEL_COFFEELAKE_R_U_IMC_HAQ 0x3ed0 @@ -1356,7 +1378,7 @@ typedef struct #define DID_INTEL_COFFEELAKE_R_S_IMC_HAQ 0x3e33 #define DID_INTEL_COFFEELAKE_R_S_IMC_HAS 0x3eca #define DID_INTEL_COFFEELAKE_R_S_IMC_HAO 0x3e32 -/* Source: 8th Generation Intel® Core™ Processor Families Datasheet Vol2 */ +/* Source: 8th Generation Intel Core Processor Families Datasheet Vol2 */ #define DID_INTEL_WHISKEYLAKE_U_IMC_HAD 0x3e35 #define DID_INTEL_WHISKEYLAKE_U_IMC_HAQ 0x3e34 #define DID_INTEL_CANNONLAKE_U_IMC_HB 0x5a04 @@ -1393,7 +1415,7 @@ typedef struct #define DID_INTEL_TIGERLAKE_U3_IMC 0x9a12 #define DID_INTEL_TIGERLAKE_U4_IMC 0x9a14 #define DID_INTEL_TIGERLAKE_H_IMC 0x9a36 -/* Source: 11th Generation Intel® Core™ Processor Desktop Datasheet Vol1 */ +/* Source: 11th Generation Intel Core Processor Desktop Datasheet Vol1 */ #define DID_INTEL_TIGERLAKE_UP3_IMC 0xa082 #define DID_INTEL_TIGERLAKE_UP4_IMC 0xa087 #define DID_INTEL_ROCKETLAKE_S_8C_IMC_HB 0x4c43 @@ -1477,11 +1499,14 @@ typedef struct #define DID_AMD_17H_ZEN2_APU_NB_IOMMU 0x1631 /* Renoir/Cezanne */ #define DID_AMD_17H_FIREFLIGHT_NB_IOMMU 0x15f9 /* FireFlight */ #define DID_AMD_17H_ARDEN_NB_IOMMU 0x1627 /* Arden */ +/* Source: Steam Deck LCD */ +#define DID_AMD_17H_JUPITER_NB_IOMMU 0x1646 /* Van Gogh/Jupiter*/ /* Source: AMD Ryzen 5 6600H [ Zen3+ Rembrandt ] */ #define DID_AMD_19H_ZEN3_RMB_NB_IOMMU 0x14b6 /* Rembrandt */ /* Source: AMD Ryzen 9 7950X [ Zen4/Raphael ] */ #define DID_AMD_19H_ZEN4_RPL_NB_IOMMU 0x14d9 /* Raphael */ #define DID_AMD_19H_ZEN4_GNA_NB_IOMMU 0x149e /* Genoa */ +#define DID_AMD_19H_ZEN4_PHX_NB_IOMMU 0x14e9 /* Phoenix */ /* Source: /include/linux/pci_ids.h */ #define DID_AMD_17H_ZEPPELIN_DF_UMC 0x1460 /* Zeppelin */ #define DID_AMD_17H_RAVEN_DF_UMC 0x15e8 /* Raven */ @@ -1492,8 +1517,10 @@ typedef struct #define DID_AMD_17H_RAVEN2_DF_UMC 0x15eb /* Raven2 */ #define DID_AMD_17H_FIREFLIGHT_DF_UMC 0x15f3 /* FireFlight */ #define DID_AMD_17H_ARDEN_DF_UMC 0x160b /* Arden */ +#define DID_AMD_17H_JUPITER_DF_UMC 0x1660 /* Van Gogh/Jupiter*/ #define DID_AMD_19H_VERMEER_DF_UMC 0x1650 /* Vermeer */ #define DID_AMD_19H_CEZANNE_DF_UMC 0x166a /* Cezanne */ #define DID_AMD_19H_REMBRANDT_DF_UMC 0x1679 /* Rembrandt */ #define DID_AMD_19H_RAPHAEL_DF_UMC 0x14e0 /* Raphael */ #define DID_AMD_19H_GENOA_DF_UMC 0x14ad /* Genoa */ +#define DID_AMD_19H_PHOENIX_DF_UMC 0x14f0 /* Phoenix */ diff --git a/x86_64/corefreq-cli-extra.c b/x86_64/corefreq-cli-extra.c new file mode 100644 index 00000000..2d832e92 --- /dev/null +++ b/x86_64/corefreq-cli-extra.c @@ -0,0 +1,219 @@ +/* + * CoreFreq (C) 2015-2024 CYRIL COURTIAT + * Contributors: Andrew Gurinovich ; CyrIng + * Licenses: GPL2 + * + * Some ideas taken from https://github.com/cesanta/frozen/ + * under Apache 2.0 license + */ + +#include +#include +#include +#include +#include +#include + +#include "corefreq-cli-extra.h" + +#define UNUSED(expr) do { (void)(expr); } while (0) + +/* --[ JSON toolkit ]-- */ +struct json_state; + +enum JSON_STATE { + DEFAULT, IN_ARRAY, IN_ARRAY2, IN_OBJECT, IN_OBJECT2 +}; + +int json_writer_stdout(struct json_state * state, const char *str, size_t len) +{ + UNUSED(state); + return fwrite(str, len, 1, stdout); +} + +size_t get_utf8_char_len(unsigned char ch) +{ + if ((ch & 0x80) == 0) + return 1; + switch (ch & 0xf0) { + case 0xf0: + return 4; + case 0xe0: + return 3; + default: + return 2; + } +} + +/* This routine does NOT handle unicode finely - everything above 0x7f should + * be \u0000 encoded, but this requires us to be utf8 capable. Check the + * following tiny libraries(for future improvement): + * https://github.com/git/git/blob/master/utf8.c + * https://github.com/JeffBezanson/cutef8/blob/master/utf8.c + * https://github.com/sheredom/utf8.h + * https://github.com/JuliaStrings/utf8proc + */ + +int json_escape(struct json_state *state, const char *p, size_t len) +{ + size_t i, cl; + const char *hex_digits = "0123456789abcdef"; + const char *specials = "btnvfr"; + int n = 0; + + for (i = 0; i < len; i++) { + unsigned char ch = ((unsigned char *) p)[i]; + if (ch == '"' || ch == '\\') { + n += state->write(state, "\\", 1); + n += state->write(state, p + i, 1); + } else if (ch >= '\b' && ch <= '\r') { + n += state->write(state, "\\", 1); + n += state->write(state, &specials[ch - '\b'], 1); + } else if (isprint(ch)) { + n += state->write(state, p + i, 1); + } else if ((cl = get_utf8_char_len(ch)) == 1) { + n += state->write(state, "\\u00", 4); + n += state->write(state, &hex_digits[(ch >> 4) % 0xf], 1); + n += state->write(state, &hex_digits[ch % 0xf], 1); + } else { + n += state->write(state, p + i, cl); + i += cl - 1; + } + } + return n; +} + +void json_start_object(struct json_state *state) +{ + assert(state->depth < JSON_MAX_DEPTH); + /* TODO: assert(state->nested_state[state->depth] != IN_OBJECT); */ + if (state->nested_state[state->depth] == IN_ARRAY2 ) { + state->write(state, ", {", 3); + } else { + state->write(state, "{", 1); + } + if (state->nested_state[state->depth] == IN_ARRAY) { + state->nested_state[state->depth] = IN_ARRAY2; + } + if (state->nested_state[state->depth] == IN_OBJECT) { + state->nested_state[state->depth] = IN_OBJECT2; + } + state->nested_state[++state->depth] = IN_OBJECT; +} + +void json_end_object(struct json_state *state) +{ + assert(state->depth >= 0); + assert(state->nested_state[state->depth] == \ + IN_OBJECT || state->nested_state[state->depth] == IN_OBJECT2); + + state->write(state, "}", 1); + state->nested_state[state->depth--] = DEFAULT; +} + +void json_start_arr(struct json_state *state) +{ + assert(state->depth < JSON_MAX_DEPTH); + + if (state->nested_state[state->depth] == IN_ARRAY2) { + state->write(state, ", [", 3); + } else { + state->write(state, "[", 1); + } + if (state->nested_state[state->depth] == IN_ARRAY) { + state->nested_state[state->depth] = IN_ARRAY2; + } + if (state->nested_state[state->depth] == IN_OBJECT) { + state->nested_state[state->depth] = IN_OBJECT2; + } + state->nested_state[++state->depth] = IN_ARRAY; +} + +void json_end_arr(struct json_state *state) +{ + assert(state->depth >= 0); + assert(state->nested_state[state->depth] == \ + IN_ARRAY || state->nested_state[state->depth] == IN_ARRAY2); + + state->write(state, "]", 1); + state->nested_state[state->depth--] = DEFAULT; +} + +void json_key(struct json_state *state, char * key) +{ + assert(state->nested_state[state->depth] == \ + IN_OBJECT || state->nested_state[state->depth] == IN_OBJECT2); + + if (state->nested_state[state->depth] == IN_OBJECT2) { + state->write(state, ", ", 1); + } + state->write(state, "\"", 1); + json_escape(state, key, strlen(key)); + state->write(state, "\":", 2); +} + +void json_string(struct json_state *state, char * value) +{ + assert(state->nested_state[state->depth] != DEFAULT); + + if (state->nested_state[state->depth] == IN_ARRAY2) { + state->write(state, ", ", 2); + } + if (state->nested_state[state->depth] == IN_ARRAY) { + state->nested_state[state->depth] = IN_ARRAY2; + } + if (state->nested_state[state->depth] == IN_OBJECT) { + state->nested_state[state->depth] = IN_OBJECT2; + } + state->write(state, "\"", 1); + json_escape(state, value, strlen(value)); + state->write(state, "\"", 1); +} + +void json_literal(struct json_state *state, char * format, ...) +{ + assert(state->nested_state[state->depth] != DEFAULT); + + if (state->nested_state[state->depth] == IN_ARRAY2) { + state->write(state, ", ", 2); + } + if (state->nested_state[state->depth] == IN_ARRAY) { + state->nested_state[state->depth] = IN_ARRAY2; + } + if (state->nested_state[state->depth] == IN_OBJECT) { + state->nested_state[state->depth] = IN_OBJECT2; + } + va_list args; + va_start(args, format); + char buf[JSON_MAX_VALUE]; + const int rc = vsprintf(buf, format, args); + const size_t bufsz = rc > 0 ? (size_t) rc : 0; + state->write(state, buf, bufsz); + va_end(args); +} + +/* --[ UTF toolkit ]-- */ + +void ISO_8859_To_Unicode(unsigned char *pIn, unsigned char *pOut) +{ + while ( (*pIn) != '\0' ) { + if ( (*pIn) > 0x7f ) { + switch ( (*pIn) ) { + case 0xc0 ... 0xff: /* To UTF-8 Ctrl:C3 */ + (*pOut) = (*pIn) ^ 0x40; + break; + case 0xa0 ... 0xbf: /* To UTF-8 Ctrl:C2 */ + (*pOut) = (*pIn) ^ 0x60; + break; + default: + (*pOut) = 0x20; + break; + } + } else { + (*pOut) = (*pIn); + } + pIn++; + pOut++; + } + (*pOut) = '\0'; +} diff --git a/x86_64/corefreq-cli-extra.h b/x86_64/corefreq-cli-extra.h new file mode 100644 index 00000000..48854e9f --- /dev/null +++ b/x86_64/corefreq-cli-extra.h @@ -0,0 +1,30 @@ +/* + * CoreFreq (C) 2015-2024 CYRIL COURTIAT + * Contributors: Andrew Gurinovich ; CyrIng + * Licenses: GPL2 + * + * Some ideas taken from github.com/cesanta/frozen + * under Apache 2.0 license + */ + +#define JSON_MAX_DEPTH 32 +#define JSON_MAX_VALUE 4096 + +struct json_state { + int (*write)(struct json_state* state, const char *str, size_t len); + unsigned char nested_state[JSON_MAX_DEPTH]; + unsigned char depth; +}; + +extern int json_writer_stdout( struct json_state * state, + const char *str, + size_t len) ; +extern void json_start_object(struct json_state *state) ; +extern void json_end_object(struct json_state *state) ; +extern void json_start_arr(struct json_state *state) ; +extern void json_end_arr(struct json_state *state) ; +extern void json_key(struct json_state *state, char * key) ; +extern void json_string(struct json_state *state, char * value) ; +extern void json_literal(struct json_state *state, char * format, ...) ; + +extern void ISO_8859_To_Unicode(unsigned char*, unsigned char*) ; diff --git a/corefreq-cli-json.c b/x86_64/corefreq-cli-json.c similarity index 91% rename from corefreq-cli-json.c rename to x86_64/corefreq-cli-json.c index 8517cf45..f6a7de7b 100644 --- a/corefreq-cli-json.c +++ b/x86_64/corefreq-cli-json.c @@ -1,5 +1,5 @@ /* - * CoreFreq (C) 2015-2023 CYRIL COURTIAT + * CoreFreq (C) 2015-2024 CYRIL COURTIAT * Contributors: Andrew Gurinovich ; CyrIng * Licenses: GPL2 */ @@ -646,95 +646,95 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm)) } json_key(&s, "Power"); { - json_start_object(&s); + json_start_object(&s); - json_key(&s, "EAX"); - { - json_start_object(&s); - json_key(&s, "DTS"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.DTS); - json_key(&s, "TurboIDA"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.TurboIDA); - json_key(&s, "ARAT"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.ARAT); - json_key(&s, "PLN"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.PLN); - json_key(&s, "ECMD"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.ECMD); - json_key(&s, "PTM"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.PTM); - json_key(&s, "HWP_Registers"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.HWP_Reg); - json_key(&s, "HWP_Interrupt"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.HWP_Int); - json_key(&s, "HWP_Activity"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.HWP_Act); - json_key(&s, "HWP_EPP"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.HWP_EPP); - json_key(&s, "HWP_Package"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.HWP_Pkg); - json_key(&s, "HDC_Registers"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.HDC_Reg); - json_key(&s, "Turbo_V3"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.Turbo_V3); - json_key(&s, "HWP_Highest_Pref_Cap"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.HWP_HPrf); - json_key(&s, "HWP_PECI"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.HWP_PECI); - json_key(&s, "HWP_Flex"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.HWP_Flex); - json_key(&s, "HWP_Fast"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.HWP_Fast); - json_key(&s, "HWFB_Cap"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.HWFB_Cap); - json_key(&s, "HWP_Idle_SMT"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.HWP_Idle); - json_key(&s, "ITD_MSR"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.ITD_MSR); - json_key(&s, "THERM_INT_MSR"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.THERM_INT_MSR); - json_end_object(&s); - } - json_key(&s, "EBX"); - { - json_start_object(&s); - json_key(&s, "DTS_INT_Threshld"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EBX.DTS_INT_Threshld); - json_end_object(&s); - } - json_key(&s, "ECX"); - { - json_start_object(&s); - if (vendor == CRC_INTEL) { - json_key(&s, "HCF_Cap"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.ECX.HCF_Cap); - json_key(&s, "ACNT_Cap"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.ECX.ACNT_Cap); - json_key(&s, "SETBH"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.ECX.SETBH); - json_key(&s, "ITD_CLS"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.ECX.ITD_CLS); - } else if ((vendor == CRC_AMD) || (vendor == CRC_HYGON)) { - json_key(&s, "EffFreq"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.ECX.EffFreq); - } else { - fprintf(stderr, "Unknown vendor"); - } + json_key(&s, "EAX"); + { + json_start_object(&s); + json_key(&s, "DTS"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.DTS); + json_key(&s, "TurboIDA"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.TurboIDA); + json_key(&s, "ARAT"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.ARAT); + json_key(&s, "PLN"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.PLN); + json_key(&s, "ECMD"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.ECMD); + json_key(&s, "PTM"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.PTM); + json_key(&s, "HWP_Registers"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.HWP_Reg); + json_key(&s, "HWP_Interrupt"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.HWP_Int); + json_key(&s, "HWP_Activity"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.HWP_Act); + json_key(&s, "HWP_EPP"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.HWP_EPP); + json_key(&s, "HWP_Package"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.HWP_Pkg); + json_key(&s, "HDC_Registers"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.HDC_Reg); + json_key(&s, "Turbo_V3"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.Turbo_V3); + json_key(&s, "HWP_Highest_Pref_Cap"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.HWP_HPrf); + json_key(&s, "HWP_PECI"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.HWP_PECI); + json_key(&s, "HWP_Flex"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.HWP_Flex); + json_key(&s, "HWP_Fast"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.HWP_Fast); + json_key(&s, "HWFB_Cap"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.HWFB_Cap); + json_key(&s, "HWP_Idle_SMT"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.HWP_Idle); + json_key(&s, "ITD_MSR"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.ITD_MSR); + json_key(&s, "THERM_INT_MSR"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.THERM_INT_MSR); + json_end_object(&s); + } + json_key(&s, "EBX"); + { + json_start_object(&s); + json_key(&s, "DTS_INT_Threshld"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EBX.DTS_INT_Threshld); + json_end_object(&s); + } + json_key(&s, "ECX"); + { + json_start_object(&s); + if (vendor == CRC_INTEL) { + json_key(&s, "HCF_Cap"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.ECX.HCF_Cap); + json_key(&s, "ACNT_Cap"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.ECX.ACNT_Cap); + json_key(&s, "SETBH"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.ECX.SETBH); + json_key(&s, "ITD_CLS"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.ECX.ITD_CLS); + } else if ((vendor == CRC_AMD) || (vendor == CRC_HYGON)) { + json_key(&s, "EffFreq"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.ECX.EffFreq); + } else { + fprintf(stderr, "Unknown vendor"); + } - json_end_object(&s); - } - json_key(&s, "EDX"); - { - json_start_object(&s); - json_key(&s, "HWFB_Cap"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EDX.HWFB_Cap); - json_key(&s, "HWFB_pSz"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EDX.HWFB_pSz); - json_key(&s, "HWFB_Idx"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EDX.HWFB_Idx); - json_end_object(&s); - } - json_end_object(&s); + json_end_object(&s); + } + json_key(&s, "EDX"); + { + json_start_object(&s); + json_key(&s, "HWFB_Cap"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EDX.HWFB_Cap); + json_key(&s, "HWFB_pSz"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EDX.HWFB_pSz); + json_key(&s, "HWFB_Idx"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EDX.HWFB_Idx); + json_end_object(&s); + } + json_end_object(&s); } json_key(&s, "ExtFeature"); { @@ -947,6 +947,10 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm)) json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature_Leaf1_EAX.FSRS); json_key(&s, "Fast_Short_REP_CMPSB"); json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature_Leaf1_EAX.FSRC); + json_key(&s, "FRED"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature_Leaf1_EAX.FRED); + json_key(&s, "LKGS"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature_Leaf1_EAX.LKGS); json_key(&s, "WRMSRNS"); json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature_Leaf1_EAX.WRMSRNS); json_key(&s, "AMX_FP16"); @@ -973,6 +977,8 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm)) json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature_Leaf1_EDX.PREFETCHI); json_key(&s, "CET_SSS"); json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature_Leaf1_EDX.CET_SSS); + json_key(&s, "AVX10"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature_Leaf1_EDX.AVX10); json_end_object(&s); } @@ -1256,35 +1262,35 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm)) { json_start_object(&s); if (vendor == CRC_INTEL) { - json_key(&s, "Inv_TSC"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AdvPower.EDX.Inv_TSC); + json_key(&s, "Inv_TSC"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AdvPower.EDX.Inv_TSC); } else if ((vendor == CRC_AMD) || (vendor == CRC_HYGON)) { - json_key(&s, "TS"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AdvPower.EDX.TS); - json_key(&s, "Legacy_FID"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AdvPower.EDX.FID); - json_key(&s, "Legacy_VID"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AdvPower.EDX.VID); - json_key(&s, "TTP"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AdvPower.EDX.TTP); - json_key(&s, "TM"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AdvPower.EDX.TM); - json_key(&s, "STC"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AdvPower.EDX.STC); - json_key(&s, "_100MHz"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AdvPower.EDX._100MHz); - json_key(&s, "HwPstate"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AdvPower.EDX.HwPstate); - json_key(&s, "TscInv"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AdvPower.EDX.TscInv); - json_key(&s, "CPB"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AdvPower.EDX.CPB); - json_key(&s, "EffFrqRO"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AdvPower.EDX.EffFrqRO); - json_key(&s, "ProcFeedback"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AdvPower.EDX.ProcFb); - json_key(&s, "ProcPower"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AdvPower.EDX.ProcPwr); + json_key(&s, "TS"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AdvPower.EDX.TS); + json_key(&s, "Legacy_FID"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AdvPower.EDX.FID); + json_key(&s, "Legacy_VID"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AdvPower.EDX.VID); + json_key(&s, "TTP"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AdvPower.EDX.TTP); + json_key(&s, "TM"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AdvPower.EDX.TM); + json_key(&s, "STC"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AdvPower.EDX.STC); + json_key(&s, "_100MHz"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AdvPower.EDX._100MHz); + json_key(&s, "HwPstate"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AdvPower.EDX.HwPstate); + json_key(&s, "TscInv"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AdvPower.EDX.TscInv); + json_key(&s, "CPB"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AdvPower.EDX.CPB); + json_key(&s, "EffFrqRO"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AdvPower.EDX.EffFrqRO); + json_key(&s, "ProcFeedback"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AdvPower.EDX.ProcFb); + json_key(&s, "ProcPower"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.AdvPower.EDX.ProcPwr); } else { fprintf(stderr, "Unknown vendor"); } @@ -1501,10 +1507,30 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm)) json_literal(&s, "%llu", RO(Shm)->Proc.Technology.L1_HW_Prefetch); json_key(&s, "L1_HW_IP_Prefetch"); json_literal(&s, "%llu", RO(Shm)->Proc.Technology.L1_HW_IP_Prefetch); + json_key(&s, "L1_NPP_Prefetch"); + json_literal(&s, "%llu", RO(Shm)->Proc.Technology.L1_NPP_Prefetch); + json_key(&s, "L1_Scrubbing"); + json_literal(&s, "%llu", RO(Shm)->Proc.Technology.L1_Scrubbing); json_key(&s, "L2_HW_Prefetch"); json_literal(&s, "%llu", RO(Shm)->Proc.Technology.L2_HW_Prefetch); json_key(&s, "L2_HW_CL_Prefetch"); json_literal(&s, "%llu", RO(Shm)->Proc.Technology.L2_HW_CL_Prefetch); + json_key(&s, "L2_AMP_Prefetch"); + json_literal(&s, "%llu", RO(Shm)->Proc.Technology.L2_AMP_Prefetch); + json_key(&s, "L2_NLP_Prefetch"); + json_literal(&s, "%llu", RO(Shm)->Proc.Technology.L2_NLP_Prefetch); + json_key(&s, "L1_Stride_Prefetch"); + json_literal(&s, "%llu", RO(Shm)->Proc.Technology.L1_Stride_Pf); + json_key(&s, "L1_Region_Prefetch"); + json_literal(&s, "%llu", RO(Shm)->Proc.Technology.L1_Region_Pf); + json_key(&s, "L1_Burst_Prefetch"); + json_literal(&s, "%llu", RO(Shm)->Proc.Technology.L1_Burst_Pf); + json_key(&s, "L2_Stream_HW_Prefetch"); + json_literal(&s, "%llu", RO(Shm)->Proc.Technology.L2_Stream_HW_Pf); + json_key(&s, "L2_UpDown_Prefetch"); + json_literal(&s, "%llu", RO(Shm)->Proc.Technology.L2_UpDown_Pf); + json_key(&s, "LLC_Streamer"); + json_literal(&s, "%llu", RO(Shm)->Proc.Technology.LLC_Streamer); json_end_object(&s); } @@ -1794,6 +1820,12 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm)) json_literal(&s, "%llu", RO(Shm)->Proc.Mechanisms.XAPIC_DIS); json_key(&s, "PBRSB_NO"); json_literal(&s, "%llu", RO(Shm)->Proc.Mechanisms.PBRSB_NO); + json_key(&s, "OC_UTILIZED"); + json_literal(&s, "%llu", RO(Shm)->Proc.Mechanisms.OC_UTILIZED); + json_key(&s, "OC_UNDERVOLT"); + json_literal(&s, "%llu", RO(Shm)->Proc.Mechanisms.OC_UNDERVOLT); + json_key(&s, "OC_UNLOCKED"); + json_literal(&s, "%llu", RO(Shm)->Proc.Mechanisms.OC_UNLOCKED); json_key(&s, "IPRED_DIS_U"); json_literal(&s, "%llu", RO(Shm)->Proc.Mechanisms.IPRED_DIS_U); json_key(&s, "IPRED_DIS_S"); @@ -1816,6 +1848,10 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm)) json_literal(&s, "%llu", RO(Shm)->Proc.Mechanisms.DRAM_Scrambler); json_key(&s, "TSME"); json_literal(&s, "%llu", RO(Shm)->Proc.Mechanisms.TSME); + json_key(&s, "XPROC_LEAK"); + json_literal(&s, "%llu", RO(Shm)->Proc.Mechanisms.XPROC_LEAK); + json_key(&s, "AGENPICK"); + json_literal(&s, "%llu", RO(Shm)->Proc.Mechanisms.AGENPICK); json_end_object(&s); } @@ -2147,9 +2183,15 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm)) snprintf(hexStr, 32, "0x%llx", RO(Shm)->Cpu[cpu].SystemRegister.XCR0); json_key(&s, "XCR0"); json_string(&s, hexStr); + snprintf(hexStr, 32, "0x%llx", RO(Shm)->Cpu[cpu].SystemRegister.XSS); + json_key(&s, "XSS"); + json_string(&s, hexStr); snprintf(hexStr, 32, "0x%llx", RO(Shm)->Cpu[cpu].SystemRegister.SYSCFG); json_key(&s, "SYSCFG"); json_string(&s, hexStr); + snprintf(hexStr, 32, "0x%llx", RO(Shm)->Cpu[cpu].SystemRegister.HWCR); + json_key(&s, "HWCR"); + json_string(&s, hexStr); json_end_object(&s); } json_key(&s, "CpuID"); diff --git a/x86_64/corefreq-cli-json.h b/x86_64/corefreq-cli-json.h new file mode 100644 index 00000000..39de3675 --- /dev/null +++ b/x86_64/corefreq-cli-json.h @@ -0,0 +1,7 @@ +/* + * CoreFreq (C) 2015-2024 CYRIL COURTIAT + * Contributors: Andrew Gurinovich ; CyrIng + * Licenses: GPL2 + */ + +extern void JsonSysInfo(RO(SHM_STRUCT)*) ; diff --git a/corefreq-cli-rsc-en.h b/x86_64/corefreq-cli-rsc-en.h similarity index 94% rename from corefreq-cli-rsc-en.h rename to x86_64/corefreq-cli-rsc-en.h index f18e008e..81d107a0 100644 --- a/corefreq-cli-rsc-en.h +++ b/x86_64/corefreq-cli-rsc-en.h @@ -1,12 +1,12 @@ /* * CoreFreq - * Copyright (C) 2015-2023 CYRIL COURTIAT + * Copyright (C) 2015-2024 CYRIL COURTIAT * Licenses: GPL2 */ #define RSC_COPY0_CODE_EN " by CyrIng " #define RSC_COPY1_CODE_EN " " -#define RSC_COPY2_CODE_EN " (C)2015-2023 CYRIL COURTIAT " +#define RSC_COPY2_CODE_EN " (C)2015-2024 CYRIL COURTIAT " #define RSC_LAYOUT_LCD_RESET_CODE "::::" @@ -886,8 +886,13 @@ #define RSC_LARGEST_EXT_FUNC_CODE_EN "Largest Extended Function" #define RSC_SYS_REGS_TITLE_CODE_EN " System Registers " +#define RSC_SYS_REG_FLAGS_CF_CODE_EN " Carry Flag " +#define RSC_SYS_REG_FLAGS_ZF_CODE_EN " Zero Flag " +#define RSC_SYS_REG_FLAGS_SF_CODE_EN " Sign Flag " #define RSC_SYS_REG_FLAGS_TF_CODE_EN " Trap Flag " #define RSC_SYS_REG_FLAGS_IF_CODE_EN " Interrupt Flag " +#define RSC_SYS_REG_FLAGS_DF_CODE_EN " Direction Flag " +#define RSC_SYS_REG_FLAGS_OF_CODE_EN " Overflow Flag " #define RSC_SYS_REG_FLAGS_IOPL_CODE_EN " I/O Privilege Level " #define RSC_SYS_REG_FLAGS_NT_CODE_EN " Nested Task " #define RSC_SYS_REG_FLAGS_RF_CODE_EN " Resume Flag " @@ -943,6 +948,7 @@ #define RSC_SYS_REG_CR4_UINTR_CODE_EN " User Interrupts Enable " #define RSC_SYS_REG_CR4_LAM_CODE_EN " LAM_SUP for Supervisor pointers " +#define RSC_SYS_REG_CR4_FRED_CODE_EN " Flexible Return and Event Delivery " #define RSC_SYS_REGS_CR8_CODE_EN " Control Register 8 " #define RSC_SYS_REG_CR8_TPL_CODE_EN " Task Priority Level " @@ -977,6 +983,8 @@ #define RSC_SYS_REG_XCR0_MPK_CODE_EN " Memory Protection Keys " #define RSC_SYS_REG_XCR0_CEU_CODE_EN " CET User State Management " #define RSC_SYS_REG_XCR0_CES_CODE_EN " CET Supervisor State Management " +#define RSC_SYS_REG_XCR0_AMX_CODE_EN " Advanced Matrix Extensions " +#define RSC_SYS_REG_XCR0_APX_CODE_EN " Advanced Performance Extensions " #define RSC_SYS_REG_XCR0_LWP_CODE_EN " Lightweight Profiling " #define RSC_SYS_REGS_CFG_CODE_EN " System Configuration Register " #define RSC_SYS_REG_CFG_MFD_CODE_EN " MtrrFixDram Enable " @@ -984,10 +992,40 @@ #define RSC_SYS_REG_CFG_MVDM_CODE_EN " MtrrVarDram Enable " #define RSC_SYS_REG_CFG_TOM2_CODE_EN " MtrrTom2 Enable " #define RSC_SYS_REG_CFG_FWB_CODE_EN " Tom2ForceMemTypeWriteBack " -#define RSC_SYS_REG_CFG_MEM_CODE_EN " MemEncryptionMode Enable " +#define RSC_SYS_REG_CFG_MEM_CODE_EN " MemEncryptionMode Enable (SMEE) " #define RSC_SYS_REG_CFG_SNP_CODE_EN " SecureNestedPaging Enable " -#define RSC_SYS_REG_CFG_VMPL_CODE_EN " Virtual Machine Privilege Levels " +#define RSC_SYS_REG_CFG_VMPL_CODE_EN " Virtual Machine Privilege Levels (VMPL) " #define RSC_SYS_REG_CFG_HMK_CODE_EN " HostMultiKeyMemEncryptionMode " +#define RSC_SYS_REGS_HWCR_CODE_EN " Hardware Configuration Register " +#define RSC_SYS_REG_HWCR_SMM_CODE_EN " SMM Configuration Lock " +#define RSC_SYS_REG_HWCR_SLW_CODE_EN " Slow SFENCE Enable " +#define RSC_SYS_REG_HWCR_TLB_CODE_EN " TLB Cacheable Memory Disable " +#define RSC_SYS_REG_HWCR_WBI_CODE_EN " Convert INVD to WBINVD " +#define RSC_SYS_REG_HWCR_FF_CODE_EN " TLB Flush Filter Disable " +#define RSC_SYS_REG_HWCR_FRR_CODE_EN " Legacy FERR signaling/exception " +#define RSC_SYS_REG_HWCR_IG_CODE_EN " IGNNE Port Emulation Enable " +#define RSC_SYS_REG_HWCR_SMW_CODE_EN " MONITOR[X] and MWAIT[X] Disable " +#define RSC_SYS_REG_HWCR_UMW_CODE_EN " MONITOR and MWAIT User Mode Enable " +#define RSC_SYS_REG_HWCR_HLT_CODE_EN " Halt-Exit special bus cycle Enable " +#define RSC_SYS_REG_HWCR_SMI_CODE_EN " SMI special bus cycle Disable " +#define RSC_SYS_REG_HWCR_RSM_CODE_EN " RSM special bus cycle Disable " +#define RSC_SYS_REG_HWCR_SSE_CODE_EN " SSE Instructions Disable " +#define RSC_SYS_REG_HWCR_WRP_CODE_EN " 32-bit Address Wrap Disable " +#define RSC_SYS_REG_HWCR_MC_CODE_EN " Machine Check Status Write Enable " +#define RSC_SYS_REG_HWCR_IO_CODE_EN " IO-space configuration causes #GP " +#define RSC_SYS_REG_HWCR_P0_CODE_EN " Lock TSC to current P0 frequency " +#define RSC_SYS_REG_HWCR_PRB_CODE_EN " Force probes for RdSized and WrSized " +#define RSC_SYS_REG_HWCR_INC_CODE_EN " TSC increments at the P0 frequency " +#define RSC_SYS_REG_HWCR_CPB_CODE_EN " Core Performance Boost Disable " +#define RSC_SYS_REG_HWCR_HCF_CODE_EN " Effective frequency MWAIT counting " +#define RSC_SYS_REG_HWCR_ROC_CODE_EN " Effective frequency R/O counters " +#define RSC_SYS_REG_HWCR_SMU_CODE_EN " SMU Lock " +#define RSC_SYS_REG_HWCR_CSE_CODE_EN " Connected Standby Enable " +#define RSC_SYS_REG_HWCR_IR_CODE_EN " Instructions Retired counter Enable " +#define RSC_SYS_REG_HWCR_SBR_CODE_EN " SMM_BASE save state area Disable " +#define RSC_SYS_REG_HWCR_TPR_CODE_EN " Fast TPR lowering Disable " +#define RSC_SYS_REG_HWCR_PG_CODE_EN " SMM Page Config Lock " +#define RSC_SYS_REG_HWCR_ID_CODE_EN " CPUID User Disable " #define RSC_ISA_TITLE_CODE_EN " Instruction Set Extensions " @@ -1106,8 +1144,10 @@ #define RSC_FEATURES_FZRM_CODE_EN "Fast Zero-length REP MOVSB" #define RSC_FEATURES_ERMS_CODE_EN "Fast-String Operation" #define RSC_FEATURES_FMA_CODE_EN "Fused Multiply Add" +#define RSC_FEATURES_FRED_CODE_EN "Flexible Return and Event Delivery" #define RSC_FEATURES_HFI_CODE_EN "Hardware Feedback Interface" #define RSC_FEATURES_HLE_CODE_EN "Hardware Lock Elision" +#define RSC_FEATURES_HTT_CODE_EN "Hyper-Threading Technology" #define RSC_FEATURES_HwP_CODE_EN "Hardware P-state control" #define RSC_FEATURES_HRESET_CODE_EN "History Reset" #define RSC_FEATURES_HYBRID_CODE_EN "Hybrid part processor" @@ -1117,6 +1157,7 @@ #define RSC_FEATURES_LM_CODE_EN "Long Mode 64 bits" #define RSC_FEATURES_LASS_CODE_EN "Linear Address Space Separation" #define RSC_FEATURES_LAM_CODE_EN "Linear Address Masking" +#define RSC_FEATURES_LKGS_CODE_EN "Load Kernel GS segment register" #define RSC_FEATURES_LWP_CODE_EN "LightWeight Profiling" #define RSC_FEATURES_MBE_CODE_EN "Memory Bandwidth Enforcement" #define RSC_FEATURES_MCA_CODE_EN "Machine-Check Architecture" @@ -1170,10 +1211,21 @@ #define RSC_TECHNOLOGIES_TITLE_CODE_EN " Technologies " #define RSC_TECHNOLOGIES_DCU_CODE_EN "Data Cache Unit" #define RSC_TECHNOLOGIES_ICU_CODE_EN "Instruction Cache Unit" +#define RSC_TECHNOLOGIES_PF_CODE_EN "Cache Prefetchers" #define RSC_TECH_L1_HW_PREFETCH_CODE_EN "L1 Prefetcher" #define RSC_TECH_L1_HW_IP_PREFETCH_CODE_EN "L1 IP Prefetcher" +#define RSC_TECH_L1_NPP_PREFETCH_CODE_EN "L1 Next Page Prefetcher" +#define RSC_TECH_L1_SCRUBBING_CODE_EN "L1 Scrubbing" #define RSC_TECH_L2_HW_PREFETCH_CODE_EN "L2 Prefetcher" -#define RSC_TECH_L2_HW_CL_PREFETCH_CODE_EN "L2 Line Prefetcher" +#define RSC_TECH_L2_HW_CL_PREFETCH_CODE_EN "L2 Adjacent Cache Line Prefetcher" +#define RSC_TECH_L2_AMP_PREFETCH_CODE_EN "L2 Adaptive Multipath Probability" +#define RSC_TECH_L2_NLP_PREFETCH_CODE_EN "L2 Next Line Prefetcher" +#define RSC_TECH_L1_STRIDE_PF_CODE_EN "L1 Stride Prefetcher" +#define RSC_TECH_L1_REGION_PF_CODE_EN "L1 Region Prefetcher" +#define RSC_TECH_L1_BURST_PF_CODE_EN "L1 Burst Prefetch Mode" +#define RSC_TECH_L2_STREAM_HW_PF_CODE_EN "L2 Stream HW Prefetcher" +#define RSC_TECH_L2_UPDOWN_PF_CODE_EN "L2 Up/Down Prefetcher" +#define RSC_TECH_LLC_STREAMER_CODE_EN "LLC Streamer" #define RSC_TECHNOLOGIES_SMM_CODE_EN "System Management Mode" #define RSC_TECHNOLOGIES_HTT_CODE_EN "Hyper-Threading" #define RSC_TECHNOLOGIES_EIST_CODE_EN "SpeedStep" @@ -1241,6 +1293,8 @@ #define RSC_PERF_MON_MONITOR_MWAIT_CODE_EN "MONITOR/MWAIT" #define RSC_PERF_MON_MWAIT_IDX_CSTATE_CODE_EN "State index" #define RSC_PERF_MON_MWAIT_SUB_CSTATE_CODE_EN "Sub C-State" +#define RSC_PERF_MON_MWAIT_EMX_MWAIT_CODE_EN "Monitor-Mwait Extensions" +#define RSC_PERF_MON_MWAIT_IBE_MWAIT_CODE_EN "Interrupt Break-Event" #define RSC_PERF_MON_CORE_CYCLE_CODE_EN "Core Cycles" #define RSC_PERF_MON_INST_RET_CODE_EN "Instructions Retired" @@ -1914,7 +1968,7 @@ #define RSC_ERROR_CMD_SYNTAX_CODE_EN \ "CoreFreq." \ - " Copyright (C) 2015-2023 CYRIL COURTIAT\n\n" \ + " Copyright (C) 2015-2024 CYRIL COURTIAT\n\n" \ "Usage:\t%s [-Option ] [-Command ]\n"\ "\n Interface options\n" \ "\t-Oa\tAbsolute frequency\n" \ @@ -2007,6 +2061,7 @@ #define RSC_MECH_SPLA_CODE_EN "Arch - Split Locked Access Exception" #define RSC_MECH_SNOOP_FILTER_CODE_EN "Arch - Snoop Filter QoS Mask" #define RSC_MECH_PSFD_CODE_EN "Arch - No Fast Predictive Store Forwarding" +#define RSC_MECH_EPSF_CODE_EN "Arch - Enhanced Predictive Store Forwarding" #define RSC_MECH_IBRS_ALWAYS_ON_CODE_EN "IBRS Always-On preferred by processor" #define RSC_MECH_IBRS_PREFERRED_CODE_EN "IBRS preferred over software solution" #define RSC_MECH_IBRS_SAME_MODE_CODE_EN "IBRS provides same speculation limits" @@ -2034,9 +2089,18 @@ #define RSC_MECH_MCDT_NO_CODE_EN "No MXCSR Configuration Dependent Timing" #define RSC_MECH_BTC_NO_CODE_EN "No Branch Type Confusion" #define RSC_MECH_BTC_NOBR_CODE_EN "BTC on Non-Branch instruction" +#define RSC_MECH_XPROC_LEAK_CODE_EN "Arch - Cross Processor Information Leak" +#define RSC_MECH_AGENPICK_CODE_EN "Limited Early Redirect Window" +#define RSC_MECH_OVERCLOCKING_CODE_EN "Overclocking" +#define RSC_MECH_OC_UTILIZED_CODE_EN "Overclocking Utilized" +#define RSC_MECH_OC_UNDERVOLT_CODE_EN "Undervolt Protection" +#define RSC_MECH_OC_UNLOCKED_CODE_EN "Overclocking Secure Status" #define RSC_SECURITY_CPUID_KL_CODE_EN "CPUID Key Locker" #define RSC_SECURITY_AESKLE_CODE_EN "AES Key Locker instructions" +#define RSC_SECURITY_CET_SS_CODE_EN "CET Shadow Stack features" +#define RSC_SECURITY_CET_IBT_CODE_EN "CET Indirect Branch Tracking" +#define RSC_SECURITY_CET_SSS_CODE_EN "CET Supervisor Shadow Stack" #define RSC_SECURITY_WIDE_KL_CODE_EN "AES Wide Key Locker instructions" #define RSC_SECURITY_SGX1_CODE_EN "Software Guard SGX1 Extensions" #define RSC_SECURITY_SGX2_CODE_EN "Software Guard SGX2 Extensions" @@ -2111,8 +2175,18 @@ #define RSC_BOX_CU_L1_TITLE_CODE " Cache Unit L1 Prefetcher " #define RSC_BOX_CU_L1_IP_TITLE_CODE " Cache Unit L1 IP Prefetcher " +#define RSC_BOX_CU_L1_NPP_TITLE_CODE " Cache Unit L1 NPP Prefetcher " +#define RSC_BOX_L1_SCRUBBING_TITLE_CODE " Cache Unit L1 Scrubbing " #define RSC_BOX_CU_L2_TITLE_CODE " Cache Unit L2 Prefetcher " #define RSC_BOX_CU_L2_CL_TITLE_CODE " Cache Unit L2 CL Prefetcher " +#define RSC_BOX_L2_AMP_TITLE_CODE " Adaptive Multipath Probability " +#define RSC_BOX_CU_L2_NLP_TITLE_CODE " Cache Unit L2 NLP Prefetcher " +#define RSC_BOX_L1_STRIDE_TITLE_CODE " L1 Stride Prefetcher " +#define RSC_BOX_L1_REGION_TITLE_CODE " L1 Region Prefetcher " +#define RSC_BOX_L1_BURST_TITLE_CODE " L1 Burst Prefetcher " +#define RSC_BOX_L2_STREAM_HW_TITLE_CODE " L2 Stream HW Prefetcher " +#define RSC_BOX_L2_UPDOWN_TITLE_CODE " L2 Up/Down Prefetcher " +#define RSC_BOX_LLC_STREAMER_TITLE_CODE " LLC Streamer " #define RSC_BOX_EIST_TITLE_CODE " EIST " @@ -2322,6 +2396,8 @@ #define RSC_PERF_LABEL_PPC_CODE "_PPC" #define RSC_PERF_LABEL_CPC_CODE "_CPC" #define RSC_PERF_LABEL_CST_CODE "_CST" +#define RSC_PERF_LABEL_EMX_CODE "EMX" +#define RSC_PERF_LABEL_IBE_CODE "IBE" #define RSC_PERF_LABEL_HWP_CODE "HWP" #define RSC_PERF_LABEL_HDC_CODE "HDC" #define RSC_PERF_LABEL_CFG_CTRL_CODE "CONFIG" @@ -2506,8 +2582,13 @@ #define RSC_SYS_REGS_NA_CODE " - " #define RSC_SYS_REGS_HDR_CPU_CODE "CPU " #define RSC_SYS_REG_HDR_FLAGS_CODE "FLAG" +#define RSC_SYS_REG_HDR_CF_CODE " CF " +#define RSC_SYS_REG_HDR_ZF_CODE " ZF " +#define RSC_SYS_REG_HDR_SF_CODE " SF " #define RSC_SYS_REG_HDR_TF_CODE " TF " #define RSC_SYS_REG_HDR_IF_CODE " IF " +#define RSC_SYS_REG_HDR_DF_CODE " DF " +#define RSC_SYS_REG_HDR_OF_CODE " OF " #define RSC_SYS_REG_HDR_IOPL_CODE "IOPL" #define RSC_SYS_REG_HDR_NT_CODE " NT " #define RSC_SYS_REG_HDR_RF_CODE " RF " @@ -2560,6 +2641,7 @@ #define RSC_SYS_REG_HDR_CR4_PKS_CODE " PKS" #define RSC_SYS_REG_HDR_CR4_UINTR_CODE " U-I" #define RSC_SYS_REG_HDR_CR4_LAM_CODE " LAM" +#define RSC_SYS_REG_HDR_CR4_FRED_CODE " FRD" #define RSC_SYS_REG_HDR_CR8_CODE "CR8:" #define RSC_SYS_REG_HDR_CR8_TPL_CODE " TPL" #define RSC_SYS_REG_HDR_EFCR_CODE "EFCR" @@ -2593,6 +2675,8 @@ #define RSC_SYS_REG_HDR_XCR0_MPK_CODE " MPK" #define RSC_SYS_REG_HDR_XCR0_CEU_CODE " CEU" #define RSC_SYS_REG_HDR_XCR0_CES_CODE " CES" +#define RSC_SYS_REG_HDR_XCR0_AMX_CODE " AMX" +#define RSC_SYS_REG_HDR_XCR0_APX_CODE " APX" #define RSC_SYS_REG_HDR_XCR0_LWP_CODE " LWP" #define RSC_SYS_REG_HDR_CFG_CODE "CFG:" #define RSC_SYS_REG_HDR_CFG_MFD_CODE " MFD" @@ -2604,6 +2688,36 @@ #define RSC_SYS_REG_HDR_CFG_SNP_CODE " SNP" #define RSC_SYS_REG_HDR_CFG_VMPL_CODE " PL " #define RSC_SYS_REG_HDR_CFG_HMK_CODE " HMK" +#define RSC_SYS_REG_HDR_HWCR_CODE "HWCR" +#define RSC_SYS_REG_HDR_HWCR_SMM_CODE " SMM" +#define RSC_SYS_REG_HDR_HWCR_SLW_CODE " SLW" +#define RSC_SYS_REG_HDR_HWCR_TLB_CODE " TLB" +#define RSC_SYS_REG_HDR_HWCR_WBI_CODE " WBI" +#define RSC_SYS_REG_HDR_HWCR_FF_CODE " FF " +#define RSC_SYS_REG_HDR_HWCR_FRR_CODE "FERR" +#define RSC_SYS_REG_HDR_HWCR_IG_CODE " IG " +#define RSC_SYS_REG_HDR_HWCR_SMW_CODE " MW " +#define RSC_SYS_REG_HDR_HWCR_UMW_CODE "U-MW" +#define RSC_SYS_REG_HDR_HWCR_HLT_CODE " HLT" +#define RSC_SYS_REG_HDR_HWCR_SMI_CODE " SMI" +#define RSC_SYS_REG_HDR_HWCR_RSM_CODE " RSM" +#define RSC_SYS_REG_HDR_HWCR_SSE_CODE " SSE" +#define RSC_SYS_REG_HDR_HWCR_WRP_CODE " WRP" +#define RSC_SYS_REG_HDR_HWCR_MC_CODE " MC " +#define RSC_SYS_REG_HDR_HWCR_IO_CODE " IO " +#define RSC_SYS_REG_HDR_HWCR_P0_CODE " P0 " +#define RSC_SYS_REG_HDR_HWCR_PRB_CODE " PRB" +#define RSC_SYS_REG_HDR_HWCR_INC_CODE " INC" +#define RSC_SYS_REG_HDR_HWCR_CPB_CODE " CPB" +#define RSC_SYS_REG_HDR_HWCR_HCF_CODE " HCF" +#define RSC_SYS_REG_HDR_HWCR_ROC_CODE " ROC" +#define RSC_SYS_REG_HDR_HWCR_SMU_CODE " SMU" +#define RSC_SYS_REG_HDR_HWCR_CSE_CODE " CSE" +#define RSC_SYS_REG_HDR_HWCR_IR_CODE " IR " +#define RSC_SYS_REG_HDR_HWCR_SBR_CODE "SMMB" +#define RSC_SYS_REG_HDR_HWCR_TPR_CODE " TPR" +#define RSC_SYS_REG_HDR_HWCR_PG_CODE " PG " +#define RSC_SYS_REG_HDR_HWCR_ID_CODE "U-ID" #define RSC_ISA_3DNOW_CODE " 3DNow!/Ext [%c/%c]" #define RSC_ISA_ADX_CODE " ADX [%c]" diff --git a/corefreq-cli-rsc-fr.h b/x86_64/corefreq-cli-rsc-fr.h similarity index 94% rename from corefreq-cli-rsc-fr.h rename to x86_64/corefreq-cli-rsc-fr.h index ebd462ae..3f304169 100644 --- a/corefreq-cli-rsc-fr.h +++ b/x86_64/corefreq-cli-rsc-fr.h @@ -1,6 +1,6 @@ /* * CoreFreq - * Copyright (C) 2015-2023 CYRIL COURTIAT + * Copyright (C) 2015-2024 CYRIL COURTIAT * Licenses: GPL2 */ @@ -13,7 +13,7 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo #define RSC_COPY0_CODE_FR " par CyrIng " #define RSC_COPY1_CODE_FR " " -#define RSC_COPY2_CODE_FR " (C)2015-2023 " \ +#define RSC_COPY2_CODE_FR " (C)2015-2024 " \ "CYRIL COURTIAT " #define RSC_LAYOUT_HEADER_PROC_CODE_FR \ @@ -388,8 +388,13 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo #define RSC_LARGEST_EXT_FUNC_CODE_FR "Fonction ""\xa9""tendue maximum" #define RSC_SYS_REGS_TITLE_CODE_FR " Registres Syst""\xa8""me " +#define RSC_SYS_REG_FLAGS_CF_CODE_FR RSC_SYS_REG_FLAGS_CF_CODE_EN +#define RSC_SYS_REG_FLAGS_ZF_CODE_FR RSC_SYS_REG_FLAGS_ZF_CODE_EN +#define RSC_SYS_REG_FLAGS_SF_CODE_FR RSC_SYS_REG_FLAGS_SF_CODE_EN #define RSC_SYS_REG_FLAGS_TF_CODE_FR RSC_SYS_REG_FLAGS_TF_CODE_EN #define RSC_SYS_REG_FLAGS_IF_CODE_FR RSC_SYS_REG_FLAGS_IF_CODE_EN +#define RSC_SYS_REG_FLAGS_DF_CODE_FR RSC_SYS_REG_FLAGS_DF_CODE_EN +#define RSC_SYS_REG_FLAGS_OF_CODE_FR RSC_SYS_REG_FLAGS_OF_CODE_EN #define RSC_SYS_REG_FLAGS_IOPL_CODE_FR RSC_SYS_REG_FLAGS_IOPL_CODE_EN #define RSC_SYS_REG_FLAGS_NT_CODE_FR RSC_SYS_REG_FLAGS_NT_CODE_EN #define RSC_SYS_REG_FLAGS_RF_CODE_FR RSC_SYS_REG_FLAGS_RF_CODE_EN @@ -442,6 +447,7 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo #define RSC_SYS_REG_CR4_PKS_CODE_FR RSC_SYS_REG_CR4_PKS_CODE_EN #define RSC_SYS_REG_CR4_UINTR_CODE_FR RSC_SYS_REG_CR4_UINTR_CODE_EN #define RSC_SYS_REG_CR4_LAM_CODE_FR RSC_SYS_REG_CR4_LAM_CODE_EN +#define RSC_SYS_REG_CR4_FRED_CODE_FR RSC_SYS_REG_CR4_FRED_CODE_EN #define RSC_SYS_REGS_CR8_CODE_FR RSC_SYS_REGS_CR8_CODE_EN #define RSC_SYS_REG_CR8_TPL_CODE_FR RSC_SYS_REG_CR8_TPL_CODE_EN #define RSC_SYS_REGS_EFCR_CODE_FR RSC_SYS_REGS_EFCR_CODE_EN @@ -475,6 +481,8 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo #define RSC_SYS_REG_XCR0_MPK_CODE_FR RSC_SYS_REG_XCR0_MPK_CODE_EN #define RSC_SYS_REG_XCR0_CEU_CODE_FR RSC_SYS_REG_XCR0_CEU_CODE_EN #define RSC_SYS_REG_XCR0_CES_CODE_FR RSC_SYS_REG_XCR0_CES_CODE_EN +#define RSC_SYS_REG_XCR0_AMX_CODE_FR RSC_SYS_REG_XCR0_AMX_CODE_EN +#define RSC_SYS_REG_XCR0_APX_CODE_FR RSC_SYS_REG_XCR0_APX_CODE_EN #define RSC_SYS_REG_XCR0_LWP_CODE_FR RSC_SYS_REG_XCR0_LWP_CODE_EN #define RSC_SYS_REGS_CFG_CODE_FR RSC_SYS_REGS_CFG_CODE_EN #define RSC_SYS_REG_CFG_MFD_CODE_FR RSC_SYS_REG_CFG_MFD_CODE_EN @@ -486,6 +494,36 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo #define RSC_SYS_REG_CFG_SNP_CODE_FR RSC_SYS_REG_CFG_SNP_CODE_EN #define RSC_SYS_REG_CFG_VMPL_CODE_FR RSC_SYS_REG_CFG_VMPL_CODE_EN #define RSC_SYS_REG_CFG_HMK_CODE_FR RSC_SYS_REG_CFG_HMK_CODE_EN +#define RSC_SYS_REGS_HWCR_CODE_FR RSC_SYS_REGS_HWCR_CODE_EN +#define RSC_SYS_REG_HWCR_SMM_CODE_FR RSC_SYS_REG_HWCR_SMM_CODE_EN +#define RSC_SYS_REG_HWCR_SLW_CODE_FR RSC_SYS_REG_HWCR_SLW_CODE_EN +#define RSC_SYS_REG_HWCR_TLB_CODE_FR RSC_SYS_REG_HWCR_TLB_CODE_EN +#define RSC_SYS_REG_HWCR_WBI_CODE_FR RSC_SYS_REG_HWCR_WBI_CODE_EN +#define RSC_SYS_REG_HWCR_FF_CODE_FR RSC_SYS_REG_HWCR_FF_CODE_EN +#define RSC_SYS_REG_HWCR_FRR_CODE_FR RSC_SYS_REG_HWCR_FRR_CODE_EN +#define RSC_SYS_REG_HWCR_IG_CODE_FR RSC_SYS_REG_HWCR_IG_CODE_EN +#define RSC_SYS_REG_HWCR_SMW_CODE_FR RSC_SYS_REG_HWCR_SMW_CODE_EN +#define RSC_SYS_REG_HWCR_UMW_CODE_FR RSC_SYS_REG_HWCR_UMW_CODE_EN +#define RSC_SYS_REG_HWCR_HLT_CODE_FR RSC_SYS_REG_HWCR_HLT_CODE_EN +#define RSC_SYS_REG_HWCR_SMI_CODE_FR RSC_SYS_REG_HWCR_SMI_CODE_EN +#define RSC_SYS_REG_HWCR_RSM_CODE_FR RSC_SYS_REG_HWCR_RSM_CODE_EN +#define RSC_SYS_REG_HWCR_SSE_CODE_FR RSC_SYS_REG_HWCR_SSE_CODE_EN +#define RSC_SYS_REG_HWCR_WRP_CODE_FR RSC_SYS_REG_HWCR_WRP_CODE_EN +#define RSC_SYS_REG_HWCR_MC_CODE_FR RSC_SYS_REG_HWCR_MC_CODE_EN +#define RSC_SYS_REG_HWCR_IO_CODE_FR RSC_SYS_REG_HWCR_IO_CODE_EN +#define RSC_SYS_REG_HWCR_P0_CODE_FR RSC_SYS_REG_HWCR_P0_CODE_EN +#define RSC_SYS_REG_HWCR_PRB_CODE_FR RSC_SYS_REG_HWCR_PRB_CODE_EN +#define RSC_SYS_REG_HWCR_INC_CODE_FR RSC_SYS_REG_HWCR_INC_CODE_EN +#define RSC_SYS_REG_HWCR_CPB_CODE_FR RSC_SYS_REG_HWCR_CPB_CODE_EN +#define RSC_SYS_REG_HWCR_HCF_CODE_FR RSC_SYS_REG_HWCR_HCF_CODE_EN +#define RSC_SYS_REG_HWCR_ROC_CODE_FR RSC_SYS_REG_HWCR_ROC_CODE_EN +#define RSC_SYS_REG_HWCR_SMU_CODE_FR RSC_SYS_REG_HWCR_SMU_CODE_EN +#define RSC_SYS_REG_HWCR_CSE_CODE_FR RSC_SYS_REG_HWCR_CSE_CODE_EN +#define RSC_SYS_REG_HWCR_IR_CODE_FR RSC_SYS_REG_HWCR_IR_CODE_EN +#define RSC_SYS_REG_HWCR_SBR_CODE_FR RSC_SYS_REG_HWCR_SBR_CODE_EN +#define RSC_SYS_REG_HWCR_TPR_CODE_FR RSC_SYS_REG_HWCR_TPR_CODE_EN +#define RSC_SYS_REG_HWCR_PG_CODE_FR RSC_SYS_REG_HWCR_PG_CODE_EN +#define RSC_SYS_REG_HWCR_ID_CODE_FR RSC_SYS_REG_HWCR_ID_CODE_EN #define RSC_ISA_TITLE_CODE_FR " Jeu d'instructions ""\xa9""tendu " @@ -580,8 +618,10 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo #define RSC_FEATURES_FZRM_CODE_FR "Fast Zero-length REP MOVSB" #define RSC_FEATURES_ERMS_CODE_FR "Fast-String Operation" #define RSC_FEATURES_FMA_CODE_FR "Fused Multiply Add" +#define RSC_FEATURES_FRED_CODE_FR "Flexible Return and Event Delivery" #define RSC_FEATURES_HFI_CODE_FR "Hardware Feedback Interface" #define RSC_FEATURES_HLE_CODE_FR "Hardware Lock Elision" +#define RSC_FEATURES_HTT_CODE_FR "Hyper-Threading Technology" #define RSC_FEATURES_HwP_CODE_FR "Hardware P-state control" #define RSC_FEATURES_HRESET_CODE_FR "History Reset" #define RSC_FEATURES_HYBRID_CODE_FR "Hybrid part processor" @@ -591,6 +631,7 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo #define RSC_FEATURES_LM_CODE_FR "Long Mode 64 bits" #define RSC_FEATURES_LASS_CODE_FR "Linear Address Space Separation" #define RSC_FEATURES_LAM_CODE_FR "Linear Address Masking" +#define RSC_FEATURES_LKGS_CODE_FR "Load Kernel GS segment register" #define RSC_FEATURES_LWP_CODE_FR "LightWeight Profiling" #define RSC_FEATURES_MBE_CODE_FR "Memory Bandwidth Enforcement" #define RSC_FEATURES_MCA_CODE_FR "Machine-Check Architecture" @@ -644,10 +685,21 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo #define RSC_TECHNOLOGIES_TITLE_CODE_FR " Technologies " #define RSC_TECHNOLOGIES_DCU_CODE_FR "Unit""\xa9"" de cache de donn""\xa9""es" #define RSC_TECHNOLOGIES_ICU_CODE_FR "Unit""\xa9"" de cache d'instructions" +#define RSC_TECHNOLOGIES_PF_CODE_FR "Pr""\xa9""lecteur de Caches" #define RSC_TECH_L1_HW_PREFETCH_CODE_FR "Pr""\xa9""lecteur L1" #define RSC_TECH_L1_HW_IP_PREFETCH_CODE_FR "Pr""\xa9""lecteur L1 IP" +#define RSC_TECH_L1_NPP_PREFETCH_CODE_FR "Pr""\xa9""lecteur L1 page suivante" +#define RSC_TECH_L1_SCRUBBING_CODE_FR "L1 Scrubbing" #define RSC_TECH_L2_HW_PREFETCH_CODE_FR "Pr""\xa9""lecteur L2" -#define RSC_TECH_L2_HW_CL_PREFETCH_CODE_FR "Pr""\xa9""lecteur L2 ligne" +#define RSC_TECH_L2_HW_CL_PREFETCH_CODE_FR "Pr""\xa9""lecteur L2 ligne de cache" +#define RSC_TECH_L2_AMP_PREFETCH_CODE_FR RSC_TECH_L2_AMP_PREFETCH_CODE_EN +#define RSC_TECH_L2_NLP_PREFETCH_CODE_FR "Pr""\xa9""lecteur L2 ligne suivante" +#define RSC_TECH_L1_STRIDE_PF_CODE_FR "Pr""\xa9""lecteur L1 Stride" +#define RSC_TECH_L1_REGION_PF_CODE_FR "Pr""\xa9""lecteur L1 Region" +#define RSC_TECH_L1_BURST_PF_CODE_FR "Pr""\xa9""lecteur L1 Burst" +#define RSC_TECH_L2_STREAM_HW_PF_CODE_FR "Pr""\xa9""lecteur HW L2 Stream" +#define RSC_TECH_L2_UPDOWN_PF_CODE_FR "Pr""\xa9""lecteur L2 Up/Down" +#define RSC_TECH_LLC_STREAMER_CODE_FR RSC_TECH_LLC_STREAMER_CODE_EN #define RSC_TECHNOLOGIES_SMM_CODE_FR "Mode de Gestion Syst""\xa8""me" #define RSC_TECHNOLOGIES_HTT_CODE_FR "Hyper-Threading" #define RSC_TECHNOLOGIES_EIST_CODE_FR "SpeedStep" @@ -717,6 +769,8 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo #define RSC_PERF_MON_MONITOR_MWAIT_CODE_FR "MONITOR/MWAIT" #define RSC_PERF_MON_MWAIT_IDX_CSTATE_CODE_FR "State index" #define RSC_PERF_MON_MWAIT_SUB_CSTATE_CODE_FR "Sub C-State" +#define RSC_PERF_MON_MWAIT_EMX_MWAIT_CODE_FR "Monitor-Mwait Extensions" +#define RSC_PERF_MON_MWAIT_IBE_MWAIT_CODE_FR "Interrupt Break-Event" #define RSC_PERF_MON_CORE_CYCLE_CODE_FR "Core Cycles" #define RSC_PERF_MON_INST_RET_CODE_FR "Instructions Retired" @@ -1379,7 +1433,7 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo #define RSC_ERROR_CMD_SYNTAX_CODE_FR \ "CoreFreq." \ - " Copyright (C) 2015-2023 CYRIL COURTIAT\n\n" \ + " Copyright (C) 2015-2024 CYRIL COURTIAT\n\n" \ "Usage:\t%s [-Option ] [-Commande ]\n"\ "\n Options de l'interface\n" \ "\t-Oa\tFréquence absolue\n" \ @@ -1473,6 +1527,7 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo #define RSC_MECH_SPLA_CODE_FR RSC_MECH_SPLA_CODE_EN #define RSC_MECH_SNOOP_FILTER_CODE_FR RSC_MECH_SNOOP_FILTER_CODE_EN #define RSC_MECH_PSFD_CODE_FR RSC_MECH_PSFD_CODE_EN +#define RSC_MECH_EPSF_CODE_FR RSC_MECH_EPSF_CODE_EN #define RSC_MECH_IBRS_ALWAYS_ON_CODE_FR RSC_MECH_IBRS_ALWAYS_ON_CODE_EN #define RSC_MECH_IBRS_PREFERRED_CODE_FR RSC_MECH_IBRS_PREFERRED_CODE_EN #define RSC_MECH_IBRS_SAME_MODE_CODE_FR RSC_MECH_IBRS_SAME_MODE_CODE_EN @@ -1500,9 +1555,18 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo #define RSC_MECH_MCDT_NO_CODE_FR RSC_MECH_MCDT_NO_CODE_EN #define RSC_MECH_BTC_NO_CODE_FR RSC_MECH_BTC_NO_CODE_EN #define RSC_MECH_BTC_NOBR_CODE_FR RSC_MECH_BTC_NOBR_CODE_EN +#define RSC_MECH_XPROC_LEAK_CODE_FR RSC_MECH_XPROC_LEAK_CODE_EN +#define RSC_MECH_AGENPICK_CODE_FR RSC_MECH_AGENPICK_CODE_EN +#define RSC_MECH_OVERCLOCKING_CODE_FR RSC_MECH_OVERCLOCKING_CODE_EN +#define RSC_MECH_OC_UTILIZED_CODE_FR RSC_MECH_OC_UTILIZED_CODE_EN +#define RSC_MECH_OC_UNDERVOLT_CODE_FR RSC_MECH_OC_UNDERVOLT_CODE_EN +#define RSC_MECH_OC_UNLOCKED_CODE_FR RSC_MECH_OC_UNLOCKED_CODE_EN #define RSC_SECURITY_CPUID_KL_CODE_FR RSC_SECURITY_CPUID_KL_CODE_EN #define RSC_SECURITY_AESKLE_CODE_FR RSC_SECURITY_AESKLE_CODE_EN +#define RSC_SECURITY_CET_SS_CODE_FR RSC_SECURITY_CET_SS_CODE_EN +#define RSC_SECURITY_CET_IBT_CODE_FR RSC_SECURITY_CET_IBT_CODE_EN +#define RSC_SECURITY_CET_SSS_CODE_FR RSC_SECURITY_CET_SSS_CODE_EN #define RSC_SECURITY_WIDE_KL_CODE_FR RSC_SECURITY_WIDE_KL_CODE_EN #define RSC_SECURITY_SGX1_CODE_FR RSC_SECURITY_SGX1_CODE_EN #define RSC_SECURITY_SGX2_CODE_FR RSC_SECURITY_SGX2_CODE_EN diff --git a/corefreq-cli-rsc-theme-dflt.h b/x86_64/corefreq-cli-rsc-theme-dflt.h similarity index 99% rename from corefreq-cli-rsc-theme-dflt.h rename to x86_64/corefreq-cli-rsc-theme-dflt.h index bea328a7..48c98584 100644 --- a/corefreq-cli-rsc-theme-dflt.h +++ b/x86_64/corefreq-cli-rsc-theme-dflt.h @@ -1,6 +1,6 @@ /* * CoreFreq - * Copyright (C) 2015-2023 CYRIL COURTIAT + * Copyright (C) 2015-2024 CYRIL COURTIAT * Licenses: GPL2 */ diff --git a/corefreq-cli-rsc-theme-usr1.h b/x86_64/corefreq-cli-rsc-theme-usr1.h similarity index 99% rename from corefreq-cli-rsc-theme-usr1.h rename to x86_64/corefreq-cli-rsc-theme-usr1.h index 223eeaf0..106062c4 100644 --- a/corefreq-cli-rsc-theme-usr1.h +++ b/x86_64/corefreq-cli-rsc-theme-usr1.h @@ -1,6 +1,6 @@ /* * CoreFreq - * Copyright (C) 2015-2023 CYRIL COURTIAT + * Copyright (C) 2015-2024 CYRIL COURTIAT * Licenses: GPL2 */ diff --git a/corefreq-cli-rsc-theme-usr2.h b/x86_64/corefreq-cli-rsc-theme-usr2.h similarity index 99% rename from corefreq-cli-rsc-theme-usr2.h rename to x86_64/corefreq-cli-rsc-theme-usr2.h index 6f889431..426c7498 100644 --- a/corefreq-cli-rsc-theme-usr2.h +++ b/x86_64/corefreq-cli-rsc-theme-usr2.h @@ -1,6 +1,6 @@ /* * CoreFreq - * Copyright (C) 2015-2023 CYRIL COURTIAT + * Copyright (C) 2015-2024 CYRIL COURTIAT * Licenses: GPL2 */ diff --git a/corefreq-cli-rsc.c b/x86_64/corefreq-cli-rsc.c similarity index 94% rename from corefreq-cli-rsc.c rename to x86_64/corefreq-cli-rsc.c index 3fb43144..9eb95a27 100644 --- a/corefreq-cli-rsc.c +++ b/x86_64/corefreq-cli-rsc.c @@ -1,6 +1,6 @@ /* * CoreFreq - * Copyright (C) 2015-2023 CYRIL COURTIAT + * Copyright (C) 2015-2024 CYRIL COURTIAT * Licenses: GPL2 */ @@ -601,8 +601,13 @@ RESOURCE_ST Resource[] = { LDQ(RSC_SYS_REGS_NA), LDQ(RSC_SYS_REGS_HDR_CPU), LDQ(RSC_SYS_REG_HDR_FLAGS), + LDQ(RSC_SYS_REG_HDR_CF), + LDQ(RSC_SYS_REG_HDR_ZF), + LDQ(RSC_SYS_REG_HDR_SF), LDQ(RSC_SYS_REG_HDR_TF), LDQ(RSC_SYS_REG_HDR_IF), + LDQ(RSC_SYS_REG_HDR_DF), + LDQ(RSC_SYS_REG_HDR_OF), LDQ(RSC_SYS_REG_HDR_IOPL), LDQ(RSC_SYS_REG_HDR_NT), LDQ(RSC_SYS_REG_HDR_RF), @@ -611,8 +616,13 @@ RESOURCE_ST Resource[] = { LDQ(RSC_SYS_REG_HDR_VIF), LDQ(RSC_SYS_REG_HDR_VIP), LDQ(RSC_SYS_REG_HDR_ID), + LDT(RSC_SYS_REG_FLAGS_CF), + LDT(RSC_SYS_REG_FLAGS_ZF), + LDT(RSC_SYS_REG_FLAGS_SF), LDT(RSC_SYS_REG_FLAGS_TF), LDT(RSC_SYS_REG_FLAGS_IF), + LDT(RSC_SYS_REG_FLAGS_DF), + LDT(RSC_SYS_REG_FLAGS_OF), LDT(RSC_SYS_REG_FLAGS_IOPL), LDT(RSC_SYS_REG_FLAGS_NT), LDT(RSC_SYS_REG_FLAGS_RF), @@ -682,6 +692,7 @@ RESOURCE_ST Resource[] = { LDQ(RSC_SYS_REG_HDR_CR4_PKS), LDQ(RSC_SYS_REG_HDR_CR4_UINTR), LDQ(RSC_SYS_REG_HDR_CR4_LAM), + LDQ(RSC_SYS_REG_HDR_CR4_FRED), LDT(RSC_SYS_REGS_CR4), LDT(RSC_SYS_REG_CR4_VME), LDT(RSC_SYS_REG_CR4_PVI), @@ -709,6 +720,7 @@ RESOURCE_ST Resource[] = { LDT(RSC_SYS_REG_CR4_PKS), LDT(RSC_SYS_REG_CR4_UINTR), LDT(RSC_SYS_REG_CR4_LAM), + LDT(RSC_SYS_REG_CR4_FRED), LDQ(RSC_SYS_REG_HDR_CR8), LDQ(RSC_SYS_REG_HDR_CR8_TPL), LDT(RSC_SYS_REGS_CR8), @@ -766,6 +778,8 @@ RESOURCE_ST Resource[] = { LDQ(RSC_SYS_REG_HDR_XCR0_MPK), LDQ(RSC_SYS_REG_HDR_XCR0_CEU), LDQ(RSC_SYS_REG_HDR_XCR0_CES), + LDQ(RSC_SYS_REG_HDR_XCR0_AMX), + LDQ(RSC_SYS_REG_HDR_XCR0_APX), LDQ(RSC_SYS_REG_HDR_XCR0_LWP), LDT(RSC_SYS_REGS_XCR0), LDT(RSC_SYS_REG_XCR0_FPU), @@ -776,6 +790,8 @@ RESOURCE_ST Resource[] = { LDT(RSC_SYS_REG_XCR0_MPK), LDT(RSC_SYS_REG_XCR0_CEU), LDT(RSC_SYS_REG_XCR0_CES), + LDT(RSC_SYS_REG_XCR0_AMX), + LDT(RSC_SYS_REG_XCR0_APX), LDT(RSC_SYS_REG_XCR0_LWP), LDQ(RSC_SYS_REG_HDR_CFG), LDQ(RSC_SYS_REG_HDR_CFG_MFD), @@ -797,6 +813,66 @@ RESOURCE_ST Resource[] = { LDT(RSC_SYS_REG_CFG_SNP), LDT(RSC_SYS_REG_CFG_VMPL), LDT(RSC_SYS_REG_CFG_HMK), + LDQ(RSC_SYS_REG_HDR_HWCR), + LDQ(RSC_SYS_REG_HDR_HWCR_SMM), + LDQ(RSC_SYS_REG_HDR_HWCR_SLW), + LDQ(RSC_SYS_REG_HDR_HWCR_TLB), + LDQ(RSC_SYS_REG_HDR_HWCR_WBI), + LDQ(RSC_SYS_REG_HDR_HWCR_FF), + LDQ(RSC_SYS_REG_HDR_HWCR_FRR), + LDQ(RSC_SYS_REG_HDR_HWCR_IG), + LDQ(RSC_SYS_REG_HDR_HWCR_SMW), + LDQ(RSC_SYS_REG_HDR_HWCR_UMW), + LDQ(RSC_SYS_REG_HDR_HWCR_HLT), + LDQ(RSC_SYS_REG_HDR_HWCR_SMI), + LDQ(RSC_SYS_REG_HDR_HWCR_RSM), + LDQ(RSC_SYS_REG_HDR_HWCR_SSE), + LDQ(RSC_SYS_REG_HDR_HWCR_WRP), + LDQ(RSC_SYS_REG_HDR_HWCR_MC), + LDQ(RSC_SYS_REG_HDR_HWCR_IO), + LDQ(RSC_SYS_REG_HDR_HWCR_P0), + LDQ(RSC_SYS_REG_HDR_HWCR_PRB), + LDQ(RSC_SYS_REG_HDR_HWCR_INC), + LDQ(RSC_SYS_REG_HDR_HWCR_CPB), + LDQ(RSC_SYS_REG_HDR_HWCR_HCF), + LDQ(RSC_SYS_REG_HDR_HWCR_ROC), + LDQ(RSC_SYS_REG_HDR_HWCR_SMU), + LDQ(RSC_SYS_REG_HDR_HWCR_CSE), + LDQ(RSC_SYS_REG_HDR_HWCR_IR), + LDQ(RSC_SYS_REG_HDR_HWCR_SBR), + LDQ(RSC_SYS_REG_HDR_HWCR_TPR), + LDQ(RSC_SYS_REG_HDR_HWCR_PG), + LDQ(RSC_SYS_REG_HDR_HWCR_ID), + LDT(RSC_SYS_REGS_HWCR), + LDT(RSC_SYS_REG_HWCR_SMM), + LDT(RSC_SYS_REG_HWCR_SLW), + LDT(RSC_SYS_REG_HWCR_TLB), + LDT(RSC_SYS_REG_HWCR_WBI), + LDT(RSC_SYS_REG_HWCR_FF), + LDT(RSC_SYS_REG_HWCR_FRR), + LDT(RSC_SYS_REG_HWCR_IG), + LDT(RSC_SYS_REG_HWCR_SMW), + LDT(RSC_SYS_REG_HWCR_UMW), + LDT(RSC_SYS_REG_HWCR_HLT), + LDT(RSC_SYS_REG_HWCR_SMI), + LDT(RSC_SYS_REG_HWCR_RSM), + LDT(RSC_SYS_REG_HWCR_SSE), + LDT(RSC_SYS_REG_HWCR_WRP), + LDT(RSC_SYS_REG_HWCR_MC), + LDT(RSC_SYS_REG_HWCR_IO), + LDT(RSC_SYS_REG_HWCR_P0), + LDT(RSC_SYS_REG_HWCR_PRB), + LDT(RSC_SYS_REG_HWCR_INC), + LDT(RSC_SYS_REG_HWCR_CPB), + LDT(RSC_SYS_REG_HWCR_HCF), + LDT(RSC_SYS_REG_HWCR_ROC), + LDT(RSC_SYS_REG_HWCR_SMU), + LDT(RSC_SYS_REG_HWCR_CSE), + LDT(RSC_SYS_REG_HWCR_IR), + LDT(RSC_SYS_REG_HWCR_SBR), + LDT(RSC_SYS_REG_HWCR_TPR), + LDT(RSC_SYS_REG_HWCR_PG), + LDT(RSC_SYS_REG_HWCR_ID), LDT(RSC_ISA_TITLE), LDQ(RSC_ISA_3DNOW), LDT(RSC_ISA_3DNOW_COMM), @@ -960,8 +1036,10 @@ RESOURCE_ST Resource[] = { LDT(RSC_FEATURES_FZRM), LDT(RSC_FEATURES_ERMS), LDT(RSC_FEATURES_FMA), + LDT(RSC_FEATURES_FRED), LDT(RSC_FEATURES_HFI), LDT(RSC_FEATURES_HLE), + LDT(RSC_FEATURES_HTT), LDT(RSC_FEATURES_HwP), LDT(RSC_FEATURES_HRESET), LDT(RSC_FEATURES_HYBRID), @@ -971,6 +1049,7 @@ RESOURCE_ST Resource[] = { LDT(RSC_FEATURES_LM), LDT(RSC_FEATURES_LASS), LDT(RSC_FEATURES_LAM), + LDT(RSC_FEATURES_LKGS), LDT(RSC_FEATURES_LWP), LDT(RSC_FEATURES_MBE), LDT(RSC_FEATURES_MCA), @@ -1023,10 +1102,21 @@ RESOURCE_ST Resource[] = { LDT(RSC_TECHNOLOGIES_TITLE), LDT(RSC_TECHNOLOGIES_DCU), LDT(RSC_TECHNOLOGIES_ICU), + LDT(RSC_TECHNOLOGIES_PF), LDT(RSC_TECH_L1_HW_PREFETCH), LDT(RSC_TECH_L1_HW_IP_PREFETCH), + LDT(RSC_TECH_L1_NPP_PREFETCH), + LDT(RSC_TECH_L1_SCRUBBING), LDT(RSC_TECH_L2_HW_PREFETCH), LDT(RSC_TECH_L2_HW_CL_PREFETCH), + LDT(RSC_TECH_L2_AMP_PREFETCH), + LDT(RSC_TECH_L2_NLP_PREFETCH), + LDT(RSC_TECH_L1_STRIDE_PF), + LDT(RSC_TECH_L1_REGION_PF), + LDT(RSC_TECH_L1_BURST_PF), + LDT(RSC_TECH_L2_STREAM_HW_PF), + LDT(RSC_TECH_L2_UPDOWN_PF), + LDT(RSC_TECH_LLC_STREAMER), LDT(RSC_TECHNOLOGIES_SMM), LDT(RSC_TECH_INTEL_SMM_COMM), LDT(RSC_TECH_AMD_SMM_COMM), @@ -1099,6 +1189,8 @@ RESOURCE_ST Resource[] = { LDT(RSC_PERF_MON_MONITOR_MWAIT), LDT(RSC_PERF_MON_MWAIT_IDX_CSTATE), LDT(RSC_PERF_MON_MWAIT_SUB_CSTATE), + LDT(RSC_PERF_MON_MWAIT_EMX_MWAIT), + LDT(RSC_PERF_MON_MWAIT_IBE_MWAIT), LDT(RSC_PERF_MON_CORE_CYCLE), LDT(RSC_PERF_MON_INST_RET), LDT(RSC_PERF_MON_REF_CYCLE), @@ -1131,6 +1223,8 @@ RESOURCE_ST Resource[] = { LDQ(RSC_PERF_LABEL_PPC), LDQ(RSC_PERF_LABEL_CPC), LDQ(RSC_PERF_LABEL_CST), + LDQ(RSC_PERF_LABEL_EMX), + LDQ(RSC_PERF_LABEL_IBE), LDQ(RSC_PERF_LABEL_HWP), LDQ(RSC_PERF_LABEL_HDC), LDQ(RSC_PERF_LABEL_CFG_CTRL), @@ -1688,8 +1782,18 @@ RESOURCE_ST Resource[] = { LDT(RSC_BOX_MODE_DESC), LDQ(RSC_BOX_CU_L1_TITLE), LDQ(RSC_BOX_CU_L1_IP_TITLE), + LDQ(RSC_BOX_CU_L1_NPP_TITLE), + LDQ(RSC_BOX_L1_SCRUBBING_TITLE), LDQ(RSC_BOX_CU_L2_TITLE), LDQ(RSC_BOX_CU_L2_CL_TITLE), + LDQ(RSC_BOX_L2_AMP_TITLE), + LDQ(RSC_BOX_CU_L2_NLP_TITLE), + LDQ(RSC_BOX_L1_STRIDE_TITLE), + LDQ(RSC_BOX_L1_REGION_TITLE), + LDQ(RSC_BOX_L1_BURST_TITLE), + LDQ(RSC_BOX_L2_STREAM_HW_TITLE), + LDQ(RSC_BOX_L2_UPDOWN_TITLE), + LDQ(RSC_BOX_LLC_STREAMER_TITLE), LDQ(RSC_BOX_EIST_TITLE), LDT(RSC_BOX_EIST_DESC), LDQ(RSC_BOX_C1E_TITLE), @@ -1948,6 +2052,7 @@ RESOURCE_ST Resource[] = { LDT(RSC_MECH_SPLA), LDT(RSC_MECH_SNOOP_FILTER), LDT(RSC_MECH_PSFD), + LDT(RSC_MECH_EPSF), LDT(RSC_MECH_IBRS_ALWAYS_ON), LDT(RSC_MECH_IBRS_PREFERRED), LDT(RSC_MECH_IBRS_SAME_MODE), @@ -1975,8 +2080,17 @@ RESOURCE_ST Resource[] = { LDT(RSC_MECH_MCDT_NO), LDT(RSC_MECH_BTC_NO), LDT(RSC_MECH_BTC_NOBR), + LDT(RSC_MECH_XPROC_LEAK), + LDT(RSC_MECH_AGENPICK), + LDT(RSC_MECH_OVERCLOCKING), + LDT(RSC_MECH_OC_UTILIZED), + LDT(RSC_MECH_OC_UNDERVOLT), + LDT(RSC_MECH_OC_UNLOCKED), LDT(RSC_SECURITY_CPUID_KL), LDT(RSC_SECURITY_AESKLE), + LDT(RSC_SECURITY_CET_SS), + LDT(RSC_SECURITY_CET_IBT), + LDT(RSC_SECURITY_CET_SSS), LDT(RSC_SECURITY_WIDE_KL), LDT(RSC_SECURITY_SGX1), LDT(RSC_SECURITY_SGX2), diff --git a/corefreq-cli-rsc.h b/x86_64/corefreq-cli-rsc.h similarity index 93% rename from corefreq-cli-rsc.h rename to x86_64/corefreq-cli-rsc.h index e91e67c6..f3fb00a2 100644 --- a/corefreq-cli-rsc.h +++ b/x86_64/corefreq-cli-rsc.h @@ -1,6 +1,6 @@ /* * CoreFreq - * Copyright (C) 2015-2023 CYRIL COURTIAT + * Copyright (C) 2015-2024 CYRIL COURTIAT * Licenses: GPL2 */ @@ -404,8 +404,13 @@ enum { RSC_SYS_REGS_NA, RSC_SYS_REGS_HDR_CPU, RSC_SYS_REG_HDR_FLAGS, + RSC_SYS_REG_HDR_CF, + RSC_SYS_REG_HDR_ZF, + RSC_SYS_REG_HDR_SF, RSC_SYS_REG_HDR_TF, RSC_SYS_REG_HDR_IF, + RSC_SYS_REG_HDR_DF, + RSC_SYS_REG_HDR_OF, RSC_SYS_REG_HDR_IOPL, RSC_SYS_REG_HDR_NT, RSC_SYS_REG_HDR_RF, @@ -414,8 +419,13 @@ enum { RSC_SYS_REG_HDR_VIF, RSC_SYS_REG_HDR_VIP, RSC_SYS_REG_HDR_ID, + RSC_SYS_REG_FLAGS_CF, + RSC_SYS_REG_FLAGS_ZF, + RSC_SYS_REG_FLAGS_SF, RSC_SYS_REG_FLAGS_TF, RSC_SYS_REG_FLAGS_IF, + RSC_SYS_REG_FLAGS_DF, + RSC_SYS_REG_FLAGS_OF, RSC_SYS_REG_FLAGS_IOPL, RSC_SYS_REG_FLAGS_NT, RSC_SYS_REG_FLAGS_RF, @@ -485,6 +495,7 @@ enum { RSC_SYS_REG_HDR_CR4_PKS, RSC_SYS_REG_HDR_CR4_UINTR, RSC_SYS_REG_HDR_CR4_LAM, + RSC_SYS_REG_HDR_CR4_FRED, RSC_SYS_REGS_CR4, RSC_SYS_REG_CR4_VME, RSC_SYS_REG_CR4_PVI, @@ -512,6 +523,7 @@ enum { RSC_SYS_REG_CR4_PKS, RSC_SYS_REG_CR4_UINTR, RSC_SYS_REG_CR4_LAM, + RSC_SYS_REG_CR4_FRED, RSC_SYS_REG_HDR_CR8, RSC_SYS_REG_HDR_CR8_TPL, RSC_SYS_REGS_CR8, @@ -569,6 +581,8 @@ enum { RSC_SYS_REG_HDR_XCR0_MPK, RSC_SYS_REG_HDR_XCR0_CEU, RSC_SYS_REG_HDR_XCR0_CES, + RSC_SYS_REG_HDR_XCR0_AMX, + RSC_SYS_REG_HDR_XCR0_APX, RSC_SYS_REG_HDR_XCR0_LWP, RSC_SYS_REGS_XCR0, RSC_SYS_REG_XCR0_FPU, @@ -579,6 +593,8 @@ enum { RSC_SYS_REG_XCR0_MPK, RSC_SYS_REG_XCR0_CEU, RSC_SYS_REG_XCR0_CES, + RSC_SYS_REG_XCR0_AMX, + RSC_SYS_REG_XCR0_APX, RSC_SYS_REG_XCR0_LWP, RSC_SYS_REG_HDR_CFG, RSC_SYS_REG_HDR_CFG_MFD, @@ -600,6 +616,66 @@ enum { RSC_SYS_REG_CFG_SNP, RSC_SYS_REG_CFG_VMPL, RSC_SYS_REG_CFG_HMK, + RSC_SYS_REG_HDR_HWCR, + RSC_SYS_REG_HDR_HWCR_SMM, + RSC_SYS_REG_HDR_HWCR_SLW, + RSC_SYS_REG_HDR_HWCR_TLB, + RSC_SYS_REG_HDR_HWCR_WBI, + RSC_SYS_REG_HDR_HWCR_FF, + RSC_SYS_REG_HDR_HWCR_FRR, + RSC_SYS_REG_HDR_HWCR_IG, + RSC_SYS_REG_HDR_HWCR_SMW, + RSC_SYS_REG_HDR_HWCR_UMW, + RSC_SYS_REG_HDR_HWCR_HLT, + RSC_SYS_REG_HDR_HWCR_SMI, + RSC_SYS_REG_HDR_HWCR_RSM, + RSC_SYS_REG_HDR_HWCR_SSE, + RSC_SYS_REG_HDR_HWCR_WRP, + RSC_SYS_REG_HDR_HWCR_MC, + RSC_SYS_REG_HDR_HWCR_IO, + RSC_SYS_REG_HDR_HWCR_P0, + RSC_SYS_REG_HDR_HWCR_PRB, + RSC_SYS_REG_HDR_HWCR_INC, + RSC_SYS_REG_HDR_HWCR_CPB, + RSC_SYS_REG_HDR_HWCR_HCF, + RSC_SYS_REG_HDR_HWCR_ROC, + RSC_SYS_REG_HDR_HWCR_SMU, + RSC_SYS_REG_HDR_HWCR_CSE, + RSC_SYS_REG_HDR_HWCR_IR, + RSC_SYS_REG_HDR_HWCR_SBR, + RSC_SYS_REG_HDR_HWCR_TPR, + RSC_SYS_REG_HDR_HWCR_PG, + RSC_SYS_REG_HDR_HWCR_ID, + RSC_SYS_REGS_HWCR, + RSC_SYS_REG_HWCR_SMM, + RSC_SYS_REG_HWCR_SLW, + RSC_SYS_REG_HWCR_TLB, + RSC_SYS_REG_HWCR_WBI, + RSC_SYS_REG_HWCR_FF, + RSC_SYS_REG_HWCR_FRR, + RSC_SYS_REG_HWCR_IG, + RSC_SYS_REG_HWCR_SMW, + RSC_SYS_REG_HWCR_UMW, + RSC_SYS_REG_HWCR_HLT, + RSC_SYS_REG_HWCR_SMI, + RSC_SYS_REG_HWCR_RSM, + RSC_SYS_REG_HWCR_SSE, + RSC_SYS_REG_HWCR_WRP, + RSC_SYS_REG_HWCR_MC, + RSC_SYS_REG_HWCR_IO, + RSC_SYS_REG_HWCR_P0, + RSC_SYS_REG_HWCR_PRB, + RSC_SYS_REG_HWCR_INC, + RSC_SYS_REG_HWCR_CPB, + RSC_SYS_REG_HWCR_HCF, + RSC_SYS_REG_HWCR_ROC, + RSC_SYS_REG_HWCR_SMU, + RSC_SYS_REG_HWCR_CSE, + RSC_SYS_REG_HWCR_IR, + RSC_SYS_REG_HWCR_SBR, + RSC_SYS_REG_HWCR_TPR, + RSC_SYS_REG_HWCR_PG, + RSC_SYS_REG_HWCR_ID, RSC_ISA_TITLE, RSC_ISA_3DNOW, RSC_ISA_3DNOW_COMM, @@ -763,8 +839,10 @@ enum { RSC_FEATURES_FZRM, RSC_FEATURES_ERMS, RSC_FEATURES_FMA, + RSC_FEATURES_FRED, RSC_FEATURES_HFI, RSC_FEATURES_HLE, + RSC_FEATURES_HTT, RSC_FEATURES_HwP, RSC_FEATURES_HRESET, RSC_FEATURES_HYBRID, @@ -774,6 +852,7 @@ enum { RSC_FEATURES_LM, RSC_FEATURES_LASS, RSC_FEATURES_LAM, + RSC_FEATURES_LKGS, RSC_FEATURES_LWP, RSC_FEATURES_MBE, RSC_FEATURES_MCA, @@ -826,10 +905,21 @@ enum { RSC_TECHNOLOGIES_TITLE, RSC_TECHNOLOGIES_DCU, RSC_TECHNOLOGIES_ICU, + RSC_TECHNOLOGIES_PF, RSC_TECH_L1_HW_PREFETCH, RSC_TECH_L1_HW_IP_PREFETCH, + RSC_TECH_L1_NPP_PREFETCH, + RSC_TECH_L1_SCRUBBING, RSC_TECH_L2_HW_PREFETCH, RSC_TECH_L2_HW_CL_PREFETCH, + RSC_TECH_L2_AMP_PREFETCH, + RSC_TECH_L2_NLP_PREFETCH, + RSC_TECH_L1_STRIDE_PF, + RSC_TECH_L1_REGION_PF, + RSC_TECH_L1_BURST_PF, + RSC_TECH_L2_STREAM_HW_PF, + RSC_TECH_L2_UPDOWN_PF, + RSC_TECH_LLC_STREAMER, RSC_TECHNOLOGIES_SMM, RSC_TECH_INTEL_SMM_COMM, RSC_TECH_AMD_SMM_COMM, @@ -902,6 +992,8 @@ enum { RSC_PERF_MON_MONITOR_MWAIT, RSC_PERF_MON_MWAIT_IDX_CSTATE, RSC_PERF_MON_MWAIT_SUB_CSTATE, + RSC_PERF_MON_MWAIT_EMX_MWAIT, + RSC_PERF_MON_MWAIT_IBE_MWAIT, RSC_PERF_MON_CORE_CYCLE, RSC_PERF_MON_INST_RET, RSC_PERF_MON_REF_CYCLE, @@ -934,6 +1026,8 @@ enum { RSC_PERF_LABEL_PPC, RSC_PERF_LABEL_CPC, RSC_PERF_LABEL_CST, + RSC_PERF_LABEL_EMX, + RSC_PERF_LABEL_IBE, RSC_PERF_LABEL_HWP, RSC_PERF_LABEL_HDC, RSC_PERF_LABEL_CFG_CTRL, @@ -1491,8 +1585,18 @@ enum { RSC_BOX_MODE_DESC, RSC_BOX_CU_L1_TITLE, RSC_BOX_CU_L1_IP_TITLE, + RSC_BOX_CU_L1_NPP_TITLE, + RSC_BOX_L1_SCRUBBING_TITLE, RSC_BOX_CU_L2_TITLE, RSC_BOX_CU_L2_CL_TITLE, + RSC_BOX_L2_AMP_TITLE, + RSC_BOX_CU_L2_NLP_TITLE, + RSC_BOX_L1_STRIDE_TITLE, + RSC_BOX_L1_REGION_TITLE, + RSC_BOX_L1_BURST_TITLE, + RSC_BOX_L2_STREAM_HW_TITLE, + RSC_BOX_L2_UPDOWN_TITLE, + RSC_BOX_LLC_STREAMER_TITLE, RSC_BOX_EIST_TITLE, RSC_BOX_EIST_DESC, RSC_BOX_C1E_TITLE, @@ -1751,6 +1855,7 @@ enum { RSC_MECH_SPLA, RSC_MECH_SNOOP_FILTER, RSC_MECH_PSFD, + RSC_MECH_EPSF, RSC_MECH_IBRS_ALWAYS_ON, RSC_MECH_IBRS_PREFERRED, RSC_MECH_IBRS_SAME_MODE, @@ -1778,8 +1883,17 @@ enum { RSC_MECH_MCDT_NO, RSC_MECH_BTC_NO, RSC_MECH_BTC_NOBR, + RSC_MECH_XPROC_LEAK, + RSC_MECH_AGENPICK, + RSC_MECH_OVERCLOCKING, + RSC_MECH_OC_UTILIZED, + RSC_MECH_OC_UNDERVOLT, + RSC_MECH_OC_UNLOCKED, RSC_SECURITY_CPUID_KL, RSC_SECURITY_AESKLE, + RSC_SECURITY_CET_SS, + RSC_SECURITY_CET_IBT, + RSC_SECURITY_CET_SSS, RSC_SECURITY_WIDE_KL, RSC_SECURITY_SGX1, RSC_SECURITY_SGX2, diff --git a/corefreq-cli.c b/x86_64/corefreq-cli.c similarity index 95% rename from corefreq-cli.c rename to x86_64/corefreq-cli.c index a1710bd1..626b0906 100644 --- a/corefreq-cli.c +++ b/x86_64/corefreq-cli.c @@ -1,6 +1,6 @@ /* * CoreFreq - * Copyright (C) 2015-2023 CYRIL COURTIAT + * Copyright (C) 2015-2024 CYRIL COURTIAT * Licenses: GPL2 */ @@ -265,7 +265,7 @@ ATTRIBUTE *StateToSymbol(short int state, char stateStr[]) } else { stateStr[jdx++] = '?'; } - } while (BITBSR(state, idx) == 0); + } while ((BITBSR(state, idx) == 0) && (jdx < TASK_COMM_LEN)); stateStr[jdx] = '\0'; return stateAttr; } @@ -501,7 +501,8 @@ REASON_CODE SystemRegisters( Window *win, enum AUTOMAT { DO_END, DO_SPC, DO_CPU, DO_FLAG, DO_CR0, DO_CR3, DO_CR4, DO_CR8, - DO_EFCR, DO_EFER, DO_XCR0, DO_CFG + DO_EFCR, DO_EFER, DO_XCR0, DO_CFG, + DO_HWCR }; const unsigned int fIntel = RO(Shm)->Proc.Features.Info.Vendor.CRC == CRC_INTEL, @@ -524,41 +525,41 @@ REASON_CODE SystemRegisters( Window *win, .header = (struct SR_HDR[]) { [ 0] = {RSC(SYS_REGS_HDR_CPU).CODE(), NULL}, [ 1] = {RSC(SYS_REG_HDR_FLAGS).CODE(), NULL}, - [ 2] = {RSC(SYS_REG_HDR_TF).CODE(), RSC(SYS_REG_FLAGS_TF).CODE()}, - [ 3] = {RSC(SYS_REG_HDR_IF).CODE(), RSC(SYS_REG_FLAGS_IF).CODE()}, - [ 4] = {RSC(SYS_REG_HDR_IOPL).CODE(), RSC(SYS_REG_FLAGS_IOPL).CODE()}, - [ 5] = {RSC(SYS_REG_HDR_NT).CODE(), RSC(SYS_REG_FLAGS_NT).CODE()}, - [ 6] = {RSC(SYS_REG_HDR_RF).CODE(), RSC(SYS_REG_FLAGS_RF).CODE()}, - [ 7] = {RSC(SYS_REG_HDR_VM).CODE(), RSC(SYS_REG_FLAGS_VM).CODE()}, - [ 8] = {RSC(SYS_REG_HDR_AC).CODE(), RSC(SYS_REG_FLAGS_AC).CODE()}, - [ 9] = {RSC(SYS_REG_HDR_VIF).CODE(), RSC(SYS_REG_FLAGS_VIF).CODE()}, - [10] = {RSC(SYS_REG_HDR_VIP).CODE(), RSC(SYS_REG_FLAGS_VIP).CODE()}, - [11] = {RSC(SYS_REG_HDR_ID).CODE(), RSC(SYS_REG_FLAGS_ID).CODE()}, - [12] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, - [13] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, - [14] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, - [15] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, - [16] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + [ 2] = {RSC(SYS_REG_HDR_CF).CODE(), RSC(SYS_REG_FLAGS_CF).CODE()}, + [ 3] = {RSC(SYS_REG_HDR_ZF).CODE(), RSC(SYS_REG_FLAGS_ZF).CODE()}, + [ 4] = {RSC(SYS_REG_HDR_SF).CODE(), RSC(SYS_REG_FLAGS_SF).CODE()}, + [ 5] = {RSC(SYS_REG_HDR_TF).CODE(), RSC(SYS_REG_FLAGS_TF).CODE()}, + [ 6] = {RSC(SYS_REG_HDR_IF).CODE(), RSC(SYS_REG_FLAGS_IF).CODE()}, + [ 7] = {RSC(SYS_REG_HDR_DF).CODE(), RSC(SYS_REG_FLAGS_DF).CODE()}, + [ 8] = {RSC(SYS_REG_HDR_OF).CODE(), RSC(SYS_REG_FLAGS_OF).CODE()}, + [ 9] = {RSC(SYS_REG_HDR_IOPL).CODE(), RSC(SYS_REG_FLAGS_IOPL).CODE()}, + [10] = {RSC(SYS_REG_HDR_NT).CODE(), RSC(SYS_REG_FLAGS_NT).CODE()}, + [11] = {RSC(SYS_REG_HDR_RF).CODE(), RSC(SYS_REG_FLAGS_RF).CODE()}, + [12] = {RSC(SYS_REG_HDR_VM).CODE(), RSC(SYS_REG_FLAGS_VM).CODE()}, + [13] = {RSC(SYS_REG_HDR_AC).CODE(), RSC(SYS_REG_FLAGS_AC).CODE()}, + [14] = {RSC(SYS_REG_HDR_VIF).CODE(), RSC(SYS_REG_FLAGS_VIF).CODE()}, + [15] = {RSC(SYS_REG_HDR_VIP).CODE(), RSC(SYS_REG_FLAGS_VIP).CODE()}, + [16] = {RSC(SYS_REG_HDR_ID).CODE(), RSC(SYS_REG_FLAGS_ID).CODE()}, {NULL, NULL} }, .flag = (struct SR_BIT[]) { [ 0] = {DO_CPU , 1 , UNDEF_CR , 0 }, [ 1] = {DO_SPC , 1 , UNDEF_CR , 0 }, - [ 2] = {DO_FLAG, 1 , RFLAG_TF , 1 }, - [ 3] = {DO_FLAG, 1 , RFLAG_IF , 1 }, - [ 4] = {DO_FLAG, 1 , RFLAG_IOPL , 2 }, - [ 5] = {DO_FLAG, 1 , RFLAG_NT , 1 }, - [ 6] = {DO_FLAG, 1 , RFLAG_RF , 1 }, - [ 7] = {DO_FLAG, 1 , RFLAG_VM , 1 }, - [ 8] = {DO_FLAG, 1 , RFLAG_AC , 1 }, - [ 9] = {DO_FLAG, 1 , RFLAG_VIF , 1 }, - [10] = {DO_FLAG, 1 , RFLAG_VIP , 1 }, - [11] = {DO_FLAG, 1 , RFLAG_ID , 1 }, - [12] = {DO_SPC , 1 , UNDEF_CR , 0 }, - [13] = {DO_SPC , 1 , UNDEF_CR , 0 }, - [14] = {DO_SPC , 1 , UNDEF_CR , 0 }, - [15] = {DO_SPC , 1 , UNDEF_CR , 0 }, - [16] = {DO_SPC , 1 , UNDEF_CR , 0 }, + [ 2] = {DO_FLAG, 1 , RFLAG_CF , 1 }, + [ 3] = {DO_FLAG, 1 , RFLAG_ZF , 1 }, + [ 4] = {DO_FLAG, 1 , RFLAG_SF , 1 }, + [ 5] = {DO_FLAG, 1 , RFLAG_TF , 1 }, + [ 6] = {DO_FLAG, 1 , RFLAG_IF , 1 }, + [ 7] = {DO_FLAG, 1 , RFLAG_DF , 1 }, + [ 8] = {DO_FLAG, 1 , RFLAG_OF , 1 }, + [ 9] = {DO_FLAG, 1 , RFLAG_IOPL , 2 }, + [10] = {DO_FLAG, 1 , RFLAG_NT , 1 }, + [11] = {DO_FLAG, 1 , RFLAG_RF , 1 }, + [12] = {DO_FLAG, 1 , RFLAG_VM , 1 }, + [13] = {DO_FLAG, 1 , RFLAG_AC , 1 }, + [14] = {DO_FLAG, 1 , RFLAG_VIF , 1 }, + [15] = {DO_FLAG, 1 , RFLAG_VIP , 1 }, + [16] = {DO_FLAG, 1 , RFLAG_ID , 1 }, {DO_END , 1 , UNDEF_CR , 0 } } }, @@ -659,7 +660,7 @@ REASON_CODE SystemRegisters( Window *win, [ 8] = {RSC(SYS_REG_HDR_CR4_PKS).CODE(),RSC(SYS_REG_CR4_PKS).CODE()}, [ 9] ={RSC(SYS_REG_HDR_CR4_UINTR).CODE(),RSC(SYS_REG_CR4_UINTR).CODE()}, [10] = {RSC(SYS_REG_HDR_CR4_LAM).CODE(),RSC(SYS_REG_CR4_LAM).CODE()}, - [11] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + [11] = {RSC(SYS_REG_HDR_CR4_FRED).CODE(),RSC(SYS_REG_CR4_FRED).CODE()}, [12] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, [13] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, [14] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, @@ -679,7 +680,7 @@ REASON_CODE SystemRegisters( Window *win, [ 8] = {DO_CR4 , 1 , CR4_PKS , 1 }, [ 9] = {DO_CR4 , 1 , CR4_UINTR , 1 }, [10] = {DO_CR4 , 1 , CR4_LAM_SUP , 1 }, - [11] = {DO_SPC , 1 , UNDEF_CR , 0 }, + [11] = {DO_CR4 , 1 , CR4_FRED , 1 }, [12] = {DO_SPC , 1 , UNDEF_CR , 0 }, [13] = {DO_SPC , 1 , UNDEF_CR , 0 }, [14] = {DO_SPC , 1 , UNDEF_CR , 0 }, @@ -784,9 +785,9 @@ REASON_CODE SystemRegisters( Window *win, [ 7] = {RSC(SYS_REG_HDR_XCR0_MPK).CODE(), RSC(SYS_REG_XCR0_MPK).CODE()}, [ 8] = {RSC(SYS_REG_HDR_XCR0_CEU).CODE(), RSC(SYS_REG_XCR0_CEU).CODE()}, [ 9] = {RSC(SYS_REG_HDR_XCR0_CES).CODE(), RSC(SYS_REG_XCR0_CES).CODE()}, - [10] = {RSC(SYS_REG_HDR_XCR0_LWP).CODE(), RSC(SYS_REG_XCR0_LWP).CODE()}, - [11] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, - [12] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + [10] = {RSC(SYS_REG_HDR_XCR0_AMX).CODE(), RSC(SYS_REG_XCR0_AMX).CODE()}, + [11] = {RSC(SYS_REG_HDR_XCR0_APX).CODE(), RSC(SYS_REG_XCR0_APX).CODE()}, + [12] = {RSC(SYS_REG_HDR_XCR0_LWP).CODE(), RSC(SYS_REG_XCR0_LWP).CODE()}, [13] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, [14] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, [15] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, @@ -799,14 +800,14 @@ REASON_CODE SystemRegisters( Window *win, [ 2] = {DO_XCR0, RO(Shm)->Proc.Features.Std.ECX.XSAVE, XCR0_FPU, 1}, [ 3] = {DO_XCR0, RO(Shm)->Proc.Features.Std.ECX.XSAVE, XCR0_SSE, 1}, [ 4] = {DO_XCR0, RO(Shm)->Proc.Features.Std.ECX.XSAVE, XCR0_AVX, 1}, - [ 5] = {DO_XCR0, RO(Shm)->Proc.Features.Std.ECX.XSAVE, XCR0_MPX, 1}, + [ 5] = {DO_XCR0, RO(Shm)->Proc.Features.Std.ECX.XSAVE, XCR0_MPX, 2}, [ 6] = {DO_XCR0, RO(Shm)->Proc.Features.Std.ECX.XSAVE, XCR0_AVX512, 3}, [ 7] = {DO_XCR0, RO(Shm)->Proc.Features.Std.ECX.XSAVE, XCR0_PKRU, 1}, [ 8] = {DO_XCR0, RO(Shm)->Proc.Features.Std.ECX.XSAVE, XCR0_CET_U, 1}, [ 9] = {DO_XCR0, RO(Shm)->Proc.Features.Std.ECX.XSAVE, XCR0_CET_S, 1}, - [10] = {DO_XCR0, RO(Shm)->Proc.Features.Std.ECX.XSAVE, XCR0_LWP, 1}, - [11] = {DO_SPC , 1 , UNDEF_CR , 0 }, - [12] = {DO_SPC , 1 , UNDEF_CR , 0 }, + [10] = {DO_XCR0, RO(Shm)->Proc.Features.Std.ECX.XSAVE, XCR0_AMX, 2}, + [11] = {DO_XCR0, RO(Shm)->Proc.Features.Std.ECX.XSAVE, XCR0_APX, 1}, + [12] = {DO_XCR0, RO(Shm)->Proc.Features.Std.ECX.XSAVE, XCR0_LWP, 1}, [13] = {DO_SPC , 1 , UNDEF_CR , 0 }, [14] = {DO_SPC , 1 , UNDEF_CR , 0 }, [15] = {DO_SPC , 1 , UNDEF_CR , 0 }, @@ -855,6 +856,90 @@ REASON_CODE SystemRegisters( Window *win, [16] = {DO_SPC , 1 , UNDEF_CR , 0 }, {DO_END , 1 , UNDEF_CR , 0 } } + }, + { + .header = (struct SR_HDR[]) { + [ 0] = {RSC(SYS_REG_HDR_HWCR).CODE() , RSC(SYS_REGS_HWCR).CODE()}, + [ 1] = {RSC(SYS_REG_HDR_HWCR_SMM).CODE(), RSC(SYS_REG_HWCR_SMM).CODE()}, + [ 2] = {RSC(SYS_REG_HDR_HWCR_SLW).CODE(), RSC(SYS_REG_HWCR_SLW).CODE()}, + [ 3] = {RSC(SYS_REG_HDR_HWCR_TLB).CODE(), RSC(SYS_REG_HWCR_TLB).CODE()}, + [ 4] = {RSC(SYS_REG_HDR_HWCR_WBI).CODE(), RSC(SYS_REG_HWCR_WBI).CODE()}, + [ 5] = {RSC(SYS_REG_HDR_HWCR_FF).CODE() , RSC(SYS_REG_HWCR_FF).CODE()}, + [ 6] = {RSC(SYS_REG_HDR_HWCR_FRR).CODE(), RSC(SYS_REG_HWCR_FRR).CODE()}, + [ 7] = {RSC(SYS_REG_HDR_HWCR_IG).CODE() , RSC(SYS_REG_HWCR_IG).CODE()}, + [ 8] = {RSC(SYS_REG_HDR_HWCR_SMW).CODE(), RSC(SYS_REG_HWCR_SMW).CODE()}, + [ 9] = {RSC(SYS_REG_HDR_HWCR_UMW).CODE(), RSC(SYS_REG_HWCR_UMW).CODE()}, + [10] = {RSC(SYS_REG_HDR_HWCR_HLT).CODE(), RSC(SYS_REG_HWCR_HLT).CODE()}, + [11] = {RSC(SYS_REG_HDR_HWCR_SMI).CODE(), RSC(SYS_REG_HWCR_SMI).CODE()}, + [12] = {RSC(SYS_REG_HDR_HWCR_RSM).CODE(), RSC(SYS_REG_HWCR_RSM).CODE()}, + [13] = {RSC(SYS_REG_HDR_HWCR_SSE).CODE(), RSC(SYS_REG_HWCR_SSE).CODE()}, + [14] = {RSC(SYS_REG_HDR_HWCR_WRP).CODE(), RSC(SYS_REG_HWCR_WRP).CODE()}, + [15] = {RSC(SYS_REG_HDR_HWCR_MC).CODE() , RSC(SYS_REG_HWCR_MC).CODE()}, + [16] = {RSC(SYS_REG_HDR_HWCR_IO).CODE() , RSC(SYS_REG_HWCR_IO).CODE()}, + {NULL, NULL} + }, + .flag = (struct SR_BIT[]) { + [ 0] = {DO_CPU , 1 , UNDEF_CR , 0 }, + [ 1] = {DO_HWCR, fAMD , HWCR_SMM , 1 }, + [ 2] = {DO_HWCR, fAMD , HWCR_SLW , 1 }, + [ 3] = {DO_HWCR, fAMD , HWCR_TLB , 1 }, + [ 4] = {DO_HWCR, fAMD , HWCR_WBI , 1 }, + [ 5] = {DO_HWCR, fAMD , HWCR_FF , 1 }, + [ 6] = {DO_HWCR, fAMD , HWCR_FRR , 1 }, + [ 7] = {DO_HWCR, fAMD , HWCR_IG , 1 }, + [ 8] = {DO_HWCR, fAMD , HWCR_SMW , 1 }, + [ 9] = {DO_HWCR, fAMD , HWCR_UMW , 1 }, + [10] = {DO_HWCR, fAMD , HWCR_HLT , 1 }, + [11] = {DO_HWCR, fAMD , HWCR_SMI , 1 }, + [12] = {DO_HWCR, fAMD , HWCR_RSM , 1 }, + [13] = {DO_HWCR, fAMD , HWCR_SSE , 1 }, + [14] = {DO_HWCR, fAMD , HWCR_WRP , 1 }, + [15] = {DO_HWCR, fAMD , HWCR_MC , 1 }, + [16] = {DO_HWCR, fAMD , HWCR_IO , 1 }, + {DO_END , 1 , UNDEF_CR , 0 } + } + }, + { + .header = (struct SR_HDR[]) { + [ 0] = {RSC(SYS_REG_HDR_HWCR).CODE() , RSC(SYS_REGS_HWCR).CODE()}, + [ 1] = {RSC(SYS_REG_HDR_HWCR_P0).CODE() , RSC(SYS_REG_HWCR_P0).CODE()}, + [ 2] = {RSC(SYS_REG_HDR_HWCR_PRB).CODE(), RSC(SYS_REG_HWCR_PRB).CODE()}, + [ 3] = {RSC(SYS_REG_HDR_HWCR_INC).CODE(), RSC(SYS_REG_HWCR_INC).CODE()}, + [ 4] = {RSC(SYS_REG_HDR_HWCR_CPB).CODE(), RSC(SYS_REG_HWCR_CPB).CODE()}, + [ 5] = {RSC(SYS_REG_HDR_HWCR_HCF).CODE(), RSC(SYS_REG_HWCR_HCF).CODE()}, + [ 6] = {RSC(SYS_REG_HDR_HWCR_ROC).CODE(), RSC(SYS_REG_HWCR_ROC).CODE()}, + [ 7] = {RSC(SYS_REG_HDR_HWCR_SMU).CODE(), RSC(SYS_REG_HWCR_SMU).CODE()}, + [ 8] = {RSC(SYS_REG_HDR_HWCR_CSE).CODE(), RSC(SYS_REG_HWCR_CSE).CODE()}, + [ 9] = {RSC(SYS_REG_HDR_HWCR_IR).CODE() , RSC(SYS_REG_HWCR_IR).CODE()}, + [10] = {RSC(SYS_REG_HDR_HWCR_SBR).CODE(), RSC(SYS_REG_HWCR_SBR).CODE()}, + [11] = {RSC(SYS_REG_HDR_HWCR_TPR).CODE(), RSC(SYS_REG_HWCR_TPR).CODE()}, + [12] = {RSC(SYS_REG_HDR_HWCR_PG).CODE() , RSC(SYS_REG_HWCR_PG).CODE()}, + [13] = {RSC(SYS_REG_HDR_HWCR_ID).CODE() , RSC(SYS_REG_HWCR_ID).CODE()}, + [14] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + [15] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + [16] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + {NULL, NULL} + }, + .flag = (struct SR_BIT[]) { + [ 0] = {DO_CPU , 1 , UNDEF_CR , 0 }, + [ 1] = {DO_HWCR, fAMD , HWCR_P0 , 1 }, + [ 2] = {DO_HWCR, fAMD , HWCR_PRB , 1 }, + [ 3] = {DO_HWCR, fAMD , HWCR_INC , 1 }, + [ 4] = {DO_HWCR, fAMD , HWCR_CPB , 1 }, + [ 5] = {DO_HWCR, fAMD , HWCR_HCF , 1 }, + [ 6] = {DO_HWCR, fAMD , HWCR_ROC , 1 }, + [ 7] = {DO_HWCR, fAMD , HWCR_SMU , 1 }, + [ 8] = {DO_HWCR, fAMD , HWCR_CSE , 1 }, + [ 9] = {DO_HWCR, fAMD , HWCR_IR , 1 }, + [10] = {DO_HWCR, fAMD , HWCR_SBR , 1 }, + [11] = {DO_HWCR, fAMD , HWCR_TPR , 1 }, + [12] = {DO_HWCR, fAMD , HWCR_PG , 1 }, + [13] = {DO_HWCR, fAMD , HWCR_ID , 1 }, + [14] = {DO_SPC , 1 , UNDEF_CR , 0 }, + [15] = {DO_SPC , 1 , UNDEF_CR , 0 }, + [16] = {DO_SPC , 1 , UNDEF_CR , 0 }, + {DO_END , 1 , UNDEF_CR , 0 } + } } }; @@ -934,6 +1019,11 @@ REASON_CODE SystemRegisters( Window *win, BITEXTRZ(RO(Shm)->Cpu[cpu].SystemRegister.SYSCFG, pFlag->pos, pFlag->len)); break; + case DO_HWCR: + PRT(REG, attrib[2], "%3llx ", + BITEXTRZ(RO(Shm)->Cpu[cpu].SystemRegister.HWCR, + pFlag->pos, pFlag->len)); + break; default: PRT(REG, attrib[1], RSC(SYS_REGS_NA).CODE()); break; @@ -1068,6 +1158,23 @@ void RefreshTopFreq(TGrid *grid, DATA_TYPE data[]) RefreshItemFreq(grid, ratio, ABS_FREQ_MHz(double, ratio, CFlop->Clock)); } +void RefreshPrimaryFreq(TGrid *grid, DATA_TYPE data[]) +{ + enum RATIO_BOOST boost = data[0].uint[0]; + unsigned int ratio = RO(Shm)->Cpu[ + RO(Shm)->Proc.Service.Core + ].Boost[boost]; + + struct FLIP_FLOP *CFlop = &RO(Shm)->Cpu[ + RO(Shm)->Proc.Service.Core + ].FlipFlop[ + !RO(Shm)->Cpu[ + RO(Shm)->Proc.Service.Core + ].Toggle + ]; + RefreshItemFreq(grid, ratio, ABS_FREQ_MHz(double, ratio, CFlop->Clock)); +} + void RefreshHybridFreq(TGrid *grid, DATA_TYPE data[]) { enum RATIO_BOOST boost = data[0].uint[0]; @@ -1379,22 +1486,23 @@ REASON_CODE SysInfoProc(Window *win, boost--, activeCores++) { CLOCK_ARG clockMod={.NC=BOXKEY_TURBO_CLOCK_NC | activeCores,.Offset=0}; + const unsigned int primary = \ + RO(Shm)->Proc.Features.ExtFeature.EDX.Hybrid == 1 ? + RO(Shm)->Proc.Service.Core : Ruler.Top[boost]; + char pfx[10+1+1]; StrFormat(pfx, 10+1+1, "%2uC", activeCores); - CFlop = &RO(Shm)->Cpu[ - Ruler.Top[boost] - ].FlipFlop[ - !RO(Shm)->Cpu[ Ruler.Top[boost] ].Toggle - ]; + CFlop = &RO(Shm)->Cpu[primary].FlipFlop[!RO(Shm)->Cpu[primary].Toggle]; GridCall( PrintRatioFreq(win, CFlop, 0, pfx, &RO(Shm)->Cpu[ - Ruler.Top[boost] + primary ].Boost[boost], 1, clockMod.ullong, width, OutFunc, cellPadding, attrib[3] ), - RefreshTopFreq, boost ); + RO(Shm)->Proc.Features.ExtFeature.EDX.Hybrid == 1 ? + RefreshPrimaryFreq : RefreshTopFreq, boost ); } if (RO(Shm)->Proc.Features.ExtFeature.EDX.Hybrid == 1) { @@ -2497,6 +2605,14 @@ REASON_CODE SysInfoFeatures( Window *win, width - 18 - RSZ(FEATURES_FMA), NULL }, + { + (unsigned int[]) { CRC_INTEL, 0 }, + RO(Shm)->Proc.Features.ExtFeature_Leaf1_EAX.FRED == 1, + attr_Feat, + 2, "%s%.*sFRED [%7s]", RSC(FEATURES_FRED).CODE(), + width - 19 - RSZ(FEATURES_FRED), + NULL + }, { (unsigned int[]) { CRC_INTEL, 0 }, RO(Shm)->Proc.Features.Power.EAX.HWFB_Cap == 1, @@ -2513,6 +2629,14 @@ REASON_CODE SysInfoFeatures( Window *win, width - 18 - RSZ(FEATURES_HLE), NULL }, + { + NULL, + RO(Shm)->Proc.Features.Std.EDX.HTT == 1, + attr_Feat, + 2, "%s%.*sHTT [%7s]", RSC(FEATURES_HTT).CODE(), + width - 18 - RSZ(FEATURES_HTT), + NULL + }, { (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, RO(Shm)->Proc.Features.AdvPower.EDX.HwPstate == 1, @@ -2585,6 +2709,14 @@ REASON_CODE SysInfoFeatures( Window *win, width - 18 - RSZ(FEATURES_LAM), NULL }, + { + (unsigned int[]) { CRC_INTEL, 0 }, + RO(Shm)->Proc.Features.ExtFeature_Leaf1_EAX.LKGS == 1, + attr_Feat, + 2, "%s%.*sLKGS [%7s]", RSC(FEATURES_LKGS).CODE(), + width - 19 - RSZ(FEATURES_LKGS), + NULL + }, { NULL, RO(Shm)->Proc.Features.ExtInfo.ECX.LWP == 1, @@ -2618,7 +2750,7 @@ REASON_CODE SysInfoFeatures( Window *win, NULL }, { - NULL, + (unsigned int[]) { CRC_INTEL, 0 }, RO(Shm)->Proc.Features.ExtFeature.EBX.MPX == 1, attr_Feat, 2, "%s%.*sMPX [%7s]", RSC(FEATURES_MPX).CODE(), @@ -2642,7 +2774,7 @@ REASON_CODE SysInfoFeatures( Window *win, NULL }, { - (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, + NULL, RO(Shm)->Proc.Features.ExtInfo.EDX.NX == 1, attr_Feat, 2, "%s%.*sNX [%7s]", RSC(FEATURES_NX).CODE(), @@ -3063,6 +3195,14 @@ REASON_CODE SysInfoFeatures( Window *win, width - 23 - RSZ(MECH_BTC_NOBR), MECH }, + { + (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, + RO(Shm)->Proc.Mechanisms.AGENPICK, + attr_Feat, + 2, "%s%.*sAGENPICK [%7s]", RSC(MECH_AGENPICK).CODE(), + width - 23 - RSZ(MECH_AGENPICK), + MECH + }, { (unsigned int[]) { CRC_INTEL, 0 }, RO(Shm)->Proc.Features.ExtFeature.EDX.L1D_FLUSH_Cap == 1, @@ -3193,6 +3333,14 @@ REASON_CODE SysInfoFeatures( Window *win, width - 19 - RSZ(MECH_PSFD), MECH }, + { + (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, + RO(Shm)->Proc.Features.ExtFeature2_EAX.EPSF, + attr_Feat, + 2, "%s%.*sEPSF [%7s]", RSC(MECH_EPSF).CODE(), + width - 19 - RSZ(MECH_EPSF), + NULL + }, /* Section Mark */ { (unsigned int[]) { CRC_INTEL, 0 }, @@ -3354,6 +3502,46 @@ REASON_CODE SysInfoFeatures( Window *win, width - 22 - RSZ(MECH_MCDT_NO), MECH }, + { + (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, + RO(Shm)->Proc.Mechanisms.XPROC_LEAK, + attr_Feat, + 2, "%s%.*sXPROC_LEAK [%7s]", RSC(MECH_XPROC_LEAK).CODE(), + width - 25 - RSZ(MECH_XPROC_LEAK), + MECH + }, + { + (unsigned int[]) { CRC_INTEL, 0 }, + 0, + attr_Feat, + 2, "%s", RSC(MECH_OVERCLOCKING).CODE(), + 0, + NULL + }, + { + (unsigned int[]) { CRC_INTEL, 0 }, + RO(Shm)->Proc.Mechanisms.OC_UTILIZED, + attr_Feat, + 3, "%s%.*sUTILIZED [%7s]", RSC(MECH_OC_UTILIZED).CODE(), + width - (OutFunc == NULL ? 26:24) - RSZ(MECH_OC_UTILIZED), + MECH + }, + { + (unsigned int[]) { CRC_INTEL, 0 }, + RO(Shm)->Proc.Mechanisms.OC_UNDERVOLT, + attr_Feat, + 3, "%s%.*sUVP [%7s]", RSC(MECH_OC_UNDERVOLT).CODE(), + width - (OutFunc == NULL ? 21:19) - RSZ(MECH_OC_UNDERVOLT), + MECH + }, + { + (unsigned int[]) { CRC_INTEL, 0 }, + RO(Shm)->Proc.Mechanisms.OC_UNLOCKED, + attr_Feat, + 3, "%s%.*sUNLOCKED [%7s]", RSC(MECH_OC_UNLOCKED).CODE(), + width - (OutFunc == NULL ? 26:24) - RSZ(MECH_OC_UNLOCKED), + MECH + }, /* Section Mark */ { NULL, @@ -3381,6 +3569,30 @@ REASON_CODE SysInfoFeatures( Window *win, width - 21 - RSZ(SECURITY_AESKLE), NULL }, + { + (unsigned int[]) { CRC_INTEL, CRC_AMD, CRC_HYGON, 0 }, + RO(Shm)->Proc.Features.ExtFeature.ECX.CET_SS == 1, + attr_Feat, + 2, "%s%.*sCET-SS [%7s]", RSC(SECURITY_CET_SS).CODE(), + width - 21 - RSZ(SECURITY_CET_SS), + NULL + }, + { + (unsigned int[]) { CRC_INTEL, 0 }, + RO(Shm)->Proc.Features.ExtFeature.EDX.CET_IBT == 1, + attr_Feat, + 2, "%s%.*sCET-IBT [%7s]", RSC(SECURITY_CET_IBT).CODE(), + width - 22 - RSZ(SECURITY_CET_IBT), + NULL + }, + { + (unsigned int[]) { CRC_INTEL, 0 }, + RO(Shm)->Proc.Features.ExtFeature_Leaf1_EDX.CET_SSS == 1, + attr_Feat, + 2, "%s%.*sCET-SSS [%7s]", RSC(SECURITY_CET_SSS).CODE(), + width - 22 - RSZ(SECURITY_CET_SSS), + NULL + }, { (unsigned int[]) { CRC_INTEL, 0 }, BITVAL(RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].CpuID[ @@ -3584,6 +3796,24 @@ void L1_HW_IP_Prefetch_Update(TGrid *grid, DATA_TYPE data[]) TechUpdate(grid, bix, pos, 3, ENABLED(bix)); } +void L1_NPP_Prefetch_Update(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int bix = RO(Shm)->Proc.Technology.L1_NPP_Prefetch == 1; + const signed int pos = grid->cell.length - 5; + UNUSED(data); + + TechUpdate(grid, bix, pos, 3, ENABLED(bix)); +} + +void L1_Scrubbing_Update(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int bix = RO(Shm)->Proc.Technology.L1_Scrubbing == 1; + const signed int pos = grid->cell.length - 5; + UNUSED(data); + + TechUpdate(grid, bix, pos, 3, ENABLED(bix)); +} + void L2_HW_Prefetch_Update(TGrid *grid, DATA_TYPE data[]) { const unsigned int bix = RO(Shm)->Proc.Technology.L2_HW_Prefetch == 1; @@ -3602,6 +3832,78 @@ void L2_HW_CL_Prefetch_Update(TGrid *grid, DATA_TYPE data[]) TechUpdate(grid, bix, pos, 3, ENABLED(bix)); } +void L2_AMP_Prefetch_Update(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int bix=RO(Shm)->Proc.Technology.L2_AMP_Prefetch == 1; + const signed int pos = grid->cell.length - 5; + UNUSED(data); + + TechUpdate(grid, bix, pos, 3, ENABLED(bix)); +} + +void L2_NLP_Prefetch_Update(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int bix = RO(Shm)->Proc.Technology.L2_NLP_Prefetch == 1; + const signed int pos = grid->cell.length - 5; + UNUSED(data); + + TechUpdate(grid, bix, pos, 3, ENABLED(bix)); +} + +void L1_Stride_Prefetch_Update(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int bix=RO(Shm)->Proc.Technology.L1_Stride_Pf == 1; + const signed int pos = grid->cell.length - 5; + UNUSED(data); + + TechUpdate(grid, bix, pos, 3, ENABLED(bix)); +} + +void L1_Region_Prefetch_Update(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int bix=RO(Shm)->Proc.Technology.L1_Region_Pf == 1; + const signed int pos = grid->cell.length - 5; + UNUSED(data); + + TechUpdate(grid, bix, pos, 3, ENABLED(bix)); +} + +void L1_Burst_Prefetch_Update(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int bix=RO(Shm)->Proc.Technology.L1_Burst_Pf == 1; + const signed int pos = grid->cell.length - 5; + UNUSED(data); + + TechUpdate(grid, bix, pos, 3, ENABLED(bix)); +} + +void L2_Stream_HW_Prefetch_Update(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int bix=RO(Shm)->Proc.Technology.L2_Stream_HW_Pf == 1; + const signed int pos = grid->cell.length - 5; + UNUSED(data); + + TechUpdate(grid, bix, pos, 3, ENABLED(bix)); +} + +void L2_UpDown_Prefetch_Update(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int bix=RO(Shm)->Proc.Technology.L2_UpDown_Pf == 1; + const signed int pos = grid->cell.length - 5; + UNUSED(data); + + TechUpdate(grid, bix, pos, 3, ENABLED(bix)); +} + +void LLC_Streamer_Update(TGrid *grid, DATA_TYPE data[]) +{ + const unsigned int bix = RO(Shm)->Proc.Technology.LLC_Streamer == 1; + const signed int pos = grid->cell.length - 5; + UNUSED(data); + + TechUpdate(grid, bix, pos, 3, ENABLED(bix)); +} + void SpeedStepUpdate(TGrid *grid, DATA_TYPE data[]) { const unsigned int bix = RO(Shm)->Proc.Technology.EIST == 1; @@ -3739,6 +4041,36 @@ REASON_CODE SysInfoTech(Window *win, BOXKEY_L1_HW_IP_PREFETCH, L1_HW_IP_Prefetch_Update }, + { + (unsigned int[]) { CRC_INTEL, 0 }, + RO(Shm)->Proc.Technology.L1_NPP_Prefetch, + 3, "%s%.*sL1 NPP <%3s>", + RSC(TECH_L1_NPP_PREFETCH).CODE(), NULL, + width - (OutFunc ? 18 : 20) - RSZ(TECH_L1_NPP_PREFETCH), + NULL, + BOXKEY_L1_NPP_PREFETCH, + L1_NPP_Prefetch_Update + }, + { + (unsigned int[]) { CRC_INTEL, 0 }, + RO(Shm)->Proc.Technology.L1_Scrubbing, + 3, "%s%.*sL1 Scrubbing <%3s>", + RSC(TECH_L1_SCRUBBING).CODE(), NULL, + width - (OutFunc ? 24 : 26) - RSZ(TECH_L1_SCRUBBING), + NULL, + BOXKEY_L1_SCRUBBING, + L1_Scrubbing_Update + }, + { + NULL, + 0, + 2, "%s%.*s", + RSC(TECHNOLOGIES_PF).CODE(), NULL, + width - 3 - RSZ(TECHNOLOGIES_PF), + NULL, + SCANKEY_NULL, + NULL + }, { (unsigned int[]) { CRC_INTEL, CRC_AMD, CRC_HYGON, 0 }, RO(Shm)->Proc.Technology.L2_HW_Prefetch, @@ -3759,6 +4091,86 @@ REASON_CODE SysInfoTech(Window *win, BOXKEY_L2_HW_CL_PREFETCH, L2_HW_CL_Prefetch_Update }, + { + (unsigned int[]) { CRC_INTEL, 0 }, + RO(Shm)->Proc.Technology.L2_AMP_Prefetch, + 3, "%s%.*sL2 AMP <%3s>", + RSC(TECH_L2_AMP_PREFETCH).CODE(), NULL, + width - (OutFunc ? 18 : 20) - RSZ(TECH_L2_AMP_PREFETCH), + NULL, + BOXKEY_L2_AMP_PREFETCH, + L2_AMP_Prefetch_Update + }, + { + (unsigned int[]) { CRC_INTEL, 0 }, + RO(Shm)->Proc.Technology.L2_NLP_Prefetch, + 3, "%s%.*sL2 NLP <%3s>", + RSC(TECH_L2_NLP_PREFETCH).CODE(), NULL, + width - (OutFunc ? 18 : 20) - RSZ(TECH_L2_NLP_PREFETCH), + NULL, + BOXKEY_L2_NLP_PREFETCH, + L2_NLP_Prefetch_Update + }, + { + (unsigned int[]) { CRC_INTEL, 0 }, + RO(Shm)->Proc.Technology.LLC_Streamer, + 3, "%s%.*sLLC <%3s>", + RSC(TECH_LLC_STREAMER).CODE(), NULL, + width - (OutFunc ? 15 : 17) - RSZ(TECH_LLC_STREAMER), + NULL, + BOXKEY_LLC_STREAMER, + LLC_Streamer_Update + }, + { + (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, + RO(Shm)->Proc.Technology.L1_Stride_Pf, + 3, "%s%.*sL1 Stride <%3s>", + RSC(TECH_L1_STRIDE_PF).CODE(), NULL, + width - (OutFunc ? 21 : 23) - RSZ(TECH_L1_STRIDE_PF), + NULL, + BOXKEY_L1_STRIDE_PREFETCH, + L1_Stride_Prefetch_Update + }, + { + (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, + RO(Shm)->Proc.Technology.L1_Region_Pf, + 3, "%s%.*sL1 Region <%3s>", + RSC(TECH_L1_REGION_PF).CODE(), NULL, + width - (OutFunc ? 21 : 23) - RSZ(TECH_L1_REGION_PF), + NULL, + BOXKEY_L1_REGION_PREFETCH, + L1_Region_Prefetch_Update + }, + { + (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, + RO(Shm)->Proc.Technology.L1_Burst_Pf, + 3, "%s%.*sL1 Burst <%3s>", + RSC(TECH_L1_BURST_PF).CODE(), NULL, + width - (OutFunc ? 20 : 22) - RSZ(TECH_L1_BURST_PF), + NULL, + BOXKEY_L1_BURST_PREFETCH, + L1_Burst_Prefetch_Update + }, + { + (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, + RO(Shm)->Proc.Technology.L2_Stream_HW_Pf, + 3, "%s%.*sL2 Stream <%3s>", + RSC(TECH_L2_STREAM_HW_PF).CODE(), NULL, + width - (OutFunc ? 21 : 23) - RSZ(TECH_L2_STREAM_HW_PF), + NULL, + BOXKEY_L2_STREAM_HW_PREFETCH, + L2_Stream_HW_Prefetch_Update + }, + { + (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, + RO(Shm)->Proc.Technology.L2_UpDown_Pf, + 3, "%s%.*sL2 Up/Down <%3s>", + RSC(TECH_L2_UPDOWN_PF).CODE(), NULL, + width - (OutFunc ? 22 : 24) - RSZ(TECH_L2_UPDOWN_PF), + NULL, + BOXKEY_L2_UPDOWN_PREFETCH, + L2_UpDown_Prefetch_Update + }, { (unsigned int[]) { CRC_INTEL, 0 }, RO(Shm)->Proc.Technology.SMM == 1, @@ -4552,6 +4964,22 @@ REASON_CODE SysInfoPerfMon( Window *win, RO(Shm)->Proc.Features.MWait.EDX.SubCstate_MWAIT5, RO(Shm)->Proc.Features.MWait.EDX.SubCstate_MWAIT6, RO(Shm)->Proc.Features.MWait.EDX.SubCstate_MWAIT7 ); + + bix = RO(Shm)->Proc.Features.MWait.ECX.EMX_MWAIT == 1 ? 2 : 0; + + PUT( SCANKEY_NULL, attrib[bix], width, 3, "%s%.*s%s [%7s]", + RSC(PERF_MON_MWAIT_EMX_MWAIT).CODE(), + width - (OutFunc == NULL ? 21 : 19 ) + - RSZ(PERF_MON_MWAIT_EMX_MWAIT), hSpace, + RSC(PERF_LABEL_EMX).CODE(), POWERED(bix) ); + + bix = RO(Shm)->Proc.Features.MWait.ECX.IBE_MWAIT == 1 ? 2 : 0; + + PUT( SCANKEY_NULL, attrib[bix], width, 3, "%s%.*s%s [%7s]", + RSC(PERF_MON_MWAIT_IBE_MWAIT).CODE(), + width - (OutFunc == NULL ? 21 : 19 ) + - RSZ(PERF_MON_MWAIT_IBE_MWAIT), hSpace, + RSC(PERF_LABEL_IBE).CODE(), POWERED(bix) ); /* Section Mark */ bix = (RO(Shm)->Proc.Features.PerfMon.EBX.CoreCycles == 0) || (RO(Shm)->Proc.Features.PerfMon.EAX.VectorSz > 0) ? 2 : 0; @@ -6315,7 +6743,9 @@ void Counters(unsigned int iter) ClientFollowService(&localService, &RO(Shm)->Proc.Service, 0); } idx = sdx; - for (cpu=0;(cpu < RO(Shm)->Proc.CPU.Count) && !BITVAL(Shutdown, SYNC);cpu++) + for (cpu = 0; + (cpu < RO(Shm)->Proc.CPU.Count) && !BITVAL(Shutdown, SYNC); + cpu++) { if (!BITVAL(RO(Shm)->Cpu[cpu].OffLine, HW)) { struct FLIP_FLOP *CFlop = \ @@ -6551,8 +6981,8 @@ void Power(unsigned int iter) idx += ldx; for (pw = PWR_DOMAIN(PKG); pw < PWR_DOMAIN(PLATFORM); pw++) { - rdx = sprintf(&out[idx], "%.*s" "%6.2f%6.2f%6.2f", - pw == PWR_DOMAIN(PKG) ? 1 : 2, hSpace, + rdx = sprintf(&out[idx], "%.*s" "%6.2f %5.1f %6.2f", + pw == PWR_DOMAIN(PKG) ? 0 : 1, hSpace, RO(Shm)->Proc.State.Energy[pw].Limit[SENSOR_LOWEST], RO(Shm)->Proc.State.Energy[pw].Current, RO(Shm)->Proc.State.Energy[pw].Limit[SENSOR_HIGHEST]); @@ -6564,8 +6994,8 @@ void Power(unsigned int iter) idx += 10; for (pw = PWR_DOMAIN(PKG); pw < PWR_DOMAIN(PLATFORM); pw++) { - rdx = sprintf(&out[idx], "%.*s" "%6.2f%6.2f%6.2f", - pw == PWR_DOMAIN(PKG) ? 1 : 2, hSpace, + rdx = sprintf(&out[idx], "%.*s" "%6.2f %5.1f %6.2f", + pw == PWR_DOMAIN(PKG) ? 0 : 1, hSpace, RO(Shm)->Proc.State.Power[pw].Limit[SENSOR_LOWEST], RO(Shm)->Proc.State.Power[pw].Current, RO(Shm)->Proc.State.Power[pw].Limit[SENSOR_HIGHEST]); @@ -6931,31 +7361,42 @@ void Topology(Window *win, CELL_FUNC OutFunc, unsigned int *cellPadding) TopologySubHeader[1] = TopologyAltSubHeader[1]; TopologyUpdate = Topology_CMP_Update; break; - case AMD_Family_17h: - case Hygon_Family_18h: - case AMD_Family_19h: - case AMD_Zen: + /* Zen APU */ case AMD_Zen_APU: - case AMD_ZenPlus: case AMD_ZenPlus_APU: case AMD_Zen_Dali: - case AMD_EPYC_Rome_CPK: case AMD_Zen2_Renoir: case AMD_Zen2_LCN: - case AMD_Zen2_MTS: case AMD_Zen2_Ariel: case AMD_Zen2_Jupiter: + case AMD_Zen2_Galileo: case AMD_Zen2_MDN: - case AMD_Zen3_VMR: case AMD_Zen3_CZN: + case AMD_Zen3Plus_RMB: + case AMD_Zen4_PHX: + case AMD_Zen4_HWK: + case AMD_Zen4_PHX2: + TopologyFunc = Topology_SMT; + OffLineItem = RSC(TOPOLOGY_OFF_0).CODE(); + TopologySubHeader[1] = TopologyAltSubHeader[0]; + TopologyUpdate = Topology_SMT_Update; + break; + /* Zen CPU Complex */ + case AMD_Family_17h: + case Hygon_Family_18h: + case AMD_Family_19h: + case AMD_Zen: + case AMD_ZenPlus: + case AMD_EPYC_Rome_CPK: + case AMD_Zen2_MTS: + case AMD_Zen3_VMR: case AMD_EPYC_Milan: case AMD_Zen3_Chagall: case AMD_Zen3_Badami: - case AMD_Zen3Plus_RMB: case AMD_Zen4_Genoa: case AMD_Zen4_RPL: - case AMD_Zen4_PHX: case AMD_Zen4_Bergamo: + case AMD_Zen4_STP: TopologyFunc = Topology_CCD; OffLineItem = RSC(TOPOLOGY_OFF_2).CODE(); TopologySubHeader[1] = TopologyAltSubHeader[2]; @@ -9024,9 +9465,9 @@ Window *CreateSysInfo(unsigned long long id) break; case SCANKEY_t: { - winOrigin.col = 23; - matrixSize.hth = 14; - winOrigin.row = TOP_HEADER_ROW + 5; + winOrigin.col = 14; + matrixSize.hth = 18; + winOrigin.row = TOP_HEADER_ROW + 2; winWidth = 60; SysInfoFunc = SysInfoTech; title = RSC(TECHNOLOGIES_TITLE).CODE(); @@ -9042,7 +9483,7 @@ Window *CreateSysInfo(unsigned long long id) break; case SCANKEY_w: { - winOrigin.col = 25; + winOrigin.col = 18; matrixSize.hth = 28; winOrigin.row = TOP_HEADER_ROW + 2; winWidth = 60; @@ -9227,6 +9668,8 @@ Window *CreateISA(unsigned long long id) StoreWindow(wISA, .key.Right, MotionRight_Win); StoreWindow(wISA, .key.Down, MotionDown_Win); StoreWindow(wISA, .key.Up, MotionUp_Win); + StoreWindow(wISA, .key.PgUp, MotionPgUp_Win); + StoreWindow(wISA, .key.PgDw, MotionPgDw_Win); StoreWindow(wISA, .key.Home, MotionHome_Win); StoreWindow(wISA, .key.End, MotionEnd_Win); @@ -10958,7 +11401,10 @@ Window *CreateSelectIdle(unsigned long long id) } StoreWindow(wIdle, .title, (char*) RSC(BOX_IDLE_LIMIT_TITLE).CODE()); - wIdle->matrix.select.row = RO(Shm)->SysGate.OS.IdleDriver.stateLimit; + wIdle->matrix.select.row = RO(Shm)->SysGate.OS.IdleDriver.stateLimit \ + < RO(Shm)->SysGate.OS.IdleDriver.stateCount ? + RO(Shm)->SysGate.OS.IdleDriver.stateLimit : 0; + TCellAt(wIdle, 0, wIdle->matrix.select.row).attr[ 8] = \ TCellAt(wIdle, 0, wIdle->matrix.select.row).attr[ 9] = \ TCellAt(wIdle, 0, wIdle->matrix.select.row).attr[10] = \ @@ -11623,7 +12069,11 @@ Window *PopUpMessage(ASCII *title, RING_CTRL *pCtrl) if (pCtrl->drc < RC_DRIVER_BASE) { + #ifdef __GLIBC__ sysMsg = strerror_r(pCtrl->drc, inStr, POPUP_ALLOC); + #else + sysMsg = strerror(pCtrl->drc); + #endif switch ( GET_LOCALE() ) { case LOC_FR: /* Convert the System message to locale */ ISO_8859_To_Unicode((ASCII *) sysMsg, (ASCII *) inStr); @@ -13096,151 +13546,631 @@ int Shortcut(SCANKEY *scan) } break; - case SCANKEY_SHIFT_w: + case SCANKEY_SHIFT_w: + { + Draw.Disposal = D_MAINVIEW; + Draw.View = V_ENERGY; + Draw.Size.height = 0; + TrapScreenSize(SIGWINCH); + } + break; + + case SCANKEY_SHIFT_t: + { + Draw.Disposal = D_MAINVIEW; + Draw.View = V_SLICE; + Draw.Size.height = 0; + TrapScreenSize(SIGWINCH); + } + break; + + case SCANKEY_y: + { + Draw.Disposal = D_MAINVIEW; + Draw.View = V_CUSTOM; + Draw.Size.height = 0; + TrapScreenSize(SIGWINCH); + } + break; +#endif /* NO_LOWER */ + case SCANKEY_s: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) { + AppendWindow(CreateSettings(scan->key), &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case SCANKEY_r: + if ((Draw.View == V_TASKS) && (Draw.Disposal == D_MAINVIEW)) { + RING_WRITE_SUB_CMD( TASK_INVERSING, + RW(Shm)->Ring[1], + COREFREQ_TASK_MONITORING ); + } + break; + + case SCANKEY_v: + if ((Draw.View == V_TASKS) && (Draw.Disposal == D_MAINVIEW)) { + Draw.Flag.taskVal = !Draw.Flag.taskVal; + Draw.Flag.layout = 1; + } + break; +#ifndef NO_LOWER + case SCANKEY_x: + if (BITWISEAND(LOCKLESS, RO(Shm)->SysGate.Operation, 0x1)) { + Draw.Disposal = D_MAINVIEW; + Draw.View = V_TASKS; + Draw.Size.height = 0; + TrapScreenSize(SIGWINCH); + } + break; +#endif + case SCANKEY_EXCL: + if (Draw.Disposal == D_MAINVIEW) { + Draw.Load = !Draw.Load; + Draw.Flag.layout = 1; + } + break; + + case SORTBY_STATE: + { + RING_WRITE_SUB_CMD( TASK_SORTING, + RW(Shm)->Ring[1], + COREFREQ_TASK_MONITORING, + F_STATE ); + } + break; + + case SORTBY_RTIME: + { + RING_WRITE_SUB_CMD( TASK_SORTING, + RW(Shm)->Ring[1], + COREFREQ_TASK_MONITORING, + F_RTIME ); + } + break; + + case SORTBY_UTIME: + { + RING_WRITE_SUB_CMD( TASK_SORTING, + RW(Shm)->Ring[1], + COREFREQ_TASK_MONITORING, + F_UTIME ); + } + break; + + case SORTBY_STIME: + { + RING_WRITE_SUB_CMD( TASK_SORTING, + RW(Shm)->Ring[1], + COREFREQ_TASK_MONITORING, + F_STIME ); + } + break; + + case SORTBY_PID: + { + RING_WRITE_SUB_CMD( TASK_SORTING, + RW(Shm)->Ring[1], + COREFREQ_TASK_MONITORING, + F_PID ); + } + break; + + case SORTBY_COMM: + { + RING_WRITE_SUB_CMD( TASK_SORTING, + RW(Shm)->Ring[1], + COREFREQ_TASK_MONITORING, + F_COMM ); + } + break; + + case BOXKEY_L1_HW_PREFETCH: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + const Coordinate origin = { + .col = (Draw.Size.width - RSZ(BOX_BLANK_DESC)) / 2, + .row = TOP_HEADER_ROW + 2 + }, select = { + .col = 0, + .row = RO(Shm)->Proc.Technology.L1_HW_Prefetch ? 2 : 1 + }; + AppendWindow( + CreateBox(scan->key, origin, select, + (char*) RSC(BOX_CU_L1_TITLE).CODE(), + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL, + stateStr[1][RO(Shm)->Proc.Technology.L1_HW_Prefetch], + stateAttr[RO(Shm)->Proc.Technology.L1_HW_Prefetch], + BOXKEY_L1_HW_PREFETCH_ON, + stateStr[0][!RO(Shm)->Proc.Technology.L1_HW_Prefetch], + stateAttr[!RO(Shm)->Proc.Technology.L1_HW_Prefetch], + BOXKEY_L1_HW_PREFETCH_OFF, + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL), + &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case BOXKEY_L1_HW_PREFETCH_OFF: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_TECHNOLOGY, + COREFREQ_TOGGLE_OFF, + TECHNOLOGY_L1_HW_PREFETCH ); + } + break; + + case BOXKEY_L1_HW_PREFETCH_ON: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_TECHNOLOGY, + COREFREQ_TOGGLE_ON, + TECHNOLOGY_L1_HW_PREFETCH ); + } + break; + + case BOXKEY_L1_HW_IP_PREFETCH: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + const Coordinate origin = { + .col = (Draw.Size.width - RSZ(BOX_BLANK_DESC)) / 2, + .row = TOP_HEADER_ROW + 3 + }, select = { + .col = 0, + .row = RO(Shm)->Proc.Technology.L1_HW_IP_Prefetch ? 2 : 1 + }; + AppendWindow( + CreateBox(scan->key, origin, select, + (char*) RSC(BOX_CU_L1_IP_TITLE).CODE(), + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL, + stateStr[1][RO(Shm)->Proc.Technology.L1_HW_IP_Prefetch], + stateAttr[RO(Shm)->Proc.Technology.L1_HW_IP_Prefetch], + BOXKEY_L1_HW_IP_PREFETCH_ON, + stateStr[0][!RO(Shm)->Proc.Technology.L1_HW_IP_Prefetch], + stateAttr[!RO(Shm)->Proc.Technology.L1_HW_IP_Prefetch], + BOXKEY_L1_HW_IP_PREFETCH_OFF, + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL), + &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case BOXKEY_L1_HW_IP_PREFETCH_OFF: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_TECHNOLOGY, + COREFREQ_TOGGLE_OFF, + TECHNOLOGY_L1_HW_IP_PREFETCH ); + } + break; + + case BOXKEY_L1_HW_IP_PREFETCH_ON: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_TECHNOLOGY, + COREFREQ_TOGGLE_ON, + TECHNOLOGY_L1_HW_IP_PREFETCH ); + } + break; + + case BOXKEY_L1_NPP_PREFETCH: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + const Coordinate origin = { + .col = (Draw.Size.width - RSZ(BOX_BLANK_DESC)) / 2, + .row = TOP_HEADER_ROW + 3 + }, select = { + .col = 0, + .row = RO(Shm)->Proc.Technology.L1_NPP_Prefetch ? 2 : 1 + }; + AppendWindow( + CreateBox(scan->key, origin, select, + (char*) RSC(BOX_CU_L1_NPP_TITLE).CODE(), + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL, + stateStr[1][RO(Shm)->Proc.Technology.L1_NPP_Prefetch], + stateAttr[RO(Shm)->Proc.Technology.L1_NPP_Prefetch], + BOXKEY_L1_NPP_PREFETCH_ON, + stateStr[0][!RO(Shm)->Proc.Technology.L1_NPP_Prefetch], + stateAttr[!RO(Shm)->Proc.Technology.L1_NPP_Prefetch], + BOXKEY_L1_NPP_PREFETCH_OFF, + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL), + &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case BOXKEY_L1_NPP_PREFETCH_OFF: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_TECHNOLOGY, + COREFREQ_TOGGLE_OFF, + TECHNOLOGY_L1_NPP_PREFETCH ); + } + break; + + case BOXKEY_L1_NPP_PREFETCH_ON: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_TECHNOLOGY, + COREFREQ_TOGGLE_ON, + TECHNOLOGY_L1_NPP_PREFETCH ); + } + break; + + case BOXKEY_L1_SCRUBBING: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + const Coordinate origin = { + .col = (Draw.Size.width - RSZ(BOX_BLANK_DESC)) / 2, + .row = TOP_HEADER_ROW + 4 + }, select = { + .col = 0, + .row = RO(Shm)->Proc.Technology.L1_Scrubbing ? 2 : 1 + }; + AppendWindow( + CreateBox(scan->key, origin, select, + (char*) RSC(BOX_L1_SCRUBBING_TITLE).CODE(), + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL, + stateStr[1][RO(Shm)->Proc.Technology.L1_Scrubbing], + stateAttr[RO(Shm)->Proc.Technology.L1_Scrubbing], + BOXKEY_L1_SCRUBBING_ON, + stateStr[0][!RO(Shm)->Proc.Technology.L1_Scrubbing], + stateAttr[!RO(Shm)->Proc.Technology.L1_Scrubbing], + BOXKEY_L1_SCRUBBING_OFF, + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL), + &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case BOXKEY_L1_SCRUBBING_OFF: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_TECHNOLOGY, + COREFREQ_TOGGLE_OFF, + TECHNOLOGY_L1_SCRUBBING ); + } + break; + + case BOXKEY_L1_SCRUBBING_ON: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_TECHNOLOGY, + COREFREQ_TOGGLE_ON, + TECHNOLOGY_L1_SCRUBBING ); + } + break; + + case BOXKEY_L2_HW_PREFETCH: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + const Coordinate origin = { + .col = (Draw.Size.width - RSZ(BOX_BLANK_DESC)) / 2, + .row = TOP_HEADER_ROW + 3 + }, select = { + .col = 0, + .row = RO(Shm)->Proc.Technology.L2_HW_Prefetch ? 2 : 1 + }; + AppendWindow( + CreateBox(scan->key, origin, select, + (char*) RSC(BOX_CU_L2_TITLE).CODE(), + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL, + stateStr[1][RO(Shm)->Proc.Technology.L2_HW_Prefetch], + stateAttr[RO(Shm)->Proc.Technology.L2_HW_Prefetch], + BOXKEY_L2_HW_PREFETCH_ON, + stateStr[0][!RO(Shm)->Proc.Technology.L2_HW_Prefetch], + stateAttr[!RO(Shm)->Proc.Technology.L2_HW_Prefetch], + BOXKEY_L2_HW_PREFETCH_OFF, + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL), + &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case BOXKEY_L2_HW_PREFETCH_OFF: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_TECHNOLOGY, + COREFREQ_TOGGLE_OFF, + TECHNOLOGY_L2_HW_PREFETCH ); + } + break; + + case BOXKEY_L2_HW_PREFETCH_ON: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_TECHNOLOGY, + COREFREQ_TOGGLE_ON, + TECHNOLOGY_L2_HW_PREFETCH ); + } + break; + + case BOXKEY_L2_HW_CL_PREFETCH: + { + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + const Coordinate origin = { + .col = (Draw.Size.width - RSZ(BOX_BLANK_DESC)) / 2, + .row = TOP_HEADER_ROW + 4 + }, select = { + .col = 0, + .row = RO(Shm)->Proc.Technology.L2_HW_CL_Prefetch ? 2 : 1 + }; + AppendWindow( + CreateBox(scan->key, origin, select, + (char*) RSC(BOX_CU_L2_CL_TITLE).CODE(), + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL, + stateStr[1][RO(Shm)->Proc.Technology.L2_HW_CL_Prefetch], + stateAttr[RO(Shm)->Proc.Technology.L2_HW_CL_Prefetch], + BOXKEY_L2_HW_CL_PREFETCH_ON, + stateStr[0][!RO(Shm)->Proc.Technology.L2_HW_CL_Prefetch], + stateAttr[!RO(Shm)->Proc.Technology.L2_HW_CL_Prefetch], + BOXKEY_L2_HW_CL_PREFETCH_OFF, + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL), + &winList); + } else { + SetHead(&winList, win); + } + } + break; + + case BOXKEY_L2_HW_CL_PREFETCH_OFF: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_TECHNOLOGY, + COREFREQ_TOGGLE_OFF, + TECHNOLOGY_L2_HW_CL_PREFETCH ); + } + break; + + case BOXKEY_L2_HW_CL_PREFETCH_ON: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_TECHNOLOGY, + COREFREQ_TOGGLE_ON, + TECHNOLOGY_L2_HW_CL_PREFETCH ); + } + break; + + case BOXKEY_L2_AMP_PREFETCH: { - Draw.Disposal = D_MAINVIEW; - Draw.View = V_ENERGY; - Draw.Size.height = 0; - TrapScreenSize(SIGWINCH); + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + const Coordinate origin = { + .col = (Draw.Size.width - RSZ(BOX_BLANK_DESC)) / 2, + .row = TOP_HEADER_ROW + 5 + }, select = { + .col = 0, + .row = RO(Shm)->Proc.Technology.L2_AMP_Prefetch ? 2 : 1 + }; + AppendWindow( + CreateBox(scan->key, origin, select, + (char*) RSC(BOX_L2_AMP_TITLE).CODE(), + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL, + stateStr[1][RO(Shm)->Proc.Technology.L2_AMP_Prefetch], + stateAttr[RO(Shm)->Proc.Technology.L2_AMP_Prefetch], + BOXKEY_L2_AMP_PREFETCH_ON, + stateStr[0][!RO(Shm)->Proc.Technology.L2_AMP_Prefetch], + stateAttr[!RO(Shm)->Proc.Technology.L2_AMP_Prefetch], + BOXKEY_L2_AMP_PREFETCH_OFF, + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL), + &winList); + } else { + SetHead(&winList, win); + } } break; - case SCANKEY_SHIFT_t: - { - Draw.Disposal = D_MAINVIEW; - Draw.View = V_SLICE; - Draw.Size.height = 0; - TrapScreenSize(SIGWINCH); - } + case BOXKEY_L2_AMP_PREFETCH_OFF: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_TECHNOLOGY, + COREFREQ_TOGGLE_OFF, + TECHNOLOGY_L2_AMP_PREFETCH ); + } break; - case SCANKEY_y: - { - Draw.Disposal = D_MAINVIEW; - Draw.View = V_CUSTOM; - Draw.Size.height = 0; - TrapScreenSize(SIGWINCH); - } + case BOXKEY_L2_AMP_PREFETCH_ON: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_TECHNOLOGY, + COREFREQ_TOGGLE_ON, + TECHNOLOGY_L2_AMP_PREFETCH ); + } break; -#endif /* NO_LOWER */ - case SCANKEY_s: + + case BOXKEY_L2_NLP_PREFETCH: { Window *win = SearchWinListById(scan->key, &winList); - if (win == NULL) { - AppendWindow(CreateSettings(scan->key), &winList); - } else { - SetHead(&winList, win); - } + if (win == NULL) + { + const Coordinate origin = { + .col = (Draw.Size.width - RSZ(BOX_BLANK_DESC)) / 2, + .row = TOP_HEADER_ROW + 3 + }, select = { + .col = 0, + .row = RO(Shm)->Proc.Technology.L2_NLP_Prefetch ? 2 : 1 + }; + AppendWindow( + CreateBox(scan->key, origin, select, + (char*) RSC(BOX_CU_L2_NLP_TITLE).CODE(), + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL, + stateStr[1][RO(Shm)->Proc.Technology.L2_NLP_Prefetch], + stateAttr[RO(Shm)->Proc.Technology.L2_NLP_Prefetch], + BOXKEY_L2_NLP_PREFETCH_ON, + stateStr[0][!RO(Shm)->Proc.Technology.L2_NLP_Prefetch], + stateAttr[!RO(Shm)->Proc.Technology.L2_NLP_Prefetch], + BOXKEY_L2_NLP_PREFETCH_OFF, + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL), + &winList); + } else { + SetHead(&winList, win); + } } break; - case SCANKEY_r: - if ((Draw.View == V_TASKS) && (Draw.Disposal == D_MAINVIEW)) { - RING_WRITE_SUB_CMD( TASK_INVERSING, - RW(Shm)->Ring[1], - COREFREQ_TASK_MONITORING ); + case BOXKEY_L2_NLP_PREFETCH_OFF: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_TECHNOLOGY, + COREFREQ_TOGGLE_OFF, + TECHNOLOGY_L2_NLP_PREFETCH ); } break; - case SCANKEY_v: - if ((Draw.View == V_TASKS) && (Draw.Disposal == D_MAINVIEW)) { - Draw.Flag.taskVal = !Draw.Flag.taskVal; - Draw.Flag.layout = 1; - } - break; -#ifndef NO_LOWER - case SCANKEY_x: - if (BITWISEAND(LOCKLESS, RO(Shm)->SysGate.Operation, 0x1)) { - Draw.Disposal = D_MAINVIEW; - Draw.View = V_TASKS; - Draw.Size.height = 0; - TrapScreenSize(SIGWINCH); - } - break; -#endif - case SCANKEY_EXCL: - if (Draw.Disposal == D_MAINVIEW) { - Draw.Load = !Draw.Load; - Draw.Flag.layout = 1; + case BOXKEY_L2_NLP_PREFETCH_ON: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_TECHNOLOGY, + COREFREQ_TOGGLE_ON, + TECHNOLOGY_L2_NLP_PREFETCH ); } break; - case SORTBY_STATE: + case BOXKEY_L1_STRIDE_PREFETCH: { - RING_WRITE_SUB_CMD( TASK_SORTING, - RW(Shm)->Ring[1], - COREFREQ_TASK_MONITORING, - F_STATE ); + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + const Coordinate origin = { + .col = (Draw.Size.width - RSZ(BOX_BLANK_DESC)) / 2, + .row = TOP_HEADER_ROW + 1 + }, select = { + .col = 0, + .row = RO(Shm)->Proc.Technology.L1_Stride_Pf ? 2 : 1 + }; + AppendWindow( + CreateBox(scan->key, origin, select, + (char*) RSC(BOX_L1_STRIDE_TITLE).CODE(), + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL, + stateStr[1][RO(Shm)->Proc.Technology.L1_Stride_Pf], + stateAttr[RO(Shm)->Proc.Technology.L1_Stride_Pf], + BOXKEY_L1_STRIDE_PF_ON, + stateStr[0][!RO(Shm)->Proc.Technology.L1_Stride_Pf], + stateAttr[!RO(Shm)->Proc.Technology.L1_Stride_Pf], + BOXKEY_L1_STRIDE_PF_OFF, + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL), + &winList); + } else { + SetHead(&winList, win); + } } break; - case SORTBY_RTIME: - { - RING_WRITE_SUB_CMD( TASK_SORTING, - RW(Shm)->Ring[1], - COREFREQ_TASK_MONITORING, - F_RTIME ); - } + case BOXKEY_L1_STRIDE_PF_OFF: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_TECHNOLOGY, + COREFREQ_TOGGLE_OFF, + TECHNOLOGY_L1_STRIDE_PREFETCH ); + } break; - case SORTBY_UTIME: - { - RING_WRITE_SUB_CMD( TASK_SORTING, - RW(Shm)->Ring[1], - COREFREQ_TASK_MONITORING, - F_UTIME ); - } + case BOXKEY_L1_STRIDE_PF_ON: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_TECHNOLOGY, + COREFREQ_TOGGLE_ON, + TECHNOLOGY_L1_STRIDE_PREFETCH ); + } break; - case SORTBY_STIME: + case BOXKEY_L1_REGION_PREFETCH: { - RING_WRITE_SUB_CMD( TASK_SORTING, - RW(Shm)->Ring[1], - COREFREQ_TASK_MONITORING, - F_STIME ); + Window *win = SearchWinListById(scan->key, &winList); + if (win == NULL) + { + const Coordinate origin = { + .col = (Draw.Size.width - RSZ(BOX_BLANK_DESC)) / 2, + .row = TOP_HEADER_ROW + 2 + }, select = { + .col = 0, + .row = RO(Shm)->Proc.Technology.L1_Region_Pf ? 2 : 1 + }; + AppendWindow( + CreateBox(scan->key, origin, select, + (char*) RSC(BOX_L1_REGION_TITLE).CODE(), + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL, + stateStr[1][RO(Shm)->Proc.Technology.L1_Region_Pf], + stateAttr[RO(Shm)->Proc.Technology.L1_Region_Pf], + BOXKEY_L1_REGION_PF_ON, + stateStr[0][!RO(Shm)->Proc.Technology.L1_Region_Pf], + stateAttr[!RO(Shm)->Proc.Technology.L1_Region_Pf], + BOXKEY_L1_REGION_PF_OFF, + RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL), + &winList); + } else { + SetHead(&winList, win); + } } break; - case SORTBY_PID: - { - RING_WRITE_SUB_CMD( TASK_SORTING, - RW(Shm)->Ring[1], - COREFREQ_TASK_MONITORING, - F_PID ); - } + case BOXKEY_L1_REGION_PF_OFF: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_TECHNOLOGY, + COREFREQ_TOGGLE_OFF, + TECHNOLOGY_L1_REGION_PREFETCH ); + } break; - case SORTBY_COMM: - { - RING_WRITE_SUB_CMD( TASK_SORTING, - RW(Shm)->Ring[1], - COREFREQ_TASK_MONITORING, - F_COMM ); - } + case BOXKEY_L1_REGION_PF_ON: + if (!RING_FULL(RW(Shm)->Ring[0])) { + RING_WRITE( RW(Shm)->Ring[0], + COREFREQ_IOCTL_TECHNOLOGY, + COREFREQ_TOGGLE_ON, + TECHNOLOGY_L1_REGION_PREFETCH ); + } break; - case BOXKEY_L1_HW_PREFETCH: + case BOXKEY_L1_BURST_PREFETCH: { Window *win = SearchWinListById(scan->key, &winList); if (win == NULL) { const Coordinate origin = { .col = (Draw.Size.width - RSZ(BOX_BLANK_DESC)) / 2, - .row = TOP_HEADER_ROW + 2 + .row = TOP_HEADER_ROW + 3 }, select = { .col = 0, - .row = RO(Shm)->Proc.Technology.L1_HW_Prefetch ? 2 : 1 + .row = RO(Shm)->Proc.Technology.L1_Burst_Pf ? 2 : 1 }; AppendWindow( CreateBox(scan->key, origin, select, - (char*) RSC(BOX_CU_L1_TITLE).CODE(), + (char*) RSC(BOX_L1_BURST_TITLE).CODE(), RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL, - stateStr[1][RO(Shm)->Proc.Technology.L1_HW_Prefetch], - stateAttr[RO(Shm)->Proc.Technology.L1_HW_Prefetch], - BOXKEY_L1_HW_PREFETCH_ON, - stateStr[0][!RO(Shm)->Proc.Technology.L1_HW_Prefetch], - stateAttr[!RO(Shm)->Proc.Technology.L1_HW_Prefetch], - BOXKEY_L1_HW_PREFETCH_OFF, + stateStr[1][RO(Shm)->Proc.Technology.L1_Burst_Pf], + stateAttr[RO(Shm)->Proc.Technology.L1_Burst_Pf], + BOXKEY_L1_BURST_PF_ON, + stateStr[0][!RO(Shm)->Proc.Technology.L1_Burst_Pf], + stateAttr[!RO(Shm)->Proc.Technology.L1_Burst_Pf], + BOXKEY_L1_BURST_PF_OFF, RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL), &winList); } else { @@ -13249,46 +14179,46 @@ int Shortcut(SCANKEY *scan) } break; - case BOXKEY_L1_HW_PREFETCH_OFF: + case BOXKEY_L1_BURST_PF_OFF: if (!RING_FULL(RW(Shm)->Ring[0])) { RING_WRITE( RW(Shm)->Ring[0], COREFREQ_IOCTL_TECHNOLOGY, COREFREQ_TOGGLE_OFF, - TECHNOLOGY_L1_HW_PREFETCH ); + TECHNOLOGY_L1_BURST_PREFETCH ); } break; - case BOXKEY_L1_HW_PREFETCH_ON: + case BOXKEY_L1_BURST_PF_ON: if (!RING_FULL(RW(Shm)->Ring[0])) { RING_WRITE( RW(Shm)->Ring[0], COREFREQ_IOCTL_TECHNOLOGY, COREFREQ_TOGGLE_ON, - TECHNOLOGY_L1_HW_PREFETCH ); + TECHNOLOGY_L1_BURST_PREFETCH ); } break; - case BOXKEY_L1_HW_IP_PREFETCH: + case BOXKEY_L2_STREAM_HW_PREFETCH: { Window *win = SearchWinListById(scan->key, &winList); if (win == NULL) { const Coordinate origin = { .col = (Draw.Size.width - RSZ(BOX_BLANK_DESC)) / 2, - .row = TOP_HEADER_ROW + 3 + .row = TOP_HEADER_ROW + 4 }, select = { .col = 0, - .row = RO(Shm)->Proc.Technology.L1_HW_IP_Prefetch ? 2 : 1 + .row = RO(Shm)->Proc.Technology.L2_Stream_HW_Pf ? 2 : 1 }; AppendWindow( CreateBox(scan->key, origin, select, - (char*) RSC(BOX_CU_L1_IP_TITLE).CODE(), + (char*) RSC(BOX_L2_STREAM_HW_TITLE).CODE(), RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL, - stateStr[1][RO(Shm)->Proc.Technology.L1_HW_IP_Prefetch], - stateAttr[RO(Shm)->Proc.Technology.L1_HW_IP_Prefetch], - BOXKEY_L1_HW_IP_PREFETCH_ON, - stateStr[0][!RO(Shm)->Proc.Technology.L1_HW_IP_Prefetch], - stateAttr[!RO(Shm)->Proc.Technology.L1_HW_IP_Prefetch], - BOXKEY_L1_HW_IP_PREFETCH_OFF, + stateStr[1][RO(Shm)->Proc.Technology.L2_Stream_HW_Pf], + stateAttr[RO(Shm)->Proc.Technology.L2_Stream_HW_Pf], + BOXKEY_L2_STREAM_HW_PF_ON, + stateStr[0][!RO(Shm)->Proc.Technology.L2_Stream_HW_Pf], + stateAttr[!RO(Shm)->Proc.Technology.L2_Stream_HW_Pf], + BOXKEY_L2_STREAM_HW_PF_OFF, RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL), &winList); } else { @@ -13297,46 +14227,46 @@ int Shortcut(SCANKEY *scan) } break; - case BOXKEY_L1_HW_IP_PREFETCH_OFF: + case BOXKEY_L2_STREAM_HW_PF_OFF: if (!RING_FULL(RW(Shm)->Ring[0])) { RING_WRITE( RW(Shm)->Ring[0], COREFREQ_IOCTL_TECHNOLOGY, COREFREQ_TOGGLE_OFF, - TECHNOLOGY_L1_HW_IP_PREFETCH ); + TECHNOLOGY_L2_STREAM_HW_PREFETCH ); } break; - case BOXKEY_L1_HW_IP_PREFETCH_ON: + case BOXKEY_L2_STREAM_HW_PF_ON: if (!RING_FULL(RW(Shm)->Ring[0])) { RING_WRITE( RW(Shm)->Ring[0], COREFREQ_IOCTL_TECHNOLOGY, COREFREQ_TOGGLE_ON, - TECHNOLOGY_L1_HW_IP_PREFETCH ); + TECHNOLOGY_L2_STREAM_HW_PREFETCH ); } break; - case BOXKEY_L2_HW_PREFETCH: + case BOXKEY_L2_UPDOWN_PREFETCH: { Window *win = SearchWinListById(scan->key, &winList); if (win == NULL) { const Coordinate origin = { .col = (Draw.Size.width - RSZ(BOX_BLANK_DESC)) / 2, - .row = TOP_HEADER_ROW + 3 + .row = TOP_HEADER_ROW + 5 }, select = { .col = 0, - .row = RO(Shm)->Proc.Technology.L2_HW_Prefetch ? 2 : 1 + .row = RO(Shm)->Proc.Technology.L2_UpDown_Pf ? 2 : 1 }; AppendWindow( CreateBox(scan->key, origin, select, - (char*) RSC(BOX_CU_L2_TITLE).CODE(), + (char*) RSC(BOX_L2_UPDOWN_TITLE).CODE(), RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL, - stateStr[1][RO(Shm)->Proc.Technology.L2_HW_Prefetch], - stateAttr[RO(Shm)->Proc.Technology.L2_HW_Prefetch], - BOXKEY_L2_HW_PREFETCH_ON, - stateStr[0][!RO(Shm)->Proc.Technology.L2_HW_Prefetch], - stateAttr[!RO(Shm)->Proc.Technology.L2_HW_Prefetch], - BOXKEY_L2_HW_PREFETCH_OFF, + stateStr[1][RO(Shm)->Proc.Technology.L2_UpDown_Pf], + stateAttr[RO(Shm)->Proc.Technology.L2_UpDown_Pf], + BOXKEY_L2_UPDOWN_PF_ON, + stateStr[0][!RO(Shm)->Proc.Technology.L2_UpDown_Pf], + stateAttr[!RO(Shm)->Proc.Technology.L2_UpDown_Pf], + BOXKEY_L2_UPDOWN_PF_OFF, RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL), &winList); } else { @@ -13345,46 +14275,46 @@ int Shortcut(SCANKEY *scan) } break; - case BOXKEY_L2_HW_PREFETCH_OFF: + case BOXKEY_L2_UPDOWN_PF_OFF: if (!RING_FULL(RW(Shm)->Ring[0])) { RING_WRITE( RW(Shm)->Ring[0], COREFREQ_IOCTL_TECHNOLOGY, COREFREQ_TOGGLE_OFF, - TECHNOLOGY_L2_HW_PREFETCH ); + TECHNOLOGY_L2_UPDOWN_PREFETCH ); } break; - case BOXKEY_L2_HW_PREFETCH_ON: + case BOXKEY_L2_UPDOWN_PF_ON: if (!RING_FULL(RW(Shm)->Ring[0])) { RING_WRITE( RW(Shm)->Ring[0], COREFREQ_IOCTL_TECHNOLOGY, COREFREQ_TOGGLE_ON, - TECHNOLOGY_L2_HW_PREFETCH ); + TECHNOLOGY_L2_UPDOWN_PREFETCH ); } break; - case BOXKEY_L2_HW_CL_PREFETCH: + case BOXKEY_LLC_STREAMER: { Window *win = SearchWinListById(scan->key, &winList); if (win == NULL) { const Coordinate origin = { .col = (Draw.Size.width - RSZ(BOX_BLANK_DESC)) / 2, - .row = TOP_HEADER_ROW + 4 + .row = TOP_HEADER_ROW + 3 }, select = { .col = 0, - .row = RO(Shm)->Proc.Technology.L2_HW_CL_Prefetch ? 2 : 1 + .row = RO(Shm)->Proc.Technology.LLC_Streamer ? 2 : 1 }; AppendWindow( CreateBox(scan->key, origin, select, - (char*) RSC(BOX_CU_L2_CL_TITLE).CODE(), + (char*) RSC(BOX_LLC_STREAMER_TITLE).CODE(), RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL, - stateStr[1][RO(Shm)->Proc.Technology.L2_HW_CL_Prefetch], - stateAttr[RO(Shm)->Proc.Technology.L2_HW_CL_Prefetch], - BOXKEY_L2_HW_CL_PREFETCH_ON, - stateStr[0][!RO(Shm)->Proc.Technology.L2_HW_CL_Prefetch], - stateAttr[!RO(Shm)->Proc.Technology.L2_HW_CL_Prefetch], - BOXKEY_L2_HW_CL_PREFETCH_OFF, + stateStr[1][RO(Shm)->Proc.Technology.LLC_Streamer], + stateAttr[RO(Shm)->Proc.Technology.LLC_Streamer], + BOXKEY_LLC_STREAMER_ON, + stateStr[0][!RO(Shm)->Proc.Technology.LLC_Streamer], + stateAttr[!RO(Shm)->Proc.Technology.LLC_Streamer], + BOXKEY_LLC_STREAMER_OFF, RSC(BOX_BLANK_DESC).CODE(), blankAttr, SCANKEY_NULL), &winList); } else { @@ -13393,21 +14323,21 @@ int Shortcut(SCANKEY *scan) } break; - case BOXKEY_L2_HW_CL_PREFETCH_OFF: + case BOXKEY_LLC_STREAMER_OFF: if (!RING_FULL(RW(Shm)->Ring[0])) { RING_WRITE( RW(Shm)->Ring[0], COREFREQ_IOCTL_TECHNOLOGY, COREFREQ_TOGGLE_OFF, - TECHNOLOGY_L2_HW_CL_PREFETCH ); + TECHNOLOGY_LLC_STREAMER ); } break; - case BOXKEY_L2_HW_CL_PREFETCH_ON: + case BOXKEY_LLC_STREAMER_ON: if (!RING_FULL(RW(Shm)->Ring[0])) { RING_WRITE( RW(Shm)->Ring[0], COREFREQ_IOCTL_TECHNOLOGY, COREFREQ_TOGGLE_ON, - TECHNOLOGY_L2_HW_CL_PREFETCH ); + TECHNOLOGY_LLC_STREAMER ); } break; @@ -21202,6 +22132,7 @@ int main(int argc, char *argv[]) { Window tty = {.matrix.size.wth = 4}; + AggregateRatio(); reason = SysInfoProc(NULL, 80, NULL, NULL); if (IS_REASON_SUCCESSFUL(reason) == 0) { break; } diff --git a/corefreq-cli.h b/x86_64/corefreq-cli.h similarity index 93% rename from corefreq-cli.h rename to x86_64/corefreq-cli.h index 7f2ab1ef..2dc03921 100644 --- a/corefreq-cli.h +++ b/x86_64/corefreq-cli.h @@ -1,6 +1,6 @@ /* * CoreFreq - * Copyright (C) 2015-2023 CYRIL COURTIAT + * Copyright (C) 2015-2024 CYRIL COURTIAT * Licenses: GPL2 */ @@ -257,6 +257,9 @@ enum KEY_ENUM { BOXKEY_L1_HW_IP_PREFETCH = 0x3000000000004210LLU, BOXKEY_L1_HW_IP_PREFETCH_OFF = 0x3000000000004211LLU, BOXKEY_L1_HW_IP_PREFETCH_ON = 0x3000000000004212LLU, + BOXKEY_L1_SCRUBBING = 0x3000000000004214LLU, + BOXKEY_L1_SCRUBBING_OFF = 0x3000000000004215LLU, + BOXKEY_L1_SCRUBBING_ON = 0x3000000000004216LLU, BOXKEY_L2_HW_PREFETCH = 0x3000000000004220LLU, BOXKEY_L2_HW_PREFETCH_OFF = 0x3000000000004221LLU, BOXKEY_L2_HW_PREFETCH_ON = 0x3000000000004222LLU, @@ -273,7 +276,33 @@ enum KEY_ENUM { BOXKEY_HSMP = 0x3000000000004410LLU, BOXKEY_HSMP_OFF = 0x3000000000004411LLU, BOXKEY_HSMP_ON = 0x3000000000004412LLU, - + BOXKEY_L2_AMP_PREFETCH = 0x3000000000004420LLU, + BOXKEY_L2_AMP_PREFETCH_OFF = 0x3000000000004421LLU, + BOXKEY_L2_AMP_PREFETCH_ON = 0x3000000000004422LLU, + BOXKEY_L1_STRIDE_PREFETCH = 0x3000000000004440LLU, + BOXKEY_L1_STRIDE_PF_OFF = 0x3000000000004441LLU, + BOXKEY_L1_STRIDE_PF_ON = 0x3000000000004442LLU, + BOXKEY_L1_REGION_PREFETCH = 0x3000000000004480LLU, + BOXKEY_L1_REGION_PF_OFF = 0x3000000000004481LLU, + BOXKEY_L1_REGION_PF_ON = 0x3000000000004482LLU, + BOXKEY_L1_BURST_PREFETCH = 0x3000000000004800LLU, + BOXKEY_L1_BURST_PF_OFF = 0x3000000000004801LLU, + BOXKEY_L1_BURST_PF_ON = 0x3000000000004802LLU, + BOXKEY_L1_NPP_PREFETCH = 0x3000000000004810LLU, + BOXKEY_L1_NPP_PREFETCH_OFF = 0x3000000000004811LLU, + BOXKEY_L1_NPP_PREFETCH_ON = 0x3000000000004812LLU, + BOXKEY_L2_STREAM_HW_PREFETCH = 0x3000000000004820LLU, + BOXKEY_L2_STREAM_HW_PF_OFF = 0x3000000000004821LLU, + BOXKEY_L2_STREAM_HW_PF_ON = 0x3000000000004822LLU, + BOXKEY_L2_UPDOWN_PREFETCH = 0x3000000000004840LLU, + BOXKEY_L2_UPDOWN_PF_OFF = 0x3000000000004841LLU, + BOXKEY_L2_UPDOWN_PF_ON = 0x3000000000004842LLU, + BOXKEY_L2_NLP_PREFETCH = 0x3000000000004880LLU, + BOXKEY_L2_NLP_PREFETCH_OFF = 0x3000000000004881LLU, + BOXKEY_L2_NLP_PREFETCH_ON = 0x3000000000004882LLU, + BOXKEY_LLC_STREAMER = 0x3000000000004120LLU, + BOXKEY_LLC_STREAMER_OFF = 0x3000000000004121LLU, + BOXKEY_LLC_STREAMER_ON = 0x3000000000004122LLU, BOXKEY_TOOLS_MACHINE = 0x3000000000010000LLU, BOXKEY_TOOLS_ATOMIC = 0x3000000000010010LLU, BOXKEY_TOOLS_CRC32 = 0x3000000000010020LLU, @@ -641,12 +670,42 @@ int CheckDuplicateKey(void) \ case BOXKEY_L1_HW_IP_PREFETCH: \ case BOXKEY_L1_HW_IP_PREFETCH_OFF: \ case BOXKEY_L1_HW_IP_PREFETCH_ON: \ + case BOXKEY_L1_SCRUBBING: \ + case BOXKEY_L1_SCRUBBING_OFF: \ + case BOXKEY_L1_SCRUBBING_ON: \ case BOXKEY_L2_HW_PREFETCH: \ case BOXKEY_L2_HW_PREFETCH_OFF: \ case BOXKEY_L2_HW_PREFETCH_ON: \ case BOXKEY_L2_HW_CL_PREFETCH: \ case BOXKEY_L2_HW_CL_PREFETCH_OFF: \ case BOXKEY_L2_HW_CL_PREFETCH_ON: \ + case BOXKEY_L2_AMP_PREFETCH: \ + case BOXKEY_L2_AMP_PREFETCH_OFF: \ + case BOXKEY_L2_AMP_PREFETCH_ON: \ + case BOXKEY_L1_STRIDE_PREFETCH: \ + case BOXKEY_L1_STRIDE_PF_OFF: \ + case BOXKEY_L1_STRIDE_PF_ON: \ + case BOXKEY_L1_REGION_PREFETCH: \ + case BOXKEY_L1_REGION_PF_OFF: \ + case BOXKEY_L1_REGION_PF_ON: \ + case BOXKEY_L1_BURST_PREFETCH: \ + case BOXKEY_L1_BURST_PF_OFF: \ + case BOXKEY_L1_BURST_PF_ON: \ + case BOXKEY_L1_NPP_PREFETCH: \ + case BOXKEY_L1_NPP_PREFETCH_OFF: \ + case BOXKEY_L1_NPP_PREFETCH_ON: \ + case BOXKEY_L2_STREAM_HW_PREFETCH: \ + case BOXKEY_L2_STREAM_HW_PF_OFF: \ + case BOXKEY_L2_STREAM_HW_PF_ON: \ + case BOXKEY_L2_UPDOWN_PREFETCH: \ + case BOXKEY_L2_UPDOWN_PF_OFF: \ + case BOXKEY_L2_UPDOWN_PF_ON: \ + case BOXKEY_L2_NLP_PREFETCH: \ + case BOXKEY_L2_NLP_PREFETCH_OFF: \ + case BOXKEY_L2_NLP_PREFETCH_ON: \ + case BOXKEY_LLC_STREAMER: \ + case BOXKEY_LLC_STREAMER_OFF: \ + case BOXKEY_LLC_STREAMER_ON: \ case BOXKEY_CFG_TDP_LVL: \ case BOXKEY_CFG_TDP_LVL0: \ case BOXKEY_CFG_TDP_LVL1: \ diff --git a/x86_64/corefreq-ui.c b/x86_64/corefreq-ui.c new file mode 100644 index 00000000..34e40c03 --- /dev/null +++ b/x86_64/corefreq-ui.c @@ -0,0 +1,2342 @@ +/* + * CoreFreq + * Copyright (C) 2015-2024 CYRIL COURTIAT + * Licenses: GPL2 + */ + +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "bitasm.h" +#include "coretypes.h" +#include "corefreq-ui.h" +#include "corefreq-cli-rsc.h" + +const char LCD[0x6][0x10][3][3] = { + { + {/* 0x20 */ + " ", + " ", + " " + }, + {/* 0x21 */ + " | ", + " | ", + " o " + }, + {/* 0x22 */ + "|| ", + " ", + " " + }, + {/* 0x23 */ + " //", + "=/=", + "// " + }, + {/* 0x24 */ + " _ ", + "(|`", + "_) " + }, + {/* 0x25 */ + " ", + "O/ ", + "/O " + }, + {/* 0x26 */ + "_ ", + "\\' ", + "(\\ " + }, + {/* 0x27 */ + " | ", + " ", + " " + }, + {/* 0x28 */ + " / ", + "| ", + " \\ " + }, + {/* 0x29 */ + " \\ ", + " |", + " / " + }, + {/* 0x2a */ + " ", + "\\|/", + "/|\\" + }, + {/* 0x2b */ + " ", + "_|_", + " | " + }, + {/* 0x2c */ + " ", + " ", + " / " + }, + {/* 0x2d */ + " ", + "___", + " " + }, + {/* 0x2e */ + " ", + " ", + " o " + }, + {/* 0x2f */ + " /", + " / ", + "/ " + } + },{ + {/* 0x30 */ + " _ ", + "| |", + "|_|" + }, + {/* 0x31 */ + " ", + " | ", + " | " + }, + {/* 0x32 */ + " _ ", + " _|", + "|_ " + }, + {/* 0x33 */ + " _ ", + " _|", + " _|" + }, + {/* 0x34 */ + " ", + "|_|", + " |" + }, + {/* 0x35 */ + " _ ", + "|_ ", + " _|" + }, + {/* 0x36 */ + " _ ", + "|_ ", + "|_|" + }, + {/* 0x37 */ + " _ ", + " |", + " |" + }, + {/* 0x38 */ + " _ ", + "|_|", + "|_|" + }, + {/* 0x39 */ + " _ ", + "|_|", + " _|" + }, + {/* 0x3a */ + " ", + " o ", + " o " + }, + {/* 0x3b */ + " ", + " o ", + "/ " + }, + {/* 0x3c */ + " / ", + "< ", + " \\ " + }, + {/* 0x3d */ + "___", + "___", + " " + }, + {/* 0x3e */ + " \\ ", + " >", + " / " + }, + {/* 0x3f */ + " _ ", + "'_)", + " ! " + } + },{ + {/* 0x40 */ + " _ ", + "(()", + " ``" + }, + {/* 0x41 */ + " _ ", + "|_|", + "| |" + }, + {/* 0x42 */ + "__ ", + "[_)", + "[_)" + }, + {/* 0x43 */ + " _ ", + "| ", + "|_ " + }, + {/* 0x44 */ + "__ ", + "| |", + "|_|" + }, + {/* 0x45 */ + " _ ", + "|_ ", + "|_ " + }, + {/* 0x46 */ + " __", + "|- ", + "| " + }, + {/* 0x47 */ + " _ ", + "| ", + "|_]" + }, + {/* 0x48 */ + " ", + "|_|", + "| |" + }, + {/* 0x49 */ + " . ", + " | ", + " | " + }, + {/* 0x4a */ + " . ", + " | ", + "_| " + }, + {/* 0x4b */ + " ", + "|/ ", + "|\\ " + }, + {/* 0x4c */ + " ", + "| ", + "|_ " + }, + {/* 0x4d */ + " ", + "|||", + "| |" + }, + {/* 0x4e */ + " ", + "|\\|", + "| |" + }, + {/* 0x4f */ + " _.", + "| |", + "|_|" + } + },{ + {/* 0x50 */ + " _ ", + "|_|", + "| " + }, + {/* 0x51 */ + " _ ", + "|\\|", + "|_!" + }, + {/* 0x52 */ + " _ ", + "|_|", + "| \\" + }, + {/* 0x53 */ + " _ ", + "( ", + "_) " + }, + {/* 0x54 */ + "___", + " | ", + " | " + }, + {/* 0x55 */ + " ", + "| |", + "|_|" + }, + {/* 0x56 */ + " ", + "\\ /", + " v " + }, + {/* 0x57 */ + " ", + "| |", + "!^!" + }, + {/* 0x58 */ + " ", + "\\/ ", + "/\\ " + }, + {/* 0x59 */ + " ", + "\\ /", + " | " + }, + {/* 0x5a */ + "__ ", + " / ", + "/_ " + }, + {/* 0x5b */ + " _", + " | ", + " |_" + }, + {/* 0x5c */ + "\\ ", + " \\ ", + " \\" + }, + {/* 0x5d */ + "_ ", + " | ", + "_| " + }, + {/* 0x5e */ + "/\\ ", + " ", + " " + }, + {/* 0x5f */ + " ", + " ", + "___" + } + },{ + {/* 0x60 */ + " \\ ", + " ", + " " + }, + {/* 0x61 */ + " ", + " _ ", + "(_(" + }, + {/* 0x62 */ + " ", + "|_ ", + "|_)" + }, + {/* 0x63 */ + " ", + " _ ", + "(_ " + }, + {/* 0x64 */ + " ", + " _|", + "(_|" + }, + {/* 0x65 */ + " ", + " _ ", + "(-'" + }, + {/* 0x66 */ + " ", + ",- ", + "|' " + }, + {/* 0x67 */ + " ", + ",- ", + "|] " + }, + {/* 0x68 */ + " ", + "|_ ", + "| |" + }, + {/* 0x69 */ + " ", + " . ", + " | " + }, + {/* 0x6a */ + " ", + " . ", + " ] " + }, + {/* 0x6b */ + " ", + "., ", + "|\\ " + }, + {/* 0x6c */ + " ", + "| ", + "|_ " + }, + {/* 0x6d */ + " ", + " ", + "|'|" + }, + {/* 0x6e */ + " ", + " ", + "|\\|" + }, + {/* 0x6f */ + " ", + " _ ", + "|_|" + } + },{ + {/* 0x70 */ + " ", + " _ ", + "|-'" + }, + {/* 0x71 */ + " ", + " _ ", + "|_!" + }, + {/* 0x72 */ + " ", + " _ ", + "|\\'" + }, + {/* 0x73 */ + " ", + " _ ", + "_) " + }, + {/* 0x74 */ + " ", + ":_ ", + "| " + }, + {/* 0x75 */ + " ", + " ", + "|_|" + }, + {/* 0x76 */ + " ", + " ", + "\\/ " + }, + {/* 0x77 */ + " ", + " ", + "V^V" + }, + {/* 0x78 */ + " ", + " ", + ">< " + }, + {/* 0x79 */ + " ", + " ", + "`/ " + }, + {/* 0x7a */ + " ", + "_ ", + "/_ " + }, + {/* 0x7b */ + " _", + "_| ", + " |_" + }, + {/* 0x7c */ + " | ", + " | ", + " | " + }, + {/* 0x7d */ + "_ ", + " |_", + "_| " + }, + {/* 0x7e */ + " ", + " ", + " ~ " + }, + {/* 0x7f */ + " ", + ".^.", + "DEL" + } + } +}; + +ASCII hSpace[] = HSPACE, + hBar[] = HBAR, + hLine[] = HLINE; + +Layer *sLayer = NULL, + *dLayer = NULL, + *wLayer = NULL, + *Fuse = NULL; + +StockList stockList = {.head = NULL, .tail = NULL}; + +WinList winList = {.head = NULL}; + +void *StreamBuf = NULL; +char *Console = NULL; + +enum LOCALES AppLoc = LOC_EN; +locale_t SysLoc = (locale_t) 0; + +typedef char I18N[5]; + +I18N i18n_FR[] = { + "fr_FR", + "br_FR", + "fr_BE", + "fr_CA", + "fr_CH", + "fr_LU", + "ca_FR", + "ia_FR", + "oc_FR", + {0,0,0,0,0} +}; + +struct LOCALE_LOOKUP { + enum LOCALES apploc; + I18N *i18n; +} LocaleLookUp[] = { + { + .apploc = LOC_FR, + .i18n = i18n_FR + }, + { + .apploc = LOC_EN, + .i18n = NULL + } +}; + +enum THEMES AppThm = THM_DFLT; + +struct termios oldt, newt; + +struct { + union { + Bit64 Reset __attribute__ ((aligned (8))); + struct { + Bit32 Status; + int Tick; + }; + }; + time_t StartedAt; + FILE *Handle; + char *Buffer; + void (*Header)(void); + void (*Write)(char*, int); + void (*Break)(void); +} Dump __attribute__ ((aligned (8))) = { + .StartedAt = 0, + .Reset = 0x0, + .Handle = NULL, + .Buffer = NULL, + .Header = JSON_Header, + .Write = JSON_Page, + .Break = JSON_Break +}; + +int GetKey(SCANKEY *scan, struct timespec *tsec) +{ + struct pollfd fds = {.fd = STDIN_FILENO, .events = POLLIN}; + register int rp, rz; + + if ((rp = ppoll(&fds, 1, tsec, NULL)) > 0) { + if (fds.revents & POLLIN) { + ssize_t lc = read(STDIN_FILENO, &scan->key, 8); + for (rz = lc; rz < 8; rz++) + scan->code[rz] = 0; + } + } + return rp; +} + +SCREEN_SIZE GetScreenSize(void) +{ + SCREEN_SIZE _screenSize = {.width = 0, .height = 0}; + struct winsize ts; + + ioctl(STDIN_FILENO, TIOCGWINSZ, &ts); + _screenSize.width = (int) ts.ws_col; + _screenSize.height = (int) ts.ws_row; + + return _screenSize; +} + +TGrid *GridHover(TGrid *pGrid, const char *comment) +{ + if ((pGrid != NULL) && (comment != NULL)) + { + size_t length = strlen(comment); + if (length > 0) + { + ASCII *comm = malloc(1 + length); + if (comm != NULL) + { + StrCopy(comm, comment, (1 + length)); + pGrid->hover.comm = comm; + pGrid->hover.length = length; + } + } + } + return pGrid; +} + +__inline__ +void Set_Data(TGrid *pGrid, DATA_TYPE data, unsigned int order) +{ + pGrid->data[order] = data; +} + +__inline__ +void Set_pVOID(TGrid *pGrid, void *pVOID, unsigned int order) +{ + pGrid->data[order].pvoid = pVOID; +} + +__inline__ +void Set_pULLONG(TGrid *pGrid, unsigned long long *pULLONG, unsigned int order) +{ + pGrid->data[order].pullong = pULLONG; +} + +__inline__ +void Set_pSLLONG(TGrid *pGrid, signed long long *pSLLONG, unsigned int order) +{ + pGrid->data[order].psllong = pSLLONG; +} + +__inline__ +void Set_pULONG(TGrid *pGrid, unsigned long *pULONG, unsigned int order) +{ + pGrid->data[order].pulong = pULONG; +} + +__inline__ +void Set_pSLONG(TGrid *pGrid, signed long *pSLONG, unsigned int order) +{ + pGrid->data[order].pslong = pSLONG; +} + +__inline__ +void Set_pUINT(TGrid *pGrid, unsigned int *pUINT, unsigned int order) +{ + pGrid->data[order].puint = pUINT; +} + +__inline__ +void Set_pSINT(TGrid *pGrid, signed int *pSINT, unsigned int order) +{ + pGrid->data[order].psint = pSINT; +} + +__inline__ +void Set_ULLONG(TGrid *pGrid, unsigned long long _ULLONG, unsigned int order) +{ + pGrid->data[order].ullong = _ULLONG; +} + +__inline__ +void Set_SLLONG(TGrid *pGrid, signed long long _SLLONG, unsigned int order) +{ + pGrid->data[order].sllong = _SLLONG; +} + +__inline__ +void Set_ULONG(TGrid *pGrid, unsigned long _ULONG, unsigned int order) +{ + pGrid->data[order].ulong = _ULONG; +} + +__inline__ +void Set_SLONG(TGrid *pGrid, signed long _SLONG, unsigned int order) +{ + pGrid->data[order].slong = _SLONG; +} + +__inline__ +void Set_UINT(TGrid *pGrid, unsigned int _UINT, unsigned int order) +{ + pGrid->data[order].uint[0] = _UINT; + pGrid->data[order].uint[1] = 0; +} + +__inline__ +void Set_SINT(TGrid *pGrid, signed int _SINT, unsigned int order) +{ + pGrid->data[order].sint[0] = _SINT; + pGrid->data[order].sint[1] = 0; +} + +void HookCellFunc(TCELLFUNC *with, TCELLFUNC what) { *with=what; } + +void HookKeyFunc(KEYFUNC *with, KEYFUNC what) { *with=what; } + +void HookWinFunc(WINFUNC *with, WINFUNC what) { *with=what; } + +void HookAttrib(ATTRIBUTE *with, ATTRIBUTE what) { with->value=what.value; } + +void HookString(REGSTR *with, REGSTR what) { strcpy(*with, what); } + +void HookPointer(REGPTR *with, REGPTR what) +{ + if ((*with = realloc(*with, 1 + strlen(what))) != NULL) { + strcpy(*with, what); + } +} + +void DestroyLayer(Layer *layer) +{ + if (layer != NULL) { + if (layer->attr != NULL) { + free(layer->attr); + layer->attr = NULL; + } + if (layer->code != NULL) { + free(layer->code); + layer->code = NULL; + } + } +} + +void CreateLayer(Layer *layer, CoordSize size) +{ + if (layer != NULL) { + layer->size.wth = size.wth; + layer->size.hth = size.hth; + size_t len = layer->size.wth * layer->size.hth; + + layer->attr = calloc(len, sizeof(ATTRIBUTE)); + layer->code = calloc(len, sizeof(ASCII)); + } +} + +void FillLayerArea(Layer *layer,CUINT col, CUINT row, + CUINT width, CUINT height, + ASCII *source, ATTRIBUTE attrib) +{ + CUINT _row; + for (_row = row; _row < row + height; _row++) { + LayerFillAt(layer, col, _row, width, source, attrib); + } +} + +void AllocCopyAttr(TCell *cell, ATTRIBUTE attrib[]) +{ + if ((attrib != NULL) && (cell->attr = malloc(cell->length)) != NULL) { + memcpy(&cell->attr->value, &attrib->value, cell->length); + } +} + +void AllocFillAttr(TCell *cell, ATTRIBUTE attrib) +{ + if ((cell->attr = malloc(cell->length)) != NULL) { + memset(&cell->attr->value, attrib.value, cell->length); + } +} + +void AllocCopyItem(TCell *cell, ASCII *item) +{ + if ((cell->item = malloc(cell->length)) != NULL) { + strncpy((char *)cell->item, (char *)item, cell->length); + } +} + +void FreeAllTCells(Window *win) +{ + if (win->grid != NULL) { + CUINT i; + for (i = 0; i < win->dim; i++) + { + free(win->grid[i].cell.attr); + free(win->grid[i].cell.item); + + if (win->grid[i].hover.comm != NULL) { + free(win->grid[i].hover.comm); + } + } + free(win->grid); + win->grid = NULL; + } +} + +Stock *CreateStock(unsigned long long id, Coordinate origin) +{ + Stock *stock = malloc(sizeof(Stock)); + if (stock != NULL) { + GetNext(stock) = NULL; + stock->id = id; + stock->geometry.origin = origin; + } + return stock; +} + +Stock *AppendStock(Stock *stock) +{ + if (stock != NULL) { + if (stockList.head == NULL) { + stockList.head = stockList.tail = stock; + } else { + GetNext(stockList.tail) = stock; + stockList.tail = stock; + } + } + return stock; +} + +void DestroyFullStock(void) +{ + Stock *stock = stockList.head; + while (stock != NULL) { + Stock *_next = GetNext(stock); + free(stock); + stock = _next; + } + stockList.head = stockList.tail = NULL; +} + +Stock *SearchStockById(unsigned long long id) +{ + Stock *walker = stockList.head; + while (walker != NULL) { + if (walker->id == id) { + break; + } + walker = GetNext(walker); + } + return walker; +} + +#define ComputeLazyBottomRow(_win, withBorder) \ +({ \ + if (_win->lazyComp.rowLen == 0) \ + { \ + CUINT _col; \ + for ( _col = 0, _win->lazyComp.rowLen = 2 * withBorder; \ + _col < _win->matrix.size.wth; \ + _col++ ) \ + { \ + _win->lazyComp.rowLen += TCellAt(_win, _col, 0).length; \ + } \ + } \ +}) + +CSINT LazyCompBottomRow(Window *win) +{ + if ((win->dim > 0) && win->matrix.size.wth) { + return (win->dim / win->matrix.size.wth) - win->matrix.size.hth; + } else { + return 1; + } +} + +void DestroyWindow(Window *win) +{ + if (win != NULL) { + if (!(win->flag & WINFLAG_NO_STOCK)) { + if (win->stock == NULL) + { + win->stock=AppendStock(CreateStock(win->id,win->matrix.origin)); + } else { + win->stock->geometry.origin = win->matrix.origin; + } + } + if (win->hook.title != NULL) { + free(win->hook.title); + win->hook.title = NULL; + win->lazyComp.titleLen = 0; + } + FreeAllTCells(win); + free(win); + win = NULL; + } +} + +Window *_CreateWindow( Layer *layer, unsigned long long id, + CUINT width, CUINT height, + CUINT oCol, CUINT oRow, WINDOW_FLAG flag ) +{ + ATTRIBUTE select[2] = { + MAKE_SELECT_UNFOCUS, + MAKE_SELECT_FOCUS + }, + border[2] = { + MAKE_BORDER_UNFOCUS, + MAKE_BORDER_FOCUS + }, + title[2] = { + MAKE_TITLE_UNFOCUS, + MAKE_TITLE_FOCUS + }; + unsigned int idx; + + Window *win = calloc(1, sizeof(Window)); + if (win != NULL) { + win->layer = layer; + win->id = id; + + win->matrix.size.wth = width; + win->matrix.size.hth = height; + + win->flag = flag; + if (win->flag & WINFLAG_NO_STOCK) + { + win->matrix.origin.col = oCol; + win->matrix.origin.row = oRow; + } else { + if ((win->stock = SearchStockById(win->id)) != NULL) { + win->matrix.origin = win->stock->geometry.origin; + } else { + win->matrix.origin.col = oCol; + win->matrix.origin.row = oRow; + } + } + for (idx = 0; idx < 2; idx++) { + win->hook.color[idx].select = select[idx]; + win->hook.color[idx].border = border[idx]; + win->hook.color[idx].title = title[idx]; + } + } + return win; +} + +Window *CreateWindow_7xArg( Layer *layer, unsigned long long id, + CUINT width, CUINT height, + CUINT oCol, CUINT oRow, WINDOW_FLAG flag ) +{ + return _CreateWindow(layer, id, width, height, oCol, oRow, flag); +} + +Window *CreateWindow_6xArg( Layer *layer, unsigned long long id, + CUINT width, CUINT height, + CUINT oCol, CUINT oRow ) +{ + return _CreateWindow(layer, id, width, height, oCol, oRow, + WINFLAG_NO_FLAGS); +} + +void RemoveWindow(Window *win, WinList *list) +{ + RemoveWinList(win, list); + + if (IsCycling(GetHead(list))) { + SetDead(list); + } else if (IsHead(list, win)) { + /*Auto shift*/ SetHead(list, GetPrev(win)); + } + DestroyWindow(win); +} + +void AppendWindow(Window *win, WinList *list) +{ + if (win != NULL) { + if (!IsDead(list)) + AppendWinList(win, list); + else { + /* Dead head, now cycling */ + GetPrev(win) = win; + GetNext(win) = win; + } + SetHead(list, win); + } +} + +void DestroyAllWindows(WinList *list) +{ + while (!IsDead(list)) { + RemoveWindow(GetHead(list), list); + } +} + +void AnimateWindow(int rotate, WinList *list) +{ + if (!IsDead(list)) { + SetHead( list, rotate == 1 ? GetNext(GetHead(list)) + : GetPrev(GetHead(list)) ); + } +} + +Window *SearchWinListById(unsigned long long id, WinList *list) +{ + Window *win = NULL; + if (!IsDead(list)) { + Window *walker = GetHead(list); + do { + if (walker->id == id) + win = walker; + + walker = GetPrev(walker); + } while (!IsHead(list, walker) && (win == NULL)); + } + return win; +} + +void PrintContent(Window *win, WinList *list, CUINT col, CUINT row) +{ + CUINT horzCol = win->matrix.scroll.horz + col, + vertRow = win->matrix.scroll.vert + row; + + if ((win->matrix.select.col == col) + && (win->matrix.select.row == row)) { + LayerFillAt(win->layer, + (win->matrix.origin.col + + (col * TCellAt(win, horzCol, vertRow).length)), + (win->matrix.origin.row + row), + TCellAt(win, horzCol, vertRow).length, + TCellAt(win, horzCol, vertRow).item, + win->hook.color[(GetFocus(list) == win)].select); + } else if (GetFocus(list) == win) { + LayerCopyAt(win->layer, + (win->matrix.origin.col + + (col * TCellAt(win, horzCol, vertRow).length)), + (win->matrix.origin.row + row), + TCellAt(win, horzCol, vertRow).length, + TCellAt(win, horzCol, vertRow).attr, + TCellAt(win, horzCol, vertRow).item); + } else { + LayerFillAt(win->layer, + (win->matrix.origin.col + + (col * TCellAt(win, horzCol, vertRow).length)), + (win->matrix.origin.row + row), + TCellAt(win, horzCol, vertRow).length, + TCellAt(win, horzCol, vertRow).item, + win->hook.color[0].select); + } +} + +void PrintComment(Window *win) +{ /* The cell comment is positioned at the bottom border center */ + CUINT horzCol = win->matrix.scroll.horz + win->matrix.select.col, + vertRow = win->matrix.scroll.vert + win->matrix.select.row; + + if (TGridAt(win, horzCol, vertRow).hover.comm != NULL) + { + size_t pos; + pos = win->lazyComp.rowLen - TGridAt(win,horzCol,vertRow).hover.length; + pos = pos >> 1; + pos = pos + (1 & TGridAt(win, horzCol, vertRow).hover.length); + + memcpy(&LayerAt(win->layer, code, + (win->matrix.origin.col + pos), + (win->matrix.origin.row + win->matrix.size.hth)), + TGridAt(win, horzCol, vertRow).hover.comm, + TGridAt(win, horzCol, vertRow).hover.length); + } +} + +void ForEachCellPrint(Window *win, WinList *list) +{ + CUINT col, row; + ATTRIBUTE border = win->hook.color[(GetFocus(list) == win)].border; + + /* Top, Left Border Corner */ + LayerAt(win->layer, attr, + (win->matrix.origin.col - 1), + (win->matrix.origin.row - 1)) = border; + + LayerAt(win->layer, code, + (win->matrix.origin.col - 1), + (win->matrix.origin.row - 1)) = 0x20; + /* Top Border Line */ + if (win->hook.title == NULL) { + LayerFillAt( win->layer, + win->matrix.origin.col, + (win->matrix.origin.row - 1), + (win->lazyComp.rowLen - 2), hLine, border ); + } else { + if (win->lazyComp.titleLen == 0) { + win->lazyComp.titleLen = strlen(win->hook.title); + } + size_t halfLeft=(win->lazyComp.rowLen - win->lazyComp.titleLen) / 2; + size_t halfRight = halfLeft + + (win->lazyComp.rowLen - win->lazyComp.titleLen) % 2; + /* Top, Half-Left Border Line */ + LayerFillAt( win->layer, + win->matrix.origin.col, + (win->matrix.origin.row - 1), + halfLeft, hLine, border ); + /* Top, Centered Border Title */ + LayerFillAt( win->layer, + (halfLeft + (win->matrix.origin.col - 1)), + (win->matrix.origin.row - 1), + win->lazyComp.titleLen, win->hook.title, + ((GetFocus(list) == win) ? + win->hook.color[1].title + : win->hook.color[0].title) ); + /* Top, Half-Right Border Line */ + LayerFillAt( win->layer, + (halfLeft + win->lazyComp.titleLen + + (win->matrix.origin.col - 1)), + (win->matrix.origin.row - 1), + (halfRight - 1), hLine, border ); + } + /* Top, Right Border Corner */ + LayerAt(win->layer, attr, + (win->matrix.origin.col + win->lazyComp.rowLen - 2), + (win->matrix.origin.row - 1)) = border; + + LayerAt(win->layer, code, + (win->matrix.origin.col + win->lazyComp.rowLen - 2), + (win->matrix.origin.row - 1)) = 0x20; + + for (row = 0; row < win->matrix.size.hth; row++) { + /* Left Side Border Column */ + LayerAt(win->layer, attr, + (win->matrix.origin.col - 1), + (win->matrix.origin.row + row)) = border; + LayerAt(win->layer, code, + (win->matrix.origin.col - 1), + (win->matrix.origin.row + row)) = 0x20; + + for (col = 0; col < win->matrix.size.wth; col++) { + PrintContent(win, list, col, row); + } + /* Right Side Border Column */ + LayerAt(win->layer, attr, + (win->matrix.origin.col + + col * TCellAt(win, 0, 0).length), + (win->matrix.origin.row + row)) = border; + LayerAt(win->layer, code, + (win->matrix.origin.col + + col * TCellAt(win, 0, 0).length), + (win->matrix.origin.row + row)) = 0x20; + } + /* Bottom, Left Border Corner */ + LayerAt(win->layer, attr, + (win->matrix.origin.col - 1), + (win->matrix.origin.row + win->matrix.size.hth)) = border; + + LayerAt(win->layer, code, + (win->matrix.origin.col - 1), + (win->matrix.origin.row + win->matrix.size.hth)) = 0x20; + /* Bottom Border Line */ + LayerFillAt(win->layer, + win->matrix.origin.col, + (win->matrix.origin.row + win->matrix.size.hth), + (win->lazyComp.rowLen - 2), hLine, border); + /* Bottom, Right Border Corner */ + LayerAt(win->layer, attr, + (win->matrix.origin.col + win->lazyComp.rowLen - 2), + (win->matrix.origin.row + win->matrix.size.hth)) = border; + + LayerAt(win->layer, code, + (win->matrix.origin.col + win->lazyComp.rowLen - 2), + (win->matrix.origin.row + win->matrix.size.hth)) = 0x20; + /* Vertical Scrolling Bar */ + if (!(win->flag & WINFLAG_NO_VSB)) { + if (win->dim / win->matrix.size.wth > win->matrix.size.hth) + { + CUINT vScrollbar = win->matrix.origin.row + + (win->matrix.size.hth - 1) + * win->matrix.scroll.vert + / LazyCompBottomRow(win); + + ATTRIBUTE attrBar=GetFocus(list) == win ? MAKE_TITLE_FOCUS + : border; + + LayerAt(win->layer, attr, + (win->matrix.origin.col + win->lazyComp.rowLen - 2), + vScrollbar) = attrBar; + + LayerAt(win->layer, code, + (win->matrix.origin.col + win->lazyComp.rowLen - 2), + vScrollbar) = '='; + } + } +} + +void EraseWindowWithBorder(Window *win) +{ /* Care about the four window side borders. */ + CUINT row; + for (row = 0; row < win->matrix.size.hth + 2; row++) { + Coordinate origin = { + .col = win->matrix.origin.col - 1, + .row = (win->matrix.origin.row + - !(win->flag & WINFLAG_NO_BORDER)) + row + }; + size_t len = win->lazyComp.rowLen + 1; + + memset(&LayerAt(win->layer, attr, origin.col,origin.row),0,len); + memset(&LayerAt(win->layer, code, origin.col,origin.row),0,len); + } +} + +void PrintLCD( Layer *layer, CUINT col, CUINT row, + int len, char *pStr, ATTRIBUTE lcdColor) +{ + register int j = len; + do { + register int offset = col + (len - j) * 3, + lo = pStr[len - j] & 0b00001111, + hi = pStr[len - j] & 0b11110000; + hi = (hi >> 4) - 0x2; + + LayerFillAt(layer, offset, row, \ + 3, LCD[hi][lo][0], \ + lcdColor); + + LayerFillAt(layer, offset, (row + 1), \ + 3, LCD[hi][lo][1], \ + lcdColor); + + LayerFillAt(layer, offset, (row + 2), \ + 3, LCD[hi][lo][2], \ + lcdColor); + j--; + } while (j > 0) ; +} + +void LazyCompWindow(Window *win) +{ + if (win->matrix.scroll.vert > LazyCompBottomRow(win)) { + win->matrix.scroll.vert = LazyCompBottomRow(win); + } + if (win->matrix.select.row > win->matrix.size.hth - 1) { + win->matrix.select.row = win->matrix.size.hth - 1; + } +} + +void MotionReset_Win(Window *win) +{ + win->matrix.scroll.horz = 0; win->matrix.select.col = 0; + win->matrix.scroll.vert = 0; win->matrix.select.row = 0; +} + +void MotionLeft_Win(Window *win) +{ + if (win->matrix.select.col > 0) { + win->matrix.select.col--; + } else { + win->matrix.select.col = win->matrix.size.wth - 1; + } +} + +void MotionRight_Win(Window *win) +{ + if (win->matrix.select.col < win->matrix.size.wth - 1) { + win->matrix.select.col++; + } else { + win->matrix.select.col = 0; + } +} + +void MotionUp_Win(Window *win) +{ + if (win->matrix.select.row > 0) { + win->matrix.select.row--; + } else if (win->matrix.scroll.vert > 0) { + win->matrix.scroll.vert--; + } +} + +void MotionDown_Win(Window *win) +{ + if (win->matrix.select.row < win->matrix.size.hth - 1) { + win->matrix.select.row++; + } else if (win->matrix.scroll.vert < LazyCompBottomRow(win)) { + win->matrix.scroll.vert++; + } +} + +void MotionHome_Win(Window *win) +{ + win->matrix.select.col = 0; +} + +void MotionEnd_Win(Window *win) +{ + win->matrix.select.col = win->matrix.size.wth - 1; +} + +void MotionTop_Win(Window *win) +{ + win->matrix.scroll.vert = 0; win->matrix.select.row = 0; +} + +void MotionBottom_Win(Window *win) +{ + win->matrix.scroll.vert = LazyCompBottomRow(win); + win->matrix.select.row = win->matrix.size.hth - 1; +} + +void MotionPgUp_Win(Window *win) +{ + if (win->matrix.scroll.vert >= win->matrix.size.hth) { + win->matrix.scroll.vert -= win->matrix.size.hth; + } else { + win->matrix.scroll.vert = 0; + } +} + +void MotionPgDw_Win(Window *win) +{ + if(win->matrix.scroll.vert + win->matrix.size.hth < LazyCompBottomRow(win)) + { + win->matrix.scroll.vert += win->matrix.size.hth; + } else { + win->matrix.scroll.vert = LazyCompBottomRow(win); + } +} + +void MotionOriginLeft_Win(Window *win) +{ + if (win->matrix.origin.col > 1) { + EraseWindowWithBorder(win); + win->matrix.origin.col--; + } +} + +void MotionOriginRight_Win(Window *win) +{ /* Care about the right-side window border. */ + const CUINT + maxVisibleCol = CUMIN(MAX_WIDTH - 1, (CUINT) GetScreenSize().width) + - win->lazyComp.rowLen; + + if (win->matrix.origin.col <= maxVisibleCol) { + EraseWindowWithBorder(win); + win->matrix.origin.col++; + } +} + +void MotionOriginUp_Win(Window *win) +{ + if (win->matrix.origin.row > 1) { + EraseWindowWithBorder(win); + win->matrix.origin.row--; + } +} + +void MotionOriginDown_Win(Window *win) +{ /* Care about the bottom window border */ + const CUINT maxVisibleRow = CUMIN(MAX_HEIGHT-1, GetScreenSize().height) + - win->matrix.size.hth - 1; + + if (win->matrix.origin.row < maxVisibleRow) { + EraseWindowWithBorder(win); + win->matrix.origin.row++; + } +} + +void MotionShrink_Win(Window *win) +{ + if (win->matrix.size.hth > 1) { + EraseWindowWithBorder(win); + win->matrix.size.hth--; + LazyCompWindow(win); + } +} + +void MotionExpand_Win(Window *win) +{ + const CUINT maxVisibleRow = GetScreenSize().height - 1, + winBottomRow = win->matrix.origin.row + win->matrix.size.hth, + winMaxHeight = win->dim / win->matrix.size.wth; + + if ((winBottomRow < maxVisibleRow)&&(win->matrix.size.hth < winMaxHeight)) + { + EraseWindowWithBorder(win); + win->matrix.size.hth++; + LazyCompWindow(win); + } +} + +void MotionUp_Wheel(Window *win) +{ + const ssize_t dim = win->dim >> 1; + if (win->matrix.scroll.vert > 0) { + win->matrix.scroll.vert--; + } else { + win->matrix.scroll.vert = dim - 1; + } +} + +void MotionDown_Wheel(Window *win) +{ + const ssize_t dim = win->dim >> 1; + if (win->matrix.scroll.vert < dim) { + win->matrix.scroll.vert++; + } else { + win->matrix.scroll.vert = 1; + } +} + +void MotionPgUp_Wheel(Window *win) +{ + const ssize_t dim = win->dim >> 1; + if (win->matrix.scroll.vert > win->matrix.select.row) { + win->matrix.scroll.vert -= win->matrix.select.row; + } else { + win->matrix.scroll.vert = dim - win->matrix.scroll.vert; + } +} + +void MotionPgDw_Wheel(Window *win) +{ + const ssize_t dim = win->dim >> 1; + if (win->matrix.scroll.vert + win->matrix.select.row < dim) { + win->matrix.scroll.vert += win->matrix.select.row; + } else { + win->matrix.scroll.vert = dim - win->matrix.scroll.vert; + } +} + +void MotionHome_Wheel(Window *win) +{ + const ssize_t dim = win->dim >> 1; + win->matrix.scroll.vert = dim - win->matrix.select.row; +} + +void MotionEnd_Wheel(Window *win) +{ + const ssize_t dim = win->dim >> 1; + win->matrix.scroll.vert = dim - win->matrix.select.row - 1; +} + +void MotionReScale(Window *win) +{ + CSINT col = -1, row = -1, height = -1; + CSINT rightSide = CUMAX(MIN_WIDTH, (CUINT) GetScreenSize().width) + - win->lazyComp.rowLen, + bottomSide = GetScreenSize().height - win->matrix.size.hth; + + if (rightSide > 0 && win->matrix.origin.col > rightSide) + { + col = rightSide + !(win->flag & WINFLAG_NO_BORDER); + } + if (bottomSide <= 0 && !(win->flag & WINFLAG_NO_SCALE)) + { + height = win->matrix.size.hth + bottomSide + - !(win->flag & WINFLAG_NO_BORDER) * 2; + + bottomSide = GetScreenSize().height - height; + } + if (bottomSide > 0 && win->matrix.origin.row >= bottomSide) + { + row = bottomSide - !(win->flag & WINFLAG_NO_BORDER); + } + if (col > 0 && win->matrix.origin.col != col) { + win->matrix.origin.col = (CUINT) col; + } + if (row > 0 && win->matrix.origin.row != row) { + win->matrix.origin.row = (CUINT) row; + } else if (row == 0 && win->matrix.origin.row != row) { + win->matrix.origin.row = 1; + height = win->matrix.size.hth - 1; + } + if (height > 0 && win->matrix.size.hth != height) { + win->matrix.size.hth = (CUINT) height; + LazyCompWindow(win); + } +} + +int Motion_Trigger(SCANKEY *scan, Window *win, WinList *list) +{ + switch (scan->key) { + case SCANKEY_ESC: + { + Layer *thisLayer = win->layer; + + if (win->hook.key.Escape != NULL) + win->hook.key.Escape(win); + else + RemoveWindow(win, list); + + ResetLayer(thisLayer, RSC(UI).ATTR()[UI_FUSE_RESET_LAYER]); + } + break; + case SCANKEY_TAB: + AnimateWindow(1, list); + break; + case SCANKEY_SHIFT_TAB: + case SCANCON_SHIFT_TAB: + AnimateWindow(0, list); + break; + case SCANKEY_LEFT: + if (win->hook.key.Left != NULL) + win->hook.key.Left(win); + break; + case SCANKEY_RIGHT: + if (win->hook.key.Right != NULL) + win->hook.key.Right(win); + break; + case SCANKEY_DOWN: + if (win->hook.key.Down != NULL) + win->hook.key.Down(win); + break; + case SCANKEY_UP: + if (win->hook.key.Up != NULL) + win->hook.key.Up(win); + break; + case SCANKEY_HOME: + case SCANCON_HOME: + case SCANSYM_HOME: + if (win->hook.key.Home != NULL) + win->hook.key.Home(win); + break; + case SCANKEY_END: + case SCANCON_END: + case SCANSYM_END: + if (win->hook.key.End != NULL) + win->hook.key.End(win); + break; + case SCANKEY_PGUP: + if (win->hook.key.PgUp != NULL) + win->hook.key.PgUp(win); + break; + case SCANKEY_PGDW: + if (win->hook.key.PgDw != NULL) + win->hook.key.PgDw(win); + break; + case SCANKEY_SHIFT_RIGHT: + case SCANSYM_SHIFT_RIGHT: + case SCANKEY_SHIFT_d: + if (win->hook.key.WinRight != NULL) + win->hook.key.WinRight(win); + break; + case SCANKEY_SHIFT_LEFT: + case SCANSYM_SHIFT_LEFT: + case SCANKEY_SHIFT_a: /* AZERTY */ + case SCANKEY_SHIFT_q: /* QWERTY */ + if (win->hook.key.WinLeft != NULL) + win->hook.key.WinLeft(win); + break; + case SCANKEY_SHIFT_UP: + case SCANSYM_SHIFT_UP: + case SCANKEY_SHIFT_s: + if (win->hook.key.WinUp != NULL) + win->hook.key.WinUp(win); + break; + case SCANKEY_SHIFT_DOWN: + case SCANSYM_SHIFT_DOWN: + case SCANKEY_SHIFT_x: + if (win->hook.key.WinDown != NULL) + win->hook.key.WinDown(win); + break; + case SCANKEY_ALT_UP: + case SCANSYM_ALT_UP: + case SCANKEY_ALT_SHIFT_s: + case SCANKEY_ALT_s: + case SCANCON_ALT_s: + if (win->hook.key.Shrink != NULL) + win->hook.key.Shrink(win); + break; + case SCANKEY_ALT_DOWN: + case SCANSYM_ALT_DOWN: + case SCANKEY_ALT_SHIFT_x: + case SCANKEY_ALT_x: + case SCANCON_ALT_x: + if (win->hook.key.Expand != NULL) + win->hook.key.Expand(win); + break; + case SCANKEY_ENTER: + if (win->hook.key.Enter != NULL) + return win->hook.key.Enter(scan, win); + fallthrough; + default: + return -1; + } + return 0; +} + +void ForEachCellPrint_Drop(Window *win, void *plist) +{ + WinList *list = (WinList *) plist; + CUINT col, row; + for (row = 0; row < win->matrix.size.hth; row++) { + for (col = 0; col < win->matrix.size.wth; col++) { + if (TCellAt(win, + (win->matrix.scroll.horz + col), + (win->matrix.scroll.vert + row)).quick.key != SCANKEY_VOID) + { + PrintContent(win, list, col, row); + } + } + } +} + +int Enter_StickyCell(SCANKEY *scan, Window *win) +{ + if ((scan->key = TCellAt(win, + ( win->matrix.select.col + + win->matrix.scroll.horz), + ( win->matrix.select.row + + win->matrix.scroll.vert) + ).quick.key) != SCANKEY_NULL) + { + return 1; + } else { + return 0; + } +} + +int MotionEnter_Cell(SCANKEY *scan, Window *win) +{ + if ((scan->key = TCellAt(win, + ( win->matrix.select.col + + win->matrix.scroll.horz), + ( win->matrix.select.row + + win->matrix.scroll.vert) + ).quick.key) != SCANKEY_NULL) + { + SCANKEY closeKey = {.key = SCANKEY_ESC}; + Motion_Trigger(&closeKey, win,&winList); + return 1; + } else { + return 0; + } +} + +void MotionEnd_Cell(Window *win) +{ + win->matrix.scroll.vert = LazyCompBottomRow(win); + win->matrix.select.row = win->matrix.size.hth - 1; +} + +void MotionLeft_Menu(Window *win) +{ + CUINT row; + for (row = 1; row < win->matrix.size.hth; row++) { + EraseTCell_Menu(win); + } + if (win->matrix.select.col > 0) { + win->matrix.select.col--; + } else { + win->matrix.select.col = win->matrix.size.wth - 1; + } + win->matrix.select.row = 0; +} + +void MotionRight_Menu(Window *win) +{ + CUINT row; + for (row = 1; row < win->matrix.size.hth; row++) { + EraseTCell_Menu(win); + } + if (win->matrix.select.col < win->matrix.size.wth - 1) { + win->matrix.select.col++; + } else { + win->matrix.select.col = 0; + } + win->matrix.select.row = 0; +} + +void MotionUp_Menu(Window *win) +{ + CUINT row = win->matrix.select.row; + + if (win->matrix.select.row > 0) { + row--; + } + if (TCellAt(win, + (win->matrix.scroll.horz + win->matrix.select.col), + (win->matrix.scroll.vert + row)).quick.key != SCANKEY_VOID) + { + win->matrix.select.row = row; + } +} + +void MotionDown_Menu(Window *win) +{ + CUINT row = win->matrix.select.row; + + if (row < win->matrix.size.hth - 1) { + row++; + } + if (TCellAt(win, + (win->matrix.scroll.horz + win->matrix.select.col), + (win->matrix.scroll.vert + row)).quick.key != SCANKEY_VOID) + { + win->matrix.select.row = row; + } +} + +void MotionHome_Menu(Window *win) +{ + if (TCellAt(win, + (win->matrix.scroll.horz + win->matrix.select.col), + (win->matrix.scroll.vert + 1)).quick.key != SCANKEY_VOID) + { + win->matrix.select.row = 1; + } else { + win->matrix.select.row = 0; + } +} + +void MotionEnd_Menu(Window *win) +{ + CUINT row = 0; + for (row = win->matrix.size.hth - 1; row > 1; row--) { + if (TCellAt(win, + (win->matrix.scroll.horz + win->matrix.select.col), + (win->matrix.scroll.vert + row)).quick.key != SCANKEY_VOID) + { + break; + } + } + win->matrix.select.row = row; +} + +#define Call_PrintHook(_win, _list) \ +({ \ + ComputeLazyBottomRow(_win, !(_win->flag & WINFLAG_NO_BORDER)); \ + \ + if (_win->hook.Print != NULL) { \ + MotionReScale(_win); \ + _win->hook.Print(_win, _list); \ + } else { \ + MotionReScale(_win); \ + ForEachCellPrint(_win, _list); \ + PrintComment(_win); \ + } \ +}) + +void PrintWindowStack(WinList *winList) +{ + Window *walker; + if ((walker = GetHead(winList)) != NULL) { + do { + walker = GetNext(walker); + Call_PrintHook(walker, winList); + } + while (!IsHead(winList, walker)) ; + } +} + +void WindowsUpdate(WinList *winList) +{ + Window *walker, *marker = NULL; + if ((walker = GetFocus(winList)) != NULL) + { + CUINT col, row; + do + { + walker = GetNext(walker); + for (row = 0; row < walker->matrix.size.hth; row++) { + for (col = 0; col < walker->matrix.size.wth; col++) + { + CUINT horzCol = walker->matrix.scroll.horz + col, + vertRow = walker->matrix.scroll.vert + row; + + if (TGridAt(walker, horzCol, vertRow).Update != NULL) + { + TGridAt(walker, horzCol, vertRow).Update( + &TGridAt(walker, horzCol, vertRow), + TGridAt(walker, horzCol, vertRow).data); + if (marker == NULL) { + marker = GetPrev(walker); + } + } + } + } + } while (!IsHead(winList, walker)) ; + } + if ((walker = marker) != NULL) + { + do + { + walker = GetNext(walker); + Call_PrintHook(walker, winList); + } + while (!IsHead(winList, walker)) ; + } +} + +void ReScaleAllWindows(WinList *list) +{ + if (!IsDead(list)) { + Window *walker = GetHead(list); + do + { + EraseWindowWithBorder(walker); + MotionReScale(walker); + Call_PrintHook(walker, list); + + walker = GetNext(walker); + } while (!IsHead(list, walker)) ; + } +} + +void HookCardFunc(CARDFUNC *with, CARDFUNC what) { *with=what; } + +Card *CreateCard(void) +{ + Card *card = calloc(1, sizeof(Card)); + if (card != NULL) { + GetNext(card) = NULL; + } + return card; +} + +void AppendCard(Card *card, CardList *list) +{ + if (card != NULL) { + if (GetHead(list) == NULL) { + GetHead(list) = GetTail(list) = card; + } else { + GetNext(GetTail(list)) = card; + GetTail(list) = card; + } + } +} + +void DestroyAllCards(CardList *list) +{ + Card *card = GetHead(list); + while (card != NULL) { + Card *_next = GetNext(card); + free(card); + card = _next; + } + GetHead(list) = GetTail(list) = NULL; +} + +void FreeAll(char *buffer) +{ + DestroyAllWindows(&winList); + DestroyFullStock(); + + if (Console != NULL) { + free(Console); + } + if (StreamBuf != NULL) { + setbuf(stdout, NULL); + free(StreamBuf); + } + if (buffer != NULL) { + free(buffer); + } + DestroyLayer(sLayer); + DestroyLayer(dLayer); + DestroyLayer(wLayer); + DestroyLayer(Fuse); + + if (sLayer != NULL) { + free(sLayer); + } + if (dLayer != NULL) { + free(dLayer); + } + if (wLayer != NULL) { + free(wLayer); + } + if (Fuse != NULL) { + free(Fuse); + } + if (Dump.Handle != NULL) { + fclose(Dump.Handle); + Dump.Handle = NULL; + } + if (Dump.Buffer != NULL) { + free(Dump.Buffer); + Dump.Buffer = NULL; + } +} + +UBENCH_DECLARE() + +#define MAX_ANSI_WIDTH (10 * MAX_WIDTH) +#define MAX_ANSI_SCREEN (MAX_ANSI_WIDTH * MAX_HEIGHT) +__typeof__ (errno) AllocAll(char **buffer) +{ /* Alloc 10 times to include the ANSI cursor strings. */ + + if ((*buffer = malloc(MAX_ANSI_WIDTH)) == NULL) { + return ENOMEM; + } + if ((Console = malloc(MAX_ANSI_SCREEN)) == NULL) { + return ENOMEM; + } + if ((StreamBuf = malloc(MAX_ANSI_SCREEN)) == NULL) { + return ENOMEM; + } else { + setvbuf(stdout, StreamBuf, _IOFBF, MAX_ANSI_SCREEN); + } + const CoordSize layerSize = { + .wth = MAX_WIDTH, + .hth = MAX_HEIGHT + }; + + if ((sLayer = calloc(1, sizeof(Layer))) == NULL) { + return ENOMEM; + } + if ((dLayer = calloc(1, sizeof(Layer))) == NULL) { + return ENOMEM; + } + if ((wLayer = calloc(1, sizeof(Layer))) == NULL) { + return ENOMEM; + } + if ((Fuse = calloc(1, sizeof(Layer))) == NULL) { + return ENOMEM; + } + CreateLayer(sLayer, layerSize); + CreateLayer(dLayer, layerSize); + CreateLayer(wLayer, layerSize); + CreateLayer(Fuse, layerSize); + + UBENCH_SETUP(1, 0); + return 0; +} + +signed int FuseAll(ASCII stream[], SCREEN_SIZE drawSize) +{ + register ATTRIBUTE *fa, *sa, *da, *wa; + register ASCII *fc, *sc, *dc, *wc; + register signed int _col, _row, cursor; + register signed int idx, sdx = 0; + register ATTRIBUTE attr = {.value = 0}; + + for (_row = 0; _row < drawSize.height; _row++) + { + stream[sdx++] = 0x1b; + stream[sdx++] = '['; + + cursor = _row + 1; + sdx += cursor >= 100 ? 3 : cursor >= 10 ? 2 : 1; + for (idx = sdx; cursor > 0; cursor /= 10) { + stream[--idx] = '0' + (ASCII) (cursor % 10); + } + stream[sdx++] = ';'; + stream[sdx++] = '1'; + stream[sdx++] = 'H'; + + cursor = _row * Fuse->size.wth; + for (_col = 0; _col < drawSize.width; _col++) + { + idx = _col + cursor; + fa = &Fuse->attr[idx]; + sa = &sLayer->attr[idx]; + da = &dLayer->attr[idx]; + wa = &wLayer->attr[idx]; + fc = &Fuse->code[idx]; + sc = &sLayer->code[idx]; + dc = &dLayer->code[idx]; + wc = &wLayer->code[idx]; + /* STATIC LAYER */ + fa->value = sa->value; + *fc = *sc; + /* DYNAMIC LAYER */ + fa->value = da->value ? da->value : fa->value; + *fc = *dc ? *dc : *fc; + /* WINDOWS LAYER */ + fa->value = wa->value ? wa->value : fa->value; + *fc = *wc ? *wc : *fc; + /* FUSED LAYER */ + if ((fa->fg ^ attr.fg) || (fa->bg ^ attr.bg) || (fa->bf ^ attr.bf)) + { + stream[sdx++] = 0x1b; + stream[sdx++] = '['; + stream[sdx++] = '0' + fa->bf; + stream[sdx++] = ';'; + stream[sdx++] = fa->bf ? '9' : '3'; + stream[sdx++] = '0' + fa->fg; + #ifndef UI_TRANSPARENCY + stream[sdx++] = ';'; + stream[sdx++] = '4'; + stream[sdx++] = '0' + fa->bg; + #endif /* UI_TRANSPARENCY */ + stream[sdx++] = 'm'; + } + if (fa->un ^ attr.un) + { + stream[sdx++] = 0x1b; + stream[sdx++] = '['; + if (fa->un) { + stream[sdx++] = '4'; + stream[sdx++] = 'm'; + } else { + stream[sdx++] = '2'; + stream[sdx++] = '4'; + stream[sdx++] = 'm'; + } + } + attr.value = fa->value; + + switch (*fc) { + case 0x0: + stream[sdx++] = 0x20; + break; + case 0xc0 ... 0xdf: + stream[sdx++] = 0xc2; /* Control C2 Unicode UTF-8 */ + stream[sdx++] = *fc ^ 0x60; + break; + case 0x80 ... 0xbf: + stream[sdx++] = 0xc3; /* Control C3 Unicode UTF-8 */ + fallthrough; + default: + stream[sdx++] = *fc; + break; + } + } + } + return sdx; +} + +__typeof__ (errno) StartDump( char *dumpFormat, int tickReset, + enum DUMP_METHOD method ) +{ + __typeof__ (errno) rc = EBUSY; + + if (!BITVAL(Dump.Status, 0)) + { + char *dumpFileName = malloc(64); + if (dumpFileName != NULL) + { + if ((Dump.Buffer = malloc(MAX_ANSI_SCREEN)) != NULL) + { + Bit64 tsc __attribute__ ((aligned (8))); + RDTSC64(tsc); + + snprintf(dumpFileName, 64, dumpFormat, tsc); + if ((Dump.Handle = fopen(dumpFileName, "w")) != NULL) + { + setvbuf(Dump.Handle,Dump.Buffer,_IOFBF,MAX_ANSI_SCREEN); + + switch (method) { + case DUMP_TO_JSON: + Dump.Header= JSON_Header; + Dump.Write = JSON_Page; + Dump.Break = JSON_Break; + break; + case DUMP_TO_ANSI: + Dump.Header= ANSI_Header; + Dump.Write = ANSI_Page; + Dump.Break = ANSI_Break; + break; + }; + Dump.Tick = tickReset; + Dump.Header(); + BITSET(LOCKLESS, Dump.Status, 0); + rc = 0; + } else { + rc = errno; + free(Dump.Buffer); + Dump.Buffer = NULL; + } + } else { + rc = ENOMEM; + } + free(dumpFileName); + } else { + rc = ENOMEM; + } + } + return rc; +} + +void AbortDump(void) +{ + Dump.Tick = 0; +} + +unsigned char DumpStatus(void) +{ + return BITVAL(Dump.Status, 0); +} + +unsigned int WriteConsole(SCREEN_SIZE drawSize) +{ + signed int writeSize; + unsigned int layout = 0; + + UI_Draw_uBenchmark(dLayer); + + UBENCH_RDCOUNTER(1); + + writeSize = FuseAll((ASCII*) Console, drawSize); + + UBENCH_RDCOUNTER(2); + UBENCH_COMPUTE(); + + if (writeSize > 0) + { + if (fwrite(Console, (size_t) writeSize, 1, stdout) > 0) { + fflush(stdout); + } + if (BITVAL(Dump.Status, 0)) + { + Dump.Write(Console, writeSize); + + if (Dump.Tick > 0) { + Dump.Tick--; + + Dump.Break(); + } else { + BITCLR(LOCKLESS, Dump.Status, 0); + + if (fclose(Dump.Handle) == 0) { + Dump.Handle = NULL; + } + if (Dump.Buffer != NULL) { + free(Dump.Buffer); + Dump.Buffer = NULL; + } + layout = 1; + } + } + } + return layout; +} + +void ANSI_Header(void) +{ +} + +void ANSI_Page(char *inStr, int outSize) +{ + fwrite(inStr, (size_t) outSize, 1, Dump.Handle); +} + +void ANSI_Break(void) +{ + fwrite( _LF _FF, 1, 1, Dump.Handle); +} + +void JSON_Header(void) +{ + SCREEN_SIZE terminalSize = GetScreenSize(); + + time(&Dump.StartedAt); + fprintf(Dump.Handle, + "{\"version\": %d, \"width\": %d, \"height\": %d," \ + " \"timestamp\": %ld, \"title\": \"%s\", " \ + "\"env\": {\"TERM\": \"%s\"}}\n", + 2, terminalSize.width, terminalSize.height, + Dump.StartedAt, "CoreFreq", "xterm"); +} + +void JSON_Page(char *inStr, int outSize) +{ + double integral, fractional; + unsigned char *pLast = (unsigned char *) &inStr[outSize], + *pFirst= (unsigned char *) &inStr[0], *pChr; + time_t now; + time(&now); + + fractional = modf(difftime(now, Dump.StartedAt), &integral); + fprintf(Dump.Handle, "[%lld.%lld, \"o\", \"", + (signed long long) integral, + (signed long long) fractional); + + for (pChr = pFirst; pChr < pLast; pChr++) { + switch (*pChr) { + case 0x1b: + fprintf(Dump.Handle, "\\u001b"); + break; + case 0xc2: + fprintf(Dump.Handle, "\\u00%x", *(++pChr)); + break; + case 0xc3: + fprintf(Dump.Handle, "\\u00%x", *(++pChr) ^ 0x40); + break; + case '\\': + fprintf(Dump.Handle, "\\u005c"); + break; + default: + fputc((*pChr), Dump.Handle); + break; + } + } + fprintf(Dump.Handle, "\"]\n"); +} + +void JSON_Break(void) +{ +} +#undef MAX_ANSI_SCREEN +#undef MAX_ANSI_WIDTH + +void _TERMINAL_IN(void) +{ + printf(SCP SCR1 CUH CLS HIDE); + + tcgetattr(STDIN_FILENO, &oldt); + newt = oldt; + __typeof__(newt.c_lflag) flags = ICANON | ECHO; + flags = ~flags; + newt.c_lflag &= flags; + newt.c_cc[VTIME] = 0; + newt.c_cc[VMIN] = 0; + tcsetattr(STDIN_FILENO, TCSANOW, &newt); +} + +void _TERMINAL_OUT(void) +{ + tcsetattr(STDIN_FILENO, TCSANOW, &oldt); + + printf(SHOW SCR0 RCP COLOR(0,9,9)); +} + +void _LOCALE_IN(void) +{ + SysLoc = newlocale(LC_MESSAGES_MASK, "", (locale_t) 0); + + if (SysLoc != NULL) { + #ifdef __GLIBC__ + const char *s18n = SysLoc->__names[5]; + #else + const char *s18n = "en_US.UTF-8"; + #endif + struct LOCALE_LOOKUP *lookUp = LocaleLookUp; + while (lookUp->i18n != NULL) { + I18N *i18n = lookUp->i18n; + while (i18n[0][0] != 0) { + if (!strncmp((char *) i18n, s18n, sizeof(I18N))) + { + SET_LOCALE(lookUp->apploc); + return; + } + i18n++; + } + lookUp++; + } + } +} + +void _LOCALE_OUT(void) +{ + if (SysLoc != (locale_t) 0) { + freelocale(SysLoc); + } +} + +void LocaleTo(int category) +{ + struct LOCALE_LOOKUP *lookUp = LocaleLookUp; + while (lookUp->i18n != NULL) { + if (lookUp->apploc == GET_LOCALE()) { + char localeStr[sizeof(I18N) + 1]; + memcpy(localeStr, lookUp->i18n[0], sizeof(I18N)); + localeStr[sizeof(I18N)] = '\0'; + setlocale(category, localeStr); + return; + } + lookUp++; + } + setlocale(category, "C"); +} + +__typeof__ (errno) SaveGeometries(char *cfgFQN) +{ + __typeof__ (errno) rc = 0; + FILE *cfgHandle = NULL; + if ((cfgHandle = fopen(cfgFQN, "w")) == NULL) + { + char *cfgdup = strdup(cfgFQN); + if (cfgdup != NULL) + { + char *dirOnly = dirname(cfgdup); + rc = mkdir(dirOnly, S_IRWXU); + free(cfgdup); + } else { + rc = errno; + } + } + if ((cfgHandle != NULL) || (cfgHandle = fopen(cfgFQN, "w")) != NULL) + { + Stock *walker = stockList.head; + while (walker != NULL) { + if (fprintf(cfgHandle, "%llx,%hu,%hu\n", + walker->id, + walker->geometry.origin.col, + walker->geometry.origin.row) < 0) + { + rc = errno; + break; + } else { + walker = GetNext(walker); + } + } + fclose(cfgHandle); + } else { + rc = errno; + } + return rc; +} + +__typeof__ (errno) LoadGeometries(char *cfgFQN) +{ + __typeof__ (errno) rc = 0; + FILE *cfgHandle = NULL; + if ((cfgHandle = fopen(cfgFQN, "r")) != NULL) + { + while (!feof(cfgHandle)) + { + unsigned long long id; + struct Geometry geometry; + int match = fscanf(cfgHandle, "%llx,%hu,%hu\n", + &id, + &geometry.origin.col, + &geometry.origin.row); + + if ((match != EOF) && (match == 3)) + { + if (AppendStock(CreateStock(id, geometry.origin)) == NULL) + { + rc = ENOMEM; + break; + } + } else { + rc = errno; + break; + } + } + fclose(cfgHandle); + } else { + rc = errno; + } + return rc; +} diff --git a/x86_64/corefreq-ui.h b/x86_64/corefreq-ui.h new file mode 100644 index 00000000..0cc91e62 --- /dev/null +++ b/x86_64/corefreq-ui.h @@ -0,0 +1,969 @@ +/* + * CoreFreq + * Copyright (C) 2015-2024 CYRIL COURTIAT + * Licenses: GPL2 + */ + +#ifdef NO_HEADER + #define TOP_HEADER_ROW 0 +#else + #define TOP_HEADER_ROW 3 +#endif + +#ifdef NO_FOOTER + #define TOP_FOOTER_ROW 0 +#else + #define TOP_FOOTER_ROW 2 +#endif + +#ifdef NO_UPPER + #define ADD_UPPER 0 +#else + #define ADD_UPPER 1 +#endif + +#ifdef NO_LOWER + #define ADD_LOWER 0 +#else + #define ADD_LOWER 1 +#endif + +#define TOP_SEPARATOR (ADD_UPPER + (2 * ADD_LOWER)) + +#define MAX_HEIGHT ((2 * CORE_COUNT) \ + + 3 /* HEADER_ROW */ \ + + 3 /* SEPARATOR */ \ + + 2 /* FOOTER_ROW */) + +#define MAX_WIDTH 320 +#define MIN_WIDTH 80 + +#define CUMAX(M, m) ((M) > (m) ? (M) : (m)) +#define CUMIN(m, M) ((m) < (M) ? (m) : (M)) + +typedef unsigned short int CUINT; +typedef signed short int CSINT; + +/* VT100 requirements. */ +#define SCP "\033[s" +#define RCP "\033[u" +#define HIDE "\033[?25l" +#define SHOW "\033[?25h" +#define RESET "\033c" +#define SCR1 "\033[?47h" +#define SCR0 "\033[?47l" +#define CLS "\033[J" +#define CUH "\033[H" +#define CUP(col, row) "\033["#row";"#col"H" +#define _LF "\x0a" +#define _FF "\x0c" + +enum PALETTE { + _BLACK, + _RED, + _GREEN, + _YELLOW, + _BLUE, + _MAGENTA, + _CYAN, + _WHITE +}; + +#define BLACK 0 +#define RED 1 +#define GREEN 2 +#define YELLOW 3 +#define BLUE 4 +#define MAGENTA 5 +#define CYAN 6 +#define WHITE 7 + +#define _COLOR(_mod, _fg, _bg) "\033["#_mod";3"#_fg";4"#_bg"m" +#define COLOR(mod, fg, bg) _COLOR(mod, fg, bg) + +#define AoK COLOR(0, WHITE, BLACK) +#define DoK COLOR(1, BLACK, BLACK) +#define RoK COLOR(1, RED, BLACK) +#define GoK COLOR(1, GREEN, BLACK) +#define YoK COLOR(1, YELLOW, BLACK) +#define BoK COLOR(1, BLUE, BLACK) +#define MoK COLOR(1, MAGENTA, BLACK) +#define CoK COLOR(1, CYAN, BLACK) +#define WoK COLOR(1, WHITE, BLACK) + +#define HSPACE " "" "" "" "" " \ + " "" "" "" "" " \ + " "" "" "" "" " \ + " "" "" "" "" " \ + " "" "" "" "" " \ + " "" "" "" "" " \ + " "" "" "" "" " \ + " "" "" "" "" " + +#define HBAR "||||||||""||||||||""||||||||""||||||||""||||||||" \ + "||||||||""||||||||""||||||||""||||||||""||||||||" \ + "||||||||""||||||||""||||||||""||||||||""||||||||" \ + "||||||||""||||||||""||||||||""||||||||""||||||||" \ + "||||||||""||||||||""||||||||""||||||||""||||||||" \ + "||||||||""||||||||""||||||||""||||||||""||||||||" \ + "||||||||""||||||||""||||||||""||||||||""||||||||" \ + "||||||||""||||||||""||||||||""||||||||""||||||||" + +#define HLINE "--------""--------""--------""--------""--------" \ + "--------""--------""--------""--------""--------" \ + "--------""--------""--------""--------""--------" \ + "--------""--------""--------""--------""--------" \ + "--------""--------""--------""--------""--------" \ + "--------""--------""--------""--------""--------" \ + "--------""--------""--------""--------""--------" \ + "--------""--------""--------""--------""--------" + +typedef union { + unsigned long long key; + unsigned char code[8]; +} SCANKEY; + +#define SCANKEY_VOID 0x8000000000000000 +#define SCANKEY_NULL 0x0000000000000000 +#define SCANKEY_TAB 0x0000000000000009 +#define SCANKEY_ENTER 0x000000000000000a +#define SCANKEY_ESC 0x000000000000001b +#define SCANKEY_UP 0x0000000000415b1b +#define SCANKEY_DOWN 0x0000000000425b1b +#define SCANKEY_RIGHT 0x0000000000435b1b +#define SCANKEY_LEFT 0x0000000000445b1b +#define SCANKEY_HOME 0x0000000000485b1b +#define SCANKEY_END 0x0000000000465b1b +#define SCANKEY_F1 0x0000000000504f1b +#define SCANKEY_F2 0x0000000000514f1b +#define SCANKEY_F3 0x0000000000524f1b +#define SCANKEY_F4 0x0000000000534f1b +#define SCANKEY_F10 0x0000007e31325b1b +#define SCANKEY_SHIFT_TAB 0x00000000005a5b1b +#define SCANKEY_PGUP 0x000000007e355b1b +#define SCANKEY_PGDW 0x000000007e365b1b +#define SCANKEY_EXCL 0x0000000000000021 +#define SCANKEY_HASH 0x0000000000000023 +#define SCANKEY_DOLLAR 0x0000000000000024 +#define SCANKEY_PERCENT 0x0000000000000025 +#define SCANKEY_AST 0x000000000000002a +#define SCANKEY_PLUS 0x000000000000002b +#define SCANKEY_MINUS 0x000000000000002d +#define SCANKEY_DOT 0x000000000000002e +#define SCANKEY_SHIFT_UP 0x000041323b315b1b +#define SCANKEY_SHIFT_DOWN 0x000042323b315b1b +#define SCANKEY_SHIFT_RIGHT 0x000043323b315b1b +#define SCANKEY_SHIFT_LEFT 0x000044323b315b1b +#define SCANKEY_ALT_UP 0x000041333b315b1b +#define SCANKEY_ALT_DOWN 0x000042333b315b1b +#define SCANKEY_SHIFT_a 0x0000000000000041 +#define SCANKEY_SHIFT_b 0x0000000000000042 +#define SCANKEY_SHIFT_c 0x0000000000000043 +#define SCANKEY_SHIFT_d 0x0000000000000044 +#define SCANKEY_SHIFT_e 0x0000000000000045 +#define SCANKEY_SHIFT_f 0x0000000000000046 +#define SCANKEY_SHIFT_g 0x0000000000000047 +#define SCANKEY_SHIFT_h 0x0000000000000048 +#define SCANKEY_SHIFT_i 0x0000000000000049 +#define SCANKEY_SHIFT_l 0x000000000000004c +#define SCANKEY_SHIFT_m 0x000000000000004d +#define SCANKEY_SHIFT_n 0x000000000000004e +#define SCANKEY_SHIFT_o 0x000000000000004f +#define SCANKEY_SHIFT_q 0x0000000000000051 +#define SCANKEY_SHIFT_r 0x0000000000000052 +#define SCANKEY_SHIFT_s 0x0000000000000053 +#define SCANKEY_SHIFT_t 0x0000000000000054 +#define SCANKEY_SHIFT_v 0x0000000000000056 +#define SCANKEY_SHIFT_w 0x0000000000000057 +#define SCANKEY_SHIFT_x 0x0000000000000058 +#define SCANKEY_SHIFT_y 0x0000000000000059 +#define SCANKEY_CTRL_p 0x0000000000000010 +#define SCANKEY_CTRL_u 0x0000000000000015 +#define SCANKEY_CTRL_x 0x0000000000000018 +#define SCANKEY_ALT_SHIFT_s 0x00000000000093c3 +#define SCANKEY_ALT_SHIFT_x 0x00000000000098c3 +#define SCANKEY_ALT_p 0x000000000000b0c3 +#define SCANKEY_ALT_s 0x000000000000b3c3 +#define SCANKEY_ALT_x 0x000000000000b8c3 +#define SCANKEY_CTRL_ALT_x 0x00000000000098c2 +#define SCANKEY_a 0x0000000000000061 +#define SCANKEY_b 0x0000000000000062 +#define SCANKEY_c 0x0000000000000063 +#define SCANKEY_d 0x0000000000000064 +#define SCANKEY_e 0x0000000000000065 +#define SCANKEY_f 0x0000000000000066 +#define SCANKEY_g 0x0000000000000067 +#define SCANKEY_h 0x0000000000000068 +#define SCANKEY_i 0x0000000000000069 +#define SCANKEY_k 0x000000000000006b +#define SCANKEY_l 0x000000000000006c +#define SCANKEY_m 0x000000000000006d +#define SCANKEY_n 0x000000000000006e +#define SCANKEY_o 0x000000000000006f +#define SCANKEY_p 0x0000000000000070 +#define SCANKEY_q 0x0000000000000071 +#define SCANKEY_r 0x0000000000000072 +#define SCANKEY_s 0x0000000000000073 +#define SCANKEY_t 0x0000000000000074 +#define SCANKEY_u 0x0000000000000075 +#define SCANKEY_v 0x0000000000000076 +#define SCANKEY_w 0x0000000000000077 +#define SCANKEY_x 0x0000000000000078 +#define SCANKEY_y 0x0000000000000079 +#define SCANKEY_z 0x000000000000007a +#define SCANKEY_OPEN_BRACE 0x000000000000007b +#define SCANKEY_CLOSE_BRACE 0x000000000000007d + +#define SCANCON_HOME 0x000000007e315b1b +#define SCANCON_END 0x000000007e345b1b +#define SCANCON_F1 0x00000000415b5b1b +#define SCANCON_F2 0x00000000425b5b1b +#define SCANCON_F3 0x00000000435b5b1b +#define SCANCON_F4 0x00000000445b5b1b +#define SCANCON_SHIFT_TAB 0x000000000000091b +#define SCANCON_ALT_p 0x000000000000701b +#define SCANCON_ALT_s 0x000000000000731b +#define SCANCON_ALT_x 0x000000000000781b +#define SCANCON_CTRL_ALT_x 0x000000000000181b + +#define SCANSYM_HOME 0x000000007e375b1b +#define SCANSYM_END 0x000000007e385b1b +#define SCANSYM_F1 0x0000007e31315b1b +#define SCANSYM_F2 0x0000007e32315b1b +#define SCANSYM_F3 0x0000007e33315b1b +#define SCANSYM_F4 0x0000007e34315b1b +#define SCANSYM_SHIFT_UP 0x0000000000615b1b +#define SCANSYM_SHIFT_DOWN 0x0000000000625b1b +#define SCANSYM_SHIFT_RIGHT 0x0000000000635b1b +#define SCANSYM_SHIFT_LEFT 0x0000000000645b1b +#define SCANSYM_ALT_UP 0x00000000415b1b1b +#define SCANSYM_ALT_DOWN 0x00000000425b1b1b + +typedef struct { + int width, + height; +} SCREEN_SIZE; + +typedef struct { + CUINT col, + row; +} Coordinate; + +typedef struct { + CSINT horz, + vert; +} CoordShift; + +typedef struct { + CUINT wth, + hth; +} CoordSize; + +typedef union { + unsigned char value; + struct { + unsigned char fg: 3-0, + un: 4-3, + bg: 7-4, + bf: 8-7; + }; +} ATTRIBUTE; + +#define MakeAttr(_fg, _un, _bg, _bf) \ + ({ATTRIBUTE _attr={.fg = _fg,.un = _un,.bg = _bg,.bf = _bf}; _attr;}) + +#define HDK {.fg = BLACK, .bg = BLACK, .bf = 1} +#define HRK {.fg = RED, .bg = BLACK, .bf = 1} +#define HGK {.fg = GREEN, .bg = BLACK, .bf = 1} +#define HYK {.fg = YELLOW, .bg = BLACK, .bf = 1} +#define HBK {.fg = BLUE, .bg = BLACK, .bf = 1} +#define HMK {.fg = MAGENTA, .bg = BLACK, .bf = 1} +#define HCK {.fg = CYAN, .bg = BLACK, .bf = 1} +#define HWK {.fg = WHITE, .bg = BLACK, .bf = 1} +#define HKB {.fg = BLACK, .bg = BLUE, .bf = 1} +#define HWB {.fg = WHITE, .bg = BLUE, .bf = 1} +#define HKM {.fg = BLACK, .bg = MAGENTA, .bf = 1} +#define HWC {.fg = WHITE, .bg = CYAN, .bf = 1} +#define HKW {.fg = BLACK, .bg = WHITE, .bf = 1} +#define HRW {.fg = RED, .bg = WHITE, .bf = 1} +#define HYW {.fg = YELLOW, .bg = WHITE, .bf = 1} +#define HBW {.fg = BLUE, .bg = WHITE, .bf = 1} +#define HCW {.fg = CYAN, .bg = WHITE, .bf = 1} +#define HMW {.fg = MAGENTA, .bg = WHITE, .bf = 1} +#define _HCK {.fg = CYAN, .bg = BLACK, .un = 1, .bf = 1} +#define _HWK {.fg = WHITE, .bg = BLACK, .un = 1, .bf = 1} +#define _HWB {.fg = WHITE, .bg = BLUE, .un = 1, .bf = 1} +#define _HKW {.fg = BLACK, .bg = WHITE, .un = 1, .bf = 1} +#define _HCW {.fg = CYAN, .bg = WHITE, .un = 1, .bf = 1} +#define LDK {.fg = BLACK, .bg = BLACK} +#define LRK {.fg = RED, .bg = BLACK} +#define LGK {.fg = GREEN, .bg = BLACK} +#define LYK {.fg = YELLOW, .bg = BLACK} +#define LBK {.fg = BLUE, .bg = BLACK} +#define LMK {.fg = MAGENTA, .bg = BLACK} +#define LCK {.fg = CYAN, .bg = BLACK} +#define LWK {.fg = WHITE, .bg = BLACK} +#define LKY {.fg = BLACK, .bg = YELLOW} +#define LWB {.fg = WHITE, .bg = BLUE} +#define LKM {.fg = BLACK, .bg = MAGENTA} +#define LWM {.fg = WHITE, .bg = MAGENTA} +#define LKC {.fg = BLACK, .bg = CYAN} +#define LKW {.fg = BLACK, .bg = WHITE} +#define LRW {.fg = RED, .bg = WHITE} +#define LGW {.fg = GREEN, .bg = WHITE} +#define LBW {.fg = BLUE, .bg = WHITE} +#define LCW {.fg = CYAN, .bg = WHITE} +#define LMW {.fg = MAGENTA, .bg = WHITE} +#define _LCK {.fg = CYAN, .bg = BLACK, .un = 1} +#define _LWK {.fg = WHITE, .bg = BLACK, .un = 1} +#define _LKM {.fg = BLACK, .bg = MAGENTA, .un = 1} +#define _LKW {.fg = BLACK, .bg = WHITE, .un = 1} +#define _LBW {.fg = BLUE, .bg = WHITE, .un = 1} + +#define MAKE_TITLE_UNFOCUS RSC(UI).ATTR()[UI_MAKE_TITLE_UNFOCUS] +#define MAKE_TITLE_FOCUS RSC(UI).ATTR()[UI_MAKE_TITLE_FOCUS] +#define MAKE_BORDER_UNFOCUS RSC(UI).ATTR()[UI_MAKE_BORDER_UNFOCUS] +#define MAKE_BORDER_FOCUS RSC(UI).ATTR()[UI_MAKE_BORDER_FOCUS] +#define MAKE_SELECT_UNFOCUS RSC(UI).ATTR()[UI_MAKE_SELECT_UNFOCUS] +#define MAKE_SELECT_FOCUS RSC(UI).ATTR()[UI_MAKE_SELECT_FOCUS] +#define MAKE_PRINT_UNFOCUS RSC(UI).ATTR()[UI_MAKE_PRINT_UNFOCUS] +#define MAKE_PRINT_FOCUS RSC(UI).ATTR()[UI_MAKE_PRINT_FOCUS] +#define MAKE_PRINT_DROP RSC(UI).ATTR()[UI_MAKE_PRINT_DROP] + +typedef unsigned char ASCII; + +typedef struct { + ASCII *code; + ATTRIBUTE *attr; + CoordSize size; +} Layer; + +typedef struct { + CoordSize size; + Coordinate origin, + select; + CoordShift scroll; +} Matrix; + +typedef struct { + SCANKEY quick; + ATTRIBUTE *attr; + ASCII *item; + size_t length; +} TCell; + +typedef struct { + ASCII *comm; + size_t length; +} THover; + +typedef union { + void *pvoid; + unsigned long long *pullong; + signed long long *psllong; + unsigned long *pulong; + signed long *pslong; + unsigned int *puint; + signed int *psint; + + unsigned long long ullong; + signed long long sllong; + unsigned long ulong; + signed long slong; + + struct { + unsigned int uint[2]; + }; + struct { + signed int sint[2]; + }; +} DATA_TYPE; + +typedef struct _Grid { + TCell cell; + THover hover; + void (*Update)(struct _Grid *grid, DATA_TYPE data[]); + DATA_TYPE data[2]; +} TGrid; + +extern void Set_Data(TGrid*, DATA_TYPE data, unsigned int) ; +extern void Set_pVOID(TGrid*, void *pVOID, unsigned int) ; +extern void Set_pULLONG(TGrid*, unsigned long long *pULLONG, unsigned int) ; +extern void Set_pSLLONG(TGrid*, signed long long *pSLLONG, unsigned int) ; +extern void Set_pULONG(TGrid*, unsigned long *pULONG, unsigned int) ; +extern void Set_pSLONG(TGrid*, signed long *pSLONG, unsigned int) ; +extern void Set_pUINT(TGrid*, unsigned int *pUINT, unsigned int) ; +extern void Set_pSINT(TGrid*, signed int *pSINT, unsigned int) ; +extern void Set_ULLONG(TGrid*, unsigned long long _ULLONG, unsigned int) ; +extern void Set_SLLONG(TGrid*, signed long long _SLLONG, unsigned int) ; +extern void Set_ULONG(TGrid*, unsigned long _ULONG, unsigned int) ; +extern void Set_SLONG(TGrid*, signed long _SLONG, unsigned int) ; +extern void Set_UINT(TGrid*, unsigned int _UINT, unsigned int) ; +extern void Set_SINT(TGrid*, signed int _SINT, unsigned int) ; + +#define SET_DATA(_pGrid , _data , _order) \ + __builtin_choose_expr(__builtin_types_compatible_p ( \ + __typeof__(_data), __typeof__(DATA_TYPE)), \ + Set_Data, \ + __builtin_choose_expr(__builtin_types_compatible_p ( \ + __typeof__(_data), __typeof__(void *)) , \ + Set_pVOID, \ + __builtin_choose_expr(__builtin_types_compatible_p ( \ + __typeof__(_data), __typeof__(unsigned long long *)), \ + Set_pULLONG, \ + __builtin_choose_expr(__builtin_types_compatible_p ( \ + __typeof__(_data), __typeof__(signed long long *)), \ + Set_pSLLONG, \ + __builtin_choose_expr(__builtin_types_compatible_p ( \ + __typeof__(_data), __typeof__(unsigned long *)) , \ + Set_pULONG, \ + __builtin_choose_expr(__builtin_types_compatible_p ( \ + __typeof__(_data), __typeof__(signed long *)), \ + Set_pSLONG, \ + __builtin_choose_expr(__builtin_types_compatible_p ( \ + __typeof__(_data), __typeof__(unsigned int *)) , \ + Set_pUINT, \ + __builtin_choose_expr(__builtin_types_compatible_p ( \ + __typeof__(_data), __typeof__(signed int *)), \ + Set_pSINT, \ + __builtin_choose_expr(__builtin_types_compatible_p ( \ + __typeof__(_data), __typeof__(unsigned long long)) , \ + Set_ULLONG, \ + __builtin_choose_expr(__builtin_types_compatible_p ( \ + __typeof__(_data), __typeof__(signed long long)) , \ + Set_SLLONG, \ + __builtin_choose_expr(__builtin_types_compatible_p ( \ + __typeof__(_data), __typeof__(unsigned long)) , \ + Set_ULONG, \ + __builtin_choose_expr(__builtin_types_compatible_p ( \ + __typeof__(_data), __typeof__(signed long)) , \ + Set_SLONG, \ + __builtin_choose_expr(__builtin_types_compatible_p ( \ + __typeof__(_data), __typeof__(unsigned int)) , \ + Set_UINT, \ + __builtin_choose_expr(__builtin_types_compatible_p ( \ + __typeof__(_data), __typeof__(signed int)) , \ + Set_SINT, \ + (void)0))))))))))))))(_pGrid, _data, _order) + +typedef struct _Stock { + struct _Stock *next; + + unsigned long long id; + + struct Geometry { + Coordinate origin; + } geometry; +} Stock; + +typedef struct { + Stock *head, + *tail; +} StockList; + +typedef enum { + WINFLAG_NO_FLAGS = 0, + WINFLAG_NO_STOCK = 1, + WINFLAG_NO_SCALE = 2, + WINFLAG_NO_BORDER= 4, + WINFLAG_NO_VSB = 8 +} WINDOW_FLAG; + +typedef struct _Win { + Layer *layer; + + unsigned long long id; + + struct _Win *prev, + *next; + struct { + void (*Print)(struct _Win *win, void *list); + struct { + int (*Enter)(SCANKEY *scan, struct _Win *win); + void (*Escape)(struct _Win *win); + void (*Left)(struct _Win *win); + void (*Right)(struct _Win *win); + void (*Down)(struct _Win *win); + void (*Up)(struct _Win *win); + void (*Home)(struct _Win *win); + void (*End)(struct _Win *win); + void (*PgUp)(struct _Win *win); + void (*PgDw)(struct _Win *win); + void (*WinLeft)(struct _Win *win); + void (*WinRight)(struct _Win *win); + void (*WinDown)(struct _Win *win); + void (*WinUp)(struct _Win *win); + void (*Shrink)(struct _Win *win); + void (*Expand)(struct _Win *win); + } key; + + struct { + ATTRIBUTE select, + border, + title; + } color[2]; + + char *title; + } hook; + + Stock *stock; + Matrix matrix; + TGrid *grid; + size_t dim; + + struct { + size_t rowLen, + titleLen; + } lazyComp; + + WINDOW_FLAG flag; +} Window; + +typedef struct { + Window *head; +} WinList; + +typedef void (*TCELLFUNC)(Window*, void*); +typedef int (*KEYFUNC)(SCANKEY*, Window*); +typedef void (*WINFUNC)(Window*); +typedef char REGSTR[]; +typedef char *REGPTR; + +extern ASCII hSpace[]; +extern ASCII hBar[]; +extern ASCII hLine[]; + +extern Layer *sLayer, + *dLayer, + *wLayer; + +extern WinList winList; + +extern int GetKey(SCANKEY *scan, struct timespec *tsec) ; + +extern SCREEN_SIZE GetScreenSize(void) ; + +extern TGrid *GridHover(TGrid *pGrid, const char *comment) ; + +extern void HookCellFunc(TCELLFUNC *with, TCELLFUNC what) ; + +extern void HookKeyFunc(KEYFUNC *with, KEYFUNC what) ; + +extern void HookWinFunc(WINFUNC *with, WINFUNC what) ; + +extern void HookAttrib(ATTRIBUTE *with, ATTRIBUTE what) ; + +extern void HookString(REGSTR *with, REGSTR what) ; + +extern void HookPointer(REGPTR *with, REGPTR what) ; + +#define StoreWindow(win, with, what) \ +( \ + __builtin_choose_expr(__builtin_types_compatible_p ( \ + __typeof__(win->hook with), __typeof__(TCELLFUNC)),HookCellFunc,\ + __builtin_choose_expr(__builtin_types_compatible_p ( \ + __typeof__(win->hook with), __typeof__(KEYFUNC)), HookKeyFunc, \ + __builtin_choose_expr(__builtin_types_compatible_p ( \ + __typeof__(win->hook with), __typeof__(WINFUNC)), HookWinFunc, \ + __builtin_choose_expr(__builtin_types_compatible_p ( \ + __typeof__(win->hook with), __typeof__(ATTRIBUTE)), HookAttrib ,\ + __builtin_choose_expr(__builtin_types_compatible_p ( \ + __typeof__(win->hook with), __typeof__(REGSTR) ), HookString, \ + __builtin_choose_expr(__builtin_types_compatible_p ( \ + __typeof__(win->hook with), __typeof__(REGPTR) ), HookPointer, \ + (void)0)))))) \ + (&(win->hook with), what) \ +) + +#define GridCall_2xArg(gridCall, updateFunc) \ +({ \ + TGrid *pGrid = gridCall; \ + if (pGrid != NULL) \ + { \ + pGrid->Update = updateFunc; \ + pGrid->data[0].pvoid = NULL; \ + pGrid->data[1].pvoid = NULL; \ + } \ + pGrid; \ +}) + +#define GridCall_3xArg(gridCall, updateFunc, arg0) \ +({ \ + TGrid *pGrid = gridCall; \ + if (pGrid != NULL) \ + { \ + pGrid->Update = updateFunc; \ + SET_DATA(pGrid, arg0, 0); \ + pGrid->data[1].pvoid = NULL; \ + } \ + pGrid; \ +}) + +#define GridCall_4xArg(gridCall, updateFunc, arg0, arg1) \ +({ \ + TGrid *pGrid = gridCall; \ + if (pGrid != NULL) \ + { \ + pGrid->Update = updateFunc; \ + SET_DATA(pGrid, arg0, 0); \ + SET_DATA(pGrid, arg1, 1); \ + } \ + pGrid; \ +}) + +#define DISPATCH_GridCall(_1,_2,_3,_4,_CURSOR, ... ) _CURSOR + +#define GridCall(...) \ + DISPATCH_GridCall( __VA_ARGS__ ,GridCall_4xArg , \ + GridCall_3xArg , \ + GridCall_2xArg , \ + NULL)( __VA_ARGS__ ) + +#define IndexAt(col, row) ((CUINT) col + (CUINT) row) + +#define LayerAt( layer, plane, col, row ) \ + layer->plane[IndexAt(col, (row * layer->size.wth))] + +#define LayerFillAt(layer, col, row, len, source, attrib) \ +({ \ + memset(&LayerAt(layer, attr, col, row), attrib.value, (size_t) len); \ + memcpy(&LayerAt(layer, code, col, row), source, (size_t) len); \ +}) + +#define LayerCopyAt(layer, col, row, len, attrib, source) \ +({ \ + memcpy(&LayerAt(layer, attr, col, row), attrib, (size_t) len); \ + memcpy(&LayerAt(layer, code, col, row), source, (size_t) len); \ +}) + +#define TGridAt(win, col, row) \ + win->grid[col + (row * win->matrix.size.wth)] + +#define TCellAt(win, col, row) \ + TGridAt(win, col, row).cell + +extern void DestroyLayer(Layer *layer) ; + +extern void CreateLayer(Layer *layer, CoordSize size) ; + +#define ResetLayer(layer, attrib) \ +({ \ + memset(layer->attr, attrib.value, layer->size.wth * layer->size.hth); \ + memset(layer->code, 0x0, layer->size.wth * layer->size.hth); \ +}) + +#define ClearGarbage(_layer, _plane, _col, _row, _len, _value) \ +({ \ + memset(&LayerAt(_layer, _plane, _col, _row), _value, (size_t) _len); \ +}) + +extern void FillLayerArea(Layer *layer,CUINT col, CUINT row, + CUINT width, CUINT height, + ASCII *source, ATTRIBUTE attrib) ; + +extern void AllocCopyAttr(TCell *cell, ATTRIBUTE attrib[]) ; + +extern void AllocFillAttr(TCell *cell, ATTRIBUTE attrib) ; + +extern void AllocCopyItem(TCell *cell, ASCII *item) ; + +extern void FreeAllTCells(Window *win) ; + +#define StoreTCell(win, shortkey, item, attrib) \ +({ \ + TGrid *pGrid = NULL; \ + if (item != NULL) \ + { \ + win->dim++; \ + \ + win->grid = realloc(win->grid, sizeof(TGrid) * win->dim); \ + if (win->grid != NULL) \ + { \ + pGrid = &win->grid[win->dim - 1]; \ + pGrid->cell.quick.key = shortkey; \ + pGrid->cell.length = strlen((char *) item); \ + pGrid->hover.comm = NULL; \ + pGrid->hover.length = 0; \ + pGrid->Update = NULL; \ + pGrid->data[0].pvoid = NULL; \ + pGrid->data[1].pvoid = NULL; \ + \ + __builtin_choose_expr(__builtin_types_compatible_p( \ + __typeof__(attrib),__typeof__(ATTRIBUTE[])),AllocCopyAttr,\ + __builtin_choose_expr(__builtin_types_compatible_p( \ + __typeof__(attrib),__typeof__(ATTRIBUTE*)),AllocCopyAttr,\ + __builtin_choose_expr(__builtin_types_compatible_p( \ + __typeof__(attrib),__typeof__(ATTRIBUTE)),AllocFillAttr,\ + (void)0))) \ + (&pGrid->cell, attrib); \ + \ + AllocCopyItem(&pGrid->cell, (ASCII *) item); \ + } \ + } \ + pGrid; \ +}) + +extern void DestroyWindow(Window *win) ; + + +extern Window *CreateWindow_6xArg(Layer *layer, unsigned long long id, + CUINT width, CUINT height, + CUINT oCol, CUINT oRow) ; + +extern Window *CreateWindow_7xArg(Layer *layer, unsigned long long id, + CUINT width, CUINT height, + CUINT oCol, CUINT oRow, WINDOW_FLAG flag) ; + +#define DISPATCH_CreateWindow(_1,_2,_3,_4,_5,_6,_7, _CURSOR, ... ) _CURSOR + +#define CreateWindow(...) \ + DISPATCH_CreateWindow( __VA_ARGS__ , \ + CreateWindow_7xArg , \ + CreateWindow_6xArg , \ + NULL, \ + NULL, \ + NULL, \ + NULL, \ + NULL)( __VA_ARGS__ ) + +extern void RemoveWindow(Window *win, WinList *list) ; + +extern void AppendWindow(Window *win, WinList *list) ; + +extern void DestroyAllWindows(WinList *list) ; + +#define RemoveWinList(win, list) RemoveNodeFromList(win, list) + +#define AppendWinList(win, list) AppendNodeToList(win, list) + +extern void AnimateWindow(int rotate, WinList *list) ; + +extern Window *SearchWinListById(unsigned long long id, WinList *list) ; + +extern void PrintContent(Window *win, WinList *list, CUINT col, CUINT row) ; + +extern void ForEachCellPrint(Window *win, WinList *list) ; + +extern void EraseWindowWithBorder(Window *win) ; + +extern void PrintLCD( Layer *layer, CUINT col, CUINT row, + int len, char *pStr, ATTRIBUTE lcdColor ) ; + +extern void MotionReset_Win(Window *win) ; + +extern void MotionLeft_Win(Window *win) ; + +extern void MotionRight_Win(Window *win) ; + +extern void MotionUp_Win(Window *win) ; + +extern void MotionDown_Win(Window *win) ; + +extern void MotionHome_Win(Window *win) ; + +extern void MotionEnd_Win(Window *win) ; + +extern void MotionTop_Win(Window *win) ; + +extern void MotionBottom_Win(Window *win) ; + +extern void MotionPgUp_Win(Window *win) ; + +extern void MotionPgDw_Win(Window *win) ; + +extern void MotionOriginLeft_Win(Window *win) ; + +extern void MotionOriginRight_Win(Window *win) ; + +extern void MotionOriginUp_Win(Window *win) ; + +extern void MotionOriginDown_Win(Window *win) ; + +extern void MotionShrink_Win(Window *win) ; + +extern void MotionExpand_Win(Window *win) ; + +extern void MotionUp_Wheel(Window *win) ; + +extern void MotionDown_Wheel(Window *win) ; + +extern void MotionPgUp_Wheel(Window *win) ; + +extern void MotionPgDw_Wheel(Window *win) ; + +extern void MotionHome_Wheel(Window *win) ; + +extern void MotionEnd_Wheel(Window *win) ; + +extern void ReScaleAllWindows(WinList *list) ; + +extern int Motion_Trigger(SCANKEY *scan, Window *win, WinList *list) ; + +extern void PrintWindowStack(WinList *winList) ; + +extern void WindowsUpdate(WinList *winList) ; + +#define EraseTCell_Menu(win) \ +({ \ + CoordShift shift = { \ + .horz = win->matrix.scroll.horz + win->matrix.select.col,\ + .vert = win->matrix.scroll.vert + row \ + }; \ + Coordinate cell = { \ + .col = (win->matrix.origin.col \ + + (win->matrix.select.col \ + * TCellAt(win, shift.horz, shift.vert).length)),\ + .row = (win->matrix.origin.row + row) \ + }; \ + memset(&LayerAt(win->layer, attr, cell.col, cell.row), \ + RSC(UI).ATTR()[UI_WIN_MENU_ERASE_CELL].value, \ + TCellAt(win, shift.horz, shift.vert).length); \ + memset(&LayerAt(win->layer, code, cell.col, cell.row), \ + RSC(UI).ATTR()[UI_WIN_MENU_ERASE_CELL].value, \ + TCellAt(win, shift.horz, shift.vert).length); \ +}) + +extern void ForEachCellPrint_Drop(Window *win, void *plist) ; + +extern int Enter_StickyCell(SCANKEY *scan, Window *win) ; + +extern int MotionEnter_Cell(SCANKEY *scan, Window *win) ; + +extern void MotionEnd_Cell(Window *win) ; + +extern void MotionLeft_Menu(Window *win) ; + +extern void MotionRight_Menu(Window *win) ; + +extern void MotionUp_Menu(Window *win) ; + +extern void MotionDown_Menu(Window *win) ; + +extern void MotionHome_Menu(Window *win) ; + +extern void MotionEnd_Menu(Window *win) ; + +typedef union { + unsigned long long qword; + struct { + unsigned int lo, hi; + } dword; + struct { + unsigned short lo[2], + hi[2]; + } word; +} DATA; + +typedef struct _Card { + struct _Card *next; + + Coordinate origin; + struct { + void (*Layout)(Layer *layer, struct _Card *card); + void (*Draw)(Layer *layer, struct _Card *card); + } hook; + DATA data; +} Card; + +typedef struct { + Card *head, + *tail; +} CardList; + +typedef void (*CARDFUNC)(Layer*, Card*); + +extern Card *CreateCard(void) ; + +extern void AppendCard(Card *card, CardList *list) ; + +extern void DestroyAllCards(CardList *list) ; + +extern void HookCardFunc(CARDFUNC *with, CARDFUNC what) ; + +#define StoreCard(card, with, what) \ +( \ + __builtin_choose_expr(__builtin_types_compatible_p( \ + __typeof__(card->hook with), __typeof__(CARDFUNC)),HookCardFunc,\ + (void)0) \ + (&(card->hook with), what) \ +) + +extern void FreeAll(char *buffer) ; + +__typeof__ (errno) AllocAll(char **buffer) ; + +extern unsigned int WriteConsole(SCREEN_SIZE drawSize) ; + +extern void _TERMINAL_IN(void) ; +extern void _TERMINAL_OUT(void) ; +#define TERMINAL(IO) _TERMINAL_##IO() + +extern void _LOCALE_IN(void) ; +extern void _LOCALE_OUT(void) ; +#define LOCALE(IO) _LOCALE_##IO() + +extern void LocaleTo(int category) ; + +enum LOCALES { + LOC_EN, + LOC_FR, + LOC_CNT +}; + +extern enum LOCALES AppLoc; +extern locale_t SysLoc; + +#define SYS_LOCALE() (SysLoc) +#define GET_LOCALE() (AppLoc) +#define SET_LOCALE(_apploc) \ +({ \ + AppLoc = _apploc; \ + LocaleTo(LC_ALL); \ +}) + +enum THEMES { + THM_DFLT, + THM_USR1, + THM_USR2, + THM_CNT +}; + +extern enum THEMES AppThm; + +#define GET_THEME() (AppThm) +#define SET_THEME(_app_thm) \ +({ \ + AppThm = _app_thm; \ +}) + +enum DUMP_METHOD { + DUMP_TO_JSON, + DUMP_TO_ANSI +}; + +extern void StopDump(void) ; +extern __typeof__ (errno) StartDump( char *dumpFormat, int tickReset, + enum DUMP_METHOD method ) ; +extern void AbortDump(void) ; +extern unsigned char DumpStatus(void) ; +void ANSI_Header(void) ; +void JSON_Header(void) ; +void ANSI_Page(char *inStr, int outSize) ; +void JSON_Page(char *inStr, int outSize) ; +void ANSI_Break(void) ; +void JSON_Break(void) ; + +extern __typeof__ (errno) SaveGeometries(char*) ; +extern __typeof__ (errno) LoadGeometries(char*) ; + +#if defined(UBENCH) && UBENCH == 1 + #define UI_Draw_uBenchmark(layer) \ + ({ \ + char str[32]; \ + int len = snprintf(str, 20+1, "%llu", UBENCH_METRIC(0)); \ + if (len > 0) \ + LayerFillAt(layer, 0, 2, len, str, RSC(UI).ATTR()[UI_LAYOUT_UBENCH]); \ + }) +#else + #define UI_Draw_uBenchmark(layer) {} +#endif /* UBENCH */ diff --git a/corefreq.h b/x86_64/corefreq.h similarity index 94% rename from corefreq.h rename to x86_64/corefreq.h index bb18d516..ad9e2396 100644 --- a/corefreq.h +++ b/x86_64/corefreq.h @@ -1,6 +1,6 @@ /* * CoreFreq - * Copyright (C) 2015-2023 CYRIL COURTIAT + * Copyright (C) 2015-2024 CYRIL COURTIAT * Licenses: GPL2 */ @@ -282,7 +282,9 @@ typedef struct EFCR __attribute__ ((aligned (8))), EFER __attribute__ ((aligned (8))), XCR0 __attribute__ ((aligned (8))), - SYSCFG __attribute__ ((aligned (8))); + XSS __attribute__ ((aligned (8))), + SYSCFG __attribute__ ((aligned (8))), + HWCR __attribute__ ((aligned (8))); } SystemRegister; CPUID_STRUCT CpuID[CPUID_MAX_FUNC]; @@ -301,11 +303,18 @@ typedef struct unsigned long long Error; + #ifdef __GLIBC__ struct { struct random_data data; char state[128]; int value[2]; } Random; + #else + struct { + char state[128]; + int value[2]; + } Random; + #endif /* __GLIBC__ */ struct { unsigned long long inside, @@ -349,7 +358,17 @@ typedef struct WDT : 29-28, TM1 : 31-29, TM2 : 33-31, - _pad64 : 64-33; + L1_NPP_Prefetch : 34-33, + L1_Scrubbing : 35-34, + L2_AMP_Prefetch : 36-35, + L2_NLP_Prefetch : 37-36, + L1_Stride_Pf : 38-37, + L1_Region_Pf : 39-38, + L1_Burst_Pf : 40-39, + L2_Stream_HW_Pf : 41-40, + L2_UpDown_Pf : 42-41, + LLC_Streamer : 43-42, + _pad64 : 64-43; } Technology; struct { @@ -394,7 +413,12 @@ typedef struct DRAM_Scrambler : 10-8, TSME : 12-10, DDPD_U_DIS : 14-12, - _UnusedMechBits : 64-14; + XPROC_LEAK : 16-14, + AGENPICK : 18-16, + OC_UTILIZED : 20-18, + OC_UNDERVOLT : 22-20, + OC_UNLOCKED : 24-22, + _UnusedMechBits : 64-24; } Mechanisms; enum THERMAL_FORMULAS thermalFormula; diff --git a/corefreqd.c b/x86_64/corefreqd.c similarity index 98% rename from corefreqd.c rename to x86_64/corefreqd.c index 1c439e2f..f57c804f 100644 --- a/corefreqd.c +++ b/x86_64/corefreqd.c @@ -1,6 +1,6 @@ /* * CoreFreq - * Copyright (C) 2015-2023 CYRIL COURTIAT + * Copyright (C) 2015-2024 CYRIL COURTIAT * Licenses: GPL2 */ @@ -37,7 +37,7 @@ sysconf(_SC_PAGESIZE) > 0 ? sysconf(_SC_PAGESIZE) : 4096 \ ) -/* §8.10.6.7 Place Locks and Semaphores in Aligned, 128-Byte Blocks of Memory */ +/*Ch:8.10.6.7 Place Locks and Semaphores in Aligned, 128-Byte Blocks of Memory*/ static BitCC roomSeed __attribute__ ((aligned (16))) = InitCC(0x0); static BitCC roomCore __attribute__ ((aligned (16))) = InitCC(0x0); static BitCC roomClear __attribute__ ((aligned (16))) = InitCC(0x0); @@ -388,7 +388,7 @@ static void (*ComputeVoltage_None_Matrix[4])( struct FLIP_FLOP*, static void ComputeVoltage_Intel_Core2( struct FLIP_FLOP *CFlip, RO(SHM_STRUCT) *RO(Shm), unsigned int cpu ) -{ /* Intel Core 2 Extreme Datasheet §3.3-Table 2 */ +{ /* Intel Core 2 Extreme Datasheet Chap. 3.3-Table 2 */ COMPUTE_VOLTAGE(INTEL_CORE2, CFlip->Voltage.Vcore, CFlip->Voltage.VID); @@ -608,7 +608,7 @@ static void (*ComputeVoltage_AMD_Matrix[4])( struct FLIP_FLOP*, static void ComputeVoltage_AMD_0Fh( struct FLIP_FLOP *CFlip, RO(SHM_STRUCT) *RO(Shm), unsigned int cpu ) -{ /* AMD BKDG Family 0Fh §10.6 Table 70 */ +{ /* AMD BKDG Family 0Fh Chap 10.6 Table 70 */ COMPUTE_VOLTAGE(AMD_0Fh, CFlip->Voltage.Vcore, CFlip->Voltage.VID); @@ -1087,7 +1087,7 @@ static void *Core_Cycle(void *arg) } if (Quiet & 0x100) { - printf(" Thread [%lx] Init CYCLE %03u\n", tid, cpu); + printf(" Thread [%lx] Init CYCLE %03u\n", (long) tid, cpu); fflush(stdout); } BITSET_CC(BUS_LOCK, roomSeed, cpu); @@ -1241,7 +1241,7 @@ static void *Core_Cycle(void *arg) BITCLR_CC(BUS_LOCK, roomSeed, cpu); EXIT: if (Quiet & 0x100) { - printf(" Thread [%lx] %s CYCLE %03u\n", tid, + printf(" Thread [%lx] %s CYCLE %03u\n", (long) tid, BITVAL(RO(Core)->OffLine, OS) ? "Offline" : "Shutdown", cpu); fflush(stdout); @@ -1270,8 +1270,12 @@ void SliceScheduling( RO(SHM_STRUCT) *RO(Shm), break; case RAND_SMT: do { + #ifdef __GLIBC__ if (random_r(&RO(Shm)->Cpu[cpu].Slice.Random.data, &RO(Shm)->Cpu[cpu].Slice.Random.value[0]) == 0) + #else + RO(Shm)->Cpu[cpu].Slice.Random.value[0] = (int) random(); + #endif /* __GLIBC__ */ { seek = RO(Shm)->Cpu[cpu].Slice.Random.value[0] % RO(Shm)->Proc.CPU.Count; @@ -1332,7 +1336,7 @@ static void *Child_Thread(void *arg) free(comm); } if (Quiet & 0x100) { - printf(" Thread [%lx] Init CHILD %03u\n", tid, cpu); + printf(" Thread [%lx] Init CHILD %03u\n", (long) tid, cpu); fflush(stdout); } @@ -1381,7 +1385,7 @@ static void *Child_Thread(void *arg) RESET_Slice(Cpu->Slice); EXIT: if (Quiet & 0x100) { - printf(" Thread [%lx] %s CHILD %03u\n", tid, + printf(" Thread [%lx] %s CHILD %03u\n", (long) tid, BITVAL(Cpu->OffLine, OS) ? "Offline" : "Shutdown",cpu); fflush(stdout); } @@ -1614,6 +1618,14 @@ void Technology_Update( RO(SHM_STRUCT) *RO(Shm), RW(Proc)->L1_HW_IP_Prefetch, RO(Proc)->DCU_Mask); + RO(Shm)->Proc.Technology.L1_NPP_Prefetch = BITCMP_CC(LOCKLESS, + RW(Proc)->L1_NPP_Prefetch, + RO(Proc)->DCU_Mask); + + RO(Shm)->Proc.Technology.L1_Scrubbing = BITWISEAND_CC(LOCKLESS, + RW(Proc)->L1_Scrubbing, + RO(Proc)->PCORE_Mask) != 0; + RO(Shm)->Proc.Technology.L2_HW_Prefetch = BITCMP_CC(LOCKLESS, RW(Proc)->L2_HW_Prefetch, RO(Proc)->DCU_Mask); @@ -1622,6 +1634,38 @@ void Technology_Update( RO(SHM_STRUCT) *RO(Shm), RW(Proc)->L2_HW_CL_Prefetch, RO(Proc)->DCU_Mask); + RO(Shm)->Proc.Technology.L2_AMP_Prefetch = BITWISEAND_CC(LOCKLESS, + RW(Proc)->L2_AMP_Prefetch, + RO(Proc)->PCORE_Mask) != 0; + + RO(Shm)->Proc.Technology.L2_NLP_Prefetch = BITWISEAND_CC(LOCKLESS, + RW(Proc)->L2_NLP_Prefetch, + RO(Proc)->ECORE_Mask) != 0; + + RO(Shm)->Proc.Technology.L1_Stride_Pf = BITCMP_CC(LOCKLESS, + RW(Proc)->L1_Stride_Pf, + RO(Proc)->DCU_Mask); + + RO(Shm)->Proc.Technology.L1_Region_Pf = BITCMP_CC(LOCKLESS, + RW(Proc)->L1_Region_Pf, + RO(Proc)->DCU_Mask); + + RO(Shm)->Proc.Technology.L1_Burst_Pf = BITCMP_CC(LOCKLESS, + RW(Proc)->L1_Burst_Pf, + RO(Proc)->DCU_Mask); + + RO(Shm)->Proc.Technology.L2_Stream_HW_Pf = BITCMP_CC(LOCKLESS, + RW(Proc)->L2_Stream_HW_Pf, + RO(Proc)->DCU_Mask); + + RO(Shm)->Proc.Technology.L2_UpDown_Pf = BITCMP_CC(LOCKLESS, + RW(Proc)->L2_UpDown_Pf, + RO(Proc)->DCU_Mask); + + RO(Shm)->Proc.Technology.LLC_Streamer = BITWISEAND_CC(LOCKLESS, + RW(Proc)->LLC_Streamer, + RO(Proc)->ECORE_Mask) != 0; + RO(Shm)->Proc.Technology.PowerMgmt = BITCMP_CC(LOCKLESS, RW(Proc)->PowerMgmt, RO(Proc)->PowerMgmt_Mask); @@ -1833,6 +1877,18 @@ void Mitigation_1st_Stage( RO(SHM_STRUCT) *RO(Shm), RW(Proc)->PBRSB_NO, RO(Proc)->ARCH_CAP_Mask ), + OC_UTILIZED = BITCMP_CC(LOCKLESS, + RW(Proc)->OC_UTILIZED, + RO(Proc)->ARCH_CAP_Mask), + + OC_UNDERVOLT = BITCMP_CC(LOCKLESS, + RW(Proc)->OC_UNDERVOLT, + RO(Proc)->ARCH_CAP_Mask), + + OC_UNLOCKED = BITCMP_CC(LOCKLESS, + RW(Proc)->OC_UNLOCKED, + RO(Proc)->ARCH_CAP_Mask), + IPRED_DIS_U = BITCMP_CC(LOCKLESS, RW(Proc)->IPRED_DIS_U, RO(Proc)->SPEC_CTRL_Mask), @@ -1973,6 +2029,21 @@ void Mitigation_1st_Stage( RO(SHM_STRUCT) *RO(Shm), + (2 * PBRSB_NO) ); + RO(Shm)->Proc.Mechanisms.OC_UTILIZED = ( + RO(Shm)->Proc.Features.ExtFeature.EDX.IA32_ARCH_CAP + + (2 * OC_UTILIZED) + ); + + RO(Shm)->Proc.Mechanisms.OC_UNDERVOLT = ( + RO(Shm)->Proc.Features.ExtFeature.EDX.IA32_ARCH_CAP + + (2 * OC_UNDERVOLT) + ); + + RO(Shm)->Proc.Mechanisms.OC_UNLOCKED = ( + RO(Shm)->Proc.Features.ExtFeature.EDX.IA32_ARCH_CAP + + (2 * OC_UNLOCKED) + ); + RO(Shm)->Proc.Mechanisms.IPRED_DIS_U = ( (RO(Shm)->Proc.Features.ExtFeature.EAX.MaxSubLeaf >= 2) && (RO(Shm)->Proc.Features.ExtFeature_Leaf2_EDX.IPRED_SPEC_CTRL == 1) @@ -2038,6 +2109,31 @@ void Mitigation_1st_Stage( RO(SHM_STRUCT) *RO(Shm), RO(Shm)->Proc.Features.leaf80000008.EBX.STIBP == 1 ); RO(Shm)->Proc.Mechanisms.BTC_NOBR += (2 * BTC_NOBR); + + switch (RO(Shm)->Proc.ArchID) { + case AMD_EPYC_Rome_CPK: + case AMD_Zen2_Renoir: + case AMD_Zen2_LCN: + case AMD_Zen2_MTS: + case AMD_Zen2_Ariel: + case AMD_Zen2_Jupiter: + case AMD_Zen2_Galileo: + case AMD_Zen2_MDN: + RO(Shm)->Proc.Mechanisms.XPROC_LEAK = \ + BITCMP_CC(LOCKLESS, + RW(Proc)->XPROC_LEAK, + RO(Proc)->XPROC_LEAK_Mask) ? 0b11 : 0b10; + + RO(Shm)->Proc.Mechanisms.AGENPICK = \ + BITCMP_CC(LOCKLESS, + RW(Proc)->AGENPICK, + RO(Proc)->BTC_NOBR_Mask) ? 0b11 : 0b10; + break; + default: + RO(Shm)->Proc.Mechanisms.XPROC_LEAK = 0; + RO(Shm)->Proc.Mechanisms.AGENPICK = 0; + break; + } } } @@ -7016,9 +7112,11 @@ void PCI_AMD(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core), case DID_AMD_17H_ZEN2_APU_NB_IOMMU: case DID_AMD_17H_FIREFLIGHT_NB_IOMMU: case DID_AMD_17H_ARDEN_NB_IOMMU: + case DID_AMD_17H_JUPITER_NB_IOMMU: case DID_AMD_19H_ZEN3_RMB_NB_IOMMU: case DID_AMD_19H_ZEN4_RPL_NB_IOMMU: case DID_AMD_19H_ZEN4_GNA_NB_IOMMU: + case DID_AMD_19H_ZEN4_PHX_NB_IOMMU: AMD_17h_IOMMU(RO(Shm), RO(Proc)); break; case DID_AMD_17H_ZEPPELIN_DF_UMC: @@ -7030,11 +7128,13 @@ void PCI_AMD(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core), case DID_AMD_17H_RAVEN2_DF_UMC: case DID_AMD_17H_FIREFLIGHT_DF_UMC: case DID_AMD_17H_ARDEN_DF_UMC: + case DID_AMD_17H_JUPITER_DF_UMC: case DID_AMD_19H_VERMEER_DF_UMC: case DID_AMD_19H_CEZANNE_DF_UMC: case DID_AMD_19H_REMBRANDT_DF_UMC: case DID_AMD_19H_RAPHAEL_DF_UMC: case DID_AMD_19H_GENOA_DF_UMC: + case DID_AMD_19H_PHOENIX_DF_UMC: AMD_17h_UMC(RO(Shm), RO(Proc)); AMD_17h_CAP(RO(Shm), RO(Proc), RO(Core)); SET_CHIPSET(IC_ZEN); @@ -7228,6 +7328,7 @@ void Topology(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) **RO(Core), case AMD_Zen2_MTS: case AMD_Zen2_Ariel: case AMD_Zen2_Jupiter: + case AMD_Zen2_Galileo: case AMD_Zen2_MDN: case AMD_Zen3_VMR: case AMD_Zen3_CZN: @@ -7238,7 +7339,10 @@ void Topology(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) **RO(Core), case AMD_Zen4_Genoa: case AMD_Zen4_RPL: case AMD_Zen4_PHX: + case AMD_Zen4_HWK: + case AMD_Zen4_PHX2: case AMD_Zen4_Bergamo: + case AMD_Zen4_STP: case AMD_Family_17h: case Hygon_Family_18h: case AMD_Family_19h: @@ -7341,8 +7445,14 @@ void SystemRegisters( RO(SHM_STRUCT) *RO(Shm), RO(CORE) **RO(Core), RO(Shm)->Cpu[cpu].SystemRegister.XCR0 = \ RO(Core, AT(cpu))->SystemRegister.XCR0; + RO(Shm)->Cpu[cpu].SystemRegister.XSS = \ + RO(Core, AT(cpu))->SystemRegister.XSS; + RO(Shm)->Cpu[cpu].SystemRegister.SYSCFG = \ RO(Core, AT(cpu))->SystemRegister.SYSCFG; + + RO(Shm)->Cpu[cpu].SystemRegister.HWCR = \ + RO(Core, AT(cpu))->SystemRegister.HWCR.value; } void SysGate_OS_Driver(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc)) @@ -8096,7 +8206,7 @@ static void Pkg_ComputeVoltage_Intel_SoC(struct PKG_FLIP_FLOP *PFlip) } static void Pkg_ComputeVoltage_Intel_SNB(struct PKG_FLIP_FLOP *PFlip) -{ /* Intel 2nd Generation Datasheet Vol-1 §7.4 Table 7-1 */ +{ /* Intel 2nd Generation Datasheet Vol-1 Chap. 7.4 Table 7-1 */ COMPUTE_VOLTAGE(INTEL_SNB, PFlip->Voltage.CPU, PFlip->Voltage.VID.CPU); @@ -8223,7 +8333,11 @@ REASON_CODE Core_Manager(REF *Ref) unsigned int cpu = 0; pthread_t tid = pthread_self(); + #ifdef __GLIBC__ RO(Shm)->App.Svr = tid; + #else + RO(Shm)->App.Svr = getpid(); + #endif if (ServerFollowService(&localService, &RO(Shm)->Proc.Service, tid) == 0) { pthread_setname_np(tid, "corefreqd-pmgr"); @@ -8708,11 +8822,14 @@ REASON_CODE Child_Manager(REF *Ref) : : "%rax", "%rcx", "%rdx", "cc", "memory" ); + #ifdef __GLIBC__ initstate_r( seed32, RO(Shm)->Cpu[cpu].Slice.Random.state, sizeof(RO(Shm)->Cpu[cpu].Slice.Random.state), &RO(Shm)->Cpu[cpu].Slice.Random.data ); - + #else + initstate(seed32, RO(Shm)->Cpu[cpu].Slice.Random.state, 128); + #endif if (!Arg[cpu].TID) { /* Add this child thread. */ Arg[cpu].Ref = Ref; @@ -8879,7 +8996,7 @@ REASON_CODE Shm_Manager(FD *fd, RO(PROC) *RO(Proc), RW(PROC) *RW(Proc), /* Welcomes with brand and per CPU base clock. */ if (Quiet & 0x001) { printf( "CoreFreq Daemon %s" \ - " Copyright (C) 2015-2023 CYRIL COURTIAT\n", + " Copyright (C) 2015-2024 CYRIL COURTIAT\n", COREFREQ_VERSION ); } if (Quiet & 0x010) { diff --git a/corefreqk.c b/x86_64/corefreqk.c similarity index 93% rename from corefreqk.c rename to x86_64/corefreqk.c index 02c67d13..60cc1191 100644 --- a/corefreqk.c +++ b/x86_64/corefreqk.c @@ -1,10 +1,10 @@ /* * CoreFreq - * Copyright (C) 2015-2023 CYRIL COURTIAT + * Copyright (C) 2015-2024 CYRIL COURTIAT * Licenses: GPL2 * + * Infliximab [11.17.2023] * Vedolizumab [05.25.2023] - * First injection * * CYRIL INGENIERIE[11.30.2022] * Company closed down @@ -40,7 +40,9 @@ #endif /* KERNEL_VERSION(4, 11, 0) */ #include #include +#ifdef CONFIG_HAVE_NMI #include +#endif #ifdef CONFIG_XEN #include #endif /* CONFIG_XEN */ @@ -197,6 +199,14 @@ static signed short L1_HW_IP_PREFETCH_Disable = -1; module_param(L1_HW_IP_PREFETCH_Disable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); MODULE_PARM_DESC(L1_HW_IP_PREFETCH_Disable, "Disable L1 HW IP Prefetcher"); +static signed short L1_NPP_PREFETCH_Disable = -1; +module_param(L1_NPP_PREFETCH_Disable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(L1_NPP_PREFETCH_Disable, "Disable L1 NPP Prefetcher"); + +static signed short L1_Scrubbing_Enable = -1; +module_param(L1_Scrubbing_Enable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(L1_Scrubbing_Enable, "Enable L1 Scrubbing"); + static signed short L2_HW_PREFETCH_Disable = -1; module_param(L2_HW_PREFETCH_Disable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); MODULE_PARM_DESC(L2_HW_PREFETCH_Disable, "Disable L2 HW Prefetcher"); @@ -205,6 +215,38 @@ static signed short L2_HW_CL_PREFETCH_Disable = -1; module_param(L2_HW_CL_PREFETCH_Disable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); MODULE_PARM_DESC(L2_HW_CL_PREFETCH_Disable, "Disable L2 HW CL Prefetcher"); +static signed short L2_AMP_PREFETCH_Disable = -1; +module_param(L2_AMP_PREFETCH_Disable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(L2_AMP_PREFETCH_Disable, "Adaptive Multipath Probability"); + +static signed short L2_NLP_PREFETCH_Disable = -1; +module_param(L2_NLP_PREFETCH_Disable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(L2_NLP_PREFETCH_Disable, "Disable L2 NLP Prefetcher"); + +static signed short L1_STRIDE_PREFETCH_Disable = -1; +module_param(L1_STRIDE_PREFETCH_Disable, short,S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(L1_STRIDE_PREFETCH_Disable, "Disable L1 Stride Prefetcher"); + +static signed short L1_REGION_PREFETCH_Disable = -1; +module_param(L1_REGION_PREFETCH_Disable, short,S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(L1_REGION_PREFETCH_Disable, "Disable L1 Region Prefetcher"); + +static signed short L1_BURST_PREFETCH_Disable = -1; +module_param(L1_BURST_PREFETCH_Disable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(L1_BURST_PREFETCH_Disable, "Disable L1 Burst Prefetcher"); + +static signed short L2_STREAM_PREFETCH_Disable = -1; +module_param(L2_STREAM_PREFETCH_Disable, short,S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(L2_STREAM_PREFETCH_Disable, "Disable L2 Stream Prefetcher"); + +static signed short L2_UPDOWN_PREFETCH_Disable = -1; +module_param(L2_UPDOWN_PREFETCH_Disable, short,S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(L2_UPDOWN_PREFETCH_Disable, "Disable L2 Up/Down Prefetcher"); + +static signed short LLC_Streamer_Disable = -1; +module_param(LLC_Streamer_Disable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(LLC_Streamer_Disable, "Disable LLC Streamer"); + static signed short SpeedStep_Enable = -1; module_param(SpeedStep_Enable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); MODULE_PARM_DESC(SpeedStep_Enable, "Enable SpeedStep"); @@ -330,8 +372,13 @@ static signed short R2H_Disable = -1; module_param(R2H_Disable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); MODULE_PARM_DESC(R2H_Disable, "Disable Race to Halt"); +#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 17, 0) +static unsigned long Clear_Events = 0; +module_param(Clear_Events, ulong, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +#else static unsigned long long Clear_Events = 0; module_param(Clear_Events, ullong, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +#endif MODULE_PARM_DESC(Clear_Events, "Clear Thermal and Power Events"); static unsigned int ThermalPoint_Count = 0; @@ -414,6 +461,14 @@ static signed short Mech_BTC_NOBR = -1; module_param(Mech_BTC_NOBR, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); MODULE_PARM_DESC(Mech_BTC_NOBR, "Mitigation Mechanism BTC-NOBR"); +static signed short Mech_XPROC_LEAK = -1; +module_param(Mech_XPROC_LEAK, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(Mech_XPROC_LEAK, "Mitigation Mech. Cross Processor Leak"); + +static signed short Mech_AGENPICK = -1; +module_param(Mech_AGENPICK, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); +MODULE_PARM_DESC(Mech_AGENPICK, "Mitigation Mech. LsCfgDisAgenPick"); + static signed short WDT_Enable = -1; module_param(WDT_Enable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH); MODULE_PARM_DESC(WDT_Enable, "Watchdog Hardware Timer"); @@ -454,8 +509,12 @@ static struct { /*MANDATORY*/ .init = CoreFreqK_Policy_Init, /*MANDATORY*/ .verify = CoreFreqK_Policy_Verify, /*MANDATORY*/ .setpolicy = CoreFreqK_SetPolicy, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0) .bios_limit= CoreFreqK_Bios_Limit, .set_boost = CoreFreqK_SetBoost +#else + .bios_limit= CoreFreqK_Bios_Limit +#endif }, .FreqGovernor = { .name = "corefreq-policy", @@ -528,7 +587,7 @@ static long CoreFreqK_Power_Scope(int scope) } } -unsigned int FixMissingRatioAndFrequency(unsigned int r32, CLOCK *pClock) +static unsigned int FixMissingRatioAndFrequency(unsigned int r32, CLOCK *pClock) { unsigned long long r64 = r32; if (PUBLIC(RO(Proc))->Features.Factory.Freq != 0) @@ -653,11 +712,11 @@ static long CoreFreqK_Register_ClockSource(unsigned int cpu) return rc; } -void VendorFromCPUID( char *pVendorID, unsigned int *pLargestFunc, +static void VendorFromCPUID(char *pVendorID, unsigned int *pLargestFunc, unsigned int *pCRC, enum HYPERVISOR *pHypervisor, - unsigned long leaf, unsigned long subLeaf ) + unsigned long leaf, unsigned long subLeaf) { - struct { +static const struct { char *vendorID; size_t vendorLen; enum CRC_MANUFACTURER mfrCRC; @@ -672,6 +731,7 @@ void VendorFromCPUID( char *pVendorID, unsigned int *pLargestFunc, {VENDOR_VMWARE ,__builtin_strlen(VENDOR_VMWARE),CRC_VMWARE,HYPERV_VMWARE}, {VENDOR_HYPERV ,__builtin_strlen(VENDOR_HYPERV),CRC_HYPERV,HYPERV_HYPERV} }; + const unsigned int mfrSize = sizeof(mfrTbl) / sizeof(mfrTbl[0]); unsigned int eax = 0x0, ebx = 0x0, ecx = 0x0, edx = 0x0; /*DWORD Only!*/ __asm__ volatile @@ -709,7 +769,7 @@ void VendorFromCPUID( char *pVendorID, unsigned int *pLargestFunc, (*pLargestFunc) = eax; - for (eax = 0; eax < sizeof(mfrTbl) / sizeof(mfrTbl[0]); eax++) { + for (eax = 0; eax < mfrSize; eax++) { if (!strncmp(pVendorID, mfrTbl[eax].vendorID, mfrTbl[eax].vendorLen)) { (*pCRC) = mfrTbl[eax].mfrCRC; @@ -720,7 +780,7 @@ void VendorFromCPUID( char *pVendorID, unsigned int *pLargestFunc, } } -signed int SearchArchitectureID(void) +static signed int SearchArchitectureID(void) { signed int id; for (id = ARCHITECTURES - 1; id > 0; id--) @@ -742,7 +802,7 @@ signed int SearchArchitectureID(void) return id; } -void BrandCleanup(char *pBrand, char inOrder[]) +static void BrandCleanup(char *pBrand, char inOrder[]) { unsigned long ix, jx; for (jx = 0; jx < BRAND_LENGTH; jx++) { @@ -757,7 +817,7 @@ void BrandCleanup(char *pBrand, char inOrder[]) } } -void BrandFromCPUID(char *buffer) +static void BrandFromCPUID(char *buffer) { BRAND Brand; unsigned long ix; @@ -792,7 +852,7 @@ void BrandFromCPUID(char *buffer) } } -unsigned int Intel_Brand(char *pBrand, char buffer[]) +static unsigned int Intel_Brand(char *pBrand, char buffer[]) { unsigned int ix, frequency = 0, multiplier = 0; @@ -818,14 +878,14 @@ unsigned int Intel_Brand(char *pBrand, char buffer[]) if (multiplier > 0) { if (buffer[ix - 3] == '.') { - frequency = (int) (buffer[ix - 4] - '0') * multiplier; - frequency += (int) (buffer[ix - 2] - '0') * (multiplier / 10); - frequency += (int) (buffer[ix - 1] - '0') * (multiplier / 100); + frequency = (int) (buffer[ix-4] - '0') * multiplier; + frequency += (int) (buffer[ix-2] - '0') * (multiplier / 10); + frequency += (int) (buffer[ix-1] - '0') * (multiplier / 100); } else { - frequency = (int) (buffer[ix - 4] - '0') * 1000; - frequency += (int) (buffer[ix - 3] - '0') * 100; - frequency += (int) (buffer[ix - 2] - '0') * 10; - frequency += (int) (buffer[ix - 1] - '0'); + frequency = (int) (buffer[ix-4] - '0') * 1000; + frequency += (int) (buffer[ix-3] - '0') * 100; + frequency += (int) (buffer[ix-2] - '0') * 10; + frequency += (int) (buffer[ix-1] - '0'); frequency *= frequency; } } @@ -1012,6 +1072,45 @@ static void Query_Features(void *pArg) : "%rax", "%rbx", "%rcx", "%rdx" ); } + } + if (iArg->Features->Info.LargestStdFunc >= 0xd) + { + __asm__ volatile + ( + "movq $0xd, %%rax \n\t" + "xorq %%rbx, %%rbx \n\t" + "xorq %%rcx, %%rcx \n\t" + "xorq %%rdx, %%rdx \n\t" + "cpuid \n\t" + "mov %%eax, %0 \n\t" + "mov %%ebx, %1 \n\t" + "mov %%ecx, %2 \n\t" + "mov %%edx, %3" + : "=r" (iArg->Features->ExtState.EAX), + "=r" (iArg->Features->ExtState.EBX), + "=r" (iArg->Features->ExtState.ECX), + "=r" (iArg->Features->ExtState.EDX) + : + : "%rax", "%rbx", "%rcx", "%rdx" + ); + __asm__ volatile + ( + "movq $0xd, %%rax \n\t" + "movq $0x1, %%rcx \n\t" + "xorq %%rbx, %%rbx \n\t" + "xorq %%rdx, %%rdx \n\t" + "cpuid \n\t" + "mov %%eax, %0 \n\t" + "mov %%ebx, %1 \n\t" + "mov %%ecx, %2 \n\t" + "mov %%edx, %3" + : "=r" (iArg->Features->ExtState_Leaf1.EAX), + "=r" (iArg->Features->ExtState_Leaf1.EBX), + "=r" (iArg->Features->ExtState_Leaf1.ECX), + "=r" (iArg->Features->ExtState_Leaf1.EDX) + : + : "%rax", "%rbx", "%rcx", "%rdx" + ); } /* Must have 0x80000000,0x80000001,0x80000002,0x80000003,0x80000004 */ __asm__ volatile @@ -1232,6 +1331,27 @@ static void Query_Features(void *pArg) } else { iArg->SMT_Count = 1; } + if (iArg->Features->Info.LargestExtFunc >= 0x80000021) + { + __asm__ volatile + ( + "movq $0x80000021, %%rax \n\t" + "xorq %%rbx, %%rbx \n\t" + "xorq %%rcx, %%rcx \n\t" + "xorq %%rdx, %%rdx \n\t" + "cpuid \n\t" + "mov %%eax, %0 \n\t" + "mov %%ebx, %1 \n\t" + "mov %%ecx, %2 \n\t" + "mov %%edx, %3" + : "=r" (iArg->Features->ExtFeature2_EAX), + "=r" (ebx), + "=r" (ecx), + "=r" (edx) + : + : "%rax", "%rbx", "%rcx", "%rdx" + ); + } if (iArg->Features->Info.LargestExtFunc >= 0x80000022) { CPUID_0x80000022 leaf80000022 = { @@ -1270,7 +1390,7 @@ static void Query_Features(void *pArg) } } -void Compute_Interval(void) +static void Compute_Interval(void) { if ( (SleepInterval >= LOOP_MIN_MS) && (SleepInterval <= LOOP_MAX_MS)) @@ -1431,7 +1551,7 @@ static void Compute_TSC(void *arg) REL_BCLK(pCompute->Clock, ratio, D[1][best[1]], 1LLU); } -CLOCK Compute_Clock(unsigned int cpu, COMPUTE_ARG *pCompute) +static CLOCK Compute_Clock(unsigned int cpu, COMPUTE_ARG *pCompute) { /* Synchronously call the Base Clock estimation on a pinned CPU. * 1/ Preemption is disabled by smp_call_function_single() > get_cpu() @@ -1445,7 +1565,7 @@ CLOCK Compute_Clock(unsigned int cpu, COMPUTE_ARG *pCompute) return pCompute->Clock; } -void ClockToHz(CLOCK *clock) +inline void ClockToHz(CLOCK *clock) { clock->Hz = clock->Q * 1000000L; clock->Hz += clock->R * PRECISION; @@ -1458,7 +1578,7 @@ static CLOCK BaseClock_GenuineIntel(unsigned int ratio) if ((PUBLIC(RO(Proc))->Features.Factory.Freq > 0) && (ratio > 0)) { - clock.Hz=(PUBLIC(RO(Proc))->Features.Factory.Freq * 1000000L) + clock.Hz = (PUBLIC(RO(Proc))->Features.Factory.Freq * 1000000L) / ratio; clock.Q = PUBLIC(RO(Proc))->Features.Factory.Freq / ratio; @@ -1771,13 +1891,13 @@ static CLOCK BaseClock_Skylake(unsigned int ratio) }; static CLOCK BaseClock_AMD_Family_17h(unsigned int ratio) -{ /* Source: AMD PPR Family 17h § 1.4/ Table 11: REFCLK = 100 MHz */ +{ /* Source: AMD PPR Family 17h Chap. 1.4/ Table 11: REFCLK = 100 MHz */ CLOCK clock = {.Q = 100, .R = 0, .Hz = 100000000L}; UNUSED(ratio); return clock; }; -void Define_CPUID(CORE_RO *Core, const CPUID_STRUCT CpuIDforVendor[]) +static void Define_CPUID(CORE_RO *Core, const CPUID_STRUCT CpuIDforVendor[]) { /* Per vendor, define a CPUID dump table to query . */ enum CPUID_ENUM i; for (i = 0; i < CPUID_MAX_FUNC; i++) { @@ -1786,7 +1906,7 @@ void Define_CPUID(CORE_RO *Core, const CPUID_STRUCT CpuIDforVendor[]) } } -void Cache_Topology(CORE_RO *Core) +static void Cache_Topology(CORE_RO *Core) { unsigned long level = 0x0; if (PUBLIC(RO(Proc))->Features.Info.Vendor.CRC == CRC_INTEL) { @@ -1887,7 +2007,7 @@ void Cache_Topology(CORE_RO *Core) } } -unsigned int L3_SubCache_AMD_Piledriver(unsigned int bits) +static unsigned int L3_SubCache_AMD_Piledriver(unsigned int bits) { /* Return the AMD Piledriver L3 Sub-Cache size in unit of 512 KB */ switch (bits) { case 0xc: @@ -1912,6 +2032,8 @@ static void Map_AMD_Topology(void *arg) .EAX = {0}, .EBX = {0}, .ECX = {0}, .EDX = {0} }; + bool CPU_Complex = true; + Cache_Topology(Core); RDMSR(Core->T.Base, MSR_IA32_APICBASE); @@ -2033,28 +2155,36 @@ static void Map_AMD_Topology(void *arg) Core->T.Cluster.CMP = leaf8000001e.EBX.CompUnitId; } break; - case AMD_Zen: + /* Zen APU */ case AMD_Zen_APU: - case AMD_ZenPlus: case AMD_ZenPlus_APU: case AMD_Zen_Dali: - case AMD_EPYC_Rome_CPK: case AMD_Zen2_Renoir: case AMD_Zen2_LCN: - case AMD_Zen2_MTS: case AMD_Zen2_Ariel: case AMD_Zen2_Jupiter: + case AMD_Zen2_Galileo: case AMD_Zen2_MDN: - case AMD_Zen3_VMR: case AMD_Zen3_CZN: + case AMD_Zen3Plus_RMB: + case AMD_Zen4_PHX: + case AMD_Zen4_HWK: + case AMD_Zen4_PHX2: + CPU_Complex = false; + fallthrough; + /* Zen CPU Complex */ + case AMD_Zen: + case AMD_ZenPlus: + case AMD_EPYC_Rome_CPK: + case AMD_Zen2_MTS: + case AMD_Zen3_VMR: case AMD_EPYC_Milan: case AMD_Zen3_Chagall: case AMD_Zen3_Badami: - case AMD_Zen3Plus_RMB: case AMD_Zen4_Genoa: case AMD_Zen4_RPL: - case AMD_Zen4_PHX: case AMD_Zen4_Bergamo: + case AMD_Zen4_STP: case AMD_Family_17h: case Hygon_Family_18h: case AMD_Family_19h: @@ -2136,7 +2266,8 @@ static void Map_AMD_Topology(void *arg) || (PUBLIC(RO(Proc))->ArchID == AMD_Zen3_Chagall) || (PUBLIC(RO(Proc))->ArchID == AMD_Zen3_Badami) || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_Genoa) - || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_Bergamo))) + || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_Bergamo) + || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_STP))) || ((leaf80000008.ECX.NC == 0x17) && ((PUBLIC(RO(Proc))->ArchID == AMD_EPYC_Rome_CPK) @@ -2144,7 +2275,8 @@ static void Map_AMD_Topology(void *arg) || (PUBLIC(RO(Proc))->ArchID == AMD_Zen3_Chagall) || (PUBLIC(RO(Proc))->ArchID == AMD_Zen3_Badami) || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_Genoa) - || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_Bergamo))); + || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_Bergamo) + || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_STP))); } else { /* SMT is disabled. */ @@ -2166,7 +2298,8 @@ static void Map_AMD_Topology(void *arg) || (PUBLIC(RO(Proc))->ArchID == AMD_Zen3_Chagall) || (PUBLIC(RO(Proc))->ArchID == AMD_Zen3_Badami) || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_Genoa) - || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_Bergamo))) + || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_Bergamo) + || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_STP))) || ((leaf80000008.ECX.NC == 0x0b) && ((PUBLIC(RO(Proc))->ArchID == AMD_EPYC_Rome_CPK) @@ -2174,14 +2307,18 @@ static void Map_AMD_Topology(void *arg) || (PUBLIC(RO(Proc))->ArchID == AMD_Zen3_Chagall) || (PUBLIC(RO(Proc))->ArchID == AMD_Zen3_Badami) || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_Genoa) - || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_Bergamo))); + || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_Bergamo) + || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_STP))); } /* CCD has to remain within range values from 0 to 7 */ factor = factor & (Core->T.CoreID < 32); - Core->T.Cluster.Node=leaf8000001e.ECX.NodeId; + Core->T.Cluster.Node = leaf8000001e.ECX.NodeId; + + if (CPU_Complex == true ) { Core->T.Cluster.CCD = (Core->T.CoreID >> 3) << factor; Core->T.Cluster.CCX = Core->T.CoreID >> 2; + } } else { /* Fallback algorithm. */ Core->T.ApicID = leaf1_ebx.Init_APIC_ID; Core->T.PackageID = leaf1_ebx.Init_APIC_ID @@ -2199,10 +2336,10 @@ static void Map_AMD_Topology(void *arg) /* Enumerate the topology of Processors, Cores and Threads Remark: Early single-core processors are not processed. - Sources: Intel Software Developer's Manual vol 3A §8.9 / + Sources: Intel Software Developer's Manual vol 3A Chap. 8.9 / Intel whitepaper: Detecting Hyper-Threading Technology / */ -unsigned short FindMaskWidth(unsigned short maxCount) +inline unsigned short FindMaskWidth(unsigned short maxCount) { unsigned short maskWidth = 0, count = (maxCount - 1); @@ -2271,9 +2408,9 @@ static void Map_Intel_Topology(void *arg) CORE_Mask_Width = 1; } - if (CORE_Mask_Width != 0) + if (CORE_Mask_Width != 0) { SMT_Mask_Width = FindMaskWidth(SMT_Mask_Width) / CORE_Mask_Width; - + } SMT_Select_Mask = ~((-1) << SMT_Mask_Width); CORE_Select_Mask = (~((-1) << (CORE_Mask_Width + SMT_Mask_Width))) @@ -2394,7 +2531,7 @@ static void Map_Intel_Extended_Topology(void *arg) } } -int Core_Topology(unsigned int cpu) +static int Core_Topology(unsigned int cpu) { int rc = smp_call_function_single(cpu, ( (PUBLIC(RO(Proc))->Features.Info.Vendor.CRC == CRC_AMD) @@ -2413,7 +2550,7 @@ int Core_Topology(unsigned int cpu) return rc; } -unsigned int Proc_Topology(void) +static unsigned int Proc_Topology(void) { unsigned int cpu, CountEnabledCPU = 0; @@ -2449,7 +2586,7 @@ unsigned int Proc_Topology(void) PUBLIC(RO(Proc))->CPU.OnLine = Proc_Topology() \ ) -void Package_Init_Reset(void) +static void Package_Init_Reset(void) { PUBLIC(RO(Proc))->Features.TgtRatio_Unlock = 1; PUBLIC(RO(Proc))->Features.ClkRatio_Unlock = 0; @@ -2460,7 +2597,7 @@ void Package_Init_Reset(void) PUBLIC(RO(Proc))->Features.Uncore_Unlock = 0; } -void Default_Unlock_Reset(void) +static void Default_Unlock_Reset(void) { switch (Target_Ratio_Unlock) { case COREFREQ_TOGGLE_OFF: @@ -2496,7 +2633,7 @@ void Default_Unlock_Reset(void) } } -void OverrideCodeNameString(PROCESSOR_SPECIFIC *pSpecific) +static void OverrideCodeNameString(PROCESSOR_SPECIFIC *pSpecific) { StrCopy(PUBLIC(RO(Proc))->Architecture, Arch[ @@ -2504,7 +2641,7 @@ void OverrideCodeNameString(PROCESSOR_SPECIFIC *pSpecific) ].Architecture[pSpecific->CodeNameIdx], CODENAME_LEN); } -void OverrideUnlockCapability(PROCESSOR_SPECIFIC *pSpecific) +static void OverrideUnlockCapability(PROCESSOR_SPECIFIC *pSpecific) { if (pSpecific->Latch & LATCH_TGT_RATIO_UNLOCK) { PUBLIC(RO(Proc))->Features.TgtRatio_Unlock=pSpecific->TgtRatioUnlocked; @@ -2523,7 +2660,7 @@ void OverrideUnlockCapability(PROCESSOR_SPECIFIC *pSpecific) } } -PROCESSOR_SPECIFIC *LookupProcessor(void) +static PROCESSOR_SPECIFIC *LookupProcessor(void) { PROCESSOR_SPECIFIC *pSpecific; for (pSpecific = Arch[PUBLIC(RO(Proc))->ArchID].Specific; @@ -2543,7 +2680,7 @@ PROCESSOR_SPECIFIC *LookupProcessor(void) return NULL; } -int Intel_MaxBusRatio(PLATFORM_ID *PfID) +static int Intel_MaxBusRatio(PLATFORM_ID *PfID) { struct SIGNATURE whiteList[] = { _Core_Conroe, /* 06_0F */ @@ -2557,7 +2694,8 @@ int Intel_MaxBusRatio(PLATFORM_ID *PfID) _Atom_Bonnell, /* 06_1C */ _Atom_Airmont /* 06_4C */ }; - int id, ids = sizeof(whiteList) / sizeof(whiteList[0]); + const int ids = sizeof(whiteList) / sizeof(whiteList[0]); + int id; for (id = 0; id < ids; id++) { if ((whiteList[id].ExtFamily \ == PUBLIC(RO(Proc))->Features.Std.EAX.ExtFamily) @@ -2575,7 +2713,7 @@ int Intel_MaxBusRatio(PLATFORM_ID *PfID) return -1; } -void Intel_Core_Platform_Info(unsigned int cpu) +static void Intel_Core_Platform_Info(unsigned int cpu) { PLATFORM_ID PfID = {.value = 0}; PLATFORM_INFO PfInfo = {.value = 0}; @@ -2588,7 +2726,7 @@ void Intel_Core_Platform_Info(unsigned int cpu) } RDMSR(PerfStatus, MSR_IA32_PERF_STATUS); - if (PerfStatus.value != 0) { /* §18.18.3.4 */ + if (PerfStatus.value != 0) { /* Chap. 18.18.3.4 */ if (PerfStatus.CORE.XE_Enable) { ratio1 = PerfStatus.CORE.MaxBusRatio; } else { @@ -2612,7 +2750,7 @@ void Intel_Core_Platform_Info(unsigned int cpu) PUBLIC(RO(Core, AT(cpu)))->Boost[BOOST(MAX)] = KMAX(ratio0, ratio1); } -void Compute_Intel_Core_Burst(unsigned int cpu) +static void Compute_Intel_Core_Burst(unsigned int cpu) { PERF_STATUS PerfStatus = {.value = 0}; RDMSR(PerfStatus, MSR_IA32_PERF_STATUS); @@ -2642,7 +2780,7 @@ void Compute_Intel_Core_Burst(unsigned int cpu) } } -PLATFORM_INFO Intel_Platform_Info(unsigned int cpu) +static PLATFORM_INFO Intel_Platform_Info(unsigned int cpu) { PLATFORM_INFO PfInfo = {.value = 0}; RDMSR(PfInfo, MSR_PLATFORM_INFO); @@ -2670,7 +2808,7 @@ typedef struct { long rc; } CLOCK_TURBO_ARG; -void Assign_8C_Boost(unsigned int *pBoost, TURBO_CONFIG *pConfig) +static void Assign_8C_Boost(unsigned int *pBoost, TURBO_CONFIG *pConfig) { pBoost[BOOST(8C)] = pConfig->Cfg0.MaxRatio_8C; pBoost[BOOST(7C)] = pConfig->Cfg0.MaxRatio_7C; @@ -2682,7 +2820,7 @@ void Assign_8C_Boost(unsigned int *pBoost, TURBO_CONFIG *pConfig) pBoost[BOOST(1C)] = pConfig->Cfg0.MaxRatio_1C; } -void Assign_15C_Boost(unsigned int *pBoost, TURBO_CONFIG *pConfig) +static void Assign_15C_Boost(unsigned int *pBoost, TURBO_CONFIG *pConfig) { pBoost[BOOST(15C)] = pConfig->Cfg1.IVB_EP.MaxRatio_15C; pBoost[BOOST(14C)] = pConfig->Cfg1.IVB_EP.MaxRatio_14C; @@ -2693,7 +2831,7 @@ void Assign_15C_Boost(unsigned int *pBoost, TURBO_CONFIG *pConfig) pBoost[BOOST(9C) ] = pConfig->Cfg1.IVB_EP.MaxRatio_9C; } -void Assign_16C_Boost(unsigned int *pBoost, TURBO_CONFIG *pConfig) +static void Assign_16C_Boost(unsigned int *pBoost, TURBO_CONFIG *pConfig) { pBoost[BOOST(16C)] = pConfig->Cfg1.HSW_EP.MaxRatio_16C; pBoost[BOOST(15C)] = pConfig->Cfg1.HSW_EP.MaxRatio_15C; @@ -2705,13 +2843,13 @@ void Assign_16C_Boost(unsigned int *pBoost, TURBO_CONFIG *pConfig) pBoost[BOOST(9C) ] = pConfig->Cfg1.HSW_EP.MaxRatio_9C; } -void Assign_18C_Boost(unsigned int *pBoost, TURBO_CONFIG *pConfig) +static void Assign_18C_Boost(unsigned int *pBoost, TURBO_CONFIG *pConfig) { pBoost[BOOST(18C)] = pConfig->Cfg2.MaxRatio_18C; pBoost[BOOST(17C)] = pConfig->Cfg2.MaxRatio_17C; } -void Assign_SKL_X_Boost(unsigned int *pBoost, TURBO_CONFIG *pConfig) +static void Assign_SKL_X_Boost(unsigned int *pBoost, TURBO_CONFIG *pConfig) { pBoost[BOOST(16C)] = pConfig->Cfg1.SKL_X.NUMCORE_7; pBoost[BOOST(15C)] = pConfig->Cfg1.SKL_X.NUMCORE_6; @@ -2723,7 +2861,7 @@ void Assign_SKL_X_Boost(unsigned int *pBoost, TURBO_CONFIG *pConfig) pBoost[BOOST(9C) ] = pConfig->Cfg1.SKL_X.NUMCORE_0; } -long For_All_Turbo_Clock(CLOCK_ARG *pClockMod, void (*ConfigFunc)(void *)) +static long For_All_Turbo_Clock(CLOCK_ARG *pClockMod, void (*ConfigFunc)(void*)) { long rc = RC_SUCCESS; unsigned int cpu = PUBLIC(RO(Proc))->CPU.Count; @@ -2958,7 +3096,7 @@ static void Intel_Turbo_Cfg15C_PerCore(void *arg) } } -long Intel_Turbo_Config15C(CLOCK_ARG *pClockMod) +static long Intel_Turbo_Config15C(CLOCK_ARG *pClockMod) { long rc = For_All_Turbo_Clock(pClockMod, Intel_Turbo_Cfg15C_PerCore); @@ -3073,7 +3211,7 @@ static void Intel_Turbo_Cfg16C_PerCore(void *arg) } } -long Intel_Turbo_Config16C(CLOCK_ARG *pClockMod) +static long Intel_Turbo_Config16C(CLOCK_ARG *pClockMod) { long rc = For_All_Turbo_Clock(pClockMod, Intel_Turbo_Cfg16C_PerCore); @@ -3128,7 +3266,7 @@ static void Intel_Turbo_Cfg18C_PerCore(void *arg) } } -long Intel_Turbo_Config18C(CLOCK_ARG *pClockMod) +static long Intel_Turbo_Config18C(CLOCK_ARG *pClockMod) { long rc = For_All_Turbo_Clock(pClockMod, Intel_Turbo_Cfg18C_PerCore); @@ -3243,7 +3381,7 @@ static void Intel_Turbo_Cfg_SKL_X_PerCore(void *arg) } } -long Skylake_X_Turbo_Config16C(CLOCK_ARG *pClockMod) +static long Skylake_X_Turbo_Config16C(CLOCK_ARG *pClockMod) { long rc = For_All_Turbo_Clock(pClockMod, Intel_Turbo_Cfg_SKL_X_PerCore); @@ -3360,7 +3498,7 @@ static void PerCore_Intel_HWP_Ignition(void *arg) } } -void Intel_Hardware_Performance(void) +static void Intel_Hardware_Performance(void) { PM_ENABLE PM_Enable = {.value = 0}; HDC_CONTROL HDC_Control = {.value = 0}; @@ -3428,7 +3566,7 @@ void Intel_Hardware_Performance(void) PUBLIC(RO(Proc))->Features.HDC_Enable = HDC_Control.HDC_Enable; } -void Skylake_PowerControl(void) +static void Skylake_PowerControl(void) { unsigned short WrRdMSR = 0; @@ -3457,7 +3595,7 @@ void Skylake_PowerControl(void) PUBLIC(RO(Proc))->Features.R2H_Enable = !PowerCtrl.R2H_Disable; } -void SandyBridge_Uncore_Ratio(unsigned int cpu) +static void SandyBridge_Uncore_Ratio(unsigned int cpu) { PUBLIC(RO(Proc))->Uncore.Boost[UNCORE_BOOST(MIN)] = \ PUBLIC(RO(Core, AT(cpu)))->Boost[BOOST(MIN)]; @@ -3513,7 +3651,7 @@ static long Haswell_Uncore_Ratio(CLOCK_ARG *pClockMod) return rc; } -void Nehalem_PowerLimit(void) +static void Nehalem_PowerLimit(void) { unsigned short WrRdMSR = 0; @@ -3580,15 +3718,15 @@ void Nehalem_PowerLimit(void) PUBLIC(RO(Proc))->PowerThermal.Enable_Limit.TDC=PowerLimit.TDC_Override; } -void Intel_PowerInterface(void) +static void Intel_PowerInterface(void) { RDMSR(PUBLIC(RO(Proc))->PowerThermal.Unit, MSR_RAPL_POWER_UNIT); RDMSR(PUBLIC(RO(Proc))->PowerThermal.PowerInfo, MSR_PKG_POWER_INFO); } -void Intel_DomainPowerLimit( unsigned int MSR_DOMAIN_POWER_LIMIT, - unsigned long long PowerLimitLockMask, - enum PWR_DOMAIN pw ) +static void Intel_DomainPowerLimit( unsigned int MSR_DOMAIN_POWER_LIMIT, + unsigned long long PowerLimitLockMask, + enum PWR_DOMAIN pw ) { const unsigned int lt = PWR_LIMIT_SIZE * pw, rt = 1 + lt; unsigned short WrRdMSR = 0; @@ -3734,12 +3872,12 @@ void Intel_DomainPowerLimit( unsigned int MSR_DOMAIN_POWER_LIMIT, PUBLIC(RO(Proc))->PowerThermal.Domain[pw].PowerLimit = PowerLimit; } -void Intel_Pkg_CST_IRTL(const unsigned int MSR, PKGCST_IRTL *PCST) +static void Intel_Pkg_CST_IRTL(const unsigned int MSR, PKGCST_IRTL *PCST) { RDMSR((*PCST), MSR); } -long Intel_ThermalOffset(bool programmableTj) +static long Intel_ThermalOffset(bool programmableTj) { long rc = -EINVAL; if (ThermalOffset != 0) { @@ -3799,7 +3937,7 @@ long Intel_ThermalOffset(bool programmableTj) return rc; } -void Intel_Processor_PIN(bool capable) +static void Intel_Processor_PIN(bool capable) { if (capable) { INTEL_PPIN_CTL PPinCtl = {.value = 0}; @@ -3812,7 +3950,7 @@ void Intel_Processor_PIN(bool capable) } } -void AMD_Processor_PIN(bool capable) +static void AMD_Processor_PIN(bool capable) { if (capable) { AMD_PPIN_CTL PPinCtl = {.value = 0}; @@ -3825,7 +3963,7 @@ void AMD_Processor_PIN(bool capable) } } -long AMD_F17h_CPPC(void) +static long AMD_F17h_CPPC(void) { AMD_CPPC_ENABLE CPPC_Enable = {.value = 0}; @@ -3845,7 +3983,7 @@ long AMD_F17h_CPPC(void) return -ENODEV; } -void Compute_ACPI_CPPC_Bounds(unsigned int cpu) +static void Compute_ACPI_CPPC_Bounds(unsigned int cpu) { CORE_RO *Core = (CORE_RO *) PUBLIC(RO(Core, AT(cpu))); @@ -3901,7 +4039,7 @@ inline signed int Enable_ACPI_CPPC(unsigned int cpu, void *arg) return rc; } -signed int Get_ACPI_CPPC_Registers(unsigned int cpu, void *arg) +static signed int Get_ACPI_CPPC_Registers(unsigned int cpu, void *arg) { #ifdef CONFIG_ACPI_CPPC_LIB struct cppc_perf_fb_ctrs CPPC_Perf; @@ -3943,7 +4081,13 @@ signed int Get_ACPI_CPPC_Registers(unsigned int cpu, void *arg) .Minimum = CPPC_Caps.lowest_perf, #endif .Maximum = CPPC_Caps.highest_perf, + #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0) .Desired = CPPC_Perf.reference_perf, + #elif LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0) + .Desired = CPPC_Caps.reference_perf, + #else + .Desired = 0, + #endif .Energy = 0 }; #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 1, 0) @@ -3968,7 +4112,7 @@ signed int Get_ACPI_CPPC_Registers(unsigned int cpu, void *arg) #endif /* CONFIG_ACPI_CPPC_LIB */ } -signed int Get_EPP_ACPI_CPPC(unsigned int cpu) +static signed int Get_EPP_ACPI_CPPC(unsigned int cpu) { signed int rc = -ENODEV; #if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) @@ -3986,7 +4130,7 @@ signed int Get_EPP_ACPI_CPPC(unsigned int cpu) return rc; } -signed int Put_EPP_ACPI_CPPC(unsigned int cpu, signed short epp) +static signed int Put_EPP_ACPI_CPPC(unsigned int cpu, signed short epp) { signed int rc = -ENODEV; #if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) @@ -4003,7 +4147,7 @@ signed int Put_EPP_ACPI_CPPC(unsigned int cpu, signed short epp) return rc; } -signed int Set_EPP_ACPI_CPPC(unsigned int cpu, void *arg) +static signed int Set_EPP_ACPI_CPPC(unsigned int cpu, void *arg) { signed int rc = 0; UNUSED(arg); @@ -4016,7 +4160,7 @@ signed int Set_EPP_ACPI_CPPC(unsigned int cpu, void *arg) return rc; } -signed int Read_ACPI_CPPC_Registers(unsigned int cpu, void *arg) +static signed int Read_ACPI_CPPC_Registers(unsigned int cpu, void *arg) { signed int rc = Get_ACPI_CPPC_Registers(cpu, arg); @@ -4030,7 +4174,7 @@ signed int Read_ACPI_CPPC_Registers(unsigned int cpu, void *arg) return rc; } -signed int Read_ACPI_PCT_Registers(unsigned int cpu) +static signed int Read_ACPI_PCT_Registers(unsigned int cpu) { #if defined(CONFIG_ACPI) signed int rc = 0; @@ -4071,7 +4215,7 @@ signed int Read_ACPI_PCT_Registers(unsigned int cpu) #endif } -signed int Read_ACPI_PSS_Registers(unsigned int cpu) +static signed int Read_ACPI_PSS_Registers(unsigned int cpu) { #if defined(CONFIG_ACPI) signed int rc = 0; @@ -4112,7 +4256,7 @@ signed int Read_ACPI_PSS_Registers(unsigned int cpu) #endif } -signed int Read_ACPI_PPC_Registers(unsigned int cpu) +static signed int Read_ACPI_PPC_Registers(unsigned int cpu) { #if defined(CONFIG_ACPI) signed int rc = 0; @@ -4158,7 +4302,7 @@ signed int Read_ACPI_PPC_Registers(unsigned int cpu) #endif } -signed int Read_ACPI_CST_Registers(unsigned int cpu) +static signed int Read_ACPI_CST_Registers(unsigned int cpu) { #if defined(CONFIG_ACPI) signed int rc = 0; @@ -4200,13 +4344,16 @@ signed int Read_ACPI_CST_Registers(unsigned int cpu) #endif } -void For_All_ACPI_CPPC(signed int(*CPPC_Func)(unsigned int, void*), void *arg) +static void For_All_ACPI_CPPC( signed int (*CPPC_Func)(unsigned int, void*), + void *arg ) { #if defined(CONFIG_ACPI_CPPC_LIB) \ && LINUX_VERSION_CODE >= KERNEL_VERSION(5, 11, 0) signed int rc = acpi_cpc_valid() == false; - #else + #elif defined(CONFIG_ACPI) signed int rc = acpi_disabled; + #else + signed int rc = false; #endif unsigned int cpu; @@ -4223,7 +4370,7 @@ void For_All_ACPI_CPPC(signed int(*CPPC_Func)(unsigned int, void*), void *arg) PUBLIC(RO(Proc))->Features.ACPI_CPPC = (rc == 0); } -void Query_Same_Platform_Features(unsigned int cpu) +static void Query_Same_Platform_Features(unsigned int cpu) { PLATFORM_INFO PfInfo; @@ -4245,14 +4392,14 @@ void Query_Same_Platform_Features(unsigned int cpu) PUBLIC(RO(Proc))->Features.SpecTurboRatio = 0; } -void Nehalem_Platform_Info(unsigned int cpu) +static void Nehalem_Platform_Info(unsigned int cpu) { Query_Same_Platform_Features(cpu); PUBLIC(RO(Proc))->Features.SpecTurboRatio += 8; /* 8C */ } -void IvyBridge_EP_Platform_Info(unsigned int cpu) +static void IvyBridge_EP_Platform_Info(unsigned int cpu) { const unsigned int NC = \ PUBLIC(RO(Proc))->CPU.Count >> PUBLIC(RO(Proc))->Features.HTT_Enable; @@ -4265,7 +4412,7 @@ void IvyBridge_EP_Platform_Info(unsigned int cpu) } } -void Haswell_EP_Platform_Info(unsigned int cpu) +static void Haswell_EP_Platform_Info(unsigned int cpu) { const unsigned int NC = \ PUBLIC(RO(Proc))->CPU.Count >> PUBLIC(RO(Proc))->Features.HTT_Enable; @@ -4281,7 +4428,7 @@ void Haswell_EP_Platform_Info(unsigned int cpu) } } -void Skylake_X_Platform_Info(unsigned int cpu) +static void Skylake_X_Platform_Info(unsigned int cpu) { const unsigned int NC = \ PUBLIC(RO(Proc))->CPU.Count >> PUBLIC(RO(Proc))->Features.HTT_Enable; @@ -4313,7 +4460,7 @@ void Skylake_X_Platform_Info(unsigned int cpu) } } -void Probe_AMD_DataFabric(void) +static void Probe_AMD_DataFabric(void) { #ifdef CONFIG_AMD_NB if (PUBLIC(RO(Proc))->Registration.Experimental) { @@ -4332,9 +4479,9 @@ void Probe_AMD_DataFabric(void) typedef void (*ROUTER)(void __iomem *mchmap, unsigned short mc); -PCI_CALLBACK Router(struct pci_dev *dev, unsigned int offset, - unsigned int bsize, unsigned long long wsize, - ROUTER route, unsigned short mc) +static PCI_CALLBACK Router( struct pci_dev *dev, unsigned int offset, + unsigned int bsize, unsigned long long wsize, + ROUTER route, unsigned short mc ) { void __iomem *mchmap; union { @@ -4357,7 +4504,7 @@ PCI_CALLBACK Router(struct pci_dev *dev, unsigned int offset, pci_read_config_dword(dev, offset + 4, &mchbar.high); break; } - mchbarEnable = BITVAL(mchbar, 0); + mchbarEnable = BITVAL(mchbar.addr, 0); if (mchbarEnable) { mchbar.addr &= wmask; mchbar.addr += wsize * mc; @@ -4374,10 +4521,10 @@ PCI_CALLBACK Router(struct pci_dev *dev, unsigned int offset, return (PCI_CALLBACK) -ENOMEM; } -PCI_CALLBACK GetMemoryBAR(int M, int B, int D, int F, unsigned int offset, - unsigned int bsize, unsigned long long wsize, - unsigned short range, - struct pci_dev **device, void __iomem **memmap) +inline PCI_CALLBACK GetMemoryBAR(int M, int B, int D, int F,unsigned int offset, + unsigned int bsize, unsigned long long wsize, + unsigned short range, + struct pci_dev **device, void __iomem **memmap) { if ((*device) == NULL) { if (((*device) = pci_get_domain_bus_and_slot(M, B, PCI_DEVFN(D,F))) != NULL) @@ -4402,7 +4549,7 @@ PCI_CALLBACK GetMemoryBAR(int M, int B, int D, int F, unsigned int offset, pci_read_config_dword((*device), offset + 4, &membar.high); break; } - membarEnable = BITVAL(membar, 0); + membarEnable = BITVAL(membar.addr, 0); if (membarEnable) { membar.addr &= wmask; membar.addr += wsize * range; @@ -4418,7 +4565,7 @@ PCI_CALLBACK GetMemoryBAR(int M, int B, int D, int F, unsigned int offset, return (PCI_CALLBACK) -EEXIST; } -void PutMemoryBAR(struct pci_dev **device, void __iomem **memmap) +inline void PutMemoryBAR(struct pci_dev **device, void __iomem **memmap) { if ((*memmap) != NULL) { iounmap((*memmap)); @@ -4431,7 +4578,7 @@ void PutMemoryBAR(struct pci_dev **device, void __iomem **memmap) } } -void Query_P945(void __iomem *mchmap, unsigned short mc) +static void Query_P945(void __iomem *mchmap, unsigned short mc) { /* Source: Mobile Intel 945 Express Chipset Family. */ unsigned short cha; @@ -4486,7 +4633,7 @@ void Query_P945(void __iomem *mchmap, unsigned short mc) } } -void Query_P955(void __iomem *mchmap, unsigned short mc) +static void Query_P955(void __iomem *mchmap, unsigned short mc) { /* Source: Intel 82955X Memory Controller Hub (MCH) */ unsigned short cha; @@ -4528,7 +4675,7 @@ void Query_P955(void __iomem *mchmap, unsigned short mc) } } -void Query_P965(void __iomem *mchmap, unsigned short mc) +static void Query_P965(void __iomem *mchmap, unsigned short mc) { unsigned short cha; @@ -4567,7 +4714,7 @@ void Query_P965(void __iomem *mchmap, unsigned short mc) } } -void Query_G965(void __iomem *mchmap, unsigned short mc) +static void Query_G965(void __iomem *mchmap, unsigned short mc) { /* Source: Mobile Intel 965 Express Chipset Family. */ unsigned short cha, slot; @@ -4605,8 +4752,8 @@ void Query_G965(void __iomem *mchmap, unsigned short mc) } } -void Query_P35(void __iomem *mchmap, unsigned short mc) -{ /* Source: Intel® 3 Series Express Chipset Family. */ +static void Query_P35(void __iomem *mchmap, unsigned short mc) +{ /* Source: Intel 3 Series Express Chipset Family. */ unsigned short cha; PUBLIC(RO(Proc))->Uncore.Bus.ClkCfg.value = readl(mchmap + 0xc00); @@ -4661,9 +4808,9 @@ void Query_P35(void __iomem *mchmap, unsigned short mc) } } -kernel_ulong_t Query_NHM_Timing(struct pci_dev *pdev, - unsigned short mc, - unsigned short cha) +static kernel_ulong_t Query_NHM_Timing( struct pci_dev *pdev, + unsigned short mc, + unsigned short cha ) { /*Source:Micron Technical Note DDR3 Power-Up, Initialization, & Reset*/ struct pci_dev *dev = pci_get_domain_bus_and_slot( pci_domain_nr(pdev->bus), @@ -4705,9 +4852,9 @@ kernel_ulong_t Query_NHM_Timing(struct pci_dev *pdev, return -ENODEV; } -kernel_ulong_t Query_NHM_DIMM(struct pci_dev *pdev, - unsigned short mc, - unsigned short cha) +static kernel_ulong_t Query_NHM_DIMM( struct pci_dev *pdev, + unsigned short mc, + unsigned short cha ) { struct pci_dev *dev = pci_get_domain_bus_and_slot( pci_domain_nr(pdev->bus), @@ -4729,7 +4876,7 @@ kernel_ulong_t Query_NHM_DIMM(struct pci_dev *pdev, } } -void Query_NHM_MaxDIMMs(struct pci_dev *dev, unsigned short mc) +static void Query_NHM_MaxDIMMs(struct pci_dev *dev, unsigned short mc) { pci_read_config_dword(dev, 0x64, &PUBLIC(RO(Proc))->Uncore.MC[mc].MaxDIMMs.NHM.DOD.value); @@ -4750,7 +4897,7 @@ void Query_NHM_MaxDIMMs(struct pci_dev *dev, unsigned short mc) } } -kernel_ulong_t Query_NHM_IMC(struct pci_dev *dev, unsigned short mc) +static kernel_ulong_t Query_NHM_IMC(struct pci_dev *dev, unsigned short mc) { kernel_ulong_t rc = 0; unsigned short cha; @@ -4776,7 +4923,7 @@ kernel_ulong_t Query_NHM_IMC(struct pci_dev *dev, unsigned short mc) return rc; } -kernel_ulong_t Query_Lynnfield_IMC(struct pci_dev *dev, unsigned short mc) +static kernel_ulong_t Query_Lynnfield_IMC(struct pci_dev *dev,unsigned short mc) { kernel_ulong_t rc = 0; unsigned short cha; @@ -4806,9 +4953,9 @@ inline void BIOS_DDR(void __iomem *mchmap) PUBLIC(RO(Proc))->Uncore.Bus.BIOS_DDR.value = readl(mchmap + 0x5e00); } -void Query_SNB_IMC(void __iomem *mchmap, unsigned short mc) -{ /* Sources: 2nd & 3rd Generation Intel® Core™ Processor Family - Intel® Xeon Processor E3-1200 Family */ +static void Query_SNB_IMC(void __iomem *mchmap, unsigned short mc) +{ /* Sources: 2nd & 3rd Generation Intel Core Processor Family + Intel Xeon Processor E3-1200 Family */ unsigned short cha, dimmCount[2]; PUBLIC(RO(Proc))->Uncore.Bus.ClkCfg.value = readl(mchmap + 0xc00); @@ -4862,7 +5009,7 @@ void Query_SNB_IMC(void __iomem *mchmap, unsigned short mc) BIOS_DDR(mchmap); } -void Query_Turbo_TDP_Config(void __iomem *mchmap) +static void Query_Turbo_TDP_Config(void __iomem *mchmap) { TURBO_ACTIVATION TurboActivation = {.value = 0}; CONFIG_TDP_NOMINAL NominalTDP = {.value = 0}; @@ -4935,8 +5082,8 @@ void Query_Turbo_TDP_Config(void __iomem *mchmap) } } -void Query_HSW_IMC(void __iomem *mchmap, unsigned short mc) -{ /*Source: Desktop 4th & 5th Generation Intel® Core™ Processor Family.*/ +static void Query_HSW_IMC(void __iomem *mchmap, unsigned short mc) +{ /* Source: Desktop 4th & 5th Generation Intel Core Processor Family */ unsigned short cha, dimmCount[2]; PUBLIC(RO(Proc))->Uncore.Bus.ClkCfg.value = readl(mchmap + 0xc00); @@ -4989,7 +5136,7 @@ void Query_HSW_IMC(void __iomem *mchmap, unsigned short mc) } } -void Query_HSW_CLK(void __iomem *mchmap, unsigned short mc) +static void Query_HSW_CLK(void __iomem *mchmap, unsigned short mc) { BIOS_DDR(mchmap); @@ -5001,8 +5148,8 @@ inline void SKL_SA(void __iomem *mchmap) PUBLIC(RO(Proc))->Uncore.Bus.SKL_SA_Pll.value = readl(mchmap + 0x5918); } -void Query_SKL_IMC(void __iomem *mchmap, unsigned short mc) -{ /*Source: 6th & 7th Generation Intel® Processor for S-Platforms Vol 2*/ +static void Query_SKL_IMC(void __iomem *mchmap, unsigned short mc) +{ /* Source: 6th & 7th Generation Intel Processor for S-Platforms Vol 2*/ unsigned short cha; /* Intra channel configuration */ PUBLIC(RO(Proc))->Uncore.MC[mc].SKL.MADCH.value = readl(mchmap+0x5000); @@ -5069,8 +5216,8 @@ inline void RKL_SA(void __iomem *mchmap) PUBLIC(RO(Proc))->Uncore.Bus.ADL_SA_Pll.SA_VOLTAGE; } -void Query_RKL_IMC(void __iomem *mchmap, unsigned short mc) -{ /*Source: 11th Generation Intel® Core Processor Datasheet Vol 2*/ +static void Query_RKL_IMC(void __iomem *mchmap, unsigned short mc) +{ /* Source: 11th Generation Intel Core Processor Datasheet Vol 2 */ unsigned short cha; /* Intra channel configuration */ PUBLIC(RO(Proc))->Uncore.MC[mc].RKL.MADCH.value = readl(mchmap+0x5000); @@ -5138,8 +5285,8 @@ void Query_RKL_IMC(void __iomem *mchmap, unsigned short mc) #define TGL_SA RKL_SA -void Query_TGL_IMC(void __iomem *mchmap, unsigned short mc) -{ /*Source: 11th Generation Intel® Core Processor Datasheet Vol 2 */ +static void Query_TGL_IMC(void __iomem *mchmap, unsigned short mc) +{ /* Source: 11th Generation Intel Core Processor Datasheet Vol 2 */ unsigned short cha; PUBLIC(RO(Proc))->Uncore.MC[mc].ChannelCount = 0; @@ -5229,8 +5376,8 @@ void Query_TGL_IMC(void __iomem *mchmap, unsigned short mc) #define ADL_SA TGL_SA -void Query_ADL_IMC(void __iomem *mchmap, unsigned short mc) -{ /*Source: 12th Generation Intel® Core Processor Datasheet Vol 2 */ +static void Query_ADL_IMC(void __iomem *mchmap, unsigned short mc) +{ /* Source: 12th Generation Intel Core Processor Datasheet Vol 2 */ unsigned short cha; PUBLIC(RO(Proc))->Uncore.MC[mc].ChannelCount = 0; @@ -5322,8 +5469,8 @@ void Query_ADL_IMC(void __iomem *mchmap, unsigned short mc) EMPTY_STMT(); } -void Query_GLK_IMC(void __iomem *mchmap, unsigned short mc) -{ /* Source: Intel® Pentium® Silver and Intel® Celeron® Processors Vol 2 */ +static void Query_GLK_IMC(void __iomem *mchmap, unsigned short mc) +{ /* Source: Intel Pentium Silver and Intel Celeron Processors Vol 2 */ PUBLIC(RO(Proc))->Uncore.MC[mc].ChannelCount = \ PUBLIC(RO(Proc))->Uncore.MC[mc].SlotCount = 0; } @@ -5687,7 +5834,7 @@ static PCI_CALLBACK SNB_EP_CAP(struct pci_dev *dev) return (PCI_CALLBACK) 0; } -kernel_ulong_t SNB_EP_CTRL(struct pci_dev *dev, unsigned short mc) +static kernel_ulong_t SNB_EP_CTRL(struct pci_dev *dev, unsigned short mc) { pci_read_config_dword(dev, 0x7c, &PUBLIC(RO(Proc))->Uncore.MC[mc].SNB_EP.TECH.value); @@ -5697,7 +5844,7 @@ kernel_ulong_t SNB_EP_CTRL(struct pci_dev *dev, unsigned short mc) return 0; } -kernel_ulong_t SNB_EP_IMC(struct pci_dev *dev , unsigned short mc, +static kernel_ulong_t SNB_EP_IMC(struct pci_dev *dev , unsigned short mc, unsigned short cha) { pci_read_config_dword(dev, 0x200, @@ -5724,7 +5871,7 @@ kernel_ulong_t SNB_EP_IMC(struct pci_dev *dev , unsigned short mc, return 0; } -kernel_ulong_t SNB_EP_TAD(struct pci_dev *dev, unsigned short mc, +static kernel_ulong_t SNB_EP_TAD(struct pci_dev *dev, unsigned short mc, unsigned short cha) { unsigned short slotCount; @@ -5877,7 +6024,7 @@ static PCI_CALLBACK HSW_CLK(struct pci_dev *dev) return HSW_HOST(dev, Query_HSW_CLK); } -kernel_ulong_t HSW_EP_CTRL(struct pci_dev *dev, unsigned short mc) +static kernel_ulong_t HSW_EP_CTRL(struct pci_dev *dev, unsigned short mc) { pci_read_config_dword(dev, 0x7c, &PUBLIC(RO(Proc))->Uncore.MC[mc].HSW_EP.TECH.value); @@ -6071,7 +6218,7 @@ static PCI_CALLBACK HSW_EP_TAD_CTRL1_CHA3(struct pci_dev *dev) return (PCI_CALLBACK) HSW_EP_TAD(dev, 1, 3); } -void SoC_SKL_VTD(void) +static void SoC_SKL_VTD(void) { if (PUBLIC(RO(Proc))->Uncore.Bus.SKL_Cap_A.VT_d == 0) { @@ -6335,8 +6482,8 @@ static PCI_CALLBACK AMD_Zen_IOMMU(struct pci_dev *dev) return (PCI_CALLBACK) 0; } -void AMD_Zen_UMC_Aggregate( unsigned short mc, unsigned short cha, - bool *Got_Mem_Clock, bool *Got_Div_Clock ) +static void AMD_Zen_UMC_Aggregate(unsigned short mc, unsigned short cha, + bool *Got_Mem_Clock, bool *Got_Div_Clock) { if ((*Got_Mem_Clock) == false) { @@ -6614,6 +6761,30 @@ static PCI_CALLBACK AMD_17h_DataFabric( struct pci_dev *pdev, return (PCI_CALLBACK) 0; } +static void AMD_UMC_Normalize_Channels(void) +{ + unsigned short umc; + for (umc = 0; umc < PUBLIC(RO(Proc))->Uncore.CtrlCount; umc++) + { /* If UMC is quad channels (in 2 x 32-bits) then unpopulate odd channels*/ + if (PUBLIC(RO(Proc))->Uncore.MC[umc].ChannelCount >= 4) { + unsigned short cha; + for (cha=0; cha < PUBLIC(RO(Proc))->Uncore.MC[umc].ChannelCount; cha++) + { + if (cha & 1) { + unsigned short slot; + for(slot=0;slot < PUBLIC(RO(Proc))->Uncore.MC[umc].SlotCount;slot++) + { + const unsigned short chipselect_pair = slot << 1; + + BITCLR(LOCKLESS, PUBLIC(RO(Proc))->Uncore.MC[umc].Channel[cha]\ + .AMD17h.CHIP[chipselect_pair][0].Chip.value, 0); + } + } + } + } + } +} + static PCI_CALLBACK AMD_DataFabric_Zeppelin(struct pci_dev *pdev) { if (strncmp(PUBLIC(RO(Proc))->Architecture, @@ -6755,6 +6926,18 @@ static PCI_CALLBACK AMD_DataFabric_Arden(struct pci_dev *pdev) (const unsigned int[]) {PCI_DEVFN(0x18, 0x0)} ); } +static PCI_CALLBACK AMD_DataFabric_VanGogh(struct pci_dev *pdev) +{ + return AMD_17h_DataFabric( pdev, + (const unsigned int[2][2]) { + { 0x0, 0x20}, + {0x10, 0x28} + }, + 0x30, 0x80, + 1, MC_MAX_CHA, + (const unsigned int[]) {PCI_DEVFN(0x18, 0x0)} ); +} + static PCI_CALLBACK AMD_DataFabric_Vermeer(struct pci_dev *pdev) { return AMD_17h_DataFabric( pdev, @@ -6790,28 +6973,9 @@ static PCI_CALLBACK AMD_DataFabric_Rembrandt(struct pci_dev *pdev) 1, MC_MAX_CHA, (const unsigned int[]) {PCI_DEVFN(0x18, 0x0)} ); - if ((PCI_CALLBACK) 0 == ret) { - unsigned short umc; - for (umc = 0; umc < PUBLIC(RO(Proc))->Uncore.CtrlCount; umc++) - { /* If UMC is quad channels (in 2 x 32-bits) then unpopulate odd channels*/ - if (PUBLIC(RO(Proc))->Uncore.MC[umc].ChannelCount >= 4) { - unsigned short cha; - for (cha=0; cha < PUBLIC(RO(Proc))->Uncore.MC[umc].ChannelCount; cha++) - { - if (cha & 1) { - unsigned short slot; - for(slot=0;slot < PUBLIC(RO(Proc))->Uncore.MC[umc].SlotCount;slot++) - { - const unsigned short chipselect_pair = slot << 1; - - BITCLR(LOCKLESS, PUBLIC(RO(Proc))->Uncore.MC[umc].Channel[cha]\ - .AMD17h.CHIP[chipselect_pair][0].Chip.value, 0); - } - } + if ((PCI_CALLBACK) 0 == ret) { + AMD_UMC_Normalize_Channels(); } - } - } - } return ret; } @@ -6839,6 +7003,23 @@ static PCI_CALLBACK AMD_DataFabric_Genoa(struct pci_dev *pdev) (const unsigned int[]) {PCI_DEVFN(0x18, 0x0)} ); } +static PCI_CALLBACK AMD_DataFabric_Phoenix(struct pci_dev *pdev) +{ + PCI_CALLBACK ret = AMD_17h_DataFabric( pdev, + (const unsigned int[2][2]) { + { 0x0, 0x20}, + {0x10, 0x30} + }, + 0x44, 0x90, + 1, MC_MAX_CHA, + (const unsigned int[]) {PCI_DEVFN(0x18, 0x0)} ); + + if ((PCI_CALLBACK) 0 == ret) { + AMD_UMC_Normalize_Channels(); + } + return ret; +} + static void CoreFreqK_ResetChip(struct pci_dev *dev) { UNUSED(dev); @@ -6896,7 +7077,7 @@ static int CoreFreqK_ProbePCI( struct pci_device_id PCI_ids[], return rc; } -void Query_Same_Genuine_Features(void) +static void Query_Same_Genuine_Features(void) { if ((PRIVATE(OF(Specific)) = LookupProcessor()) != NULL) { @@ -7165,7 +7346,7 @@ static void Query_Skylake_X(unsigned int cpu) Intel_Hardware_Performance(); } -unsigned short Compute_AuthenticAMD_Boost(unsigned int cpu) +static unsigned short Compute_AuthenticAMD_Boost(unsigned int cpu) { unsigned short SpecTurboRatio = 0; /* Lowest frequency according to BKDG */ @@ -7266,8 +7447,8 @@ static void Query_AuthenticAMD(unsigned int cpu) HyperThreading_Technology(); } -unsigned short Compute_AMD_Family_0Fh_Boost(unsigned int cpu) -{ /* Source: BKDG for AMD NPT Family 0Fh: §13.8 */ +static unsigned short Compute_AMD_Family_0Fh_Boost(unsigned int cpu) +{ /* Source: BKDG for AMD NPT Family 0Fh: Chap. 13.8 */ unsigned short SpecTurboRatio = 0; if (PUBLIC(RO(Proc))->Features.AdvPower.EDX.FID == 1) @@ -7295,11 +7476,10 @@ unsigned short Compute_AMD_Family_0Fh_Boost(unsigned int cpu) SpecTurboRatio = 1; } } else { - HWCR HwCfgRegister = {.value = 0}; - RDMSR(HwCfgRegister, MSR_K7_HWCR); + RDMSR(PUBLIC(RO(Core, AT(cpu)))->SystemRegister.HWCR, MSR_K7_HWCR); PUBLIC(RO(Core, AT(cpu)))->Boost[BOOST(MIN)] = 8 - + HwCfgRegister.Family_0Fh.StartFID; + + PUBLIC(RO(Core, AT(cpu)))->SystemRegister.HWCR.Family_0Fh.StartFID; PUBLIC(RO(Core, AT(cpu)))->Boost[BOOST(MAX)] = \ PUBLIC(RO(Core, AT(cpu)))->Boost[BOOST(MIN)]; @@ -7329,19 +7509,21 @@ static void Query_AMD_Family_0Fh(unsigned int cpu) HyperThreading_Technology(); } -void Compute_AMD_Family_10h_Boost(unsigned int cpu) +static void Compute_AMD_Family_10h_Boost(unsigned int cpu) { unsigned int pstate, sort[5] = { BOOST(1C), BOOST(MAX), BOOST(2C), BOOST(3C), BOOST(MIN) }; for (pstate = 0; pstate <= 4; pstate++) { + unsigned int fid, did; PSTATEDEF PstateDef = {.value = 0}; RDMSR(PstateDef, (MSR_AMD_PSTATE_DEF_BASE + pstate)); - PUBLIC(RO(Core, AT(cpu)))->Boost[sort[pstate]] = \ - (PstateDef.Family_10h.CpuFid + 0x10) - / (1 << PstateDef.Family_10h.CpuDid); + fid = PstateDef.Family_10h.CpuFid + 0x10; + did = 1 << PstateDef.Family_10h.CpuDid; + + PUBLIC(RO(Core, AT(cpu)))->Boost[sort[pstate]] = fid / did; } } @@ -7364,7 +7546,7 @@ static void Query_AMD_Family_10h(unsigned int cpu) HyperThreading_Technology(); } -void Compute_AMD_Family_11h_Boost(unsigned int cpu) +static void Compute_AMD_Family_11h_Boost(unsigned int cpu) { unsigned int pstate, sort[8] = { BOOST(1C), BOOST(MAX), BOOST(2C), BOOST(3C), @@ -7372,12 +7554,14 @@ void Compute_AMD_Family_11h_Boost(unsigned int cpu) }; for (pstate = 0; pstate <= 7; pstate++) { + unsigned int fid, did; PSTATEDEF PstateDef = {.value = 0}; RDMSR(PstateDef, (MSR_AMD_PSTATE_DEF_BASE + pstate)); - PUBLIC(RO(Core, AT(cpu)))->Boost[sort[pstate]] = \ - (PstateDef.Family_10h.CpuFid + 0x8) - / (1 << PstateDef.Family_10h.CpuDid); + fid = PstateDef.Family_10h.CpuFid + 0x8; + did = 1 << PstateDef.Family_10h.CpuDid; + + PUBLIC(RO(Core, AT(cpu)))->Boost[sort[pstate]] = fid / did; } } @@ -7400,7 +7584,7 @@ static void Query_AMD_Family_11h(unsigned int cpu) HyperThreading_Technology(); } -void Compute_AMD_Family_12h_Boost(unsigned int cpu) +static void Compute_AMD_Family_12h_Boost(unsigned int cpu) { unsigned int pstate, sort[8] = { BOOST(1C), BOOST(MAX), BOOST(2C), BOOST(3C), @@ -7408,12 +7592,14 @@ void Compute_AMD_Family_12h_Boost(unsigned int cpu) }; for (pstate = 0; pstate <= 7; pstate++) { + unsigned int fid, did; PSTATEDEF PstateDef = {.value = 0}; RDMSR(PstateDef, (MSR_AMD_PSTATE_DEF_BASE + pstate)); - PUBLIC(RO(Core, AT(cpu)))->Boost[sort[pstate]] = \ - (PstateDef.Family_12h.CpuFid + 0x10) - / PstateDef.Family_12h.CpuDid; + fid = PstateDef.Family_12h.CpuFid + 0x10; + did = PstateDef.Family_12h.CpuDid; + + PUBLIC(RO(Core, AT(cpu)))->Boost[sort[pstate]] = fid / did; } } @@ -7436,7 +7622,7 @@ static void Query_AMD_Family_12h(unsigned int cpu) HyperThreading_Technology(); } -void Compute_AMD_Family_14h_Boost(unsigned int cpu) +static void Compute_AMD_Family_14h_Boost(unsigned int cpu) { COFVID CofVid = {.value = 0}; unsigned int MaxFreq = 100, ClockDiv; @@ -7457,8 +7643,8 @@ void Compute_AMD_Family_14h_Boost(unsigned int cpu) ClockDiv = (PstateDef.Family_14h.CpuDidMSD + 1) * 4; ClockDiv += PstateDef.Family_14h.CpuDidLSD; - PUBLIC(RO(Core, AT(cpu)))->Boost[sort[pstate]] = (MaxFreq * 4) - / ClockDiv; + PUBLIC(RO(Core, AT(cpu)))->Boost[sort[pstate]] = \ + (MaxFreq * 4) / ClockDiv; } /* Frequency @ MainPllOpFidMax (MHz) */ } @@ -7495,7 +7681,7 @@ inline unsigned int AMD_F15h_CoreFID(unsigned int COF, unsigned int DID) return FID; } -void Compute_AMD_Family_15h_Boost(unsigned int cpu) +static void Compute_AMD_Family_15h_Boost(unsigned int cpu) { if (PUBLIC(RO(Proc))->Features.AdvPower.EDX.HwPstate) { @@ -7612,7 +7798,7 @@ inline unsigned short AMD_Zen_Compute_FID_DID( unsigned int COF, } } -unsigned short AMD_Zen_CoreFID( unsigned int COF, +static unsigned short AMD_Zen_CoreFID( unsigned int COF, unsigned int *FID, unsigned int *DID ) { @@ -7625,14 +7811,13 @@ unsigned short AMD_Zen_CoreFID( unsigned int COF, return ret; } -bool Compute_AMD_Zen_Boost(unsigned int cpu) +static bool Compute_AMD_Zen_Boost(unsigned int cpu) { COF_ST COF = {.Q = 0, .R = 0}; unsigned int pstate, sort[8] = { /* P[0..7]-States */ BOOST(MAX), BOOST(1C), BOOST(2C), BOOST(3C), BOOST(4C) , BOOST(5C), BOOST(6C), BOOST(7C) }; - HWCR HwCfgRegister = {.value = 0}; PSTATEDEF PstateDef = {.value = 0}; PSTATECTRL PstateCtrl = {.value = 0}; @@ -7681,12 +7866,14 @@ bool Compute_AMD_Zen_Boost(unsigned int cpu) PUBLIC(RO(Core, AT(cpu)))->Boost[BOOST(TGT)] = COF.Q; /* If CPB is enabled then add Boost + XFR to the P0 ratio. */ - RDMSR(HwCfgRegister, MSR_K7_HWCR); - if (HwCfgRegister.Family_17h.CpbDis == 0) + RDMSR(PUBLIC(RO(Core, AT(cpu)))->SystemRegister.HWCR, MSR_K7_HWCR); + if (PUBLIC(RO(Core, AT(cpu)))->SystemRegister.HWCR.Family_17h.CpbDis == 0) { AMD_17_ZEN2_COF XtraCOF = {.value = 0}; switch (PUBLIC(RO(Proc))->ArchID) { + case AMD_Zen4_PHX2: + case AMD_Zen4_HWK: case AMD_Zen4_PHX: case AMD_Zen4_RPL: case AMD_Zen3Plus_RMB: @@ -7697,12 +7884,13 @@ bool Compute_AMD_Zen_Boost(unsigned int cpu) PRIVATE(OF(Zen)).Device.DF); break; case AMD_Zen4_Bergamo: - case AMD_Zen4_Genoa: case AMD_EPYC_Rome_CPK: Core_AMD_SMN_Read(XtraCOF, SMU_AMD_F17H_ZEN2_MCM_COF, PRIVATE(OF(Zen)).Device.DF); break; + case AMD_Zen4_Genoa: + break; } if (XtraCOF.value != 0) { @@ -7802,12 +7990,14 @@ static void TurboClock_AMD_Zen_PerCore(void *arg) { CLOCK_ZEN_ARG *pClockZen = (CLOCK_ZEN_ARG *) arg; PSTATEDEF PstateDef = {.value = 0}; - HWCR HwCfgRegister = {.value = 0}; COF_ST COF = {.Q = 0, .R = 0}; unsigned int FID, DID; + const unsigned int smp = pClockZen->pClockMod->cpu == -1 ? + smp_processor_id() : pClockZen->pClockMod->cpu; + /* Make sure the Core Performance Boost is disabled. */ - RDMSR(HwCfgRegister, MSR_K7_HWCR); - if (HwCfgRegister.Family_17h.CpbDis) + RDMSR(PUBLIC(RO(Core, AT(smp)))->SystemRegister.HWCR, MSR_K7_HWCR); + if (PUBLIC(RO(Core, AT(smp)))->SystemRegister.HWCR.Family_17h.CpbDis) { /* Apply if and only if the P-State is enabled ? */ RDMSR(PstateDef, pClockZen->PstateAddr); @@ -7947,7 +8137,7 @@ inline unsigned int CPPC_AMD_Zen_ScaleHint( CORE_RO *Core, return flag; } -signed int Put_ACPI_CPPC_Registers(unsigned int cpu, void *arg) +static signed int Put_ACPI_CPPC_Registers(unsigned int cpu, void *arg) { #if defined (CONFIG_ACPI_CPPC_LIB) \ && LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0) @@ -7958,23 +8148,30 @@ signed int Put_ACPI_CPPC_Registers(unsigned int cpu, void *arg) CORE_RO *Core = (CORE_RO *) PUBLIC(RO(Core, AT(cpu))); + RDMSR(Core->SystemRegister.HWCR, MSR_K7_HWCR); + if ((cppc_get_perf_ctrs(Core->Bind, &CPPC_Perf) == 0) && (cppc_get_perf_caps(Core->Bind, &CPPC_Caps) == 0)) { - HWCR HwCfgRegister = {.value = 0}; unsigned short WrRdCPPC = 0; struct cppc_perf_ctrls perf_ctrls = { .max_perf = CPPC_Caps.highest_perf, #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 18, 0) - .min_perf = CPPC_AMD_Zen_ScaleHint(Core, - Core->PowerThermal.ACPI_CPPC.Highest, - CPPC_Caps.lowest_freq / PRECISION, - !HwCfgRegister.Family_17h.CpbDis), + .min_perf = CPPC_AMD_Zen_ScaleHint( + Core, + Core->PowerThermal.ACPI_CPPC.Highest, + CPPC_Caps.lowest_freq / PRECISION, + !Core->SystemRegister.HWCR.Family_17h.CpbDis + ), #else .min_perf = CPPC_Caps.lowest_perf, #endif + #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0) .desired_perf = CPPC_Perf.reference_perf + #else + .desired_perf = CPPC_Caps.reference_perf + #endif }; #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 1, 0) unsigned long long desired_perf = 0; @@ -7986,8 +8183,6 @@ signed int Put_ACPI_CPPC_Registers(unsigned int cpu, void *arg) } #endif - RDMSR(HwCfgRegister, MSR_K7_HWCR); - switch (pClockZen->pClockMod->NC) { case CLOCK_MOD_HWP_MIN: pClockZen->rc = -RC_UNIMPLEMENTED; @@ -7999,20 +8194,22 @@ signed int Put_ACPI_CPPC_Registers(unsigned int cpu, void *arg) { unsigned int hint; if (pClockZen->pClockMod->cpu == -1) { - hint = CPPC_AMD_Zen_ScaleHint( Core, - Core->PowerThermal.ACPI_CPPC.Highest, - pClockZen->pClockMod->Ratio, - !HwCfgRegister.Family_17h.CpbDis ); - + hint = CPPC_AMD_Zen_ScaleHint( + Core, + Core->PowerThermal.ACPI_CPPC.Highest, + pClockZen->pClockMod->Ratio, + !Core->SystemRegister.HWCR.Family_17h.CpbDis + ); perf_ctrls.desired_perf = hint & 0xff; WrRdCPPC = 1; } else if (pClockZen->pClockMod->cpu == cpu) { - hint = CPPC_AMD_Zen_ScaleHint( Core, - Core->PowerThermal.ACPI_CPPC.Highest, - Core->Boost[BOOST(HWP_TGT)] - + pClockZen->pClockMod->Offset, - !HwCfgRegister.Family_17h.CpbDis ); - + hint = CPPC_AMD_Zen_ScaleHint( + Core, + Core->PowerThermal.ACPI_CPPC.Highest, + Core->Boost[BOOST(HWP_TGT)] + + pClockZen->pClockMod->Offset, + !Core->SystemRegister.HWCR.Family_17h.CpbDis + ); perf_ctrls.desired_perf = hint & 0xff; WrRdCPPC = 1; } @@ -8030,20 +8227,24 @@ signed int Put_ACPI_CPPC_Registers(unsigned int cpu, void *arg) { perf_ctrls.max_perf = CPPC_Caps.highest_perf; #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 18, 0) - perf_ctrls.min_perf = CPPC_AMD_Zen_ScaleHint(Core, - Core->PowerThermal.ACPI_CPPC.Highest, - CPPC_Caps.lowest_freq / PRECISION, - !HwCfgRegister.Family_17h.CpbDis); - + perf_ctrls.min_perf = \ + CPPC_AMD_Zen_ScaleHint( + Core, + Core->PowerThermal.ACPI_CPPC.Highest, + CPPC_Caps.lowest_freq / PRECISION, + !Core->SystemRegister.HWCR.Family_17h.CpbDis + ); Core->PowerThermal.ACPI_CPPC.Minimum = CPPC_Caps.lowest_freq; #else perf_ctrls.min_perf = CPPC_Caps.lowest_perf; - Core->PowerThermal.ACPI_CPPC.Minimum = CPPC_AMD_Zen_ScaleRatio( - Core, - 255U, - CPPC_Caps.lowest_perf, - !HwCfgRegister.Family_17h.CpbDis); + Core->PowerThermal.ACPI_CPPC.Minimum = \ + CPPC_AMD_Zen_ScaleRatio( + Core, + 255U, + CPPC_Caps.lowest_perf, + !Core->SystemRegister.HWCR.Family_17h.CpbDis + ); #endif Core->PowerThermal.ACPI_CPPC.Maximum = CPPC_Caps.highest_perf; @@ -8070,7 +8271,7 @@ signed int Put_ACPI_CPPC_Registers(unsigned int cpu, void *arg) #endif /* CONFIG_ACPI_CPPC_LIB */ } -signed int Write_ACPI_CPPC_Registers(unsigned int cpu, void *arg) +static signed int Write_ACPI_CPPC_Registers(unsigned int cpu, void *arg) { signed int rc = Put_ACPI_CPPC_Registers(cpu, arg); @@ -8085,11 +8286,10 @@ static void CPPC_AMD_Zen_PerCore(void *arg) unsigned int cpu = smp_processor_id(); CORE_RO *Core = (CORE_RO *) PUBLIC(RO(Core, AT(cpu))); - HWCR HwCfgRegister = {.value = 0}; AMD_CPPC_REQUEST CPPC_Req = {.value = 0}; unsigned short WrRdCPPC = 0; - RDMSR(HwCfgRegister, MSR_K7_HWCR); + RDMSR(Core->SystemRegister.HWCR, MSR_K7_HWCR); RDMSR(CPPC_Req, MSR_AMD_CPPC_REQ); switch (pClockZen->pClockMod->NC) { @@ -8097,14 +8297,18 @@ static void CPPC_AMD_Zen_PerCore(void *arg) { unsigned int hint; if (pClockZen->pClockMod->cpu == -1) { - hint = CPPC_AMD_Zen_ScaleHint( Core, 255U, - pClockZen->pClockMod->Ratio, - !HwCfgRegister.Family_17h.CpbDis ); + hint = CPPC_AMD_Zen_ScaleHint( + Core, 255U, + pClockZen->pClockMod->Ratio, + !Core->SystemRegister.HWCR.Family_17h.CpbDis + ); } else { - hint = CPPC_AMD_Zen_ScaleHint( Core, 255U, - Core->Boost[BOOST(HWP_MIN)] - + pClockZen->pClockMod->Offset, - !HwCfgRegister.Family_17h.CpbDis ); + hint = CPPC_AMD_Zen_ScaleHint( + Core, 255U, + Core->Boost[BOOST(HWP_MIN)] + + pClockZen->pClockMod->Offset, + !Core->SystemRegister.HWCR.Family_17h.CpbDis + ); } if ((hint & (1 << 31)) == (1 << 31)) { @@ -8119,14 +8323,18 @@ static void CPPC_AMD_Zen_PerCore(void *arg) { unsigned int hint; if (pClockZen->pClockMod->cpu == -1) { - hint = CPPC_AMD_Zen_ScaleHint( Core, 255U, - pClockZen->pClockMod->Ratio, - !HwCfgRegister.Family_17h.CpbDis ); + hint = CPPC_AMD_Zen_ScaleHint( + Core, 255U, + pClockZen->pClockMod->Ratio, + !Core->SystemRegister.HWCR.Family_17h.CpbDis + ); } else { - hint = CPPC_AMD_Zen_ScaleHint( Core, 255U, - Core->Boost[BOOST(HWP_MAX)] - + pClockZen->pClockMod->Offset, - !HwCfgRegister.Family_17h.CpbDis ); + hint = CPPC_AMD_Zen_ScaleHint( + Core, 255U, + Core->Boost[BOOST(HWP_MAX)] + + pClockZen->pClockMod->Offset, + !Core->SystemRegister.HWCR.Family_17h.CpbDis + ); } if ((hint & (1 << 31)) == (1 << 31)) { @@ -8141,14 +8349,18 @@ static void CPPC_AMD_Zen_PerCore(void *arg) { unsigned int hint; if (pClockZen->pClockMod->cpu == -1) { - hint = CPPC_AMD_Zen_ScaleHint( Core, 255U, - pClockZen->pClockMod->Ratio, - !HwCfgRegister.Family_17h.CpbDis ); + hint = CPPC_AMD_Zen_ScaleHint( + Core, 255U, + pClockZen->pClockMod->Ratio, + !Core->SystemRegister.HWCR.Family_17h.CpbDis + ); } else { - hint = CPPC_AMD_Zen_ScaleHint( Core, 255U, - Core->Boost[BOOST(HWP_TGT)] - + pClockZen->pClockMod->Offset, - !HwCfgRegister.Family_17h.CpbDis ); + hint = CPPC_AMD_Zen_ScaleHint( + Core, 255U, + Core->Boost[BOOST(HWP_TGT)] + + pClockZen->pClockMod->Offset, + !Core->SystemRegister.HWCR.Family_17h.CpbDis + ); } if ((hint & (1 << 31)) == (1 << 31)) { @@ -8169,16 +8381,22 @@ static void CPPC_AMD_Zen_PerCore(void *arg) RDMSR(CPPC_Req, MSR_AMD_CPPC_REQ); Core->PowerThermal.HWP_Request.Minimum_Perf = \ - CPPC_AMD_Zen_ScaleRatio(Core, 255U, CPPC_Req.Minimum_Perf, - !HwCfgRegister.Family_17h.CpbDis); + CPPC_AMD_Zen_ScaleRatio( + Core, 255U, CPPC_Req.Minimum_Perf, + !Core->SystemRegister.HWCR.Family_17h.CpbDis + ); Core->PowerThermal.HWP_Request.Maximum_Perf = \ - CPPC_AMD_Zen_ScaleRatio(Core, 255U, CPPC_Req.Maximum_Perf, - !HwCfgRegister.Family_17h.CpbDis); + CPPC_AMD_Zen_ScaleRatio( + Core, 255U, CPPC_Req.Maximum_Perf, + !Core->SystemRegister.HWCR.Family_17h.CpbDis + ); Core->PowerThermal.HWP_Request.Desired_Perf = \ - CPPC_AMD_Zen_ScaleRatio(Core, 255U, CPPC_Req.Desired_Perf, - !HwCfgRegister.Family_17h.CpbDis); + CPPC_AMD_Zen_ScaleRatio( + Core, 255U, CPPC_Req.Desired_Perf, + !Core->SystemRegister.HWCR.Family_17h.CpbDis + ); Core->Boost[BOOST(HWP_MIN)]=Core->PowerThermal.HWP_Request.Minimum_Perf; Core->Boost[BOOST(HWP_MAX)]=Core->PowerThermal.HWP_Request.Maximum_Perf; @@ -8188,7 +8406,8 @@ static void CPPC_AMD_Zen_PerCore(void *arg) } } -long For_All_AMD_Zen_Clock(CLOCK_ZEN_ARG *pClockZen, void (*PerCore)(void *)) +static long For_All_AMD_Zen_Clock( CLOCK_ZEN_ARG *pClockZen, + void (*PerCore)(void *) ) { long rc = RC_SUCCESS; unsigned int cpu = PUBLIC(RO(Proc))->CPU.Count; @@ -8207,7 +8426,7 @@ long For_All_AMD_Zen_Clock(CLOCK_ZEN_ARG *pClockZen, void (*PerCore)(void *)) return rc; } -long ClockSource_OC_Granted(void) +static long ClockSource_OC_Granted(void) { long rc = -RC_CLOCKSOURCE; @@ -8259,7 +8478,8 @@ long ClockSource_OC_Granted(void) return rc; } -long For_All_AMD_Zen_BaseClock(CLOCK_ZEN_ARG *pClockZen, void (*PerCore)(void*)) +static long For_All_AMD_Zen_BaseClock( CLOCK_ZEN_ARG *pClockZen, + void (*PerCore)(void*) ) { long rc; unsigned int cpu = PUBLIC(RO(Proc))->Service.Core; @@ -8356,7 +8576,7 @@ static long ClockMod_AMD_Zen(CLOCK_ARG *pClockMod) } } -void Query_AMD_F17h_Power_Limits(PROC_RO *Pkg) +static void Query_AMD_F17h_Power_Limits(PROC_RO *Pkg) { /* Package Power Tracking */ Core_AMD_SMN_Read( Pkg->PowerThermal.Zen.PWR, SMU_AMD_F17H_ZEN2_MCM_PWR, @@ -8374,7 +8594,7 @@ void Query_AMD_F17h_Power_Limits(PROC_RO *Pkg) PRIVATE(OF(Zen)).Device.DF ); } -unsigned int Query_AMD_HSMP_Interface(void) +static unsigned int Query_AMD_HSMP_Interface(void) { HSMP_ARG arg[8]; unsigned int rx = HSMP_UNSPECIFIED; @@ -8532,7 +8752,7 @@ unsigned int Query_AMD_HSMP_Interface(void) return rx; } -void Query_AMD_Family_17h(unsigned int cpu) +static void Query_AMD_Family_17h(unsigned int cpu) { PRIVATE(OF(Specific)) = LookupProcessor(); if (PRIVATE(OF(Specific)) != NULL) @@ -8615,6 +8835,26 @@ static void Query_AMD_F17h_PerCluster(unsigned int cpu) } } +static void Query_AMD_F19h_11h_PerCluster(unsigned int cpu) +{ + Core_AMD_Family_17h_Temp = CCD_AMD_Family_19h_Genoa_Temp; + + Probe_AMD_DataFabric(); + + Query_AMD_Family_17h(cpu); + + if (cpu == PUBLIC(RO(Proc))->Service.Core) { + Query_AMD_F17h_Power_Limits(PUBLIC(RO(Proc))); + if (AMD_F17h_CPPC() == -ENODEV) { + For_All_ACPI_CPPC(Read_ACPI_CPPC_Registers, NULL); + } + Read_ACPI_PCT_Registers(cpu); + Read_ACPI_PSS_Registers(cpu); + Read_ACPI_PPC_Registers(cpu); + Read_ACPI_CST_Registers(cpu); + } +} + static void Query_AMD_F19h_61h_PerCluster(unsigned int cpu) { Core_AMD_Family_17h_Temp = CCD_AMD_Family_19h_Zen4_Temp; @@ -8660,7 +8900,7 @@ static void Query_Hygon_F18h(unsigned int cpu) Query_AMD_F17h_PerSocket(cpu); } -void Dump_CPUID(CORE_RO *Core) +static void Dump_CPUID(CORE_RO *Core) { unsigned int i; @@ -8729,7 +8969,7 @@ void Dump_CPUID(CORE_RO *Core) } } -void AMD_F17h_DCU_Technology(CORE_RO *Core) /* Per Core */ +static void AMD_F17h_DCU_Technology(CORE_RO *Core) /* Per Core */ { AMD_DC_CFG DC_Cfg1 = {.value = 0}; AMD_CU_CFG3 CU_Cfg3 = {.value = 0}; @@ -8765,7 +9005,6 @@ void AMD_F17h_DCU_Technology(CORE_RO *Core) /* Per Core */ break; } - if (DC_Cfg1.L1_HW_Prefetch) { BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_HW_Prefetch, Core->Bind); @@ -8783,10 +9022,87 @@ void AMD_F17h_DCU_Technology(CORE_RO *Core) /* Per Core */ } else { BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_HW_IP_Prefetch, Core->Bind); } + + if (PUBLIC(RO(Proc))->Features.ExtFeature2_EAX.PrefetchCtl_MSR == 1) + { + int ToggleFeature = 0; + AMD_PREFETCH_CONTROL PrefetchCtl = {.value = 0}; + RDMSR(PrefetchCtl, MSR_AMD_PREFETCH_CTRL); + + switch (L1_STRIDE_PREFETCH_Disable) { + case COREFREQ_TOGGLE_OFF: + case COREFREQ_TOGGLE_ON: + PrefetchCtl.L1Stride = L1_STRIDE_PREFETCH_Disable; + ToggleFeature = 1; + break; + } + switch (L1_REGION_PREFETCH_Disable) { + case COREFREQ_TOGGLE_OFF: + case COREFREQ_TOGGLE_ON: + PrefetchCtl.L1Region = L1_REGION_PREFETCH_Disable; + ToggleFeature = 1; + break; + } + switch (L1_BURST_PREFETCH_Disable) { + case COREFREQ_TOGGLE_OFF: + case COREFREQ_TOGGLE_ON: + PrefetchCtl.L1Stream = L1_BURST_PREFETCH_Disable; + ToggleFeature = 1; + break; + } + switch (L2_STREAM_PREFETCH_Disable) { + case COREFREQ_TOGGLE_OFF: + case COREFREQ_TOGGLE_ON: + PrefetchCtl.L2Stream = L2_STREAM_PREFETCH_Disable; + ToggleFeature = 1; + break; + } + switch (L2_UPDOWN_PREFETCH_Disable) { + case COREFREQ_TOGGLE_OFF: + case COREFREQ_TOGGLE_ON: + PrefetchCtl.UpDown = L2_UPDOWN_PREFETCH_Disable; + ToggleFeature = 1; + break; + } + if (ToggleFeature == 1) { + WRMSR(PrefetchCtl, MSR_AMD_PREFETCH_CTRL); + RDMSR(PrefetchCtl, MSR_AMD_PREFETCH_CTRL); + } + if (PrefetchCtl.L1Stride) + { + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_Stride_Pf, Core->Bind); + } else { + BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_Stride_Pf, Core->Bind); + } + if (PrefetchCtl.L1Region) + { + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_Region_Pf, Core->Bind); + } else { + BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_Region_Pf, Core->Bind); + } + if (PrefetchCtl.L1Stream) + { + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_Burst_Pf, Core->Bind); + } else { + BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_Burst_Pf, Core->Bind); + } + if (PrefetchCtl.L2Stream) + { + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L2_Stream_HW_Pf, Core->Bind); + } else { + BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->L2_Stream_HW_Pf, Core->Bind); + } + if (PrefetchCtl.UpDown) + { + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L2_UpDown_Pf, Core->Bind); + } else { + BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->L2_UpDown_Pf, Core->Bind); + } + } BITSET_CC(LOCKLESS, PUBLIC(RO(Proc))->DCU_Mask, Core->Bind); } -void Intel_DCU_Technology(CORE_RO *Core) /*Per Core */ +static void Intel_DCU_Technology(CORE_RO *Core) /*Per Core */ { /* Avoton[06_4D], GDM[06_5C], NHM[06_1A, 06_1E, 06_1F, 06_2E], SNB+, Phi */ if ((Core->T.ThreadID == 0) || (Core->T.ThreadID == -1)) { @@ -8822,6 +9138,13 @@ void Intel_DCU_Technology(CORE_RO *Core) /*Per Core */ ToggleFeature = 1; break; } + switch (L1_NPP_PREFETCH_Disable) { + case COREFREQ_TOGGLE_OFF: + case COREFREQ_TOGGLE_ON: + MiscFeatCtrl.L1_NPP_Prefetch = L1_NPP_PREFETCH_Disable; + ToggleFeature = 1; + break; + } if (ToggleFeature == 1) { WRMSR(MiscFeatCtrl, MSR_MISC_FEATURE_CONTROL); @@ -8846,12 +9169,122 @@ void Intel_DCU_Technology(CORE_RO *Core) /*Per Core */ BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_HW_IP_Prefetch, Core->Bind); } else { BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_HW_IP_Prefetch, Core->Bind); + } + if (MiscFeatCtrl.L1_NPP_Prefetch == 1) { + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_NPP_Prefetch, Core->Bind); + } else { + BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_NPP_Prefetch, Core->Bind); } BITSET_CC(LOCKLESS, PUBLIC(RO(Proc))->DCU_Mask, Core->Bind); + + switch (Core->T.Cluster.Hybrid.CoreType) { + case Hybrid_Atom: + { + ATOM_L2_PREFETCH_0X1321 MLC_Ctrl = {.value = 0}; + ATOM_L2_PREFETCH_0X1320 LLC_Ctrl = {.value = 0}; + + RDMSR(MLC_Ctrl, MSR_ATOM_L2_PREFETCH_0X1321); + RDMSR(LLC_Ctrl, MSR_ATOM_L2_PREFETCH_0X1320); + + switch (L2_NLP_PREFETCH_Disable) { + case COREFREQ_TOGGLE_OFF: + case COREFREQ_TOGGLE_ON: + MLC_Ctrl.L2_DISABLE_NEXT_LINE_PREFETCH = L2_NLP_PREFETCH_Disable; + WRMSR(MLC_Ctrl, MSR_ATOM_L2_PREFETCH_0X1321); + RDMSR(MLC_Ctrl, MSR_ATOM_L2_PREFETCH_0X1321); + break; + } + if (MLC_Ctrl.L2_DISABLE_NEXT_LINE_PREFETCH == 1) { + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L2_NLP_Prefetch, Core->Bind); + } else { + BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->L2_NLP_Prefetch, Core->Bind); + } + + switch (LLC_Streamer_Disable) { + case COREFREQ_TOGGLE_OFF: + case COREFREQ_TOGGLE_ON: + LLC_Ctrl.LLC_STREAM_DISABLE = LLC_Streamer_Disable; + WRMSR(LLC_Ctrl, MSR_ATOM_L2_PREFETCH_0X1320); + RDMSR(LLC_Ctrl, MSR_ATOM_L2_PREFETCH_0X1320); + break; + } + if (LLC_Ctrl.LLC_STREAM_DISABLE == 1) { + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->LLC_Streamer, Core->Bind); + } else { + BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->LLC_Streamer, Core->Bind); + } + BITSET_CC(LOCKLESS, PUBLIC(RO(Proc))->ECORE_Mask, Core->Bind); + } + break; + case Hybrid_Core: + /* Invalid MSR_ATOM_L2_PREFETCH registers with P-Core */ + break; + case Hybrid_RSVD1: + case Hybrid_RSVD2: + default: + break; + } + } +} + +static void Intel_Core_MicroArchitecture(CORE_RO *Core) /* Per P-Core */ +{ /* 06_7D, 06_7E, 06_8C, 06_8D, 06_97, 06_9A, 06_B7, 06_BA, 06_BF, MTL */ + if ((Core->T.ThreadID == 0) || (Core->T.ThreadID == -1)) + { + switch (Core->T.Cluster.Hybrid.CoreType) { + case Hybrid_Atom: + /* No MSR_CORE_UARCH_CTL(0x541) register with E-Core */ + break; + case Hybrid_Core: + { + CORE_UARCH_CTL Core_Uarch_Ctl = {.value = 0}; + MISC_FEATURE_CONTROL MiscFeatCtrl = {.value = 0}; + + RDMSR(Core_Uarch_Ctl, MSR_CORE_UARCH_CTL); + + switch (L1_Scrubbing_Enable) { + case COREFREQ_TOGGLE_OFF: + case COREFREQ_TOGGLE_ON: + Core_Uarch_Ctl.L1_Scrubbing_En = L1_Scrubbing_Enable; + WRMSR(Core_Uarch_Ctl, MSR_CORE_UARCH_CTL); + RDMSR(Core_Uarch_Ctl, MSR_CORE_UARCH_CTL); + break; + } + if (Core_Uarch_Ctl.L1_Scrubbing_En == 1) { + BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_Scrubbing, Core->Bind); + } else { + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_Scrubbing, Core->Bind); + } + + RDMSR(MiscFeatCtrl, MSR_MISC_FEATURE_CONTROL); + + switch (L2_AMP_PREFETCH_Disable) { + case COREFREQ_TOGGLE_OFF: + case COREFREQ_TOGGLE_ON: + MiscFeatCtrl.L2_AMP_Prefetch = L2_AMP_PREFETCH_Disable; + WRMSR(MiscFeatCtrl, MSR_MISC_FEATURE_CONTROL); + RDMSR(MiscFeatCtrl, MSR_MISC_FEATURE_CONTROL); + break; + } + if (MiscFeatCtrl.L2_AMP_Prefetch == 1) { + BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->L2_AMP_Prefetch, Core->Bind); + } else { + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L2_AMP_Prefetch, Core->Bind); + } + + BITSET_CC(LOCKLESS, PUBLIC(RO(Proc))->PCORE_Mask, Core->Bind); + } + break; + case Hybrid_RSVD1: + case Hybrid_RSVD2: + default: + /* Unspecified MSR_CORE_UARCH_CTL(0x541) register with IDs */ + break; + } } } -void SpeedStep_Technology(CORE_RO *Core) /*Per Package*/ +static void SpeedStep_Technology(CORE_RO *Core) /*Per Package*/ { if (Core->Bind == PUBLIC(RO(Proc))->Service.Core) { if (PUBLIC(RO(Proc))->Features.Std.ECX.EIST == 1) @@ -8880,9 +9313,9 @@ void SpeedStep_Technology(CORE_RO *Core) /*Per Package*/ } } -void Intel_Turbo_Config(CORE_RO *Core, void (*ConfigFunc)(void*),/*Per Package*/ +static void Intel_Turbo_Config(CORE_RO *Core, void (*ConfigFunc)(void*), void (*AssignFunc)(unsigned int*, TURBO_CONFIG*)) -{ +{ /*Per Package*/ CLOCK_TURBO_ARG ClockTurbo = { .pClockMod = NULL, /* Read-Only Operation */ .Config = {.MSR = {.value = 0}}, @@ -8964,7 +9397,7 @@ static int Cmp_Skylake_Target(CORE_RO *Core, unsigned int ratio) return (Core->PowerThermal.PerfControl.SNB.TargetRatio >= ratio); } -bool IsPerformanceControlCapable(void) +static bool IsPerformanceControlCapable(void) { struct SIGNATURE blackList[] = { _Silvermont_Bay_Trail, /* 06_37 */ @@ -8987,7 +9420,7 @@ bool IsPerformanceControlCapable(void) return true; } -bool WritePerformanceControl(PERF_CONTROL *pPerfControl) +static bool WritePerformanceControl(PERF_CONTROL *pPerfControl) { bool isCapable = IsPerformanceControlCapable(); if (isCapable == true) @@ -8997,7 +9430,7 @@ bool WritePerformanceControl(PERF_CONTROL *pPerfControl) return isCapable; } -void TurboBoost_Technology(CORE_RO *Core, SET_TARGET SetTarget, +static void TurboBoost_Technology(CORE_RO *Core,SET_TARGET SetTarget, GET_TARGET GetTarget, CMP_TARGET CmpTarget, unsigned int TurboRatio, @@ -9083,7 +9516,7 @@ void TurboBoost_Technology(CORE_RO *Core, SET_TARGET SetTarget, } } -void DynamicAcceleration(CORE_RO *Core) /* Unique */ +static void DynamicAcceleration(CORE_RO *Core) /* Unique */ { if (IsPerformanceControlCapable() == true) { @@ -9154,7 +9587,7 @@ void DynamicAcceleration(CORE_RO *Core) /* Unique */ } } -void SoC_Turbo_Override(CORE_RO *Core) +static void SoC_Turbo_Override(CORE_RO *Core) { int ToggleFeature; @@ -9222,7 +9655,7 @@ static void ClockMod_PPC_PerCore(void *arg) Core->Boost[BOOST(TGT)] = pClockPPC->GetTarget(Core); } -long For_All_PPC_Clock(CLOCK_PPC_ARG *pClockPPC) +static long For_All_PPC_Clock(CLOCK_PPC_ARG *pClockPPC) { long rc = RC_SUCCESS; unsigned int cpu = PUBLIC(RO(Proc))->CPU.Count; @@ -9355,7 +9788,7 @@ static void ClockMod_HWP_PerCore(void *arg) } } -long For_All_HWP_Clock(CLOCK_HWP_ARG *pClockHWP) +static long For_All_HWP_Clock(CLOCK_HWP_ARG *pClockHWP) { long rc = RC_SUCCESS; unsigned int cpu = PUBLIC(RO(Proc))->CPU.Count; @@ -9401,7 +9834,7 @@ static long ClockMod_Intel_HWP(CLOCK_ARG *pClockMod) } -void AMD_Watchdog(CORE_RO *Core) +static void AMD_Watchdog(CORE_RO *Core) { /* CPU Watchdog Timer. */ if ((Core->T.ThreadID == 0) || (Core->T.ThreadID == -1)) { @@ -9425,24 +9858,23 @@ void AMD_Watchdog(CORE_RO *Core) } } -void PerCore_AMD_CState_BAR(CORE_RO *Core) +static void PerCore_AMD_CState_BAR(CORE_RO *Core) { /* Families: 10h, 12h, 14h, 15h, 16h, 17h: I/O C-State Base Address. */ CSTATE_BASE_ADDR CStateBaseAddr = {.value = 0}; RDMSR(CStateBaseAddr, MSR_AMD_CSTATE_BAR); Core->Query.CStateBaseAddr = CStateBaseAddr.IOaddr; } -void PerCore_Query_AMD_Zen_Features(CORE_RO *Core) /* Per SMT */ +static void PerCore_Query_AMD_Zen_Features(CORE_RO *Core) /* Per SMT */ { ZEN_CSTATE_CONFIG CStateCfg = {.value = 0}; int ToggleFeature; /* Read The Hardware Configuration Register. */ - HWCR HwCfgRegister = {.value = 0}; - RDMSR(HwCfgRegister, MSR_K7_HWCR); + RDMSR(Core->SystemRegister.HWCR, MSR_K7_HWCR); /* Query the SMM. */ - if (HwCfgRegister.Family_17h.SmmLock) { + if (Core->SystemRegister.HWCR.Family_17h.SmmLock) { BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->SMM, Core->Bind); } else { BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->SMM, Core->Bind); @@ -9450,11 +9882,11 @@ void PerCore_Query_AMD_Zen_Features(CORE_RO *Core) /* Per SMT */ /* Enable or Disable the Core Performance Boost. */ switch (TurboBoost_Enable[0]) { case COREFREQ_TOGGLE_OFF: - HwCfgRegister.Family_17h.CpbDis = 1; + Core->SystemRegister.HWCR.Family_17h.CpbDis = 1; ToggleFeature = 1; break; case COREFREQ_TOGGLE_ON: - HwCfgRegister.Family_17h.CpbDis = 0; + Core->SystemRegister.HWCR.Family_17h.CpbDis = 0; ToggleFeature = 1; break; default: @@ -9463,10 +9895,10 @@ void PerCore_Query_AMD_Zen_Features(CORE_RO *Core) /* Per SMT */ } if (ToggleFeature == 1) { - WRMSR(HwCfgRegister, MSR_K7_HWCR); - RDMSR(HwCfgRegister, MSR_K7_HWCR); + WRMSR(Core->SystemRegister.HWCR, MSR_K7_HWCR); + RDMSR(Core->SystemRegister.HWCR, MSR_K7_HWCR); } - if (HwCfgRegister.Family_17h.CpbDis == 0) + if (Core->SystemRegister.HWCR.Family_17h.CpbDis == 0) { BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->TurboBoost, Core->Bind); } else { @@ -9500,7 +9932,7 @@ void PerCore_Query_AMD_Zen_Features(CORE_RO *Core) /* Per SMT */ RDMSR(CStateCfg, MSR_AMD_F17H_CSTATE_CONFIG); } if (CStateCfg.CCR2_CC6EN && CStateCfg.CCR1_CC6EN && CStateCfg.CCR0_CC6EN - && HwCfgRegister.Family_17h.INVDWBINVD) + && Core->SystemRegister.HWCR.Family_17h.INVDWBINVD) { BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->CC6, Core->Bind); } else { @@ -9568,7 +10000,7 @@ void PerCore_Query_AMD_Zen_Features(CORE_RO *Core) /* Per SMT */ AMD_Watchdog(Core); } -void Intel_Watchdog(CORE_RO *Core) +static void Intel_Watchdog(CORE_RO *Core) { struct pci_device_id PCI_WDT_ids[] = { { @@ -9595,7 +10027,7 @@ void Intel_Watchdog(CORE_RO *Core) BITSET_CC(LOCKLESS, PUBLIC(RO(Proc))->WDT_Mask, Core->Bind); } -void Intel_Turbo_Activation_Ratio(CORE_RO *Core) +static void Intel_Turbo_Activation_Ratio(CORE_RO *Core) { TURBO_ACTIVATION TurboActivation = {.value = 0}; @@ -9622,7 +10054,7 @@ void Intel_Turbo_Activation_Ratio(CORE_RO *Core) } } -void Intel_Turbo_TDP_Config(CORE_RO *Core) +static void Intel_Turbo_TDP_Config(CORE_RO *Core) { CONFIG_TDP_NOMINAL NominalTDP = {.value = 0}; CONFIG_TDP_CONTROL ControlTDP = {.value = 0}; @@ -9678,7 +10110,7 @@ void Intel_Turbo_TDP_Config(CORE_RO *Core) } } -void Query_Intel_C1E(CORE_RO *Core) /*Per Package*/ +static void Query_Intel_C1E(CORE_RO *Core) /*Per Package*/ { if (Core->Bind == PUBLIC(RO(Proc))->Service.Core) { @@ -9703,7 +10135,7 @@ void Query_Intel_C1E(CORE_RO *Core) /*Per Package*/ } } -void Query_AMD_Family_0Fh_C1E(CORE_RO *Core) /* Per Core */ +static void Query_AMD_Family_0Fh_C1E(CORE_RO *Core) /* Per Core */ { INT_PENDING_MSG IntPendingMsg = {.value = 0}; @@ -9718,7 +10150,7 @@ void Query_AMD_Family_0Fh_C1E(CORE_RO *Core) /* Per Core */ BITSET_CC(LOCKLESS, PUBLIC(RO(Proc))->C1E_Mask, Core->Bind); } -void ThermalMonitor2_Set(CORE_RO *Core, MISC_PROC_FEATURES MiscFeatures) +static void ThermalMonitor2_Set(CORE_RO *Core, MISC_PROC_FEATURES MiscFeatures) { /* Intel Core Solo Duo. */ struct SIGNATURE whiteList[] = { _Core_Yonah , /* 06_0E */ @@ -9733,7 +10165,8 @@ void ThermalMonitor2_Set(CORE_RO *Core, MISC_PROC_FEATURES MiscFeatures) _Tigerlake_U , /* 06_8C */ _Alderlake_S /* 06_97 */ }; - int id, ids = sizeof(whiteList) / sizeof(whiteList[0]); + const int ids = sizeof(whiteList) / sizeof(whiteList[0]); + int id; for (id = 0; id < ids; id++) { if((whiteList[id].ExtFamily == PUBLIC(RO(Proc))->Features.Std.EAX.ExtFamily) @@ -9760,7 +10193,7 @@ void ThermalMonitor2_Set(CORE_RO *Core, MISC_PROC_FEATURES MiscFeatures) } } -void ThermalMonitor_IA32(CORE_RO *Core) +static void ThermalMonitor_IA32(CORE_RO *Core) { MISC_PROC_FEATURES MiscFeatures = {.value = 0}; THERM_STATUS ThermStatus = {.value = 0}; @@ -10066,7 +10499,7 @@ void ThermalMonitor_IA32(CORE_RO *Core) } } -void ThermalMonitor_Atom_Bonnell(CORE_RO *Core) +static void ThermalMonitor_Atom_Bonnell(CORE_RO *Core) { Core->PowerThermal.Param.Offset[THERMAL_TARGET] = 100; Core->PowerThermal.Param.Offset[THERMAL_OFFSET_P1] = 0; @@ -10074,7 +10507,7 @@ void ThermalMonitor_Atom_Bonnell(CORE_RO *Core) ThermalMonitor_IA32(Core); } -void ThermalMonitor_Set(CORE_RO *Core) +static void ThermalMonitor_Set(CORE_RO *Core) { TJMAX TjMax = {.value = 0}; PLATFORM_INFO PfInfo = {.value = 0}; @@ -10114,7 +10547,7 @@ void ThermalMonitor_Set(CORE_RO *Core) ThermalMonitor_IA32(Core); } -void CorePerfLimitReasons(CORE_RO *Core) +static void CorePerfLimitReasons(CORE_RO *Core) { if (Core->Bind == PUBLIC(RO(Proc))->Service.Core) { @@ -10206,7 +10639,7 @@ void CorePerfLimitReasons(CORE_RO *Core) } } -void GraphicsPerfLimitReasons(CORE_RO *Core) +static void GraphicsPerfLimitReasons(CORE_RO *Core) { if (Core->Bind == PUBLIC(RO(Proc))->Service.Core) { @@ -10280,7 +10713,7 @@ void GraphicsPerfLimitReasons(CORE_RO *Core) } } -void RingPerfLimitReasons(CORE_RO *Core) +static void RingPerfLimitReasons(CORE_RO *Core) { if (Core->Bind == PUBLIC(RO(Proc))->Service.Core) { @@ -10348,9 +10781,9 @@ void RingPerfLimitReasons(CORE_RO *Core) } } -void PowerThermal(CORE_RO *Core) +static void PowerThermal(CORE_RO *Core) { - struct { +static struct { struct SIGNATURE Arch; unsigned short grantPWR_MGMT : 1-0, grantODCM : 2-1, @@ -10448,9 +10881,14 @@ void PowerThermal(CORE_RO *Core) {_Raptorlake_P, 1, 1, 0, 0}, {_Raptorlake_S, 1, 1, 0, 0}, {_Lunarlake, 1, 1, 1, 0}, /* 06_BD */ - {_Arrowlake, 1, 1, 1, 0} /* 06_C6 */ + {_Arrowlake, 1, 1, 1, 0}, /* 06_C6 */ + {_Arrowlake_H, 1, 1, 1, 0}, /* 06_C5 */ + {_Arrowlake_U, 1, 1, 1, 0}, /* 06_B5 */ + {_Pantherlake, 1, 1, 1, 0}, /* 06_CC */ + {_Clearwater_Forest, 1, 1, 1, 0} /* 06_DD */ }; - unsigned int id, ids = sizeof(whiteList) / sizeof(whiteList[0]); + const unsigned int ids = sizeof(whiteList) / sizeof(whiteList[0]); + unsigned int id; for (id = 0; id < ids; id++) { if((whiteList[id].Arch.ExtFamily==PUBLIC(RO(Proc))->Features.Std.EAX.ExtFamily) @@ -10788,8 +11226,8 @@ MAKE_TOGGLE_CSTATE_FUNC(MC6_CONFIG, MC6demotion, PC6_Enable) ret; \ }) -void Control_IO_MWAIT( struct CSTATES_ENCODING_ST IORedir[], - CORE_RO *Core ) +static void Control_IO_MWAIT( struct CSTATES_ENCODING_ST IORedir[], + CORE_RO *Core ) { CSTATE_IO_MWAIT CState_IO_MWAIT = {.value = 0}; RDMSR(CState_IO_MWAIT, MSR_PMG_IO_CAPTURE_BASE); @@ -10829,9 +11267,9 @@ void Control_IO_MWAIT( struct CSTATES_ENCODING_ST IORedir[], ); } -void Control_CSTATES_NHM( struct CSTATES_ENCODING_ST Limit[], +static void Control_CSTATES_NHM(struct CSTATES_ENCODING_ST Limit[], struct CSTATES_ENCODING_ST IORedir[], - CORE_RO *Core ) + CORE_RO *Core) { /* Family: 06_1A, 06_1E, 06_1F, 06_25, 06_2C, 06_2E */ CSTATE_CONFIG CStateConfig = {.value = 0}; unsigned int toggleFeature = 0; @@ -10909,11 +11347,11 @@ void Control_CSTATES_NHM( struct CSTATES_ENCODING_ST Limit[], Control_IO_MWAIT(IORedir, Core); } -void Control_CSTATES_COMMON( struct CSTATES_ENCODING_ST Limit[], - struct CSTATES_ENCODING_ST IORedir[], - CORE_RO *Core, - const unsigned short bitMask, - const unsigned short unMask ) +static void Control_CSTATES_COMMON( struct CSTATES_ENCODING_ST Limit[], + struct CSTATES_ENCODING_ST IORedir[], + CORE_RO *Core, + const unsigned short bitMask, + const unsigned short unMask ) { CSTATE_CONFIG CStateConfig = {.value = 0}; unsigned int toggleFeature = 0; @@ -11011,32 +11449,32 @@ void Control_CSTATES_COMMON( struct CSTATES_ENCODING_ST Limit[], Control_IO_MWAIT(IORedir, Core); } -void Control_CSTATES_SNB( struct CSTATES_ENCODING_ST Limit[], +static void Control_CSTATES_SNB(struct CSTATES_ENCODING_ST Limit[], struct CSTATES_ENCODING_ST IORedir[], - CORE_RO *Core ) + CORE_RO *Core) { /* Family: 06_2A, 06_3A, 06_3E, 06_3F, 06_4F, 06_56, 06_57, 06_85 */ Control_CSTATES_COMMON(Limit, IORedir, Core, 0b0111, 0b1000); } -void Control_CSTATES_ULT( struct CSTATES_ENCODING_ST Limit[], +static void Control_CSTATES_ULT(struct CSTATES_ENCODING_ST Limit[], struct CSTATES_ENCODING_ST IORedir[], - CORE_RO *Core ) + CORE_RO *Core) { /* Family: 06_3C, 06_3D, 06_45, 06_46, 06_47, 06_86 */ Control_CSTATES_COMMON(Limit, IORedir, Core, 0b1111, 0b0000); } -void Control_CSTATES_SKL( struct CSTATES_ENCODING_ST Limit[], +static void Control_CSTATES_SKL(struct CSTATES_ENCODING_ST Limit[], struct CSTATES_ENCODING_ST IORedir[], - CORE_RO *Core ) + CORE_RO *Core) { /* Family: 06_4E, 06_5E, 06_55, 06_66, 06_7D, 06_7E, 06_8E, 06_9E */ Control_CSTATES_COMMON(Limit, IORedir, Core, 0b0111, 0b1000); } -void Control_CSTATES_SOC_ATOM( struct CSTATES_ENCODING_ST Limit[], - struct CSTATES_ENCODING_ST IORedir[], - CORE_RO *Core, - const unsigned short bitMask, - const unsigned short unMask ) +static void Control_CSTATES_SOC_ATOM( struct CSTATES_ENCODING_ST Limit[], + struct CSTATES_ENCODING_ST IORedir[], + CORE_RO *Core, + const unsigned short bitMask, + const unsigned short unMask ) { CSTATE_CONFIG CStateConfig = {.value = 0}; unsigned int toggleFeature = 0; @@ -11094,9 +11532,9 @@ void Control_CSTATES_SOC_ATOM( struct CSTATES_ENCODING_ST Limit[], Control_IO_MWAIT(IORedir, Core); } -void Control_CSTATES_SOC_SLM( struct CSTATES_ENCODING_ST Limit[], - struct CSTATES_ENCODING_ST IORedir[], - CORE_RO *Core ) +static void Control_CSTATES_SOC_SLM( struct CSTATES_ENCODING_ST Limit[], + struct CSTATES_ENCODING_ST IORedir[], + CORE_RO *Core ) { /* Family: 06_37, 06_4A, 06_4C, 06_4D, 06_5A */ CC6_CONFIG CC6_Config = {.value = 0}; MC6_CONFIG MC6_Config = {.value = 0}; @@ -11133,9 +11571,9 @@ void Control_CSTATES_SOC_SLM( struct CSTATES_ENCODING_ST Limit[], BITSET_CC(LOCKLESS, PUBLIC(RO(Proc))->PC6_Mask, Core->Bind); } -void Control_CSTATES_SOC_GDM( struct CSTATES_ENCODING_ST Limit[], - struct CSTATES_ENCODING_ST IORedir[], - CORE_RO *Core ) +static void Control_CSTATES_SOC_GDM( struct CSTATES_ENCODING_ST Limit[], + struct CSTATES_ENCODING_ST IORedir[], + CORE_RO *Core ) { /* Family: 06_5CH */ Control_CSTATES_SOC_ATOM(Limit, IORedir, Core, 0b1111, 0b0000); } @@ -11149,7 +11587,7 @@ void Control_CSTATES_SOC_GDM( struct CSTATES_ENCODING_ST Limit[], Control_##_CLASS(Limit_##_CLASS, IORedir_##_CLASS, Core); \ }) -void PerCore_AMD_Family_0Fh_PStates(CORE_RO *Core) +static void PerCore_AMD_Family_0Fh_PStates(CORE_RO *Core) { FIDVID_STATUS FidVidStatus = {.value = 0}; FIDVID_CONTROL FidVidControl = {.value = 0}; @@ -11187,16 +11625,34 @@ void PerCore_AMD_Family_0Fh_PStates(CORE_RO *Core) } while (FidVidStatus.FidVidPending == 1) ; } -void SystemRegisters(CORE_RO *Core) +static void SystemRegisters(CORE_RO *Core) { + unsigned long long mem64; + __asm__ volatile ( - "# RFLAGS" "\n\t" - "pushfq" "\n\t" - "popq %0" "\n\t" + "xorq %%rbx, %%rbx" "\n\t" + "xorq %%rcx, %%rcx" "\n\t" + "xorq %%rdx, %%rdx" "\n\t" + "# Carry, Sign, Overflow Flags" "\n\t" + "xorq %%rax, %%rax" "\n\t" + "cmpl $-0x80000000, %%eax" "\n\t" + "# Zero Flag" "\n\t" + "movq %%rax, %1" "\n\t" + "cmpxchg8b %1" "\n\t" + "# Direction Flag" "\n\t" + "std" "\n\t" + "# Interrupt Flag" "\n\t" + "sti" "\n\t" + "# Save all RFLAGS" "\n\t" + "pushfq" "\n\t" + "popq %0" "\n\t" + "# Reset Flags" "\n\t" + "cli" "\n\t" + "cld" : "=r" (Core->SystemRegister.RFLAGS) - : - : + : "m" (mem64) + : "%rax", "%rbx", "%rcx", "%rdx", "cc" ); if (RDPMC_Enable) { __asm__ volatile @@ -11284,6 +11740,7 @@ void SystemRegisters(CORE_RO *Core) && BITVAL(Core->SystemRegister.CR4, CR4_OSXSAVE)) { __asm__ volatile ( + "# XCR0" "\n\t" "xorq %%rcx, %%rcx" "\n\t" "xgetbv" "\n\t" "shlq $32, %%rdx" "\n\t" @@ -11294,9 +11751,25 @@ void SystemRegisters(CORE_RO *Core) : "%rax", "%rcx", "%rdx" ); } + if (PUBLIC(RO(Proc))->Features.ExtState_Leaf1.EAX.IA32_XSS) { + __asm__ volatile + ( + "# XSS" "\n\t" + "xorq %%rax, %%rax" "\n\t" + "xorq %%rdx, %%rdx" "\n\t" + "movq %1,%%rcx" "\n\t" + "rdmsr" "\n\t" + "shlq $32, %%rdx" "\n\t" + "orq %%rdx, %%rax" "\n\t" + "movq %%rax, %0" + : "=r" (Core->SystemRegister.XSS) + : "i" (MSR_IA32_XSS) + : "%rax", "%rcx", "%rdx" + ); + } } -void Intel_Mitigation_Mechanisms(CORE_RO *Core) +static void Intel_Mitigation_Mechanisms(CORE_RO *Core) { SPEC_CTRL Spec_Ctrl = {.value = 0}; PRED_CMD Pred_Cmd = {.value = 0}; @@ -11566,6 +12039,26 @@ void Intel_Mitigation_Mechanisms(CORE_RO *Core) } else { BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->PBRSB_NO, Core->Bind); } + if (Arch_Cap.OVERCLOCKING_STATUS_MSR) { + OVERCLOCKING_STATUS OC_Status = {.value = 0}; + RDMSR(OC_Status, MSR_IA32_OVERCLOCKING_STATUS); + + if (OC_Status.OC_Utilized) { + BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->OC_UTILIZED, Core->Bind); + } else { + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->OC_UTILIZED, Core->Bind); + } + if (OC_Status.OC_Undervolt) { + BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->OC_UNDERVOLT, Core->Bind); + } else { + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->OC_UNDERVOLT, Core->Bind); + } + if (OC_Status.OC_Unlocked) { + BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->OC_UNLOCKED, Core->Bind); + } else { + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->OC_UNLOCKED, Core->Bind); + } + } } if (PUBLIC(RO(Proc))->Features.ExtFeature.EDX.IA32_CORE_CAP) { @@ -11624,7 +12117,7 @@ void Intel_Mitigation_Mechanisms(CORE_RO *Core) BITSET_CC(LOCKLESS, PUBLIC(RO(Proc))->ARCH_CAP_Mask, Core->Bind); } -void AMD_Mitigation_Mechanisms(CORE_RO *Core) +static void AMD_Mitigation_Mechanisms(CORE_RO *Core) { AMD_SPEC_CTRL Spec_Ctrl = {.value = 0}; AMD_PRED_CMD Pred_Cmd = {.value = 0}; @@ -11753,14 +12246,18 @@ void AMD_Mitigation_Mechanisms(CORE_RO *Core) BITSET_CC(LOCKLESS, PUBLIC(RO(Proc))->ARCH_CAP_Mask, Core->Bind); switch (PUBLIC(RO(Proc))->ArchID) { + case AMD_EPYC_Rome_CPK: case AMD_Zen2_Renoir: case AMD_Zen2_LCN: case AMD_Zen2_MTS: case AMD_Zen2_Ariel: case AMD_Zen2_Jupiter: + case AMD_Zen2_Galileo: case AMD_Zen2_MDN: { + AMD_LS_CFG LS_CFG = {.value = 0}; AMD_DE_CFG2 DE_CFG = {.value = 0}; + RDMSR(DE_CFG, MSR_AMD_DE_CFG2); if (((Mech_BTC_NOBR == COREFREQ_TOGGLE_OFF) @@ -11776,6 +12273,21 @@ void AMD_Mitigation_Mechanisms(CORE_RO *Core) } else { BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->BTC_NOBR, Core->Bind); } + + RDMSR(LS_CFG, MSR_AMD64_LS_CFG); + + if ( (Mech_AGENPICK == COREFREQ_TOGGLE_OFF) + || (Mech_AGENPICK == COREFREQ_TOGGLE_ON) ) + { + LS_CFG.F17h_AgenPick = Mech_AGENPICK; + WRMSR(LS_CFG, MSR_AMD64_LS_CFG); + RDMSR(LS_CFG, MSR_AMD64_LS_CFG); + } + if (LS_CFG.F17h_AgenPick == 1) { + BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->AGENPICK, Core->Bind); + } else { + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->AGENPICK, Core->Bind); + } } break; default: @@ -11783,9 +12295,46 @@ void AMD_Mitigation_Mechanisms(CORE_RO *Core) break; } BITSET_CC(LOCKLESS, PUBLIC(RO(Proc))->BTC_NOBR_Mask, Core->Bind); + + if ((Core->T.ThreadID == 0) || (Core->T.ThreadID == -1)) { + switch (PUBLIC(RO(Proc))->ArchID) { + case AMD_EPYC_Rome_CPK: + case AMD_Zen2_Renoir: + case AMD_Zen2_LCN: + case AMD_Zen2_MTS: + case AMD_Zen2_Ariel: + case AMD_Zen2_Jupiter: + case AMD_Zen2_Galileo: + case AMD_Zen2_MDN: + { + AMD_DE_CFG DE_CFG = {.value = 0}; + RDMSR(DE_CFG, MSR_AMD64_DE_CFG); + + if ((Mech_XPROC_LEAK == COREFREQ_TOGGLE_OFF) + || (Mech_XPROC_LEAK == COREFREQ_TOGGLE_ON)) + { + DE_CFG.Cross_Proc_Leak = Mech_XPROC_LEAK; + WRMSR(DE_CFG, MSR_AMD64_DE_CFG); + RDMSR(DE_CFG, MSR_AMD64_DE_CFG); + } + if (DE_CFG.Cross_Proc_Leak) { + BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->XPROC_LEAK, Core->Bind); + } else { + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->XPROC_LEAK, Core->Bind); + } + } + break; + default: + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->XPROC_LEAK, Core->Bind); + break; + } + BITSET_CC(LOCKLESS, PUBLIC(RO(Proc))->XPROC_LEAK_Mask, Core->Bind); + } else { + BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->XPROC_LEAK_Mask, Core->Bind); + } } -void Intel_VirtualMachine(CORE_RO *Core) +static void Intel_VirtualMachine(CORE_RO *Core) { if (PUBLIC(RO(Proc))->Features.Std.ECX.VMX) { VMX_BASIC VMX_Basic = {.value = 0}; @@ -11801,7 +12350,7 @@ void Intel_VirtualMachine(CORE_RO *Core) } } -void Intel_Microcode(CORE_RO *Core) +static void Intel_Microcode(CORE_RO *Core) { MICROCODE_ID Microcode = {.value = 0}; @@ -11809,7 +12358,7 @@ void Intel_Microcode(CORE_RO *Core) Core->Query.Microcode = Microcode.Signature; } -void AMD_Microcode(CORE_RO *Core) +static void AMD_Microcode(CORE_RO *Core) { unsigned long long value = 0; RDMSR64(value, MSR_AMD64_PATCH_LEVEL); @@ -11823,11 +12372,13 @@ void AMD_Microcode(CORE_RO *Core) BITWISECLR(LOCKLESS, Pkg->ThermalPoint.State); \ }) -void PerCore_Reset(CORE_RO *Core) +static void PerCore_Reset(CORE_RO *Core) { BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->TM_Mask , Core->Bind); BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->ODCM_Mask , Core->Bind); BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->DCU_Mask , Core->Bind); + BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->PCORE_Mask, Core->Bind); + BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->ECORE_Mask, Core->Bind); BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->PowerMgmt_Mask, Core->Bind); BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->SpeedStep_Mask, Core->Bind); BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->TurboBoost_Mask,Core->Bind); @@ -11843,6 +12394,7 @@ void PerCore_Reset(CORE_RO *Core) BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->SPEC_CTRL_Mask, Core->Bind); BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->ARCH_CAP_Mask , Core->Bind); BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->BTC_NOBR_Mask , Core->Bind); + BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->XPROC_LEAK_Mask,Core->Bind); BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->CR_Mask , Core->Bind); BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->WDT_Mask , Core->Bind); @@ -11852,8 +12404,17 @@ void PerCore_Reset(CORE_RO *Core) BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->ODCM , Core->Bind); BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_HW_Prefetch , Core->Bind); BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_HW_IP_Prefetch , Core->Bind); + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_NPP_Prefetch , Core->Bind); + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_Scrubbing , Core->Bind); BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L2_HW_Prefetch , Core->Bind); BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L2_HW_CL_Prefetch , Core->Bind); + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L2_AMP_Prefetch , Core->Bind); + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_Stride_Pf , Core->Bind); + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_Region_Pf , Core->Bind); + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_Burst_Pf , Core->Bind); + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L2_Stream_HW_Pf , Core->Bind); + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L2_UpDown_Pf , Core->Bind); + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->LLC_Streamer , Core->Bind); BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->PowerMgmt , Core->Bind); BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->SpeedStep , Core->Bind); BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->TurboBoost, Core->Bind); @@ -11911,6 +12472,10 @@ void PerCore_Reset(CORE_RO *Core) BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->DDPD_U_DIS, Core->Bind); BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->BHI_DIS_S , Core->Bind); BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->BTC_NOBR , Core->Bind); + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->XPROC_LEAK, Core->Bind); + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->OC_UTILIZED, Core->Bind); + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->OC_UNDERVOLT, Core->Bind); + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->OC_UNLOCKED, Core->Bind); BITWISECLR(LOCKLESS, Core->ThermalPoint.Mask); BITWISECLR(LOCKLESS, Core->ThermalPoint.Kind); @@ -12122,7 +12687,7 @@ static void PerCore_Atom_Bonnell_Query(void *arg) ThermalMonitor_Atom_Bonnell(Core); } -void Compute_Intel_Silvermont_Burst(CORE_RO *Core) +static void Compute_Intel_Silvermont_Burst(CORE_RO *Core) { enum RATIO_BOOST boost; unsigned int burstRatio; @@ -12314,10 +12879,7 @@ static void PerCore_Atom_Goldmont_Query(void *arg) static void PerCore_Goldmont_Query(void *arg) { - CORE_RO *Core = (CORE_RO *) arg; - PerCore_Atom_Goldmont_Query(arg); - Intel_Turbo_Activation_Ratio(Core); } static void PerCore_Geminilake_Query(void *arg) @@ -12325,6 +12887,15 @@ static void PerCore_Geminilake_Query(void *arg) PerCore_Atom_Goldmont_Query(arg); } +static void PerCore_Tremont_Query(void *arg) +{ + CORE_RO *Core = (CORE_RO *) arg; + + PerCore_Atom_Goldmont_Query(arg); + + Intel_Turbo_Activation_Ratio(Core); +} + static void PerCore_Nehalem_Same_Query(void *arg) { CORE_RO *Core = (CORE_RO *) arg; @@ -12891,6 +13462,24 @@ static void PerCore_Kaby_Lake_Query(void *arg) } } +static void PerCore_Icelake_Query(void *arg) +{ + CORE_RO *Core = (CORE_RO *) arg; + + PerCore_Skylake_Query(arg); + + Intel_Core_MicroArchitecture(Core); +} + +static void PerCore_Tigerlake_Query(void *arg) +{ + CORE_RO *Core = (CORE_RO *) arg; + + PerCore_Kaby_Lake_Query(arg); + + Intel_Core_MicroArchitecture(Core); +} + static void PerCore_AMD_Family_0Fh_Query(void *arg) { CORE_RO *Core = (CORE_RO *) arg; @@ -12924,7 +13513,7 @@ static void PerCore_AMD_Family_0Fh_Query(void *arg) BITSET_CC(LOCKLESS, PUBLIC(RO(Proc))->WDT_Mask, Core->Bind); } -void PerCore_AMD_Family_Same_Query(void *arg) +static void PerCore_AMD_Family_Same_Query(void *arg) { CORE_RO *Core = (CORE_RO *) arg; @@ -13235,28 +13824,35 @@ static void PerCore_AMD_Family_17h_Query(void *arg) /* Collaborative Processor Performance Control */ if (PUBLIC(RO(Proc))->Features.HWP_Enable) { - HWCR HwCfgRegister = {.value = 0}; AMD_CPPC_CAP1 CPPC_Cap = {.value = 0}; AMD_CPPC_REQUEST CPPC_Req = {.value = 0}; - RDMSR(HwCfgRegister, MSR_K7_HWCR); + RDMSR(Core->SystemRegister.HWCR, MSR_K7_HWCR); RDMSR(CPPC_Cap, MSR_AMD_CPPC_CAP1); Core->PowerThermal.HWP_Capabilities.Highest = \ - CPPC_AMD_Zen_ScaleRatio(Core, 255U, CPPC_Cap.Highest, - !HwCfgRegister.Family_17h.CpbDis); + CPPC_AMD_Zen_ScaleRatio( + Core, 255U, CPPC_Cap.Highest, + !Core->SystemRegister.HWCR.Family_17h.CpbDis + ); Core->PowerThermal.HWP_Capabilities.Guaranteed = \ - CPPC_AMD_Zen_ScaleRatio(Core, 255U, CPPC_Cap.Nominal, - !HwCfgRegister.Family_17h.CpbDis); + CPPC_AMD_Zen_ScaleRatio( + Core, 255U, CPPC_Cap.Nominal, + !Core->SystemRegister.HWCR.Family_17h.CpbDis + ); Core->PowerThermal.HWP_Capabilities.Most_Efficient = \ - CPPC_AMD_Zen_ScaleRatio(Core, 255U, CPPC_Cap.LowNonlinear, - !HwCfgRegister.Family_17h.CpbDis); + CPPC_AMD_Zen_ScaleRatio( + Core, 255U, CPPC_Cap.LowNonlinear, + !Core->SystemRegister.HWCR.Family_17h.CpbDis + ); Core->PowerThermal.HWP_Capabilities.Lowest = \ - CPPC_AMD_Zen_ScaleRatio(Core, 255U, CPPC_Cap.Lowest, - !HwCfgRegister.Family_17h.CpbDis); + CPPC_AMD_Zen_ScaleRatio( + Core, 255U, CPPC_Cap.Lowest, + !Core->SystemRegister.HWCR.Family_17h.CpbDis + ); RDMSR(CPPC_Req, MSR_AMD_CPPC_REQ); if ((HWP_EPP >= 0) && (HWP_EPP <= 0xff)) @@ -13267,16 +13863,22 @@ static void PerCore_AMD_Family_17h_Query(void *arg) } Core->PowerThermal.HWP_Request.Minimum_Perf = \ - CPPC_AMD_Zen_ScaleRatio(Core, 255U, CPPC_Req.Minimum_Perf, - !HwCfgRegister.Family_17h.CpbDis); + CPPC_AMD_Zen_ScaleRatio( + Core, 255U, CPPC_Req.Minimum_Perf, + !Core->SystemRegister.HWCR.Family_17h.CpbDis + ); Core->PowerThermal.HWP_Request.Maximum_Perf = \ - CPPC_AMD_Zen_ScaleRatio(Core, 255U, CPPC_Req.Maximum_Perf, - !HwCfgRegister.Family_17h.CpbDis); + CPPC_AMD_Zen_ScaleRatio( + Core, 255U, CPPC_Req.Maximum_Perf, + !Core->SystemRegister.HWCR.Family_17h.CpbDis + ); Core->PowerThermal.HWP_Request.Desired_Perf = \ - CPPC_AMD_Zen_ScaleRatio(Core, 255U, CPPC_Req.Desired_Perf, - !HwCfgRegister.Family_17h.CpbDis); + CPPC_AMD_Zen_ScaleRatio( + Core, 255U, CPPC_Req.Desired_Perf, + !Core->SystemRegister.HWCR.Family_17h.CpbDis + ); Core->PowerThermal.HWP_Request.Energy_Pref = CPPC_Req.Energy_Pref; @@ -13286,21 +13888,19 @@ static void PerCore_AMD_Family_17h_Query(void *arg) } else if (PUBLIC(RO(Proc))->Features.ACPI_CPPC) { - HWCR HwCfgRegister = {.value = 0}; - - RDMSR(HwCfgRegister, MSR_K7_HWCR); + RDMSR(Core->SystemRegister.HWCR, MSR_K7_HWCR); Core->PowerThermal.HWP_Capabilities.Highest = \ CPPC_AMD_Zen_ScaleRatio(Core, PUBLIC(RO(Proc))->PowerThermal.ACPI_CPPC.Maximum, Core->PowerThermal.ACPI_CPPC.Highest, - !HwCfgRegister.Family_17h.CpbDis + !Core->SystemRegister.HWCR.Family_17h.CpbDis ); Core->PowerThermal.HWP_Capabilities.Guaranteed = \ CPPC_AMD_Zen_ScaleRatio(Core, PUBLIC(RO(Proc))->PowerThermal.ACPI_CPPC.Maximum, Core->PowerThermal.ACPI_CPPC.Guaranteed, - !HwCfgRegister.Family_17h.CpbDis + !Core->SystemRegister.HWCR.Family_17h.CpbDis ); #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 18, 0) Core->PowerThermal.HWP_Capabilities.Most_Efficient = \ @@ -13316,32 +13916,32 @@ static void PerCore_AMD_Family_17h_Query(void *arg) CPPC_AMD_Zen_ScaleRatio(Core, PUBLIC(RO(Proc))->PowerThermal.ACPI_CPPC.Maximum, Core->PowerThermal.ACPI_CPPC.Efficient, - !HwCfgRegister.Family_17h.CpbDis + !Core->SystemRegister.HWCR.Family_17h.CpbDis ); Core->PowerThermal.HWP_Capabilities.Lowest = \ CPPC_AMD_Zen_ScaleRatio(Core, PUBLIC(RO(Proc))->PowerThermal.ACPI_CPPC.Maximum, Core->PowerThermal.ACPI_CPPC.Lowest, - !HwCfgRegister.Family_17h.CpbDis + !Core->SystemRegister.HWCR.Family_17h.CpbDis ); Core->PowerThermal.HWP_Request.Minimum_Perf = \ CPPC_AMD_Zen_ScaleRatio(Core, Core->PowerThermal.ACPI_CPPC.Highest, Core->PowerThermal.ACPI_CPPC.Minimum, - !HwCfgRegister.Family_17h.CpbDis + !Core->SystemRegister.HWCR.Family_17h.CpbDis ); #endif Core->PowerThermal.HWP_Request.Maximum_Perf = \ CPPC_AMD_Zen_ScaleRatio(Core, Core->PowerThermal.ACPI_CPPC.Highest, Core->PowerThermal.ACPI_CPPC.Maximum, - !HwCfgRegister.Family_17h.CpbDis + !Core->SystemRegister.HWCR.Family_17h.CpbDis ); Core->PowerThermal.HWP_Request.Desired_Perf = \ CPPC_AMD_Zen_ScaleRatio(Core, Core->PowerThermal.ACPI_CPPC.Highest, Core->PowerThermal.ACPI_CPPC.Desired, - !HwCfgRegister.Family_17h.CpbDis + !Core->SystemRegister.HWCR.Family_17h.CpbDis ); Core->PowerThermal.HWP_Request.Energy_Pref = \ Core->PowerThermal.ACPI_CPPC.Energy; @@ -13353,18 +13953,19 @@ static void PerCore_AMD_Family_17h_Query(void *arg) } #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 56) -void Sys_DumpTask(SYSGATE_RO *SysGate) +inline void Sys_DumpTask(SYSGATE_RO *SysGate) { SysGate->taskCount = 0; } #else /* KERNEL_VERSION(3, 10, 56) */ -void Sys_DumpTask(SYSGATE_RO *SysGate) +static void Sys_DumpTask(SYSGATE_RO *SysGate) { /* Source: /include/linux/sched.h */ struct task_struct *process, *thread; int cnt = 0; rcu_read_lock(); for_each_process_thread(process, thread) { + if (cnt < TASK_LIMIT) { #if defined(CONFIG_SCHED_MUQSS) \ || defined(CONFIG_SCHED_BMQ) \ || defined(CONFIG_SCHED_PDS) @@ -13377,10 +13978,11 @@ void Sys_DumpTask(SYSGATE_RO *SysGate) SysGate->taskList[cnt].pid = thread->pid; SysGate->taskList[cnt].tgid = thread->tgid; SysGate->taskList[cnt].ppid = thread->parent->pid; -#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 14, 0) - SysGate->taskList[cnt].state = (short int) thread->state; -#else +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0) \ + || (defined(RHEL_MAJOR) && (RHEL_MAJOR == 8) && (RHEL_MINOR >= 9)) SysGate->taskList[cnt].state = (short int) thread->__state; +#else + SysGate->taskList[cnt].state = (short int) thread->state; #endif #if defined(CONFIG_SCHED_ALT) SysGate->taskList[cnt].wake_cpu = (short int) task_cpu(thread); @@ -13391,9 +13993,8 @@ void Sys_DumpTask(SYSGATE_RO *SysGate) #endif /* CONFIG_SCHED_BMQ */ memcpy(SysGate->taskList[cnt].comm, thread->comm,TASK_COMM_LEN); - if (cnt < TASK_LIMIT) { - cnt++; - } + cnt++; + } } rcu_read_unlock(); SysGate->taskCount = cnt; @@ -13428,7 +14029,7 @@ static void InitTimer(void *Cycle_Function) } } -void Controller_Init(void) +static void Controller_Init(void) { CLOCK sClock = {.Q = 0, .R = 0, .Hz = 0}; unsigned int cpu = PUBLIC(RO(Proc))->CPU.Count, ratio = 0; @@ -13529,7 +14130,7 @@ void Controller_Init(void) } } -void Controller_Start(int wait) +static void Controller_Start(int wait) { if (Arch[PUBLIC(RO(Proc))->ArchID].Start != NULL) { @@ -13547,7 +14148,7 @@ void Controller_Start(int wait) } } -void Controller_Stop(int wait) +static void Controller_Stop(int wait) { if (Arch[PUBLIC(RO(Proc))->ArchID].Stop != NULL) { @@ -13563,7 +14164,7 @@ void Controller_Stop(int wait) } } -void Controller_Exit(void) +static void Controller_Exit(void) { unsigned int cpu; @@ -13577,7 +14178,7 @@ void Controller_Exit(void) } } -void Intel_Core_Counters_Set(union SAVE_AREA_CORE *Save, CORE_RO *Core) +static void Intel_Core_Counters_Set(union SAVE_AREA_CORE *Save, CORE_RO *Core) { UNUSED(Core); @@ -13660,12 +14261,10 @@ void Intel_Core_Counters_Set(union SAVE_AREA_CORE *Save, CORE_RO *Core) ({ \ if (PUBLIC(RO(Proc))->Features.PerfMon.EBX.InstrRetired == 0) \ { \ - HWCR HwCfgRegister = {.value = 0}; \ - \ - RDMSR(HwCfgRegister, MSR_K7_HWCR); \ - Save->Core_HardwareConfiguration = HwCfgRegister; \ - HwCfgRegister.PMC.IRPerfEn = 1 ; \ - WRMSR(HwCfgRegister, MSR_K7_HWCR); \ + RDMSR(Core->SystemRegister.HWCR, MSR_K7_HWCR); \ + Save->Core_HardwareConfiguration = Core->SystemRegister.HWCR; \ + Core->SystemRegister.HWCR.PMC.IRPerfEn = 1 ; \ + WRMSR(Core->SystemRegister.HWCR, MSR_K7_HWCR); \ } \ }) @@ -13684,6 +14283,9 @@ void Intel_Core_Counters_Set(union SAVE_AREA_CORE *Save, CORE_RO *Core) Zen_L3_Cache_PerfControl.EventSelect = 0x90; \ Zen_L3_Cache_PerfControl.UnitMask = 0x00; \ Zen_L3_Cache_PerfControl.CounterEn = 1; \ + Zen_L3_Cache_PerfControl.CoreID = 0; \ + Zen_L3_Cache_PerfControl.EnAllSlices = 0; \ + Zen_L3_Cache_PerfControl.EnAllCores = 0; \ Zen_L3_Cache_PerfControl.SliceMask = 0x0f; \ Zen_L3_Cache_PerfControl.ThreadMask = 0xff; \ WRMSR(Zen_L3_Cache_PerfControl, MSR_AMD_F17H_L3_PERF_CTL); \ @@ -13767,7 +14369,7 @@ void Intel_Core_Counters_Set(union SAVE_AREA_CORE *Save, CORE_RO *Core) } \ }) -void Intel_Core_Counters_Clear(union SAVE_AREA_CORE *Save, CORE_RO *Core) +static void Intel_Core_Counters_Clear(union SAVE_AREA_CORE *Save, CORE_RO *Core) { UNUSED(Core); @@ -13779,7 +14381,7 @@ void Intel_Core_Counters_Clear(union SAVE_AREA_CORE *Save, CORE_RO *Core) } } -void AMD_Core_Counters_Clear(union SAVE_AREA_CORE *Save, CORE_RO *Core) +static void AMD_Core_Counters_Clear(union SAVE_AREA_CORE *Save, CORE_RO *Core) { UNUSED(Core); @@ -14319,8 +14921,11 @@ static void PKG_Counters_IvyBridge_EP(CORE_RO *Core, unsigned int T) case Raptorlake: \ case Raptorlake_P: \ case Raptorlake_S: \ - case Lunarlake: \ - case Arrowlake: \ + case LunarLake: \ + case ArrowLake: \ + case ArrowLake_H: \ + case ArrowLake_U: \ + case PantherLake: \ ADL_SA(PRIVATE(OF(PCU)).BAR); \ break; \ } \ @@ -14947,7 +15552,7 @@ static void Power_ACCU_SKL_PLATFORM(PROC_RO *Pkg, unsigned int T) __VA_ARGS__; \ }) -void Core_Intel_Temp(CORE_RO *Core) +static void Core_Intel_Temp(CORE_RO *Core) { THERM_STATUS ThermStatus = {.value = 0}; RDMSR(ThermStatus, MSR_IA32_THERM_STATUS); /*All Intel families.*/ @@ -14997,7 +15602,7 @@ void Core_Intel_Temp(CORE_RO *Core) } \ }) -void Monitor_CorePerfLimitReasons(PROC_RO *Pkg) +static void Monitor_CorePerfLimitReasons(PROC_RO *Pkg) { CORE_PERF_LIMIT_REASONS limit = {.value = 0}; RDMSR(limit, MSR_SKL_CORE_PERF_LIMIT_REASONS); @@ -15033,7 +15638,7 @@ void Monitor_CorePerfLimitReasons(PROC_RO *Pkg) ); } -void Monitor_GraphicsPerfLimitReasons(PROC_RO *Pkg) +static void Monitor_GraphicsPerfLimitReasons(PROC_RO *Pkg) { GRAPHICS_PERF_LIMIT_REASONS limit = {.value = 0}; RDMSR(limit, MSR_GRAPHICS_PERF_LIMIT_REASONS); @@ -15063,7 +15668,7 @@ void Monitor_GraphicsPerfLimitReasons(PROC_RO *Pkg) ); } -void Monitor_RingPerfLimitReasons(PROC_RO *Pkg) +static void Monitor_RingPerfLimitReasons(PROC_RO *Pkg) { RING_PERF_LIMIT_REASONS limit = {.value = 0}; RDMSR(limit, MSR_RING_PERF_LIMIT_REASONS); @@ -15091,7 +15696,7 @@ void Monitor_RingPerfLimitReasons(PROC_RO *Pkg) ); } -void Core_AMD_Family_0Fh_Temp(CORE_RO *Core) +static void Core_AMD_Family_0Fh_Temp(CORE_RO *Core) { if (PUBLIC(RO(Proc))->Features.AdvPower.EDX.TTP == 1) { THERMTRIP_STATUS ThermTrip = {0}; @@ -15113,7 +15718,7 @@ void Core_AMD_Family_0Fh_Temp(CORE_RO *Core) } } -void Core_AMD_Family_15h_00h_Temp(CORE_RO *Core) +static void Core_AMD_Family_15h_00h_Temp(CORE_RO *Core) { TCTL_REGISTER TctlSensor = {.value = 0}; @@ -15131,7 +15736,7 @@ void Core_AMD_Family_15h_00h_Temp(CORE_RO *Core) } /* Bulldozer/Excavator through SMU interface */ -void Core_AMD_Family_15_60h_Temp(CORE_RO *Core) +static void Core_AMD_Family_15_60h_Temp(CORE_RO *Core) { TCTL_REGISTER TctlSensor = {.value = 0}; @@ -15154,7 +15759,7 @@ void Core_AMD_Family_15_60h_Temp(CORE_RO *Core) } } -void Core_AMD_Family_15h_Temp(CORE_RO *Core) +static void Core_AMD_Family_15h_Temp(CORE_RO *Core) { switch (PUBLIC(RO(Proc))->Features.Std.EAX.ExtModel) { case 0x6: @@ -15172,10 +15777,25 @@ void Core_AMD_Family_15h_Temp(CORE_RO *Core) } } +static void Core_AMD_Family_17h_ThermTrip(CORE_RO *Core) +{ + TCTL_THERM_TRIP ThermTrip = {.value = 0}; + + Core_AMD_SMN_Read( ThermTrip, + SMU_AMD_THM_TCTL_REGISTER_F17H + 0x8, + PRIVATE(OF(Zen)).Device.DF ); + + if (ThermTrip.THERM_TP_EN) { + Core->PowerThermal.Events[eSTS] = \ + (Bit64)ThermTrip.THERM_TP << LSHIFT_THERMAL_STS; + } + Core->PowerThermal.Events[eSTS] |= \ + (Bit64)ThermTrip.CTF_THRESHOLD << LSHIFT_CRITIC_TMP; +} + static void CTL_AMD_Family_17h_Temp(CORE_RO *Core) { TCTL_REGISTER TctlSensor = {.value = 0}; - TCTL_THERM_TRIP ThermTrip = {.value = 0}; Core_AMD_SMN_Read( TctlSensor, SMU_AMD_THM_TCTL_REGISTER_F17H, @@ -15194,22 +15814,12 @@ static void CTL_AMD_Family_17h_Temp(CORE_RO *Core) Core->PowerThermal.Param.Offset[THERMAL_OFFSET_P1] = 0; } - Core_AMD_SMN_Read( ThermTrip, - SMU_AMD_THM_TCTL_REGISTER_F17H + 0x8, - PRIVATE(OF(Zen)).Device.DF ); - - if (ThermTrip.THERM_TP_EN) { - Core->PowerThermal.Events[eSTS] = \ - (Bit64)ThermTrip.THERM_TP << LSHIFT_THERMAL_STS; - } - Core->PowerThermal.Events[eSTS] = \ - (Bit64)ThermTrip.CTF_THRESHOLD << LSHIFT_CRITIC_TMP; + Core_AMD_Family_17h_ThermTrip(Core); } static void CCD_AMD_Family_17h_Zen2_Temp(CORE_RO *Core) { TCCD_REGISTER TccdSensor = {.value = 0}; - TCTL_THERM_TRIP ThermTrip = {.value = 0}; Core_AMD_SMN_Read( TccdSensor, (SMU_AMD_THM_TCTL_CCD_REGISTER_F17H @@ -15225,16 +15835,7 @@ static void CCD_AMD_Family_17h_Zen2_Temp(CORE_RO *Core) Core->PowerThermal.Param.Offset[THERMAL_OFFSET_P1] = 0; } - Core_AMD_SMN_Read( ThermTrip, - SMU_AMD_THM_TCTL_REGISTER_F17H + 0x8, - PRIVATE(OF(Zen)).Device.DF ); - - if (ThermTrip.THERM_TP_EN) { - Core->PowerThermal.Events[eSTS] = \ - (Bit64)ThermTrip.THERM_TP << LSHIFT_THERMAL_STS; - } - Core->PowerThermal.Events[eSTS] = \ - (Bit64)ThermTrip.CTF_THRESHOLD << LSHIFT_CRITIC_TMP; + Core_AMD_Family_17h_ThermTrip(Core); } #define Pkg_AMD_Family_17h_Temp(Pkg, Core) \ @@ -15244,13 +15845,12 @@ static void CCD_AMD_Family_17h_Zen2_Temp(CORE_RO *Core) Pkg->PowerThermal.Sensor = Core->PowerThermal.Sensor; \ }) -static void CCD_AMD_Family_19h_Zen4_Temp(CORE_RO *Core) +static void CCD_AMD_Family_19h_Genoa_Temp(CORE_RO *Core) { TCCD_REGISTER TccdSensor = {.value = 0}; - TCTL_THERM_TRIP ThermTrip = {.value = 0}; Core_AMD_SMN_Read( TccdSensor, - (SMU_AMD_THM_TCTL_CCD_REGISTER_F19H_61H + (SMU_AMD_THM_TCTL_CCD_REGISTER_F19H_11H + (Core->T.Cluster.CCD << 2)), PRIVATE(OF(Zen)).Device.DF ); @@ -15263,16 +15863,28 @@ static void CCD_AMD_Family_19h_Zen4_Temp(CORE_RO *Core) Core->PowerThermal.Param.Offset[THERMAL_OFFSET_P1] = 0; } - Core_AMD_SMN_Read( ThermTrip, - SMU_AMD_THM_TCTL_REGISTER_F17H + 0x8, + Core_AMD_Family_17h_ThermTrip(Core); +} + +static void CCD_AMD_Family_19h_Zen4_Temp(CORE_RO *Core) +{ + TCCD_REGISTER TccdSensor = {.value = 0}; + + Core_AMD_SMN_Read( TccdSensor, + (SMU_AMD_THM_TCTL_CCD_REGISTER_F19H_61H + + (Core->T.Cluster.CCD << 2)), PRIVATE(OF(Zen)).Device.DF ); - if (ThermTrip.THERM_TP_EN) { - Core->PowerThermal.Events[eSTS] = \ - (Bit64)ThermTrip.THERM_TP << LSHIFT_THERMAL_STS; + Core->PowerThermal.Sensor = TccdSensor.CurTmp; + + if (TccdSensor.CurTempRangeSel == 1) + { + Core->PowerThermal.Param.Offset[THERMAL_OFFSET_P1] = 49; + } else { + Core->PowerThermal.Param.Offset[THERMAL_OFFSET_P1] = 0; } - Core->PowerThermal.Events[eSTS] = \ - (Bit64)ThermTrip.CTF_THRESHOLD << LSHIFT_CRITIC_TMP; + + Core_AMD_Family_17h_ThermTrip(Core); } @@ -18830,7 +19442,7 @@ static void Start_AMD_Family_15h(void *arg) BITSET(LOCKLESS, PRIVATE(OF(Core, AT(cpu)))->Join.TSM, STARTED); } -void Cycle_AMD_Family_17h(CORE_RO *Core, +static void Cycle_AMD_Family_17h(CORE_RO *Core, void (*Call_SMU)(const unsigned int, const unsigned int, const unsigned long long), const unsigned int plane0, const unsigned int plane1, @@ -19247,49 +19859,49 @@ static void Stop_Uncore_AMD_Family_17h(void *arg) } -long Sys_OS_Driver_Query(void) +static long Sys_OS_Driver_Query(void) { int rc = RC_SUCCESS; #ifdef CONFIG_CPU_FREQ const char *pFreqDriver; - struct cpufreq_policy freqPolicy; + struct cpufreq_policy *pFreqPolicy; #endif /* CONFIG_CPU_FREQ */ #ifdef CONFIG_CPU_IDLE - struct cpuidle_driver *idleDriver; + struct cpuidle_driver *pIdleDriver; #endif /* CONFIG_CPU_IDLE */ memset(&PUBLIC(RO(Proc))->OS, 0, sizeof(OS_DRIVER)); #ifdef CONFIG_CPU_IDLE - if ((idleDriver = cpuidle_get_driver()) != NULL) + if ((pIdleDriver = cpuidle_get_driver()) != NULL) { int idx; StrCopy(PUBLIC(RO(Proc))->OS.IdleDriver.Name, - idleDriver->name, + pIdleDriver->name, CPUIDLE_NAME_LEN); - if (idleDriver->state_count < CPUIDLE_STATE_MAX) { - PUBLIC(RO(Proc))->OS.IdleDriver.stateCount = idleDriver->state_count; + if (pIdleDriver->state_count < CPUIDLE_STATE_MAX) { + PUBLIC(RO(Proc))->OS.IdleDriver.stateCount = pIdleDriver->state_count; } else { PUBLIC(RO(Proc))->OS.IdleDriver.stateCount = CPUIDLE_STATE_MAX; } - PUBLIC(RO(Proc))->OS.IdleDriver.stateLimit = idleDriver->state_count; + PUBLIC(RO(Proc))->OS.IdleDriver.stateLimit = pIdleDriver->state_count; for (idx = 0; idx < PUBLIC(RO(Proc))->OS.IdleDriver.stateCount; idx++) { StrCopy(PUBLIC(RO(Proc))->OS.IdleDriver.State[idx].Name, - idleDriver->states[idx].name, CPUIDLE_NAME_LEN); + pIdleDriver->states[idx].name, CPUIDLE_NAME_LEN); StrCopy(PUBLIC(RO(Proc))->OS.IdleDriver.State[idx].Desc, - idleDriver->states[idx].desc, CPUIDLE_NAME_LEN); + pIdleDriver->states[idx].desc, CPUIDLE_NAME_LEN); PUBLIC(RO(Proc))->OS.IdleDriver.State[idx].exitLatency = \ - idleDriver->states[idx].exit_latency; + pIdleDriver->states[idx].exit_latency; PUBLIC(RO(Proc))->OS.IdleDriver.State[idx].powerUsage = \ - idleDriver->states[idx].power_usage; + pIdleDriver->states[idx].power_usage; PUBLIC(RO(Proc))->OS.IdleDriver.State[idx].targetResidency = \ - idleDriver->states[idx].target_residency; + pIdleDriver->states[idx].target_residency; } if(PUBLIC(RO(Proc))->Registration.Driver.CPUidle == REGISTRATION_ENABLE) { @@ -19309,10 +19921,10 @@ long Sys_OS_Driver_Query(void) StrCopy(PUBLIC(RO(Proc))->OS.FreqDriver.Name, pFreqDriver, CPUFREQ_NAME_LEN); } - memset(&freqPolicy, 0, sizeof(freqPolicy)); - if((rc=cpufreq_get_policy(&freqPolicy, PUBLIC(RO(Proc))->Service.Core))==0) + if ((pFreqPolicy=kzalloc(sizeof(struct cpufreq_policy),GFP_KERNEL)) != NULL) { + if((rc=cpufreq_get_policy(pFreqPolicy,PUBLIC(RO(Proc))->Service.Core)) == 0) { - struct cpufreq_governor *pGovernor = freqPolicy.governor; + struct cpufreq_governor *pGovernor = pFreqPolicy->governor; if (pGovernor != NULL) { StrCopy(PUBLIC(RO(Proc))->OS.FreqDriver.Governor, pGovernor->name, CPUFREQ_NAME_LEN); @@ -19322,11 +19934,15 @@ long Sys_OS_Driver_Query(void) } else { PUBLIC(RO(Proc))->OS.FreqDriver.Governor[0] = '\0'; } + kfree(pFreqPolicy); + } else { + rc = -ENOMEM; + } #endif /* CONFIG_CPU_FREQ */ return rc; } -long Sys_Kernel(SYSGATE_RO *SysGate) +static long Sys_Kernel(SYSGATE_RO *SysGate) { /* Sources: /include/generated/uapi/linux/version.h /include/uapi/linux/utsname.h */ if (SysGate != NULL) { @@ -19342,7 +19958,7 @@ long Sys_Kernel(SYSGATE_RO *SysGate) } } -long SysGate_OnDemand(void) +static long SysGate_OnDemand(void) { long rc = -1; if (PUBLIC(OF(Gate)) == NULL) @@ -20379,8 +20995,9 @@ static int CoreFreqK_Bios_Limit(int cpu, unsigned int *limit) return 0; } -void Policy_Aggregate_Turbo(void) +static void Policy_Aggregate_Turbo(void) { +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0) if (PUBLIC(RO(Proc))->Registration.Driver.CPUfreq & REGISTRATION_ENABLE) { CoreFreqK.FreqDriver.boost_enabled = ( BITWISEAND_CC( LOCKLESS, @@ -20388,8 +21005,10 @@ void Policy_Aggregate_Turbo(void) PUBLIC(RO(Proc))->TurboBoost_Mask ) != 0 ); } +#endif } +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0) #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 8, 0) \ || ((RHEL_MAJOR == 8) && (RHEL_MINOR > 3)) static int CoreFreqK_SetBoost(struct cpufreq_policy *policy, int state) @@ -20407,6 +21026,7 @@ static int CoreFreqK_SetBoost(int state) BITSET(BUS_LOCK, PUBLIC(RW(Proc))->OS.Signal, NTFY); /* Notify Daemon*/ return 0; } +#endif /* 3.14.0 */ static ssize_t CoreFreqK_Show_SetSpeed(struct cpufreq_policy *policy,char *buf) { @@ -20685,15 +21305,16 @@ static void Policy_Zen_CPPC_SetTarget(void *arg) if (((*ratio) >= Core->PowerThermal.HWP_Capabilities.Lowest) && ((*ratio) <= Core->PowerThermal.HWP_Capabilities.Highest)) { - HWCR HwCfgRegister = {.value = 0}; AMD_CPPC_REQUEST CPPC_Req = {.value = 0}; unsigned int hint; - RDMSR(HwCfgRegister, MSR_K7_HWCR); + RDMSR(Core->SystemRegister.HWCR, MSR_K7_HWCR); RDMSR(CPPC_Req, MSR_AMD_CPPC_REQ); - hint = CPPC_AMD_Zen_ScaleHint( Core, 255U, (*ratio), - !HwCfgRegister.Family_17h.CpbDis ); + hint = CPPC_AMD_Zen_ScaleHint( + Core, 255U, (*ratio), + !Core->SystemRegister.HWCR.Family_17h.CpbDis + ); if ((hint & (1 << 31)) != (1 << 31)) { @@ -20702,12 +21323,16 @@ static void Policy_Zen_CPPC_SetTarget(void *arg) RDMSR(CPPC_Req, MSR_AMD_CPPC_REQ); Core->PowerThermal.HWP_Request.Maximum_Perf = \ - CPPC_AMD_Zen_ScaleRatio(Core, 255U, CPPC_Req.Maximum_Perf, - !HwCfgRegister.Family_17h.CpbDis); + CPPC_AMD_Zen_ScaleRatio( + Core, 255U, CPPC_Req.Maximum_Perf, + !Core->SystemRegister.HWCR.Family_17h.CpbDis + ); Core->PowerThermal.HWP_Request.Desired_Perf = \ - CPPC_AMD_Zen_ScaleRatio(Core, 255U, CPPC_Req.Desired_Perf, - !HwCfgRegister.Family_17h.CpbDis); + CPPC_AMD_Zen_ScaleRatio( + Core, 255U, CPPC_Req.Desired_Perf, + !Core->SystemRegister.HWCR.Family_17h.CpbDis + ); Core->Boost[BOOST(HWP_MAX)]=Core->PowerThermal.HWP_Request.Maximum_Perf; Core->Boost[BOOST(HWP_TGT)]=Core->PowerThermal.HWP_Request.Desired_Perf; @@ -20725,7 +21350,8 @@ static int CoreFreqK_FreqDriver_UnInit(void) { int rc = -EINVAL; #ifdef CONFIG_CPU_FREQ -#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 3, 0)) && (!defined(CONFIG_CACHY)) +#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 3, 0)) && (!defined(CONFIG_CACHY)) \ + && (!defined(RHEL_MAJOR)) rc = #else rc = 0; @@ -20774,7 +21400,7 @@ static int CoreFreqK_Governor_Init(void) return rc; } -signed int Seek_Topology_Core_Peer(unsigned int cpu, signed int exclude) +static signed int Seek_Topology_Core_Peer(unsigned int cpu, signed int exclude) { unsigned int seek; @@ -20797,7 +21423,7 @@ signed int Seek_Topology_Core_Peer(unsigned int cpu, signed int exclude) return -1; } -signed int Seek_Topology_Thread_Peer(unsigned int cpu, signed int exclude) +static signed int Seek_Topology_Thread_Peer(unsigned int cpu,signed int exclude) { unsigned int seek; @@ -20820,7 +21446,7 @@ signed int Seek_Topology_Thread_Peer(unsigned int cpu, signed int exclude) return -1; } -signed int Seek_Topology_Hybrid_Core(unsigned int cpu) +static signed int Seek_Topology_Hybrid_Core(unsigned int cpu) { signed int any = (signed int) PUBLIC(RO(Proc))->CPU.Count, seek; @@ -20842,7 +21468,8 @@ signed int Seek_Topology_Hybrid_Core(unsigned int cpu) return any; } -void MatchCoreForService(SERVICE_PROC *pService,unsigned int cpi,signed int cpx) +static void MatchCoreForService(SERVICE_PROC *pService, + unsigned int cpi, signed int cpx) { unsigned int cpu; @@ -20859,7 +21486,8 @@ void MatchCoreForService(SERVICE_PROC *pService,unsigned int cpi,signed int cpx) } } -int MatchPeerForService(SERVICE_PROC *pService, unsigned int cpi,signed int cpx) +static int MatchPeerForService(SERVICE_PROC *pService, + unsigned int cpi, signed int cpx) { unsigned int cpu = cpi, cpn = 0; signed int seek; @@ -20889,7 +21517,7 @@ int MatchPeerForService(SERVICE_PROC *pService, unsigned int cpi,signed int cpx) return -1; } -void MatchPeerForDefaultService(SERVICE_PROC *pService, unsigned int cpu) +static void MatchPeerForDefaultService(SERVICE_PROC *pService, unsigned int cpu) { if (PUBLIC(RO(Proc))->Features.HTT_Enable) { if (MatchPeerForService(pService, cpu, -1) == -1) @@ -20911,7 +21539,7 @@ void MatchPeerForDefaultService(SERVICE_PROC *pService, unsigned int cpu) } } -void MatchPeerForUpService(SERVICE_PROC *pService, unsigned int cpu) +static void MatchPeerForUpService(SERVICE_PROC *pService, unsigned int cpu) { /* Try to restore the initial Service affinity or move to SMT peer. */ SERVICE_PROC hService = { .Core = cpu, @@ -20957,7 +21585,7 @@ void MatchPeerForUpService(SERVICE_PROC *pService, unsigned int cpu) } } -void MatchPeerForDownService(SERVICE_PROC *pService, unsigned int cpu) +static void MatchPeerForDownService(SERVICE_PROC *pService, unsigned int cpu) { int rc = -1; @@ -20970,6 +21598,7 @@ void MatchPeerForDownService(SERVICE_PROC *pService, unsigned int cpu) } #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0) +#ifdef CONFIG_HAVE_NMI static int CoreFreqK_NMI_Handler(unsigned int type, struct pt_regs *pRegs) { unsigned int cpu = smp_processor_id(); @@ -20991,6 +21620,7 @@ static int CoreFreqK_NMI_Handler(unsigned int type, struct pt_regs *pRegs) } return NMI_DONE; } +#endif /* CONFIG_HAVE_NMI */ static long CoreFreqK_UnRegister_CPU_Idle(void) { @@ -21119,6 +21749,7 @@ static long CoreFreqK_Register_Governor(void) static void CoreFreqK_Register_NMI(void) { +#ifdef CONFIG_HAVE_NMI if (BITVAL(PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_LOCAL) == 0) { if(register_nmi_handler(NMI_LOCAL, @@ -21167,10 +21798,12 @@ static void CoreFreqK_Register_NMI(void) BITCLR(LOCKLESS, PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_IO_CHECK); } } +#endif /* CONFIG_HAVE_NMI */ } static void CoreFreqK_UnRegister_NMI(void) { +#ifdef CONFIG_HAVE_NMI if (BITVAL(PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_LOCAL) == 1) { unregister_nmi_handler(NMI_LOCAL, "corefreqk"); @@ -21191,6 +21824,7 @@ static void CoreFreqK_UnRegister_NMI(void) unregister_nmi_handler(NMI_IO_CHECK, "corefreqk"); BITCLR(LOCKLESS, PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_IO_CHECK); } +#endif /* CONFIG_HAVE_NMI */ } #else static void CoreFreqK_Register_NMI(void) {} @@ -21525,6 +22159,32 @@ static long CoreFreqK_ioctl( struct file *filp, } break; + case TECHNOLOGY_L1_NPP_PREFETCH: + switch (prm.dl.lo) { + case COREFREQ_TOGGLE_OFF: + case COREFREQ_TOGGLE_ON: + Controller_Stop(1); + L1_NPP_PREFETCH_Disable = !prm.dl.lo; + Controller_Start(1); + L1_NPP_PREFETCH_Disable = -1; + rc = RC_SUCCESS; + break; + } + break; + + case TECHNOLOGY_L1_SCRUBBING: + switch (prm.dl.lo) { + case COREFREQ_TOGGLE_OFF: + case COREFREQ_TOGGLE_ON: + Controller_Stop(1); + L1_Scrubbing_Enable = prm.dl.lo; + Controller_Start(1); + L1_Scrubbing_Enable = -1; + rc = RC_SUCCESS; + break; + } + break; + case TECHNOLOGY_L2_HW_PREFETCH: switch (prm.dl.lo) { case COREFREQ_TOGGLE_OFF: @@ -21551,6 +22211,130 @@ static long CoreFreqK_ioctl( struct file *filp, } break; + case TECHNOLOGY_L2_AMP_PREFETCH: + switch (prm.dl.lo) { + case COREFREQ_TOGGLE_OFF: + case COREFREQ_TOGGLE_ON: + Controller_Stop(1); + L2_AMP_PREFETCH_Disable = !prm.dl.lo; + Controller_Start(1); + L2_AMP_PREFETCH_Disable = -1; + rc = RC_SUCCESS; + break; + } + break; + + case TECHNOLOGY_L2_NLP_PREFETCH: + switch (prm.dl.lo) { + case COREFREQ_TOGGLE_OFF: + case COREFREQ_TOGGLE_ON: + Controller_Stop(1); + L2_NLP_PREFETCH_Disable = !prm.dl.lo; + Controller_Start(1); + L2_NLP_PREFETCH_Disable = -1; + rc = RC_SUCCESS; + break; + } + break; + + case TECHNOLOGY_L1_STRIDE_PREFETCH: + if (PUBLIC(RO(Proc))->Features.ExtFeature2_EAX.PrefetchCtl_MSR) { + switch (prm.dl.lo) { + case COREFREQ_TOGGLE_OFF: + case COREFREQ_TOGGLE_ON: + Controller_Stop(1); + L1_STRIDE_PREFETCH_Disable = !prm.dl.lo; + Controller_Start(1); + L1_STRIDE_PREFETCH_Disable = -1; + rc = RC_SUCCESS; + break; + } + } else { + rc = -ENXIO; + } + break; + + case TECHNOLOGY_L1_REGION_PREFETCH: + if (PUBLIC(RO(Proc))->Features.ExtFeature2_EAX.PrefetchCtl_MSR) { + switch (prm.dl.lo) { + case COREFREQ_TOGGLE_OFF: + case COREFREQ_TOGGLE_ON: + Controller_Stop(1); + L1_REGION_PREFETCH_Disable = !prm.dl.lo; + Controller_Start(1); + L1_REGION_PREFETCH_Disable = -1; + rc = RC_SUCCESS; + break; + } + } else { + rc = -ENXIO; + } + break; + + case TECHNOLOGY_L1_BURST_PREFETCH: + if (PUBLIC(RO(Proc))->Features.ExtFeature2_EAX.PrefetchCtl_MSR) { + switch (prm.dl.lo) { + case COREFREQ_TOGGLE_OFF: + case COREFREQ_TOGGLE_ON: + Controller_Stop(1); + L1_BURST_PREFETCH_Disable = !prm.dl.lo; + Controller_Start(1); + L1_BURST_PREFETCH_Disable = -1; + rc = RC_SUCCESS; + break; + } + } else { + rc = -ENXIO; + } + break; + + case TECHNOLOGY_L2_STREAM_HW_PREFETCH: + if (PUBLIC(RO(Proc))->Features.ExtFeature2_EAX.PrefetchCtl_MSR) { + switch (prm.dl.lo) { + case COREFREQ_TOGGLE_OFF: + case COREFREQ_TOGGLE_ON: + Controller_Stop(1); + L2_STREAM_PREFETCH_Disable = !prm.dl.lo; + Controller_Start(1); + L2_STREAM_PREFETCH_Disable = -1; + rc = RC_SUCCESS; + break; + } + } else { + rc = -ENXIO; + } + break; + + case TECHNOLOGY_L2_UPDOWN_PREFETCH: + if (PUBLIC(RO(Proc))->Features.ExtFeature2_EAX.PrefetchCtl_MSR) { + switch (prm.dl.lo) { + case COREFREQ_TOGGLE_OFF: + case COREFREQ_TOGGLE_ON: + Controller_Stop(1); + L2_UPDOWN_PREFETCH_Disable = !prm.dl.lo; + Controller_Start(1); + L2_UPDOWN_PREFETCH_Disable = -1; + rc = RC_SUCCESS; + break; + } + } else { + rc = -ENXIO; + } + break; + + case TECHNOLOGY_LLC_STREAMER: + switch (prm.dl.lo) { + case COREFREQ_TOGGLE_OFF: + case COREFREQ_TOGGLE_ON: + Controller_Stop(1); + LLC_Streamer_Disable = !prm.dl.lo; + Controller_Start(1); + LLC_Streamer_Disable = -1; + rc = RC_SUCCESS; + break; + } + break; + case TECHNOLOGY_EIST: switch (prm.dl.lo) { case COREFREQ_TOGGLE_OFF: @@ -22151,7 +22935,11 @@ static long CoreFreqK_ioctl( struct file *filp, break; case EVENT_ALL_OF_THEM: Controller_Stop(1); + #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 17, 0) + Clear_Events = (unsigned long)(-1); + #else Clear_Events = (unsigned long long)(-1); + #endif Controller_Start(1); Clear_Events = 0; rc = RC_OK_COMPUTE; @@ -22335,7 +23123,7 @@ static struct file_operations CoreFreqK_fops = { }; #ifdef CONFIG_PM_SLEEP -void Print_SuspendResume(void) +inline void Print_SuspendResume(void) { pr_notice("CoreFreq: %s(%u:%d:%d)\n", CoreFreqK.ResumeFromSuspend ? "Suspend" : "Resume", @@ -22574,7 +23362,7 @@ static struct notifier_block CoreFreqK_notifier_block = { #endif /* KERNEL_VERSION(4, 10, 0) */ #endif /* CONFIG_HOTPLUG_CPU */ -void SMBIOS_Collect(void) +static void SMBIOS_Collect(void) { #ifdef CONFIG_DMI struct { @@ -22599,8 +23387,8 @@ void SMBIOS_Collect(void) { DMI_BOARD_VERSION, PUBLIC(RO(Proc))->SMB.Board.Version }, { DMI_BOARD_SERIAL, PUBLIC(RO(Proc))->SMB.Board.Serial } }; - size_t count = sizeof(dmi_collect) / sizeof(dmi_collect[0]), idx; - + const size_t count = sizeof(dmi_collect) / sizeof(dmi_collect[0]); + size_t idx; for (idx = 0; idx < count; idx++) { const char *pInfo = dmi_get_system_info(dmi_collect[idx].field); if ((pInfo != NULL) && (strlen(pInfo) > 0)) { @@ -22611,7 +23399,7 @@ void SMBIOS_Collect(void) } #ifdef CONFIG_DMI -char *SMBIOS_String(const struct dmi_header *dh, u8 id) +static char *SMBIOS_String(const struct dmi_header *dh, u8 id) { char *pStr = (char *) dh; pStr += dh->length; @@ -22628,7 +23416,7 @@ char *SMBIOS_String(const struct dmi_header *dh, u8 id) #define safe_strim(pStr) (strim(pStr == NULL ? "" : pStr)) -void SMBIOS_Entries(const struct dmi_header *dh, void *priv) +static void SMBIOS_Entries(const struct dmi_header *dh, void *priv) { size_t *count = (size_t*) priv; switch (dh->type) { @@ -22685,7 +23473,7 @@ void SMBIOS_Entries(const struct dmi_header *dh, void *priv) #undef safe_strim #endif /* CONFIG_DMI */ -void SMBIOS_Decoder(void) +inline void SMBIOS_Decoder(void) { #ifdef CONFIG_DMI size_t count = 0; @@ -22693,7 +23481,9 @@ void SMBIOS_Decoder(void) #endif /* CONFIG_DMI */ } -#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 2, 0) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 2, 0) \ + || ((RHEL_MAJOR == 8) && ((RHEL_MINOR < 3) || (RHEL_MINOR > 8))) \ + || ((RHEL_MAJOR == 9) && (RHEL_MINOR > 0)) static char *CoreFreqK_DevNode(const struct device *dev, umode_t *mode) #else static char *CoreFreqK_DevNode(struct device *dev, umode_t *mode) @@ -23110,12 +23900,13 @@ static int CoreFreqK_Alloc_Per_CPU_Level_Up(INIT_ARG *pArg) rc = -ENOMEM; break; } - + if (rc == 0) { BITCLR(LOCKLESS, PUBLIC(RW(Core, AT(cpu)))->Sync.V, NTFY); PUBLIC(RO(Core, AT(cpu)))->Bind = cpu; Define_CPUID(PUBLIC(RO(Core, AT(cpu))), CpuIDforVendor); + } } return rc; } @@ -23280,6 +24071,7 @@ static int CoreFreqK_Ignition_Level_Up(INIT_ARG *pArg) /* Initialize the CoreFreq controller */ Controller_Init(); + /* Seek for an appropriate service processor */ MatchPeerForDefaultService( &PUBLIC(RO(Proc))->Service, pArg->localProcessor ); diff --git a/corefreqk.h b/x86_64/corefreqk.h similarity index 92% rename from corefreqk.h rename to x86_64/corefreqk.h index 76e53646..2d2ac683 100644 --- a/corefreqk.h +++ b/x86_64/corefreqk.h @@ -1,6 +1,6 @@ /* * CoreFreq - * Copyright (C) 2015-2023 CYRIL COURTIAT + * Copyright (C) 2015-2024 CYRIL COURTIAT * Licenses: GPL2 */ @@ -433,7 +433,7 @@ ASM_COUNTERx4(r10, r11, r12, r13, r14, ASM_RDTSC, mem_tsc, __VA_ARGS__) ASM_COUNTERx4(r10, r11, r12, r13, r14, ASM_RDTSCP, mem_tsc, __VA_ARGS__) -#if defined(OPTIM_LVL) && OPTIM_LVL == 0 +#if defined(OPTIM_LVL) && (OPTIM_LVL == 0 || OPTIM_LVL == 1) #define RDTSC_COUNTERx5(mem_tsc, ...) \ ASM_COUNTERx5_STACK(r12, r13, r14, r15, ASM_RDTSC, mem_tsc, __VA_ARGS__) @@ -454,7 +454,7 @@ ASM_COUNTERx7_STACK(r13, r14, r15, ASM_RDTSC, mem_tsc, __VA_ARGS__) ASM_COUNTERx7_STACK(r13, r14, r15, ASM_RDTSCP, mem_tsc, __VA_ARGS__) #else -/* #warning "Optimization" */ +/* #warning "Optimization" */ #define RDTSC_COUNTERx5(mem_tsc, ...) \ ASM_COUNTERx5(r10, r11, r12, r13, r14, r15, ASM_RDTSC, mem_tsc, __VA_ARGS__) @@ -1145,7 +1145,7 @@ typedef struct /* Sources: - * Intel® 64 and IA-32 Architectures Software Developer’s Manual; Vol. 2A + * Intel 64 and IA-32 Architectures Software Developer’s Manual; Vol. 2A * AMD64 Architecture Programmer’s Manual; Vol. 3 */ @@ -1258,8 +1258,26 @@ static const CPUID_STRUCT CpuIDforVendor[CPUID_MAX_FUNC] = { = {.func = 0x0000001a, .sub = 0x00000000}, [CPUID_0000001B_00000000_PCONFIG_INFORMATION] = {.func = 0x0000001b, .sub = 0x00000000}, + [CPUID_0000001C_00000000_LAST_BRANCH_RECORDS] + = {.func = 0x0000001c, .sub = 0x00000000}, + [CPUID_0000001D_00000000_TILE_PALETTE_MAIN_LEAF] + = {.func = 0x0000001d, .sub = 0x00000000}, + [CPUID_0000001D_00000001_TILE_PALETTE_SUB_LEAF_1] + = {.func = 0x0000001d, .sub = 0x00000001}, + [CPUID_0000001E_00000000_TMUL_MAIN_LEAF] + = {.func = 0x0000001e, .sub = 0x00000000}, [CPUID_0000001F_00000000_EXT_TOPOLOGY_V2] = {.func = 0x0000001f, .sub = 0x00000000}, + [CPUID_00000020_00000000_PROCESSOR_HRESET] + = {.func = 0x00000020, .sub = 0x00000000}, + [CPUID_00000023_00000000_PM_EXT_MAIN_LEAF] + = {.func = 0x00000023, .sub = 0x00000000}, + [CPUID_00000023_00000001_PM_EXT_SUB_LEAF_1] + = {.func = 0x00000023, .sub = 0x00000001}, + [CPUID_00000023_00000002_PM_EXT_SUB_LEAF_2] + = {.func = 0x00000023, .sub = 0x00000002}, + [CPUID_00000023_00000003_PM_EXT_SUB_LEAF_3] + = {.func = 0x00000023, .sub = 0x00000003}, /* x86 */ [CPUID_80000001_00000000_EXTENDED_FEATURES] = {.func = 0x80000001, .sub = 0x00000000}, @@ -1526,6 +1544,7 @@ static void Query_Airmont(unsigned int cpu) ; static void PerCore_Airmont_Query(void *arg) ; static void PerCore_Geminilake_Query(void *arg) ; +static void PerCore_Tremont_Query(void *arg) ; static void Query_Nehalem(unsigned int cpu) ; static void PerCore_Nehalem_Query(void *arg) ; @@ -1629,6 +1648,10 @@ static void (*Power_ACCU_Skylake)(PROC_RO*,unsigned int)=Power_ACCU_SKL_DEFAULT; static void Query_Kaby_Lake(unsigned int cpu) ; static void PerCore_Kaby_Lake_Query(void *arg) ; +static void PerCore_Icelake_Query(void *arg) ; + +static void PerCore_Tigerlake_Query(void *arg) ; + static void Query_AMD_Family_0Fh(unsigned int cpu) ; static void PerCore_AMD_Family_0Fh_Query(void *arg) ; static void Start_AMD_Family_0Fh(void *arg) ; @@ -1709,7 +1732,9 @@ static void Query_Hygon_F18h(unsigned int cpu); #define Start_Uncore_AMD_Family_19h Start_Uncore_AMD_Family_17h #define Stop_Uncore_AMD_Family_19h Stop_Uncore_AMD_Family_17h +static void CCD_AMD_Family_19h_Genoa_Temp(CORE_RO *Core) ; static void CCD_AMD_Family_19h_Zen4_Temp(CORE_RO *Core) ; +static void Query_AMD_F19h_11h_PerCluster(unsigned int cpu) ; static void Query_AMD_F19h_61h_PerCluster(unsigned int cpu) ; static void InitTimer_AMD_Zen4_RPL(unsigned int cpu) ; @@ -1894,22 +1919,33 @@ static void InitTimer_AMD_Zen4_RPL(unsigned int cpu) ; #define _Alderlake_N {.ExtFamily=0x0, .Family=0x6, .ExtModel=0xB, .Model=0xE} /* [MeteorLake/M] 06_AAh - [MeteorLake/N] 06_B5h + [MeteorLake/N] 06_ABh [MeteorLake/S] 06_ACh [RaptorLake] 06_B7h [RaptorLake/P] 06_BAh [RaptorLake/S] 06_BFh */ #define _Meteorlake_M {.ExtFamily=0x0, .Family=0x6, .ExtModel=0xA, .Model=0xA} -#define _Meteorlake_N {.ExtFamily=0x0, .Family=0x6, .ExtModel=0xB, .Model=0x5} +#define _Meteorlake_N {.ExtFamily=0x0, .Family=0x6, .ExtModel=0xA, .Model=0xB} #define _Meteorlake_S {.ExtFamily=0x0, .Family=0x6, .ExtModel=0xA, .Model=0xC} #define _Raptorlake {.ExtFamily=0x0, .Family=0x6, .ExtModel=0xB, .Model=0x7} #define _Raptorlake_P {.ExtFamily=0x0, .Family=0x6, .ExtModel=0xB, .Model=0xA} #define _Raptorlake_S {.ExtFamily=0x0, .Family=0x6, .ExtModel=0xB, .Model=0xF} /* [LunarLake] 06_BDh - [ArrowLake] 06_C6h */ + [ArrowLake] 06_C6h + [ArrowLake/H] 06_C5h + [ArrowLake/U] 06_B5h */ #define _Lunarlake {.ExtFamily=0x0, .Family=0x6, .ExtModel=0xB, .Model=0xD} #define _Arrowlake {.ExtFamily=0x0, .Family=0x6, .ExtModel=0xC, .Model=0x6} +#define _Arrowlake_H {.ExtFamily=0x0, .Family=0x6, .ExtModel=0xC, .Model=0x5} +#define _Arrowlake_U {.ExtFamily=0x0, .Family=0x6, .ExtModel=0xB, .Model=0x5} + +/* [PantherLake] 06_CCh */ +#define _Pantherlake {.ExtFamily=0x0, .Family=0x6, .ExtModel=0xC, .Model=0xC} + +/* [Clearwater Forest] 06_DDh */ +#define _Clearwater_Forest \ + {.ExtFamily=0x0, .Family=0x6, .ExtModel=0xD, .Model=0xD} /* [Family 0Fh] 0F_00h */ #define _AMD_Family_0Fh {.ExtFamily=0x0, .Family=0xF, .ExtModel=0x0, .Model=0x0} @@ -1948,7 +1984,8 @@ static void InitTimer_AMD_Zen4_RPL(unsigned int cpu) ; [Zen2/Lucienne] 8F_68h Stepping 1 7 nm APU [Zen2/Matisse] 8F_71h Stepping 0 7 nm [Zen2/Xbox 8F_74h Stepping 0 7 nm - [Zen2/VanGogh] 8F_90h Stepping 1 7 nm Valve Jupiter + [Zen2/Van Gogh] 8F_90h Stepping 1 7 nm Valve Jupiter + [Zen2/Van Gogh] 8F_91h Stepping 0 6 nm Valve Galileo [Zen2/Mendocino] 8F_A0h Stepping 0 6 nm [MDN] */ #define _AMD_Zen {.ExtFamily=0x8, .Family=0xF, .ExtModel=0x0, .Model=0x1} #define _AMD_Zen_APU {.ExtFamily=0x8, .Family=0xF, .ExtModel=0x1, .Model=0x1} @@ -1966,6 +2003,9 @@ static void InitTimer_AMD_Zen4_RPL(unsigned int cpu) ; #define _AMD_Zen2_Jupiter \ {.ExtFamily=0x8, .Family=0xF, .ExtModel=0x9, .Model=0x0} +#define _AMD_Zen2_Galileo \ + {.ExtFamily=0x8, .Family=0xF, .ExtModel=0x9, .Model=0x1} + #define _AMD_Zen2_MDN {.ExtFamily=0x8, .Family=0xF, .ExtModel=0xA, .Model=0x0} #define _AMD_Family_17h {.ExtFamily=0x8, .Family=0xF, .ExtModel=0x0, .Model=0x0} @@ -2004,13 +2044,10 @@ static void InitTimer_AMD_Zen4_RPL(unsigned int cpu) ; [Zen4/Raphael] AF_61h Stepping 2 5 nm [RPL] [Zen4/Dragon Range] AF_61h Stepping 2 5 nm FL1 [Zen4/Phoenix Point] AF_74h 4 nm [PHX] - [Zen4c/Bergamo] AF_A0h Stepping 1 5 nm SVR */ -/* - [Zen4/Storm Peak] AF_18h Stepping 1 HEDT/TR5 - [Zen4/Genoa-X] ??_??h Stepping ? 5 nm - "AMD EPYC Embedded 9684X" .Boost = {+12, 0} - "AMD EPYC Embedded 9384X" .Boost = {+8, 0} - "AMD EPYC Embedded 9184X" .Boost = {+7, 0} + [Zen4/Hawk Point] AF_75h 4 nm [PHX] + [Zen4c/Phoenix2] AF_78h 4 nm [PHX2] + [Zen4c][Bergamo][Siena] AF_A0h Stepping [1][2] 5 nm SVR + [Zen4/Storm Peak] AF_18h Stepping 1 5 nm WS/SP6 [Zen5/Granite Ridge] */ #define _AMD_Family_19h {.ExtFamily=0xa, .Family=0xF, .ExtModel=0x0, .Model=0x0} #define _AMD_Zen3_VMR {.ExtFamily=0xa, .Family=0xF, .ExtModel=0x2, .Model=0x1} @@ -2026,9 +2063,13 @@ static void InitTimer_AMD_Zen4_RPL(unsigned int cpu) ; #define _AMD_Zen4_Genoa {.ExtFamily=0xa, .Family=0xF, .ExtModel=0x1, .Model=0x1} #define _AMD_Zen4_RPL {.ExtFamily=0xa, .Family=0xF, .ExtModel=0x6, .Model=0x1} #define _AMD_Zen4_PHX {.ExtFamily=0xa, .Family=0xF, .ExtModel=0x7, .Model=0x4} +#define _AMD_Zen4_HWK {.ExtFamily=0xa, .Family=0xF, .ExtModel=0x7, .Model=0x5} +#define _AMD_Zen4_PHX2 {.ExtFamily=0xa, .Family=0xF, .ExtModel=0x7, .Model=0x8} #define _AMD_Zen4_Bergamo \ {.ExtFamily=0xa, .Family=0xF, .ExtModel=0xa, .Model=0x0} +#define _AMD_Zen4_STP {.ExtFamily=0xa, .Family=0xF, .ExtModel=0x1, .Model=0x8} + typedef kernel_ulong_t (*PCI_CALLBACK)(struct pci_dev *); static PCI_CALLBACK P945(struct pci_dev *dev) ; @@ -2100,11 +2141,13 @@ static PCI_CALLBACK AMD_DataFabric_Ariel(struct pci_dev *pdev) ; static PCI_CALLBACK AMD_DataFabric_Raven2(struct pci_dev *pdev) ; static PCI_CALLBACK AMD_DataFabric_Fireflight(struct pci_dev *pdev) ; static PCI_CALLBACK AMD_DataFabric_Arden(struct pci_dev *pdev) ; +static PCI_CALLBACK AMD_DataFabric_VanGogh(struct pci_dev *pdev) ; static PCI_CALLBACK AMD_DataFabric_Vermeer(struct pci_dev *pdev) ; static PCI_CALLBACK AMD_DataFabric_Cezanne(struct pci_dev *pdev) ; static PCI_CALLBACK AMD_DataFabric_Rembrandt(struct pci_dev *pdev) ; static PCI_CALLBACK AMD_DataFabric_Raphael(struct pci_dev *pdev) ; static PCI_CALLBACK AMD_DataFabric_Genoa(struct pci_dev *pdev) ; +static PCI_CALLBACK AMD_DataFabric_Phoenix(struct pci_dev *pdev) ; static struct pci_device_id PCI_Void_ids[] = { {0, } @@ -3066,6 +3109,10 @@ static struct pci_device_id PCI_AMD_17h_ids[] = { PCI_VDEVICE(AMD, DID_AMD_17H_ARDEN_NB_IOMMU), .driver_data = (kernel_ulong_t) AMD_Zen_IOMMU }, + { + PCI_VDEVICE(AMD, DID_AMD_17H_JUPITER_NB_IOMMU), + .driver_data = (kernel_ulong_t) AMD_Zen_IOMMU + }, { PCI_VDEVICE(AMD, DID_AMD_19H_ZEN3_RMB_NB_IOMMU), .driver_data = (kernel_ulong_t) AMD_Zen_IOMMU @@ -3078,6 +3125,10 @@ static struct pci_device_id PCI_AMD_17h_ids[] = { PCI_VDEVICE(AMD, DID_AMD_19H_ZEN4_GNA_NB_IOMMU), .driver_data = (kernel_ulong_t) AMD_Zen_IOMMU }, + { + PCI_VDEVICE(AMD, DID_AMD_19H_ZEN4_PHX_NB_IOMMU), + .driver_data = (kernel_ulong_t) AMD_Zen_IOMMU + }, /* Source: HYGON: PCI list */ { PCI_VDEVICE(HYGON, DID_AMD_17H_ZEN_PLUS_NB_IOMMU), @@ -3120,6 +3171,10 @@ static struct pci_device_id PCI_AMD_17h_ids[] = { PCI_VDEVICE(AMD, DID_AMD_17H_ARDEN_DF_UMC), .driver_data = (kernel_ulong_t) AMD_DataFabric_Arden }, + { + PCI_VDEVICE(AMD, DID_AMD_17H_JUPITER_DF_UMC), + .driver_data = (kernel_ulong_t) AMD_DataFabric_VanGogh + }, /* AMD Family 19h */ /* Source: SMU > Data Fabric > UMC */ { @@ -3142,6 +3197,10 @@ static struct pci_device_id PCI_AMD_17h_ids[] = { PCI_VDEVICE(AMD, DID_AMD_19H_GENOA_DF_UMC), .driver_data = (kernel_ulong_t) AMD_DataFabric_Genoa }, + { + PCI_VDEVICE(AMD, DID_AMD_19H_PHOENIX_DF_UMC), + .driver_data = (kernel_ulong_t) AMD_DataFabric_Phoenix + }, {0, } }; @@ -3372,6 +3431,11 @@ static char *Arch_Tigerlake_U[] = ZLIST("Tiger Lake/U"); static char *Arch_Cometlake[] = ZLIST("Comet Lake"); static char *Arch_Cometlake_UY[] = ZLIST("Comet Lake/UY"); +enum { + CN_ALDERLAKE_H, + CN_ARIZONA_BEACH +}; + static char *Arch_Atom_Denverton[] = ZLIST("Atom/Denverton"); static char *Arch_Tremont_Jacobsville[] = ZLIST("Tremont/Jacobsville"); @@ -3388,7 +3452,10 @@ static char *Arch_Grand_Ridge[] = ZLIST("Grand Ridge"); static char *Arch_Rocketlake[] = ZLIST("Rocket Lake"); static char *Arch_Rocketlake_U[] = ZLIST("Rocket Lake/U"); static char *Arch_Alderlake_S[] = ZLIST("Alder Lake"); -static char *Arch_Alderlake_H[] = ZLIST("Alder Lake/H"); +static char *Arch_Alderlake_H[] = ZLIST( + [CN_ALDERLAKE_H] = "Alder Lake/H", + [CN_ARIZONA_BEACH] = "Arizona Beach" +); static char *Arch_Alderlake_N[] = ZLIST("Alder Lake/N"); static char *Arch_Meteorlake_M[] = ZLIST("Meteor Lake/M"); static char *Arch_Meteorlake_N[] = ZLIST("Meteor Lake/N"); @@ -3398,6 +3465,11 @@ static char *Arch_Raptorlake_P[] = ZLIST("Raptor Lake/P"); static char *Arch_Raptorlake_S[] = ZLIST("Raptor Lake/S"); static char *Arch_Lunarlake[] = ZLIST("Lunar Lake"); static char *Arch_Arrowlake[] = ZLIST("Arrow Lake"); +static char *Arch_Arrowlake_H[] = ZLIST("Arrow Lake/H"); +static char *Arch_Arrowlake_U[] = ZLIST("Arrow Lake/U"); +static char *Arch_Pantherlake[] = ZLIST("Panther Lake"); + +static char *Arch_Clearwater_Forest[] = ZLIST("Panther Lake"); enum { CN_BULLDOZER, @@ -3481,7 +3553,8 @@ enum { CN_REMBRANDT_R }; enum { - CN_GENOA + CN_GENOA, + CN_GENOA_X }; enum { CN_RAPHAEL, @@ -3490,6 +3563,12 @@ enum { enum { CN_PHOENIX }; +enum { + CN_PHOENIX_R +}; +enum { + CN_PHOENIX2 +}; enum { CN_DHYANA, @@ -3498,7 +3577,12 @@ enum { }; enum { - CN_BERGAMO + CN_BERGAMO, + CN_SIENA +}; + +enum { + CN_STORM_PEAK }; static char *Arch_AMD_Zen[] = ZLIST( @@ -3541,7 +3625,10 @@ static char *Arch_AMD_Zen2_MTS[] = ZLIST( static char *Arch_AMD_Zen2_Ariel[] = ZLIST("Zen2/Ariel"); static char *Arch_AMD_Zen2_Jupiter[] = ZLIST( - [CN_VANGOGH] = "Zen2/VanGogh" + [CN_VANGOGH] = "Zen2/Van Gogh/Aerith" +); +static char *Arch_AMD_Zen2_Galileo[] = ZLIST( + [CN_VANGOGH] = "Zen2/Van Gogh/Sephiroth" ); static char *Arch_AMD_Zen2_MDN[] = ZLIST( [CN_MENDOCINO] = "Zen2/Mendocino" @@ -3567,7 +3654,8 @@ static char *Arch_AMD_Zen3Plus_RMB[] = ZLIST( [CN_REMBRANDT_R] = "Zen3+ Rembrandt-R" ); static char *Arch_AMD_Zen4_Genoa[] = ZLIST( - [CN_GENOA] = "EPYC/Genoa" + [CN_GENOA] = "EPYC/Genoa", + [CN_GENOA_X] = "EPYC/Genoa-X" ); static char *Arch_AMD_Zen4_RPL[] = ZLIST( [CN_RAPHAEL] = "Zen4/Raphael", @@ -3576,8 +3664,18 @@ static char *Arch_AMD_Zen4_RPL[] = ZLIST( static char *Arch_AMD_Zen4_PHX[] = ZLIST( [CN_PHOENIX] = "Zen4/Phoenix Point" ); +static char *Arch_AMD_Zen4_HWK[] = ZLIST( + [CN_PHOENIX_R] = "Zen4/Hawk Point" +); +static char *Arch_AMD_Zen4_PHX2[] = ZLIST( + [CN_PHOENIX2] = "Zen4/Phoenix2" +); static char *Arch_AMD_Zen4_Bergamo[] = ZLIST( - [CN_BERGAMO] = "Zen4c/Bergamo" + [CN_BERGAMO] = "Zen4c/Bergamo", + [CN_SIENA] = "Zen4c/Siena" +); +static char *Arch_AMD_Zen4_STP[] = ZLIST( + [CN_STORM_PEAK] = "Zen4/Storm Peak" ); static char *Arch_AMD_Family_17h[] = ZLIST("AMD Zen"); @@ -4440,6 +4538,23 @@ static PROCESSOR_SPECIFIC Kabylake_UY_Specific[] = { {0} }; +static PROCESSOR_SPECIFIC Alderlake_H_Specific[] = { + { /* 06_9A Stepping 4 */ + .Brand = ZLIST( "Intel(R) Atom C1130", \ + "Intel(R) Atom C1110", \ + "Intel(R) Atom C1100" ), + .Boost = {0, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_ARIZONA_BEACH, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b00, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_UNCORE_UNLOCK|LATCH_TURBO_UNLOCK + }, + {0} +}; + /* AMD Family 17h Remarks:Thermal Offset taken from Linux/k10temp.c +0.5 XFR is rounded to +1 multiplier bin @@ -6003,6 +6118,17 @@ static PROCESSOR_SPECIFIC AMD_Zen2_Renoir_Specific[] = { .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK }, { + .Brand = ZLIST("AMD Ryzen 5 4500"), + .Boost = {+5, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_RENOIR, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 1, + .UncoreUnlocked = 0, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK + }, + { .Brand = ZLIST("AMD Ryzen 5 PRO 4650GE"), .Boost = {+9, 0}, .Param.Offset = {0, 0, 0}, @@ -6388,9 +6514,10 @@ static PROCESSOR_SPECIFIC AMD_Zen2_MTS_Specific[] = { {0} }; static PROCESSOR_SPECIFIC AMD_Zen2_Jupiter_Specific[] = { -/* [Zen2/VanGogh] Valve Jupiter */ +/* [Zen2/Van Gogh] 7 nm Valve Jupiter. 6 nm Sephiroth */ { - .Brand = ZLIST("AMD Custom APU 0405"), + .Brand = ZLIST( "AMD Custom APU 0405", \ + "AMD Custom APU 0932" ), .Boost = {+7, 0}, .Param.Offset = {0, 0, 0}, .CodeNameIdx = CN_VANGOGH, @@ -6611,7 +6738,8 @@ static PROCESSOR_SPECIFIC AMD_Zen3_VMR_Specific[] = { }; static PROCESSOR_SPECIFIC AMD_Zen3_CZN_Specific[] = { { - .Brand = ZLIST("AMD Ryzen 3 PRO 5350GE"), + .Brand = ZLIST( "AMD Ryzen 3 PRO 5350GE", \ + "AMD Ryzen 3 PRO 5355GE" ), .Boost = {+6, 0}, .Param.Offset = {0, 0, 0}, .CodeNameIdx = CN_CEZANNE, @@ -6622,7 +6750,8 @@ static PROCESSOR_SPECIFIC AMD_Zen3_CZN_Specific[] = { .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK }, { - .Brand = ZLIST("AMD Ryzen 3 PRO 5350G"), + .Brand = ZLIST( "AMD Ryzen 3 PRO 5350G", \ + "AMD Ryzen 3 PRO 5355G" ), .Boost = {+2, 0}, .Param.Offset = {0, 0, 0}, .CodeNameIdx = CN_CEZANNE, @@ -6655,7 +6784,8 @@ static PROCESSOR_SPECIFIC AMD_Zen3_CZN_Specific[] = { .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK }, { - .Brand = ZLIST("AMD Ryzen 5 PRO 5650GE"), + .Brand = ZLIST( "AMD Ryzen 5 PRO 5650GE", \ + "AMD Ryzen 5 PRO 5655GE" ), .Boost = {+10, 0}, .Param.Offset = {0, 0, 0}, .CodeNameIdx = CN_CEZANNE, @@ -6666,7 +6796,8 @@ static PROCESSOR_SPECIFIC AMD_Zen3_CZN_Specific[] = { .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK }, { - .Brand = ZLIST("AMD Ryzen 5 PRO 5650G"), + .Brand = ZLIST( "AMD Ryzen 5 PRO 5650G", \ + "AMD Ryzen 5 PRO 5655G" ), .Boost = {+5, 0}, .Param.Offset = {0, 0, 0}, .CodeNameIdx = CN_CEZANNE, @@ -6677,7 +6808,8 @@ static PROCESSOR_SPECIFIC AMD_Zen3_CZN_Specific[] = { .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK }, { - .Brand = ZLIST("AMD Ryzen 5 5600GE"), + .Brand = ZLIST( "AMD Ryzen 5 5600GE", \ + "AMD Ryzen 5 5600GT" ), .Boost = {+10, +1}, .Param.Offset = {0, 0, 0}, .CodeNameIdx = CN_CEZANNE, @@ -6754,7 +6886,9 @@ static PROCESSOR_SPECIFIC AMD_Zen3_CZN_Specific[] = { .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK }, { - .Brand = ZLIST("AMD Ryzen 7 5700G"), + .Brand = ZLIST( "AMD Ryzen 7 5700G" \ + "AMD Ryzen 7 5700", \ + "AMD Ryzen 5 5500GT" ), .Boost = {+8, +1}, .Param.Offset = {0, 0, 0}, .CodeNameIdx = CN_CEZANNE, @@ -6777,7 +6911,19 @@ static PROCESSOR_SPECIFIC AMD_Zen3_CZN_Specific[] = { .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK }, { - .Brand = ZLIST( "AMD Ryzen 3 5425U", \ + .Brand = ZLIST("AMD Ryzen 3 5125C"), + .Boost = {+0, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_BARCELO, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK + }, + { + .Brand = ZLIST( "AMD Ryzen 3 5425C", \ + "AMD Ryzen 3 5425U", \ "AMD Ryzen 3 PRO 5475U" ), .Boost = {+14, 0}, .Param.Offset = {0, 0, 0}, @@ -6789,6 +6935,29 @@ static PROCESSOR_SPECIFIC AMD_Zen3_CZN_Specific[] = { .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK }, { + .Brand = ZLIST("AMD Ryzen 5 5600HS"), + .Boost = {+12, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_CEZANNE, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK + }, + { + .Brand = ZLIST( "AMD Ryzen 5 5500H" \ + "AMD Ryzen 5 5600H" ), + .Boost = {+9, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_CEZANNE, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK + }, + { .Brand = ZLIST("AMD Ryzen 5 5600U"), .Boost = {+19, 0}, .Param.Offset = {0, 0, 0}, @@ -6800,7 +6969,19 @@ static PROCESSOR_SPECIFIC AMD_Zen3_CZN_Specific[] = { .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK }, { - .Brand = ZLIST( "AMD Ryzen 5 5625U", \ + .Brand = ZLIST("AMD Ryzen 5 5560U"), + .Boost = {+17, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_CEZANNE, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK + }, + { + .Brand = ZLIST( "AMD Ryzen 5 5625C", \ + "AMD Ryzen 5 5625U", \ "AMD Ryzen 5 PRO 5675U" ), .Boost = {+20, 0}, .Param.Offset = {0, 0, 0}, @@ -6847,7 +7028,8 @@ static PROCESSOR_SPECIFIC AMD_Zen3_CZN_Specific[] = { .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK }, { - .Brand = ZLIST( "AMD Ryzen 7 5825U", \ + .Brand = ZLIST( "AMD Ryzen 7 5825C", \ + "AMD Ryzen 7 5825U", \ "AMD Ryzen 7 PRO 5875U" ), .Boost = {+25, 0}, .Param.Offset = {0, 0, 0}, @@ -6906,7 +7088,8 @@ static PROCESSOR_SPECIFIC AMD_Zen3_CZN_Specific[] = { .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK }, { - .Brand = ZLIST( "AMD Ryzen 3 7330U", \ + .Brand = ZLIST( "AMD Ryzen 5 7430U", \ + "AMD Ryzen 3 7330U", \ "AMD Ryzen 3 PRO 7330U" ), .Boost = {+20, 0}, .Param.Offset = {0, 0, 0}, @@ -6952,7 +7135,8 @@ static PROCESSOR_SPECIFIC AMD_EPYC_Milan_Specific[] = { |LATCH_HSMP_CAPABLE }, { - .Brand = ZLIST("AMD EPYC 7663"), + .Brand = ZLIST( "AMD EPYC 7663P", \ + "AMD EPYC 7663" ), .Boost = {+15, 0}, .Param.Offset = {0, 0, 0}, .CodeNameIdx = CN_MILAN, @@ -6967,6 +7151,7 @@ static PROCESSOR_SPECIFIC AMD_EPYC_Milan_Specific[] = { { .Brand = ZLIST( "AMD EPYC Embedded 7643", \ "AMD EPYC 7773X", \ + "AMD EPYC 7643P", \ "AMD EPYC 7643" ), .Boost = {+13, 0}, .Param.Offset = {0, 0, 0}, @@ -6983,7 +7168,8 @@ static PROCESSOR_SPECIFIC AMD_EPYC_Milan_Specific[] = { .Brand = ZLIST( "AMD EPYC Embedded 7543P", \ "AMD EPYC Embedded 7543", \ "AMD EPYC 7543P", \ - "AMD EPYC 7543" ), + "AMD EPYC 7543", \ + "AMD EPYC 7473X" ), .Boost = {+9, 0}, .Param.Offset = {0, 0, 0}, .CodeNameIdx = CN_MILAN, @@ -6996,7 +7182,9 @@ static PROCESSOR_SPECIFIC AMD_EPYC_Milan_Specific[] = { |LATCH_HSMP_CAPABLE }, { - .Brand = ZLIST("AMD EPYC 74F3"), + .Brand = ZLIST( "AMD EPYC 7573X", \ + "AMD EPYC 7373X", \ + "AMD EPYC 74F3" ), .Boost = {+8, 0}, .Param.Offset = {0, 0, 0}, .CodeNameIdx = CN_MILAN, @@ -7044,7 +7232,9 @@ static PROCESSOR_SPECIFIC AMD_EPYC_Milan_Specific[] = { }, { .Brand = ZLIST( "AMD EPYC Embedded 7413", \ - "AMD EPYC 7413" ), + "AMD EPYC 7413", \ + "AMD EPYC 7303P", \ + "AMD EPYC 7303" ), .Boost = {+10, 0}, .Param.Offset = {0, 0, 0}, .CodeNameIdx = CN_MILAN, @@ -7082,6 +7272,20 @@ static PROCESSOR_SPECIFIC AMD_EPYC_Milan_Specific[] = { .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ |LATCH_HSMP_CAPABLE }, + { + .Brand = ZLIST( "AMD EPYC 7203P", \ + "AMD EPYC 7203" ), + .Boost = {+6, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_MILAN, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .HSMP_Capable = 1, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ + |LATCH_HSMP_CAPABLE + }, {0} }; static PROCESSOR_SPECIFIC AMD_Zen3Plus_RMB_Specific[] = { @@ -7184,7 +7388,8 @@ static PROCESSOR_SPECIFIC AMD_Zen3Plus_RMB_Specific[] = { { .Brand = ZLIST( "AMD Ryzen 3 7335U", \ "AMD Ryzen 5 7535HS", \ - "AMD Ryzen 5 7535H" ), + "AMD Ryzen 5 7535H", \ + "AMD Ryzen 3 PRO 7335U" ), .Boost = {+13, 0}, .Param.Offset = {0, 0, 0}, .CodeNameIdx = CN_REMBRANDT_R, @@ -7196,7 +7401,21 @@ static PROCESSOR_SPECIFIC AMD_Zen3Plus_RMB_Specific[] = { .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK }, { - .Brand = ZLIST("AMD Ryzen 5 7535U"), + .Brand = ZLIST( "AMD Ryzen 5 7235HS", \ + "AMD Ryzen 5 7235H" ), /* zh-cn */ + .Boost = {+10, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_REMBRANDT_R, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .HSMP_Capable = 0, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK + }, + { + .Brand = ZLIST( "AMD Ryzen 5 7535U", \ + "AMD Ryzen 5 PRO 7535U" ), .Boost = {+17, 0}, .Param.Offset = {0, 0, 0}, .CodeNameIdx = CN_REMBRANDT_R, @@ -7208,6 +7427,19 @@ static PROCESSOR_SPECIFIC AMD_Zen3Plus_RMB_Specific[] = { .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK }, { + .Brand = ZLIST( "AMD Ryzen 7 7435HS", \ + "AMD Ryzen 7 7435H" ), /* zh-cn */ + .Boost = {+14, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_REMBRANDT_R, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .HSMP_Capable = 0, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK + }, + { .Brand = ZLIST( "AMD Ryzen 7 7735HS", \ "AMD Ryzen 7 7735H" ), .Boost = {+16, 0}, @@ -7233,7 +7465,8 @@ static PROCESSOR_SPECIFIC AMD_Zen3Plus_RMB_Specific[] = { .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK }, { - .Brand = ZLIST("AMD Ryzen 7 7736U"), + .Brand = ZLIST( "AMD Ryzen 7 7736U", \ + "AMD Ryzen 7 PRO 7735U" ), .Boost = {+20, 0}, .Param.Offset = {0, 0, 0}, .CodeNameIdx = CN_REMBRANDT_R, @@ -7500,11 +7733,52 @@ static PROCESSOR_SPECIFIC AMD_Zen4_Genoa_Specific[] = { .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ |LATCH_HSMP_CAPABLE }, + /* EPYC Genoa-X Family with 3D V-Cache Technology */ + { + .Brand = ZLIST("AMD EPYC 9684X"), + .Boost = {+12, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_GENOA_X, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .HSMP_Capable = 1, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ + |LATCH_HSMP_CAPABLE + }, + { + .Brand = ZLIST("AMD EPYC 9384X"), + .Boost = {+8, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_GENOA_X, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .HSMP_Capable = 1, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ + |LATCH_HSMP_CAPABLE + }, + { + .Brand = ZLIST("AMD EPYC 9184X"), + .Boost = {+7, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_GENOA_X, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .HSMP_Capable = 1, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ + |LATCH_HSMP_CAPABLE + }, {0} }; static PROCESSOR_SPECIFIC AMD_Zen4_RPL_Specific[] = { { - .Brand = ZLIST("AMD Ryzen 9 PRO 7945"), + .Brand = ZLIST( "AMD Ryzen 9 PRO 7945", \ + "AMD Ryzen Embedded 7945" ), .Boost = {+17, 0}, .Param.Offset = {0, 0, 0}, .CodeNameIdx = CN_RAPHAEL, @@ -7517,7 +7791,8 @@ static PROCESSOR_SPECIFIC AMD_Zen4_RPL_Specific[] = { |LATCH_HSMP_CAPABLE }, { - .Brand = ZLIST("AMD Ryzen 7 PRO 7745"), + .Brand = ZLIST( "AMD Ryzen 7 PRO 7745", \ + "AMD Ryzen Embedded 7745" ), .Boost = {+15, 0}, .Param.Offset = {0, 0, 0}, .CodeNameIdx = CN_RAPHAEL, @@ -7530,7 +7805,8 @@ static PROCESSOR_SPECIFIC AMD_Zen4_RPL_Specific[] = { |LATCH_HSMP_CAPABLE }, { - .Brand = ZLIST("AMD Ryzen 5 PRO 7645"), + .Brand = ZLIST( "AMD Ryzen 5 PRO 7645", \ + "AMD Ryzen Embedded 7645" ), .Boost = {+13, 0}, .Param.Offset = {0, 0, 0}, .CodeNameIdx = CN_RAPHAEL, @@ -7595,8 +7871,9 @@ static PROCESSOR_SPECIFIC AMD_Zen4_RPL_Specific[] = { |LATCH_HSMP_CAPABLE }, { - .Brand = ZLIST( "AMD Ryzen 9 7900X", \ - "AMD Ryzen 7 7700X" ), + .Brand = ZLIST( "AMD Ryzen 9 7900X", \ + "AMD Ryzen 7 7700X", \ + "AMD Ryzen Embedded 7700X" ), .Boost = {+9, +1}, .Param.Offset = {0, 0, 0}, .CodeNameIdx = CN_RAPHAEL, @@ -7609,7 +7886,8 @@ static PROCESSOR_SPECIFIC AMD_Zen4_RPL_Specific[] = { |LATCH_HSMP_CAPABLE }, { - .Brand = ZLIST("AMD Ryzen 5 7600X"), + .Brand = ZLIST( "AMD Ryzen 5 7600X", \ + "AMD Ryzen Embedded 7600X" ), .Boost = {+6, +1}, .Param.Offset = {0, 0, 0}, .CodeNameIdx = CN_RAPHAEL, @@ -7648,7 +7926,8 @@ static PROCESSOR_SPECIFIC AMD_Zen4_RPL_Specific[] = { |LATCH_HSMP_CAPABLE }, { - .Brand = ZLIST("AMD Ryzen 5 7600"), + .Brand = ZLIST( "AMD Ryzen 5 7600", \ + "AMD Ryzen 5 7500F" ), .Boost = {+12, +1}, .Param.Offset = {0, 0, 0}, .CodeNameIdx = CN_RAPHAEL, @@ -7661,6 +7940,18 @@ static PROCESSOR_SPECIFIC AMD_Zen4_RPL_Specific[] = { |LATCH_HSMP_CAPABLE }, { + .Brand = ZLIST("AMD Ryzen 9 7945HX3D"), + .Boost = {+31, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_DRAGON_RANGE, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .HSMP_Capable = 0, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK + }, + { .Brand = ZLIST("AMD Ryzen 9 7945HX"), .Boost = {+29, +1}, .Param.Offset = {0, 0, 0}, @@ -7673,7 +7964,20 @@ static PROCESSOR_SPECIFIC AMD_Zen4_RPL_Specific[] = { .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK }, { - .Brand = ZLIST("AMD Ryzen 9 7845HX"), + .Brand = ZLIST("AMD Ryzen 9 7940HX"), + .Boost = {+28, +1}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_DRAGON_RANGE, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 1, + .UncoreUnlocked = 0, + .HSMP_Capable = 0, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK + }, + { + .Brand = ZLIST( "AMD Ryzen 9 7845HX", \ + "AMD Ryzen 9 7840HX" ), .Boost = {+22, +1}, .Param.Offset = {0, 0, 0}, .CodeNameIdx = CN_DRAGON_RANGE, @@ -7796,93 +8100,407 @@ static PROCESSOR_SPECIFIC AMD_Zen4_PHX_Specific[] = { }, {0} }; -static PROCESSOR_SPECIFIC AMD_Zen4_Bergamo_Specific[] = { +static PROCESSOR_SPECIFIC AMD_Zen4_HWK_Specific[] = { { - .Brand = ZLIST( "AMD EPYC Embedded 9754S", \ - "AMD EPYC Embedded 9754" ), - .Boost = {+9, 0}, + .Brand = ZLIST( "AMD Ryzen 9 8945HS", \ + "AMD Ryzen 9 8945H", /* zh-cn */\ + "AMD Ryzen 9 8940H" ), + .Boost = {+12, 0}, .Param.Offset = {0, 0, 0}, - .CodeNameIdx = CN_BERGAMO, + .CodeNameIdx = CN_PHOENIX_R, .TgtRatioUnlocked = 1, .ClkRatioUnlocked = 0b10, .TurboUnlocked = 0, .UncoreUnlocked = 0, - .HSMP_Capable = 1, - .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ - |LATCH_HSMP_CAPABLE + .HSMP_Capable = 0, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK }, { - .Brand = ZLIST("AMD EPYC Embedded 9734"), - .Boost = {+8, 0}, + .Brand = ZLIST( "AMD Ryzen 7 8845HS", \ + "AMD Ryzen 7 8845H", /* zh-cn */\ + "AMD Ryzen Embedded 8845HS" ), + .Boost = {+13, 0}, .Param.Offset = {0, 0, 0}, - .CodeNameIdx = CN_BERGAMO, + .CodeNameIdx = CN_PHOENIX_R, .TgtRatioUnlocked = 1, .ClkRatioUnlocked = 0b10, .TurboUnlocked = 0, .UncoreUnlocked = 0, - .HSMP_Capable = 1, - .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ - |LATCH_HSMP_CAPABLE + .HSMP_Capable = 0, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK }, - {0} -}; - -static PROCESSOR_SPECIFIC Misc_Specific_Processor[] = { - {0} -}; - -#ifdef CONFIG_CPU_FREQ -#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 19) -#define CPUFREQ_POLICY_UNKNOWN (0) -#endif -static int CoreFreqK_Policy_Exit(struct cpufreq_policy*) ; -static int CoreFreqK_Policy_Init(struct cpufreq_policy*) ; -#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 19)) \ - && (LINUX_VERSION_CODE <= KERNEL_VERSION(5, 5, 0))) \ - || (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 5, 3)) \ - || (RHEL_MAJOR == 8) -static int CoreFreqK_Policy_Verify(struct cpufreq_policy_data*) ; -#else -static int CoreFreqK_Policy_Verify(struct cpufreq_policy*) ; -#endif -static int CoreFreqK_SetPolicy(struct cpufreq_policy*) ; -static int CoreFreqK_Bios_Limit(int, unsigned int*) ; -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 8, 0) \ - || ((RHEL_MAJOR == 8) && (RHEL_MINOR > 3)) -static int CoreFreqK_SetBoost(struct cpufreq_policy*, int) ; -#else -static int CoreFreqK_SetBoost(int) ; -#endif -static ssize_t CoreFreqK_Show_SetSpeed(struct cpufreq_policy*, char*); -static int CoreFreqK_Store_SetSpeed(struct cpufreq_policy*, unsigned int) ; -#endif /* CONFIG_CPU_FREQ */ - -static unsigned int Policy_GetFreq(unsigned int cpu) ; -static void Policy_Core2_SetTarget(void *arg) ; -static void Policy_Nehalem_SetTarget(void *arg) ; -static void Policy_SandyBridge_SetTarget(void *arg) ; -static void Policy_HWP_SetTarget(void *arg) ; -#define Policy_Broadwell_EP_SetTarget Policy_SandyBridge_SetTarget -static void Policy_Skylake_SetTarget(void *arg) ; -static void Policy_Zen_SetTarget(void *arg) ; -static void Policy_Zen_CPPC_SetTarget(void *arg) ; - -#define VOID_Driver { \ - .IdleState = NULL , \ - .GetFreq = NULL , \ - .SetTarget = NULL \ -} - -#define CORE2_Driver { \ - .IdleState = NULL , \ - .GetFreq = Policy_GetFreq, \ - .SetTarget = Policy_Core2_SetTarget \ -} - -static IDLE_STATE SLM_IdleState[] = { { - .Name = "C1", - .Desc = "SLM-C1", + .Brand = ZLIST( "AMD Ryzen 7 8840HS", \ + "AMD Ryzen 7 8840H", /* zh-cn */\ + "AMD Ryzen 7 8840U", \ + "AMD Ryzen Embedded 8840U" ), + .Boost = {+18, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_PHOENIX_R, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .HSMP_Capable = 0, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK + }, + { + .Brand = ZLIST( "AMD Ryzen 5 8645HS", \ + "AMD Ryzen 5 8645H", /* zh-cn */\ + "AMD Ryzen Embedded 8645HS" ), + .Boost = {+7, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_PHOENIX_R, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .HSMP_Capable = 0, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK + }, + { + .Brand = ZLIST( "AMD Ryzen 5 8640HS", \ + "AMD Ryzen 5 8640U", \ + "AMD Ryzen Embedded 8640U" ), + .Boost = {+14, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_PHOENIX_R, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .HSMP_Capable = 0, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK + }, + { + .Brand = ZLIST( "AMD Ryzen 5 8540U", \ + "AMD Ryzen 3 8440U" ), + .Boost = {+17, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_PHOENIX_R, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .HSMP_Capable = 0, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK + }, + { + .Brand = ZLIST("AMD Ryzen 7 8700G"), + .Boost = {+9, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_PHOENIX_R, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 1, + .UncoreUnlocked = 0, + .HSMP_Capable = 0, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK + }, + { + .Brand = ZLIST("AMD Ryzen 5 8600G"), + .Boost = {+7, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_PHOENIX_R, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 1, + .UncoreUnlocked = 0, + .HSMP_Capable = 0, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK + }, + {0} +}; +static PROCESSOR_SPECIFIC AMD_Zen4_PHX2_Specific[] = { + { + .Brand = ZLIST( "AMD Ryzen 5 PRO 7545U", \ + "AMD Ryzen 5 7545U", \ + "AMD Ryzen 3 7440U" ), + .Boost = {+17, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_PHOENIX2, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .HSMP_Capable = 0, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK + }, + { + .Brand = ZLIST( "AMD Ryzen 5 8500G", \ + "AMD Ryzen 3 8300G" ), + .Boost = {+15, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_PHOENIX2, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .HSMP_Capable = 0, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK + }, + {0} +}; +static PROCESSOR_SPECIFIC AMD_Zen4_Bergamo_Specific[] = { + { + .Brand = ZLIST( "AMD EPYC Embedded 9754S", \ + "AMD EPYC Embedded 9754", \ + "AMD EPYC 9754S", \ + "AMD EPYC 9754" ), + .Boost = {+9, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_BERGAMO, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .HSMP_Capable = 1, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ + |LATCH_HSMP_CAPABLE + }, + { + .Brand = ZLIST( "AMD EPYC Embedded 9734", \ + "AMD EPYC 9734" ), + .Boost = {+8, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_BERGAMO, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .HSMP_Capable = 1, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ + |LATCH_HSMP_CAPABLE + }, + { + .Brand = ZLIST("AMD EPYC 8534PN"), + .Boost = {+11, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_SIENA, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .HSMP_Capable = 1, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ + |LATCH_HSMP_CAPABLE + }, + { + .Brand = ZLIST("AMD EPYC 8534P"), + .Boost = {+8, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_SIENA, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .HSMP_Capable = 1, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ + |LATCH_HSMP_CAPABLE + }, + { + .Brand = ZLIST( "AMD EPYC 8434PN", \ + "AMD EPYC 8324PN", \ + "AMD EPYC 8224PN", \ + "AMD EPYC 8124PN", \ + "AMD EPYC 8024PN" ) , + .Boost = {+10, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_SIENA, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .HSMP_Capable = 1, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ + |LATCH_HSMP_CAPABLE + }, + { + .Brand = ZLIST( "AMD EPYC 8434P", \ + "AMD EPYC 8124P", \ + "AMD EPYC 8024P" ) , + .Boost = {+6, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_SIENA, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .HSMP_Capable = 1, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ + |LATCH_HSMP_CAPABLE + }, + { + .Brand = ZLIST("AMD EPYC 8324P"), + .Boost = {+4, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_SIENA, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .HSMP_Capable = 1, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ + |LATCH_HSMP_CAPABLE + }, + { + .Brand = ZLIST("AMD EPYC 8224P"), + .Boost = {+5, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_SIENA, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .HSMP_Capable = 1, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ + |LATCH_HSMP_CAPABLE + }, + {0} +}; +static PROCESSOR_SPECIFIC AMD_Zen4_STP_Specific[] = { + { + .Brand = ZLIST("AMD Ryzen Threadripper PRO 7995WX"), + .Boost = {+26, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_STORM_PEAK, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 1, + .UncoreUnlocked = 0, + .HSMP_Capable = 1, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ + |LATCH_HSMP_CAPABLE + }, + { + .Brand = ZLIST( "AMD Ryzen Threadripper PRO 7985WX", \ + "AMD Ryzen Threadripper 7980X" ), + .Boost = {+19, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_STORM_PEAK, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 1, + .UncoreUnlocked = 0, + .HSMP_Capable = 1, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ + |LATCH_HSMP_CAPABLE + }, + { + .Brand = ZLIST( "AMD Ryzen Threadripper PRO 7975WX", \ + "AMD Ryzen Threadripper 7970X" ), + .Boost = {+13, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_STORM_PEAK, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 1, + .UncoreUnlocked = 0, + .HSMP_Capable = 1, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ + |LATCH_HSMP_CAPABLE + }, + { + .Brand = ZLIST( "AMD Ryzen Threadripper PRO 7965WX", \ + "AMD Ryzen Threadripper 7960X" ), + .Boost = {+11, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_STORM_PEAK, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 1, + .UncoreUnlocked = 0, + .HSMP_Capable = 1, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ + |LATCH_HSMP_CAPABLE + }, + { + .Brand = ZLIST("AMD Ryzen Threadripper PRO 7955WX"), + .Boost = {+8, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_STORM_PEAK, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 1, + .UncoreUnlocked = 0, + .HSMP_Capable = 1, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ + |LATCH_HSMP_CAPABLE + }, + { + .Brand = ZLIST("AMD Ryzen Threadripper PRO 7945WX"), + .Boost = {+6, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_STORM_PEAK, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 1, + .UncoreUnlocked = 0, + .HSMP_Capable = 1, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ + |LATCH_HSMP_CAPABLE + }, + {0} +}; + +static PROCESSOR_SPECIFIC Misc_Specific_Processor[] = { + {0} +}; + +#ifdef CONFIG_CPU_FREQ +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 19) +#define CPUFREQ_POLICY_UNKNOWN (0) +#endif +static int CoreFreqK_Policy_Exit(struct cpufreq_policy*) ; +static int CoreFreqK_Policy_Init(struct cpufreq_policy*) ; +#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 19)) \ + && (LINUX_VERSION_CODE <= KERNEL_VERSION(5, 5, 0))) \ + || (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 5, 3)) \ + || (RHEL_MAJOR == 8) +static int CoreFreqK_Policy_Verify(struct cpufreq_policy_data*) ; +#else +static int CoreFreqK_Policy_Verify(struct cpufreq_policy*) ; +#endif +static int CoreFreqK_SetPolicy(struct cpufreq_policy*) ; +static int CoreFreqK_Bios_Limit(int, unsigned int*) ; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 8, 0) \ + || ((RHEL_MAJOR == 8) && (RHEL_MINOR > 3)) +static int CoreFreqK_SetBoost(struct cpufreq_policy*, int) ; +#else +static int CoreFreqK_SetBoost(int) ; +#endif +#endif +static ssize_t CoreFreqK_Show_SetSpeed(struct cpufreq_policy*, char*); +static int CoreFreqK_Store_SetSpeed(struct cpufreq_policy*, unsigned int) ; +#endif /* CONFIG_CPU_FREQ */ + +static unsigned int Policy_GetFreq(unsigned int cpu) ; +static void Policy_Core2_SetTarget(void *arg) ; +static void Policy_Nehalem_SetTarget(void *arg) ; +static void Policy_SandyBridge_SetTarget(void *arg) ; +static void Policy_HWP_SetTarget(void *arg) ; +#define Policy_Broadwell_EP_SetTarget Policy_SandyBridge_SetTarget +static void Policy_Skylake_SetTarget(void *arg) ; +static void Policy_Zen_SetTarget(void *arg) ; +static void Policy_Zen_CPPC_SetTarget(void *arg) ; + +#define VOID_Driver { \ + .IdleState = NULL , \ + .GetFreq = NULL , \ + .SetTarget = NULL \ +} + +#define CORE2_Driver { \ + .IdleState = NULL , \ + .GetFreq = Policy_GetFreq, \ + .SetTarget = Policy_Core2_SetTarget \ +} + +static IDLE_STATE SLM_IdleState[] = { + { + .Name = "C1", + .Desc = "SLM-C1", .flags = 0x00 << 24, .Latency = 1, .Residency = 1 @@ -9038,8 +9656,8 @@ static ARCH Arch[ARCHITECTURES] = { .ClockMod = ClockMod_SandyBridge_PPC, .TurboClock = Intel_Turbo_Config8C, .thermalFormula = THERMAL_FORMULA_INTEL, - .voltageFormula = VOLTAGE_FORMULA_INTEL_SOC, - .powerFormula = POWER_FORMULA_INTEL_ATOM, + .voltageFormula = VOLTAGE_FORMULA_INTEL_SNB, + .powerFormula = POWER_FORMULA_INTEL, .PCI_ids = PCI_Void_ids, .Uncore = { .Start = NULL, @@ -9903,7 +10521,7 @@ static ARCH Arch[ARCHITECTURES] = { [Icelake] = { /* 58*/ .Signature = _Icelake, .Query = Query_Kaby_Lake, - .Update = PerCore_Skylake_Query, + .Update = PerCore_Icelake_Query, .Start = Start_Skylake, .Stop = Stop_Skylake, .Exit = NULL, @@ -9927,7 +10545,7 @@ static ARCH Arch[ARCHITECTURES] = { [Icelake_UY] = { /* 59*/ .Signature = _Icelake_UY, .Query = Query_Kaby_Lake, - .Update = PerCore_Skylake_Query, + .Update = PerCore_Icelake_Query, .Start = Start_Skylake, .Stop = Stop_Skylake, .Exit = NULL, @@ -10025,7 +10643,7 @@ static ARCH Arch[ARCHITECTURES] = { [Tigerlake] = { /* 63*/ .Signature = _Tigerlake, .Query = Query_Skylake, - .Update = PerCore_Kaby_Lake_Query, + .Update = PerCore_Tigerlake_Query, .Start = Start_Skylake, .Stop = Stop_Skylake, .Exit = NULL, @@ -10049,7 +10667,7 @@ static ARCH Arch[ARCHITECTURES] = { [Tigerlake_U] = { /* 64*/ .Signature = _Tigerlake_U, .Query = Query_Skylake, - .Update = PerCore_Kaby_Lake_Query, + .Update = PerCore_Tigerlake_Query, .Start = Start_Skylake, .Stop = Stop_Skylake, .Exit = NULL, @@ -10132,8 +10750,8 @@ static ARCH Arch[ARCHITECTURES] = { .ClockMod = ClockMod_SandyBridge_PPC, .TurboClock = Intel_Turbo_Config8C, .thermalFormula = THERMAL_FORMULA_INTEL, - .voltageFormula = VOLTAGE_FORMULA_INTEL_SOC, - .powerFormula = POWER_FORMULA_INTEL_ATOM, + .voltageFormula = VOLTAGE_FORMULA_INTEL_SNB, + .powerFormula = POWER_FORMULA_INTEL, .PCI_ids = PCI_Void_ids, .Uncore = { .Start = NULL, @@ -10147,7 +10765,7 @@ static ARCH Arch[ARCHITECTURES] = { [Tremont_Jacobsville] = { /* 68*/ .Signature = _Tremont_Jacobsville, .Query = Query_Goldmont, - .Update = PerCore_Goldmont_Query, + .Update = PerCore_Tremont_Query, .Start = Start_Goldmont, .Stop = Stop_Goldmont, .Exit = NULL, @@ -10437,7 +11055,7 @@ static ARCH Arch[ARCHITECTURES] = { [Alderlake_S] = { /* 80*/ .Signature = _Alderlake_S, .Query = Query_Skylake, - .Update = PerCore_Kaby_Lake_Query, + .Update = PerCore_Tigerlake_Query, .Start = Start_Alderlake, .Stop = Stop_Alderlake, .Exit = NULL, @@ -10461,7 +11079,7 @@ static ARCH Arch[ARCHITECTURES] = { [Alderlake_H] = { /* 81*/ .Signature = _Alderlake_H, .Query = Query_Skylake, - .Update = PerCore_Kaby_Lake_Query, + .Update = PerCore_Tigerlake_Query, .Start = Start_Alderlake, .Stop = Stop_Alderlake, .Exit = NULL, @@ -10478,7 +11096,7 @@ static ARCH Arch[ARCHITECTURES] = { .Stop = Stop_Uncore_Alderlake, .ClockMod = Haswell_Uncore_Ratio }, - .Specific = Void_Specific, + .Specific = Alderlake_H_Specific, .SystemDriver = SKL_Driver, .Architecture = Arch_Alderlake_H }, @@ -10510,7 +11128,7 @@ static ARCH Arch[ARCHITECTURES] = { [Meteorlake_M] = { /* 83*/ .Signature = _Meteorlake_M, .Query = Query_Skylake, - .Update = PerCore_Kaby_Lake_Query, + .Update = PerCore_Tigerlake_Query, .Start = Start_Alderlake, .Stop = Stop_Alderlake, .Exit = NULL, @@ -10534,7 +11152,7 @@ static ARCH Arch[ARCHITECTURES] = { [Meteorlake_N] = { /* 84*/ .Signature = _Meteorlake_N, .Query = Query_Skylake, - .Update = PerCore_Kaby_Lake_Query, + .Update = PerCore_Tigerlake_Query, .Start = Start_Alderlake, .Stop = Stop_Alderlake, .Exit = NULL, @@ -10558,7 +11176,7 @@ static ARCH Arch[ARCHITECTURES] = { [Meteorlake_S] = { /* 85*/ .Signature = _Meteorlake_S, .Query = Query_Skylake, - .Update = PerCore_Kaby_Lake_Query, + .Update = PerCore_Tigerlake_Query, .Start = Start_Alderlake, .Stop = Stop_Alderlake, .Exit = NULL, @@ -10583,7 +11201,7 @@ static ARCH Arch[ARCHITECTURES] = { [Raptorlake] = { /* 86*/ .Signature = _Raptorlake, .Query = Query_Skylake, - .Update = PerCore_Skylake_Query, + .Update = PerCore_Icelake_Query, .Start = Start_Alderlake, .Stop = Stop_Alderlake, .Exit = NULL, @@ -10607,7 +11225,7 @@ static ARCH Arch[ARCHITECTURES] = { [Raptorlake_P] = { /* 87*/ .Signature = _Raptorlake_P, .Query = Query_Skylake, - .Update = PerCore_Skylake_Query, + .Update = PerCore_Icelake_Query, .Start = Start_Alderlake, .Stop = Stop_Alderlake, .Exit = NULL, @@ -10631,7 +11249,7 @@ static ARCH Arch[ARCHITECTURES] = { [Raptorlake_S] = { /* 88*/ .Signature = _Raptorlake_S, .Query = Query_Skylake, - .Update = PerCore_Skylake_Query, + .Update = PerCore_Icelake_Query, .Start = Start_Alderlake, .Stop = Stop_Alderlake, .Exit = NULL, @@ -10655,7 +11273,7 @@ static ARCH Arch[ARCHITECTURES] = { [LunarLake] = { /* 89*/ .Signature = _Lunarlake, .Query = Query_Skylake, - .Update = PerCore_Skylake_Query, + .Update = PerCore_Icelake_Query, .Start = Start_Alderlake, .Stop = Stop_Alderlake, .Exit = NULL, @@ -10679,7 +11297,7 @@ static ARCH Arch[ARCHITECTURES] = { [ArrowLake] = { /* 90*/ .Signature = _Arrowlake, .Query = Query_Skylake, - .Update = PerCore_Skylake_Query, + .Update = PerCore_Icelake_Query, .Start = Start_Alderlake, .Stop = Stop_Alderlake, .Exit = NULL, @@ -10700,8 +11318,105 @@ static ARCH Arch[ARCHITECTURES] = { .SystemDriver = SKL_Driver, .Architecture = Arch_Arrowlake }, +[ArrowLake_H] = { /* 91*/ + .Signature = _Arrowlake_H, + .Query = Query_Skylake, + .Update = PerCore_Icelake_Query, + .Start = Start_Alderlake, + .Stop = Stop_Alderlake, + .Exit = NULL, + .Timer = InitTimer_Alderlake, + .BaseClock = BaseClock_Skylake, + .ClockMod = ClockMod_Skylake_HWP, + .TurboClock = Intel_Turbo_Config8C, + .thermalFormula = THERMAL_FORMULA_INTEL, + .voltageFormula = VOLTAGE_FORMULA_INTEL_SAV, + .powerFormula = POWER_FORMULA_INTEL, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = Start_Uncore_Alderlake, + .Stop = Stop_Uncore_Alderlake, + .ClockMod = Haswell_Uncore_Ratio + }, + .Specific = Void_Specific, + .SystemDriver = SKL_Driver, + .Architecture = Arch_Arrowlake_H + }, +[ArrowLake_U] = { /* 92*/ + .Signature = _Arrowlake_U, + .Query = Query_Skylake, + .Update = PerCore_Icelake_Query, + .Start = Start_Alderlake, + .Stop = Stop_Alderlake, + .Exit = NULL, + .Timer = InitTimer_Alderlake, + .BaseClock = BaseClock_Skylake, + .ClockMod = ClockMod_Skylake_HWP, + .TurboClock = Intel_Turbo_Config8C, + .thermalFormula = THERMAL_FORMULA_INTEL, + .voltageFormula = VOLTAGE_FORMULA_INTEL_SAV, + .powerFormula = POWER_FORMULA_INTEL, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = Start_Uncore_Alderlake, + .Stop = Stop_Uncore_Alderlake, + .ClockMod = Haswell_Uncore_Ratio + }, + .Specific = Void_Specific, + .SystemDriver = SKL_Driver, + .Architecture = Arch_Arrowlake_U + }, +[PantherLake] = { /* 93*/ + .Signature = _Pantherlake, + .Query = Query_Skylake, + .Update = PerCore_Icelake_Query, + .Start = Start_Alderlake, + .Stop = Stop_Alderlake, + .Exit = NULL, + .Timer = InitTimer_Alderlake, + .BaseClock = BaseClock_Skylake, + .ClockMod = ClockMod_Skylake_HWP, + .TurboClock = Intel_Turbo_Config8C, + .thermalFormula = THERMAL_FORMULA_INTEL, + .voltageFormula = VOLTAGE_FORMULA_INTEL_SAV, + .powerFormula = POWER_FORMULA_INTEL, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = Start_Uncore_Alderlake, + .Stop = Stop_Uncore_Alderlake, + .ClockMod = Haswell_Uncore_Ratio + }, + .Specific = Void_Specific, + .SystemDriver = SKL_Driver, + .Architecture = Arch_Pantherlake + }, + +[Clearwater_Forest] = { /* 94*/ + .Signature = _Clearwater_Forest, + .Query = Query_Skylake, + .Update = PerCore_Skylake_Query, + .Start = Start_Skylake, + .Stop = Stop_Skylake, + .Exit = NULL, + .Timer = InitTimer_Skylake, + .BaseClock = BaseClock_Skylake, + .ClockMod = ClockMod_Skylake_HWP, + .TurboClock = Intel_Turbo_Config8C, + .thermalFormula = THERMAL_FORMULA_INTEL, + .voltageFormula = VOLTAGE_FORMULA_INTEL_SNB, + .powerFormula = POWER_FORMULA_INTEL, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = Start_Uncore_Skylake, + .Stop = Stop_Uncore_Skylake, + .ClockMod = Haswell_Uncore_Ratio + }, + .Specific = Void_Specific, + .SystemDriver = Intel_Driver, + .Architecture = Arch_Clearwater_Forest + }, -[AMD_Zen] = { /* 91*/ +[AMD_Zen] = { /* 95*/ .Signature = _AMD_Zen, .Query = Query_AMD_F17h_PerSocket, .Update = PerCore_AMD_Family_17h_Query, @@ -10725,7 +11440,7 @@ static ARCH Arch[ARCHITECTURES] = { .SystemDriver = AMD_Zen_Driver, .Architecture = Arch_AMD_Zen }, -[AMD_Zen_APU] = { /* 92*/ +[AMD_Zen_APU] = { /* 96*/ .Signature = _AMD_Zen_APU, .Query = Query_AMD_F17h_PerSocket, .Update = PerCore_AMD_Family_17h_Query, @@ -10749,7 +11464,7 @@ static ARCH Arch[ARCHITECTURES] = { .SystemDriver = AMD_Zen_Driver, .Architecture = Arch_AMD_Zen_APU }, -[AMD_ZenPlus] = { /* 93*/ +[AMD_ZenPlus] = { /* 97*/ .Signature = _AMD_ZenPlus, .Query = Query_AMD_F17h_PerSocket, .Update = PerCore_AMD_Family_17h_Query, @@ -10773,7 +11488,7 @@ static ARCH Arch[ARCHITECTURES] = { .SystemDriver = AMD_Zen_Driver, .Architecture = Arch_AMD_ZenPlus }, -[AMD_ZenPlus_APU] = { /* 94*/ +[AMD_ZenPlus_APU] = { /* 98*/ .Signature = _AMD_ZenPlus_APU, .Query = Query_AMD_F17h_PerSocket, .Update = PerCore_AMD_Family_17h_Query, @@ -10797,7 +11512,7 @@ static ARCH Arch[ARCHITECTURES] = { .SystemDriver = AMD_Zen_Driver, .Architecture = Arch_AMD_ZenPlus_APU }, -[AMD_Zen_Dali] = { /* 95*/ +[AMD_Zen_Dali] = { /* 99*/ .Signature = _AMD_Zen_Dali, .Query = Query_AMD_F17h_PerSocket, .Update = PerCore_AMD_Family_17h_Query, @@ -10821,7 +11536,7 @@ static ARCH Arch[ARCHITECTURES] = { .SystemDriver = AMD_Zen_Driver, .Architecture = Arch_AMD_Zen_Dali }, -[AMD_EPYC_Rome_CPK] = { /* 96*/ +[AMD_EPYC_Rome_CPK] = { /*100*/ .Signature = _AMD_EPYC_Rome_CPK, .Query = Query_AMD_F17h_PerCluster, .Update = PerCore_AMD_Family_17h_Query, @@ -10845,7 +11560,7 @@ static ARCH Arch[ARCHITECTURES] = { .SystemDriver = AMD_Zen_Driver, .Architecture = Arch_AMD_EPYC_Rome_CPK }, -[AMD_Zen2_Renoir] = { /* 97*/ +[AMD_Zen2_Renoir] = { /*101*/ .Signature = _AMD_Zen2_Renoir, .Query = Query_AMD_F17h_PerSocket, .Update = PerCore_AMD_Family_17h_Query, @@ -10869,7 +11584,7 @@ static ARCH Arch[ARCHITECTURES] = { .SystemDriver = AMD_Zen_Driver, .Architecture = Arch_AMD_Zen2_Renoir }, -[AMD_Zen2_LCN] = { /* 98*/ +[AMD_Zen2_LCN] = { /*102*/ .Signature = _AMD_Zen2_LCN, .Query = Query_AMD_F17h_PerSocket, .Update = PerCore_AMD_Family_17h_Query, @@ -10893,7 +11608,7 @@ static ARCH Arch[ARCHITECTURES] = { .SystemDriver = AMD_Zen_Driver, .Architecture = Arch_AMD_Zen2_LCN }, -[AMD_Zen2_MTS] = { /* 99*/ +[AMD_Zen2_MTS] = { /*103*/ .Signature = _AMD_Zen2_MTS, .Query = Query_AMD_F17h_PerCluster, .Update = PerCore_AMD_Family_17h_Query, @@ -10917,9 +11632,9 @@ static ARCH Arch[ARCHITECTURES] = { .SystemDriver = AMD_Zen_Driver, .Architecture = Arch_AMD_Zen2_MTS }, -[AMD_Zen2_Ariel] = { /*100*/ +[AMD_Zen2_Ariel] = { /*104*/ .Signature = _AMD_Zen2_Ariel, - .Query = Query_AMD_F17h_PerCluster, + .Query = Query_AMD_F17h_PerSocket, .Update = PerCore_AMD_Family_17h_Query, .Start = Start_AMD_Family_17h, .Stop = Stop_AMD_Family_17h, @@ -10941,9 +11656,9 @@ static ARCH Arch[ARCHITECTURES] = { .SystemDriver = AMD_Zen_Driver, .Architecture = Arch_AMD_Zen2_Ariel }, -[AMD_Zen2_Jupiter] = { /*101*/ +[AMD_Zen2_Jupiter] = { /*105*/ .Signature = _AMD_Zen2_Jupiter, - .Query = Query_AMD_F17h_PerCluster, + .Query = Query_AMD_F17h_PerSocket, .Update = PerCore_AMD_Family_17h_Query, .Start = Start_AMD_Family_17h, .Stop = Stop_AMD_Family_17h, @@ -10965,9 +11680,33 @@ static ARCH Arch[ARCHITECTURES] = { .SystemDriver = AMD_Zen_Driver, .Architecture = Arch_AMD_Zen2_Jupiter }, -[AMD_Zen2_MDN] = { /*102*/ +[AMD_Zen2_Galileo] = { /*106*/ + .Signature = _AMD_Zen2_Galileo, + .Query = Query_AMD_F17h_PerSocket, + .Update = PerCore_AMD_Family_17h_Query, + .Start = Start_AMD_Family_17h, + .Stop = Stop_AMD_Family_17h, + .Exit = Exit_AMD_F17h, + .Timer = InitTimer_AMD_F17h_Zen2_SP, + .BaseClock = BaseClock_AMD_Family_17h, + .ClockMod = ClockMod_AMD_Zen, + .TurboClock = TurboClock_AMD_Zen, + .thermalFormula = THERMAL_FORMULA_AMD_ZEN2, + .voltageFormula = VOLTAGE_FORMULA_AMD_17h, + .powerFormula = POWER_FORMULA_AMD_17h, + .PCI_ids = PCI_AMD_17h_ids, + .Uncore = { + .Start = Start_Uncore_AMD_Family_17h, + .Stop = Stop_Uncore_AMD_Family_17h, + .ClockMod = NULL + }, + .Specific = Void_Specific, + .SystemDriver = AMD_Zen_Driver, + .Architecture = Arch_AMD_Zen2_Galileo + }, +[AMD_Zen2_MDN] = { /*107*/ .Signature = _AMD_Zen2_MDN, - .Query = Query_AMD_F17h_PerCluster, + .Query = Query_AMD_F17h_PerSocket, .Update = PerCore_AMD_Family_17h_Query, .Start = Start_AMD_Family_17h, .Stop = Stop_AMD_Family_17h, @@ -10989,7 +11728,7 @@ static ARCH Arch[ARCHITECTURES] = { .SystemDriver = AMD_Zen_Driver, .Architecture = Arch_AMD_Zen2_MDN }, -[AMD_Zen3_VMR] = { /*103*/ +[AMD_Zen3_VMR] = { /*108*/ .Signature = _AMD_Zen3_VMR, .Query = Query_AMD_F19h_PerCluster, .Update = PerCore_AMD_Family_19h_Query, @@ -11013,7 +11752,7 @@ static ARCH Arch[ARCHITECTURES] = { .SystemDriver = AMD_Zen_Driver, .Architecture = Arch_AMD_Zen3_VMR }, -[AMD_Zen3_CZN] = { /*104*/ +[AMD_Zen3_CZN] = { /*109*/ .Signature = _AMD_Zen3_CZN, .Query = Query_AMD_F19h_PerSocket, .Update = PerCore_AMD_Family_19h_Query, @@ -11037,7 +11776,7 @@ static ARCH Arch[ARCHITECTURES] = { .SystemDriver = AMD_Zen_Driver, .Architecture = Arch_AMD_Zen3_CZN }, -[AMD_EPYC_Milan] = { /*105*/ +[AMD_EPYC_Milan] = { /*110*/ .Signature = _AMD_EPYC_Milan, .Query = Query_AMD_F19h_PerCluster, .Update = PerCore_AMD_Family_19h_Query, @@ -11061,7 +11800,7 @@ static ARCH Arch[ARCHITECTURES] = { .SystemDriver = AMD_Zen_Driver, .Architecture = Arch_AMD_EPYC_Milan }, -[AMD_Zen3_Chagall] = { /*106*/ +[AMD_Zen3_Chagall] = { /*111*/ .Signature = _AMD_Zen3_Chagall, .Query = Query_AMD_F19h_PerCluster, .Update = PerCore_AMD_Family_19h_Query, @@ -11085,7 +11824,7 @@ static ARCH Arch[ARCHITECTURES] = { .SystemDriver = AMD_Zen_Driver, .Architecture = Arch_AMD_Zen3_Chagall }, -[AMD_Zen3_Badami] = { /*107*/ +[AMD_Zen3_Badami] = { /*112*/ .Signature = _AMD_Zen3_Badami, .Query = Query_AMD_F19h_PerCluster, .Update = PerCore_AMD_Family_19h_Query, @@ -11109,7 +11848,7 @@ static ARCH Arch[ARCHITECTURES] = { .SystemDriver = AMD_Zen_Driver, .Architecture = Arch_AMD_Zen3_Badami }, -[AMD_Zen3Plus_RMB] = { /*108*/ +[AMD_Zen3Plus_RMB] = { /*113*/ .Signature = _AMD_Zen3Plus_RMB, .Query = Query_AMD_F19h_PerSocket, .Update = PerCore_AMD_Family_19h_Query, @@ -11133,9 +11872,9 @@ static ARCH Arch[ARCHITECTURES] = { .SystemDriver = AMD_Zen_Driver, .Architecture = Arch_AMD_Zen3Plus_RMB }, -[AMD_Zen4_Genoa] = { /*109*/ +[AMD_Zen4_Genoa] = { /*114*/ .Signature = _AMD_Zen4_Genoa, - .Query = Query_AMD_F19h_PerCluster, + .Query = Query_AMD_F19h_11h_PerCluster, .Update = PerCore_AMD_Family_19h_Query, .Start = Start_AMD_Family_19h, .Stop = Stop_AMD_Family_19h, @@ -11157,7 +11896,7 @@ static ARCH Arch[ARCHITECTURES] = { .SystemDriver = AMD_Zen_Driver, .Architecture = Arch_AMD_Zen4_Genoa }, -[AMD_Zen4_RPL] = { /*110*/ +[AMD_Zen4_RPL] = { /*115*/ .Signature = _AMD_Zen4_RPL, .Query = Query_AMD_F19h_61h_PerCluster, .Update = PerCore_AMD_Family_19h_Query, @@ -11181,7 +11920,7 @@ static ARCH Arch[ARCHITECTURES] = { .SystemDriver = AMD_Zen_Driver, .Architecture = Arch_AMD_Zen4_RPL }, -[AMD_Zen4_PHX] = { /*111*/ +[AMD_Zen4_PHX] = { /*116*/ .Signature = _AMD_Zen4_PHX, .Query = Query_AMD_F19h_74h_PerSocket, .Update = PerCore_AMD_Family_19h_Query, @@ -11205,9 +11944,57 @@ static ARCH Arch[ARCHITECTURES] = { .SystemDriver = AMD_Zen_Driver, .Architecture = Arch_AMD_Zen4_PHX }, -[AMD_Zen4_Bergamo] = { /*112*/ +[AMD_Zen4_HWK] = { /*117*/ + .Signature = _AMD_Zen4_HWK, + .Query = Query_AMD_F19h_PerSocket, + .Update = PerCore_AMD_Family_19h_Query, + .Start = Start_AMD_Family_19h, + .Stop = Stop_AMD_Family_19h, + .Exit = Exit_AMD_F19h, + .Timer = InitTimer_AMD_Zen4_PHX, + .BaseClock = BaseClock_AMD_Family_19h, + .ClockMod = ClockMod_AMD_Zen, + .TurboClock = TurboClock_AMD_Zen, + .thermalFormula = THERMAL_FORMULA_AMD_19h, + .voltageFormula = VOLTAGE_FORMULA_AMD_ZEN4, + .powerFormula = POWER_FORMULA_AMD_19h, + .PCI_ids = PCI_AMD_19h_ids, + .Uncore = { + .Start = Start_Uncore_AMD_Family_19h, + .Stop = Stop_Uncore_AMD_Family_19h, + .ClockMod = NULL + }, + .Specific = AMD_Zen4_HWK_Specific, + .SystemDriver = AMD_Zen_Driver, + .Architecture = Arch_AMD_Zen4_HWK + }, +[AMD_Zen4_PHX2] = { /*118*/ + .Signature = _AMD_Zen4_PHX2, + .Query = Query_AMD_F19h_74h_PerSocket, + .Update = PerCore_AMD_Family_19h_Query, + .Start = Start_AMD_Family_19h, + .Stop = Stop_AMD_Family_19h, + .Exit = Exit_AMD_F19h, + .Timer = InitTimer_AMD_Zen4_PHX, + .BaseClock = BaseClock_AMD_Family_19h, + .ClockMod = ClockMod_AMD_Zen, + .TurboClock = TurboClock_AMD_Zen, + .thermalFormula = THERMAL_FORMULA_AMD_ZEN4, + .voltageFormula = VOLTAGE_FORMULA_AMD_ZEN4, + .powerFormula = POWER_FORMULA_AMD_19h, + .PCI_ids = PCI_AMD_19h_ids, + .Uncore = { + .Start = Start_Uncore_AMD_Family_19h, + .Stop = Stop_Uncore_AMD_Family_19h, + .ClockMod = NULL + }, + .Specific = AMD_Zen4_PHX2_Specific, + .SystemDriver = AMD_Zen_Driver, + .Architecture = Arch_AMD_Zen4_PHX2 + }, +[AMD_Zen4_Bergamo] = { /*119*/ .Signature = _AMD_Zen4_Bergamo, - .Query = Query_AMD_F19h_PerCluster, + .Query = Query_AMD_F19h_11h_PerCluster, .Update = PerCore_AMD_Family_19h_Query, .Start = Start_AMD_Family_19h, .Stop = Stop_AMD_Family_19h, @@ -11228,5 +12015,29 @@ static ARCH Arch[ARCHITECTURES] = { .Specific = AMD_Zen4_Bergamo_Specific, .SystemDriver = AMD_Zen_Driver, .Architecture = Arch_AMD_Zen4_Bergamo + }, +[AMD_Zen4_STP] = { /*120*/ + .Signature = _AMD_Zen4_STP, + .Query = Query_AMD_F19h_11h_PerCluster, + .Update = PerCore_AMD_Family_19h_Query, + .Start = Start_AMD_Family_19h, + .Stop = Stop_AMD_Family_19h, + .Exit = Exit_AMD_F19h, + .Timer = InitTimer_AMD_F19h_Zen3_MP, + .BaseClock = BaseClock_AMD_Family_19h, + .ClockMod = ClockMod_AMD_Zen, + .TurboClock = TurboClock_AMD_Zen, + .thermalFormula = THERMAL_FORMULA_AMD_ZEN4, + .voltageFormula = VOLTAGE_FORMULA_AMD_ZEN4, + .powerFormula = POWER_FORMULA_AMD_19h, + .PCI_ids = PCI_AMD_19h_ids, + .Uncore = { + .Start = Start_Uncore_AMD_Family_19h, + .Stop = Stop_Uncore_AMD_Family_19h, + .ClockMod = NULL + }, + .Specific = AMD_Zen4_STP_Specific, + .SystemDriver = AMD_Zen_Driver, + .Architecture = Arch_AMD_Zen4_STP } }; diff --git a/corefreqm.c b/x86_64/corefreqm.c similarity index 97% rename from corefreqm.c rename to x86_64/corefreqm.c index bcab9601..652ba1d8 100644 --- a/corefreqm.c +++ b/x86_64/corefreqm.c @@ -1,6 +1,6 @@ /* * CoreFreq - * Copyright (C) 2015-2023 CYRIL COURTIAT + * Copyright (C) 2015-2024 CYRIL COURTIAT * Licenses: GPL2 */ @@ -276,11 +276,15 @@ void Slice_Monte_Carlo(RO(SHM_STRUCT) *RO(Shm), RW(SHM_STRUCT) *RW(Shm), { double X, Y, Z; UNUSED(arg); - + #ifdef __GLIBC__ if (!random_r( &RO(Shm)->Cpu[cpu].Slice.Random.data, &RO(Shm)->Cpu[cpu].Slice.Random.value[0] ) && !random_r( &RO(Shm)->Cpu[cpu].Slice.Random.data, &RO(Shm)->Cpu[cpu].Slice.Random.value[1] )) + #else + RO(Shm)->Cpu[cpu].Slice.Random.value[0] = (int) random(); + RO(Shm)->Cpu[cpu].Slice.Random.value[1] = (int) random(); + #endif /* __GLIBC__ */ { X = (double) RO(Shm)->Cpu[cpu].Slice.Random.value[0] / RAND_MAX; Y = (double) RO(Shm)->Cpu[cpu].Slice.Random.value[1] / RAND_MAX; diff --git a/corefreqm.h b/x86_64/corefreqm.h similarity index 97% rename from corefreqm.h rename to x86_64/corefreqm.h index c2e24c04..0247f761 100644 --- a/corefreqm.h +++ b/x86_64/corefreqm.h @@ -1,6 +1,6 @@ /* * CoreFreq - * Copyright (C) 2015-2023 CYRIL COURTIAT + * Copyright (C) 2015-2024 CYRIL COURTIAT * Licenses: GPL2 */ diff --git a/coretypes.h b/x86_64/coretypes.h similarity index 93% rename from coretypes.h rename to x86_64/coretypes.h index f2e16884..02ce946d 100644 --- a/coretypes.h +++ b/x86_64/coretypes.h @@ -1,12 +1,12 @@ /* * CoreFreq - * Copyright (C) 2015-2023 CYRIL COURTIAT + * Copyright (C) 2015-2024 CYRIL COURTIAT * Licenses: GPL2 */ #define COREFREQ_MAJOR 1 -#define COREFREQ_MINOR 96 -#define COREFREQ_REV 5 +#define COREFREQ_MINOR 97 +#define COREFREQ_REV 1 #if !defined(CORE_COUNT) #define CORE_COUNT 256 @@ -118,6 +118,10 @@ enum { GenuineArch = 0, Raptorlake_S, LunarLake, ArrowLake, + ArrowLake_H, + ArrowLake_U, + PantherLake, + Clearwater_Forest, AMD_Zen, AMD_Zen_APU, AMD_ZenPlus, @@ -129,6 +133,7 @@ enum { GenuineArch = 0, AMD_Zen2_MTS, AMD_Zen2_Ariel, AMD_Zen2_Jupiter, + AMD_Zen2_Galileo, AMD_Zen2_MDN, AMD_Zen3_VMR, AMD_Zen3_CZN, @@ -139,7 +144,10 @@ enum { GenuineArch = 0, AMD_Zen4_Genoa, AMD_Zen4_RPL, AMD_Zen4_PHX, + AMD_Zen4_HWK, + AMD_Zen4_PHX2, AMD_Zen4_Bergamo, + AMD_Zen4_STP, ARCHITECTURES }; @@ -164,8 +172,13 @@ enum HYPERVISOR { #define HYPERVISORS ( 1 + HYPERV_HYPERV ) enum SYS_REG { + RFLAG_CF = 0, + RFLAG_ZF = 6, + RFLAG_SF = 7, RFLAG_TF = 8, RFLAG_IF = 9, + RFLAG_DF = 10, + RFLAG_OF = 11, RFLAG_IOPL = 12, /* [13:12] */ RFLAG_NT = 14, RFLAG_RF = 16, @@ -218,6 +231,7 @@ enum SYS_REG { CR4_PKS = 24, CR4_UINTR = 25, CR4_LAM_SUP = 28, + CR4_FRED = 32, CR8_TPL = 0, /* [3:0] */ @@ -246,11 +260,13 @@ enum SYS_REG { XCR0_FPU = 0, XCR0_SSE = 1, XCR0_AVX = 2, - XCR0_MPX = 3, + XCR0_MPX = 3, /* [BNDCSR:4, BNDREG:3] */ XCR0_AVX512 = 5, /* [7:5] */ XCR0_PKRU = 9, - XCR0_CET_U = 11, /* AMD64 */ - XCR0_CET_S = 12, /* AMD64 */ + XCR0_CET_U = 11, /* AMD64, Intel */ + XCR0_CET_S = 12, /* AMD64, Intel */ + XCR0_AMX = 17, /* Sapphire Rapids [TILEDATA:18, TILECFG:17] */ + XCR0_APX = 19, XCR0_LWP = 62, /* AMD64 */ SYSCFG_MFD = 18, /* AMD64: System Configuration Register */ @@ -263,6 +279,36 @@ enum SYS_REG { SYSCFG_VMPL = 25, SYSCFG_HMK = 26, + HWCR_SMM = 0, + HWCR_SLW = 1, /* AMD F0FH: SLOWFENCE */ + HWCR_TLB = 3, + HWCR_WBI = 4, + HWCR_FF = 6, /* AMD F0FH: TLB Flush Filter */ + HWCR_FRR = 7, + HWCR_IG = 8, + HWCR_SMW = 9, + HWCR_UMW = 10, + HWCR_HLT = 12, /* AMD F0FH,F12H: halt-exit special bus cycle */ + HWCR_SMI = 13, + HWCR_RSM = 14, + HWCR_SSE = 15, /* AMD F0FH: SSE Instructions Disable. */ + HWCR_WRP = 17, + HWCR_MC = 18, + HWCR_IO = 20, + HWCR_P0 = 21, + HWCR_PRB = 23, /* F12H: Force probes for RdSized and WrSized */ + HWCR_INC = 24, + HWCR_CPB = 25, + HWCR_HCF = 26, + HWCR_ROC = 27, + HWCR_SMU = 28, /* AMD F12H: SmuLock */ + HWCR_CSE = 29, + HWCR_IR = 30, + HWCR_SBR = 31, + HWCR_TPR = 32, + HWCR_PG = 33, + HWCR_ID = 35, + UNDEF_CR = 64 }; @@ -820,7 +866,7 @@ enum UNCORE_BOOST { #define CLOCK_GHz(_t, _f) ((_t)(_f) / (_t)UNIT_GHz(1)) #if !defined(MAX_FREQ_HZ) - #define MAX_FREQ_HZ 6575000000 + #define MAX_FREQ_HZ 7125000000 #elif (MAX_FREQ_HZ < 4850000000) #error "MAX_FREQ_HZ must be at least 4850000000 Hz" #endif @@ -979,7 +1025,16 @@ enum CPUID_ENUM { CPUID_00000019_00000000_KEY_LOCKER, CPUID_0000001A_00000000_HYBRID_INFORMATION, CPUID_0000001B_00000000_PCONFIG_INFORMATION, + CPUID_0000001C_00000000_LAST_BRANCH_RECORDS, + CPUID_0000001D_00000000_TILE_PALETTE_MAIN_LEAF, + CPUID_0000001D_00000001_TILE_PALETTE_SUB_LEAF_1, + CPUID_0000001E_00000000_TMUL_MAIN_LEAF, CPUID_0000001F_00000000_EXT_TOPOLOGY_V2, + CPUID_00000020_00000000_PROCESSOR_HRESET, + CPUID_00000023_00000000_PM_EXT_MAIN_LEAF, + CPUID_00000023_00000001_PM_EXT_SUB_LEAF_1, + CPUID_00000023_00000002_PM_EXT_SUB_LEAF_2, + CPUID_00000023_00000003_PM_EXT_SUB_LEAF_3, /* x86 */ CPUID_80000001_00000000_EXTENDED_FEATURES, CPUID_80000002_00000000_PROCESSOR_NAME_ID, @@ -1397,16 +1452,20 @@ typedef struct /* Extended Feature Flags Enumeration Leaf 1 */ FZRM : 11-10, /* Fast Zero-length REP MOVSB */ FSRS : 12-11, /* Fast Short REP STOSB:Store String */ FSRC : 13-12, /* Fast Short REP CMPSB, REP SCASB */ - Reserved3 : 19-13, + Reserved3 : 17-13, + FRED : 18-17, /* Flexible Return and Event Delivery*/ + LKGS : 19-18, /* Load Kernel GS segment register */ WRMSRNS : 20-19, /* Sierra Forest, Grand Ridge */ - Reserved4 : 21-20, + NMI_SRC : 21-20, /* NMI-source reporting */ AMX_FP16 : 22-21, /* Granite Rapids */ HRESET : 23-22, /* History Reset instruction */ AVX_IFMA : 24-23, /* Sierra Forest, Grand Ridge */ - Reserved5 : 26-24, + Reserved4 : 26-24, LAM : 27-26, /* Linear Address Masking */ RDMSRLIST : 28-27, /* Sierra Forest, Grand Ridge */ - Reserved6 : 32-28; + Reserved5 : 30-28, + INVD_DISABLE : 31-30, + Reserved6 : 32-31; } EAX; struct { @@ -1429,7 +1488,8 @@ typedef struct /* Extended Feature Flags Enumeration Leaf 1 */ PREFETCHI : 15-14, /* Granite Rapids: IA32_UINTR */ Reserved3 : 18-15, CET_SSS : 19-18, - Reserved4 : 32-19; + AVX10 : 20-19, /* AVX10 Converged Vector ISA */ + Reserved4 : 32-20; } EDX; } CPUID_0x00000007_1; @@ -1492,6 +1552,75 @@ typedef struct /* Architectural Performance Monitoring Leaf. */ } EDX; } CPUID_0x0000000a; +typedef struct /* Processor Extended State Enumeration Main Leaf. */ +{ + struct + { + unsigned int + XCR0_FPU : 1-0, + XCR0_SSE : 2-1, + XCR0_AVX : 3-2, + XCR0_MPX : 5-3, + XCR0_AVX512 : 8-5, + IA32_XSS_8 : 9-8, + XCR0_PKRU : 10-9, + IA32_XSS_10 : 17-10, + TILECFG : 18-17, + TILEDATA : 19-18, + Reserved : 32-19; + } EAX; + struct + { + unsigned int + XCR0_MaxSize : 32-0; + } EBX, ECX; + struct + { + unsigned int + XCR0_UpperBits : 32-0; + } EDX; +} CPUID_0x0000000d; + +typedef struct /* Processor Extended State Enumeration Sub-leaf. */ +{ + struct + { + unsigned int + XSAVEOPT : 1-0, + XSAVEC : 2-1, + XGETBV : 3-2, + IA32_XSS : 4-3, + XFD : 5-4, + Reserved : 32-5; + } EAX; + struct + { + unsigned int + XSAVE_Size : 32-0; /* if (!EAX.IA32_XSS && EAX.XSAVEC) */ + } EBX; + struct + { + unsigned int + XSS_XCR0_0 : 8-0, + XSS_PT : 9-8, + XSS_XCR0_9 : 10-9, + XSS_PASID : 11-10, + XSS_CET_U : 12-11, + XSS_CET_S : 13-12, + XSS_HDC : 14-13, + XSS_UINTR : 15-14, + XSS_LBR : 16-15, + XSS_HWP : 17-16, + XSS_XCR0_17 : 19-17, + Reserved : 32-19; + } ECX; + struct + { + unsigned int + XSS_UpperBits : 32-0; + } EDX; +} CPUID_0x0000000d_1; + typedef struct /* Intel Hybrid Information Enumeration Leaf */ { unsigned int @@ -1799,6 +1928,33 @@ typedef struct /* AMD Extended ID Leaf. */ } EDX; } CPUID_0x8000001e; +typedef struct /* AMD Extended Feature Identification 2 */ +{ + struct CPUID_0x80000021_EAX { + unsigned int + NoNestDataBp : 1-0, + Reserved_01 : 2-1, + LFenceAlways : 3-2, + SmmPgCfgLock : 4-3, + Reserved_04 : 5-4, + Reserved_05 : 6-5, + NullSelector : 7-6, + UAIE : 8-7, + AUTO_IBRS : 9-8, + NoSmmCtl_MSR : 10-9, + Reserved_10 : 11-10, + Reserved_11 : 12-11, + Reserved_12 : 13-12, + PrefetchCtl_MSR : 14-13, + Reserved_14 : 15-14, + Reserved_15 : 16-15, + Reserved_16 : 17-16, + CpuidUserDis : 18-17, + EPSF : 19-18, + Reserved : 32-19; + } EAX; +} CPUID_0x80000021; + enum /* Intel SGX Capability Enumeration Leaf. */ { CPUID_00000012_00000000_EAX_SGX1, @@ -1842,7 +1998,7 @@ enum /* AMD SVM Revision and Feature Identification. */ CPUID_8000000A_00000000_EDX_VMCB_Clean, CPUID_8000000A_00000000_EDX_FlushBy_ASID, CPUID_8000000A_00000000_EDX_DecodeAssists, - CPUID_8000000A_00000000_EDX_Reserved_08, + CPUID_8000000A_00000000_EDX_PmcVirt, CPUID_8000000A_00000000_EDX_Reserved_09, CPUID_8000000A_00000000_EDX_PAUSE_Filter, CPUID_8000000A_00000000_EDX_Reserved_11, @@ -1861,10 +2017,10 @@ enum /* AMD SVM Revision and Feature Identification. */ CPUID_8000000A_00000000_EDX_TLB_Intercept, CPUID_8000000A_00000000_EDX_VNMI, CPUID_8000000A_00000000_EDX_IBS_Virt, - CPUID_8000000A_00000000_EDX_Reserved_27, - CPUID_8000000A_00000000_EDX_Reserved_28, - CPUID_8000000A_00000000_EDX_Reserved_29, - CPUID_8000000A_00000000_EDX_Reserved_30, + CPUID_8000000A_00000000_EDX_ExtLvtAvicAccessChg, + CPUID_8000000A_00000000_EDX_NestedVirtVmcbAddrChk, + CPUID_8000000A_00000000_EDX_BusLockThreshold, + CPUID_8000000A_00000000_EDX_IdleHltIntercept, CPUID_8000000A_00000000_EDX_Reserved_31 }; @@ -1891,24 +2047,24 @@ enum /* AMD Encrypted Memory Capabilities. */ CPUID_8000001F_00000000_EAX_SEV_64BitHost, CPUID_8000001F_00000000_EAX_RestrictedInject, CPUID_8000001F_00000000_EAX_AlternateInject, - CPUID_8000001F_00000000_EAX_DebugSwap, + CPUID_8000001F_00000000_EAX_DebugSwap, /* DebugVirt */ CPUID_8000001F_00000000_EAX_Prevent_Host_IBS, CPUID_8000001F_00000000_EAX_VTE, CPUID_8000001F_00000000_EAX_VMGEXIT_Param, CPUID_8000001F_00000000_EAX_Virtual_TOM_MSR, CPUID_8000001F_00000000_EAX_IBS_Virt_SEV_ES, - CPUID_8000001F_00000000_EAX_Reserved_20, - CPUID_8000001F_00000000_EAX_Reserved_21, + CPUID_8000001F_00000000_EAX_PmcVirtGuestCtl, + CPUID_8000001F_00000000_EAX_RMPREAD, CPUID_8000001F_00000000_EAX_Reserved_22, CPUID_8000001F_00000000_EAX_Reserved_23, CPUID_8000001F_00000000_EAX_VMSA_Protection, CPUID_8000001F_00000000_EAX_SMT_Protection, - CPUID_8000001F_00000000_EAX_Reserved_26, - CPUID_8000001F_00000000_EAX_Reserved_27, + CPUID_8000001F_00000000_EAX_SecureAvic, + CPUID_8000001F_00000000_EAX_AllowedSevFeatures, CPUID_8000001F_00000000_EAX_SVSM_MSR, CPUID_8000001F_00000000_EAX_Virt_SNP_MSR, - CPUID_8000001F_00000000_EAX_Reserved_30, - CPUID_8000001F_00000000_EAX_Reserved_31 + CPUID_8000001F_00000000_EAX_HvInUseWrAllowed, + CPUID_8000001F_00000000_EAX_IbpbOnEntry }; enum /* AMD Multi-Key Encrypted Memory Capabilities. */ @@ -1993,9 +2149,12 @@ typedef struct /* BSP CPUID features. */ struct CPUID_0x00000007_1_EDX ExtFeature_Leaf1_EDX; struct CPUID_0x00000007_2_EDX ExtFeature_Leaf2_EDX; CPUID_0x0000000a PerfMon; + CPUID_0x0000000d ExtState; + CPUID_0x0000000d_1 ExtState_Leaf1; CPUID_0x80000001 ExtInfo; CPUID_0x80000007 AdvPower; CPUID_0x80000008 leaf80000008; + struct CPUID_0x80000021_EAX ExtFeature2_EAX; struct { unsigned long long PPIN; @@ -2404,8 +2563,18 @@ enum { TECHNOLOGY_R2H, TECHNOLOGY_L1_HW_PREFETCH, TECHNOLOGY_L1_HW_IP_PREFETCH, + TECHNOLOGY_L1_NPP_PREFETCH, + TECHNOLOGY_L1_SCRUBBING, TECHNOLOGY_L2_HW_PREFETCH, TECHNOLOGY_L2_HW_CL_PREFETCH, + TECHNOLOGY_L2_AMP_PREFETCH, + TECHNOLOGY_L2_NLP_PREFETCH, + TECHNOLOGY_L1_STRIDE_PREFETCH, + TECHNOLOGY_L1_REGION_PREFETCH, + TECHNOLOGY_L1_BURST_PREFETCH, + TECHNOLOGY_L2_STREAM_HW_PREFETCH, + TECHNOLOGY_L2_UPDOWN_PREFETCH, + TECHNOLOGY_LLC_STREAMER, TECHNOLOGY_CFG_TDP_LVL, TECHNOLOGY_TDP_LIMITING, TECHNOLOGY_TDP_OFFSET, diff --git a/intel_reg.h b/x86_64/intel_reg.h similarity index 96% rename from intel_reg.h rename to x86_64/intel_reg.h index 70bb6bad..229d35dd 100644 --- a/intel_reg.h +++ b/x86_64/intel_reg.h @@ -1,6 +1,6 @@ /* * CoreFreq - * Copyright (C) 2015-2023 CYRIL COURTIAT + * Copyright (C) 2015-2024 CYRIL COURTIAT * Licenses: GPL2 */ @@ -36,6 +36,8 @@ #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a #endif +#define MSR_IA32_OVERCLOCKING_STATUS 0x00000195 + #ifndef MSR_IA32_XAPIC_DISABLE_STATUS #define MSR_IA32_XAPIC_DISABLE_STATUS 0x000000bd #endif @@ -94,6 +96,16 @@ #define MSR_TURBO_POWER_CURRENT_LIMIT 0x000001ac #endif +#define MSR_IA32_FRED_STKLVLS 0x000001d0 +#define MSR_IA32_FRED_SSP1 0x000001d1 +#define MSR_IA32_FRED_SSP2 0x000001d2 +#define MSR_IA32_FRED_SSP3 0x000001d3 +#define MSR_IA32_FRED_CONFIG 0x000001d4 +#define MSR_IA32_FRED_RSP0 0x000001cc +#define MSR_IA32_FRED_RSP1 0x000001cd +#define MSR_IA32_FRED_RSP2 0x000001ce +#define MSR_IA32_FRED_RSP3 0x000001cf + #ifndef MSR_IA32_POWER_CTL #define MSR_IA32_POWER_CTL 0x000001fc #endif @@ -341,6 +353,10 @@ #define MSR_IA32_HWP_REQUEST MSR_HWP_REQUEST #endif +#ifndef MSR_IA32_XSS + #define MSR_IA32_XSS 0x00000da0 +#endif + /* MSR registers related to Hardware Duty Cycling (HDC) */ #ifndef MSR_IA32_PKG_HDC_CTL #define MSR_IA32_PKG_HDC_CTL 0x00000db0 @@ -412,11 +428,19 @@ #endif #endif +#define MSR_CORE_UARCH_CTL 0x00000541 + /* Partially documented registers */ #define MSR_FLEX_RATIO 0x00000194 -#define MSR_IA32_OVERCLOCKING_STATUS 0x00000195 #define MSR_IA32_MISC_PACKAGE_CTLS 0x000000bc +/* Whitepaper: Hardware Prefetch Controls for Intel Atom Cores */ +#define MSR_ATOM_L2_PREFETCH_0X1320 0x00001320 +#define MSR_ATOM_L2_PREFETCH_0X1321 0x00001321 +#define MSR_ATOM_L2_PREFETCH_0X1322 0x00001322 +#define MSR_ATOM_L2_PREFETCH_0X1323 0x00001323 +#define MSR_ATOM_L2_PREFETCH_0X1324 0x00001324 + typedef union { unsigned long long value; @@ -528,23 +552,23 @@ typedef union PSCHANGE_MC_NO : 7-6, TSX_CTRL : 8-7, TAA_NO : 9-8, - ReservedBits1 : 10-9, + MCU_CONTROL_SUP : 10-9, /* IA32_MCU_CONTROL MSR */ MISC_PACKAGE_CTLS_SUP : 11-10, /* IA32_MISC_PACKAGE_CTLS */ ENERGY_FILTERING_CTL_SUP: 12-11, /* ENERGY_FILTERING_CTL */ DOITM_UARCH_MISC_CTRL : 13-12, SBDR_SSDP_NO : 14-13, FBSDP_NO : 15-14, PSDP_NO : 16-15, - ReservedBits2 : 17-16, + ReservedBits1 : 17-16, FB_CLEAR : 18-17, FB_CLEAR_CTRL : 19-18, /* IA32_MCU_OPT_CTRL[3] */ RRSBA : 20-19, BHI_NO : 21-20, XAPIC_DISABLE_STATUS_MSR: 22-21, /* xAPIC disable status */ - ReservedBits3 : 23-22, - OVERCLOCKING_STATUS_SUP : 24-23, /* IA32_OVERLOCKING_STATUS */ + ReservedBits2 : 23-22, + OVERCLOCKING_STATUS_MSR : 24-23, /* IA32_OVERLOCKING_STATUS */ PBRSB_NO : 25-24, - ReservedBits4 : 64-25; + ReservedBits3 : 64-25; }; } ARCH_CAPABILITIES; @@ -633,8 +657,8 @@ typedef union { unsigned long long OC_Utilized : 1-0, /* 1:OC have been enabled */ - Undervolt : 2-1, /* 1:Dynamic OC Undervolt Protection*/ - OC_Unlock : 3-2, /* 1:OC unlocked by BIOS */ + OC_Undervolt : 2-1, /* 1:Dynamic OC Undervolt Protection*/ + OC_Unlocked : 3-2, /* 1:OC unlocked by BIOS */ ReservedBits : 64-3; }; } OVERCLOCKING_STATUS; @@ -743,9 +767,11 @@ typedef union L2_HW_CL_Prefetch : 2-1, /* NHM, SNB */ L1_HW_Prefetch : 3-2, /* Avoton, Goldmont, NHM, SNB*/ L1_HW_IP_Prefetch : 4-3, /* NHM, SNB */ - ReservedBits1 : 11-4, + L1_NPP_Prefetch : 5-4, /* DCU Next Page Prefetcher */ + L2_AMP_Prefetch : 6-5, /* 12th, 13th Gen; Xeon 4th */ + ReservedBits2 : 11-6, DISABLE_THREE_STRIKE_CNT: 12-11, /* Errata [ADL021] */ - ReservedBits2 : 64-12; + ReservedBits3 : 64-12; }; struct { @@ -756,6 +782,95 @@ typedef union } Phi; } MISC_FEATURE_CONTROL; +typedef union +{ /* MSR_ATOM_L2_PREFETCH(0x00001320): Atom E-Core only */ + unsigned long long value; + struct { + unsigned long long + L2_STREAM_AMP_XQ_THRESHOLD : 5-0, + pad0 : 20-5, + L2_STREAM_MAX_DISTANCE : 25-20, + pad1 : 30-25, + L2_AMP_DISABLE_RECURSION : 31-30, + pad2 : 37-31, + LLC_STREAM_MAX_DISTANCE : 43-37, + LLC_STREAM_DISABLE : 44-43, + pad3 : 58-44, + LLC_STREAM_XQ_THRESHOLD : 63-58, + pad4 : 64-63; + }; +} ATOM_L2_PREFETCH_0X1320; + +typedef union +{ /* MSR_ATOM_L2_PREFETCH(0x00001321): Atom E-Core only */ + unsigned long long value; + struct { + unsigned long long + L2_STREAM_AMP_CREATE_IL1 : 1-0, + pad0 : 21-1, + L2_STREAM_DEMAND_DENSITY : 29-21, + L2_STREAM_DEMAND_DENSITY_OVR : 33-29, + pad1 : 40-33, + L2_DISABLE_NEXT_LINE_PREFETCH : 41-40, + L2_LLC_STREAM_AMP_XQ_THRESHOLD : 47-41, + pad2 : 64-47; + }; +} ATOM_L2_PREFETCH_0X1321; + +typedef union +{ /* MSR_ATOM_L2_PREFETCH(0x00001322): Atom E-Core only */ + unsigned long long value; + struct { + unsigned long long + pad0 : 14-0, + LLC_STREAM_DEMAND_DENSITY : 23-14, + LLC_STREAM_DEMAND_DENSITY_OVR : 27-23, + L2_AMP_CONFIDENCE_DPT0 : 33-27, + L2_AMP_CONFIDENCE_DPT1 : 39-33, + L2_AMP_CONFIDENCE_DPT2 : 45-39, + L2_AMP_CONFIDENCE_DPT3 : 51-45, + pad1 : 59-51, + L2_LLC_STREAM_DEMAND_DENSITY_XQ : 62-59, + pad2 : 64-62; + }; +} ATOM_L2_PREFETCH_0X1322; + +typedef union +{ /* MSR_ATOM_L2_PREFETCH(0x00001323): Atom E-Core only */ + unsigned long long value; + struct { + unsigned long long + pad0 : 34-0, + L2_STREAM_AMP_CREATE_SWPFRFO : 35-34, + L2_STREAM_AMP_CREATE_SWPFRD : 36-35, + pad1 : 37-36, + L2_STREAM_AMP_CREATE_HWPFD : 38-37, + L2_STREAM_AMP_CREATE_DRFO : 39-38, + STABILIZE_PREF_ON_SWPFRFO : 40-39, + STABILIZE_PREF_ON_SWPFRD : 41-40, + STABILIZE_PREF_ON_IL1 : 42-41, + pad2 : 43-42, + STABILIZE_PREF_ON_HWPFD : 44-43, + STABILIZE_PREF_ON_DRFO : 45-44, + L2_STREAM_AMP_CREATE_PFNPP : 46-45, + L2_STREAM_AMP_CREATE_PFIPP : 47-46, + STABILIZE_PREF_ON_PFNPP : 48-47, + STABILIZE_PREF_ON_PFIPP : 49-48, + pad3 : 64-48; + }; +} ATOM_L2_PREFETCH_0X1323; + +typedef union +{ /* MSR_ATOM_L2_PREFETCH(0x00001324): Atom E-Core only */ + unsigned long long value; + struct { + unsigned long long + pad0 : 54-0, + L1_HOMELESS_THRESHOLD : 62-54, + pad1 : 64-62; + }; +} ATOM_L2_PREFETCH_0X1324; + typedef union { unsigned long long value; @@ -1074,6 +1189,23 @@ typedef union }; } MISC_PROC_FEATURES; +typedef union +{ /* IA32_FRED_CONFIG (MSR index 1D4H). */ + unsigned long long value; + struct + { + unsigned long long int + CSL : 2-0, + ReservedBits1 : 3-2, + SSP : 4-3, + ReservedBits2 : 6-4, + RSP : 9-6, + RING0 : 11-9, + ReservedBits3 : 12-11, + LAP : 64-12; + }; +} FRED_CONFIG; + typedef union { unsigned long long value; @@ -1846,7 +1978,7 @@ typedef struct ReservedBits2 : 64-12; } MTRR_DEF_TYPE; - §18.2.4 PM4 + Chap. 18.2.4 PM4 IA32_PERF_GLOBAL_STATUS_RESET IA32_PERF_GLOBAL_STATUS_SET @@ -1868,6 +2000,16 @@ typedef union }; } VMX_BASIC; +typedef union +{ /* MSR_CORE_UARCH_CTL(0x541): R/W, SMT, P-Core only */ + unsigned long long value; + struct { + unsigned long long /* 10th, 12th, 13th generations */ + L1_Scrubbing_En : 1-0, + ReservedBits : 64-1; + }; +} CORE_UARCH_CTL; + typedef union { unsigned int value; @@ -3413,7 +3555,7 @@ typedef union ReservedBits2 : 23-15, VT_d : 24-23, /* VT-d: 0=Enable, 1=Disable */ ReservedBits3 : 32-24; - }; /* §2.5.33 CAPID0_A Capabilities A Register */ + }; /* Chap. 2.5.33 CAPID0_A Capabilities A Register */ struct { unsigned int DDR3L_EN : 1-0, /* DDR3L (1.35V) operation allowed */ @@ -3631,7 +3773,7 @@ typedef union SMTCAP : 29-28, /* SMT Capability */ ReservedBits5 : 32-29; }; -} IVB_CAPID_B; /* §2.5.39 CAPID0_B Capabilities B Register */ +} IVB_CAPID_B; /* Chap. 2.5.39 CAPID0_B Capabilities B Register */ typedef union { /* Device: 0 - Function: 0 - Offset Channel0: 4C00h */ @@ -4577,7 +4719,7 @@ typedef union ReservedBits3 : 25-24, ECCDIS : 26-25, /* 0:ECC capable, 1:Not ECC capable */ ReservedBits4 : 32-26; - }; /* §3.39 CAPID0_A Capabilities A Register */ + }; /* Chap. 3.39 CAPID0_A Capabilities A Register */ } SKL_CAPID_A; typedef union @@ -4611,7 +4753,7 @@ typedef union PEG11D : 30-29, PEG12D : 31-30, NVME_FOD : 32-31; /* 1: Disable NVMe at Dev 3 Func 0 */ - }; /* RKL: §3.1.38 ; TGL: $3.1.40 */ + }; /* RKL: Chap. 3.1.38 ; TGL: $3.1.40 */ } RKL_CAPID_A; #define TGL_CAPID_A RKL_CAPID_A @@ -4678,7 +4820,7 @@ typedef union SMTCAP : 29-28, ReservedBits8 : 31-29, IMGU_DIS : 32-31; /* Device 5 associated memory spaces */ - }; /* §3.40 CAPID0_B Capabilities B Register */ + }; /* Chap. 3.40 CAPID0_B Capabilities B Register */ } SKL_CAPID_B; typedef union @@ -4710,7 +4852,7 @@ typedef union OC_ENABLED : 30-29, /* 0: Overclocking is disabled */ TRACE_HUB_DIS : 31-30, /* Trace Hub & I/O are disabled */ IMGU_DIS : 32-31; /* Device 5 associated memory spaces */ - }; /* RKL: §3.1.39 ; TGL: $3.1.41 */ + }; /* RKL: Chap. 3.1.39 ; TGL: $3.1.41 */ } RKL_CAPID_B; #define TGL_CAPID_B RKL_CAPID_B @@ -4757,7 +4899,7 @@ typedef union DMFC_LPDDR3 : 17-14, DMFC_DDR4 : 20-17, ReservedBits2 : 32-20; - }; /* §3.41 CAPID0_C Capabilities C Register */ + }; /* Chap. 3.41 CAPID0_C Capabilities C Register */ } SKL_CAPID_C; typedef union @@ -4779,7 +4921,7 @@ typedef union DATA_RATE_DDR4 : 28-23, /* mult of 266 MHz iff DDR_OVERCLOCK */ PEGG4_DIS : 29-28, ReservedBits2 : 32-29; - }; /* RKL: §3.1.40 ; TGL: $3.1.42 */ + }; /* RKL: Chap. 3.1.40 ; TGL: $3.1.42 */ } RKL_CAPID_C; #define TGL_CAPID_C RKL_CAPID_C