Designing chips has become pay-to-win—OpenChips is an open source project that aims to change that. We design, verify, and publish Verilog modules, free for all to use. The OpenChips repository has extensive SystemVerilog 2007 support, and all OpenChips modules have undergone basic synthesis and parameterization. Every module provided under the OpenChips repository is a free software licensed under the ISC license (a GPL compatible license that is similar in terms to the MIT license or the 2-clause BSD license).
Please check out Contributing.md!
We use SemVer for versioning. For the versions available, see the tags on this repository.