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cpr3-regulator.c
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cpr3-regulator.c
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/*
* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define pr_fmt(fmt) "%s: " fmt, __func__
#include <linux/bitops.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/ktime.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_opp.h>
#include <linux/slab.h>
#include <linux/sort.h>
#include <linux/string.h>
#include <linux/uaccess.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/of_regulator.h>
#include <linux/regulator/msm-ldo-regulator.h>
#include <soc/qcom/spm.h>
#include "cpr3-regulator.h"
#define CPR3_REGULATOR_CORNER_INVALID (-1)
#define CPR3_RO_MASK GENMASK(CPR3_RO_COUNT - 1, 0)
/* CPR3 registers */
#define CPR3_REG_CPR_CTL 0x4
#define CPR3_CPR_CTL_LOOP_EN_MASK BIT(0)
#define CPR3_CPR_CTL_LOOP_ENABLE BIT(0)
#define CPR3_CPR_CTL_LOOP_DISABLE 0
#define CPR3_CPR_CTL_IDLE_CLOCKS_MASK GENMASK(5, 1)
#define CPR3_CPR_CTL_IDLE_CLOCKS_SHIFT 1
#define CPR3_CPR_CTL_COUNT_MODE_MASK GENMASK(7, 6)
#define CPR3_CPR_CTL_COUNT_MODE_SHIFT 6
#define CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_MIN 0
#define CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_MAX 1
#define CPR3_CPR_CTL_COUNT_MODE_STAGGERED 2
#define CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_AGE 3
#define CPR3_CPR_CTL_COUNT_REPEAT_MASK GENMASK(31, 9)
#define CPR3_CPR_CTL_COUNT_REPEAT_SHIFT 9
#define CPR3_REG_CPR_STATUS 0x8
#define CPR3_CPR_STATUS_BUSY_MASK BIT(0)
#define CPR3_CPR_STATUS_AGING_MEASUREMENT_MASK BIT(1)
/*
* This register is not present on controllers that support HW closed-loop
* except CPR4 APSS controller.
*/
#define CPR3_REG_CPR_TIMER_AUTO_CONT 0xC
#define CPR3_REG_CPR_STEP_QUOT 0x14
#define CPR3_CPR_STEP_QUOT_MIN_MASK GENMASK(5, 0)
#define CPR3_CPR_STEP_QUOT_MIN_SHIFT 0
#define CPR3_CPR_STEP_QUOT_MAX_MASK GENMASK(11, 6)
#define CPR3_CPR_STEP_QUOT_MAX_SHIFT 6
#define CPR3_REG_GCNT(ro) (0xA0 + 0x4 * (ro))
#define CPR3_REG_SENSOR_BYPASS_WRITE(sensor) (0xE0 + 0x4 * ((sensor) / 32))
#define CPR3_REG_SENSOR_BYPASS_WRITE_BANK(bank) (0xE0 + 0x4 * (bank))
#define CPR3_REG_SENSOR_MASK_WRITE(sensor) (0x120 + 0x4 * ((sensor) / 32))
#define CPR3_REG_SENSOR_MASK_WRITE_BANK(bank) (0x120 + 0x4 * (bank))
#define CPR3_REG_SENSOR_MASK_READ(sensor) (0x140 + 0x4 * ((sensor) / 32))
#define CPR3_REG_SENSOR_OWNER(sensor) (0x200 + 0x4 * (sensor))
#define CPR3_REG_CONT_CMD 0x800
#define CPR3_CONT_CMD_ACK 0x1
#define CPR3_CONT_CMD_NACK 0x0
#define CPR3_REG_THRESH(thread) (0x808 + 0x440 * (thread))
#define CPR3_THRESH_CONS_DOWN_MASK GENMASK(3, 0)
#define CPR3_THRESH_CONS_DOWN_SHIFT 0
#define CPR3_THRESH_CONS_UP_MASK GENMASK(7, 4)
#define CPR3_THRESH_CONS_UP_SHIFT 4
#define CPR3_THRESH_DOWN_THRESH_MASK GENMASK(12, 8)
#define CPR3_THRESH_DOWN_THRESH_SHIFT 8
#define CPR3_THRESH_UP_THRESH_MASK GENMASK(17, 13)
#define CPR3_THRESH_UP_THRESH_SHIFT 13
#define CPR3_REG_RO_MASK(thread) (0x80C + 0x440 * (thread))
#define CPR3_REG_RESULT0(thread) (0x810 + 0x440 * (thread))
#define CPR3_RESULT0_BUSY_MASK BIT(0)
#define CPR3_RESULT0_STEP_DN_MASK BIT(1)
#define CPR3_RESULT0_STEP_UP_MASK BIT(2)
#define CPR3_RESULT0_ERROR_STEPS_MASK GENMASK(7, 3)
#define CPR3_RESULT0_ERROR_STEPS_SHIFT 3
#define CPR3_RESULT0_ERROR_MASK GENMASK(19, 8)
#define CPR3_RESULT0_ERROR_SHIFT 8
#define CPR3_RESULT0_NEGATIVE_MASK BIT(20)
#define CPR3_REG_RESULT1(thread) (0x814 + 0x440 * (thread))
#define CPR3_RESULT1_QUOT_MIN_MASK GENMASK(11, 0)
#define CPR3_RESULT1_QUOT_MIN_SHIFT 0
#define CPR3_RESULT1_QUOT_MAX_MASK GENMASK(23, 12)
#define CPR3_RESULT1_QUOT_MAX_SHIFT 12
#define CPR3_RESULT1_RO_MIN_MASK GENMASK(27, 24)
#define CPR3_RESULT1_RO_MIN_SHIFT 24
#define CPR3_RESULT1_RO_MAX_MASK GENMASK(31, 28)
#define CPR3_RESULT1_RO_MAX_SHIFT 28
#define CPR3_REG_RESULT2(thread) (0x818 + 0x440 * (thread))
#define CPR3_RESULT2_STEP_QUOT_MIN_MASK GENMASK(5, 0)
#define CPR3_RESULT2_STEP_QUOT_MIN_SHIFT 0
#define CPR3_RESULT2_STEP_QUOT_MAX_MASK GENMASK(11, 6)
#define CPR3_RESULT2_STEP_QUOT_MAX_SHIFT 6
#define CPR3_RESULT2_SENSOR_MIN_MASK GENMASK(23, 16)
#define CPR3_RESULT2_SENSOR_MIN_SHIFT 16
#define CPR3_RESULT2_SENSOR_MAX_MASK GENMASK(31, 24)
#define CPR3_RESULT2_SENSOR_MAX_SHIFT 24
#define CPR3_REG_IRQ_EN 0x81C
#define CPR3_REG_IRQ_CLEAR 0x820
#define CPR3_REG_IRQ_STATUS 0x824
#define CPR3_IRQ_UP BIT(3)
#define CPR3_IRQ_MID BIT(2)
#define CPR3_IRQ_DOWN BIT(1)
#define CPR3_REG_TARGET_QUOT(thread, ro) \
(0x840 + 0x440 * (thread) + 0x4 * (ro))
/* Registers found only on controllers that support HW closed-loop. */
#define CPR3_REG_PD_THROTTLE 0xE8
#define CPR3_PD_THROTTLE_DISABLE 0x0
#define CPR3_REG_HW_CLOSED_LOOP 0x3000
#define CPR3_HW_CLOSED_LOOP_ENABLE 0x0
#define CPR3_HW_CLOSED_LOOP_DISABLE 0x1
#define CPR3_REG_CPR_TIMER_MID_CONT 0x3004
#define CPR3_REG_CPR_TIMER_UP_DN_CONT 0x3008
#define CPR3_REG_LAST_MEASUREMENT 0x7F8
#define CPR3_LAST_MEASUREMENT_THREAD_DN_SHIFT 0
#define CPR3_LAST_MEASUREMENT_THREAD_UP_SHIFT 4
#define CPR3_LAST_MEASUREMENT_THREAD_DN(thread) \
(BIT(thread) << CPR3_LAST_MEASUREMENT_THREAD_DN_SHIFT)
#define CPR3_LAST_MEASUREMENT_THREAD_UP(thread) \
(BIT(thread) << CPR3_LAST_MEASUREMENT_THREAD_UP_SHIFT)
#define CPR3_LAST_MEASUREMENT_AGGR_DN BIT(8)
#define CPR3_LAST_MEASUREMENT_AGGR_MID BIT(9)
#define CPR3_LAST_MEASUREMENT_AGGR_UP BIT(10)
#define CPR3_LAST_MEASUREMENT_VALID BIT(11)
#define CPR3_LAST_MEASUREMENT_SAW_ERROR BIT(12)
#define CPR3_LAST_MEASUREMENT_PD_BYPASS_MASK GENMASK(23, 16)
#define CPR3_LAST_MEASUREMENT_PD_BYPASS_SHIFT 16
/* CPR4 controller specific registers and bit definitions */
#define CPR4_REG_CPR_TIMER_CLAMP 0x10
#define CPR4_CPR_TIMER_CLAMP_THREAD_AGGREGATION_EN BIT(27)
#define CPR4_REG_MISC 0x700
#define CPR4_MISC_RESET_STEP_QUOT_LOOP_EN BIT(2)
#define CPR4_MISC_MARGIN_TABLE_ROW_SELECT_MASK GENMASK(23, 20)
#define CPR4_MISC_MARGIN_TABLE_ROW_SELECT_SHIFT 20
#define CPR4_MISC_TEMP_SENSOR_ID_START_MASK GENMASK(27, 24)
#define CPR4_MISC_TEMP_SENSOR_ID_START_SHIFT 24
#define CPR4_MISC_TEMP_SENSOR_ID_END_MASK GENMASK(31, 28)
#define CPR4_MISC_TEMP_SENSOR_ID_END_SHIFT 28
#define CPR4_REG_SAW_ERROR_STEP_LIMIT 0x7A4
#define CPR4_SAW_ERROR_STEP_LIMIT_UP_MASK GENMASK(4, 0)
#define CPR4_SAW_ERROR_STEP_LIMIT_UP_SHIFT 0
#define CPR4_SAW_ERROR_STEP_LIMIT_DN_MASK GENMASK(9, 5)
#define CPR4_SAW_ERROR_STEP_LIMIT_DN_SHIFT 5
#define CPR4_REG_MARGIN_TEMP_CORE_TIMERS 0x7A8
#define CPR4_MARGIN_TEMP_CORE_TIMERS_SETTLE_VOLTAGE_COUNT_MASK GENMASK(28, 18)
#define CPR4_MARGIN_TEMP_CORE_TIMERS_SETTLE_VOLTAGE_COUNT_SHIFT 18
#define CPR4_REG_MARGIN_TEMP_CORE(core) (0x7AC + 0x4 * (core))
#define CPR4_MARGIN_TEMP_CORE_ADJ_MASK GENMASK(7, 0)
#define CPR4_MARGIN_TEMP_CORE_ADJ_SHIFT 8
#define CPR4_REG_MARGIN_TEMP_POINT0N1 0x7F0
#define CPR4_MARGIN_TEMP_POINT0_MASK GENMASK(11, 0)
#define CPR4_MARGIN_TEMP_POINT0_SHIFT 0
#define CPR4_MARGIN_TEMP_POINT1_MASK GENMASK(23, 12)
#define CPR4_MARGIN_TEMP_POINT1_SHIFT 12
#define CPR4_REG_MARGIN_TEMP_POINT2 0x7F4
#define CPR4_MARGIN_TEMP_POINT2_MASK GENMASK(11, 0)
#define CPR4_MARGIN_TEMP_POINT2_SHIFT 0
#define CPR4_REG_MARGIN_ADJ_CTL 0x7F8
#define CPR4_MARGIN_ADJ_CTL_BOOST_EN BIT(0)
#define CPR4_MARGIN_ADJ_CTL_CORE_ADJ_EN BIT(1)
#define CPR4_MARGIN_ADJ_CTL_TEMP_ADJ_EN BIT(2)
#define CPR4_MARGIN_ADJ_CTL_TIMER_SETTLE_VOLTAGE_EN BIT(3)
#define CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK BIT(4)
#define CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_ENABLE BIT(4)
#define CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_DISABLE 0
#define CPR4_MARGIN_ADJ_CTL_PER_RO_KV_MARGIN_EN BIT(7)
#define CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_EN BIT(8)
#define CPR4_MARGIN_ADJ_CTL_PMIC_STEP_SIZE_MASK GENMASK(16, 12)
#define CPR4_MARGIN_ADJ_CTL_PMIC_STEP_SIZE_SHIFT 12
#define CPR4_MARGIN_ADJ_CTL_INITIAL_TEMP_BAND_MASK GENMASK(21, 19)
#define CPR4_MARGIN_ADJ_CTL_INITIAL_TEMP_BAND_SHIFT 19
#define CPR4_MARGIN_ADJ_CTL_MAX_NUM_CORES_MASK GENMASK(25, 22)
#define CPR4_MARGIN_ADJ_CTL_MAX_NUM_CORES_SHIFT 22
#define CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_STEP_QUOT_MASK GENMASK(31, 26)
#define CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_STEP_QUOT_SHIFT 26
#define CPR4_REG_CPR_MASK_THREAD(thread) (0x80C + 0x440 * (thread))
#define CPR4_CPR_MASK_THREAD_DISABLE_THREAD BIT(31)
#define CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK GENMASK(15, 0)
/* CPRh controller specific registers and bit definitions */
#define CPRH_REG_CORNER(corner) (0x3A00 + 0x4 * (corner))
#define CPRH_CORNER_INIT_VOLTAGE_MASK GENMASK(7, 0)
#define CPRH_CORNER_INIT_VOLTAGE_SHIFT 0
#define CPRH_CORNER_FLOOR_VOLTAGE_MASK GENMASK(15, 8)
#define CPRH_CORNER_FLOOR_VOLTAGE_SHIFT 8
#define CPRH_CORNER_QUOT_DELTA_MASK GENMASK(24, 16)
#define CPRH_CORNER_QUOT_DELTA_SHIFT 16
#define CPRH_CORNER_RO_SEL_MASK GENMASK(28, 25)
#define CPRH_CORNER_RO_SEL_SHIFT 25
#define CPRH_CORNER_CPR_CL_DISABLE BIT(29)
#define CPRH_CORNER_CORE_TEMP_MARGIN_DISABLE BIT(30)
#define CPRH_CORNER_LAST_KNOWN_VOLTAGE_ENABLE BIT(31)
#define CPRH_CORNER_INIT_VOLTAGE_MAX_VALUE 255
#define CPRH_CORNER_FLOOR_VOLTAGE_MAX_VALUE 255
#define CPRH_CORNER_QUOT_DELTA_MAX_VALUE 511
#define CPRH_REG_CTL 0x3AA0
#define CPRH_CTL_OSM_ENABLED BIT(0)
#define CPRH_CTL_BASE_VOLTAGE_MASK GENMASK(10, 1)
#define CPRH_CTL_BASE_VOLTAGE_SHIFT 1
#define CPRH_CTL_INIT_MODE_MASK GENMASK(16, 11)
#define CPRH_CTL_INIT_MODE_SHIFT 11
#define CPRH_CTL_MODE_SWITCH_DELAY_MASK GENMASK(24, 17)
#define CPRH_CTL_MODE_SWITCH_DELAY_SHIFT 17
#define CPRH_CTL_VOLTAGE_MULTIPLIER_MASK GENMASK(28, 25)
#define CPRH_CTL_VOLTAGE_MULTIPLIER_SHIFT 25
#define CPRH_CTL_LAST_KNOWN_VOLTAGE_MARGIN_MASK GENMASK(31, 29)
#define CPRH_CTL_LAST_KNOWN_VOLTAGE_MARGIN_SHIFT 29
#define CPRH_REG_STATUS 0x3AA4
#define CPRH_STATUS_CORNER GENMASK(5, 0)
#define CPRH_STATUS_CORNER_LAST_VOLT_MASK GENMASK(17, 6)
#define CPRH_STATUS_CORNER_LAST_VOLT_SHIFT 6
#define CPRH_REG_CORNER_BAND 0x3AA8
#define CPRH_CORNER_BAND_MASK GENMASK(5, 0)
#define CPRH_CORNER_BAND_SHIFT 6
#define CPRH_CORNER_BAND_MAX_COUNT 4
#define CPRH_MARGIN_TEMP_CORE_VBAND(core, vband) \
((vband) == 0 ? CPR4_REG_MARGIN_TEMP_CORE(core) \
: 0x3AB0 + 0x40 * ((vband) - 1) + 0x4 * (core))
/*
* The amount of time to wait for the CPR controller to become idle when
* performing an aging measurement.
*/
#define CPR3_AGING_MEASUREMENT_TIMEOUT_NS 5000000
/*
* The number of individual aging measurements to perform which are then
* averaged together in order to determine the final aging adjustment value.
*/
#define CPR3_AGING_MEASUREMENT_ITERATIONS 16
/*
* Aging measurements for the aged and unaged ring oscillators take place a few
* microseconds apart. If the vdd-supply voltage fluctuates between the two
* measurements, then the difference between them will be incorrect. The
* difference could end up too high or too low. This constant defines the
* number of lowest and highest measurements to ignore when averaging.
*/
#define CPR3_AGING_MEASUREMENT_FILTER 3
/*
* The number of times to attempt the full aging measurement sequence before
* declaring a measurement failure.
*/
#define CPR3_AGING_RETRY_COUNT 5
/*
* The maximum time to wait in microseconds for a CPR register write to
* complete.
*/
#define CPR3_REGISTER_WRITE_DELAY_US 200
/*
* The number of times the CPRh controller multiplies the mode switch
* delay before utilizing it.
*/
#define CPRH_MODE_SWITCH_DELAY_FACTOR 4
/*
* The number of times the CPRh controller multiplies the delta quotient
* steps before utilizing it.
*/
#define CPRH_DELTA_QUOT_STEP_FACTOR 4
/*
* The multiplier applied to scaling factor value used to derive GCNT
* for aging measurements.
*/
#define CPR3_AGING_GCNT_SCALING_UNITY 1000
static DEFINE_MUTEX(cpr3_controller_list_mutex);
static LIST_HEAD(cpr3_controller_list);
static struct dentry *cpr3_debugfs_base;
/**
* cpr3_read() - read four bytes from the memory address specified
* @ctrl: Pointer to the CPR3 controller
* @offset: Offset in bytes from the CPR3 controller's base address
*
* Return: memory address value
*/
static inline u32 cpr3_read(struct cpr3_controller *ctrl, u32 offset)
{
if (!ctrl->cpr_enabled) {
cpr3_err(ctrl, "CPR register reads are not possible when CPR clocks are disabled\n");
return 0;
}
return readl_relaxed(ctrl->cpr_ctrl_base + offset);
}
/**
* cpr3_write() - write four bytes to the memory address specified
* @ctrl: Pointer to the CPR3 controller
* @offset: Offset in bytes from the CPR3 controller's base address
* @value: Value to write to the memory address
*
* Return: none
*/
static inline void cpr3_write(struct cpr3_controller *ctrl, u32 offset,
u32 value)
{
if (!ctrl->cpr_enabled) {
cpr3_err(ctrl, "CPR register writes are not possible when CPR clocks are disabled\n");
return;
}
writel_relaxed(value, ctrl->cpr_ctrl_base + offset);
}
/**
* cpr3_masked_write() - perform a read-modify-write sequence so that only
* masked bits are modified
* @ctrl: Pointer to the CPR3 controller
* @offset: Offset in bytes from the CPR3 controller's base address
* @mask: Mask identifying the bits that should be modified
* @value: Value to write to the memory address
*
* Return: none
*/
static inline void cpr3_masked_write(struct cpr3_controller *ctrl, u32 offset,
u32 mask, u32 value)
{
u32 reg_val, orig_val;
if (!ctrl->cpr_enabled) {
cpr3_err(ctrl, "CPR register writes are not possible when CPR clocks are disabled\n");
return;
}
reg_val = orig_val = readl_relaxed(ctrl->cpr_ctrl_base + offset);
reg_val &= ~mask;
reg_val |= value & mask;
if (reg_val != orig_val)
writel_relaxed(reg_val, ctrl->cpr_ctrl_base + offset);
}
/**
* cpr3_ctrl_loop_enable() - enable the CPR sensing loop for a given controller
* @ctrl: Pointer to the CPR3 controller
*
* Return: none
*/
static inline void cpr3_ctrl_loop_enable(struct cpr3_controller *ctrl)
{
if (ctrl->cpr_enabled && !(ctrl->aggr_corner.sdelta
&& ctrl->aggr_corner.sdelta->allow_boost))
cpr3_masked_write(ctrl, CPR3_REG_CPR_CTL,
CPR3_CPR_CTL_LOOP_EN_MASK, CPR3_CPR_CTL_LOOP_ENABLE);
}
/**
* cpr3_ctrl_loop_disable() - disable the CPR sensing loop for a given
* controller
* @ctrl: Pointer to the CPR3 controller
*
* Return: none
*/
static inline void cpr3_ctrl_loop_disable(struct cpr3_controller *ctrl)
{
if (ctrl->cpr_enabled)
cpr3_masked_write(ctrl, CPR3_REG_CPR_CTL,
CPR3_CPR_CTL_LOOP_EN_MASK, CPR3_CPR_CTL_LOOP_DISABLE);
}
/**
* cpr3_clock_enable() - prepare and enable all clocks used by this CPR3
* controller
* @ctrl: Pointer to the CPR3 controller
*
* Return: 0 on success, errno on failure
*/
static int cpr3_clock_enable(struct cpr3_controller *ctrl)
{
int rc;
rc = clk_prepare_enable(ctrl->bus_clk);
if (rc) {
cpr3_err(ctrl, "failed to enable bus clock, rc=%d\n", rc);
return rc;
}
rc = clk_prepare_enable(ctrl->iface_clk);
if (rc) {
cpr3_err(ctrl, "failed to enable interface clock, rc=%d\n", rc);
clk_disable_unprepare(ctrl->bus_clk);
return rc;
}
rc = clk_prepare_enable(ctrl->core_clk);
if (rc) {
cpr3_err(ctrl, "failed to enable core clock, rc=%d\n", rc);
clk_disable_unprepare(ctrl->iface_clk);
clk_disable_unprepare(ctrl->bus_clk);
return rc;
}
return 0;
}
/**
* cpr3_clock_disable() - disable and unprepare all clocks used by this CPR3
* controller
* @ctrl: Pointer to the CPR3 controller
*
* Return: none
*/
static void cpr3_clock_disable(struct cpr3_controller *ctrl)
{
clk_disable_unprepare(ctrl->core_clk);
clk_disable_unprepare(ctrl->iface_clk);
clk_disable_unprepare(ctrl->bus_clk);
}
/**
* cpr3_ctrl_clear_cpr4_config() - clear the CPR4 register configuration
* programmed for current aggregated corner of a given controller
* @ctrl: Pointer to the CPR3 controller
*
* Return: 0 on success, errno on failure
*/
static inline int cpr3_ctrl_clear_cpr4_config(struct cpr3_controller *ctrl)
{
struct cpr4_sdelta *aggr_sdelta = ctrl->aggr_corner.sdelta;
bool cpr_enabled = ctrl->cpr_enabled;
int i, rc = 0;
if (!aggr_sdelta || !(aggr_sdelta->allow_core_count_adj
|| aggr_sdelta->allow_temp_adj || aggr_sdelta->allow_boost))
/* cpr4 features are not enabled */
return 0;
/* Ensure that CPR clocks are enabled before writing to registers. */
if (!cpr_enabled) {
rc = cpr3_clock_enable(ctrl);
if (rc) {
cpr3_err(ctrl, "clock enable failed, rc=%d\n", rc);
return rc;
}
ctrl->cpr_enabled = true;
}
/*
* Clear feature enable configuration made for current
* aggregated corner.
*/
cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL,
CPR4_MARGIN_ADJ_CTL_MAX_NUM_CORES_MASK
| CPR4_MARGIN_ADJ_CTL_CORE_ADJ_EN
| CPR4_MARGIN_ADJ_CTL_TEMP_ADJ_EN
| CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_EN
| CPR4_MARGIN_ADJ_CTL_BOOST_EN
| CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK, 0);
cpr3_masked_write(ctrl, CPR4_REG_MISC,
CPR4_MISC_MARGIN_TABLE_ROW_SELECT_MASK,
0 << CPR4_MISC_MARGIN_TABLE_ROW_SELECT_SHIFT);
for (i = 0; i <= aggr_sdelta->max_core_count; i++) {
/* Clear voltage margin adjustments programmed in TEMP_COREi */
cpr3_write(ctrl, CPR4_REG_MARGIN_TEMP_CORE(i), 0);
}
/* Turn off CPR clocks if they were off before this function call. */
if (!cpr_enabled) {
cpr3_clock_disable(ctrl);
ctrl->cpr_enabled = false;
}
return 0;
}
/**
* cpr3_closed_loop_enable() - enable logical CPR closed-loop operation
* @ctrl: Pointer to the CPR3 controller
*
* Return: 0 on success, errno on failure
*/
static int cpr3_closed_loop_enable(struct cpr3_controller *ctrl)
{
int rc;
if (!ctrl->cpr_allowed_hw || !ctrl->cpr_allowed_sw) {
cpr3_err(ctrl, "cannot enable closed-loop CPR operation because it is disallowed\n");
return -EPERM;
} else if (ctrl->cpr_enabled) {
/* Already enabled */
return 0;
} else if (ctrl->cpr_suspended) {
/*
* CPR must remain disabled as the system is entering suspend.
*/
return 0;
}
rc = cpr3_clock_enable(ctrl);
if (rc) {
cpr3_err(ctrl, "unable to enable CPR clocks, rc=%d\n", rc);
return rc;
}
ctrl->cpr_enabled = true;
cpr3_debug(ctrl, "CPR closed-loop operation enabled\n");
return 0;
}
/**
* cpr3_closed_loop_disable() - disable logical CPR closed-loop operation
* @ctrl: Pointer to the CPR3 controller
*
* Return: 0 on success, errno on failure
*/
static inline int cpr3_closed_loop_disable(struct cpr3_controller *ctrl)
{
if (!ctrl->cpr_enabled) {
/* Already disabled */
return 0;
}
cpr3_clock_disable(ctrl);
ctrl->cpr_enabled = false;
cpr3_debug(ctrl, "CPR closed-loop operation disabled\n");
return 0;
}
/**
* cpr3_regulator_get_gcnt() - returns the GCNT register value corresponding
* to the clock rate and sensor time of the CPR3 controller
* @ctrl: Pointer to the CPR3 controller
*
* Return: GCNT value
*/
static u32 cpr3_regulator_get_gcnt(struct cpr3_controller *ctrl)
{
u64 temp;
unsigned int remainder;
u32 gcnt;
temp = (u64)ctrl->cpr_clock_rate * (u64)ctrl->sensor_time;
remainder = do_div(temp, 1000000000);
if (remainder)
temp++;
/*
* GCNT == 0 corresponds to a single ref clock measurement interval so
* offset GCNT values by 1.
*/
gcnt = temp - 1;
return gcnt;
}
/**
* cpr3_regulator_init_thread() - performs hardware initialization of CPR
* thread registers
* @thread: Pointer to the CPR3 thread
*
* CPR interface/bus clocks must be enabled before calling this function.
*
* Return: 0 on success, errno on failure
*/
static int cpr3_regulator_init_thread(struct cpr3_thread *thread)
{
u32 reg;
reg = (thread->consecutive_up << CPR3_THRESH_CONS_UP_SHIFT)
& CPR3_THRESH_CONS_UP_MASK;
reg |= (thread->consecutive_down << CPR3_THRESH_CONS_DOWN_SHIFT)
& CPR3_THRESH_CONS_DOWN_MASK;
reg |= (thread->up_threshold << CPR3_THRESH_UP_THRESH_SHIFT)
& CPR3_THRESH_UP_THRESH_MASK;
reg |= (thread->down_threshold << CPR3_THRESH_DOWN_THRESH_SHIFT)
& CPR3_THRESH_DOWN_THRESH_MASK;
cpr3_write(thread->ctrl, CPR3_REG_THRESH(thread->thread_id), reg);
/*
* Mask all RO's initially so that unused thread doesn't contribute
* to closed-loop voltage.
*/
cpr3_write(thread->ctrl, CPR3_REG_RO_MASK(thread->thread_id),
CPR3_RO_MASK);
return 0;
}
/**
* cpr4_regulator_init_temp_points() - performs hardware initialization of CPR4
* registers to track tsen temperature data and also specify the
* temperature band range values to apply different voltage margins
* @ctrl: Pointer to the CPR3 controller
*
* CPR interface/bus clocks must be enabled before calling this function.
*
* Return: 0 on success, errno on failure
*/
static int cpr4_regulator_init_temp_points(struct cpr3_controller *ctrl)
{
if (!ctrl->allow_temp_adj)
return 0;
cpr3_masked_write(ctrl, CPR4_REG_MISC,
CPR4_MISC_TEMP_SENSOR_ID_START_MASK,
ctrl->temp_sensor_id_start
<< CPR4_MISC_TEMP_SENSOR_ID_START_SHIFT);
cpr3_masked_write(ctrl, CPR4_REG_MISC,
CPR4_MISC_TEMP_SENSOR_ID_END_MASK,
ctrl->temp_sensor_id_end
<< CPR4_MISC_TEMP_SENSOR_ID_END_SHIFT);
cpr3_masked_write(ctrl, CPR4_REG_MARGIN_TEMP_POINT2,
CPR4_MARGIN_TEMP_POINT2_MASK,
(ctrl->temp_band_count == 4 ? ctrl->temp_points[2] : 0x7FF)
<< CPR4_MARGIN_TEMP_POINT2_SHIFT);
cpr3_masked_write(ctrl, CPR4_REG_MARGIN_TEMP_POINT0N1,
CPR4_MARGIN_TEMP_POINT1_MASK,
(ctrl->temp_band_count >= 3 ? ctrl->temp_points[1] : 0x7FF)
<< CPR4_MARGIN_TEMP_POINT1_SHIFT);
cpr3_masked_write(ctrl, CPR4_REG_MARGIN_TEMP_POINT0N1,
CPR4_MARGIN_TEMP_POINT0_MASK,
(ctrl->temp_band_count >= 2 ? ctrl->temp_points[0] : 0x7FF)
<< CPR4_MARGIN_TEMP_POINT0_SHIFT);
return 0;
}
/**
* cpr3_regulator_init_cpr4() - performs hardware initialization at the
* controller and thread level required for CPR4 operation.
* @ctrl: Pointer to the CPR3 controller
*
* CPR interface/bus clocks must be enabled before calling this function.
* This function allocates sdelta structures and sdelta tables for aggregated
* corners of the controller and its threads.
*
* Return: 0 on success, errno on failure
*/
static int cpr3_regulator_init_cpr4(struct cpr3_controller *ctrl)
{
struct cpr3_thread *thread;
struct cpr3_regulator *vreg;
struct cpr4_sdelta *sdelta;
int i, j, ctrl_max_core_count, thread_max_core_count, rc = 0;
bool ctrl_valid_sdelta, thread_valid_sdelta;
u32 pmic_step_size = 1;
int thread_id = 0;
u64 temp;
if (ctrl->reset_step_quot_loop_en)
cpr3_masked_write(ctrl, CPR4_REG_MISC,
CPR4_MISC_RESET_STEP_QUOT_LOOP_EN,
CPR4_MISC_RESET_STEP_QUOT_LOOP_EN);
if (ctrl->supports_hw_closed_loop) {
if (ctrl->saw_use_unit_mV)
pmic_step_size = ctrl->step_volt / 1000;
cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL,
CPR4_MARGIN_ADJ_CTL_PMIC_STEP_SIZE_MASK,
(pmic_step_size
<< CPR4_MARGIN_ADJ_CTL_PMIC_STEP_SIZE_SHIFT));
cpr3_masked_write(ctrl, CPR4_REG_SAW_ERROR_STEP_LIMIT,
CPR4_SAW_ERROR_STEP_LIMIT_DN_MASK,
(ctrl->down_error_step_limit
<< CPR4_SAW_ERROR_STEP_LIMIT_DN_SHIFT));
cpr3_masked_write(ctrl, CPR4_REG_SAW_ERROR_STEP_LIMIT,
CPR4_SAW_ERROR_STEP_LIMIT_UP_MASK,
(ctrl->up_error_step_limit
<< CPR4_SAW_ERROR_STEP_LIMIT_UP_SHIFT));
/*
* Enable thread aggregation regardless of which threads are
* enabled or disabled.
*/
cpr3_masked_write(ctrl, CPR4_REG_CPR_TIMER_CLAMP,
CPR4_CPR_TIMER_CLAMP_THREAD_AGGREGATION_EN,
CPR4_CPR_TIMER_CLAMP_THREAD_AGGREGATION_EN);
switch (ctrl->thread_count) {
case 0:
/* Disable both threads */
cpr3_masked_write(ctrl, CPR4_REG_CPR_MASK_THREAD(0),
CPR4_CPR_MASK_THREAD_DISABLE_THREAD
| CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK,
CPR4_CPR_MASK_THREAD_DISABLE_THREAD
| CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK);
cpr3_masked_write(ctrl, CPR4_REG_CPR_MASK_THREAD(1),
CPR4_CPR_MASK_THREAD_DISABLE_THREAD
| CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK,
CPR4_CPR_MASK_THREAD_DISABLE_THREAD
| CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK);
break;
case 1:
/* Disable unused thread */
thread_id = ctrl->thread[0].thread_id ? 0 : 1;
cpr3_masked_write(ctrl,
CPR4_REG_CPR_MASK_THREAD(thread_id),
CPR4_CPR_MASK_THREAD_DISABLE_THREAD
| CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK,
CPR4_CPR_MASK_THREAD_DISABLE_THREAD
| CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK);
break;
}
}
if (!ctrl->allow_core_count_adj && !ctrl->allow_temp_adj
&& !ctrl->allow_boost) {
/*
* Skip below configuration as none of the features
* are enabled.
*/
return rc;
}
if (ctrl->supports_hw_closed_loop)
cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL,
CPR4_MARGIN_ADJ_CTL_TIMER_SETTLE_VOLTAGE_EN,
CPR4_MARGIN_ADJ_CTL_TIMER_SETTLE_VOLTAGE_EN);
cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL,
CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_STEP_QUOT_MASK,
ctrl->step_quot_fixed
<< CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_STEP_QUOT_SHIFT);
cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL,
CPR4_MARGIN_ADJ_CTL_PER_RO_KV_MARGIN_EN,
(ctrl->use_dynamic_step_quot
? CPR4_MARGIN_ADJ_CTL_PER_RO_KV_MARGIN_EN : 0));
cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL,
CPR4_MARGIN_ADJ_CTL_INITIAL_TEMP_BAND_MASK,
ctrl->initial_temp_band
<< CPR4_MARGIN_ADJ_CTL_INITIAL_TEMP_BAND_SHIFT);
rc = cpr4_regulator_init_temp_points(ctrl);
if (rc) {
cpr3_err(ctrl, "initialize temp points failed, rc=%d\n", rc);
return rc;
}
if (ctrl->voltage_settling_time) {
/*
* Configure the settling timer used to account for
* one VDD supply step.
*/
temp = (u64)ctrl->cpr_clock_rate
* (u64)ctrl->voltage_settling_time;
do_div(temp, 1000000000);
cpr3_masked_write(ctrl, CPR4_REG_MARGIN_TEMP_CORE_TIMERS,
CPR4_MARGIN_TEMP_CORE_TIMERS_SETTLE_VOLTAGE_COUNT_MASK,
temp
<< CPR4_MARGIN_TEMP_CORE_TIMERS_SETTLE_VOLTAGE_COUNT_SHIFT);
}
/*
* Allocate memory for cpr4_sdelta structure and sdelta table for
* controller aggregated corner by finding the maximum core count
* used by any cpr3 regulators.
*/
ctrl_max_core_count = 1;
ctrl_valid_sdelta = false;
for (i = 0; i < ctrl->thread_count; i++) {
thread = &ctrl->thread[i];
/*
* Allocate memory for cpr4_sdelta structure and sdelta table
* for thread aggregated corner by finding the maximum core
* count used by any cpr3 regulators of the thread.
*/
thread_max_core_count = 1;
thread_valid_sdelta = false;
for (j = 0; j < thread->vreg_count; j++) {
vreg = &thread->vreg[j];
thread_max_core_count = max(thread_max_core_count,
vreg->max_core_count);
thread_valid_sdelta |= (vreg->allow_core_count_adj
| vreg->allow_temp_adj
| vreg->allow_boost);
}
if (thread_valid_sdelta) {
sdelta = devm_kzalloc(ctrl->dev, sizeof(*sdelta),
GFP_KERNEL);
if (!sdelta)
return -ENOMEM;
sdelta->table = devm_kcalloc(ctrl->dev,
thread_max_core_count
* ctrl->temp_band_count,
sizeof(*sdelta->table),
GFP_KERNEL);
if (!sdelta->table)
return -ENOMEM;
sdelta->boost_table = devm_kcalloc(ctrl->dev,
ctrl->temp_band_count,
sizeof(*sdelta->boost_table),
GFP_KERNEL);
if (!sdelta->boost_table)
return -ENOMEM;
thread->aggr_corner.sdelta = sdelta;
}
ctrl_valid_sdelta |= thread_valid_sdelta;
ctrl_max_core_count = max(ctrl_max_core_count,
thread_max_core_count);
}
if (ctrl_valid_sdelta) {
sdelta = devm_kzalloc(ctrl->dev, sizeof(*sdelta), GFP_KERNEL);
if (!sdelta)
return -ENOMEM;
sdelta->table = devm_kcalloc(ctrl->dev, ctrl_max_core_count
* ctrl->temp_band_count,
sizeof(*sdelta->table), GFP_KERNEL);
if (!sdelta->table)
return -ENOMEM;
sdelta->boost_table = devm_kcalloc(ctrl->dev,
ctrl->temp_band_count,
sizeof(*sdelta->boost_table),
GFP_KERNEL);
if (!sdelta->boost_table)
return -ENOMEM;
ctrl->aggr_corner.sdelta = sdelta;
}
return 0;
}
/**
* cpr3_write_temp_core_margin() - programs hardware SDELTA registers with
* the voltage margin adjustments that need to be applied for
* different online core-count and temperature bands.
* @ctrl: Pointer to the CPR3 controller
* @addr: SDELTA register address
* @temp_core_adj: Array of voltage margin values for different temperature
* bands.
*
* CPR interface/bus clocks must be enabled before calling this function.
*
* Return: none
*/
static void cpr3_write_temp_core_margin(struct cpr3_controller *ctrl,
int addr, int *temp_core_adj)
{
int i, margin_steps;
u32 reg = 0;
for (i = 0; i < ctrl->temp_band_count; i++) {
margin_steps = max(min(temp_core_adj[i], 127), -128);
reg |= (margin_steps & CPR4_MARGIN_TEMP_CORE_ADJ_MASK) <<
(i * CPR4_MARGIN_TEMP_CORE_ADJ_SHIFT);
}
cpr3_write(ctrl, addr, reg);
cpr3_debug(ctrl, "sdelta offset=0x%08x, val=0x%08x\n", addr, reg);
}
/**
* cpr3_controller_program_sdelta() - programs hardware SDELTA registers with
* the voltage margin adjustments that need to be applied at
* different online core-count and temperature bands. Also,
* programs hardware register configuration for per-online-core
* and per-temperature based adjustments.
* @ctrl: Pointer to the CPR3 controller
*
* CPR interface/bus clocks must be enabled before calling this function.
*
* Return: 0 on success, errno on failure
*/
static int cpr3_controller_program_sdelta(struct cpr3_controller *ctrl)
{
struct cpr3_corner *corner = &ctrl->aggr_corner;
struct cpr4_sdelta *sdelta = corner->sdelta;
int i, index, max_core_count, rc = 0;
bool cpr_enabled = ctrl->cpr_enabled;
if (!sdelta)
/* cpr4_sdelta not defined for current aggregated corner */
return 0;
if (ctrl->supports_hw_closed_loop && ctrl->cpr_enabled) {
cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL,
CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK,
(ctrl->use_hw_closed_loop && !sdelta->allow_boost)
? CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_ENABLE : 0);
}
if (!sdelta->allow_core_count_adj && !sdelta->allow_temp_adj
&& !sdelta->allow_boost) {
/*
* Per-online-core, per-temperature and voltage boost
* adjustments are disabled for this aggregation corner.
*/
return 0;
}
/* Ensure that CPR clocks are enabled before writing to registers. */
if (!cpr_enabled) {
rc = cpr3_clock_enable(ctrl);
if (rc) {
cpr3_err(ctrl, "clock enable failed, rc=%d\n", rc);
return rc;
}
ctrl->cpr_enabled = true;
}
max_core_count = sdelta->max_core_count;
if (sdelta->allow_core_count_adj || sdelta->allow_temp_adj) {
if (sdelta->allow_core_count_adj) {
/* Program TEMP_CORE0 to same margins as TEMP_CORE1 */
cpr3_write_temp_core_margin(ctrl,
CPR4_REG_MARGIN_TEMP_CORE(0),
&sdelta->table[0]);
}
for (i = 0; i < max_core_count; i++) {
index = i * sdelta->temp_band_count;
/*
* Program TEMP_COREi with voltage margin adjustments
* that need to be applied when the number of cores
* becomes i.
*/
cpr3_write_temp_core_margin(ctrl,
CPR4_REG_MARGIN_TEMP_CORE(
sdelta->allow_core_count_adj
? i + 1 : max_core_count),
&sdelta->table[index]);
}
}
if (sdelta->allow_boost) {
/* Program only boost_num_cores row of SDELTA */
cpr3_write_temp_core_margin(ctrl,
CPR4_REG_MARGIN_TEMP_CORE(sdelta->boost_num_cores),