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40 stars written in Verilog
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Verilog AXI components for FPGA implementation

Verilog 1,380 422 Updated Dec 7, 2023
Verilog 1,155 244 Updated Jul 28, 2024

Verilog PCI express components

Verilog 1,033 274 Updated Apr 26, 2024

An Open-source FPGA IP Generator

Verilog 783 158 Updated Jul 28, 2024

Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

Verilog 770 142 Updated Oct 22, 2023

iCESugar FPGA Board (base on iCE40UP5k)

Verilog 344 97 Updated Jun 5, 2024

Verilog Generator of Neural Net Digit Detector for FPGA

Verilog 290 88 Updated Sep 7, 2022

An attempt to recreate the RP2040 PIO in an FPGA

Verilog 278 30 Updated Jun 6, 2024

current focus on Colorlight i5 and i9 & i9plus module

Verilog 240 52 Updated Feb 20, 2024

Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation

Verilog 238 43 Updated Feb 11, 2024
Verilog 227 66 Updated Mar 3, 2024

A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals

Verilog 226 32 Updated Nov 29, 2018

Nintendo Entertainment System (NES) / Famicom / Famiclones chip reversing

Verilog 163 18 Updated Jul 22, 2024

iCESugar series FPGA dev board

Verilog 161 26 Updated Jun 27, 2024

Betrusted main SoC design

Verilog 136 20 Updated Nov 24, 2023

Universal Memory Interface (UMI)

Verilog 124 10 Updated Jul 26, 2024

IEEE 754 floating point unit in Verilog

Verilog 120 22 Updated May 20, 2016

Pong game in a FPGA.

Verilog 91 16 Updated Oct 28, 2020

My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu

Verilog 84 17 Updated Jul 28, 2021

"What comes next? Super Mario 128? Actually, that's what I want to do."

Verilog 76 4 Updated Jan 23, 2024

Human Resource Machine - CPU Design #HRM

Verilog 71 8 Updated Feb 14, 2021

sliding DFT for FPGA, targetting Lattice ICE40 1k

Verilog 71 16 Updated Apr 24, 2020

ice40 USB Analyzer

Verilog 57 7 Updated Aug 8, 2020
Verilog 54 11 Updated Aug 30, 2021

Icestudio Pixel Stream collection

Verilog 53 3 Updated Jun 1, 2018

Exploring gate level simulation

Verilog 52 4 Updated Sep 18, 2022

This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.

Verilog 46 8 Updated Aug 12, 2017

DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3

Verilog 40 11 Updated May 29, 2022

Integration of two camera 📷 modules to Basys 3 FPGA

Verilog 32 7 Updated Feb 8, 2023

Reusable Verilog 2005 components for FPGA designs

Verilog 26 3 Updated Jun 26, 2023
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