Open source FPGA-based NIC and platform for in-network compute

一步一步写MIPS CPU

Various HDL (Verilog) IP Cores

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip …

IC implementation of Systolic Array for TPU

Parallel Array of Simple Cores. Multicore processor.

体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器

This repository is used to release the Labs of Computer Architecture Course from USTC