Work-In-Progress
These notes have moved to https://github.com/mwrnd/alveo_u25_notes.
Currently focused on trying to debug a faulty Alveo U25.
The Alveo U25 is based on the XCU25==XCZU19EG-FFVC1760.
UrJTAG is a low-level tool for communicating with JTAG devices. It supports Xilinx Platform Cable USB II adapters and clones. Main use is EXTEST pin toggling although it is theoretically possible to program the FPGA using an SVF file generated from the Vivado Tcl Console.
cd ~
wget https://downloads.sourceforge.net/project/urjtag/urjtag/2021.03/urjtag-2021.03.tar.xz
sha256sum urjtag-2021.03.tar.xz
echo b0a2eaa245513af096dc4d770109832335c694c6c12aa5e92fefae8685416f1c should be the SHA256 Checksum
tar -xvf urjtag-2021.03.tar.xz
cd urjtag-2021.03/
./configure
make
sudo make install
sudo ldconfigXilinx's Zynq Ultrascale+ BSDL Files include STD_1149_6_2003.all definitions that UrJTAG's bsdl2jtag cannot process and must therefore be removed. The included xczu19eg_ffvc1760.jtag and zynqu_arm_dap.jtag files are processed and tested to work with UrJTAG.
From the directory containing the .jtag files run the following commands which create PART and STEPPINGS files for the XCZU19EG. These commands assume UrJTAG installed support files to the default /usr/local/share/ directory. Values were found by running the UrJTAG detect command which reads the Device Id from the JTAG chain. First 4 bits (0001) are the STEPPING, next 16 bits (0100011101011000) are the PART, last 12 bits (01000111011) are the MANUFACTURER.
sudo su
echo "# Zynq Ultrascale+ (XCZUxxEG)" >>/usr/local/share/urjtag/xilinx/PARTS
echo -e "0100011101011000\txczu19eg_1760\txczu19eg_ffvc1760" >>/usr/local/share/urjtag/xilinx/PARTS
mkdir /usr/local/share/urjtag/xilinx/xczu19eg_1760
touch /usr/local/share/urjtag/xilinx/xczu19eg_1760/STEPPINGS
echo "0001 xczu19eg_1760 1" >>/usr/local/share/urjtag/xilinx/xczu19eg_1760/STEPPINGS
echo "0000 xczu19eg_1760 0" >>/usr/local/share/urjtag/xilinx/xczu19eg_1760/STEPPINGS
cp xczu19eg_ffvc1760.jtag /usr/local/share/urjtag/xilinx/xczu19eg_1760/xczu19eg_1760
echo -e "01000111011\tarm\t\tARM" >>/usr/local/share/urjtag/MANUFACTURERS
mkdir /usr/local/share/urjtag/arm
touch /usr/local/share/urjtag/arm/PARTS
echo -e "1011101000000000\tzynqu_arm_dap\tzynqu_arm_dap" >>/usr/local/share/urjtag/arm/PARTS
mkdir /usr/local/share/urjtag/arm/zynqu_arm_dap
touch /usr/local/share/urjtag/arm/zynqu_arm_dap/STEPPINGS
echo "0101 zynqu_arm_dap 5" >>/usr/local/share/urjtag/arm/zynqu_arm_dap/STEPPINGS
cp zynqu_arm_dap.jtag /usr/local/share/urjtag/arm/zynqu_arm_dap/zynqu_arm_dap
exit
Connect your JTAG Adapter to the Alveo U25. The Alveo needs to be powered over its PCIe connection.
If you are using a Platform Cable USB II compatible adapter it will show up under lsusb as 03fd:0013 Xilinx, Inc. In this state it CANNOT be used for JTAG.
Run Xilinx's xsdb which comes with Vivado:
source /tools/Xilinx/Vivado/2021.2/settings64.sh
xsdb
In xsdb run the following commands to bring the Zynq out of the L2 Cache Reset state and into the Power On Reset and External Debug Request state. The 10 second delay (after 10000) allows for Xilinx's hw_server to update the Platform Cable II Firmware in the background.
connect
after 10000
targets
targets -set -nocase -filter {name =~ "*APU*"}
mwr 0xffff0000 0x14000000
mask_write 0xFD1A0104 0x501 0x0
targets -set -nocase -filter {name =~ "*A53*#0"}
stop
targets
exit from xsdb. lsusb should now show 03fd:0008 Xilinx, Inc. Platform Cable USB II. The JTAG adapter is ready to be used by UrJTAG.
sudo jtag to start UrJTAG with access to USB. You should see the jtag> command prompt. A JTAG Overview may be helpful before you begin. Note that shift ir and shift dr need to be run to change the debug target's state. Running instruction commands only changes UrJTAG's internal state.
Valid signal names can be found in the xczu19eg_ffvc1760.jtag file.
cable xpc_ext selects the Xilinx Platform Cable II, external JTAG chain
detect finds all devices in the JTAG chain
print chain prints all devices in the JTAG chain
part 1 selects the Zynq for JTAG communication. Good practise to always make this explicit.
instruction EXTEST select the External Test Function
shift ir shifts EXTEST into the JTAG Instruction Register to put the device into EXTEST mode
shift dr shifts the Data Register containing all pin states into UrJTAG memory
dr prints the full contents of the JTAG Data Register.
It is more useful to read individual signals:
get signal PS_MODE0 displays the value of pin PS_MODE0(AA27)
get signal PS_MODE1 displays the value of pin PS_MODE1(AC28)
get signal PS_MODE2 displays the value of pin PS_MODE2(AA28)
get signal PS_MODE3 displays the value of pin PS_MODE3(AB28)
The above MODE pins define Quad-SPI as the Boot Mode.
get signal PS_ERROR_OUT indicates a Power, Hardware, or PMU Exception when =1.
get signal PS_INIT_B indicates a CRC Error in the PL Bitstream when =1.
get signal PS_ERROR_STATUS indicates a lockdown state or PMU Status Error when =1.
get signal PS_DONE indicates PL Configuration completed when =1.
reset resets the JTAG chain and enters Bypass Mode
quit exits UrJTAG
The included UrJTAG scripts getallio and getallpsmio will return the states of all the Programmable Logic (PL) I/O pins and Processing System (PS) Multiplexed I/O pins, respectively.
include /DOWNLOAD_DIRECTORY/getallio
A sequence of instructions like the following can be used to set IO pins. Be careful which signals you set. They should be wired appropriately on the board. Refer to xczu19eg_ffvc1760.jtag for signal names.
instruction SAMPLE/PRELOAD
shift ir
shift dr
get signal IO_??
instruction EXTEST
shift ir
set signal IO_?? out 0
shift dr
instruction SAMPLE/PRELOAD
shift ir
shift dr
get signal IO_??
instruction EXTEST
shift ir
set signal IO_?? in
shift dr
instruction SAMPLE/PRELOAD
shift ir
shift dr
get signal IO_??
In the Vivado Tcl Console, run:
readback_hw_device [current_hw_device] -readback_file zu19eg_u25_r.rbd -bin_file zu19eg_u25_b.bin
XCU25==XCZU19EG-FFVC1760 Banks from Zynq Ultrascale+ Device Packaging and Pinouts.
Zynq Ultrascale+ MPSoC Overview
Zynq Ultrascale+ MPSoC Design Hub
Zynq Ultrascale+ Technical Reference Manual
Zynq Ultrascale+ Device Packaging and Pinouts
Zynq Ultrascale+ MPSoC Datasheet
Zynq UltraScale+ Devices Register Reference(HTML) is Downloadable
ServeTheHome Forum post about the Alveo U25
Bare Metal Application Development
XRT Dual-Stage Platform - U25 shell stage is included in the U25 FPGA Utility (2.8.372) package. Base stage is not public.
Flashing Shell to U25 Support Forum Post
U25 Xilinx Lenovo Page has a Production Package and a Utilities Package
U25 X2 NIC Driver (4.15.10.1003)
U25 X2 NIC Firmware (8.1.3.1011-1)
Alveo U25N Product Brief is almost identical but lacks the FPGA to PCIe connections.
MT40A512M16LY-062E(D9WFJ FBGA Code) is the DDR4 memory IC used on the U25.
MT25QU01(RW188 FBGA Code) is the QSPI Configuration Memory flash IC used on the U25.