diff --git a/tests/test_syntax/test_fsm.py b/tests/test_syntax/test_fsm.py
index 23f4af2b0..5bbd78596 100644
--- a/tests/test_syntax/test_fsm.py
+++ b/tests/test_syntax/test_fsm.py
@@ -50,5 +50,5 @@ class Foo(m.Circuit):
                     io.O @= i
                     state.next @= states[(i + 1) % 3]
 
-    m.compile("build/test_fsm_loop_unroll", Foo, output="mlir-verilog")
+    m.compile("build/test_fsm_loop_unroll", Foo, output="mlir")
     assert check_gold(__file__, "test_fsm_loop_unroll.mlir")