From 8c4886fcc23587bfb34254860fd4b7912897bbf2 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 22 Mar 2024 16:33:20 -0700 Subject: [PATCH] Remove verilog compile --- tests/test_syntax/test_fsm.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/test_syntax/test_fsm.py b/tests/test_syntax/test_fsm.py index 23f4af2b0..5bbd78596 100644 --- a/tests/test_syntax/test_fsm.py +++ b/tests/test_syntax/test_fsm.py @@ -50,5 +50,5 @@ class Foo(m.Circuit): io.O @= i state.next @= states[(i + 1) % 3] - m.compile("build/test_fsm_loop_unroll", Foo, output="mlir-verilog") + m.compile("build/test_fsm_loop_unroll", Foo, output="mlir") assert check_gold(__file__, "test_fsm_loop_unroll.mlir")