Add shift_register_gated

[qian-gu]

A shift register with clock gating

[niwis]

Thank you @qian-gu for this PR. To avoid code fragmentation, could you adapt shift_reg such that it instantiates this module, tying valid_i to 1'b1 and leaving valid_o open? Furthermore, could you update the following files with this module:

• Bender.yml
• README.md
• src_files.yml

Finally, please rebase to master (we updated the CI last night)

[niwis]

Is this needed? If not, please remove

[qian-gu]

This directive is added to ensure all internal variables are declared explicitly by designer. I will remove it to keep consistent with other modules.

[niwis]

Same here as L13

[niwis]

Adapt this to our coding convention

Suggested change

	logic [Depth-1 : 0] valid_d;
	logic [Depth-1 : 0] valid_q;
	dtype [Depth-1 : 0] data_d;
	dtype [Depth-1 : 0] data_q;
	logic [Depth-1:0] valid_d, valid_q;
	dtype [Depth-1:0] data_d, data_q;

[qian-gu]

update commits have been pushed, but the CI command

git remote add gitlab ***iis-git.ee.ethz.ch/github-mirror/common_cells
git push --force --mirror gitlab

gives an error message:

remote: HTTP Basic: Access denied. The provided password or token is incorrect or your account has 2FA enabled and you must use a personal access token instead of a password.

[niwis]

Thanks a lot! The CI is failing since you don't have access to the required github secrets... we're working on a solution for future PRs.