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mxc_epdc_fb.c
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mxc_epdc_fb.c
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/*
* Copyright (C) 2010-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
/*
* Based on STMP378X LCDIF
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
#include <linux/busfreq-imx.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/input.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/mutex.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/uaccess.h>
#include <linux/cpufreq.h>
#include <linux/firmware.h>
#include <linux/kthread.h>
#include <linux/dmaengine.h>
#include <linux/pxp_dma.h>
#include <linux/pm_runtime.h>
#include <linux/mxcfb.h>
#include <linux/mxcfb_epdc.h>
#include <linux/gpio.h>
#include <linux/regulator/driver.h>
#include <linux/fsl_devices.h>
#include <linux/bitops.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_data/dma-imx.h>
#include <asm/cacheflush.h>
#include "epdc_regs.h"
#define QOS_ENABLE
/*
* MMDC_MAARCR[ARCR_RCH_EN] = 1 by default
* QoS=='F' is real time access
*/
#ifdef QOS_ENABLE
#include <linux/of_address.h>
#define QOS_EPDC_OFFSET 0x1400 // 0x1400 for 6SL, 0x1800 for 6SLL
#endif
/*
* Enable this define to have a default panel
* loaded during driver initialization
*/
/*#define DEFAULT_PANEL_HW_INIT*/
#define NUM_SCREENS_MIN 2
#define EPDC_V1_NUM_LUTS 16
#define EPDC_V1_MAX_NUM_UPDATES 20
#define EPDC_V2_NUM_LUTS 64
#define EPDC_V2_MAX_NUM_UPDATES 64
#define EPDC_MAX_NUM_BUFFERS 2
#define INVALID_LUT (-1)
#define DRY_RUN_NO_LUT 100
/* Maximum update buffer image width due to v2.0 and v2.1 errata ERR005313. */
#define EPDC_V2_MAX_UPDATE_WIDTH 2047
#define EPDC_V2_ROTATION_ALIGNMENT 8
#define DEFAULT_TEMP_INDEX 0
#define DEFAULT_TEMP 20 /* room temp in deg Celsius */
#define DEFAULT_TEMP_AUTO_UPDATE_PERIOD 60 /* 60 seconds */
#define INIT_UPDATE_MARKER 0x12345678
#define PAN_UPDATE_MARKER 0x12345679
#define POWER_STATE_OFF 0
#define POWER_STATE_ON 1
#define MERGE_OK 0
#define MERGE_FAIL 1
#define MERGE_BLOCK 2
static unsigned long default_bpp = 16;
static DEFINE_MUTEX(hard_lock);
struct update_marker_data {
struct list_head full_list;
struct list_head upd_list;
u32 update_marker;
struct completion update_completion;
int lut_num;
bool collision_test;
bool waiting;
};
struct update_desc_list {
struct list_head list;
struct mxcfb_update_data upd_data;/* Update parameters */
u32 epdc_offs; /* Added to buffer ptr to resolve alignment */
u32 epdc_stride; /* Depends on rotation & whether we skip PxP */
struct list_head upd_marker_list; /* List of markers for this update */
u32 update_order; /* Numeric ordering value for update */
};
/* This structure represents a list node containing both
* a memory region allocated as an output buffer for the PxP
* update processing task, and the update description (mode, region, etc.) */
struct update_data_list {
struct list_head list;
dma_addr_t phys_addr; /* Pointer to phys address of processed Y buf */
void *virt_addr;
struct update_desc_list *update_desc;
int lut_num; /* Assigned before update is processed into working buffer */
u64 collision_mask; /* Set when update creates collision */
/* Mask of the LUTs the update collides with */
};
struct mxc_epdc_fb_data {
struct fb_info info;
struct fb_var_screeninfo epdc_fb_var; /* Internal copy of screeninfo
so we can sync changes to it */
u32 pseudo_palette[16];
char fw_str[24];
struct list_head list;
struct imx_epdc_fb_mode *cur_mode;
struct imx_epdc_fb_platform_data *pdata;
int blank;
u32 max_pix_size;
ssize_t map_size;
dma_addr_t phys_start;
u32 fb_offset;
int default_bpp;
int native_width;
int native_height;
int num_screens;
int epdc_irq;
struct device *dev;
int power_state;
int wait_for_powerdown;
struct completion powerdown_compl;
struct clk *epdc_clk_axi;
struct clk *epdc_clk_pix;
struct regulator *display_regulator;
struct regulator *vcom_regulator;
struct regulator *v3p3_regulator;
struct regulator *tmst_regulator;
bool fw_default_load;
int rev;
/* FB elements related to EPDC updates */
int num_luts;
int max_num_updates;
bool in_init;
bool hw_ready;
bool hw_initializing;
bool waiting_for_idle;
u32 auto_mode;
u32 upd_scheme;
struct list_head upd_pending_list;
struct list_head upd_buf_queue;
struct list_head upd_buf_free_list;
struct list_head upd_buf_collision_list;
struct update_data_list *cur_update;
struct mutex queue_mutex;
int trt_entries;
int temp_auto_update_period;
unsigned long last_time_temp_auto_update;
int temp_index;
u8 *temp_range_bounds;
struct mxcfb_waveform_modes wv_modes;
bool wv_modes_update;
u32 *waveform_buffer_virt;
u32 waveform_buffer_phys;
u32 waveform_buffer_size;
u32 *working_buffer_virt;
u32 working_buffer_phys;
u32 working_buffer_size;
dma_addr_t *phys_addr_updbuf;
void **virt_addr_updbuf;
u32 upd_buffer_num;
u32 max_num_buffers;
dma_addr_t phys_addr_copybuf; /* Phys address of copied update data */
void *virt_addr_copybuf; /* Used for PxP SW workaround */
u32 order_cnt;
struct list_head full_marker_list;
u32 *lut_update_order; /* Array size = number of luts */
u64 epdc_colliding_luts;
u64 luts_complete_wb;
struct completion updates_done;
struct delayed_work epdc_done_work;
struct workqueue_struct *epdc_submit_workqueue;
struct work_struct epdc_submit_work;
struct workqueue_struct *epdc_intr_workqueue;
struct work_struct epdc_intr_work;
bool waiting_for_wb;
bool waiting_for_lut;
bool waiting_for_lut15;
struct completion update_res_free;
struct completion lut15_free;
struct completion eof_event;
int eof_sync_period;
struct mutex power_mutex;
bool powering_down;
bool updates_active;
int pwrdown_delay;
unsigned long tce_prevent;
bool restrict_width; /* work around rev >=2.0 width and
stride restriction */
/* FB elements related to PxP DMA */
struct completion pxp_tx_cmpl;
struct pxp_channel *pxp_chan;
struct pxp_config_data pxp_conf;
struct dma_async_tx_descriptor *txd;
dma_cookie_t cookie;
struct scatterlist sg[2];
struct mutex pxp_mutex; /* protects access to PxP */
#ifdef QOS_ENABLE
void __iomem *qos_base;
#endif
};
struct waveform_data_header {
unsigned int wi0;
unsigned int wi1;
unsigned int wi2;
unsigned int wi3;
unsigned int wi4;
unsigned int wi5;
unsigned int wi6;
unsigned int xwia:24;
unsigned int cs1:8;
unsigned int wmta:24;
unsigned int fvsn:8;
unsigned int luts:8;
unsigned int mc:8;
unsigned int trc:8;
unsigned int reserved0_0:8;
unsigned int eb:8;
unsigned int sb:8;
unsigned int reserved0_1:8;
unsigned int reserved0_2:8;
unsigned int reserved0_3:8;
unsigned int reserved0_4:8;
unsigned int reserved0_5:8;
unsigned int cs2:8;
};
struct mxcfb_waveform_data_file {
struct waveform_data_header wdh;
u32 *data; /* Temperature Range Table + Waveform Data */
};
static struct fb_videomode e60_v110_mode = {
.name = "E60_V110",
.refresh = 50,
.xres = 800,
.yres = 600,
.pixclock = 18604700,
.left_margin = 8,
.right_margin = 178,
.upper_margin = 4,
.lower_margin = 10,
.hsync_len = 20,
.vsync_len = 4,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED,
.flag = 0,
};
static struct fb_videomode e60_v220_mode = {
.name = "E60_V220",
.refresh = 85,
.xres = 800,
.yres = 600,
.pixclock = 30000000,
.left_margin = 8,
.right_margin = 164,
.upper_margin = 4,
.lower_margin = 8,
.hsync_len = 4,
.vsync_len = 1,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED,
.flag = 0,
};
static struct fb_videomode e060scm_mode = {
.name = "E060SCM",
.refresh = 85,
.xres = 800,
.yres = 600,
.pixclock = 26666667,
.left_margin = 8,
.right_margin = 100,
.upper_margin = 4,
.lower_margin = 8,
.hsync_len = 4,
.vsync_len = 1,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED,
.flag = 0,
};
static struct fb_videomode e97_v110_mode = {
.name = "E97_V110",
.refresh = 50,
.xres = 1200,
.yres = 825,
.pixclock = 32000000,
.left_margin = 12,
.right_margin = 128,
.upper_margin = 4,
.lower_margin = 10,
.hsync_len = 20,
.vsync_len = 4,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED,
.flag = 0,
};
static struct fb_videomode es103cs1_mode = {
.name = "ES103CS1",
.refresh = 85,
.xres = 1872,
.yres = 1404,
.pixclock = 160000000,
.left_margin = 32,
.right_margin = 326,
.upper_margin = 4,
.lower_margin = 12,
.hsync_len = 44,
.vsync_len = 1,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED,
.flag = 0,
};
static struct imx_epdc_fb_mode panel_modes[] = {
{
&es103cs1_mode,
4, /* vscan_holdoff */
10, /* sdoed_width */
20, /* sdoed_delay */
10, /* sdoez_width */
20, /* sdoez_delay */
1042, /* gdclk_hp_offs */
762, /* gdsp_offs */
0, /* gdoe_offs */
91, /* gdclk_offs */
1, /* num_ce */
},
{
&e60_v110_mode,
4, /* vscan_holdoff */
10, /* sdoed_width */
20, /* sdoed_delay */
10, /* sdoez_width */
20, /* sdoez_delay */
428, /* gdclk_hp_offs */
20, /* gdsp_offs */
0, /* gdoe_offs */
1, /* gdclk_offs */
1, /* num_ce */
},
{
&e60_v220_mode,
4, /* vscan_holdoff */
10, /* sdoed_width */
20, /* sdoed_delay */
10, /* sdoez_width */
20, /* sdoez_delay */
465, /* gdclk_hp_offs */
20, /* gdsp_offs */
0, /* gdoe_offs */
9, /* gdclk_offs */
1, /* num_ce */
},
{
&e060scm_mode,
4, /* vscan_holdoff */
10, /* sdoed_width */
20, /* sdoed_delay */
10, /* sdoez_width */
20, /* sdoez_delay */
419, /* gdclk_hp_offs */
20, /* gdsp_offs */
0, /* gdoe_offs */
5, /* gdclk_offs */
1, /* num_ce */
},
{
&e97_v110_mode,
8, /* vscan_holdoff */
10, /* sdoed_width */
20, /* sdoed_delay */
10, /* sdoez_width */
20, /* sdoez_delay */
632, /* gdclk_hp_offs */
20, /* gdsp_offs */
0, /* gdoe_offs */
1, /* gdclk_offs */
3, /* num_ce */
}
};
static struct imx_epdc_fb_platform_data epdc_data = {
.epdc_mode = panel_modes,
.num_modes = ARRAY_SIZE(panel_modes),
};
void __iomem *epdc_base;
struct mxc_epdc_fb_data *g_fb_data;
/* forward declaration */
static int mxc_epdc_fb_get_temp_index(struct mxc_epdc_fb_data *fb_data,
int temp);
static void mxc_epdc_fb_flush_updates(struct mxc_epdc_fb_data *fb_data);
static int mxc_epdc_fb_blank(int blank, struct fb_info *info);
static int mxc_epdc_fb_init_hw(struct fb_info *info);
static int pxp_process_update(struct mxc_epdc_fb_data *fb_data,
u32 src_width, u32 src_height,
struct mxcfb_rect *update_region);
static int pxp_complete_update(struct mxc_epdc_fb_data *fb_data, u32 *hist_stat);
static void draw_mode0(struct mxc_epdc_fb_data *fb_data);
static bool is_free_list_full(struct mxc_epdc_fb_data *fb_data);
static void do_dithering_processing_Y1_v1_0(
unsigned char *update_region_virt_ptr,
dma_addr_t update_region_phys_ptr,
struct mxcfb_rect *update_region,
unsigned long update_region_stride,
int *err_dist);
static void do_dithering_processing_Y4_v1_0(
unsigned char *update_region_virt_ptr,
dma_addr_t update_region_phys_ptr,
struct mxcfb_rect *update_region,
unsigned long update_region_stride,
int *err_dist);
#ifdef DEBUG
static void dump_pxp_config(struct mxc_epdc_fb_data *fb_data,
struct pxp_config_data *pxp_conf)
{
dev_info(fb_data->dev, "S0 fmt 0x%x",
pxp_conf->s0_param.pixel_fmt);
dev_info(fb_data->dev, "S0 width 0x%x",
pxp_conf->s0_param.width);
dev_info(fb_data->dev, "S0 height 0x%x",
pxp_conf->s0_param.height);
dev_info(fb_data->dev, "S0 ckey 0x%x",
pxp_conf->s0_param.color_key);
dev_info(fb_data->dev, "S0 ckey en 0x%x",
pxp_conf->s0_param.color_key_enable);
dev_info(fb_data->dev, "OL0 combine en 0x%x",
pxp_conf->ol_param[0].combine_enable);
dev_info(fb_data->dev, "OL0 fmt 0x%x",
pxp_conf->ol_param[0].pixel_fmt);
dev_info(fb_data->dev, "OL0 width 0x%x",
pxp_conf->ol_param[0].width);
dev_info(fb_data->dev, "OL0 height 0x%x",
pxp_conf->ol_param[0].height);
dev_info(fb_data->dev, "OL0 ckey 0x%x",
pxp_conf->ol_param[0].color_key);
dev_info(fb_data->dev, "OL0 ckey en 0x%x",
pxp_conf->ol_param[0].color_key_enable);
dev_info(fb_data->dev, "OL0 alpha 0x%x",
pxp_conf->ol_param[0].global_alpha);
dev_info(fb_data->dev, "OL0 alpha en 0x%x",
pxp_conf->ol_param[0].global_alpha_enable);
dev_info(fb_data->dev, "OL0 local alpha en 0x%x",
pxp_conf->ol_param[0].local_alpha_enable);
dev_info(fb_data->dev, "Out fmt 0x%x",
pxp_conf->out_param.pixel_fmt);
dev_info(fb_data->dev, "Out width 0x%x",
pxp_conf->out_param.width);
dev_info(fb_data->dev, "Out height 0x%x",
pxp_conf->out_param.height);
dev_info(fb_data->dev,
"drect left 0x%x right 0x%x width 0x%x height 0x%x",
pxp_conf->proc_data.drect.left, pxp_conf->proc_data.drect.top,
pxp_conf->proc_data.drect.width,
pxp_conf->proc_data.drect.height);
dev_info(fb_data->dev,
"srect left 0x%x right 0x%x width 0x%x height 0x%x",
pxp_conf->proc_data.srect.left, pxp_conf->proc_data.srect.top,
pxp_conf->proc_data.srect.width,
pxp_conf->proc_data.srect.height);
dev_info(fb_data->dev, "Scaling en 0x%x", pxp_conf->proc_data.scaling);
dev_info(fb_data->dev, "HFlip en 0x%x", pxp_conf->proc_data.hflip);
dev_info(fb_data->dev, "VFlip en 0x%x", pxp_conf->proc_data.vflip);
dev_info(fb_data->dev, "Rotation 0x%x", pxp_conf->proc_data.rotate);
dev_info(fb_data->dev, "BG Color 0x%x", pxp_conf->proc_data.bgcolor);
}
static void dump_epdc_reg(void)
{
printk(KERN_DEBUG "\n\n");
printk(KERN_DEBUG "EPDC_CTRL 0x%x\n", __raw_readl(EPDC_CTRL));
printk(KERN_DEBUG "EPDC_WVADDR 0x%x\n", __raw_readl(EPDC_WVADDR));
printk(KERN_DEBUG "EPDC_WB_ADDR 0x%x\n", __raw_readl(EPDC_WB_ADDR));
printk(KERN_DEBUG "EPDC_RES 0x%x\n", __raw_readl(EPDC_RES));
printk(KERN_DEBUG "EPDC_FORMAT 0x%x\n", __raw_readl(EPDC_FORMAT));
printk(KERN_DEBUG "EPDC_FIFOCTRL 0x%x\n", __raw_readl(EPDC_FIFOCTRL));
printk(KERN_DEBUG "EPDC_UPD_ADDR 0x%x\n", __raw_readl(EPDC_UPD_ADDR));
printk(KERN_DEBUG "EPDC_UPD_STRIDE 0x%x\n", __raw_readl(EPDC_UPD_STRIDE));
printk(KERN_DEBUG "EPDC_UPD_FIXED 0x%x\n", __raw_readl(EPDC_UPD_FIXED));
printk(KERN_DEBUG "EPDC_UPD_CORD 0x%x\n", __raw_readl(EPDC_UPD_CORD));
printk(KERN_DEBUG "EPDC_UPD_SIZE 0x%x\n", __raw_readl(EPDC_UPD_SIZE));
printk(KERN_DEBUG "EPDC_UPD_CTRL 0x%x\n", __raw_readl(EPDC_UPD_CTRL));
printk(KERN_DEBUG "EPDC_TEMP 0x%x\n", __raw_readl(EPDC_TEMP));
printk(KERN_DEBUG "EPDC_AUTOWV_LUT 0x%x\n", __raw_readl(EPDC_AUTOWV_LUT));
printk(KERN_DEBUG "EPDC_TCE_CTRL 0x%x\n", __raw_readl(EPDC_TCE_CTRL));
printk(KERN_DEBUG "EPDC_TCE_SDCFG 0x%x\n", __raw_readl(EPDC_TCE_SDCFG));
printk(KERN_DEBUG "EPDC_TCE_GDCFG 0x%x\n", __raw_readl(EPDC_TCE_GDCFG));
printk(KERN_DEBUG "EPDC_TCE_HSCAN1 0x%x\n", __raw_readl(EPDC_TCE_HSCAN1));
printk(KERN_DEBUG "EPDC_TCE_HSCAN2 0x%x\n", __raw_readl(EPDC_TCE_HSCAN2));
printk(KERN_DEBUG "EPDC_TCE_VSCAN 0x%x\n", __raw_readl(EPDC_TCE_VSCAN));
printk(KERN_DEBUG "EPDC_TCE_OE 0x%x\n", __raw_readl(EPDC_TCE_OE));
printk(KERN_DEBUG "EPDC_TCE_POLARITY 0x%x\n", __raw_readl(EPDC_TCE_POLARITY));
printk(KERN_DEBUG "EPDC_TCE_TIMING1 0x%x\n", __raw_readl(EPDC_TCE_TIMING1));
printk(KERN_DEBUG "EPDC_TCE_TIMING2 0x%x\n", __raw_readl(EPDC_TCE_TIMING2));
printk(KERN_DEBUG "EPDC_TCE_TIMING3 0x%x\n", __raw_readl(EPDC_TCE_TIMING3));
printk(KERN_DEBUG "EPDC_PIGEON_CTRL0 0x%x\n", __raw_readl(EPDC_PIGEON_CTRL0));
printk(KERN_DEBUG "EPDC_PIGEON_CTRL1 0x%x\n", __raw_readl(EPDC_PIGEON_CTRL1));
printk(KERN_DEBUG "EPDC_IRQ_MASK1 0x%x\n", __raw_readl(EPDC_IRQ_MASK1));
printk(KERN_DEBUG "EPDC_IRQ_MASK2 0x%x\n", __raw_readl(EPDC_IRQ_MASK2));
printk(KERN_DEBUG "EPDC_IRQ1 0x%x\n", __raw_readl(EPDC_IRQ1));
printk(KERN_DEBUG "EPDC_IRQ2 0x%x\n", __raw_readl(EPDC_IRQ2));
printk(KERN_DEBUG "EPDC_IRQ_MASK 0x%x\n", __raw_readl(EPDC_IRQ_MASK));
printk(KERN_DEBUG "EPDC_IRQ 0x%x\n", __raw_readl(EPDC_IRQ));
printk(KERN_DEBUG "EPDC_STATUS_LUTS 0x%x\n", __raw_readl(EPDC_STATUS_LUTS));
printk(KERN_DEBUG "EPDC_STATUS_LUTS2 0x%x\n", __raw_readl(EPDC_STATUS_LUTS2));
printk(KERN_DEBUG "EPDC_STATUS_NEXTLUT 0x%x\n", __raw_readl(EPDC_STATUS_NEXTLUT));
printk(KERN_DEBUG "EPDC_STATUS_COL1 0x%x\n", __raw_readl(EPDC_STATUS_COL));
printk(KERN_DEBUG "EPDC_STATUS_COL2 0x%x\n", __raw_readl(EPDC_STATUS_COL2));
printk(KERN_DEBUG "EPDC_STATUS 0x%x\n", __raw_readl(EPDC_STATUS));
printk(KERN_DEBUG "EPDC_UPD_COL_CORD 0x%x\n", __raw_readl(EPDC_UPD_COL_CORD));
printk(KERN_DEBUG "EPDC_UPD_COL_SIZE 0x%x\n", __raw_readl(EPDC_UPD_COL_SIZE));
printk(KERN_DEBUG "EPDC_DEBUG 0x%x\n", __raw_readl(EPDC_DEBUG));
printk(KERN_DEBUG "EPDC_DEBUG_LUT 0x%x\n", __raw_readl(EPDC_DEBUG_LUT));
printk(KERN_DEBUG "EPDC_HIST1_PARAM 0x%x\n", __raw_readl(EPDC_HIST1_PARAM));
printk(KERN_DEBUG "EPDC_HIST2_PARAM 0x%x\n", __raw_readl(EPDC_HIST2_PARAM));
printk(KERN_DEBUG "EPDC_HIST4_PARAM 0x%x\n", __raw_readl(EPDC_HIST4_PARAM));
printk(KERN_DEBUG "EPDC_HIST8_PARAM0 0x%x\n", __raw_readl(EPDC_HIST8_PARAM0));
printk(KERN_DEBUG "EPDC_HIST8_PARAM1 0x%x\n", __raw_readl(EPDC_HIST8_PARAM1));
printk(KERN_DEBUG "EPDC_HIST16_PARAM0 0x%x\n", __raw_readl(EPDC_HIST16_PARAM0));
printk(KERN_DEBUG "EPDC_HIST16_PARAM1 0x%x\n", __raw_readl(EPDC_HIST16_PARAM1));
printk(KERN_DEBUG "EPDC_HIST16_PARAM2 0x%x\n", __raw_readl(EPDC_HIST16_PARAM2));
printk(KERN_DEBUG "EPDC_HIST16_PARAM3 0x%x\n", __raw_readl(EPDC_HIST16_PARAM3));
printk(KERN_DEBUG "EPDC_GPIO 0x%x\n", __raw_readl(EPDC_GPIO));
printk(KERN_DEBUG "EPDC_VERSION 0x%x\n", __raw_readl(EPDC_VERSION));
printk(KERN_DEBUG "\n\n");
}
static void dump_update_data(struct device *dev,
struct update_data_list *upd_data_list)
{
dev_info(dev,
"X = %d, Y = %d, Width = %d, Height = %d, WaveMode = %d, "
"LUT = %d, Coll Mask = 0x%llx, order = %d\n",
upd_data_list->update_desc->upd_data.update_region.left,
upd_data_list->update_desc->upd_data.update_region.top,
upd_data_list->update_desc->upd_data.update_region.width,
upd_data_list->update_desc->upd_data.update_region.height,
upd_data_list->update_desc->upd_data.waveform_mode,
upd_data_list->lut_num,
upd_data_list->collision_mask,
upd_data_list->update_desc->update_order);
}
static void dump_collision_list(struct mxc_epdc_fb_data *fb_data)
{
struct update_data_list *plist;
dev_info(fb_data->dev, "Collision List:\n");
if (list_empty(&fb_data->upd_buf_collision_list))
dev_info(fb_data->dev, "Empty");
list_for_each_entry(plist, &fb_data->upd_buf_collision_list, list) {
dev_info(fb_data->dev, "Virt Addr = 0x%x, Phys Addr = 0x%x ",
(u32)plist->virt_addr, plist->phys_addr);
dump_update_data(fb_data->dev, plist);
}
}
static void dump_free_list(struct mxc_epdc_fb_data *fb_data)
{
struct update_data_list *plist;
dev_info(fb_data->dev, "Free List:\n");
if (list_empty(&fb_data->upd_buf_free_list))
dev_info(fb_data->dev, "Empty");
list_for_each_entry(plist, &fb_data->upd_buf_free_list, list)
dev_info(fb_data->dev, "Virt Addr = 0x%x, Phys Addr = 0x%x ",
(u32)plist->virt_addr, plist->phys_addr);
}
static void dump_queue(struct mxc_epdc_fb_data *fb_data)
{
struct update_data_list *plist;
dev_info(fb_data->dev, "Queue:\n");
if (list_empty(&fb_data->upd_buf_queue))
dev_info(fb_data->dev, "Empty");
list_for_each_entry(plist, &fb_data->upd_buf_queue, list) {
dev_info(fb_data->dev, "Virt Addr = 0x%x, Phys Addr = 0x%x ",
(u32)plist->virt_addr, plist->phys_addr);
dump_update_data(fb_data->dev, plist);
}
}
static void dump_desc_data(struct device *dev,
struct update_desc_list *upd_desc_list)
{
dev_info(dev,
"X = %d, Y = %d, Width = %d, Height = %d, WaveMode = %d, "
"order = %d\n",
upd_desc_list->upd_data.update_region.left,
upd_desc_list->upd_data.update_region.top,
upd_desc_list->upd_data.update_region.width,
upd_desc_list->upd_data.update_region.height,
upd_desc_list->upd_data.waveform_mode,
upd_desc_list->update_order);
}
static void dump_pending_list(struct mxc_epdc_fb_data *fb_data)
{
struct update_desc_list *plist;
dev_info(fb_data->dev, "Queue:\n");
if (list_empty(&fb_data->upd_pending_list))
dev_info(fb_data->dev, "Empty");
list_for_each_entry(plist, &fb_data->upd_pending_list, list)
dump_desc_data(fb_data->dev, plist);
}
static void dump_all_updates(struct mxc_epdc_fb_data *fb_data)
{
dump_free_list(fb_data);
dump_queue(fb_data);
dump_collision_list(fb_data);
dev_info(fb_data->dev, "Current update being processed:\n");
if (fb_data->cur_update == NULL)
dev_info(fb_data->dev, "No current update\n");
else
dump_update_data(fb_data->dev, fb_data->cur_update);
}
#else
static inline void dump_pxp_config(struct mxc_epdc_fb_data *fb_data,
struct pxp_config_data *pxp_conf) {}
static inline void dump_epdc_reg(void) {}
static inline void dump_update_data(struct device *dev,
struct update_data_list *upd_data_list) {}
static inline void dump_collision_list(struct mxc_epdc_fb_data *fb_data) {}
static inline void dump_free_list(struct mxc_epdc_fb_data *fb_data) {}
static inline void dump_queue(struct mxc_epdc_fb_data *fb_data) {}
static inline void dump_all_updates(struct mxc_epdc_fb_data *fb_data) {}
#endif
/********************************************************
* Start Low-Level EPDC Functions
********************************************************/
static inline void epdc_lut_complete_intr(int rev, u32 lut_num, bool enable)
{
if (rev < 20) {
if (enable)
__raw_writel(1 << lut_num, EPDC_IRQ_MASK_SET);
else
__raw_writel(1 << lut_num, EPDC_IRQ_MASK_CLEAR);
} else {
if (enable) {
if (lut_num < 32)
__raw_writel(1 << lut_num, EPDC_IRQ_MASK1_SET);
else
__raw_writel(1 << (lut_num - 32),
EPDC_IRQ_MASK2_SET);
} else {
if (lut_num < 32)
__raw_writel(1 << lut_num,
EPDC_IRQ_MASK1_CLEAR);
else
__raw_writel(1 << (lut_num - 32),
EPDC_IRQ_MASK2_CLEAR);
}
}
}
static inline void epdc_working_buf_intr(bool enable)
{
if (enable)
__raw_writel(EPDC_IRQ_WB_CMPLT_IRQ, EPDC_IRQ_MASK_SET);
else
__raw_writel(EPDC_IRQ_WB_CMPLT_IRQ, EPDC_IRQ_MASK_CLEAR);
}
static inline void epdc_clear_working_buf_irq(void)
{
__raw_writel(EPDC_IRQ_WB_CMPLT_IRQ | EPDC_IRQ_LUT_COL_IRQ,
EPDC_IRQ_CLEAR);
}
static inline void epdc_eof_intr(bool enable)
{
if (enable)
__raw_writel(EPDC_IRQ_FRAME_END_IRQ, EPDC_IRQ_MASK_SET);
else
__raw_writel(EPDC_IRQ_FRAME_END_IRQ, EPDC_IRQ_MASK_CLEAR);
}
static inline void epdc_clear_eof_irq(void)
{
__raw_writel(EPDC_IRQ_FRAME_END_IRQ, EPDC_IRQ_CLEAR);
}
static inline bool epdc_signal_eof(void)
{
return (__raw_readl(EPDC_IRQ_MASK) & __raw_readl(EPDC_IRQ)
& EPDC_IRQ_FRAME_END_IRQ) ? true : false;
}
static inline void epdc_set_temp(u32 temp)
{
__raw_writel(temp, EPDC_TEMP);
}
static inline void epdc_set_screen_res(u32 width, u32 height)
{
u32 val = (height << EPDC_RES_VERTICAL_OFFSET) | width;
__raw_writel(val, EPDC_RES);
}
static inline void epdc_set_update_addr(u32 addr)
{
__raw_writel(addr, EPDC_UPD_ADDR);
}
static inline void epdc_set_update_coord(u32 x, u32 y)
{
u32 val = (y << EPDC_UPD_CORD_YCORD_OFFSET) | x;
__raw_writel(val, EPDC_UPD_CORD);
}
static inline void epdc_set_update_dimensions(u32 width, u32 height)
{
u32 val = (height << EPDC_UPD_SIZE_HEIGHT_OFFSET) | width;
__raw_writel(val, EPDC_UPD_SIZE);
}
static void epdc_set_update_waveform(struct mxcfb_waveform_modes *wv_modes)
{
u32 val;
/* Configure the auto-waveform look-up table based on waveform modes */
/* Entry 1 = DU, 2 = GC4, 3 = GC8, etc. */
val = (wv_modes->mode_du << EPDC_AUTOWV_LUT_DATA_OFFSET) |
(0 << EPDC_AUTOWV_LUT_ADDR_OFFSET);
__raw_writel(val, EPDC_AUTOWV_LUT);
val = (wv_modes->mode_du << EPDC_AUTOWV_LUT_DATA_OFFSET) |
(1 << EPDC_AUTOWV_LUT_ADDR_OFFSET);
__raw_writel(val, EPDC_AUTOWV_LUT);
val = (wv_modes->mode_gc4 << EPDC_AUTOWV_LUT_DATA_OFFSET) |
(2 << EPDC_AUTOWV_LUT_ADDR_OFFSET);
__raw_writel(val, EPDC_AUTOWV_LUT);
val = (wv_modes->mode_gc8 << EPDC_AUTOWV_LUT_DATA_OFFSET) |
(3 << EPDC_AUTOWV_LUT_ADDR_OFFSET);
__raw_writel(val, EPDC_AUTOWV_LUT);
val = (wv_modes->mode_gc16 << EPDC_AUTOWV_LUT_DATA_OFFSET) |
(4 << EPDC_AUTOWV_LUT_ADDR_OFFSET);
__raw_writel(val, EPDC_AUTOWV_LUT);
val = (wv_modes->mode_gc32 << EPDC_AUTOWV_LUT_DATA_OFFSET) |
(5 << EPDC_AUTOWV_LUT_ADDR_OFFSET);
__raw_writel(val, EPDC_AUTOWV_LUT);
}
static void epdc_set_update_stride(u32 stride)
{
__raw_writel(stride, EPDC_UPD_STRIDE);
}
static void epdc_submit_update(u32 lut_num, u32 waveform_mode, u32 update_mode,
bool use_dry_run, bool use_test_mode, u32 np_val)
{
u32 reg_val = 0;
if (use_test_mode) {
reg_val |=
((np_val << EPDC_UPD_FIXED_FIXNP_OFFSET) &
EPDC_UPD_FIXED_FIXNP_MASK) | EPDC_UPD_FIXED_FIXNP_EN;
__raw_writel(reg_val, EPDC_UPD_FIXED);
reg_val = EPDC_UPD_CTRL_USE_FIXED;
} else {
__raw_writel(reg_val, EPDC_UPD_FIXED);
}
if (waveform_mode == WAVEFORM_MODE_AUTO)
reg_val |= EPDC_UPD_CTRL_AUTOWV;
else
reg_val |= ((waveform_mode <<
EPDC_UPD_CTRL_WAVEFORM_MODE_OFFSET) &
EPDC_UPD_CTRL_WAVEFORM_MODE_MASK);
reg_val |= (use_dry_run ? EPDC_UPD_CTRL_DRY_RUN : 0) |
((lut_num << EPDC_UPD_CTRL_LUT_SEL_OFFSET) &
EPDC_UPD_CTRL_LUT_SEL_MASK) |
update_mode;
__raw_writel(reg_val, EPDC_UPD_CTRL);
}
static inline bool epdc_is_lut_complete(int rev, u32 lut_num)
{
u32 val;
bool is_compl;
if (rev < 20) {
val = __raw_readl(EPDC_IRQ);
is_compl = val & (1 << lut_num) ? true : false;
} else if (lut_num < 32) {
val = __raw_readl(EPDC_IRQ1);
is_compl = val & (1 << lut_num) ? true : false;
} else {
val = __raw_readl(EPDC_IRQ2);
is_compl = val & (1 << (lut_num - 32)) ? true : false;
}
return is_compl;
}
static inline void epdc_clear_lut_complete_irq(int rev, u32 lut_num)
{
if (rev < 20)
__raw_writel(1 << lut_num, EPDC_IRQ_CLEAR);
else if (lut_num < 32)
__raw_writel(1 << lut_num, EPDC_IRQ1_CLEAR);
else
__raw_writel(1 << (lut_num - 32), EPDC_IRQ2_CLEAR);
}
static inline bool epdc_is_lut_active(u32 lut_num)
{
u32 val;
bool is_active;
if (lut_num < 32) {
val = __raw_readl(EPDC_STATUS_LUTS);
is_active = val & (1 << lut_num) ? true : false;
} else {
val = __raw_readl(EPDC_STATUS_LUTS2);
is_active = val & (1 << (lut_num - 32)) ? true : false;
}
return is_active;
}
static inline bool epdc_any_luts_active(int rev)
{
bool any_active;
if (rev < 20)
any_active = __raw_readl(EPDC_STATUS_LUTS) ? true : false;
else
any_active = (__raw_readl(EPDC_STATUS_LUTS) |
__raw_readl(EPDC_STATUS_LUTS2)) ? true : false;
return any_active;
}
static inline bool epdc_any_luts_available(void)
{
bool luts_available =
(__raw_readl(EPDC_STATUS_NEXTLUT) &
EPDC_STATUS_NEXTLUT_NEXT_LUT_VALID) ? true : false;
return luts_available;
}
static inline int epdc_get_next_lut(void)
{
u32 val =
__raw_readl(EPDC_STATUS_NEXTLUT) &
EPDC_STATUS_NEXTLUT_NEXT_LUT_MASK;
return val;
}
static int epdc_choose_next_lut(int rev, int *next_lut)
{
u64 luts_status, unprocessed_luts, used_luts;
/* Available LUTs are reduced to 16 in 5-bit waveform mode */
bool format_p5n = ((__raw_readl(EPDC_FORMAT) &
EPDC_FORMAT_BUF_PIXEL_FORMAT_MASK) ==
EPDC_FORMAT_BUF_PIXEL_FORMAT_P5N);
luts_status = __raw_readl(EPDC_STATUS_LUTS);
if ((rev < 20) || format_p5n)
luts_status &= 0xFFFF;
else
luts_status |= ((u64)__raw_readl(EPDC_STATUS_LUTS2) << 32);
if (rev < 20) {
unprocessed_luts = __raw_readl(EPDC_IRQ) & 0xFFFF;
} else {
unprocessed_luts = __raw_readl(EPDC_IRQ1) |
((u64)__raw_readl(EPDC_IRQ2) << 32);
if (format_p5n)
unprocessed_luts &= 0xFFFF;
}
/*
* Note on unprocessed_luts: There is a race condition
* where a LUT completes, but has not been processed by
* IRQ handler workqueue, and then a new update request
* attempts to use that LUT. We prevent that here by
* ensuring that the LUT we choose doesn't have its IRQ
* bit set (indicating it has completed but not yet been
* processed).
*/
used_luts = luts_status | unprocessed_luts;
/*
* Selecting a LUT to minimize incidence of TCE Underrun Error
* --------------------------------------------------------
* We want to find the lowest order LUT that is of greater
* order than all other active LUTs. If highest order LUT
* is active, then we want to choose the lowest order
* available LUT.
*
* NOTE: For EPDC version 2.0 and later, TCE Underrun error
* bug is fixed, so it doesn't matter which LUT is used.
*/
if ((rev < 20) || format_p5n) {
*next_lut = fls64(used_luts);
if (*next_lut > 15)
*next_lut = ffz(used_luts);
} else {
if ((u32)used_luts != ~0UL)
*next_lut = ffz((u32)used_luts);
else if ((u32)(used_luts >> 32) != ~0UL)
*next_lut = ffz((u32)(used_luts >> 32)) + 32;
else
*next_lut = INVALID_LUT;
}
if (used_luts & 0x8000)
return 1;
else
return 0;
}
static inline bool epdc_is_working_buffer_busy(void)
{
u32 val = __raw_readl(EPDC_STATUS);
bool is_busy = (val & EPDC_STATUS_WB_BUSY) ? true : false;
return is_busy;
}
static inline bool epdc_is_working_buffer_complete(void)
{
u32 val = __raw_readl(EPDC_IRQ);
bool is_compl = (val & EPDC_IRQ_WB_CMPLT_IRQ) ? true : false;
return is_compl;
}
static inline bool epdc_is_lut_cancelled(void)
{
u32 val = __raw_readl(EPDC_STATUS);
bool is_void = (val & EPDC_STATUS_UPD_VOID) ? true : false;