OpenTitan: Open source silicon root of trust

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

VeeR EH1 core

Project F brings FPGAs to life with exciting open-source designs you can build on.

Common SystemVerilog components

VeeR EL2 Core

Tile based architecture designed for computing efficiency, scalability and generality

RISC-V Debug Support for our PULP RISC-V Cores

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

Proposed RISC-V Composable Custom Extensions Specification

Demo SoC for SiliconCompiler.

This repo is for ECE44x (Fall2015-Spring2016)

Advanced Debug Interface

This repository contains a symbolic and secure configuration template for the RISC-V Physical Memory Protection (PMP) to be used in SV/SVA based verification flows.