- Edinburgh, United Kingdom.
- https://www.linkedin.com/in/tej-sanghavi/
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GitHub Actions that can be used as status checks for RTL development
UpdatedSep 19, 2024 -
Basic-JTAG-Implementation Public
The intent of this repository is to get a better understanding of JTAG
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logicLocking Public
The aim of this project is to try out the logic locking Yosys plugin.
SystemVerilog UpdatedFeb 22, 2024 -
DE1-SoC-Projects Public
This repository contains simple projects that have been implemented to gain a better understanding of the architecture of the DE1-SoC board.
Verilog UpdatedFeb 21, 2024 -
Advance-FPGA-Design Public
Examples discussed in the book: "Advanced FPGA design: Architecture, Implementation, and Optimization" by Steve Kilts, in System Verilog.
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2D-Systolic-Array-Multiplier Public
2D Systolic Array Multiplier
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This repository contains a list of semiconductor firms operating in the UK.
UpdatedDec 6, 2023 -
This repository contains my masters thesis and a presentation on it.
UpdatedNov 18, 2023 -
SV-Coding-Practices Public
Forked from DaveMcEwan/dmpvlFrom Dave McEwan's Personal Verilog Library
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gnu-eprog_exercises Public
This repository implements the tutorials found on: https://www.bravegnu.org/gnu-eprog/
Assembly UpdatedOct 10, 2023 -
Full Custom Design of a Touchscreen Front-End in 0.18µm CMOS
UpdatedAug 11, 2023 -
SPI Public
A SPI controller and peripheral is implemented in System Verilog.
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Cummings_FIFO Public
Simulation and Synthesis Techniques for Asynchronous FIFO Design
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svlint-rules Public
Forked from dalance/svlintSystemVerilog linter by dalance
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uvm_primer Public
Forked from raysalemi/uvmprimerContains the code examples from The UVM Primer Book sorted by chapters.
SystemVerilog UpdatedDec 24, 2021