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Hardcaml is an OCaml library for designing hardware.

OCaml 650 39 Updated Sep 26, 2024

IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.

Python 302 49 Updated Sep 18, 2024

A list of tutorials, paper, talks, and open-source projects for emerging compiler and architecture

381 31 Updated Sep 24, 2024

ChampSim is an open-source trace based simulator maintained at Texas A&M University and through the support of the computer architecture community.

C++ 500 415 Updated Sep 20, 2024

List of awesome semiconductor startups

Python 440 70 Updated Sep 9, 2024

Verilog package manager written in Rust

Rust 116 10 Updated Sep 27, 2024

Veryl: A Modern Hardware Description Language

Rust 478 22 Updated Sep 29, 2024

This repo provide an index of VLSI content creators and their materials

131 16 Updated Aug 21, 2024

Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit

Verilog 104 5 Updated Apr 19, 2024

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

SystemVerilog 782 89 Updated Jun 21, 2024

JTAG Test Access Port (TAP)

Verilog 30 12 Updated Jul 17, 2014

A tool for synthesizing Verilog programs

Verilog 30 4 Updated Sep 26, 2024

Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.

494 55 Updated Jul 4, 2024
Verilog 10 Updated May 31, 2024

EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)

Jupyter Notebook 125 24 Updated Sep 25, 2024
Jupyter Notebook 23 12 Updated Aug 11, 2024

Code generation tool for control and status registers

Ruby 318 43 Updated Jul 20, 2024

A minimal GPU design in Verilog to learn how GPUs work from the ground up

SystemVerilog 6,959 521 Updated Aug 18, 2024
Tcl 3 Updated Sep 8, 2023

SystemVerilog language server client for Visual Studio Code

TypeScript 20 3 Updated Dec 30, 2022

SystemVerilog language server

Rust 451 32 Updated Sep 16, 2024

SystemVerilog linter

Rust 304 33 Updated Sep 13, 2024

lowRISC Style Guides

359 122 Updated Sep 13, 2024

List of awesome open source hardware tools, generators, and reusable designs

Python 1,865 168 Updated Aug 31, 2024

Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference for understanding and implementing robust clock domain crossi…

Verilog 45 3 Updated Apr 14, 2024

draws an SVG schematic from a JSON netlist

JavaScript 627 80 Updated Jan 25, 2024

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

VHDL 542 45 Updated Sep 29, 2024

Raptor end-to-end FPGA Compiler and GUI

Verilog 61 22 Updated Sep 28, 2024

A collection of learning resources for curious software engineers

Python 46,462 3,710 Updated Sep 16, 2024
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