FIFO buffer library. Written and verified in SystemVerilog. Can be synthetised in ASIC or FPGA.
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Updated
Jun 17, 2022 - SystemVerilog
FIFO buffer library. Written and verified in SystemVerilog. Can be synthetised in ASIC or FPGA.
This repository contains my BSc graduation project at the Faculty of Engineering, Ain Shams University. The project focuses on implementing the RISC-V core, specifically the CV32E40 ,with a focus on achieving high performance and maximizing frequency through synthesis, place and route (PNR).
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