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A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical path, as described by MICRO 2022 paper by Bera et al. (https://arxiv.org/pdf/2209.00188.pdf)
Implemented modern last-level cache(LLC) with the concept of "Perceptron Learning for Reuse Prediction" that use neural network idea, which is training the predictor by a smaller independent cache with a series of features.
Something I worked on when I started learning about machine learning. This program trains itself to guess which of the two given numbers is the greatest using a given predefined data set.