Uma ferramenta para automação da publicação de dados conectados utilizando o LodFlow.

Virtuoso triplestore installation for DDEV

Virtuoso Docker image

In this project, we aim to design and optimize a fully differential sigma-delta ADC that achieves exceptional performance in terms of noise shaping, signal-to-noise ratio (SNR), and bandwidth.

Let's take advantage of GCP and get SPARQL endpoints with ease !

8bit x 8bit Signed Wallace Tree Multiplier 600nm CMOS VLSI Design

Design VLSI system with Cadance Tools

Тестовое задание INFINITE SYNERGY — это одностраничное веб-приложение, позволяющее отображать и редактировать 🗂️ большой массив данных без зависаний.

Scripts to load and delete data from a Virtuoso docker container

This file includes a plug and play macrospin model which can be used in any verilog ams simulator (Ex. Cadence Virtuoso) . The model includes magnetization dynamics of a ferromagnet under the effect of an effective field , spin transfer torque and spin orbit torque . The model also includes the field like torque and damping like torque component…

Homework about semantic web

Repo to control issues related to our infrastructure

This frequency divider is able to divide the clock signal depending on 3-bit input signal. Also, we were required to draw block diagrams to represent the structure, use “laker” to layout, use another software to simulate the different after doing layout, and analyze delay and power consumption.

VLSI DESIGN: AOI32 gate, layout on virtuoso, simulation waveform and comparison of pre and post layout results.

OpenLink DBpedia VAD

Sample visualisation of virtuoso sparql-json response from simplebrainz REST service using d3.js forcegraph

Programming in the Life Sciences: Work in Progress

Study Of Static CMOS Inverter

Project used to deploy Virtuoso database drivers to a public maven repository