memory

Memory - Verilog Library

Memory Verilog designs from Project F, including ROM, block ram, and SPRAM. You can freely build on these MIT licensed designs. See the Library for other helpful Verilog modules or discover the background to the Library.

Learn more at projectf.io, follow @WillFlux for updates, and join the FPGA discussion on 1BitSquared Discord.

Verilog Modules

• rom_async.sv - asynchronous ROM in logic (no clock)
• rom_sync.sv - synchronous ROM in logic (uses clock)
• ice40/bram_sdp.sv - iCE40 simple dual-port block RAM (one read port, one write port)
• ice40/spram.sv - iCE40 single port RAM (16-bit data width)
• ice40/spram_nibble.sv - iCE40 single port RAM (4-bit data width)
• xc7/bram_sdp.sv - XC7 simple dual-port block RAM (one read port, one write port)

Locate Vivado test benches in the xc7 directory.
Find other modules in the Library.

Blog Posts

The following blog posts document and make use of these memory modules:

• Practical ROM usage: Hardware Spites
• Practical BRAM and SPRAM usage: Lines & Triangles
• SPRAM on iCE40 FPGA - learn how to use SPRAM with Yosys and contrast it with Block RAM
• Initialize Memory in Verilog - use $readmemh and $readmemb to initialize the contents of ROM or RAM

Memory Modules Interface

These memory modules share similar parameters:

• WIDTH - data width in bits (may be renamed DATAW in future)
• DEPTH - memory depth (number of elements)
• INIT_F - data file to load into memory at initialization
• ADDRW - address width; by default this is calculated with $clog2(DEPTH)

SystemVerilog?

These modules use a little SystemVerilog to make Verilog more pleasant, see the main Library README for details.