Skip to content

Project F brings FPGAs to life with exciting open-source designs you can build on.

License

Notifications You must be signed in to change notification settings

tristanitschner/projf-explore

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Repository files navigation

Exploring FPGAs from Project F

Project F brings FPGAs to life with exciting open-source designs you can build on. Learn more at projectf.io and follow @WillFlux for updates.

Graphics

In this series, we explore graphics at the hardware level and get a feel for the power of FPGAs. If you're new to the series, start by reading the Exploring FPGA Graphics blog post.

Hello

A three-part introduction to FPGA development with Verilog; currently available for two boards: the Arty A7 and Nexys Video.

The third part will be available in spring 2021.

Maths

Maths & Algorithms is our next topic. Stay tuned for this series in 2021.

Library

Verilog library used across Project F. See Library for details.

Requirements

FPGA

Our designs seek to be vendor-neutral, but some functionality requires support for vendor primitives. We currently support two FPGA architectures:

  • XC7 - Xilinx Series 7 FPGAs, such as Spartan-7 and Arty-7
  • iCE40 - Lattice iCE40 FPGAs, such as iCE40 UltraPLus

Porting to other architectures should be straightforward.

SystemVerilog

We use a few choice features from SystemVerilog to make Verilog a little more pleasant. If you’re familiar with Verilog, you’ll have no trouble. All the designs are tested with Yosys and Vivado.

About

Project F brings FPGAs to life with exciting open-source designs you can build on.

Resources

License

Stars

Watchers

Forks

Releases

No releases published

Packages

No packages published

Languages

  • SystemVerilog 81.8%
  • C++ 8.4%
  • Tcl 5.0%
  • Makefile 2.3%
  • Shell 2.1%
  • Verilog 0.4%